1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2008  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  Using the EtherCAT technology and brand is permitted in compliance with

    23  *  the industrial property and similar rights of Beckhoff Automation GmbH.

    24  *

    25  *****************************************************************************/

    26 

    27 /**

    28    \file

    29    EtherCAT driver for RTL8139-compatible NICs.

    30 */

    31 

    32 /*****************************************************************************/

    33 

    34 /*

    35   Former documentation:

    36 

    37 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    38 

    39 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    40 	Copyright 2000-2002 Jeff Garzik

    41 

    42 	Much code comes from Donald Becker's rtl8139.c driver,

    43 	versions 1.13 and older.  This driver was originally based

    44 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    45 

    46 	-----<snip>-----

    47 

    48         	Written 1997-2001 by Donald Becker.

    49 		This software may be used and distributed according to the

    50 		terms of the GNU General Public License (GPL), incorporated

    51 		herein by reference.  Drivers based on or derived from this

    52 		code fall under the GPL and must retain the authorship,

    53 		copyright and license notice.  This file is not a complete

    54 		program and may only be used when the entire operating

    55 		system is licensed under the GPL.

    56 

    57 		This driver is for boards based on the RTL8129 and RTL8139

    58 		PCI ethernet chips.

    59 

    60 		The author may be reached as becker@scyld.com, or C/O Scyld

    61 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    62 		MD 21403

    63 

    64 		Support and updates available at

    65 		http://www.scyld.com/network/rtl8139.html

    66 

    67 		Twister-tuning table provided by Kinston

    68 		<shangh@realtek.com.tw>.

    69 

    70 	-----<snip>-----

    71 

    72 	This software may be used and distributed according to the terms

    73 	of the GNU General Public License, incorporated herein by reference.

    74 

    75 	Contributors:

    76 

    77 		Donald Becker - he wrote the original driver, kudos to him!

    78 		(but please don't e-mail him for support, this isn't his driver)

    79 

    80 		Tigran Aivazian - bug fixes, skbuff free cleanup

    81 

    82 		Martin Mares - suggestions for PCI cleanup

    83 

    84 		David S. Miller - PCI DMA and softnet updates

    85 

    86 		Ernst Gill - fixes ported from BSD driver

    87 

    88 		Daniel Kobras - identified specific locations of

    89 			posted MMIO write bugginess

    90 

    91 		Gerard Sharp - bug fix, testing and feedback

    92 

    93 		David Ford - Rx ring wrap fix

    94 

    95 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    96 		to find and fix a crucial bug on older chipsets.

    97 

    98 		Donald Becker/Chris Butterworth/Marcus Westergren -

    99 		Noticed various Rx packet size-related buglets.

   100 

   101 		Santiago Garcia Mantinan - testing and feedback

   102 

   103 		Jens David - 2.2.x kernel backports

   104 

   105 		Martin Dennett - incredibly helpful insight on undocumented

   106 		features of the 8139 chips

   107 

   108 		Jean-Jacques Michel - bug fix

   109 

   110 		Tobias Ringström - Rx interrupt status checking suggestion

   111 

   112 		Andrew Morton - Clear blocked signals, avoid

   113 		buffer overrun setting current->comm.

   114 

   115 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   116 

   117 		Robert Kuebel - Save kernel thread from dying on any signal.

   118 

   119 	Submitting bug reports:

   120 

   121 		"rtl8139-diag -mmmaaavvveefN" output

   122 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   123 

   124 */

   125 

   126 #define DRV_NAME	"ec_8139too"

   127 #define DRV_VERSION	"0.9.28"

   128 

   129 

   130 #include <linux/module.h>

   131 #include <linux/kernel.h>

   132 #include <linux/compiler.h>

   133 #include <linux/pci.h>

   134 #include <linux/init.h>

   135 #include <linux/ioport.h>

   136 #include <linux/netdevice.h>

   137 #include <linux/etherdevice.h>

   138 #include <linux/rtnetlink.h>

   139 #include <linux/delay.h>

   140 #include <linux/ethtool.h>

   141 #include <linux/mii.h>

   142 #include <linux/completion.h>

   143 #include <linux/crc32.h>

   144 #include <asm/io.h>

   145 #include <asm/uaccess.h>

   146 #include <asm/irq.h>

   147 

   148 #include "../globals.h"

   149 #include "ecdev.h"

   150 

   151 #define RTL8139_DRIVER_NAME DRV_NAME \

   152                             " EtherCAT-capable Fast Ethernet driver " \

   153                             DRV_VERSION ", master " EC_MASTER_VERSION

   154 

   155 #define PFX DRV_NAME ": "

   156 

   157 /* Default Message level */

   158 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   159                                  NETIF_MSG_PROBE  | \

   160                                  NETIF_MSG_LINK)

   161 

   162 

   163 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   164 #ifdef CONFIG_8139TOO_PIO

   165 #define USE_IO_OPS 1

   166 #endif

   167 

   168 /* define to 1, 2 or 3 to enable copious debugging info */

   169 #define RTL8139_DEBUG 0

   170 

   171 /* define to 1 to disable lightweight runtime debugging checks */

   172 #undef RTL8139_NDEBUG

   173 

   174 

   175 #if RTL8139_DEBUG

   176 /* note: prints function name for you */

   177 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   178 #else

   179 #  define DPRINTK(fmt, args...)

   180 #endif

   181 

   182 #ifdef RTL8139_NDEBUG

   183 #  define assert(expr) do {} while (0)

   184 #else

   185 #  define assert(expr) \

   186         if(unlikely(!(expr))) {				        \

   187         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   188         #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   189         }

   190 #endif

   191 

   192 

   193 /* A few user-configurable values. */

   194 /* media options */

   195 #define MAX_UNITS 8

   196 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   197 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   198 

   199 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   200    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   201 static int multicast_filter_limit = 32;

   202 

   203 /* bitmapped message enable number */

   204 static int debug = -1;

   205 

   206 /*

   207  * Receive ring size

   208  * Warning: 64K ring has hardware issues and may lock up.

   209  */

   210 #if defined(CONFIG_SH_DREAMCAST)

   211 #define RX_BUF_IDX 0	/* 8K ring */

   212 #else

   213 #define RX_BUF_IDX	2	/* 32K ring */

   214 #endif

   215 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   216 #define RX_BUF_PAD	16

   217 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   218 

   219 #if RX_BUF_LEN == 65536

   220 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   221 #else

   222 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   223 #endif

   224 

   225 /* Number of Tx descriptor registers. */

   226 #define NUM_TX_DESC	4

   227 

   228 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   229 #define MAX_ETH_FRAME_SIZE	1536

   230 

   231 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   232 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   233 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   234 

   235 /* PCI Tuning Parameters

   236    Threshold is bytes transferred to chip before transmission starts. */

   237 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   238 

   239 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   240 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   241 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   242 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   243 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   244 

   245 /* Operational parameters that usually are not changed. */

   246 /* Time in jiffies before concluding the transmitter is hung. */

   247 #define TX_TIMEOUT  (6*HZ)

   248 

   249 

   250 enum {

   251 	HAS_MII_XCVR = 0x010000,

   252 	HAS_CHIP_XCVR = 0x020000,

   253 	HAS_LNK_CHNG = 0x040000,

   254 };

   255 

   256 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   257 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   258 #define RTL_MIN_IO_SIZE 0x80

   259 #define RTL8139B_IO_SIZE 256

   260 

   261 #define RTL8129_CAPS	HAS_MII_XCVR

   262 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   263 

   264 typedef enum {

   265 	RTL8139 = 0,

   266 	RTL8129,

   267 } board_t;

   268 

   269 

   270 /* indexed by board_t, above */

   271 static const struct {

   272 	const char *name;

   273 	u32 hw_flags;

   274 } board_info[] __devinitdata = {

   275 	{ "RealTek RTL8139", RTL8139_CAPS },

   276 	{ "RealTek RTL8129", RTL8129_CAPS },

   277 };

   278 

   279 

   280 static struct pci_device_id rtl8139_pci_tbl[] = {

   281 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   282 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 

   301 #ifdef CONFIG_SH_SECUREEDGE5410

   302 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   303 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 #endif

   305 #ifdef CONFIG_8139TOO_8129

   306 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   307 #endif

   308 

   309 	/* some crazy cards report invalid vendor ids like

   310 	 * 0x0001 here.  The other ids are valid and constant,

   311 	 * so we simply don't match on the main vendor id.

   312 	 */

   313 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   314 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   315 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   316 

   317 	{0,}

   318 };

   319 

   320 /* prevent driver from being loaded automatically */

   321 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   322 

   323 static struct {

   324 	const char str[ETH_GSTRING_LEN];

   325 } ethtool_stats_keys[] = {

   326 	{ "early_rx" },

   327 	{ "tx_buf_mapped" },

   328 	{ "tx_timeouts" },

   329 	{ "rx_lost_in_ring" },

   330 };

   331 

   332 /* The rest of these values should never change. */

   333 

   334 /* Symbolic offsets to registers. */

   335 enum RTL8139_registers {

   336 	MAC0		= 0,	 /* Ethernet hardware address. */

   337 	MAR0		= 8,	 /* Multicast filter. */

   338 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   339 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   340 	RxBuf		= 0x30,

   341 	ChipCmd		= 0x37,

   342 	RxBufPtr	= 0x38,

   343 	RxBufAddr	= 0x3A,

   344 	IntrMask	= 0x3C,

   345 	IntrStatus	= 0x3E,

   346 	TxConfig	= 0x40,

   347 	RxConfig	= 0x44,

   348 	Timer		= 0x48,	 /* A general-purpose counter. */

   349 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   350 	Cfg9346		= 0x50,

   351 	Config0		= 0x51,

   352 	Config1		= 0x52,

   353 	FlashReg	= 0x54,

   354 	MediaStatus	= 0x58,

   355 	Config3		= 0x59,

   356 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   357 	HltClk		= 0x5B,

   358 	MultiIntr	= 0x5C,

   359 	TxSummary	= 0x60,

   360 	BasicModeCtrl	= 0x62,

   361 	BasicModeStatus	= 0x64,

   362 	NWayAdvert	= 0x66,

   363 	NWayLPAR	= 0x68,

   364 	NWayExpansion	= 0x6A,

   365 	/* Undocumented registers, but required for proper operation. */

   366 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   367 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   368 	PARA78		= 0x78,

   369 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   370 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   371 };

   372 

   373 enum ClearBitMasks {

   374 	MultiIntrClear	= 0xF000,

   375 	ChipCmdClear	= 0xE2,

   376 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   377 };

   378 

   379 enum ChipCmdBits {

   380 	CmdReset	= 0x10,

   381 	CmdRxEnb	= 0x08,

   382 	CmdTxEnb	= 0x04,

   383 	RxBufEmpty	= 0x01,

   384 };

   385 

   386 /* Interrupt register bits, using my own meaningful names. */

   387 enum IntrStatusBits {

   388 	PCIErr		= 0x8000,

   389 	PCSTimeout	= 0x4000,

   390 	RxFIFOOver	= 0x40,

   391 	RxUnderrun	= 0x20,

   392 	RxOverflow	= 0x10,

   393 	TxErr		= 0x08,

   394 	TxOK		= 0x04,

   395 	RxErr		= 0x02,

   396 	RxOK		= 0x01,

   397 

   398 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   399 };

   400 

   401 enum TxStatusBits {

   402 	TxHostOwns	= 0x2000,

   403 	TxUnderrun	= 0x4000,

   404 	TxStatOK	= 0x8000,

   405 	TxOutOfWindow	= 0x20000000,

   406 	TxAborted	= 0x40000000,

   407 	TxCarrierLost	= 0x80000000,

   408 };

   409 enum RxStatusBits {

   410 	RxMulticast	= 0x8000,

   411 	RxPhysical	= 0x4000,

   412 	RxBroadcast	= 0x2000,

   413 	RxBadSymbol	= 0x0020,

   414 	RxRunt		= 0x0010,

   415 	RxTooLong	= 0x0008,

   416 	RxCRCErr	= 0x0004,

   417 	RxBadAlign	= 0x0002,

   418 	RxStatusOK	= 0x0001,

   419 };

   420 

   421 /* Bits in RxConfig. */

   422 enum rx_mode_bits {

   423 	AcceptErr	= 0x20,

   424 	AcceptRunt	= 0x10,

   425 	AcceptBroadcast	= 0x08,

   426 	AcceptMulticast	= 0x04,

   427 	AcceptMyPhys	= 0x02,

   428 	AcceptAllPhys	= 0x01,

   429 };

   430 

   431 /* Bits in TxConfig. */

   432 enum tx_config_bits {

   433         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   434         TxIFGShift	= 24,

   435         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   436         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   437         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   438         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   439 

   440 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   441 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   442 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   443 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   444 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   445 

   446 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   447 };

   448 

   449 /* Bits in Config1 */

   450 enum Config1Bits {

   451 	Cfg1_PM_Enable	= 0x01,

   452 	Cfg1_VPD_Enable	= 0x02,

   453 	Cfg1_PIO	= 0x04,

   454 	Cfg1_MMIO	= 0x08,

   455 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   456 	Cfg1_Driver_Load = 0x20,

   457 	Cfg1_LED0	= 0x40,

   458 	Cfg1_LED1	= 0x80,

   459 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   460 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   461 };

   462 

   463 /* Bits in Config3 */

   464 enum Config3Bits {

   465 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   466 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   467 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   468 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   469 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   470 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   471 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   472 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   473 };

   474 

   475 /* Bits in Config4 */

   476 enum Config4Bits {

   477 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   478 };

   479 

   480 /* Bits in Config5 */

   481 enum Config5Bits {

   482 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   483 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   484 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   485 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   486 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   487 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   488 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   489 };

   490 

   491 enum RxConfigBits {

   492 	/* rx fifo threshold */

   493 	RxCfgFIFOShift	= 13,

   494 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   495 

   496 	/* Max DMA burst */

   497 	RxCfgDMAShift	= 8,

   498 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   499 

   500 	/* rx ring buffer length */

   501 	RxCfgRcv8K	= 0,

   502 	RxCfgRcv16K	= (1 << 11),

   503 	RxCfgRcv32K	= (1 << 12),

   504 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   505 

   506 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   507 	RxNoWrap	= (1 << 7),

   508 };

   509 

   510 /* Twister tuning parameters from RealTek.

   511    Completely undocumented, but required to tune bad links on some boards. */

   512 enum CSCRBits {

   513 	CSCR_LinkOKBit		= 0x0400,

   514 	CSCR_LinkChangeBit	= 0x0800,

   515 	CSCR_LinkStatusBits	= 0x0f000,

   516 	CSCR_LinkDownOffCmd	= 0x003c0,

   517 	CSCR_LinkDownCmd	= 0x0f3c0,

   518 };

   519 

   520 enum Cfg9346Bits {

   521 	Cfg9346_Lock	= 0x00,

   522 	Cfg9346_Unlock	= 0xC0,

   523 };

   524 

   525 typedef enum {

   526 	CH_8139	= 0,

   527 	CH_8139_K,

   528 	CH_8139A,

   529 	CH_8139A_G,

   530 	CH_8139B,

   531 	CH_8130,

   532 	CH_8139C,

   533 	CH_8100,

   534 	CH_8100B_8139D,

   535 	CH_8101,

   536 } chip_t;

   537 

   538 enum chip_flags {

   539 	HasHltClk	= (1 << 0),

   540 	HasLWake	= (1 << 1),

   541 };

   542 

   543 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   544 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   545 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   546 

   547 /* directly indexed by chip_t, above */

   548 static const struct {

   549 	const char *name;

   550 	u32 version; /* from RTL8139C/RTL8139D docs */

   551 	u32 flags;

   552 } rtl_chip_info[] = {

   553 	{ "RTL-8139",

   554 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   555 	  HasHltClk,

   556 	},

   557 

   558 	{ "RTL-8139 rev K",

   559 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   560 	  HasHltClk,

   561 	},

   562 

   563 	{ "RTL-8139A",

   564 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   565 	  HasHltClk, /* XXX undocumented? */

   566 	},

   567 

   568 	{ "RTL-8139A rev G",

   569 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   570 	  HasHltClk, /* XXX undocumented? */

   571 	},

   572 

   573 	{ "RTL-8139B",

   574 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   575 	  HasLWake,

   576 	},

   577 

   578 	{ "RTL-8130",

   579 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   580 	  HasLWake,

   581 	},

   582 

   583 	{ "RTL-8139C",

   584 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   585 	  HasLWake,

   586 	},

   587 

   588 	{ "RTL-8100",

   589 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   590  	  HasLWake,

   591  	},

   592 

   593 	{ "RTL-8100B/8139D",

   594 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   595 	  HasHltClk /* XXX undocumented? */

   596 	| HasLWake,

   597 	},

   598 

   599 	{ "RTL-8101",

   600 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   601 	  HasLWake,

   602 	},

   603 };

   604 

   605 struct rtl_extra_stats {

   606 	unsigned long early_rx;

   607 	unsigned long tx_buf_mapped;

   608 	unsigned long tx_timeouts;

   609 	unsigned long rx_lost_in_ring;

   610 };

   611 

   612 struct rtl8139_private {

   613 	void __iomem		*mmio_addr;

   614 	int			drv_flags;

   615 	struct pci_dev		*pci_dev;

   616 	u32			msg_enable;

   617 	struct napi_struct	napi;

   618 	struct net_device	*dev;

   619 	struct net_device_stats	stats;

   620 

   621 	unsigned char		*rx_ring;

   622 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   623 	dma_addr_t		rx_ring_dma;

   624 

   625 	unsigned int		tx_flag;

   626 	unsigned long		cur_tx;

   627 	unsigned long		dirty_tx;

   628 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   629 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   630 	dma_addr_t		tx_bufs_dma;

   631 

   632 	signed char		phys[4];	/* MII device addresses. */

   633 

   634 				/* Twister tune state. */

   635 	char			twistie, twist_row, twist_col;

   636 

   637 	unsigned int		watchdog_fired : 1;

   638 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   639 	unsigned int		have_thread : 1;

   640 

   641 	spinlock_t		lock;

   642 	spinlock_t		rx_lock;

   643 

   644 	chip_t			chipset;

   645 	u32			rx_config;

   646 	struct rtl_extra_stats	xstats;

   647 

   648 	struct delayed_work	thread;

   649 

   650 	struct mii_if_info	mii;

   651 	unsigned int		regs_len;

   652 	unsigned long		fifo_copy_timeout;

   653     

   654 	ec_device_t *ecdev;

   655 };

   656 

   657 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   658 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   659 MODULE_LICENSE("GPL");

   660 MODULE_VERSION(EC_MASTER_VERSION);

   661 

   662 module_param(multicast_filter_limit, int, 0);

   663 module_param_array(media, int, NULL, 0);

   664 module_param_array(full_duplex, int, NULL, 0);

   665 module_param(debug, int, 0);

   666 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   667 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   668 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   669 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   670 

   671 void ec_poll(struct net_device *);

   672 

   673 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   674 static int rtl8139_open (struct net_device *dev);

   675 static int mdio_read (struct net_device *dev, int phy_id, int location);

   676 static void mdio_write (struct net_device *dev, int phy_id, int location,

   677 			int val);

   678 static void rtl8139_start_thread(struct rtl8139_private *tp);

   679 static void rtl8139_tx_timeout (struct net_device *dev);

   680 static void rtl8139_init_ring (struct net_device *dev);

   681 static int rtl8139_start_xmit (struct sk_buff *skb,

   682 			       struct net_device *dev);

   683 #ifdef CONFIG_NET_POLL_CONTROLLER

   684 static void rtl8139_poll_controller(struct net_device *dev);

   685 #endif

   686 static int rtl8139_poll(struct napi_struct *napi, int budget);

   687 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   688 static int rtl8139_close (struct net_device *dev);

   689 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   690 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   691 static void rtl8139_set_rx_mode (struct net_device *dev);

   692 static void __set_rx_mode (struct net_device *dev);

   693 static void rtl8139_hw_start (struct net_device *dev);

   694 static void rtl8139_thread (struct work_struct *work);

   695 static void rtl8139_tx_timeout_task(struct work_struct *work);

   696 static const struct ethtool_ops rtl8139_ethtool_ops;

   697 

   698 /* write MMIO register, with flush */

   699 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   700 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   701 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   702 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   703 

   704 /* write MMIO register */

   705 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   706 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   707 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   708 

   709 /* read MMIO register */

   710 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   711 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   712 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   713 

   714 

   715 static const u16 rtl8139_intr_mask =

   716 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   717 	TxErr | TxOK | RxErr | RxOK;

   718 

   719 static const u16 rtl8139_norx_intr_mask =

   720 	PCIErr | PCSTimeout | RxUnderrun |

   721 	TxErr | TxOK | RxErr ;

   722 

   723 #if RX_BUF_IDX == 0

   724 static const unsigned int rtl8139_rx_config =

   725 	RxCfgRcv8K | RxNoWrap |

   726 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   727 	(RX_DMA_BURST << RxCfgDMAShift);

   728 #elif RX_BUF_IDX == 1

   729 static const unsigned int rtl8139_rx_config =

   730 	RxCfgRcv16K | RxNoWrap |

   731 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   732 	(RX_DMA_BURST << RxCfgDMAShift);

   733 #elif RX_BUF_IDX == 2

   734 static const unsigned int rtl8139_rx_config =

   735 	RxCfgRcv32K | RxNoWrap |

   736 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   737 	(RX_DMA_BURST << RxCfgDMAShift);

   738 #elif RX_BUF_IDX == 3

   739 static const unsigned int rtl8139_rx_config =

   740 	RxCfgRcv64K |

   741 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   742 	(RX_DMA_BURST << RxCfgDMAShift);

   743 #else

   744 #error "Invalid configuration for 8139_RXBUF_IDX"

   745 #endif

   746 

   747 static const unsigned int rtl8139_tx_config =

   748 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   749 

   750 static void __rtl8139_cleanup_dev (struct net_device *dev)

   751 {

   752 	struct rtl8139_private *tp = netdev_priv(dev);

   753 	struct pci_dev *pdev;

   754 

   755 	assert (dev != NULL);

   756 	assert (tp->pci_dev != NULL);

   757 	pdev = tp->pci_dev;

   758 

   759 #ifdef USE_IO_OPS

   760 	if (tp->mmio_addr)

   761 		ioport_unmap (tp->mmio_addr);

   762 #else

   763 	if (tp->mmio_addr)

   764 		pci_iounmap (pdev, tp->mmio_addr);

   765 #endif /* USE_IO_OPS */

   766 

   767 	/* it's ok to call this even if we have no regions to free */

   768 	pci_release_regions (pdev);

   769 

   770 	free_netdev(dev);

   771 	pci_set_drvdata (pdev, NULL);

   772 }

   773 

   774 

   775 static void rtl8139_chip_reset (void __iomem *ioaddr)

   776 {

   777 	int i;

   778 

   779 	/* Soft reset the chip. */

   780 	RTL_W8 (ChipCmd, CmdReset);

   781 

   782 	/* Check that the chip has finished the reset. */

   783 	for (i = 1000; i > 0; i--) {

   784 		barrier();

   785 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   786 			break;

   787 		udelay (10);

   788 	}

   789 }

   790 

   791 

   792 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   793 					 struct net_device **dev_out)

   794 {

   795 	void __iomem *ioaddr;

   796 	struct net_device *dev;

   797 	struct rtl8139_private *tp;

   798 	u8 tmp8;

   799 	int rc, disable_dev_on_err = 0;

   800 	unsigned int i;

   801 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   802 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   803 	u32 version;

   804 

   805 	assert (pdev != NULL);

   806 

   807 	*dev_out = NULL;

   808 

   809 	/* dev and priv zeroed in alloc_etherdev */

   810 	dev = alloc_etherdev (sizeof (*tp));

   811 	if (dev == NULL) {

   812 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   813 		return -ENOMEM;

   814 	}

   815 	SET_NETDEV_DEV(dev, &pdev->dev);

   816 

   817 	tp = netdev_priv(dev);

   818 	tp->pci_dev = pdev;

   819 

   820 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   821 	rc = pci_enable_device (pdev);

   822 	if (rc)

   823 		goto err_out;

   824 

   825 	pio_start = pci_resource_start (pdev, 0);

   826 	pio_end = pci_resource_end (pdev, 0);

   827 	pio_flags = pci_resource_flags (pdev, 0);

   828 	pio_len = pci_resource_len (pdev, 0);

   829 

   830 	mmio_start = pci_resource_start (pdev, 1);

   831 	mmio_end = pci_resource_end (pdev, 1);

   832 	mmio_flags = pci_resource_flags (pdev, 1);

   833 	mmio_len = pci_resource_len (pdev, 1);

   834 

   835 	/* set this immediately, we need to know before

   836 	 * we talk to the chip directly */

   837 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   838 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   839 

   840 #ifdef USE_IO_OPS

   841 	/* make sure PCI base addr 0 is PIO */

   842 	if (!(pio_flags & IORESOURCE_IO)) {

   843 		dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   844 		rc = -ENODEV;

   845 		goto err_out;

   846 	}

   847 	/* check for weird/broken PCI region reporting */

   848 	if (pio_len < RTL_MIN_IO_SIZE) {

   849 		dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   850 		rc = -ENODEV;

   851 		goto err_out;

   852 	}

   853 #else

   854 	/* make sure PCI base addr 1 is MMIO */

   855 	if (!(mmio_flags & IORESOURCE_MEM)) {

   856 		dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   857 		rc = -ENODEV;

   858 		goto err_out;

   859 	}

   860 	if (mmio_len < RTL_MIN_IO_SIZE) {

   861 		dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   862 		rc = -ENODEV;

   863 		goto err_out;

   864 	}

   865 #endif

   866 

   867 	rc = pci_request_regions (pdev, DRV_NAME);

   868 	if (rc)

   869 		goto err_out;

   870 	disable_dev_on_err = 1;

   871 

   872 	/* enable PCI bus-mastering */

   873 	pci_set_master (pdev);

   874 

   875 #ifdef USE_IO_OPS

   876 	ioaddr = ioport_map(pio_start, pio_len);

   877 	if (!ioaddr) {

   878 		dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   879 		rc = -EIO;

   880 		goto err_out;

   881 	}

   882 	dev->base_addr = pio_start;

   883 	tp->mmio_addr = ioaddr;

   884 	tp->regs_len = pio_len;

   885 #else

   886 	/* ioremap MMIO region */

   887 	ioaddr = pci_iomap(pdev, 1, 0);

   888 	if (ioaddr == NULL) {

   889 		dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");

   890 		rc = -EIO;

   891 		goto err_out;

   892 	}

   893 	dev->base_addr = (long) ioaddr;

   894 	tp->mmio_addr = ioaddr;

   895 	tp->regs_len = mmio_len;

   896 #endif /* USE_IO_OPS */

   897 

   898 	/* Bring old chips out of low-power mode. */

   899 	RTL_W8 (HltClk, 'R');

   900 

   901 	/* check for missing/broken hardware */

   902 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   903 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   904 		rc = -EIO;

   905 		goto err_out;

   906 	}

   907 

   908 	/* identify chip attached to board */

   909 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   910 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   911 		if (version == rtl_chip_info[i].version) {

   912 			tp->chipset = i;

   913 			goto match;

   914 		}

   915 

   916 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   917 	dev_printk (KERN_DEBUG, &pdev->dev,

   918 		    "unknown chip version, assuming RTL-8139\n");

   919 	dev_printk (KERN_DEBUG, &pdev->dev,

   920 		    "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   921 	tp->chipset = 0;

   922 

   923 match:

   924 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   925 		 version, i, rtl_chip_info[i].name);

   926 

   927 	if (tp->chipset >= CH_8139B) {

   928 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   929 		DPRINTK("PCI PM wakeup\n");

   930 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   931 		    (tmp8 & LWAKE))

   932 			new_tmp8 &= ~LWAKE;

   933 		new_tmp8 |= Cfg1_PM_Enable;

   934 		if (new_tmp8 != tmp8) {

   935 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   936 			RTL_W8 (Config1, tmp8);

   937 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   938 		}

   939 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   940 			tmp8 = RTL_R8 (Config4);

   941 			if (tmp8 & LWPTN) {

   942 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   943 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   944 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   945 			}

   946 		}

   947 	} else {

   948 		DPRINTK("Old chip wakeup\n");

   949 		tmp8 = RTL_R8 (Config1);

   950 		tmp8 &= ~(SLEEP | PWRDN);

   951 		RTL_W8 (Config1, tmp8);

   952 	}

   953 

   954 	rtl8139_chip_reset (ioaddr);

   955 

   956 	*dev_out = dev;

   957 	return 0;

   958 

   959 err_out:

   960 	__rtl8139_cleanup_dev (dev);

   961 	if (disable_dev_on_err)

   962 		pci_disable_device (pdev);

   963 	return rc;

   964 }

   965 

   966 

   967 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   968 				       const struct pci_device_id *ent)

   969 {

   970 	struct net_device *dev = NULL;

   971 	struct rtl8139_private *tp;

   972 	int i, addr_len, option;

   973 	void __iomem *ioaddr;

   974 	static int board_idx = -1;

   975 	DECLARE_MAC_BUF(mac);

   976 

   977 	assert (pdev != NULL);

   978 	assert (ent != NULL);

   979 

   980 	board_idx++;

   981 

   982 	/* when we're built into the kernel, the driver version message

   983 	 * is only printed if at least one 8139 board has been found

   984 	 */

   985 #ifndef MODULE

   986 	{

   987 		static int printed_version;

   988 		if (!printed_version++)

   989 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

   990 	}

   991 #endif

   992 

   993 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

   994 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

   995 		dev_info(&pdev->dev,

   996 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

   997 		       	   pdev->vendor, pdev->device, pdev->revision);

   998 		dev_info(&pdev->dev,

   999 			   "Use the \"8139cp\" driver for improved performance and stability.\n");

  1000 	}

  1001 

  1002 	i = rtl8139_init_board (pdev, &dev);

  1003 	if (i < 0)

  1004 		return i;

  1005 

  1006 	assert (dev != NULL);

  1007 	tp = netdev_priv(dev);

  1008 	tp->dev = dev;

  1009 

  1010 	ioaddr = tp->mmio_addr;

  1011 	assert (ioaddr != NULL);

  1012 

  1013 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1014 	for (i = 0; i < 3; i++)

  1015 		((__le16 *) (dev->dev_addr))[i] =

  1016 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1017 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1018 

  1019 	/* The Rtl8139-specific entries in the device structure. */

  1020 	dev->open = rtl8139_open;

  1021 	dev->hard_start_xmit = rtl8139_start_xmit;

  1022 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1023 	dev->stop = rtl8139_close;

  1024 	dev->get_stats = rtl8139_get_stats;

  1025 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1026 	dev->do_ioctl = netdev_ioctl;

  1027 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1028 	dev->tx_timeout = rtl8139_tx_timeout;

  1029 	dev->watchdog_timeo = TX_TIMEOUT;

  1030 #ifdef CONFIG_NET_POLL_CONTROLLER

  1031 	dev->poll_controller = rtl8139_poll_controller;

  1032 #endif

  1033 

  1034 	/* note: the hardware is not capable of sg/csum/highdma, however

  1035 	 * through the use of skb_copy_and_csum_dev we enable these

  1036 	 * features

  1037 	 */

  1038 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1039 

  1040 	dev->irq = pdev->irq;

  1041 

  1042 	/* tp zeroed and aligned in alloc_etherdev */

  1043 	tp = netdev_priv(dev);

  1044 

  1045 	/* note: tp->chipset set in rtl8139_init_board */

  1046 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1047 	tp->mmio_addr = ioaddr;

  1048 	tp->msg_enable =

  1049 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1050 	spin_lock_init (&tp->lock);

  1051 	spin_lock_init (&tp->rx_lock);

  1052 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1053 	tp->mii.dev = dev;

  1054 	tp->mii.mdio_read = mdio_read;

  1055 	tp->mii.mdio_write = mdio_write;

  1056 	tp->mii.phy_id_mask = 0x3f;

  1057 	tp->mii.reg_num_mask = 0x1f;

  1058 

  1059 	/* dev is fully set up and ready to use now */

  1060     

  1061 	// offer device to EtherCAT master module

  1062 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1063 

  1064 	if (!tp->ecdev) {

  1065 		DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1066 		i = register_netdev (dev);

  1067 		if (i) goto err_out;

  1068 	}

  1069 

  1070 	pci_set_drvdata (pdev, dev);

  1071 

  1072 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1073 		"%s, IRQ %d\n",

  1074 		dev->name,

  1075 		board_info[ent->driver_data].name,

  1076 		dev->base_addr,

  1077 		print_mac(mac, dev->dev_addr),

  1078 		dev->irq);

  1079 

  1080 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1081 		dev->name, rtl_chip_info[tp->chipset].name);

  1082 

  1083 	/* Find the connected MII xcvrs.

  1084 	   Doing this in open() would allow detecting external xcvrs later, but

  1085 	   takes too much time. */

  1086 #ifdef CONFIG_8139TOO_8129

  1087 	if (tp->drv_flags & HAS_MII_XCVR) {

  1088 		int phy, phy_idx = 0;

  1089 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1090 			int mii_status = mdio_read(dev, phy, 1);

  1091 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1092 				u16 advertising = mdio_read(dev, phy, 4);

  1093 				tp->phys[phy_idx++] = phy;

  1094 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1095 					   "advertising %4.4x.\n",

  1096 					   dev->name, phy, mii_status, advertising);

  1097 			}

  1098 		}

  1099 		if (phy_idx == 0) {

  1100 			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1101 				   "transceiver.\n",

  1102 				   dev->name);

  1103 			tp->phys[0] = 32;

  1104 		}

  1105 	} else

  1106 #endif

  1107 		tp->phys[0] = 32;

  1108 	tp->mii.phy_id = tp->phys[0];

  1109 

  1110 	/* The lower four bits are the media type. */

  1111 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1112 	if (option > 0) {

  1113 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1114 		tp->default_port = option & 0xFF;

  1115 		if (tp->default_port)

  1116 			tp->mii.force_media = 1;

  1117 	}

  1118 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1119 		tp->mii.full_duplex = full_duplex[board_idx];

  1120 	if (tp->mii.full_duplex) {

  1121 		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);

  1122 		/* Changing the MII-advertised media because might prevent

  1123 		   re-connection. */

  1124 		tp->mii.force_media = 1;

  1125 	}

  1126 	if (tp->default_port) {

  1127 		printk(KERN_INFO "  Forcing %dMbps %s-duplex operation.\n",

  1128 			   (option & 0x20 ? 100 : 10),

  1129 			   (option & 0x10 ? "full" : "half"));

  1130 		mdio_write(dev, tp->phys[0], 0,

  1131 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */

  1132 				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */

  1133 	}

  1134 

  1135 	/* Put the chip into low-power mode. */

  1136 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)