|
1 /******************************************************************************* |
|
2 |
|
3 Intel PRO/1000 Linux driver |
|
4 Copyright(c) 1999 - 2006 Intel Corporation. |
|
5 |
|
6 This program is free software; you can redistribute it and/or modify it |
|
7 under the terms and conditions of the GNU General Public License, |
|
8 version 2, as published by the Free Software Foundation. |
|
9 |
|
10 This program is distributed in the hope it will be useful, but WITHOUT |
|
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
|
13 more details. |
|
14 |
|
15 You should have received a copy of the GNU General Public License along with |
|
16 this program; if not, write to the Free Software Foundation, Inc., |
|
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
|
18 |
|
19 The full GNU General Public License is included in this distribution in |
|
20 the file called "COPYING". |
|
21 |
|
22 Contact Information: |
|
23 Linux NICS <linux.nics@intel.com> |
|
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
|
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
|
26 |
|
27 *******************************************************************************/ |
|
28 |
|
29 /* e1000_hw.c |
|
30 * Shared functions for accessing and configuring the MAC |
|
31 */ |
|
32 |
|
33 |
|
34 #include "e1000_hw-2.6.24-ethercat.h" |
|
35 |
|
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); |
|
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); |
|
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); |
|
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); |
|
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); |
|
41 static void e1000_release_software_semaphore(struct e1000_hw *hw); |
|
42 |
|
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); |
|
44 static int32_t e1000_check_downshift(struct e1000_hw *hw); |
|
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); |
|
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
|
47 static void e1000_clear_vfta(struct e1000_hw *hw); |
|
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); |
|
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); |
|
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); |
|
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); |
|
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); |
|
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); |
|
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); |
|
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
|
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); |
|
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw); |
|
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); |
|
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); |
|
60 static int32_t e1000_id_led_init(struct e1000_hw *hw); |
|
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); |
|
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); |
|
63 static void e1000_init_rx_addrs(struct e1000_hw *hw); |
|
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw); |
|
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
|
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); |
|
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); |
|
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); |
|
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); |
|
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw); |
|
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
|
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
|
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
|
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
|
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); |
|
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
|
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
|
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); |
|
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); |
|
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); |
|
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); |
|
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); |
|
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); |
|
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
|
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
|
86 static void e1000_release_software_flag(struct e1000_hw *hw); |
|
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); |
|
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); |
|
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); |
|
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); |
|
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw); |
|
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); |
|
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
|
94 static void e1000_phy_init_script(struct e1000_hw *hw); |
|
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw); |
|
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
|
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
|
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
|
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); |
|
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
|
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
|
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, |
|
103 uint16_t count); |
|
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
|
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); |
|
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, |
|
107 uint16_t words, uint16_t *data); |
|
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, |
|
109 uint16_t offset, uint16_t words, |
|
110 uint16_t *data); |
|
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); |
|
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
|
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
|
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, |
|
115 uint16_t count); |
|
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
|
117 uint16_t phy_data); |
|
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, |
|
119 uint16_t *phy_data); |
|
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); |
|
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); |
|
122 static void e1000_release_eeprom(struct e1000_hw *hw); |
|
123 static void e1000_standby_eeprom(struct e1000_hw *hw); |
|
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
|
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
|
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
|
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
|
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); |
|
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, |
|
130 uint16_t duplex); |
|
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
|
132 |
|
133 /* IGP cable length table */ |
|
134 static const |
|
135 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
|
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
|
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
|
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
|
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
|
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
|
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
|
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
|
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
|
144 |
|
145 static const |
|
146 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
|
147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
|
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
|
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
|
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
|
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
|
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
|
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
|
154 104, 109, 114, 118, 121, 124}; |
|
155 |
|
156 /****************************************************************************** |
|
157 * Set the phy type member in the hw struct. |
|
158 * |
|
159 * hw - Struct containing variables accessed by shared code |
|
160 *****************************************************************************/ |
|
161 static int32_t |
|
162 e1000_set_phy_type(struct e1000_hw *hw) |
|
163 { |
|
164 DEBUGFUNC("e1000_set_phy_type"); |
|
165 |
|
166 if (hw->mac_type == e1000_undefined) |
|
167 return -E1000_ERR_PHY_TYPE; |
|
168 |
|
169 switch (hw->phy_id) { |
|
170 case M88E1000_E_PHY_ID: |
|
171 case M88E1000_I_PHY_ID: |
|
172 case M88E1011_I_PHY_ID: |
|
173 case M88E1111_I_PHY_ID: |
|
174 hw->phy_type = e1000_phy_m88; |
|
175 break; |
|
176 case IGP01E1000_I_PHY_ID: |
|
177 if (hw->mac_type == e1000_82541 || |
|
178 hw->mac_type == e1000_82541_rev_2 || |
|
179 hw->mac_type == e1000_82547 || |
|
180 hw->mac_type == e1000_82547_rev_2) { |
|
181 hw->phy_type = e1000_phy_igp; |
|
182 break; |
|
183 } |
|
184 case IGP03E1000_E_PHY_ID: |
|
185 hw->phy_type = e1000_phy_igp_3; |
|
186 break; |
|
187 case IFE_E_PHY_ID: |
|
188 case IFE_PLUS_E_PHY_ID: |
|
189 case IFE_C_E_PHY_ID: |
|
190 hw->phy_type = e1000_phy_ife; |
|
191 break; |
|
192 case GG82563_E_PHY_ID: |
|
193 if (hw->mac_type == e1000_80003es2lan) { |
|
194 hw->phy_type = e1000_phy_gg82563; |
|
195 break; |
|
196 } |
|
197 /* Fall Through */ |
|
198 default: |
|
199 /* Should never have loaded on this device */ |
|
200 hw->phy_type = e1000_phy_undefined; |
|
201 return -E1000_ERR_PHY_TYPE; |
|
202 } |
|
203 |
|
204 return E1000_SUCCESS; |
|
205 } |
|
206 |
|
207 /****************************************************************************** |
|
208 * IGP phy init script - initializes the GbE PHY |
|
209 * |
|
210 * hw - Struct containing variables accessed by shared code |
|
211 *****************************************************************************/ |
|
212 static void |
|
213 e1000_phy_init_script(struct e1000_hw *hw) |
|
214 { |
|
215 uint32_t ret_val; |
|
216 uint16_t phy_saved_data; |
|
217 |
|
218 DEBUGFUNC("e1000_phy_init_script"); |
|
219 |
|
220 if (hw->phy_init_script) { |
|
221 msleep(20); |
|
222 |
|
223 /* Save off the current value of register 0x2F5B to be restored at |
|
224 * the end of this routine. */ |
|
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
226 |
|
227 /* Disabled the PHY transmitter */ |
|
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
229 |
|
230 msleep(20); |
|
231 |
|
232 e1000_write_phy_reg(hw,0x0000,0x0140); |
|
233 |
|
234 msleep(5); |
|
235 |
|
236 switch (hw->mac_type) { |
|
237 case e1000_82541: |
|
238 case e1000_82547: |
|
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
|
240 |
|
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
|
242 |
|
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
|
244 |
|
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
|
246 |
|
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
|
248 |
|
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
|
250 |
|
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
|
252 |
|
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
|
254 |
|
255 e1000_write_phy_reg(hw, 0x2010, 0x0008); |
|
256 break; |
|
257 |
|
258 case e1000_82541_rev_2: |
|
259 case e1000_82547_rev_2: |
|
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
|
261 break; |
|
262 default: |
|
263 break; |
|
264 } |
|
265 |
|
266 e1000_write_phy_reg(hw, 0x0000, 0x3300); |
|
267 |
|
268 msleep(20); |
|
269 |
|
270 /* Now enable the transmitter */ |
|
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
272 |
|
273 if (hw->mac_type == e1000_82547) { |
|
274 uint16_t fused, fine, coarse; |
|
275 |
|
276 /* Move to analog registers page */ |
|
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
|
278 |
|
279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
|
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
|
281 |
|
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
|
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
|
284 |
|
285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
|
286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
|
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
|
288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
|
289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
|
290 |
|
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
|
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
|
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
|
294 |
|
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
|
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, |
|
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
|
298 } |
|
299 } |
|
300 } |
|
301 } |
|
302 |
|
303 /****************************************************************************** |
|
304 * Set the mac type member in the hw struct. |
|
305 * |
|
306 * hw - Struct containing variables accessed by shared code |
|
307 *****************************************************************************/ |
|
308 int32_t |
|
309 e1000_set_mac_type(struct e1000_hw *hw) |
|
310 { |
|
311 DEBUGFUNC("e1000_set_mac_type"); |
|
312 |
|
313 switch (hw->device_id) { |
|
314 case E1000_DEV_ID_82542: |
|
315 switch (hw->revision_id) { |
|
316 case E1000_82542_2_0_REV_ID: |
|
317 hw->mac_type = e1000_82542_rev2_0; |
|
318 break; |
|
319 case E1000_82542_2_1_REV_ID: |
|
320 hw->mac_type = e1000_82542_rev2_1; |
|
321 break; |
|
322 default: |
|
323 /* Invalid 82542 revision ID */ |
|
324 return -E1000_ERR_MAC_TYPE; |
|
325 } |
|
326 break; |
|
327 case E1000_DEV_ID_82543GC_FIBER: |
|
328 case E1000_DEV_ID_82543GC_COPPER: |
|
329 hw->mac_type = e1000_82543; |
|
330 break; |
|
331 case E1000_DEV_ID_82544EI_COPPER: |
|
332 case E1000_DEV_ID_82544EI_FIBER: |
|
333 case E1000_DEV_ID_82544GC_COPPER: |
|
334 case E1000_DEV_ID_82544GC_LOM: |
|
335 hw->mac_type = e1000_82544; |
|
336 break; |
|
337 case E1000_DEV_ID_82540EM: |
|
338 case E1000_DEV_ID_82540EM_LOM: |
|
339 case E1000_DEV_ID_82540EP: |
|
340 case E1000_DEV_ID_82540EP_LOM: |
|
341 case E1000_DEV_ID_82540EP_LP: |
|
342 hw->mac_type = e1000_82540; |
|
343 break; |
|
344 case E1000_DEV_ID_82545EM_COPPER: |
|
345 case E1000_DEV_ID_82545EM_FIBER: |
|
346 hw->mac_type = e1000_82545; |
|
347 break; |
|
348 case E1000_DEV_ID_82545GM_COPPER: |
|
349 case E1000_DEV_ID_82545GM_FIBER: |
|
350 case E1000_DEV_ID_82545GM_SERDES: |
|
351 hw->mac_type = e1000_82545_rev_3; |
|
352 break; |
|
353 case E1000_DEV_ID_82546EB_COPPER: |
|
354 case E1000_DEV_ID_82546EB_FIBER: |
|
355 case E1000_DEV_ID_82546EB_QUAD_COPPER: |
|
356 hw->mac_type = e1000_82546; |
|
357 break; |
|
358 case E1000_DEV_ID_82546GB_COPPER: |
|
359 case E1000_DEV_ID_82546GB_FIBER: |
|
360 case E1000_DEV_ID_82546GB_SERDES: |
|
361 case E1000_DEV_ID_82546GB_PCIE: |
|
362 case E1000_DEV_ID_82546GB_QUAD_COPPER: |
|
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
|
364 hw->mac_type = e1000_82546_rev_3; |
|
365 break; |
|
366 case E1000_DEV_ID_82541EI: |
|
367 case E1000_DEV_ID_82541EI_MOBILE: |
|
368 case E1000_DEV_ID_82541ER_LOM: |
|
369 hw->mac_type = e1000_82541; |
|
370 break; |
|
371 case E1000_DEV_ID_82541ER: |
|
372 case E1000_DEV_ID_82541GI: |
|
373 case E1000_DEV_ID_82541GI_LF: |
|
374 case E1000_DEV_ID_82541GI_MOBILE: |
|
375 hw->mac_type = e1000_82541_rev_2; |
|
376 break; |
|
377 case E1000_DEV_ID_82547EI: |
|
378 case E1000_DEV_ID_82547EI_MOBILE: |
|
379 hw->mac_type = e1000_82547; |
|
380 break; |
|
381 case E1000_DEV_ID_82547GI: |
|
382 hw->mac_type = e1000_82547_rev_2; |
|
383 break; |
|
384 case E1000_DEV_ID_82571EB_COPPER: |
|
385 case E1000_DEV_ID_82571EB_FIBER: |
|
386 case E1000_DEV_ID_82571EB_SERDES: |
|
387 case E1000_DEV_ID_82571EB_SERDES_DUAL: |
|
388 case E1000_DEV_ID_82571EB_SERDES_QUAD: |
|
389 case E1000_DEV_ID_82571EB_QUAD_COPPER: |
|
390 case E1000_DEV_ID_82571PT_QUAD_COPPER: |
|
391 case E1000_DEV_ID_82571EB_QUAD_FIBER: |
|
392 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: |
|
393 hw->mac_type = e1000_82571; |
|
394 break; |
|
395 case E1000_DEV_ID_82572EI_COPPER: |
|
396 case E1000_DEV_ID_82572EI_FIBER: |
|
397 case E1000_DEV_ID_82572EI_SERDES: |
|
398 case E1000_DEV_ID_82572EI: |
|
399 hw->mac_type = e1000_82572; |
|
400 break; |
|
401 case E1000_DEV_ID_82573E: |
|
402 case E1000_DEV_ID_82573E_IAMT: |
|
403 case E1000_DEV_ID_82573L: |
|
404 hw->mac_type = e1000_82573; |
|
405 break; |
|
406 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
|
407 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: |
|
408 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: |
|
409 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
|
410 hw->mac_type = e1000_80003es2lan; |
|
411 break; |
|
412 case E1000_DEV_ID_ICH8_IGP_M_AMT: |
|
413 case E1000_DEV_ID_ICH8_IGP_AMT: |
|
414 case E1000_DEV_ID_ICH8_IGP_C: |
|
415 case E1000_DEV_ID_ICH8_IFE: |
|
416 case E1000_DEV_ID_ICH8_IFE_GT: |
|
417 case E1000_DEV_ID_ICH8_IFE_G: |
|
418 case E1000_DEV_ID_ICH8_IGP_M: |
|
419 hw->mac_type = e1000_ich8lan; |
|
420 break; |
|
421 default: |
|
422 /* Should never have loaded on this device */ |
|
423 return -E1000_ERR_MAC_TYPE; |
|
424 } |
|
425 |
|
426 switch (hw->mac_type) { |
|
427 case e1000_ich8lan: |
|
428 hw->swfwhw_semaphore_present = TRUE; |
|
429 hw->asf_firmware_present = TRUE; |
|
430 break; |
|
431 case e1000_80003es2lan: |
|
432 hw->swfw_sync_present = TRUE; |
|
433 /* fall through */ |
|
434 case e1000_82571: |
|
435 case e1000_82572: |
|
436 case e1000_82573: |
|
437 hw->eeprom_semaphore_present = TRUE; |
|
438 /* fall through */ |
|
439 case e1000_82541: |
|
440 case e1000_82547: |
|
441 case e1000_82541_rev_2: |
|
442 case e1000_82547_rev_2: |
|
443 hw->asf_firmware_present = TRUE; |
|
444 break; |
|
445 default: |
|
446 break; |
|
447 } |
|
448 |
|
449 /* The 82543 chip does not count tx_carrier_errors properly in |
|
450 * FD mode |
|
451 */ |
|
452 if (hw->mac_type == e1000_82543) |
|
453 hw->bad_tx_carr_stats_fd = TRUE; |
|
454 |
|
455 /* capable of receiving management packets to the host */ |
|
456 if (hw->mac_type >= e1000_82571) |
|
457 hw->has_manc2h = TRUE; |
|
458 |
|
459 /* In rare occasions, ESB2 systems would end up started without |
|
460 * the RX unit being turned on. |
|
461 */ |
|
462 if (hw->mac_type == e1000_80003es2lan) |
|
463 hw->rx_needs_kicking = TRUE; |
|
464 |
|
465 if (hw->mac_type > e1000_82544) |
|
466 hw->has_smbus = TRUE; |
|
467 |
|
468 return E1000_SUCCESS; |
|
469 } |
|
470 |
|
471 /***************************************************************************** |
|
472 * Set media type and TBI compatibility. |
|
473 * |
|
474 * hw - Struct containing variables accessed by shared code |
|
475 * **************************************************************************/ |
|
476 void |
|
477 e1000_set_media_type(struct e1000_hw *hw) |
|
478 { |
|
479 uint32_t status; |
|
480 |
|
481 DEBUGFUNC("e1000_set_media_type"); |
|
482 |
|
483 if (hw->mac_type != e1000_82543) { |
|
484 /* tbi_compatibility is only valid on 82543 */ |
|
485 hw->tbi_compatibility_en = FALSE; |
|
486 } |
|
487 |
|
488 switch (hw->device_id) { |
|
489 case E1000_DEV_ID_82545GM_SERDES: |
|
490 case E1000_DEV_ID_82546GB_SERDES: |
|
491 case E1000_DEV_ID_82571EB_SERDES: |
|
492 case E1000_DEV_ID_82571EB_SERDES_DUAL: |
|
493 case E1000_DEV_ID_82571EB_SERDES_QUAD: |
|
494 case E1000_DEV_ID_82572EI_SERDES: |
|
495 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
|
496 hw->media_type = e1000_media_type_internal_serdes; |
|
497 break; |
|
498 default: |
|
499 switch (hw->mac_type) { |
|
500 case e1000_82542_rev2_0: |
|
501 case e1000_82542_rev2_1: |
|
502 hw->media_type = e1000_media_type_fiber; |
|
503 break; |
|
504 case e1000_ich8lan: |
|
505 case e1000_82573: |
|
506 /* The STATUS_TBIMODE bit is reserved or reused for the this |
|
507 * device. |
|
508 */ |
|
509 hw->media_type = e1000_media_type_copper; |
|
510 break; |
|
511 default: |
|
512 status = E1000_READ_REG(hw, STATUS); |
|
513 if (status & E1000_STATUS_TBIMODE) { |
|
514 hw->media_type = e1000_media_type_fiber; |
|
515 /* tbi_compatibility not valid on fiber */ |
|
516 hw->tbi_compatibility_en = FALSE; |
|
517 } else { |
|
518 hw->media_type = e1000_media_type_copper; |
|
519 } |
|
520 break; |
|
521 } |
|
522 } |
|
523 } |
|
524 |
|
525 /****************************************************************************** |
|
526 * Reset the transmit and receive units; mask and clear all interrupts. |
|
527 * |
|
528 * hw - Struct containing variables accessed by shared code |
|
529 *****************************************************************************/ |
|
530 int32_t |
|
531 e1000_reset_hw(struct e1000_hw *hw) |
|
532 { |
|
533 uint32_t ctrl; |
|
534 uint32_t ctrl_ext; |
|
535 uint32_t icr; |
|
536 uint32_t manc; |
|
537 uint32_t led_ctrl; |
|
538 uint32_t timeout; |
|
539 uint32_t extcnf_ctrl; |
|
540 int32_t ret_val; |
|
541 |
|
542 DEBUGFUNC("e1000_reset_hw"); |
|
543 |
|
544 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
|
545 if (hw->mac_type == e1000_82542_rev2_0) { |
|
546 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
|
547 e1000_pci_clear_mwi(hw); |
|
548 } |
|
549 |
|
550 if (hw->bus_type == e1000_bus_type_pci_express) { |
|
551 /* Prevent the PCI-E bus from sticking if there is no TLP connection |
|
552 * on the last TLP read/write transaction when MAC is reset. |
|
553 */ |
|
554 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
|
555 DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
|
556 } |
|
557 } |
|
558 |
|
559 /* Clear interrupt mask to stop board from generating interrupts */ |
|
560 DEBUGOUT("Masking off all interrupts\n"); |
|
561 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
562 |
|
563 /* Disable the Transmit and Receive units. Then delay to allow |
|
564 * any pending transactions to complete before we hit the MAC with |
|
565 * the global reset. |
|
566 */ |
|
567 E1000_WRITE_REG(hw, RCTL, 0); |
|
568 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
|
569 E1000_WRITE_FLUSH(hw); |
|
570 |
|
571 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
|
572 hw->tbi_compatibility_on = FALSE; |
|
573 |
|
574 /* Delay to allow any outstanding PCI transactions to complete before |
|
575 * resetting the device |
|
576 */ |
|
577 msleep(10); |
|
578 |
|
579 ctrl = E1000_READ_REG(hw, CTRL); |
|
580 |
|
581 /* Must reset the PHY before resetting the MAC */ |
|
582 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
583 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
|
584 msleep(5); |
|
585 } |
|
586 |
|
587 /* Must acquire the MDIO ownership before MAC reset. |
|
588 * Ownership defaults to firmware after a reset. */ |
|
589 if (hw->mac_type == e1000_82573) { |
|
590 timeout = 10; |
|
591 |
|
592 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
593 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
594 |
|
595 do { |
|
596 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
597 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
598 |
|
599 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
|
600 break; |
|
601 else |
|
602 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
603 |
|
604 msleep(2); |
|
605 timeout--; |
|
606 } while (timeout); |
|
607 } |
|
608 |
|
609 /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
|
610 if (hw->mac_type == e1000_ich8lan) { |
|
611 /* Set Tx and Rx buffer allocation to 8k apiece. */ |
|
612 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); |
|
613 /* Set Packet Buffer Size to 16k. */ |
|
614 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); |
|
615 } |
|
616 |
|
617 /* Issue a global reset to the MAC. This will reset the chip's |
|
618 * transmit, receive, DMA, and link units. It will not effect |
|
619 * the current PCI configuration. The global reset bit is self- |
|
620 * clearing, and should clear within a microsecond. |
|
621 */ |
|
622 DEBUGOUT("Issuing a global reset to MAC\n"); |
|
623 |
|
624 switch (hw->mac_type) { |
|
625 case e1000_82544: |
|
626 case e1000_82540: |
|
627 case e1000_82545: |
|
628 case e1000_82546: |
|
629 case e1000_82541: |
|
630 case e1000_82541_rev_2: |
|
631 /* These controllers can't ack the 64-bit write when issuing the |
|
632 * reset, so use IO-mapping as a workaround to issue the reset */ |
|
633 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
634 break; |
|
635 case e1000_82545_rev_3: |
|
636 case e1000_82546_rev_3: |
|
637 /* Reset is performed on a shadow of the control register */ |
|
638 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
|
639 break; |
|
640 case e1000_ich8lan: |
|
641 if (!hw->phy_reset_disable && |
|
642 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { |
|
643 /* e1000_ich8lan PHY HW reset requires MAC CORE reset |
|
644 * at the same time to make sure the interface between |
|
645 * MAC and the external PHY is reset. |
|
646 */ |
|
647 ctrl |= E1000_CTRL_PHY_RST; |
|
648 } |
|
649 |
|
650 e1000_get_software_flag(hw); |
|
651 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
652 msleep(5); |
|
653 break; |
|
654 default: |
|
655 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
|
656 break; |
|
657 } |
|
658 |
|
659 /* After MAC reset, force reload of EEPROM to restore power-on settings to |
|
660 * device. Later controllers reload the EEPROM automatically, so just wait |
|
661 * for reload to complete. |
|
662 */ |
|
663 switch (hw->mac_type) { |
|
664 case e1000_82542_rev2_0: |
|
665 case e1000_82542_rev2_1: |
|
666 case e1000_82543: |
|
667 case e1000_82544: |
|
668 /* Wait for reset to complete */ |
|
669 udelay(10); |
|
670 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
671 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
672 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
673 E1000_WRITE_FLUSH(hw); |
|
674 /* Wait for EEPROM reload */ |
|
675 msleep(2); |
|
676 break; |
|
677 case e1000_82541: |
|
678 case e1000_82541_rev_2: |
|
679 case e1000_82547: |
|
680 case e1000_82547_rev_2: |
|
681 /* Wait for EEPROM reload */ |
|
682 msleep(20); |
|
683 break; |
|
684 case e1000_82573: |
|
685 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
|
686 udelay(10); |
|
687 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
688 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
689 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
690 E1000_WRITE_FLUSH(hw); |
|
691 } |
|
692 /* fall through */ |
|
693 default: |
|
694 /* Auto read done will delay 5ms or poll based on mac type */ |
|
695 ret_val = e1000_get_auto_rd_done(hw); |
|
696 if (ret_val) |
|
697 return ret_val; |
|
698 break; |
|
699 } |
|
700 |
|
701 /* Disable HW ARPs on ASF enabled adapters */ |
|
702 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
|
703 manc = E1000_READ_REG(hw, MANC); |
|
704 manc &= ~(E1000_MANC_ARP_EN); |
|
705 E1000_WRITE_REG(hw, MANC, manc); |
|
706 } |
|
707 |
|
708 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
709 e1000_phy_init_script(hw); |
|
710 |
|
711 /* Configure activity LED after PHY reset */ |
|
712 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
713 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
714 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
715 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
716 } |
|
717 |
|
718 /* Clear interrupt mask to stop board from generating interrupts */ |
|
719 DEBUGOUT("Masking off all interrupts\n"); |
|
720 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
721 |
|
722 /* Clear any pending interrupt events. */ |
|
723 icr = E1000_READ_REG(hw, ICR); |
|
724 |
|
725 /* If MWI was previously enabled, reenable it. */ |
|
726 if (hw->mac_type == e1000_82542_rev2_0) { |
|
727 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
728 e1000_pci_set_mwi(hw); |
|
729 } |
|
730 |
|
731 if (hw->mac_type == e1000_ich8lan) { |
|
732 uint32_t kab = E1000_READ_REG(hw, KABGTXD); |
|
733 kab |= E1000_KABGTXD_BGSQLBIAS; |
|
734 E1000_WRITE_REG(hw, KABGTXD, kab); |
|
735 } |
|
736 |
|
737 return E1000_SUCCESS; |
|
738 } |
|
739 |
|
740 /****************************************************************************** |
|
741 * |
|
742 * Initialize a number of hardware-dependent bits |
|
743 * |
|
744 * hw: Struct containing variables accessed by shared code |
|
745 * |
|
746 * This function contains hardware limitation workarounds for PCI-E adapters |
|
747 * |
|
748 *****************************************************************************/ |
|
749 static void |
|
750 e1000_initialize_hardware_bits(struct e1000_hw *hw) |
|
751 { |
|
752 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { |
|
753 /* Settings common to all PCI-express silicon */ |
|
754 uint32_t reg_ctrl, reg_ctrl_ext; |
|
755 uint32_t reg_tarc0, reg_tarc1; |
|
756 uint32_t reg_tctl; |
|
757 uint32_t reg_txdctl, reg_txdctl1; |
|
758 |
|
759 /* link autonegotiation/sync workarounds */ |
|
760 reg_tarc0 = E1000_READ_REG(hw, TARC0); |
|
761 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
|
762 |
|
763 /* Enable not-done TX descriptor counting */ |
|
764 reg_txdctl = E1000_READ_REG(hw, TXDCTL); |
|
765 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; |
|
766 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); |
|
767 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); |
|
768 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; |
|
769 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); |
|
770 |
|
771 switch (hw->mac_type) { |
|
772 case e1000_82571: |
|
773 case e1000_82572: |
|
774 /* Clear PHY TX compatible mode bits */ |
|
775 reg_tarc1 = E1000_READ_REG(hw, TARC1); |
|
776 reg_tarc1 &= ~((1 << 30)|(1 << 29)); |
|
777 |
|
778 /* link autonegotiation/sync workarounds */ |
|
779 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); |
|
780 |
|
781 /* TX ring control fixes */ |
|
782 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); |
|
783 |
|
784 /* Multiple read bit is reversed polarity */ |
|
785 reg_tctl = E1000_READ_REG(hw, TCTL); |
|
786 if (reg_tctl & E1000_TCTL_MULR) |
|
787 reg_tarc1 &= ~(1 << 28); |
|
788 else |
|
789 reg_tarc1 |= (1 << 28); |
|
790 |
|
791 E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
|
792 break; |
|
793 case e1000_82573: |
|
794 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
795 reg_ctrl_ext &= ~(1 << 23); |
|
796 reg_ctrl_ext |= (1 << 22); |
|
797 |
|
798 /* TX byte count fix */ |
|
799 reg_ctrl = E1000_READ_REG(hw, CTRL); |
|
800 reg_ctrl &= ~(1 << 29); |
|
801 |
|
802 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
|
803 E1000_WRITE_REG(hw, CTRL, reg_ctrl); |
|
804 break; |
|
805 case e1000_80003es2lan: |
|
806 /* improve small packet performace for fiber/serdes */ |
|
807 if ((hw->media_type == e1000_media_type_fiber) || |
|
808 (hw->media_type == e1000_media_type_internal_serdes)) { |
|
809 reg_tarc0 &= ~(1 << 20); |
|
810 } |
|
811 |
|
812 /* Multiple read bit is reversed polarity */ |
|
813 reg_tctl = E1000_READ_REG(hw, TCTL); |
|
814 reg_tarc1 = E1000_READ_REG(hw, TARC1); |
|
815 if (reg_tctl & E1000_TCTL_MULR) |
|
816 reg_tarc1 &= ~(1 << 28); |
|
817 else |
|
818 reg_tarc1 |= (1 << 28); |
|
819 |
|
820 E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
|
821 break; |
|
822 case e1000_ich8lan: |
|
823 /* Reduce concurrent DMA requests to 3 from 4 */ |
|
824 if ((hw->revision_id < 3) || |
|
825 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
|
826 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) |
|
827 reg_tarc0 |= ((1 << 29)|(1 << 28)); |
|
828 |
|
829 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
830 reg_ctrl_ext |= (1 << 22); |
|
831 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
|
832 |
|
833 /* workaround TX hang with TSO=on */ |
|
834 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); |
|
835 |
|
836 /* Multiple read bit is reversed polarity */ |
|
837 reg_tctl = E1000_READ_REG(hw, TCTL); |
|
838 reg_tarc1 = E1000_READ_REG(hw, TARC1); |
|
839 if (reg_tctl & E1000_TCTL_MULR) |
|
840 reg_tarc1 &= ~(1 << 28); |
|
841 else |
|
842 reg_tarc1 |= (1 << 28); |
|
843 |
|
844 /* workaround TX hang with TSO=on */ |
|
845 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); |
|
846 |
|
847 E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
|
848 break; |
|
849 default: |
|
850 break; |
|
851 } |
|
852 |
|
853 E1000_WRITE_REG(hw, TARC0, reg_tarc0); |
|
854 } |
|
855 } |
|
856 |
|
857 /****************************************************************************** |
|
858 * Performs basic configuration of the adapter. |
|
859 * |
|
860 * hw - Struct containing variables accessed by shared code |
|
861 * |
|
862 * Assumes that the controller has previously been reset and is in a |
|
863 * post-reset uninitialized state. Initializes the receive address registers, |
|
864 * multicast table, and VLAN filter table. Calls routines to setup link |
|
865 * configuration and flow control settings. Clears all on-chip counters. Leaves |
|
866 * the transmit and receive units disabled and uninitialized. |
|
867 *****************************************************************************/ |
|
868 int32_t |
|
869 e1000_init_hw(struct e1000_hw *hw) |
|
870 { |
|
871 uint32_t ctrl; |
|
872 uint32_t i; |
|
873 int32_t ret_val; |
|
874 uint32_t mta_size; |
|
875 uint32_t reg_data; |
|
876 uint32_t ctrl_ext; |
|
877 |
|
878 DEBUGFUNC("e1000_init_hw"); |
|
879 |
|
880 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
|
881 if ((hw->mac_type == e1000_ich8lan) && |
|
882 ((hw->revision_id < 3) || |
|
883 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
|
884 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { |
|
885 reg_data = E1000_READ_REG(hw, STATUS); |
|
886 reg_data &= ~0x80000000; |
|
887 E1000_WRITE_REG(hw, STATUS, reg_data); |
|
888 } |
|
889 |
|
890 /* Initialize Identification LED */ |
|
891 ret_val = e1000_id_led_init(hw); |
|
892 if (ret_val) { |
|
893 DEBUGOUT("Error Initializing Identification LED\n"); |
|
894 return ret_val; |
|
895 } |
|
896 |
|
897 /* Set the media type and TBI compatibility */ |
|
898 e1000_set_media_type(hw); |
|
899 |
|
900 /* Must be called after e1000_set_media_type because media_type is used */ |
|
901 e1000_initialize_hardware_bits(hw); |
|
902 |
|
903 /* Disabling VLAN filtering. */ |
|
904 DEBUGOUT("Initializing the IEEE VLAN\n"); |
|
905 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
|
906 if (hw->mac_type != e1000_ich8lan) { |
|
907 if (hw->mac_type < e1000_82545_rev_3) |
|
908 E1000_WRITE_REG(hw, VET, 0); |
|
909 e1000_clear_vfta(hw); |
|
910 } |
|
911 |
|
912 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
|
913 if (hw->mac_type == e1000_82542_rev2_0) { |
|
914 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
|
915 e1000_pci_clear_mwi(hw); |
|
916 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
|
917 E1000_WRITE_FLUSH(hw); |
|
918 msleep(5); |
|
919 } |
|
920 |
|
921 /* Setup the receive address. This involves initializing all of the Receive |
|
922 * Address Registers (RARs 0 - 15). |
|
923 */ |
|
924 e1000_init_rx_addrs(hw); |
|
925 |
|
926 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
|
927 if (hw->mac_type == e1000_82542_rev2_0) { |
|
928 E1000_WRITE_REG(hw, RCTL, 0); |
|
929 E1000_WRITE_FLUSH(hw); |
|
930 msleep(1); |
|
931 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
|
932 e1000_pci_set_mwi(hw); |
|
933 } |
|
934 |
|
935 /* Zero out the Multicast HASH table */ |
|
936 DEBUGOUT("Zeroing the MTA\n"); |
|
937 mta_size = E1000_MC_TBL_SIZE; |
|
938 if (hw->mac_type == e1000_ich8lan) |
|
939 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; |
|
940 for (i = 0; i < mta_size; i++) { |
|
941 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
|
942 /* use write flush to prevent Memory Write Block (MWB) from |
|
943 * occuring when accessing our register space */ |
|
944 E1000_WRITE_FLUSH(hw); |
|
945 } |
|
946 |
|
947 /* Set the PCI priority bit correctly in the CTRL register. This |
|
948 * determines if the adapter gives priority to receives, or if it |
|
949 * gives equal priority to transmits and receives. Valid only on |
|
950 * 82542 and 82543 silicon. |
|
951 */ |
|
952 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
|
953 ctrl = E1000_READ_REG(hw, CTRL); |
|
954 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
|
955 } |
|
956 |
|
957 switch (hw->mac_type) { |
|
958 case e1000_82545_rev_3: |
|
959 case e1000_82546_rev_3: |
|
960 break; |
|
961 default: |
|
962 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
|
963 if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) |
|
964 e1000_pcix_set_mmrbc(hw, 2048); |
|
965 break; |
|
966 } |
|
967 |
|
968 /* More time needed for PHY to initialize */ |
|
969 if (hw->mac_type == e1000_ich8lan) |
|
970 msleep(15); |
|
971 |
|
972 /* Call a subroutine to configure the link and setup flow control. */ |
|
973 ret_val = e1000_setup_link(hw); |
|
974 |
|
975 /* Set the transmit descriptor write-back policy */ |
|
976 if (hw->mac_type > e1000_82544) { |
|
977 ctrl = E1000_READ_REG(hw, TXDCTL); |
|
978 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
|
979 E1000_WRITE_REG(hw, TXDCTL, ctrl); |
|
980 } |
|
981 |
|
982 if (hw->mac_type == e1000_82573) { |
|
983 e1000_enable_tx_pkt_filtering(hw); |
|
984 } |
|
985 |
|
986 switch (hw->mac_type) { |
|
987 default: |
|
988 break; |
|
989 case e1000_80003es2lan: |
|
990 /* Enable retransmit on late collisions */ |
|
991 reg_data = E1000_READ_REG(hw, TCTL); |
|
992 reg_data |= E1000_TCTL_RTLC; |
|
993 E1000_WRITE_REG(hw, TCTL, reg_data); |
|
994 |
|
995 /* Configure Gigabit Carry Extend Padding */ |
|
996 reg_data = E1000_READ_REG(hw, TCTL_EXT); |
|
997 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
|
998 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; |
|
999 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); |
|
1000 |
|
1001 /* Configure Transmit Inter-Packet Gap */ |
|
1002 reg_data = E1000_READ_REG(hw, TIPG); |
|
1003 reg_data &= ~E1000_TIPG_IPGT_MASK; |
|
1004 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
|
1005 E1000_WRITE_REG(hw, TIPG, reg_data); |
|
1006 |
|
1007 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); |
|
1008 reg_data &= ~0x00100000; |
|
1009 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); |
|
1010 /* Fall through */ |
|
1011 case e1000_82571: |
|
1012 case e1000_82572: |
|
1013 case e1000_ich8lan: |
|
1014 ctrl = E1000_READ_REG(hw, TXDCTL1); |
|
1015 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
|
1016 E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
|
1017 break; |
|
1018 } |
|
1019 |
|
1020 |
|
1021 if (hw->mac_type == e1000_82573) { |
|
1022 uint32_t gcr = E1000_READ_REG(hw, GCR); |
|
1023 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
|
1024 E1000_WRITE_REG(hw, GCR, gcr); |
|
1025 } |
|
1026 |
|
1027 /* Clear all of the statistics registers (clear on read). It is |
|
1028 * important that we do this after we have tried to establish link |
|
1029 * because the symbol error count will increment wildly if there |
|
1030 * is no link. |
|
1031 */ |
|
1032 e1000_clear_hw_cntrs(hw); |
|
1033 |
|
1034 /* ICH8 No-snoop bits are opposite polarity. |
|
1035 * Set to snoop by default after reset. */ |
|
1036 if (hw->mac_type == e1000_ich8lan) |
|
1037 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); |
|
1038 |
|
1039 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
|
1040 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
|
1041 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
1042 /* Relaxed ordering must be disabled to avoid a parity |
|
1043 * error crash in a PCI slot. */ |
|
1044 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
1045 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
1046 } |
|
1047 |
|
1048 return ret_val; |
|
1049 } |
|
1050 |
|
1051 /****************************************************************************** |
|
1052 * Adjust SERDES output amplitude based on EEPROM setting. |
|
1053 * |
|
1054 * hw - Struct containing variables accessed by shared code. |
|
1055 *****************************************************************************/ |
|
1056 static int32_t |
|
1057 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
|
1058 { |
|
1059 uint16_t eeprom_data; |
|
1060 int32_t ret_val; |
|
1061 |
|
1062 DEBUGFUNC("e1000_adjust_serdes_amplitude"); |
|
1063 |
|
1064 if (hw->media_type != e1000_media_type_internal_serdes) |
|
1065 return E1000_SUCCESS; |
|
1066 |
|
1067 switch (hw->mac_type) { |
|
1068 case e1000_82545_rev_3: |
|
1069 case e1000_82546_rev_3: |
|
1070 break; |
|
1071 default: |
|
1072 return E1000_SUCCESS; |
|
1073 } |
|
1074 |
|
1075 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); |
|
1076 if (ret_val) { |
|
1077 return ret_val; |
|
1078 } |
|
1079 |
|
1080 if (eeprom_data != EEPROM_RESERVED_WORD) { |
|
1081 /* Adjust SERDES output amplitude only. */ |
|
1082 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
|
1083 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
|
1084 if (ret_val) |
|
1085 return ret_val; |
|
1086 } |
|
1087 |
|
1088 return E1000_SUCCESS; |
|
1089 } |
|
1090 |
|
1091 /****************************************************************************** |
|
1092 * Configures flow control and link settings. |
|
1093 * |
|
1094 * hw - Struct containing variables accessed by shared code |
|
1095 * |
|
1096 * Determines which flow control settings to use. Calls the apropriate media- |
|
1097 * specific link configuration function. Configures the flow control settings. |
|
1098 * Assuming the adapter has a valid link partner, a valid link should be |
|
1099 * established. Assumes the hardware has previously been reset and the |
|
1100 * transmitter and receiver are not enabled. |
|
1101 *****************************************************************************/ |
|
1102 int32_t |
|
1103 e1000_setup_link(struct e1000_hw *hw) |
|
1104 { |
|
1105 uint32_t ctrl_ext; |
|
1106 int32_t ret_val; |
|
1107 uint16_t eeprom_data; |
|
1108 |
|
1109 DEBUGFUNC("e1000_setup_link"); |
|
1110 |
|
1111 /* In the case of the phy reset being blocked, we already have a link. |
|
1112 * We do not have to set it up again. */ |
|
1113 if (e1000_check_phy_reset_block(hw)) |
|
1114 return E1000_SUCCESS; |
|
1115 |
|
1116 /* Read and store word 0x0F of the EEPROM. This word contains bits |
|
1117 * that determine the hardware's default PAUSE (flow control) mode, |
|
1118 * a bit that determines whether the HW defaults to enabling or |
|
1119 * disabling auto-negotiation, and the direction of the |
|
1120 * SW defined pins. If there is no SW over-ride of the flow |
|
1121 * control setting, then the variable hw->fc will |
|
1122 * be initialized based on a value in the EEPROM. |
|
1123 */ |
|
1124 if (hw->fc == E1000_FC_DEFAULT) { |
|
1125 switch (hw->mac_type) { |
|
1126 case e1000_ich8lan: |
|
1127 case e1000_82573: |
|
1128 hw->fc = E1000_FC_FULL; |
|
1129 break; |
|
1130 default: |
|
1131 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
1132 1, &eeprom_data); |
|
1133 if (ret_val) { |
|
1134 DEBUGOUT("EEPROM Read Error\n"); |
|
1135 return -E1000_ERR_EEPROM; |
|
1136 } |
|
1137 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
|
1138 hw->fc = E1000_FC_NONE; |
|
1139 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
|
1140 EEPROM_WORD0F_ASM_DIR) |
|
1141 hw->fc = E1000_FC_TX_PAUSE; |
|
1142 else |
|
1143 hw->fc = E1000_FC_FULL; |
|
1144 break; |
|
1145 } |
|
1146 } |
|
1147 |
|
1148 /* We want to save off the original Flow Control configuration just |
|
1149 * in case we get disconnected and then reconnected into a different |
|
1150 * hub or switch with different Flow Control capabilities. |
|
1151 */ |
|
1152 if (hw->mac_type == e1000_82542_rev2_0) |
|
1153 hw->fc &= (~E1000_FC_TX_PAUSE); |
|
1154 |
|
1155 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
|
1156 hw->fc &= (~E1000_FC_RX_PAUSE); |
|
1157 |
|
1158 hw->original_fc = hw->fc; |
|
1159 |
|
1160 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
|
1161 |
|
1162 /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
|
1163 * polarity value for the SW controlled pins, and setup the |
|
1164 * Extended Device Control reg with that info. |
|
1165 * This is needed because one of the SW controlled pins is used for |
|
1166 * signal detection. So this should be done before e1000_setup_pcs_link() |
|
1167 * or e1000_phy_setup() is called. |
|
1168 */ |
|
1169 if (hw->mac_type == e1000_82543) { |
|
1170 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
|
1171 1, &eeprom_data); |
|
1172 if (ret_val) { |
|
1173 DEBUGOUT("EEPROM Read Error\n"); |
|
1174 return -E1000_ERR_EEPROM; |
|
1175 } |
|
1176 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
|
1177 SWDPIO__EXT_SHIFT); |
|
1178 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
1179 } |
|
1180 |
|
1181 /* Call the necessary subroutine to configure the link. */ |
|
1182 ret_val = (hw->media_type == e1000_media_type_copper) ? |
|
1183 e1000_setup_copper_link(hw) : |
|
1184 e1000_setup_fiber_serdes_link(hw); |
|
1185 |
|
1186 /* Initialize the flow control address, type, and PAUSE timer |
|
1187 * registers to their default values. This is done even if flow |
|
1188 * control is disabled, because it does not hurt anything to |
|
1189 * initialize these registers. |
|
1190 */ |
|
1191 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); |
|
1192 |
|
1193 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
|
1194 if (hw->mac_type != e1000_ich8lan) { |
|
1195 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
|
1196 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
|
1197 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
|
1198 } |
|
1199 |
|
1200 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
|
1201 |
|
1202 /* Set the flow control receive threshold registers. Normally, |
|
1203 * these registers will be set to a default threshold that may be |
|
1204 * adjusted later by the driver's runtime code. However, if the |
|
1205 * ability to transmit pause frames in not enabled, then these |
|
1206 * registers will be set to 0. |
|
1207 */ |
|
1208 if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
|
1209 E1000_WRITE_REG(hw, FCRTL, 0); |
|
1210 E1000_WRITE_REG(hw, FCRTH, 0); |
|
1211 } else { |
|
1212 /* We need to set up the Receive Threshold high and low water marks |
|
1213 * as well as (optionally) enabling the transmission of XON frames. |
|
1214 */ |
|
1215 if (hw->fc_send_xon) { |
|
1216 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
|
1217 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
|
1218 } else { |
|
1219 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
|
1220 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
|
1221 } |
|
1222 } |
|
1223 return ret_val; |
|
1224 } |
|
1225 |
|
1226 /****************************************************************************** |
|
1227 * Sets up link for a fiber based or serdes based adapter |
|
1228 * |
|
1229 * hw - Struct containing variables accessed by shared code |
|
1230 * |
|
1231 * Manipulates Physical Coding Sublayer functions in order to configure |
|
1232 * link. Assumes the hardware has been previously reset and the transmitter |
|
1233 * and receiver are not enabled. |
|
1234 *****************************************************************************/ |
|
1235 static int32_t |
|
1236 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
|
1237 { |
|
1238 uint32_t ctrl; |
|
1239 uint32_t status; |
|
1240 uint32_t txcw = 0; |
|
1241 uint32_t i; |
|
1242 uint32_t signal = 0; |
|
1243 int32_t ret_val; |
|
1244 |
|
1245 DEBUGFUNC("e1000_setup_fiber_serdes_link"); |
|
1246 |
|
1247 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
|
1248 * until explicitly turned off or a power cycle is performed. A read to |
|
1249 * the register does not indicate its status. Therefore, we ensure |
|
1250 * loopback mode is disabled during initialization. |
|
1251 */ |
|
1252 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) |
|
1253 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); |
|
1254 |
|
1255 /* On adapters with a MAC newer than 82544, SWDP 1 will be |
|
1256 * set when the optics detect a signal. On older adapters, it will be |
|
1257 * cleared when there is a signal. This applies to fiber media only. |
|
1258 * If we're on serdes media, adjust the output amplitude to value |
|
1259 * set in the EEPROM. |
|
1260 */ |
|
1261 ctrl = E1000_READ_REG(hw, CTRL); |
|
1262 if (hw->media_type == e1000_media_type_fiber) |
|
1263 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
1264 |
|
1265 ret_val = e1000_adjust_serdes_amplitude(hw); |
|
1266 if (ret_val) |
|
1267 return ret_val; |
|
1268 |
|
1269 /* Take the link out of reset */ |
|
1270 ctrl &= ~(E1000_CTRL_LRST); |
|
1271 |
|
1272 /* Adjust VCO speed to improve BER performance */ |
|
1273 ret_val = e1000_set_vco_speed(hw); |
|
1274 if (ret_val) |
|
1275 return ret_val; |
|
1276 |
|
1277 e1000_config_collision_dist(hw); |
|
1278 |
|
1279 /* Check for a software override of the flow control settings, and setup |
|
1280 * the device accordingly. If auto-negotiation is enabled, then software |
|
1281 * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
|
1282 * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
|
1283 * auto-negotiation is disabled, then software will have to manually |
|
1284 * configure the two flow control enable bits in the CTRL register. |
|
1285 * |
|
1286 * The possible values of the "fc" parameter are: |
|
1287 * 0: Flow control is completely disabled |
|
1288 * 1: Rx flow control is enabled (we can receive pause frames, but |
|
1289 * not send pause frames). |
|
1290 * 2: Tx flow control is enabled (we can send pause frames but we do |
|
1291 * not support receiving pause frames). |
|
1292 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
1293 */ |
|
1294 switch (hw->fc) { |
|
1295 case E1000_FC_NONE: |
|
1296 /* Flow control is completely disabled by a software over-ride. */ |
|
1297 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
|
1298 break; |
|
1299 case E1000_FC_RX_PAUSE: |
|
1300 /* RX Flow control is enabled and TX Flow control is disabled by a |
|
1301 * software over-ride. Since there really isn't a way to advertise |
|
1302 * that we are capable of RX Pause ONLY, we will advertise that we |
|
1303 * support both symmetric and asymmetric RX PAUSE. Later, we will |
|
1304 * disable the adapter's ability to send PAUSE frames. |
|
1305 */ |
|
1306 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
1307 break; |
|
1308 case E1000_FC_TX_PAUSE: |
|
1309 /* TX Flow control is enabled, and RX Flow control is disabled, by a |
|
1310 * software over-ride. |
|
1311 */ |
|
1312 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
|
1313 break; |
|
1314 case E1000_FC_FULL: |
|
1315 /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
|
1316 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
|
1317 break; |
|
1318 default: |
|
1319 DEBUGOUT("Flow control param set incorrectly\n"); |
|
1320 return -E1000_ERR_CONFIG; |
|
1321 break; |
|
1322 } |
|
1323 |
|
1324 /* Since auto-negotiation is enabled, take the link out of reset (the link |
|
1325 * will be in reset, because we previously reset the chip). This will |
|
1326 * restart auto-negotiation. If auto-neogtiation is successful then the |
|
1327 * link-up status bit will be set and the flow control enable bits (RFCE |
|
1328 * and TFCE) will be set according to their negotiated value. |
|
1329 */ |
|
1330 DEBUGOUT("Auto-negotiation enabled\n"); |
|
1331 |
|
1332 E1000_WRITE_REG(hw, TXCW, txcw); |
|
1333 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1334 E1000_WRITE_FLUSH(hw); |
|
1335 |
|
1336 hw->txcw = txcw; |
|
1337 msleep(1); |
|
1338 |
|
1339 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
|
1340 * indication in the Device Status Register. Time-out if a link isn't |
|
1341 * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
|
1342 * less than 500 milliseconds even if the other end is doing it in SW). |
|
1343 * For internal serdes, we just assume a signal is present, then poll. |
|
1344 */ |
|
1345 if (hw->media_type == e1000_media_type_internal_serdes || |
|
1346 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
|
1347 DEBUGOUT("Looking for Link\n"); |
|
1348 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
|
1349 msleep(10); |
|
1350 status = E1000_READ_REG(hw, STATUS); |
|
1351 if (status & E1000_STATUS_LU) break; |
|
1352 } |
|
1353 if (i == (LINK_UP_TIMEOUT / 10)) { |
|
1354 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
|
1355 hw->autoneg_failed = 1; |
|
1356 /* AutoNeg failed to achieve a link, so we'll call |
|
1357 * e1000_check_for_link. This routine will force the link up if |
|
1358 * we detect a signal. This will allow us to communicate with |
|
1359 * non-autonegotiating link partners. |
|
1360 */ |
|
1361 ret_val = e1000_check_for_link(hw); |
|
1362 if (ret_val) { |
|
1363 DEBUGOUT("Error while checking for link\n"); |
|
1364 return ret_val; |
|
1365 } |
|
1366 hw->autoneg_failed = 0; |
|
1367 } else { |
|
1368 hw->autoneg_failed = 0; |
|
1369 DEBUGOUT("Valid Link Found\n"); |
|
1370 } |
|
1371 } else { |
|
1372 DEBUGOUT("No Signal Detected\n"); |
|
1373 } |
|
1374 return E1000_SUCCESS; |
|
1375 } |
|
1376 |
|
1377 /****************************************************************************** |
|
1378 * Make sure we have a valid PHY and change PHY mode before link setup. |
|
1379 * |
|
1380 * hw - Struct containing variables accessed by shared code |
|
1381 ******************************************************************************/ |
|
1382 static int32_t |
|
1383 e1000_copper_link_preconfig(struct e1000_hw *hw) |
|
1384 { |
|
1385 uint32_t ctrl; |
|
1386 int32_t ret_val; |
|
1387 uint16_t phy_data; |
|
1388 |
|
1389 DEBUGFUNC("e1000_copper_link_preconfig"); |
|
1390 |
|
1391 ctrl = E1000_READ_REG(hw, CTRL); |
|
1392 /* With 82543, we need to force speed and duplex on the MAC equal to what |
|
1393 * the PHY speed and duplex configuration is. In addition, we need to |
|
1394 * perform a hardware reset on the PHY to take it out of reset. |
|
1395 */ |
|
1396 if (hw->mac_type > e1000_82543) { |
|
1397 ctrl |= E1000_CTRL_SLU; |
|
1398 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1399 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1400 } else { |
|
1401 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
|
1402 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
1403 ret_val = e1000_phy_hw_reset(hw); |
|
1404 if (ret_val) |
|
1405 return ret_val; |
|
1406 } |
|
1407 |
|
1408 /* Make sure we have a valid PHY */ |
|
1409 ret_val = e1000_detect_gig_phy(hw); |
|
1410 if (ret_val) { |
|
1411 DEBUGOUT("Error, did not detect valid phy.\n"); |
|
1412 return ret_val; |
|
1413 } |
|
1414 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
|
1415 |
|
1416 /* Set PHY to class A mode (if necessary) */ |
|
1417 ret_val = e1000_set_phy_mode(hw); |
|
1418 if (ret_val) |
|
1419 return ret_val; |
|
1420 |
|
1421 if ((hw->mac_type == e1000_82545_rev_3) || |
|
1422 (hw->mac_type == e1000_82546_rev_3)) { |
|
1423 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1424 phy_data |= 0x00000008; |
|
1425 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1426 } |
|
1427 |
|
1428 if (hw->mac_type <= e1000_82543 || |
|
1429 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
|
1430 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) |
|
1431 hw->phy_reset_disable = FALSE; |
|
1432 |
|
1433 return E1000_SUCCESS; |
|
1434 } |
|
1435 |
|
1436 |
|
1437 /******************************************************************** |
|
1438 * Copper link setup for e1000_phy_igp series. |
|
1439 * |
|
1440 * hw - Struct containing variables accessed by shared code |
|
1441 *********************************************************************/ |
|
1442 static int32_t |
|
1443 e1000_copper_link_igp_setup(struct e1000_hw *hw) |
|
1444 { |
|
1445 uint32_t led_ctrl; |
|
1446 int32_t ret_val; |
|
1447 uint16_t phy_data; |
|
1448 |
|
1449 DEBUGFUNC("e1000_copper_link_igp_setup"); |
|
1450 |
|
1451 if (hw->phy_reset_disable) |
|
1452 return E1000_SUCCESS; |
|
1453 |
|
1454 ret_val = e1000_phy_reset(hw); |
|
1455 if (ret_val) { |
|
1456 DEBUGOUT("Error Resetting the PHY\n"); |
|
1457 return ret_val; |
|
1458 } |
|
1459 |
|
1460 /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
|
1461 msleep(15); |
|
1462 if (hw->mac_type != e1000_ich8lan) { |
|
1463 /* Configure activity LED after PHY reset */ |
|
1464 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
1465 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
1466 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
1467 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
1468 } |
|
1469 |
|
1470 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
|
1471 if (hw->phy_type == e1000_phy_igp) { |
|
1472 /* disable lplu d3 during driver init */ |
|
1473 ret_val = e1000_set_d3_lplu_state(hw, FALSE); |
|
1474 if (ret_val) { |
|
1475 DEBUGOUT("Error Disabling LPLU D3\n"); |
|
1476 return ret_val; |
|
1477 } |
|
1478 } |
|
1479 |
|
1480 /* disable lplu d0 during driver init */ |
|
1481 ret_val = e1000_set_d0_lplu_state(hw, FALSE); |
|
1482 if (ret_val) { |
|
1483 DEBUGOUT("Error Disabling LPLU D0\n"); |
|
1484 return ret_val; |
|
1485 } |
|
1486 /* Configure mdi-mdix settings */ |
|
1487 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1488 if (ret_val) |
|
1489 return ret_val; |
|
1490 |
|
1491 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
1492 hw->dsp_config_state = e1000_dsp_config_disabled; |
|
1493 /* Force MDI for earlier revs of the IGP PHY */ |
|
1494 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
|
1495 hw->mdix = 1; |
|
1496 |
|
1497 } else { |
|
1498 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1499 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1500 |
|
1501 switch (hw->mdix) { |
|
1502 case 1: |
|
1503 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1504 break; |
|
1505 case 2: |
|
1506 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1507 break; |
|
1508 case 0: |
|
1509 default: |
|
1510 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
1511 break; |
|
1512 } |
|
1513 } |
|
1514 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1515 if (ret_val) |
|
1516 return ret_val; |
|
1517 |
|
1518 /* set auto-master slave resolution settings */ |
|
1519 if (hw->autoneg) { |
|
1520 e1000_ms_type phy_ms_setting = hw->master_slave; |
|
1521 |
|
1522 if (hw->ffe_config_state == e1000_ffe_config_active) |
|
1523 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
1524 |
|
1525 if (hw->dsp_config_state == e1000_dsp_config_activated) |
|
1526 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
1527 |
|
1528 /* when autonegotiation advertisment is only 1000Mbps then we |
|
1529 * should disable SmartSpeed and enable Auto MasterSlave |
|
1530 * resolution as hardware default. */ |
|
1531 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
1532 /* Disable SmartSpeed */ |
|
1533 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1534 &phy_data); |
|
1535 if (ret_val) |
|
1536 return ret_val; |
|
1537 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1538 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1539 phy_data); |
|
1540 if (ret_val) |
|
1541 return ret_val; |
|
1542 /* Set auto Master/Slave resolution process */ |
|
1543 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1544 if (ret_val) |
|
1545 return ret_val; |
|
1546 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1547 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1548 if (ret_val) |
|
1549 return ret_val; |
|
1550 } |
|
1551 |
|
1552 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
|
1553 if (ret_val) |
|
1554 return ret_val; |
|
1555 |
|
1556 /* load defaults for future use */ |
|
1557 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
|
1558 ((phy_data & CR_1000T_MS_VALUE) ? |
|
1559 e1000_ms_force_master : |
|
1560 e1000_ms_force_slave) : |
|
1561 e1000_ms_auto; |
|
1562 |
|
1563 switch (phy_ms_setting) { |
|
1564 case e1000_ms_force_master: |
|
1565 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
1566 break; |
|
1567 case e1000_ms_force_slave: |
|
1568 phy_data |= CR_1000T_MS_ENABLE; |
|
1569 phy_data &= ~(CR_1000T_MS_VALUE); |
|
1570 break; |
|
1571 case e1000_ms_auto: |
|
1572 phy_data &= ~CR_1000T_MS_ENABLE; |
|
1573 default: |
|
1574 break; |
|
1575 } |
|
1576 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
|
1577 if (ret_val) |
|
1578 return ret_val; |
|
1579 } |
|
1580 |
|
1581 return E1000_SUCCESS; |
|
1582 } |
|
1583 |
|
1584 /******************************************************************** |
|
1585 * Copper link setup for e1000_phy_gg82563 series. |
|
1586 * |
|
1587 * hw - Struct containing variables accessed by shared code |
|
1588 *********************************************************************/ |
|
1589 static int32_t |
|
1590 e1000_copper_link_ggp_setup(struct e1000_hw *hw) |
|
1591 { |
|
1592 int32_t ret_val; |
|
1593 uint16_t phy_data; |
|
1594 uint32_t reg_data; |
|
1595 |
|
1596 DEBUGFUNC("e1000_copper_link_ggp_setup"); |
|
1597 |
|
1598 if (!hw->phy_reset_disable) { |
|
1599 |
|
1600 /* Enable CRS on TX for half-duplex operation. */ |
|
1601 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
|
1602 &phy_data); |
|
1603 if (ret_val) |
|
1604 return ret_val; |
|
1605 |
|
1606 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
1607 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ |
|
1608 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; |
|
1609 |
|
1610 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
|
1611 phy_data); |
|
1612 if (ret_val) |
|
1613 return ret_val; |
|
1614 |
|
1615 /* Options: |
|
1616 * MDI/MDI-X = 0 (default) |
|
1617 * 0 - Auto for all speeds |
|
1618 * 1 - MDI mode |
|
1619 * 2 - MDI-X mode |
|
1620 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1621 */ |
|
1622 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); |
|
1623 if (ret_val) |
|
1624 return ret_val; |
|
1625 |
|
1626 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; |
|
1627 |
|
1628 switch (hw->mdix) { |
|
1629 case 1: |
|
1630 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; |
|
1631 break; |
|
1632 case 2: |
|
1633 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; |
|
1634 break; |
|
1635 case 0: |
|
1636 default: |
|
1637 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; |
|
1638 break; |
|
1639 } |
|
1640 |
|
1641 /* Options: |
|
1642 * disable_polarity_correction = 0 (default) |
|
1643 * Automatic Correction for Reversed Cable Polarity |
|
1644 * 0 - Disabled |
|
1645 * 1 - Enabled |
|
1646 */ |
|
1647 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
1648 if (hw->disable_polarity_correction == 1) |
|
1649 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
1650 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); |
|
1651 |
|
1652 if (ret_val) |
|
1653 return ret_val; |
|
1654 |
|
1655 /* SW Reset the PHY so all changes take effect */ |
|
1656 ret_val = e1000_phy_reset(hw); |
|
1657 if (ret_val) { |
|
1658 DEBUGOUT("Error Resetting the PHY\n"); |
|
1659 return ret_val; |
|
1660 } |
|
1661 } /* phy_reset_disable */ |
|
1662 |
|
1663 if (hw->mac_type == e1000_80003es2lan) { |
|
1664 /* Bypass RX and TX FIFO's */ |
|
1665 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, |
|
1666 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | |
|
1667 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); |
|
1668 if (ret_val) |
|
1669 return ret_val; |
|
1670 |
|
1671 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); |
|
1672 if (ret_val) |
|
1673 return ret_val; |
|
1674 |
|
1675 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; |
|
1676 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); |
|
1677 |
|
1678 if (ret_val) |
|
1679 return ret_val; |
|
1680 |
|
1681 reg_data = E1000_READ_REG(hw, CTRL_EXT); |
|
1682 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); |
|
1683 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); |
|
1684 |
|
1685 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
|
1686 &phy_data); |
|
1687 if (ret_val) |
|
1688 return ret_val; |
|
1689 |
|
1690 /* Do not init these registers when the HW is in IAMT mode, since the |
|
1691 * firmware will have already initialized them. We only initialize |
|
1692 * them if the HW is not in IAMT mode. |
|
1693 */ |
|
1694 if (e1000_check_mng_mode(hw) == FALSE) { |
|
1695 /* Enable Electrical Idle on the PHY */ |
|
1696 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; |
|
1697 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
|
1698 phy_data); |
|
1699 if (ret_val) |
|
1700 return ret_val; |
|
1701 |
|
1702 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
|
1703 &phy_data); |
|
1704 if (ret_val) |
|
1705 return ret_val; |
|
1706 |
|
1707 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1708 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
|
1709 phy_data); |
|
1710 |
|
1711 if (ret_val) |
|
1712 return ret_val; |
|
1713 } |
|
1714 |
|
1715 /* Workaround: Disable padding in Kumeran interface in the MAC |
|
1716 * and in the PHY to avoid CRC errors. |
|
1717 */ |
|
1718 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
|
1719 &phy_data); |
|
1720 if (ret_val) |
|
1721 return ret_val; |
|
1722 phy_data |= GG82563_ICR_DIS_PADDING; |
|
1723 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
|
1724 phy_data); |
|
1725 if (ret_val) |
|
1726 return ret_val; |
|
1727 } |
|
1728 |
|
1729 return E1000_SUCCESS; |
|
1730 } |
|
1731 |
|
1732 /******************************************************************** |
|
1733 * Copper link setup for e1000_phy_m88 series. |
|
1734 * |
|
1735 * hw - Struct containing variables accessed by shared code |
|
1736 *********************************************************************/ |
|
1737 static int32_t |
|
1738 e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
|
1739 { |
|
1740 int32_t ret_val; |
|
1741 uint16_t phy_data; |
|
1742 |
|
1743 DEBUGFUNC("e1000_copper_link_mgp_setup"); |
|
1744 |
|
1745 if (hw->phy_reset_disable) |
|
1746 return E1000_SUCCESS; |
|
1747 |
|
1748 /* Enable CRS on TX. This must be set for half-duplex operation. */ |
|
1749 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1750 if (ret_val) |
|
1751 return ret_val; |
|
1752 |
|
1753 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1754 |
|
1755 /* Options: |
|
1756 * MDI/MDI-X = 0 (default) |
|
1757 * 0 - Auto for all speeds |
|
1758 * 1 - MDI mode |
|
1759 * 2 - MDI-X mode |
|
1760 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
1761 */ |
|
1762 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1763 |
|
1764 switch (hw->mdix) { |
|
1765 case 1: |
|
1766 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
1767 break; |
|
1768 case 2: |
|
1769 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
1770 break; |
|
1771 case 3: |
|
1772 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
1773 break; |
|
1774 case 0: |
|
1775 default: |
|
1776 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
1777 break; |
|
1778 } |
|
1779 |
|
1780 /* Options: |
|
1781 * disable_polarity_correction = 0 (default) |
|
1782 * Automatic Correction for Reversed Cable Polarity |
|
1783 * 0 - Disabled |
|
1784 * 1 - Enabled |
|
1785 */ |
|
1786 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
1787 if (hw->disable_polarity_correction == 1) |
|
1788 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
1789 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1790 if (ret_val) |
|
1791 return ret_val; |
|
1792 |
|
1793 if (hw->phy_revision < M88E1011_I_REV_4) { |
|
1794 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
1795 * to 25MHz clock. |
|
1796 */ |
|
1797 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
1798 if (ret_val) |
|
1799 return ret_val; |
|
1800 |
|
1801 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1802 |
|
1803 if ((hw->phy_revision == E1000_REVISION_2) && |
|
1804 (hw->phy_id == M88E1111_I_PHY_ID)) { |
|
1805 /* Vidalia Phy, set the downshift counter to 5x */ |
|
1806 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
|
1807 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
1808 ret_val = e1000_write_phy_reg(hw, |
|
1809 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1810 if (ret_val) |
|
1811 return ret_val; |
|
1812 } else { |
|
1813 /* Configure Master and Slave downshift values */ |
|
1814 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
1815 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
1816 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
1817 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
1818 ret_val = e1000_write_phy_reg(hw, |
|
1819 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1820 if (ret_val) |
|
1821 return ret_val; |
|
1822 } |
|
1823 } |
|
1824 |
|
1825 /* SW Reset the PHY so all changes take effect */ |
|
1826 ret_val = e1000_phy_reset(hw); |
|
1827 if (ret_val) { |
|
1828 DEBUGOUT("Error Resetting the PHY\n"); |
|
1829 return ret_val; |
|
1830 } |
|
1831 |
|
1832 return E1000_SUCCESS; |
|
1833 } |
|
1834 |
|
1835 /******************************************************************** |
|
1836 * Setup auto-negotiation and flow control advertisements, |
|
1837 * and then perform auto-negotiation. |
|
1838 * |
|
1839 * hw - Struct containing variables accessed by shared code |
|
1840 *********************************************************************/ |
|
1841 static int32_t |
|
1842 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1843 { |
|
1844 int32_t ret_val; |
|
1845 uint16_t phy_data; |
|
1846 |
|
1847 DEBUGFUNC("e1000_copper_link_autoneg"); |
|
1848 |
|
1849 /* Perform some bounds checking on the hw->autoneg_advertised |
|
1850 * parameter. If this variable is zero, then set it to the default. |
|
1851 */ |
|
1852 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1853 |
|
1854 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1855 * by the calling code so we set to advertise full capability. |
|
1856 */ |
|
1857 if (hw->autoneg_advertised == 0) |
|
1858 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
|
1859 |
|
1860 /* IFE phy only supports 10/100 */ |
|
1861 if (hw->phy_type == e1000_phy_ife) |
|
1862 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; |
|
1863 |
|
1864 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
|
1865 ret_val = e1000_phy_setup_autoneg(hw); |
|
1866 if (ret_val) { |
|
1867 DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
|
1868 return ret_val; |
|
1869 } |
|
1870 DEBUGOUT("Restarting Auto-Neg\n"); |
|
1871 |
|
1872 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1873 * the Auto Neg Restart bit in the PHY control register. |
|
1874 */ |
|
1875 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
1876 if (ret_val) |
|
1877 return ret_val; |
|
1878 |
|
1879 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1880 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
1881 if (ret_val) |
|
1882 return ret_val; |
|
1883 |
|
1884 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1885 * check at a later time (for example, callback routine). |
|
1886 */ |
|
1887 if (hw->wait_autoneg_complete) { |
|
1888 ret_val = e1000_wait_autoneg(hw); |
|
1889 if (ret_val) { |
|
1890 DEBUGOUT("Error while waiting for autoneg to complete\n"); |
|
1891 return ret_val; |
|
1892 } |
|
1893 } |
|
1894 |
|
1895 hw->get_link_status = TRUE; |
|
1896 |
|
1897 return E1000_SUCCESS; |
|
1898 } |
|
1899 |
|
1900 /****************************************************************************** |
|
1901 * Config the MAC and the PHY after link is up. |
|
1902 * 1) Set up the MAC to the current PHY speed/duplex |
|
1903 * if we are on 82543. If we |
|
1904 * are on newer silicon, we only need to configure |
|
1905 * collision distance in the Transmit Control Register. |
|
1906 * 2) Set up flow control on the MAC to that established with |
|
1907 * the link partner. |
|
1908 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
|
1909 * |
|
1910 * hw - Struct containing variables accessed by shared code |
|
1911 ******************************************************************************/ |
|
1912 static int32_t |
|
1913 e1000_copper_link_postconfig(struct e1000_hw *hw) |
|
1914 { |
|
1915 int32_t ret_val; |
|
1916 DEBUGFUNC("e1000_copper_link_postconfig"); |
|
1917 |
|
1918 if (hw->mac_type >= e1000_82544) { |
|
1919 e1000_config_collision_dist(hw); |
|
1920 } else { |
|
1921 ret_val = e1000_config_mac_to_phy(hw); |
|
1922 if (ret_val) { |
|
1923 DEBUGOUT("Error configuring MAC to PHY settings\n"); |
|
1924 return ret_val; |
|
1925 } |
|
1926 } |
|
1927 ret_val = e1000_config_fc_after_link_up(hw); |
|
1928 if (ret_val) { |
|
1929 DEBUGOUT("Error Configuring Flow Control\n"); |
|
1930 return ret_val; |
|
1931 } |
|
1932 |
|
1933 /* Config DSP to improve Giga link quality */ |
|
1934 if (hw->phy_type == e1000_phy_igp) { |
|
1935 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
|
1936 if (ret_val) { |
|
1937 DEBUGOUT("Error Configuring DSP after link up\n"); |
|
1938 return ret_val; |
|
1939 } |
|
1940 } |
|
1941 |
|
1942 return E1000_SUCCESS; |
|
1943 } |
|
1944 |
|
1945 /****************************************************************************** |
|
1946 * Detects which PHY is present and setup the speed and duplex |
|
1947 * |
|
1948 * hw - Struct containing variables accessed by shared code |
|
1949 ******************************************************************************/ |
|
1950 static int32_t |
|
1951 e1000_setup_copper_link(struct e1000_hw *hw) |
|
1952 { |
|
1953 int32_t ret_val; |
|
1954 uint16_t i; |
|
1955 uint16_t phy_data; |
|
1956 uint16_t reg_data; |
|
1957 |
|
1958 DEBUGFUNC("e1000_setup_copper_link"); |
|
1959 |
|
1960 switch (hw->mac_type) { |
|
1961 case e1000_80003es2lan: |
|
1962 case e1000_ich8lan: |
|
1963 /* Set the mac to wait the maximum time between each |
|
1964 * iteration and increase the max iterations when |
|
1965 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ |
|
1966 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
|
1967 if (ret_val) |
|
1968 return ret_val; |
|
1969 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); |
|
1970 if (ret_val) |
|
1971 return ret_val; |
|
1972 reg_data |= 0x3F; |
|
1973 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); |
|
1974 if (ret_val) |
|
1975 return ret_val; |
|
1976 default: |
|
1977 break; |
|
1978 } |
|
1979 |
|
1980 /* Check if it is a valid PHY and set PHY mode if necessary. */ |
|
1981 ret_val = e1000_copper_link_preconfig(hw); |
|
1982 if (ret_val) |
|
1983 return ret_val; |
|
1984 |
|
1985 switch (hw->mac_type) { |
|
1986 case e1000_80003es2lan: |
|
1987 /* Kumeran registers are written-only */ |
|
1988 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; |
|
1989 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
|
1990 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, |
|
1991 reg_data); |
|
1992 if (ret_val) |
|
1993 return ret_val; |
|
1994 break; |
|
1995 default: |
|
1996 break; |
|
1997 } |
|
1998 |
|
1999 if (hw->phy_type == e1000_phy_igp || |
|
2000 hw->phy_type == e1000_phy_igp_3 || |
|
2001 hw->phy_type == e1000_phy_igp_2) { |
|
2002 ret_val = e1000_copper_link_igp_setup(hw); |
|
2003 if (ret_val) |
|
2004 return ret_val; |
|
2005 } else if (hw->phy_type == e1000_phy_m88) { |
|
2006 ret_val = e1000_copper_link_mgp_setup(hw); |
|
2007 if (ret_val) |
|
2008 return ret_val; |
|
2009 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
2010 ret_val = e1000_copper_link_ggp_setup(hw); |
|
2011 if (ret_val) |
|
2012 return ret_val; |
|
2013 } |
|
2014 |
|
2015 if (hw->autoneg) { |
|
2016 /* Setup autoneg and flow control advertisement |
|
2017 * and perform autonegotiation */ |
|
2018 ret_val = e1000_copper_link_autoneg(hw); |
|
2019 if (ret_val) |
|
2020 return ret_val; |
|
2021 } else { |
|
2022 /* PHY will be set to 10H, 10F, 100H,or 100F |
|
2023 * depending on value from forced_speed_duplex. */ |
|
2024 DEBUGOUT("Forcing speed and duplex\n"); |
|
2025 ret_val = e1000_phy_force_speed_duplex(hw); |
|
2026 if (ret_val) { |
|
2027 DEBUGOUT("Error Forcing Speed and Duplex\n"); |
|
2028 return ret_val; |
|
2029 } |
|
2030 } |
|
2031 |
|
2032 /* Check link status. Wait up to 100 microseconds for link to become |
|
2033 * valid. |
|
2034 */ |
|
2035 for (i = 0; i < 10; i++) { |
|
2036 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2037 if (ret_val) |
|
2038 return ret_val; |
|
2039 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2040 if (ret_val) |
|
2041 return ret_val; |
|
2042 |
|
2043 if (phy_data & MII_SR_LINK_STATUS) { |
|
2044 /* Config the MAC and PHY after link is up */ |
|
2045 ret_val = e1000_copper_link_postconfig(hw); |
|
2046 if (ret_val) |
|
2047 return ret_val; |
|
2048 |
|
2049 DEBUGOUT("Valid link established!!!\n"); |
|
2050 return E1000_SUCCESS; |
|
2051 } |
|
2052 udelay(10); |
|
2053 } |
|
2054 |
|
2055 DEBUGOUT("Unable to establish link!!!\n"); |
|
2056 return E1000_SUCCESS; |
|
2057 } |
|
2058 |
|
2059 /****************************************************************************** |
|
2060 * Configure the MAC-to-PHY interface for 10/100Mbps |
|
2061 * |
|
2062 * hw - Struct containing variables accessed by shared code |
|
2063 ******************************************************************************/ |
|
2064 static int32_t |
|
2065 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) |
|
2066 { |
|
2067 int32_t ret_val = E1000_SUCCESS; |
|
2068 uint32_t tipg; |
|
2069 uint16_t reg_data; |
|
2070 |
|
2071 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); |
|
2072 |
|
2073 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; |
|
2074 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
|
2075 reg_data); |
|
2076 if (ret_val) |
|
2077 return ret_val; |
|
2078 |
|
2079 /* Configure Transmit Inter-Packet Gap */ |
|
2080 tipg = E1000_READ_REG(hw, TIPG); |
|
2081 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
2082 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; |
|
2083 E1000_WRITE_REG(hw, TIPG, tipg); |
|
2084 |
|
2085 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
2086 |
|
2087 if (ret_val) |
|
2088 return ret_val; |
|
2089 |
|
2090 if (duplex == HALF_DUPLEX) |
|
2091 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
|
2092 else |
|
2093 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
2094 |
|
2095 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
2096 |
|
2097 return ret_val; |
|
2098 } |
|
2099 |
|
2100 static int32_t |
|
2101 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) |
|
2102 { |
|
2103 int32_t ret_val = E1000_SUCCESS; |
|
2104 uint16_t reg_data; |
|
2105 uint32_t tipg; |
|
2106 |
|
2107 DEBUGFUNC("e1000_configure_kmrn_for_1000"); |
|
2108 |
|
2109 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; |
|
2110 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
|
2111 reg_data); |
|
2112 if (ret_val) |
|
2113 return ret_val; |
|
2114 |
|
2115 /* Configure Transmit Inter-Packet Gap */ |
|
2116 tipg = E1000_READ_REG(hw, TIPG); |
|
2117 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
2118 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
|
2119 E1000_WRITE_REG(hw, TIPG, tipg); |
|
2120 |
|
2121 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
2122 |
|
2123 if (ret_val) |
|
2124 return ret_val; |
|
2125 |
|
2126 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
2127 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
2128 |
|
2129 return ret_val; |
|
2130 } |
|
2131 |
|
2132 /****************************************************************************** |
|
2133 * Configures PHY autoneg and flow control advertisement settings |
|
2134 * |
|
2135 * hw - Struct containing variables accessed by shared code |
|
2136 ******************************************************************************/ |
|
2137 int32_t |
|
2138 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
2139 { |
|
2140 int32_t ret_val; |
|
2141 uint16_t mii_autoneg_adv_reg; |
|
2142 uint16_t mii_1000t_ctrl_reg; |
|
2143 |
|
2144 DEBUGFUNC("e1000_phy_setup_autoneg"); |
|
2145 |
|
2146 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
2147 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
2148 if (ret_val) |
|
2149 return ret_val; |
|
2150 |
|
2151 if (hw->phy_type != e1000_phy_ife) { |
|
2152 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
2153 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
2154 if (ret_val) |
|
2155 return ret_val; |
|
2156 } else |
|
2157 mii_1000t_ctrl_reg=0; |
|
2158 |
|
2159 /* Need to parse both autoneg_advertised and fc and set up |
|
2160 * the appropriate PHY registers. First we will parse for |
|
2161 * autoneg_advertised software override. Since we can advertise |
|
2162 * a plethora of combinations, we need to check each bit |
|
2163 * individually. |
|
2164 */ |
|
2165 |
|
2166 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
2167 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
2168 * the 1000Base-T Control Register (Address 9). |
|
2169 */ |
|
2170 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
|
2171 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
|
2172 |
|
2173 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
|
2174 |
|
2175 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
2176 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
|
2177 DEBUGOUT("Advertise 10mb Half duplex\n"); |
|
2178 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
2179 } |
|
2180 |
|
2181 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
2182 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
|
2183 DEBUGOUT("Advertise 10mb Full duplex\n"); |
|
2184 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
2185 } |
|
2186 |
|
2187 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
2188 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
|
2189 DEBUGOUT("Advertise 100mb Half duplex\n"); |
|
2190 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
2191 } |
|
2192 |
|
2193 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
2194 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
|
2195 DEBUGOUT("Advertise 100mb Full duplex\n"); |
|
2196 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
2197 } |
|
2198 |
|
2199 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
2200 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
|
2201 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
|
2202 } |
|
2203 |
|
2204 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
2205 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
2206 DEBUGOUT("Advertise 1000mb Full duplex\n"); |
|
2207 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
2208 if (hw->phy_type == e1000_phy_ife) { |
|
2209 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); |
|
2210 } |
|
2211 } |
|
2212 |
|
2213 /* Check for a software override of the flow control settings, and |
|
2214 * setup the PHY advertisement registers accordingly. If |
|
2215 * auto-negotiation is enabled, then software will have to set the |
|
2216 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
2217 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
|
2218 * |
|
2219 * The possible values of the "fc" parameter are: |
|
2220 * 0: Flow control is completely disabled |
|
2221 * 1: Rx flow control is enabled (we can receive pause frames |
|
2222 * but not send pause frames). |
|
2223 * 2: Tx flow control is enabled (we can send pause frames |
|
2224 * but we do not support receiving pause frames). |
|
2225 * 3: Both Rx and TX flow control (symmetric) are enabled. |
|
2226 * other: No software override. The flow control configuration |
|
2227 * in the EEPROM is used. |
|
2228 */ |
|
2229 switch (hw->fc) { |
|
2230 case E1000_FC_NONE: /* 0 */ |
|
2231 /* Flow control (RX & TX) is completely disabled by a |
|
2232 * software over-ride. |
|
2233 */ |
|
2234 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2235 break; |
|
2236 case E1000_FC_RX_PAUSE: /* 1 */ |
|
2237 /* RX Flow control is enabled, and TX Flow control is |
|
2238 * disabled, by a software over-ride. |
|
2239 */ |
|
2240 /* Since there really isn't a way to advertise that we are |
|
2241 * capable of RX Pause ONLY, we will advertise that we |
|
2242 * support both symmetric and asymmetric RX PAUSE. Later |
|
2243 * (in e1000_config_fc_after_link_up) we will disable the |
|
2244 *hw's ability to send PAUSE frames. |
|
2245 */ |
|
2246 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2247 break; |
|
2248 case E1000_FC_TX_PAUSE: /* 2 */ |
|
2249 /* TX Flow control is enabled, and RX Flow control is |
|
2250 * disabled, by a software over-ride. |
|
2251 */ |
|
2252 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
2253 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
2254 break; |
|
2255 case E1000_FC_FULL: /* 3 */ |
|
2256 /* Flow control (both RX and TX) is enabled by a software |
|
2257 * over-ride. |
|
2258 */ |
|
2259 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
2260 break; |
|
2261 default: |
|
2262 DEBUGOUT("Flow control param set incorrectly\n"); |
|
2263 return -E1000_ERR_CONFIG; |
|
2264 } |
|
2265 |
|
2266 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
2267 if (ret_val) |
|
2268 return ret_val; |
|
2269 |
|
2270 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
2271 |
|
2272 if (hw->phy_type != e1000_phy_ife) { |
|
2273 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
|
2274 if (ret_val) |
|
2275 return ret_val; |
|
2276 } |
|
2277 |
|
2278 return E1000_SUCCESS; |
|
2279 } |
|
2280 |
|
2281 /****************************************************************************** |
|
2282 * Force PHY speed and duplex settings to hw->forced_speed_duplex |
|
2283 * |
|
2284 * hw - Struct containing variables accessed by shared code |
|
2285 ******************************************************************************/ |
|
2286 static int32_t |
|
2287 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
2288 { |
|
2289 uint32_t ctrl; |
|
2290 int32_t ret_val; |
|
2291 uint16_t mii_ctrl_reg; |
|
2292 uint16_t mii_status_reg; |
|
2293 uint16_t phy_data; |
|
2294 uint16_t i; |
|
2295 |
|
2296 DEBUGFUNC("e1000_phy_force_speed_duplex"); |
|
2297 |
|
2298 /* Turn off Flow control if we are forcing speed and duplex. */ |
|
2299 hw->fc = E1000_FC_NONE; |
|
2300 |
|
2301 DEBUGOUT1("hw->fc = %d\n", hw->fc); |
|
2302 |
|
2303 /* Read the Device Control Register. */ |
|
2304 ctrl = E1000_READ_REG(hw, CTRL); |
|
2305 |
|
2306 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
|
2307 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
2308 ctrl &= ~(DEVICE_SPEED_MASK); |
|
2309 |
|
2310 /* Clear the Auto Speed Detect Enable bit. */ |
|
2311 ctrl &= ~E1000_CTRL_ASDE; |
|
2312 |
|
2313 /* Read the MII Control Register. */ |
|
2314 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
|
2315 if (ret_val) |
|
2316 return ret_val; |
|
2317 |
|
2318 /* We need to disable autoneg in order to force link and duplex. */ |
|
2319 |
|
2320 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
|
2321 |
|
2322 /* Are we forcing Full or Half Duplex? */ |
|
2323 if (hw->forced_speed_duplex == e1000_100_full || |
|
2324 hw->forced_speed_duplex == e1000_10_full) { |
|
2325 /* We want to force full duplex so we SET the full duplex bits in the |
|
2326 * Device and MII Control Registers. |
|
2327 */ |
|
2328 ctrl |= E1000_CTRL_FD; |
|
2329 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
|
2330 DEBUGOUT("Full Duplex\n"); |
|
2331 } else { |
|
2332 /* We want to force half duplex so we CLEAR the full duplex bits in |
|
2333 * the Device and MII Control Registers. |
|
2334 */ |
|
2335 ctrl &= ~E1000_CTRL_FD; |
|
2336 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
|
2337 DEBUGOUT("Half Duplex\n"); |
|
2338 } |
|
2339 |
|
2340 /* Are we forcing 100Mbps??? */ |
|
2341 if (hw->forced_speed_duplex == e1000_100_full || |
|
2342 hw->forced_speed_duplex == e1000_100_half) { |
|
2343 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
|
2344 ctrl |= E1000_CTRL_SPD_100; |
|
2345 mii_ctrl_reg |= MII_CR_SPEED_100; |
|
2346 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
2347 DEBUGOUT("Forcing 100mb "); |
|
2348 } else { |
|
2349 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
|
2350 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
2351 mii_ctrl_reg |= MII_CR_SPEED_10; |
|
2352 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
2353 DEBUGOUT("Forcing 10mb "); |
|
2354 } |
|
2355 |
|
2356 e1000_config_collision_dist(hw); |
|
2357 |
|
2358 /* Write the configured values back to the Device Control Reg. */ |
|
2359 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2360 |
|
2361 if ((hw->phy_type == e1000_phy_m88) || |
|
2362 (hw->phy_type == e1000_phy_gg82563)) { |
|
2363 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
2364 if (ret_val) |
|
2365 return ret_val; |
|
2366 |
|
2367 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
2368 * forced whenever speed are duplex are forced. |
|
2369 */ |
|
2370 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
2371 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
2372 if (ret_val) |
|
2373 return ret_val; |
|
2374 |
|
2375 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
|
2376 |
|
2377 /* Need to reset the PHY or these changes will be ignored */ |
|
2378 mii_ctrl_reg |= MII_CR_RESET; |
|
2379 |
|
2380 /* Disable MDI-X support for 10/100 */ |
|
2381 } else if (hw->phy_type == e1000_phy_ife) { |
|
2382 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
|
2383 if (ret_val) |
|
2384 return ret_val; |
|
2385 |
|
2386 phy_data &= ~IFE_PMC_AUTO_MDIX; |
|
2387 phy_data &= ~IFE_PMC_FORCE_MDIX; |
|
2388 |
|
2389 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); |
|
2390 if (ret_val) |
|
2391 return ret_val; |
|
2392 |
|
2393 } else { |
|
2394 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
2395 * forced whenever speed or duplex are forced. |
|
2396 */ |
|
2397 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
2398 if (ret_val) |
|
2399 return ret_val; |
|
2400 |
|
2401 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
2402 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
2403 |
|
2404 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
2405 if (ret_val) |
|
2406 return ret_val; |
|
2407 } |
|
2408 |
|
2409 /* Write back the modified PHY MII control register. */ |
|
2410 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
|
2411 if (ret_val) |
|
2412 return ret_val; |
|
2413 |
|
2414 udelay(1); |
|
2415 |
|
2416 /* The wait_autoneg_complete flag may be a little misleading here. |
|
2417 * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
|
2418 * But we do want to delay for a period while forcing only so we |
|
2419 * don't generate false No Link messages. So we will wait here |
|
2420 * only if the user has set wait_autoneg_complete to 1, which is |
|
2421 * the default. |
|
2422 */ |
|
2423 if (hw->wait_autoneg_complete) { |
|
2424 /* We will wait for autoneg to complete. */ |
|
2425 DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
|
2426 mii_status_reg = 0; |
|
2427 |
|
2428 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
2429 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
2430 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
2431 * to be set. |
|
2432 */ |
|
2433 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2434 if (ret_val) |
|
2435 return ret_val; |
|
2436 |
|
2437 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2438 if (ret_val) |
|
2439 return ret_val; |
|
2440 |
|
2441 if (mii_status_reg & MII_SR_LINK_STATUS) break; |
|
2442 msleep(100); |
|
2443 } |
|
2444 if ((i == 0) && |
|
2445 ((hw->phy_type == e1000_phy_m88) || |
|
2446 (hw->phy_type == e1000_phy_gg82563))) { |
|
2447 /* We didn't get link. Reset the DSP and wait again for link. */ |
|
2448 ret_val = e1000_phy_reset_dsp(hw); |
|
2449 if (ret_val) { |
|
2450 DEBUGOUT("Error Resetting PHY DSP\n"); |
|
2451 return ret_val; |
|
2452 } |
|
2453 } |
|
2454 /* This loop will early-out if the link condition has been met. */ |
|
2455 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
2456 if (mii_status_reg & MII_SR_LINK_STATUS) break; |
|
2457 msleep(100); |
|
2458 /* Read the MII Status Register and wait for Auto-Neg Complete bit |
|
2459 * to be set. |
|
2460 */ |
|
2461 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2462 if (ret_val) |
|
2463 return ret_val; |
|
2464 |
|
2465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2466 if (ret_val) |
|
2467 return ret_val; |
|
2468 } |
|
2469 } |
|
2470 |
|
2471 if (hw->phy_type == e1000_phy_m88) { |
|
2472 /* Because we reset the PHY above, we need to re-force TX_CLK in the |
|
2473 * Extended PHY Specific Control Register to 25MHz clock. This value |
|
2474 * defaults back to a 2.5MHz clock when the PHY is reset. |
|
2475 */ |
|
2476 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
2477 if (ret_val) |
|
2478 return ret_val; |
|
2479 |
|
2480 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
2481 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
2482 if (ret_val) |
|
2483 return ret_val; |
|
2484 |
|
2485 /* In addition, because of the s/w reset above, we need to enable CRS on |
|
2486 * TX. This must be set for both full and half duplex operation. |
|
2487 */ |
|
2488 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
2489 if (ret_val) |
|
2490 return ret_val; |
|
2491 |
|
2492 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
2493 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
2494 if (ret_val) |
|
2495 return ret_val; |
|
2496 |
|
2497 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
|
2498 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || |
|
2499 hw->forced_speed_duplex == e1000_10_half)) { |
|
2500 ret_val = e1000_polarity_reversal_workaround(hw); |
|
2501 if (ret_val) |
|
2502 return ret_val; |
|
2503 } |
|
2504 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
2505 /* The TX_CLK of the Extended PHY Specific Control Register defaults |
|
2506 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if |
|
2507 * we're not in a forced 10/duplex configuration. */ |
|
2508 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); |
|
2509 if (ret_val) |
|
2510 return ret_val; |
|
2511 |
|
2512 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; |
|
2513 if ((hw->forced_speed_duplex == e1000_10_full) || |
|
2514 (hw->forced_speed_duplex == e1000_10_half)) |
|
2515 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; |
|
2516 else |
|
2517 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; |
|
2518 |
|
2519 /* Also due to the reset, we need to enable CRS on Tx. */ |
|
2520 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
2521 |
|
2522 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); |
|
2523 if (ret_val) |
|
2524 return ret_val; |
|
2525 } |
|
2526 return E1000_SUCCESS; |
|
2527 } |
|
2528 |
|
2529 /****************************************************************************** |
|
2530 * Sets the collision distance in the Transmit Control register |
|
2531 * |
|
2532 * hw - Struct containing variables accessed by shared code |
|
2533 * |
|
2534 * Link should have been established previously. Reads the speed and duplex |
|
2535 * information from the Device Status register. |
|
2536 ******************************************************************************/ |
|
2537 void |
|
2538 e1000_config_collision_dist(struct e1000_hw *hw) |
|
2539 { |
|
2540 uint32_t tctl, coll_dist; |
|
2541 |
|
2542 DEBUGFUNC("e1000_config_collision_dist"); |
|
2543 |
|
2544 if (hw->mac_type < e1000_82543) |
|
2545 coll_dist = E1000_COLLISION_DISTANCE_82542; |
|
2546 else |
|
2547 coll_dist = E1000_COLLISION_DISTANCE; |
|
2548 |
|
2549 tctl = E1000_READ_REG(hw, TCTL); |
|
2550 |
|
2551 tctl &= ~E1000_TCTL_COLD; |
|
2552 tctl |= coll_dist << E1000_COLD_SHIFT; |
|
2553 |
|
2554 E1000_WRITE_REG(hw, TCTL, tctl); |
|
2555 E1000_WRITE_FLUSH(hw); |
|
2556 } |
|
2557 |
|
2558 /****************************************************************************** |
|
2559 * Sets MAC speed and duplex settings to reflect the those in the PHY |
|
2560 * |
|
2561 * hw - Struct containing variables accessed by shared code |
|
2562 * mii_reg - data to write to the MII control register |
|
2563 * |
|
2564 * The contents of the PHY register containing the needed information need to |
|
2565 * be passed in. |
|
2566 ******************************************************************************/ |
|
2567 static int32_t |
|
2568 e1000_config_mac_to_phy(struct e1000_hw *hw) |
|
2569 { |
|
2570 uint32_t ctrl; |
|
2571 int32_t ret_val; |
|
2572 uint16_t phy_data; |
|
2573 |
|
2574 DEBUGFUNC("e1000_config_mac_to_phy"); |
|
2575 |
|
2576 /* 82544 or newer MAC, Auto Speed Detection takes care of |
|
2577 * MAC speed/duplex configuration.*/ |
|
2578 if (hw->mac_type >= e1000_82544) |
|
2579 return E1000_SUCCESS; |
|
2580 |
|
2581 /* Read the Device Control Register and set the bits to Force Speed |
|
2582 * and Duplex. |
|
2583 */ |
|
2584 ctrl = E1000_READ_REG(hw, CTRL); |
|
2585 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
2586 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
|
2587 |
|
2588 /* Set up duplex in the Device Control and Transmit Control |
|
2589 * registers depending on negotiated values. |
|
2590 */ |
|
2591 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
2592 if (ret_val) |
|
2593 return ret_val; |
|
2594 |
|
2595 if (phy_data & M88E1000_PSSR_DPLX) |
|
2596 ctrl |= E1000_CTRL_FD; |
|
2597 else |
|
2598 ctrl &= ~E1000_CTRL_FD; |
|
2599 |
|
2600 e1000_config_collision_dist(hw); |
|
2601 |
|
2602 /* Set up speed in the Device Control register depending on |
|
2603 * negotiated values. |
|
2604 */ |
|
2605 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
|
2606 ctrl |= E1000_CTRL_SPD_1000; |
|
2607 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
|
2608 ctrl |= E1000_CTRL_SPD_100; |
|
2609 |
|
2610 /* Write the configured values back to the Device Control Reg. */ |
|
2611 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2612 return E1000_SUCCESS; |
|
2613 } |
|
2614 |
|
2615 /****************************************************************************** |
|
2616 * Forces the MAC's flow control settings. |
|
2617 * |
|
2618 * hw - Struct containing variables accessed by shared code |
|
2619 * |
|
2620 * Sets the TFCE and RFCE bits in the device control register to reflect |
|
2621 * the adapter settings. TFCE and RFCE need to be explicitly set by |
|
2622 * software when a Copper PHY is used because autonegotiation is managed |
|
2623 * by the PHY rather than the MAC. Software must also configure these |
|
2624 * bits when link is forced on a fiber connection. |
|
2625 *****************************************************************************/ |
|
2626 int32_t |
|
2627 e1000_force_mac_fc(struct e1000_hw *hw) |
|
2628 { |
|
2629 uint32_t ctrl; |
|
2630 |
|
2631 DEBUGFUNC("e1000_force_mac_fc"); |
|
2632 |
|
2633 /* Get the current configuration of the Device Control Register */ |
|
2634 ctrl = E1000_READ_REG(hw, CTRL); |
|
2635 |
|
2636 /* Because we didn't get link via the internal auto-negotiation |
|
2637 * mechanism (we either forced link or we got link via PHY |
|
2638 * auto-neg), we have to manually enable/disable transmit an |
|
2639 * receive flow control. |
|
2640 * |
|
2641 * The "Case" statement below enables/disable flow control |
|
2642 * according to the "hw->fc" parameter. |
|
2643 * |
|
2644 * The possible values of the "fc" parameter are: |
|
2645 * 0: Flow control is completely disabled |
|
2646 * 1: Rx flow control is enabled (we can receive pause |
|
2647 * frames but not send pause frames). |
|
2648 * 2: Tx flow control is enabled (we can send pause frames |
|
2649 * frames but we do not receive pause frames). |
|
2650 * 3: Both Rx and TX flow control (symmetric) is enabled. |
|
2651 * other: No other values should be possible at this point. |
|
2652 */ |
|
2653 |
|
2654 switch (hw->fc) { |
|
2655 case E1000_FC_NONE: |
|
2656 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
|
2657 break; |
|
2658 case E1000_FC_RX_PAUSE: |
|
2659 ctrl &= (~E1000_CTRL_TFCE); |
|
2660 ctrl |= E1000_CTRL_RFCE; |
|
2661 break; |
|
2662 case E1000_FC_TX_PAUSE: |
|
2663 ctrl &= (~E1000_CTRL_RFCE); |
|
2664 ctrl |= E1000_CTRL_TFCE; |
|
2665 break; |
|
2666 case E1000_FC_FULL: |
|
2667 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
|
2668 break; |
|
2669 default: |
|
2670 DEBUGOUT("Flow control param set incorrectly\n"); |
|
2671 return -E1000_ERR_CONFIG; |
|
2672 } |
|
2673 |
|
2674 /* Disable TX Flow Control for 82542 (rev 2.0) */ |
|
2675 if (hw->mac_type == e1000_82542_rev2_0) |
|
2676 ctrl &= (~E1000_CTRL_TFCE); |
|
2677 |
|
2678 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
2679 return E1000_SUCCESS; |
|
2680 } |
|
2681 |
|
2682 /****************************************************************************** |
|
2683 * Configures flow control settings after link is established |
|
2684 * |
|
2685 * hw - Struct containing variables accessed by shared code |
|
2686 * |
|
2687 * Should be called immediately after a valid link has been established. |
|
2688 * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
|
2689 * and autonegotiation is enabled, the MAC flow control settings will be set |
|
2690 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
|
2691 * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
|
2692 *****************************************************************************/ |
|
2693 static int32_t |
|
2694 e1000_config_fc_after_link_up(struct e1000_hw *hw) |
|
2695 { |
|
2696 int32_t ret_val; |
|
2697 uint16_t mii_status_reg; |
|
2698 uint16_t mii_nway_adv_reg; |
|
2699 uint16_t mii_nway_lp_ability_reg; |
|
2700 uint16_t speed; |
|
2701 uint16_t duplex; |
|
2702 |
|
2703 DEBUGFUNC("e1000_config_fc_after_link_up"); |
|
2704 |
|
2705 /* Check for the case where we have fiber media and auto-neg failed |
|
2706 * so we had to force link. In this case, we need to force the |
|
2707 * configuration of the MAC to match the "fc" parameter. |
|
2708 */ |
|
2709 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
|
2710 ((hw->media_type == e1000_media_type_internal_serdes) && |
|
2711 (hw->autoneg_failed)) || |
|
2712 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { |
|
2713 ret_val = e1000_force_mac_fc(hw); |
|
2714 if (ret_val) { |
|
2715 DEBUGOUT("Error forcing flow control settings\n"); |
|
2716 return ret_val; |
|
2717 } |
|
2718 } |
|
2719 |
|
2720 /* Check for the case where we have copper media and auto-neg is |
|
2721 * enabled. In this case, we need to check and see if Auto-Neg |
|
2722 * has completed, and if so, how the PHY and link partner has |
|
2723 * flow control configured. |
|
2724 */ |
|
2725 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
|
2726 /* Read the MII Status Register and check to see if AutoNeg |
|
2727 * has completed. We read this twice because this reg has |
|
2728 * some "sticky" (latched) bits. |
|
2729 */ |
|
2730 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2731 if (ret_val) |
|
2732 return ret_val; |
|
2733 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
2734 if (ret_val) |
|
2735 return ret_val; |
|
2736 |
|
2737 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
|
2738 /* The AutoNeg process has completed, so we now need to |
|
2739 * read both the Auto Negotiation Advertisement Register |
|
2740 * (Address 4) and the Auto_Negotiation Base Page Ability |
|
2741 * Register (Address 5) to determine how flow control was |
|
2742 * negotiated. |
|
2743 */ |
|
2744 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
|
2745 &mii_nway_adv_reg); |
|
2746 if (ret_val) |
|
2747 return ret_val; |
|
2748 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
|
2749 &mii_nway_lp_ability_reg); |
|
2750 if (ret_val) |
|
2751 return ret_val; |
|
2752 |
|
2753 /* Two bits in the Auto Negotiation Advertisement Register |
|
2754 * (Address 4) and two bits in the Auto Negotiation Base |
|
2755 * Page Ability Register (Address 5) determine flow control |
|
2756 * for both the PHY and the link partner. The following |
|
2757 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
|
2758 * 1999, describes these PAUSE resolution bits and how flow |
|
2759 * control is determined based upon these settings. |
|
2760 * NOTE: DC = Don't Care |
|
2761 * |
|
2762 * LOCAL DEVICE | LINK PARTNER |
|
2763 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
|
2764 *-------|---------|-------|---------|-------------------- |
|
2765 * 0 | 0 | DC | DC | E1000_FC_NONE |
|
2766 * 0 | 1 | 0 | DC | E1000_FC_NONE |
|
2767 * 0 | 1 | 1 | 0 | E1000_FC_NONE |
|
2768 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2769 * 1 | 0 | 0 | DC | E1000_FC_NONE |
|
2770 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2771 * 1 | 1 | 0 | 0 | E1000_FC_NONE |
|
2772 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2773 * |
|
2774 */ |
|
2775 /* Are both PAUSE bits set to 1? If so, this implies |
|
2776 * Symmetric Flow Control is enabled at both ends. The |
|
2777 * ASM_DIR bits are irrelevant per the spec. |
|
2778 * |
|
2779 * For Symmetric Flow Control: |
|
2780 * |
|
2781 * LOCAL DEVICE | LINK PARTNER |
|
2782 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2783 *-------|---------|-------|---------|-------------------- |
|
2784 * 1 | DC | 1 | DC | E1000_FC_FULL |
|
2785 * |
|
2786 */ |
|
2787 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2788 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
|
2789 /* Now we need to check if the user selected RX ONLY |
|
2790 * of pause frames. In this case, we had to advertise |
|
2791 * FULL flow control because we could not advertise RX |
|
2792 * ONLY. Hence, we must now check to see if we need to |
|
2793 * turn OFF the TRANSMISSION of PAUSE frames. |
|
2794 */ |
|
2795 if (hw->original_fc == E1000_FC_FULL) { |
|
2796 hw->fc = E1000_FC_FULL; |
|
2797 DEBUGOUT("Flow Control = FULL.\n"); |
|
2798 } else { |
|
2799 hw->fc = E1000_FC_RX_PAUSE; |
|
2800 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2801 } |
|
2802 } |
|
2803 /* For receiving PAUSE frames ONLY. |
|
2804 * |
|
2805 * LOCAL DEVICE | LINK PARTNER |
|
2806 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2807 *-------|---------|-------|---------|-------------------- |
|
2808 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
|
2809 * |
|
2810 */ |
|
2811 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2812 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2813 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2814 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
2815 hw->fc = E1000_FC_TX_PAUSE; |
|
2816 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
|
2817 } |
|
2818 /* For transmitting PAUSE frames ONLY. |
|
2819 * |
|
2820 * LOCAL DEVICE | LINK PARTNER |
|
2821 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
2822 *-------|---------|-------|---------|-------------------- |
|
2823 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
|
2824 * |
|
2825 */ |
|
2826 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
2827 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
2828 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
2829 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
2830 hw->fc = E1000_FC_RX_PAUSE; |
|
2831 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2832 } |
|
2833 /* Per the IEEE spec, at this point flow control should be |
|
2834 * disabled. However, we want to consider that we could |
|
2835 * be connected to a legacy switch that doesn't advertise |
|
2836 * desired flow control, but can be forced on the link |
|
2837 * partner. So if we advertised no flow control, that is |
|
2838 * what we will resolve to. If we advertised some kind of |
|
2839 * receive capability (Rx Pause Only or Full Flow Control) |
|
2840 * and the link partner advertised none, we will configure |
|
2841 * ourselves to enable Rx Flow Control only. We can do |
|
2842 * this safely for two reasons: If the link partner really |
|
2843 * didn't want flow control enabled, and we enable Rx, no |
|
2844 * harm done since we won't be receiving any PAUSE frames |
|
2845 * anyway. If the intent on the link partner was to have |
|
2846 * flow control enabled, then by us enabling RX only, we |
|
2847 * can at least receive pause frames and process them. |
|
2848 * This is a good idea because in most cases, since we are |
|
2849 * predominantly a server NIC, more times than not we will |
|
2850 * be asked to delay transmission of packets than asking |
|
2851 * our link partner to pause transmission of frames. |
|
2852 */ |
|
2853 else if ((hw->original_fc == E1000_FC_NONE || |
|
2854 hw->original_fc == E1000_FC_TX_PAUSE) || |
|
2855 hw->fc_strict_ieee) { |
|
2856 hw->fc = E1000_FC_NONE; |
|
2857 DEBUGOUT("Flow Control = NONE.\n"); |
|
2858 } else { |
|
2859 hw->fc = E1000_FC_RX_PAUSE; |
|
2860 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
|
2861 } |
|
2862 |
|
2863 /* Now we need to do one last check... If we auto- |
|
2864 * negotiated to HALF DUPLEX, flow control should not be |
|
2865 * enabled per IEEE 802.3 spec. |
|
2866 */ |
|
2867 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
2868 if (ret_val) { |
|
2869 DEBUGOUT("Error getting link speed and duplex\n"); |
|
2870 return ret_val; |
|
2871 } |
|
2872 |
|
2873 if (duplex == HALF_DUPLEX) |
|
2874 hw->fc = E1000_FC_NONE; |
|
2875 |
|
2876 /* Now we call a subroutine to actually force the MAC |
|
2877 * controller to use the correct flow control settings. |
|
2878 */ |
|
2879 ret_val = e1000_force_mac_fc(hw); |
|
2880 if (ret_val) { |
|
2881 DEBUGOUT("Error forcing flow control settings\n"); |
|
2882 return ret_val; |
|
2883 } |
|
2884 } else { |
|
2885 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
|
2886 } |
|
2887 } |
|
2888 return E1000_SUCCESS; |
|
2889 } |
|
2890 |
|
2891 /****************************************************************************** |
|
2892 * Checks to see if the link status of the hardware has changed. |
|
2893 * |
|
2894 * hw - Struct containing variables accessed by shared code |
|
2895 * |
|
2896 * Called by any function that needs to check the link status of the adapter. |
|
2897 *****************************************************************************/ |
|
2898 int32_t |
|
2899 e1000_check_for_link(struct e1000_hw *hw) |
|
2900 { |
|
2901 uint32_t rxcw = 0; |
|
2902 uint32_t ctrl; |
|
2903 uint32_t status; |
|
2904 uint32_t rctl; |
|
2905 uint32_t icr; |
|
2906 uint32_t signal = 0; |
|
2907 int32_t ret_val; |
|
2908 uint16_t phy_data; |
|
2909 |
|
2910 DEBUGFUNC("e1000_check_for_link"); |
|
2911 |
|
2912 ctrl = E1000_READ_REG(hw, CTRL); |
|
2913 status = E1000_READ_REG(hw, STATUS); |
|
2914 |
|
2915 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
|
2916 * set when the optics detect a signal. On older adapters, it will be |
|
2917 * cleared when there is a signal. This applies to fiber media only. |
|
2918 */ |
|
2919 if ((hw->media_type == e1000_media_type_fiber) || |
|
2920 (hw->media_type == e1000_media_type_internal_serdes)) { |
|
2921 rxcw = E1000_READ_REG(hw, RXCW); |
|
2922 |
|
2923 if (hw->media_type == e1000_media_type_fiber) { |
|
2924 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
|
2925 if (status & E1000_STATUS_LU) |
|
2926 hw->get_link_status = FALSE; |
|
2927 } |
|
2928 } |
|
2929 |
|
2930 /* If we have a copper PHY then we only want to go out to the PHY |
|
2931 * registers to see if Auto-Neg has completed and/or if our link |
|
2932 * status has changed. The get_link_status flag will be set if we |
|
2933 * receive a Link Status Change interrupt or we have Rx Sequence |
|
2934 * Errors. |
|
2935 */ |
|
2936 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
|
2937 /* First we want to see if the MII Status Register reports |
|
2938 * link. If so, then we want to get the current speed/duplex |
|
2939 * of the PHY. |
|
2940 * Read the register twice since the link bit is sticky. |
|
2941 */ |
|
2942 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2943 if (ret_val) |
|
2944 return ret_val; |
|
2945 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
2946 if (ret_val) |
|
2947 return ret_val; |
|
2948 |
|
2949 if (phy_data & MII_SR_LINK_STATUS) { |
|
2950 hw->get_link_status = FALSE; |
|
2951 /* Check if there was DownShift, must be checked immediately after |
|
2952 * link-up */ |
|
2953 e1000_check_downshift(hw); |
|
2954 |
|
2955 /* If we are on 82544 or 82543 silicon and speed/duplex |
|
2956 * are forced to 10H or 10F, then we will implement the polarity |
|
2957 * reversal workaround. We disable interrupts first, and upon |
|
2958 * returning, place the devices interrupt state to its previous |
|
2959 * value except for the link status change interrupt which will |
|
2960 * happen due to the execution of this workaround. |
|
2961 */ |
|
2962 |
|
2963 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
|
2964 (!hw->autoneg) && |
|
2965 (hw->forced_speed_duplex == e1000_10_full || |
|
2966 hw->forced_speed_duplex == e1000_10_half)) { |
|
2967 E1000_WRITE_REG(hw, IMC, 0xffffffff); |
|
2968 ret_val = e1000_polarity_reversal_workaround(hw); |
|
2969 icr = E1000_READ_REG(hw, ICR); |
|
2970 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); |
|
2971 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); |
|
2972 } |
|
2973 |
|
2974 } else { |
|
2975 /* No link detected */ |
|
2976 e1000_config_dsp_after_link_change(hw, FALSE); |
|
2977 return 0; |
|
2978 } |
|
2979 |
|
2980 /* If we are forcing speed/duplex, then we simply return since |
|
2981 * we have already determined whether we have link or not. |
|
2982 */ |
|
2983 if (!hw->autoneg) return -E1000_ERR_CONFIG; |
|
2984 |
|
2985 /* optimize the dsp settings for the igp phy */ |
|
2986 e1000_config_dsp_after_link_change(hw, TRUE); |
|
2987 |
|
2988 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
|
2989 * have Si on board that is 82544 or newer, Auto |
|
2990 * Speed Detection takes care of MAC speed/duplex |
|
2991 * configuration. So we only need to configure Collision |
|
2992 * Distance in the MAC. Otherwise, we need to force |
|
2993 * speed/duplex on the MAC to the current PHY speed/duplex |
|
2994 * settings. |
|
2995 */ |
|
2996 if (hw->mac_type >= e1000_82544) |
|
2997 e1000_config_collision_dist(hw); |
|
2998 else { |
|
2999 ret_val = e1000_config_mac_to_phy(hw); |
|
3000 if (ret_val) { |
|
3001 DEBUGOUT("Error configuring MAC to PHY settings\n"); |
|
3002 return ret_val; |
|
3003 } |
|
3004 } |
|
3005 |
|
3006 /* Configure Flow Control now that Auto-Neg has completed. First, we |
|
3007 * need to restore the desired flow control settings because we may |
|
3008 * have had to re-autoneg with a different link partner. |
|
3009 */ |
|
3010 ret_val = e1000_config_fc_after_link_up(hw); |
|
3011 if (ret_val) { |
|
3012 DEBUGOUT("Error configuring flow control\n"); |
|
3013 return ret_val; |
|
3014 } |
|
3015 |
|
3016 /* At this point we know that we are on copper and we have |
|
3017 * auto-negotiated link. These are conditions for checking the link |
|
3018 * partner capability register. We use the link speed to determine if |
|
3019 * TBI compatibility needs to be turned on or off. If the link is not |
|
3020 * at gigabit speed, then TBI compatibility is not needed. If we are |
|
3021 * at gigabit speed, we turn on TBI compatibility. |
|
3022 */ |
|
3023 if (hw->tbi_compatibility_en) { |
|
3024 uint16_t speed, duplex; |
|
3025 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
3026 if (ret_val) { |
|
3027 DEBUGOUT("Error getting link speed and duplex\n"); |
|
3028 return ret_val; |
|
3029 } |
|
3030 if (speed != SPEED_1000) { |
|
3031 /* If link speed is not set to gigabit speed, we do not need |
|
3032 * to enable TBI compatibility. |
|
3033 */ |
|
3034 if (hw->tbi_compatibility_on) { |
|
3035 /* If we previously were in the mode, turn it off. */ |
|
3036 rctl = E1000_READ_REG(hw, RCTL); |
|
3037 rctl &= ~E1000_RCTL_SBP; |
|
3038 E1000_WRITE_REG(hw, RCTL, rctl); |
|
3039 hw->tbi_compatibility_on = FALSE; |
|
3040 } |
|
3041 } else { |
|
3042 /* If TBI compatibility is was previously off, turn it on. For |
|
3043 * compatibility with a TBI link partner, we will store bad |
|
3044 * packets. Some frames have an additional byte on the end and |
|
3045 * will look like CRC errors to to the hardware. |
|
3046 */ |
|
3047 if (!hw->tbi_compatibility_on) { |
|
3048 hw->tbi_compatibility_on = TRUE; |
|
3049 rctl = E1000_READ_REG(hw, RCTL); |
|
3050 rctl |= E1000_RCTL_SBP; |
|
3051 E1000_WRITE_REG(hw, RCTL, rctl); |
|
3052 } |
|
3053 } |
|
3054 } |
|
3055 } |
|
3056 /* If we don't have link (auto-negotiation failed or link partner cannot |
|
3057 * auto-negotiate), the cable is plugged in (we have signal), and our |
|
3058 * link partner is not trying to auto-negotiate with us (we are receiving |
|
3059 * idles or data), we need to force link up. We also need to give |
|
3060 * auto-negotiation time to complete, in case the cable was just plugged |
|
3061 * in. The autoneg_failed flag does this. |
|
3062 */ |
|
3063 else if ((((hw->media_type == e1000_media_type_fiber) && |
|
3064 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
|
3065 (hw->media_type == e1000_media_type_internal_serdes)) && |
|
3066 (!(status & E1000_STATUS_LU)) && |
|
3067 (!(rxcw & E1000_RXCW_C))) { |
|
3068 if (hw->autoneg_failed == 0) { |
|
3069 hw->autoneg_failed = 1; |
|
3070 return 0; |
|
3071 } |
|
3072 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
|
3073 |
|
3074 /* Disable auto-negotiation in the TXCW register */ |
|
3075 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
|
3076 |
|
3077 /* Force link-up and also force full-duplex. */ |
|
3078 ctrl = E1000_READ_REG(hw, CTRL); |
|
3079 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
3080 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3081 |
|
3082 /* Configure Flow Control after forcing link up. */ |
|
3083 ret_val = e1000_config_fc_after_link_up(hw); |
|
3084 if (ret_val) { |
|
3085 DEBUGOUT("Error configuring flow control\n"); |
|
3086 return ret_val; |
|
3087 } |
|
3088 } |
|
3089 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
|
3090 * auto-negotiation in the TXCW register and disable forced link in the |
|
3091 * Device Control register in an attempt to auto-negotiate with our link |
|
3092 * partner. |
|
3093 */ |
|
3094 else if (((hw->media_type == e1000_media_type_fiber) || |
|
3095 (hw->media_type == e1000_media_type_internal_serdes)) && |
|
3096 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
|
3097 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
|
3098 E1000_WRITE_REG(hw, TXCW, hw->txcw); |
|
3099 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
3100 |
|
3101 hw->serdes_link_down = FALSE; |
|
3102 } |
|
3103 /* If we force link for non-auto-negotiation switch, check link status |
|
3104 * based on MAC synchronization for internal serdes media type. |
|
3105 */ |
|
3106 else if ((hw->media_type == e1000_media_type_internal_serdes) && |
|
3107 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
|
3108 /* SYNCH bit and IV bit are sticky. */ |
|
3109 udelay(10); |
|
3110 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
|
3111 if (!(rxcw & E1000_RXCW_IV)) { |
|
3112 hw->serdes_link_down = FALSE; |
|
3113 DEBUGOUT("SERDES: Link is up.\n"); |
|
3114 } |
|
3115 } else { |
|
3116 hw->serdes_link_down = TRUE; |
|
3117 DEBUGOUT("SERDES: Link is down.\n"); |
|
3118 } |
|
3119 } |
|
3120 if ((hw->media_type == e1000_media_type_internal_serdes) && |
|
3121 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
|
3122 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
|
3123 } |
|
3124 return E1000_SUCCESS; |
|
3125 } |
|
3126 |
|
3127 /****************************************************************************** |
|
3128 * Detects the current speed and duplex settings of the hardware. |
|
3129 * |
|
3130 * hw - Struct containing variables accessed by shared code |
|
3131 * speed - Speed of the connection |
|
3132 * duplex - Duplex setting of the connection |
|
3133 *****************************************************************************/ |
|
3134 int32_t |
|
3135 e1000_get_speed_and_duplex(struct e1000_hw *hw, |
|
3136 uint16_t *speed, |
|
3137 uint16_t *duplex) |
|
3138 { |
|
3139 uint32_t status; |
|
3140 int32_t ret_val; |
|
3141 uint16_t phy_data; |
|
3142 |
|
3143 DEBUGFUNC("e1000_get_speed_and_duplex"); |
|
3144 |
|
3145 if (hw->mac_type >= e1000_82543) { |
|
3146 status = E1000_READ_REG(hw, STATUS); |
|
3147 if (status & E1000_STATUS_SPEED_1000) { |
|
3148 *speed = SPEED_1000; |
|
3149 DEBUGOUT("1000 Mbs, "); |
|
3150 } else if (status & E1000_STATUS_SPEED_100) { |
|
3151 *speed = SPEED_100; |
|
3152 DEBUGOUT("100 Mbs, "); |
|
3153 } else { |
|
3154 *speed = SPEED_10; |
|
3155 DEBUGOUT("10 Mbs, "); |
|
3156 } |
|
3157 |
|
3158 if (status & E1000_STATUS_FD) { |
|
3159 *duplex = FULL_DUPLEX; |
|
3160 DEBUGOUT("Full Duplex\n"); |
|
3161 } else { |
|
3162 *duplex = HALF_DUPLEX; |
|
3163 DEBUGOUT(" Half Duplex\n"); |
|
3164 } |
|
3165 } else { |
|
3166 DEBUGOUT("1000 Mbs, Full Duplex\n"); |
|
3167 *speed = SPEED_1000; |
|
3168 *duplex = FULL_DUPLEX; |
|
3169 } |
|
3170 |
|
3171 /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
|
3172 * if it is operating at half duplex. Here we set the duplex settings to |
|
3173 * match the duplex in the link partner's capabilities. |
|
3174 */ |
|
3175 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
|
3176 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
|
3177 if (ret_val) |
|
3178 return ret_val; |
|
3179 |
|
3180 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
|
3181 *duplex = HALF_DUPLEX; |
|
3182 else { |
|
3183 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
|
3184 if (ret_val) |
|
3185 return ret_val; |
|
3186 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
|
3187 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
|
3188 *duplex = HALF_DUPLEX; |
|
3189 } |
|
3190 } |
|
3191 |
|
3192 if ((hw->mac_type == e1000_80003es2lan) && |
|
3193 (hw->media_type == e1000_media_type_copper)) { |
|
3194 if (*speed == SPEED_1000) |
|
3195 ret_val = e1000_configure_kmrn_for_1000(hw); |
|
3196 else |
|
3197 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
|
3198 if (ret_val) |
|
3199 return ret_val; |
|
3200 } |
|
3201 |
|
3202 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { |
|
3203 ret_val = e1000_kumeran_lock_loss_workaround(hw); |
|
3204 if (ret_val) |
|
3205 return ret_val; |
|
3206 } |
|
3207 |
|
3208 return E1000_SUCCESS; |
|
3209 } |
|
3210 |
|
3211 /****************************************************************************** |
|
3212 * Blocks until autoneg completes or times out (~4.5 seconds) |
|
3213 * |
|
3214 * hw - Struct containing variables accessed by shared code |
|
3215 ******************************************************************************/ |
|
3216 static int32_t |
|
3217 e1000_wait_autoneg(struct e1000_hw *hw) |
|
3218 { |
|
3219 int32_t ret_val; |
|
3220 uint16_t i; |
|
3221 uint16_t phy_data; |
|
3222 |
|
3223 DEBUGFUNC("e1000_wait_autoneg"); |
|
3224 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
|
3225 |
|
3226 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
|
3227 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
|
3228 /* Read the MII Status Register and wait for Auto-Neg |
|
3229 * Complete bit to be set. |
|
3230 */ |
|
3231 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3232 if (ret_val) |
|
3233 return ret_val; |
|
3234 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
3235 if (ret_val) |
|
3236 return ret_val; |
|
3237 if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
|
3238 return E1000_SUCCESS; |
|
3239 } |
|
3240 msleep(100); |
|
3241 } |
|
3242 return E1000_SUCCESS; |
|
3243 } |
|
3244 |
|
3245 /****************************************************************************** |
|
3246 * Raises the Management Data Clock |
|
3247 * |
|
3248 * hw - Struct containing variables accessed by shared code |
|
3249 * ctrl - Device control register's current value |
|
3250 ******************************************************************************/ |
|
3251 static void |
|
3252 e1000_raise_mdi_clk(struct e1000_hw *hw, |
|
3253 uint32_t *ctrl) |
|
3254 { |
|
3255 /* Raise the clock input to the Management Data Clock (by setting the MDC |
|
3256 * bit), and then delay 10 microseconds. |
|
3257 */ |
|
3258 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
|
3259 E1000_WRITE_FLUSH(hw); |
|
3260 udelay(10); |
|
3261 } |
|
3262 |
|
3263 /****************************************************************************** |
|
3264 * Lowers the Management Data Clock |
|
3265 * |
|
3266 * hw - Struct containing variables accessed by shared code |
|
3267 * ctrl - Device control register's current value |
|
3268 ******************************************************************************/ |
|
3269 static void |
|
3270 e1000_lower_mdi_clk(struct e1000_hw *hw, |
|
3271 uint32_t *ctrl) |
|
3272 { |
|
3273 /* Lower the clock input to the Management Data Clock (by clearing the MDC |
|
3274 * bit), and then delay 10 microseconds. |
|
3275 */ |
|
3276 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
|
3277 E1000_WRITE_FLUSH(hw); |
|
3278 udelay(10); |
|
3279 } |
|
3280 |
|
3281 /****************************************************************************** |
|
3282 * Shifts data bits out to the PHY |
|
3283 * |
|
3284 * hw - Struct containing variables accessed by shared code |
|
3285 * data - Data to send out to the PHY |
|
3286 * count - Number of bits to shift out |
|
3287 * |
|
3288 * Bits are shifted out in MSB to LSB order. |
|
3289 ******************************************************************************/ |
|
3290 static void |
|
3291 e1000_shift_out_mdi_bits(struct e1000_hw *hw, |
|
3292 uint32_t data, |
|
3293 uint16_t count) |
|
3294 { |
|
3295 uint32_t ctrl; |
|
3296 uint32_t mask; |
|
3297 |
|
3298 /* We need to shift "count" number of bits out to the PHY. So, the value |
|
3299 * in the "data" parameter will be shifted out to the PHY one bit at a |
|
3300 * time. In order to do this, "data" must be broken down into bits. |
|
3301 */ |
|
3302 mask = 0x01; |
|
3303 mask <<= (count - 1); |
|
3304 |
|
3305 ctrl = E1000_READ_REG(hw, CTRL); |
|
3306 |
|
3307 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
|
3308 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
|
3309 |
|
3310 while (mask) { |
|
3311 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
|
3312 * then raising and lowering the Management Data Clock. A "0" is |
|
3313 * shifted out to the PHY by setting the MDIO bit to "0" and then |
|
3314 * raising and lowering the clock. |
|
3315 */ |
|
3316 if (data & mask) |
|
3317 ctrl |= E1000_CTRL_MDIO; |
|
3318 else |
|
3319 ctrl &= ~E1000_CTRL_MDIO; |
|
3320 |
|
3321 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3322 E1000_WRITE_FLUSH(hw); |
|
3323 |
|
3324 udelay(10); |
|
3325 |
|
3326 e1000_raise_mdi_clk(hw, &ctrl); |
|
3327 e1000_lower_mdi_clk(hw, &ctrl); |
|
3328 |
|
3329 mask = mask >> 1; |
|
3330 } |
|
3331 } |
|
3332 |
|
3333 /****************************************************************************** |
|
3334 * Shifts data bits in from the PHY |
|
3335 * |
|
3336 * hw - Struct containing variables accessed by shared code |
|
3337 * |
|
3338 * Bits are shifted in in MSB to LSB order. |
|
3339 ******************************************************************************/ |
|
3340 static uint16_t |
|
3341 e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
|
3342 { |
|
3343 uint32_t ctrl; |
|
3344 uint16_t data = 0; |
|
3345 uint8_t i; |
|
3346 |
|
3347 /* In order to read a register from the PHY, we need to shift in a total |
|
3348 * of 18 bits from the PHY. The first two bit (turnaround) times are used |
|
3349 * to avoid contention on the MDIO pin when a read operation is performed. |
|
3350 * These two bits are ignored by us and thrown away. Bits are "shifted in" |
|
3351 * by raising the input to the Management Data Clock (setting the MDC bit), |
|
3352 * and then reading the value of the MDIO bit. |
|
3353 */ |
|
3354 ctrl = E1000_READ_REG(hw, CTRL); |
|
3355 |
|
3356 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
|
3357 ctrl &= ~E1000_CTRL_MDIO_DIR; |
|
3358 ctrl &= ~E1000_CTRL_MDIO; |
|
3359 |
|
3360 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3361 E1000_WRITE_FLUSH(hw); |
|
3362 |
|
3363 /* Raise and Lower the clock before reading in the data. This accounts for |
|
3364 * the turnaround bits. The first clock occurred when we clocked out the |
|
3365 * last bit of the Register Address. |
|
3366 */ |
|
3367 e1000_raise_mdi_clk(hw, &ctrl); |
|
3368 e1000_lower_mdi_clk(hw, &ctrl); |
|
3369 |
|
3370 for (data = 0, i = 0; i < 16; i++) { |
|
3371 data = data << 1; |
|
3372 e1000_raise_mdi_clk(hw, &ctrl); |
|
3373 ctrl = E1000_READ_REG(hw, CTRL); |
|
3374 /* Check to see if we shifted in a "1". */ |
|
3375 if (ctrl & E1000_CTRL_MDIO) |
|
3376 data |= 1; |
|
3377 e1000_lower_mdi_clk(hw, &ctrl); |
|
3378 } |
|
3379 |
|
3380 e1000_raise_mdi_clk(hw, &ctrl); |
|
3381 e1000_lower_mdi_clk(hw, &ctrl); |
|
3382 |
|
3383 return data; |
|
3384 } |
|
3385 |
|
3386 static int32_t |
|
3387 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
|
3388 { |
|
3389 uint32_t swfw_sync = 0; |
|
3390 uint32_t swmask = mask; |
|
3391 uint32_t fwmask = mask << 16; |
|
3392 int32_t timeout = 200; |
|
3393 |
|
3394 DEBUGFUNC("e1000_swfw_sync_acquire"); |
|
3395 |
|
3396 if (hw->swfwhw_semaphore_present) |
|
3397 return e1000_get_software_flag(hw); |
|
3398 |
|
3399 if (!hw->swfw_sync_present) |
|
3400 return e1000_get_hw_eeprom_semaphore(hw); |
|
3401 |
|
3402 while (timeout) { |
|
3403 if (e1000_get_hw_eeprom_semaphore(hw)) |
|
3404 return -E1000_ERR_SWFW_SYNC; |
|
3405 |
|
3406 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
|
3407 if (!(swfw_sync & (fwmask | swmask))) { |
|
3408 break; |
|
3409 } |
|
3410 |
|
3411 /* firmware currently using resource (fwmask) */ |
|
3412 /* or other software thread currently using resource (swmask) */ |
|
3413 e1000_put_hw_eeprom_semaphore(hw); |
|
3414 mdelay(5); |
|
3415 timeout--; |
|
3416 } |
|
3417 |
|
3418 if (!timeout) { |
|
3419 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
|
3420 return -E1000_ERR_SWFW_SYNC; |
|
3421 } |
|
3422 |
|
3423 swfw_sync |= swmask; |
|
3424 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
|
3425 |
|
3426 e1000_put_hw_eeprom_semaphore(hw); |
|
3427 return E1000_SUCCESS; |
|
3428 } |
|
3429 |
|
3430 static void |
|
3431 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
|
3432 { |
|
3433 uint32_t swfw_sync; |
|
3434 uint32_t swmask = mask; |
|
3435 |
|
3436 DEBUGFUNC("e1000_swfw_sync_release"); |
|
3437 |
|
3438 if (hw->swfwhw_semaphore_present) { |
|
3439 e1000_release_software_flag(hw); |
|
3440 return; |
|
3441 } |
|
3442 |
|
3443 if (!hw->swfw_sync_present) { |
|
3444 e1000_put_hw_eeprom_semaphore(hw); |
|
3445 return; |
|
3446 } |
|
3447 |
|
3448 /* if (e1000_get_hw_eeprom_semaphore(hw)) |
|
3449 * return -E1000_ERR_SWFW_SYNC; */ |
|
3450 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); |
|
3451 /* empty */ |
|
3452 |
|
3453 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
|
3454 swfw_sync &= ~swmask; |
|
3455 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
|
3456 |
|
3457 e1000_put_hw_eeprom_semaphore(hw); |
|
3458 } |
|
3459 |
|
3460 /***************************************************************************** |
|
3461 * Reads the value from a PHY register, if the value is on a specific non zero |
|
3462 * page, sets the page first. |
|
3463 * hw - Struct containing variables accessed by shared code |
|
3464 * reg_addr - address of the PHY register to read |
|
3465 ******************************************************************************/ |
|
3466 int32_t |
|
3467 e1000_read_phy_reg(struct e1000_hw *hw, |
|
3468 uint32_t reg_addr, |
|
3469 uint16_t *phy_data) |
|
3470 { |
|
3471 uint32_t ret_val; |
|
3472 uint16_t swfw; |
|
3473 |
|
3474 DEBUGFUNC("e1000_read_phy_reg"); |
|
3475 |
|
3476 if ((hw->mac_type == e1000_80003es2lan) && |
|
3477 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3478 swfw = E1000_SWFW_PHY1_SM; |
|
3479 } else { |
|
3480 swfw = E1000_SWFW_PHY0_SM; |
|
3481 } |
|
3482 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3483 return -E1000_ERR_SWFW_SYNC; |
|
3484 |
|
3485 if ((hw->phy_type == e1000_phy_igp || |
|
3486 hw->phy_type == e1000_phy_igp_3 || |
|
3487 hw->phy_type == e1000_phy_igp_2) && |
|
3488 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
3489 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
3490 (uint16_t)reg_addr); |
|
3491 if (ret_val) { |
|
3492 e1000_swfw_sync_release(hw, swfw); |
|
3493 return ret_val; |
|
3494 } |
|
3495 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
3496 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
|
3497 (hw->mac_type == e1000_80003es2lan)) { |
|
3498 /* Select Configuration Page */ |
|
3499 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
|
3500 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
|
3501 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3502 } else { |
|
3503 /* Use Alternative Page Select register to access |
|
3504 * registers 30 and 31 |
|
3505 */ |
|
3506 ret_val = e1000_write_phy_reg_ex(hw, |
|
3507 GG82563_PHY_PAGE_SELECT_ALT, |
|
3508 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3509 } |
|
3510 |
|
3511 if (ret_val) { |
|
3512 e1000_swfw_sync_release(hw, swfw); |
|
3513 return ret_val; |
|
3514 } |
|
3515 } |
|
3516 } |
|
3517 |
|
3518 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
3519 phy_data); |
|
3520 |
|
3521 e1000_swfw_sync_release(hw, swfw); |
|
3522 return ret_val; |
|
3523 } |
|
3524 |
|
3525 static int32_t |
|
3526 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
|
3527 uint16_t *phy_data) |
|
3528 { |
|
3529 uint32_t i; |
|
3530 uint32_t mdic = 0; |
|
3531 const uint32_t phy_addr = 1; |
|
3532 |
|
3533 DEBUGFUNC("e1000_read_phy_reg_ex"); |
|
3534 |
|
3535 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
3536 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
|
3537 return -E1000_ERR_PARAM; |
|
3538 } |
|
3539 |
|
3540 if (hw->mac_type > e1000_82543) { |
|
3541 /* Set up Op-code, Phy Address, and register address in the MDI |
|
3542 * Control register. The MAC will take care of interfacing with the |
|
3543 * PHY to retrieve the desired data. |
|
3544 */ |
|
3545 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3546 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3547 (E1000_MDIC_OP_READ)); |
|
3548 |
|
3549 E1000_WRITE_REG(hw, MDIC, mdic); |
|
3550 |
|
3551 /* Poll the ready bit to see if the MDI read completed */ |
|
3552 for (i = 0; i < 64; i++) { |
|
3553 udelay(50); |
|
3554 mdic = E1000_READ_REG(hw, MDIC); |
|
3555 if (mdic & E1000_MDIC_READY) break; |
|
3556 } |
|
3557 if (!(mdic & E1000_MDIC_READY)) { |
|
3558 DEBUGOUT("MDI Read did not complete\n"); |
|
3559 return -E1000_ERR_PHY; |
|
3560 } |
|
3561 if (mdic & E1000_MDIC_ERROR) { |
|
3562 DEBUGOUT("MDI Error\n"); |
|
3563 return -E1000_ERR_PHY; |
|
3564 } |
|
3565 *phy_data = (uint16_t) mdic; |
|
3566 } else { |
|
3567 /* We must first send a preamble through the MDIO pin to signal the |
|
3568 * beginning of an MII instruction. This is done by sending 32 |
|
3569 * consecutive "1" bits. |
|
3570 */ |
|
3571 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
3572 |
|
3573 /* Now combine the next few fields that are required for a read |
|
3574 * operation. We use this method instead of calling the |
|
3575 * e1000_shift_out_mdi_bits routine five different times. The format of |
|
3576 * a MII read instruction consists of a shift out of 14 bits and is |
|
3577 * defined as follows: |
|
3578 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
|
3579 * followed by a shift in of 18 bits. This first two bits shifted in |
|
3580 * are TurnAround bits used to avoid contention on the MDIO pin when a |
|
3581 * READ operation is performed. These two bits are thrown away |
|
3582 * followed by a shift in of 16 bits which contains the desired data. |
|
3583 */ |
|
3584 mdic = ((reg_addr) | (phy_addr << 5) | |
|
3585 (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
|
3586 |
|
3587 e1000_shift_out_mdi_bits(hw, mdic, 14); |
|
3588 |
|
3589 /* Now that we've shifted out the read command to the MII, we need to |
|
3590 * "shift in" the 16-bit value (18 total bits) of the requested PHY |
|
3591 * register address. |
|
3592 */ |
|
3593 *phy_data = e1000_shift_in_mdi_bits(hw); |
|
3594 } |
|
3595 return E1000_SUCCESS; |
|
3596 } |
|
3597 |
|
3598 /****************************************************************************** |
|
3599 * Writes a value to a PHY register |
|
3600 * |
|
3601 * hw - Struct containing variables accessed by shared code |
|
3602 * reg_addr - address of the PHY register to write |
|
3603 * data - data to write to the PHY |
|
3604 ******************************************************************************/ |
|
3605 int32_t |
|
3606 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
|
3607 uint16_t phy_data) |
|
3608 { |
|
3609 uint32_t ret_val; |
|
3610 uint16_t swfw; |
|
3611 |
|
3612 DEBUGFUNC("e1000_write_phy_reg"); |
|
3613 |
|
3614 if ((hw->mac_type == e1000_80003es2lan) && |
|
3615 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3616 swfw = E1000_SWFW_PHY1_SM; |
|
3617 } else { |
|
3618 swfw = E1000_SWFW_PHY0_SM; |
|
3619 } |
|
3620 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3621 return -E1000_ERR_SWFW_SYNC; |
|
3622 |
|
3623 if ((hw->phy_type == e1000_phy_igp || |
|
3624 hw->phy_type == e1000_phy_igp_3 || |
|
3625 hw->phy_type == e1000_phy_igp_2) && |
|
3626 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
|
3627 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
|
3628 (uint16_t)reg_addr); |
|
3629 if (ret_val) { |
|
3630 e1000_swfw_sync_release(hw, swfw); |
|
3631 return ret_val; |
|
3632 } |
|
3633 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
3634 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
|
3635 (hw->mac_type == e1000_80003es2lan)) { |
|
3636 /* Select Configuration Page */ |
|
3637 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
|
3638 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
|
3639 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3640 } else { |
|
3641 /* Use Alternative Page Select register to access |
|
3642 * registers 30 and 31 |
|
3643 */ |
|
3644 ret_val = e1000_write_phy_reg_ex(hw, |
|
3645 GG82563_PHY_PAGE_SELECT_ALT, |
|
3646 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
|
3647 } |
|
3648 |
|
3649 if (ret_val) { |
|
3650 e1000_swfw_sync_release(hw, swfw); |
|
3651 return ret_val; |
|
3652 } |
|
3653 } |
|
3654 } |
|
3655 |
|
3656 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
|
3657 phy_data); |
|
3658 |
|
3659 e1000_swfw_sync_release(hw, swfw); |
|
3660 return ret_val; |
|
3661 } |
|
3662 |
|
3663 static int32_t |
|
3664 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
|
3665 uint16_t phy_data) |
|
3666 { |
|
3667 uint32_t i; |
|
3668 uint32_t mdic = 0; |
|
3669 const uint32_t phy_addr = 1; |
|
3670 |
|
3671 DEBUGFUNC("e1000_write_phy_reg_ex"); |
|
3672 |
|
3673 if (reg_addr > MAX_PHY_REG_ADDRESS) { |
|
3674 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
|
3675 return -E1000_ERR_PARAM; |
|
3676 } |
|
3677 |
|
3678 if (hw->mac_type > e1000_82543) { |
|
3679 /* Set up Op-code, Phy Address, register address, and data intended |
|
3680 * for the PHY register in the MDI Control register. The MAC will take |
|
3681 * care of interfacing with the PHY to send the desired data. |
|
3682 */ |
|
3683 mdic = (((uint32_t) phy_data) | |
|
3684 (reg_addr << E1000_MDIC_REG_SHIFT) | |
|
3685 (phy_addr << E1000_MDIC_PHY_SHIFT) | |
|
3686 (E1000_MDIC_OP_WRITE)); |
|
3687 |
|
3688 E1000_WRITE_REG(hw, MDIC, mdic); |
|
3689 |
|
3690 /* Poll the ready bit to see if the MDI read completed */ |
|
3691 for (i = 0; i < 641; i++) { |
|
3692 udelay(5); |
|
3693 mdic = E1000_READ_REG(hw, MDIC); |
|
3694 if (mdic & E1000_MDIC_READY) break; |
|
3695 } |
|
3696 if (!(mdic & E1000_MDIC_READY)) { |
|
3697 DEBUGOUT("MDI Write did not complete\n"); |
|
3698 return -E1000_ERR_PHY; |
|
3699 } |
|
3700 } else { |
|
3701 /* We'll need to use the SW defined pins to shift the write command |
|
3702 * out to the PHY. We first send a preamble to the PHY to signal the |
|
3703 * beginning of the MII instruction. This is done by sending 32 |
|
3704 * consecutive "1" bits. |
|
3705 */ |
|
3706 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
|
3707 |
|
3708 /* Now combine the remaining required fields that will indicate a |
|
3709 * write operation. We use this method instead of calling the |
|
3710 * e1000_shift_out_mdi_bits routine for each field in the command. The |
|
3711 * format of a MII write instruction is as follows: |
|
3712 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
|
3713 */ |
|
3714 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
|
3715 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
|
3716 mdic <<= 16; |
|
3717 mdic |= (uint32_t) phy_data; |
|
3718 |
|
3719 e1000_shift_out_mdi_bits(hw, mdic, 32); |
|
3720 } |
|
3721 |
|
3722 return E1000_SUCCESS; |
|
3723 } |
|
3724 |
|
3725 static int32_t |
|
3726 e1000_read_kmrn_reg(struct e1000_hw *hw, |
|
3727 uint32_t reg_addr, |
|
3728 uint16_t *data) |
|
3729 { |
|
3730 uint32_t reg_val; |
|
3731 uint16_t swfw; |
|
3732 DEBUGFUNC("e1000_read_kmrn_reg"); |
|
3733 |
|
3734 if ((hw->mac_type == e1000_80003es2lan) && |
|
3735 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3736 swfw = E1000_SWFW_PHY1_SM; |
|
3737 } else { |
|
3738 swfw = E1000_SWFW_PHY0_SM; |
|
3739 } |
|
3740 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3741 return -E1000_ERR_SWFW_SYNC; |
|
3742 |
|
3743 /* Write register address */ |
|
3744 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
|
3745 E1000_KUMCTRLSTA_OFFSET) | |
|
3746 E1000_KUMCTRLSTA_REN; |
|
3747 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
|
3748 udelay(2); |
|
3749 |
|
3750 /* Read the data returned */ |
|
3751 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); |
|
3752 *data = (uint16_t)reg_val; |
|
3753 |
|
3754 e1000_swfw_sync_release(hw, swfw); |
|
3755 return E1000_SUCCESS; |
|
3756 } |
|
3757 |
|
3758 static int32_t |
|
3759 e1000_write_kmrn_reg(struct e1000_hw *hw, |
|
3760 uint32_t reg_addr, |
|
3761 uint16_t data) |
|
3762 { |
|
3763 uint32_t reg_val; |
|
3764 uint16_t swfw; |
|
3765 DEBUGFUNC("e1000_write_kmrn_reg"); |
|
3766 |
|
3767 if ((hw->mac_type == e1000_80003es2lan) && |
|
3768 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3769 swfw = E1000_SWFW_PHY1_SM; |
|
3770 } else { |
|
3771 swfw = E1000_SWFW_PHY0_SM; |
|
3772 } |
|
3773 if (e1000_swfw_sync_acquire(hw, swfw)) |
|
3774 return -E1000_ERR_SWFW_SYNC; |
|
3775 |
|
3776 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
|
3777 E1000_KUMCTRLSTA_OFFSET) | data; |
|
3778 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
|
3779 udelay(2); |
|
3780 |
|
3781 e1000_swfw_sync_release(hw, swfw); |
|
3782 return E1000_SUCCESS; |
|
3783 } |
|
3784 |
|
3785 /****************************************************************************** |
|
3786 * Returns the PHY to the power-on reset state |
|
3787 * |
|
3788 * hw - Struct containing variables accessed by shared code |
|
3789 ******************************************************************************/ |
|
3790 int32_t |
|
3791 e1000_phy_hw_reset(struct e1000_hw *hw) |
|
3792 { |
|
3793 uint32_t ctrl, ctrl_ext; |
|
3794 uint32_t led_ctrl; |
|
3795 int32_t ret_val; |
|
3796 uint16_t swfw; |
|
3797 |
|
3798 DEBUGFUNC("e1000_phy_hw_reset"); |
|
3799 |
|
3800 /* In the case of the phy reset being blocked, it's not an error, we |
|
3801 * simply return success without performing the reset. */ |
|
3802 ret_val = e1000_check_phy_reset_block(hw); |
|
3803 if (ret_val) |
|
3804 return E1000_SUCCESS; |
|
3805 |
|
3806 DEBUGOUT("Resetting Phy...\n"); |
|
3807 |
|
3808 if (hw->mac_type > e1000_82543) { |
|
3809 if ((hw->mac_type == e1000_80003es2lan) && |
|
3810 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
|
3811 swfw = E1000_SWFW_PHY1_SM; |
|
3812 } else { |
|
3813 swfw = E1000_SWFW_PHY0_SM; |
|
3814 } |
|
3815 if (e1000_swfw_sync_acquire(hw, swfw)) { |
|
3816 DEBUGOUT("Unable to acquire swfw sync\n"); |
|
3817 return -E1000_ERR_SWFW_SYNC; |
|
3818 } |
|
3819 /* Read the device control register and assert the E1000_CTRL_PHY_RST |
|
3820 * bit. Then, take it out of reset. |
|
3821 * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
|
3822 * and deassert. For e1000_82571 hardware and later, we instead delay |
|
3823 * for 50us between and 10ms after the deassertion. |
|
3824 */ |
|
3825 ctrl = E1000_READ_REG(hw, CTRL); |
|
3826 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
3827 E1000_WRITE_FLUSH(hw); |
|
3828 |
|
3829 if (hw->mac_type < e1000_82571) |
|
3830 msleep(10); |
|
3831 else |
|
3832 udelay(100); |
|
3833 |
|
3834 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
3835 E1000_WRITE_FLUSH(hw); |
|
3836 |
|
3837 if (hw->mac_type >= e1000_82571) |
|
3838 mdelay(10); |
|
3839 |
|
3840 e1000_swfw_sync_release(hw, swfw); |
|
3841 } else { |
|
3842 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
|
3843 * bit to put the PHY into reset. Then, take it out of reset. |
|
3844 */ |
|
3845 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
3846 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
|
3847 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
|
3848 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
3849 E1000_WRITE_FLUSH(hw); |
|
3850 msleep(10); |
|
3851 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
|
3852 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
3853 E1000_WRITE_FLUSH(hw); |
|
3854 } |
|
3855 udelay(150); |
|
3856 |
|
3857 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
|
3858 /* Configure activity LED after PHY reset */ |
|
3859 led_ctrl = E1000_READ_REG(hw, LEDCTL); |
|
3860 led_ctrl &= IGP_ACTIVITY_LED_MASK; |
|
3861 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
|
3862 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
|
3863 } |
|
3864 |
|
3865 /* Wait for FW to finish PHY configuration. */ |
|
3866 ret_val = e1000_get_phy_cfg_done(hw); |
|
3867 if (ret_val != E1000_SUCCESS) |
|
3868 return ret_val; |
|
3869 e1000_release_software_semaphore(hw); |
|
3870 |
|
3871 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) |
|
3872 ret_val = e1000_init_lcd_from_nvm(hw); |
|
3873 |
|
3874 return ret_val; |
|
3875 } |
|
3876 |
|
3877 /****************************************************************************** |
|
3878 * Resets the PHY |
|
3879 * |
|
3880 * hw - Struct containing variables accessed by shared code |
|
3881 * |
|
3882 * Sets bit 15 of the MII Control register |
|
3883 ******************************************************************************/ |
|
3884 int32_t |
|
3885 e1000_phy_reset(struct e1000_hw *hw) |
|
3886 { |
|
3887 int32_t ret_val; |
|
3888 uint16_t phy_data; |
|
3889 |
|
3890 DEBUGFUNC("e1000_phy_reset"); |
|
3891 |
|
3892 /* In the case of the phy reset being blocked, it's not an error, we |
|
3893 * simply return success without performing the reset. */ |
|
3894 ret_val = e1000_check_phy_reset_block(hw); |
|
3895 if (ret_val) |
|
3896 return E1000_SUCCESS; |
|
3897 |
|
3898 switch (hw->phy_type) { |
|
3899 case e1000_phy_igp: |
|
3900 case e1000_phy_igp_2: |
|
3901 case e1000_phy_igp_3: |
|
3902 case e1000_phy_ife: |
|
3903 ret_val = e1000_phy_hw_reset(hw); |
|
3904 if (ret_val) |
|
3905 return ret_val; |
|
3906 break; |
|
3907 default: |
|
3908 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
|
3909 if (ret_val) |
|
3910 return ret_val; |
|
3911 |
|
3912 phy_data |= MII_CR_RESET; |
|
3913 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
|
3914 if (ret_val) |
|
3915 return ret_val; |
|
3916 |
|
3917 udelay(1); |
|
3918 break; |
|
3919 } |
|
3920 |
|
3921 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
|
3922 e1000_phy_init_script(hw); |
|
3923 |
|
3924 return E1000_SUCCESS; |
|
3925 } |
|
3926 |
|
3927 /****************************************************************************** |
|
3928 * Work-around for 82566 power-down: on D3 entry- |
|
3929 * 1) disable gigabit link |
|
3930 * 2) write VR power-down enable |
|
3931 * 3) read it back |
|
3932 * if successful continue, else issue LCD reset and repeat |
|
3933 * |
|
3934 * hw - struct containing variables accessed by shared code |
|
3935 ******************************************************************************/ |
|
3936 void |
|
3937 e1000_phy_powerdown_workaround(struct e1000_hw *hw) |
|
3938 { |
|
3939 int32_t reg; |
|
3940 uint16_t phy_data; |
|
3941 int32_t retry = 0; |
|
3942 |
|
3943 DEBUGFUNC("e1000_phy_powerdown_workaround"); |
|
3944 |
|
3945 if (hw->phy_type != e1000_phy_igp_3) |
|
3946 return; |
|
3947 |
|
3948 do { |
|
3949 /* Disable link */ |
|
3950 reg = E1000_READ_REG(hw, PHY_CTRL); |
|
3951 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
|
3952 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
3953 |
|
3954 /* Write VR power-down enable - bits 9:8 should be 10b */ |
|
3955 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
|
3956 phy_data |= (1 << 9); |
|
3957 phy_data &= ~(1 << 8); |
|
3958 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); |
|
3959 |
|
3960 /* Read it back and test */ |
|
3961 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
|
3962 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) |
|
3963 break; |
|
3964 |
|
3965 /* Issue PHY reset and repeat at most one more time */ |
|
3966 reg = E1000_READ_REG(hw, CTRL); |
|
3967 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); |
|
3968 retry++; |
|
3969 } while (retry); |
|
3970 |
|
3971 return; |
|
3972 |
|
3973 } |
|
3974 |
|
3975 /****************************************************************************** |
|
3976 * Work-around for 82566 Kumeran PCS lock loss: |
|
3977 * On link status change (i.e. PCI reset, speed change) and link is up and |
|
3978 * speed is gigabit- |
|
3979 * 0) if workaround is optionally disabled do nothing |
|
3980 * 1) wait 1ms for Kumeran link to come up |
|
3981 * 2) check Kumeran Diagnostic register PCS lock loss bit |
|
3982 * 3) if not set the link is locked (all is good), otherwise... |
|
3983 * 4) reset the PHY |
|
3984 * 5) repeat up to 10 times |
|
3985 * Note: this is only called for IGP3 copper when speed is 1gb. |
|
3986 * |
|
3987 * hw - struct containing variables accessed by shared code |
|
3988 ******************************************************************************/ |
|
3989 static int32_t |
|
3990 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) |
|
3991 { |
|
3992 int32_t ret_val; |
|
3993 int32_t reg; |
|
3994 int32_t cnt; |
|
3995 uint16_t phy_data; |
|
3996 |
|
3997 if (hw->kmrn_lock_loss_workaround_disabled) |
|
3998 return E1000_SUCCESS; |
|
3999 |
|
4000 /* Make sure link is up before proceeding. If not just return. |
|
4001 * Attempting this while link is negotiating fouled up link |
|
4002 * stability */ |
|
4003 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4004 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4005 |
|
4006 if (phy_data & MII_SR_LINK_STATUS) { |
|
4007 for (cnt = 0; cnt < 10; cnt++) { |
|
4008 /* read once to clear */ |
|
4009 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
|
4010 if (ret_val) |
|
4011 return ret_val; |
|
4012 /* and again to get new status */ |
|
4013 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
|
4014 if (ret_val) |
|
4015 return ret_val; |
|
4016 |
|
4017 /* check for PCS lock */ |
|
4018 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
|
4019 return E1000_SUCCESS; |
|
4020 |
|
4021 /* Issue PHY reset */ |
|
4022 e1000_phy_hw_reset(hw); |
|
4023 mdelay(5); |
|
4024 } |
|
4025 /* Disable GigE link negotiation */ |
|
4026 reg = E1000_READ_REG(hw, PHY_CTRL); |
|
4027 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
|
4028 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
|
4029 |
|
4030 /* unable to acquire PCS lock */ |
|
4031 return E1000_ERR_PHY; |
|
4032 } |
|
4033 |
|
4034 return E1000_SUCCESS; |
|
4035 } |
|
4036 |
|
4037 /****************************************************************************** |
|
4038 * Probes the expected PHY address for known PHY IDs |
|
4039 * |
|
4040 * hw - Struct containing variables accessed by shared code |
|
4041 ******************************************************************************/ |
|
4042 static int32_t |
|
4043 e1000_detect_gig_phy(struct e1000_hw *hw) |
|
4044 { |
|
4045 int32_t phy_init_status, ret_val; |
|
4046 uint16_t phy_id_high, phy_id_low; |
|
4047 boolean_t match = FALSE; |
|
4048 |
|
4049 DEBUGFUNC("e1000_detect_gig_phy"); |
|
4050 |
|
4051 if (hw->phy_id != 0) |
|
4052 return E1000_SUCCESS; |
|
4053 |
|
4054 /* The 82571 firmware may still be configuring the PHY. In this |
|
4055 * case, we cannot access the PHY until the configuration is done. So |
|
4056 * we explicitly set the PHY values. */ |
|
4057 if (hw->mac_type == e1000_82571 || |
|
4058 hw->mac_type == e1000_82572) { |
|
4059 hw->phy_id = IGP01E1000_I_PHY_ID; |
|
4060 hw->phy_type = e1000_phy_igp_2; |
|
4061 return E1000_SUCCESS; |
|
4062 } |
|
4063 |
|
4064 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
|
4065 * around that forces PHY page 0 to be set or the reads fail. The rest of |
|
4066 * the code in this routine uses e1000_read_phy_reg to read the PHY ID. |
|
4067 * So for ESB-2 we need to have this set so our reads won't fail. If the |
|
4068 * attached PHY is not a e1000_phy_gg82563, the routines below will figure |
|
4069 * this out as well. */ |
|
4070 if (hw->mac_type == e1000_80003es2lan) |
|
4071 hw->phy_type = e1000_phy_gg82563; |
|
4072 |
|
4073 /* Read the PHY ID Registers to identify which PHY is onboard. */ |
|
4074 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
|
4075 if (ret_val) |
|
4076 return ret_val; |
|
4077 |
|
4078 hw->phy_id = (uint32_t) (phy_id_high << 16); |
|
4079 udelay(20); |
|
4080 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
|
4081 if (ret_val) |
|
4082 return ret_val; |
|
4083 |
|
4084 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
|
4085 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
|
4086 |
|
4087 switch (hw->mac_type) { |
|
4088 case e1000_82543: |
|
4089 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
|
4090 break; |
|
4091 case e1000_82544: |
|
4092 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
|
4093 break; |
|
4094 case e1000_82540: |
|
4095 case e1000_82545: |
|
4096 case e1000_82545_rev_3: |
|
4097 case e1000_82546: |
|
4098 case e1000_82546_rev_3: |
|
4099 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
|
4100 break; |
|
4101 case e1000_82541: |
|
4102 case e1000_82541_rev_2: |
|
4103 case e1000_82547: |
|
4104 case e1000_82547_rev_2: |
|
4105 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
|
4106 break; |
|
4107 case e1000_82573: |
|
4108 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
|
4109 break; |
|
4110 case e1000_80003es2lan: |
|
4111 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; |
|
4112 break; |
|
4113 case e1000_ich8lan: |
|
4114 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; |
|
4115 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; |
|
4116 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; |
|
4117 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; |
|
4118 break; |
|
4119 default: |
|
4120 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
|
4121 return -E1000_ERR_CONFIG; |
|
4122 } |
|
4123 phy_init_status = e1000_set_phy_type(hw); |
|
4124 |
|
4125 if ((match) && (phy_init_status == E1000_SUCCESS)) { |
|
4126 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
|
4127 return E1000_SUCCESS; |
|
4128 } |
|
4129 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
|
4130 return -E1000_ERR_PHY; |
|
4131 } |
|
4132 |
|
4133 /****************************************************************************** |
|
4134 * Resets the PHY's DSP |
|
4135 * |
|
4136 * hw - Struct containing variables accessed by shared code |
|
4137 ******************************************************************************/ |
|
4138 static int32_t |
|
4139 e1000_phy_reset_dsp(struct e1000_hw *hw) |
|
4140 { |
|
4141 int32_t ret_val; |
|
4142 DEBUGFUNC("e1000_phy_reset_dsp"); |
|
4143 |
|
4144 do { |
|
4145 if (hw->phy_type != e1000_phy_gg82563) { |
|
4146 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
|
4147 if (ret_val) break; |
|
4148 } |
|
4149 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
|
4150 if (ret_val) break; |
|
4151 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
|
4152 if (ret_val) break; |
|
4153 ret_val = E1000_SUCCESS; |
|
4154 } while (0); |
|
4155 |
|
4156 return ret_val; |
|
4157 } |
|
4158 |
|
4159 /****************************************************************************** |
|
4160 * Get PHY information from various PHY registers for igp PHY only. |
|
4161 * |
|
4162 * hw - Struct containing variables accessed by shared code |
|
4163 * phy_info - PHY information structure |
|
4164 ******************************************************************************/ |
|
4165 static int32_t |
|
4166 e1000_phy_igp_get_info(struct e1000_hw *hw, |
|
4167 struct e1000_phy_info *phy_info) |
|
4168 { |
|
4169 int32_t ret_val; |
|
4170 uint16_t phy_data, min_length, max_length, average; |
|
4171 e1000_rev_polarity polarity; |
|
4172 |
|
4173 DEBUGFUNC("e1000_phy_igp_get_info"); |
|
4174 |
|
4175 /* The downshift status is checked only once, after link is established, |
|
4176 * and it stored in the hw->speed_downgraded parameter. */ |
|
4177 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4178 |
|
4179 /* IGP01E1000 does not need to support it. */ |
|
4180 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
4181 |
|
4182 /* IGP01E1000 always correct polarity reversal */ |
|
4183 phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
|
4184 |
|
4185 /* Check polarity status */ |
|
4186 ret_val = e1000_check_polarity(hw, &polarity); |
|
4187 if (ret_val) |
|
4188 return ret_val; |
|
4189 |
|
4190 phy_info->cable_polarity = polarity; |
|
4191 |
|
4192 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
|
4193 if (ret_val) |
|
4194 return ret_val; |
|
4195 |
|
4196 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> |
|
4197 IGP01E1000_PSSR_MDIX_SHIFT); |
|
4198 |
|
4199 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
4200 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
4201 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
|
4202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
4203 if (ret_val) |
|
4204 return ret_val; |
|
4205 |
|
4206 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
4207 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
4208 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
4209 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
4210 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
4211 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
4212 |
|
4213 /* Get cable length */ |
|
4214 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
4215 if (ret_val) |
|
4216 return ret_val; |
|
4217 |
|
4218 /* Translate to old method */ |
|
4219 average = (max_length + min_length) / 2; |
|
4220 |
|
4221 if (average <= e1000_igp_cable_length_50) |
|
4222 phy_info->cable_length = e1000_cable_length_50; |
|
4223 else if (average <= e1000_igp_cable_length_80) |
|
4224 phy_info->cable_length = e1000_cable_length_50_80; |
|
4225 else if (average <= e1000_igp_cable_length_110) |
|
4226 phy_info->cable_length = e1000_cable_length_80_110; |
|
4227 else if (average <= e1000_igp_cable_length_140) |
|
4228 phy_info->cable_length = e1000_cable_length_110_140; |
|
4229 else |
|
4230 phy_info->cable_length = e1000_cable_length_140; |
|
4231 } |
|
4232 |
|
4233 return E1000_SUCCESS; |
|
4234 } |
|
4235 |
|
4236 /****************************************************************************** |
|
4237 * Get PHY information from various PHY registers for ife PHY only. |
|
4238 * |
|
4239 * hw - Struct containing variables accessed by shared code |
|
4240 * phy_info - PHY information structure |
|
4241 ******************************************************************************/ |
|
4242 static int32_t |
|
4243 e1000_phy_ife_get_info(struct e1000_hw *hw, |
|
4244 struct e1000_phy_info *phy_info) |
|
4245 { |
|
4246 int32_t ret_val; |
|
4247 uint16_t phy_data; |
|
4248 e1000_rev_polarity polarity; |
|
4249 |
|
4250 DEBUGFUNC("e1000_phy_ife_get_info"); |
|
4251 |
|
4252 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4253 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
|
4254 |
|
4255 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); |
|
4256 if (ret_val) |
|
4257 return ret_val; |
|
4258 phy_info->polarity_correction = |
|
4259 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> |
|
4260 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? |
|
4261 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
|
4262 |
|
4263 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { |
|
4264 ret_val = e1000_check_polarity(hw, &polarity); |
|
4265 if (ret_val) |
|
4266 return ret_val; |
|
4267 } else { |
|
4268 /* Polarity is forced. */ |
|
4269 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> |
|
4270 IFE_PSC_FORCE_POLARITY_SHIFT) ? |
|
4271 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
4272 } |
|
4273 phy_info->cable_polarity = polarity; |
|
4274 |
|
4275 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
|
4276 if (ret_val) |
|
4277 return ret_val; |
|
4278 |
|
4279 phy_info->mdix_mode = (e1000_auto_x_mode) |
|
4280 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> |
|
4281 IFE_PMC_MDIX_MODE_SHIFT); |
|
4282 |
|
4283 return E1000_SUCCESS; |
|
4284 } |
|
4285 |
|
4286 /****************************************************************************** |
|
4287 * Get PHY information from various PHY registers fot m88 PHY only. |
|
4288 * |
|
4289 * hw - Struct containing variables accessed by shared code |
|
4290 * phy_info - PHY information structure |
|
4291 ******************************************************************************/ |
|
4292 static int32_t |
|
4293 e1000_phy_m88_get_info(struct e1000_hw *hw, |
|
4294 struct e1000_phy_info *phy_info) |
|
4295 { |
|
4296 int32_t ret_val; |
|
4297 uint16_t phy_data; |
|
4298 e1000_rev_polarity polarity; |
|
4299 |
|
4300 DEBUGFUNC("e1000_phy_m88_get_info"); |
|
4301 |
|
4302 /* The downshift status is checked only once, after link is established, |
|
4303 * and it stored in the hw->speed_downgraded parameter. */ |
|
4304 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
|
4305 |
|
4306 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
4307 if (ret_val) |
|
4308 return ret_val; |
|
4309 |
|
4310 phy_info->extended_10bt_distance = |
|
4311 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
|
4312 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? |
|
4313 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; |
|
4314 |
|
4315 phy_info->polarity_correction = |
|
4316 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
|
4317 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? |
|
4318 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
|
4319 |
|
4320 /* Check polarity status */ |
|
4321 ret_val = e1000_check_polarity(hw, &polarity); |
|
4322 if (ret_val) |
|
4323 return ret_val; |
|
4324 phy_info->cable_polarity = polarity; |
|
4325 |
|
4326 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
4327 if (ret_val) |
|
4328 return ret_val; |
|
4329 |
|
4330 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> |
|
4331 M88E1000_PSSR_MDIX_SHIFT); |
|
4332 |
|
4333 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
4334 /* Cable Length Estimation and Local/Remote Receiver Information |
|
4335 * are only valid at 1000 Mbps. |
|
4336 */ |
|
4337 if (hw->phy_type != e1000_phy_gg82563) { |
|
4338 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
4339 M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
|
4340 } else { |
|
4341 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
|
4342 &phy_data); |
|
4343 if (ret_val) |
|
4344 return ret_val; |
|
4345 |
|
4346 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); |
|
4347 } |
|
4348 |
|
4349 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
|
4350 if (ret_val) |
|
4351 return ret_val; |
|
4352 |
|
4353 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
|
4354 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
|
4355 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
4356 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
|
4357 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
|
4358 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
|
4359 |
|
4360 } |
|
4361 |
|
4362 return E1000_SUCCESS; |
|
4363 } |
|
4364 |
|
4365 /****************************************************************************** |
|
4366 * Get PHY information from various PHY registers |
|
4367 * |
|
4368 * hw - Struct containing variables accessed by shared code |
|
4369 * phy_info - PHY information structure |
|
4370 ******************************************************************************/ |
|
4371 int32_t |
|
4372 e1000_phy_get_info(struct e1000_hw *hw, |
|
4373 struct e1000_phy_info *phy_info) |
|
4374 { |
|
4375 int32_t ret_val; |
|
4376 uint16_t phy_data; |
|
4377 |
|
4378 DEBUGFUNC("e1000_phy_get_info"); |
|
4379 |
|
4380 phy_info->cable_length = e1000_cable_length_undefined; |
|
4381 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
|
4382 phy_info->cable_polarity = e1000_rev_polarity_undefined; |
|
4383 phy_info->downshift = e1000_downshift_undefined; |
|
4384 phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
|
4385 phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
|
4386 phy_info->local_rx = e1000_1000t_rx_status_undefined; |
|
4387 phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
|
4388 |
|
4389 if (hw->media_type != e1000_media_type_copper) { |
|
4390 DEBUGOUT("PHY info is only valid for copper media\n"); |
|
4391 return -E1000_ERR_CONFIG; |
|
4392 } |
|
4393 |
|
4394 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4395 if (ret_val) |
|
4396 return ret_val; |
|
4397 |
|
4398 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
|
4399 if (ret_val) |
|
4400 return ret_val; |
|
4401 |
|
4402 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
|
4403 DEBUGOUT("PHY info is only valid if link is up\n"); |
|
4404 return -E1000_ERR_CONFIG; |
|
4405 } |
|
4406 |
|
4407 if (hw->phy_type == e1000_phy_igp || |
|
4408 hw->phy_type == e1000_phy_igp_3 || |
|
4409 hw->phy_type == e1000_phy_igp_2) |
|
4410 return e1000_phy_igp_get_info(hw, phy_info); |
|
4411 else if (hw->phy_type == e1000_phy_ife) |
|
4412 return e1000_phy_ife_get_info(hw, phy_info); |
|
4413 else |
|
4414 return e1000_phy_m88_get_info(hw, phy_info); |
|
4415 } |
|
4416 |
|
4417 int32_t |
|
4418 e1000_validate_mdi_setting(struct e1000_hw *hw) |
|
4419 { |
|
4420 DEBUGFUNC("e1000_validate_mdi_settings"); |
|
4421 |
|
4422 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
|
4423 DEBUGOUT("Invalid MDI setting detected\n"); |
|
4424 hw->mdix = 1; |
|
4425 return -E1000_ERR_CONFIG; |
|
4426 } |
|
4427 return E1000_SUCCESS; |
|
4428 } |
|
4429 |
|
4430 |
|
4431 /****************************************************************************** |
|
4432 * Sets up eeprom variables in the hw struct. Must be called after mac_type |
|
4433 * is configured. Additionally, if this is ICH8, the flash controller GbE |
|
4434 * registers must be mapped, or this will crash. |
|
4435 * |
|
4436 * hw - Struct containing variables accessed by shared code |
|
4437 *****************************************************************************/ |
|
4438 int32_t |
|
4439 e1000_init_eeprom_params(struct e1000_hw *hw) |
|
4440 { |
|
4441 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4442 uint32_t eecd = E1000_READ_REG(hw, EECD); |
|
4443 int32_t ret_val = E1000_SUCCESS; |
|
4444 uint16_t eeprom_size; |
|
4445 |
|
4446 DEBUGFUNC("e1000_init_eeprom_params"); |
|
4447 |
|
4448 switch (hw->mac_type) { |
|
4449 case e1000_82542_rev2_0: |
|
4450 case e1000_82542_rev2_1: |
|
4451 case e1000_82543: |
|
4452 case e1000_82544: |
|
4453 eeprom->type = e1000_eeprom_microwire; |
|
4454 eeprom->word_size = 64; |
|
4455 eeprom->opcode_bits = 3; |
|
4456 eeprom->address_bits = 6; |
|
4457 eeprom->delay_usec = 50; |
|
4458 eeprom->use_eerd = FALSE; |
|
4459 eeprom->use_eewr = FALSE; |
|
4460 break; |
|
4461 case e1000_82540: |
|
4462 case e1000_82545: |
|
4463 case e1000_82545_rev_3: |
|
4464 case e1000_82546: |
|
4465 case e1000_82546_rev_3: |
|
4466 eeprom->type = e1000_eeprom_microwire; |
|
4467 eeprom->opcode_bits = 3; |
|
4468 eeprom->delay_usec = 50; |
|
4469 if (eecd & E1000_EECD_SIZE) { |
|
4470 eeprom->word_size = 256; |
|
4471 eeprom->address_bits = 8; |
|
4472 } else { |
|
4473 eeprom->word_size = 64; |
|
4474 eeprom->address_bits = 6; |
|
4475 } |
|
4476 eeprom->use_eerd = FALSE; |
|
4477 eeprom->use_eewr = FALSE; |
|
4478 break; |
|
4479 case e1000_82541: |
|
4480 case e1000_82541_rev_2: |
|
4481 case e1000_82547: |
|
4482 case e1000_82547_rev_2: |
|
4483 if (eecd & E1000_EECD_TYPE) { |
|
4484 eeprom->type = e1000_eeprom_spi; |
|
4485 eeprom->opcode_bits = 8; |
|
4486 eeprom->delay_usec = 1; |
|
4487 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4488 eeprom->page_size = 32; |
|
4489 eeprom->address_bits = 16; |
|
4490 } else { |
|
4491 eeprom->page_size = 8; |
|
4492 eeprom->address_bits = 8; |
|
4493 } |
|
4494 } else { |
|
4495 eeprom->type = e1000_eeprom_microwire; |
|
4496 eeprom->opcode_bits = 3; |
|
4497 eeprom->delay_usec = 50; |
|
4498 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4499 eeprom->word_size = 256; |
|
4500 eeprom->address_bits = 8; |
|
4501 } else { |
|
4502 eeprom->word_size = 64; |
|
4503 eeprom->address_bits = 6; |
|
4504 } |
|
4505 } |
|
4506 eeprom->use_eerd = FALSE; |
|
4507 eeprom->use_eewr = FALSE; |
|
4508 break; |
|
4509 case e1000_82571: |
|
4510 case e1000_82572: |
|
4511 eeprom->type = e1000_eeprom_spi; |
|
4512 eeprom->opcode_bits = 8; |
|
4513 eeprom->delay_usec = 1; |
|
4514 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4515 eeprom->page_size = 32; |
|
4516 eeprom->address_bits = 16; |
|
4517 } else { |
|
4518 eeprom->page_size = 8; |
|
4519 eeprom->address_bits = 8; |
|
4520 } |
|
4521 eeprom->use_eerd = FALSE; |
|
4522 eeprom->use_eewr = FALSE; |
|
4523 break; |
|
4524 case e1000_82573: |
|
4525 eeprom->type = e1000_eeprom_spi; |
|
4526 eeprom->opcode_bits = 8; |
|
4527 eeprom->delay_usec = 1; |
|
4528 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4529 eeprom->page_size = 32; |
|
4530 eeprom->address_bits = 16; |
|
4531 } else { |
|
4532 eeprom->page_size = 8; |
|
4533 eeprom->address_bits = 8; |
|
4534 } |
|
4535 eeprom->use_eerd = TRUE; |
|
4536 eeprom->use_eewr = TRUE; |
|
4537 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
|
4538 eeprom->type = e1000_eeprom_flash; |
|
4539 eeprom->word_size = 2048; |
|
4540 |
|
4541 /* Ensure that the Autonomous FLASH update bit is cleared due to |
|
4542 * Flash update issue on parts which use a FLASH for NVM. */ |
|
4543 eecd &= ~E1000_EECD_AUPDEN; |
|
4544 E1000_WRITE_REG(hw, EECD, eecd); |
|
4545 } |
|
4546 break; |
|
4547 case e1000_80003es2lan: |
|
4548 eeprom->type = e1000_eeprom_spi; |
|
4549 eeprom->opcode_bits = 8; |
|
4550 eeprom->delay_usec = 1; |
|
4551 if (eecd & E1000_EECD_ADDR_BITS) { |
|
4552 eeprom->page_size = 32; |
|
4553 eeprom->address_bits = 16; |
|
4554 } else { |
|
4555 eeprom->page_size = 8; |
|
4556 eeprom->address_bits = 8; |
|
4557 } |
|
4558 eeprom->use_eerd = TRUE; |
|
4559 eeprom->use_eewr = FALSE; |
|
4560 break; |
|
4561 case e1000_ich8lan: |
|
4562 { |
|
4563 int32_t i = 0; |
|
4564 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); |
|
4565 |
|
4566 eeprom->type = e1000_eeprom_ich8; |
|
4567 eeprom->use_eerd = FALSE; |
|
4568 eeprom->use_eewr = FALSE; |
|
4569 eeprom->word_size = E1000_SHADOW_RAM_WORDS; |
|
4570 |
|
4571 /* Zero the shadow RAM structure. But don't load it from NVM |
|
4572 * so as to save time for driver init */ |
|
4573 if (hw->eeprom_shadow_ram != NULL) { |
|
4574 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
|
4575 hw->eeprom_shadow_ram[i].modified = FALSE; |
|
4576 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
|
4577 } |
|
4578 } |
|
4579 |
|
4580 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * |
|
4581 ICH_FLASH_SECTOR_SIZE; |
|
4582 |
|
4583 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; |
|
4584 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); |
|
4585 |
|
4586 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; |
|
4587 |
|
4588 hw->flash_bank_size /= 2 * sizeof(uint16_t); |
|
4589 |
|
4590 break; |
|
4591 } |
|
4592 default: |
|
4593 break; |
|
4594 } |
|
4595 |
|
4596 if (eeprom->type == e1000_eeprom_spi) { |
|
4597 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
|
4598 * 32KB (incremented by powers of 2). |
|
4599 */ |
|
4600 if (hw->mac_type <= e1000_82547_rev_2) { |
|
4601 /* Set to default value for initial eeprom read. */ |
|
4602 eeprom->word_size = 64; |
|
4603 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
|
4604 if (ret_val) |
|
4605 return ret_val; |
|
4606 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
|
4607 /* 256B eeprom size was not supported in earlier hardware, so we |
|
4608 * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
|
4609 * is never the result used in the shifting logic below. */ |
|
4610 if (eeprom_size) |
|
4611 eeprom_size++; |
|
4612 } else { |
|
4613 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
|
4614 E1000_EECD_SIZE_EX_SHIFT); |
|
4615 } |
|
4616 |
|
4617 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
|
4618 } |
|
4619 return ret_val; |
|
4620 } |
|
4621 |
|
4622 /****************************************************************************** |
|
4623 * Raises the EEPROM's clock input. |
|
4624 * |
|
4625 * hw - Struct containing variables accessed by shared code |
|
4626 * eecd - EECD's current value |
|
4627 *****************************************************************************/ |
|
4628 static void |
|
4629 e1000_raise_ee_clk(struct e1000_hw *hw, |
|
4630 uint32_t *eecd) |
|
4631 { |
|
4632 /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
|
4633 * wait <delay> microseconds. |
|
4634 */ |
|
4635 *eecd = *eecd | E1000_EECD_SK; |
|
4636 E1000_WRITE_REG(hw, EECD, *eecd); |
|
4637 E1000_WRITE_FLUSH(hw); |
|
4638 udelay(hw->eeprom.delay_usec); |
|
4639 } |
|
4640 |
|
4641 /****************************************************************************** |
|
4642 * Lowers the EEPROM's clock input. |
|
4643 * |
|
4644 * hw - Struct containing variables accessed by shared code |
|
4645 * eecd - EECD's current value |
|
4646 *****************************************************************************/ |
|
4647 static void |
|
4648 e1000_lower_ee_clk(struct e1000_hw *hw, |
|
4649 uint32_t *eecd) |
|
4650 { |
|
4651 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
|
4652 * wait 50 microseconds. |
|
4653 */ |
|
4654 *eecd = *eecd & ~E1000_EECD_SK; |
|
4655 E1000_WRITE_REG(hw, EECD, *eecd); |
|
4656 E1000_WRITE_FLUSH(hw); |
|
4657 udelay(hw->eeprom.delay_usec); |
|
4658 } |
|
4659 |
|
4660 /****************************************************************************** |
|
4661 * Shift data bits out to the EEPROM. |
|
4662 * |
|
4663 * hw - Struct containing variables accessed by shared code |
|
4664 * data - data to send to the EEPROM |
|
4665 * count - number of bits to shift out |
|
4666 *****************************************************************************/ |
|
4667 static void |
|
4668 e1000_shift_out_ee_bits(struct e1000_hw *hw, |
|
4669 uint16_t data, |
|
4670 uint16_t count) |
|
4671 { |
|
4672 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4673 uint32_t eecd; |
|
4674 uint32_t mask; |
|
4675 |
|
4676 /* We need to shift "count" bits out to the EEPROM. So, value in the |
|
4677 * "data" parameter will be shifted out to the EEPROM one bit at a time. |
|
4678 * In order to do this, "data" must be broken down into bits. |
|
4679 */ |
|
4680 mask = 0x01 << (count - 1); |
|
4681 eecd = E1000_READ_REG(hw, EECD); |
|
4682 if (eeprom->type == e1000_eeprom_microwire) { |
|
4683 eecd &= ~E1000_EECD_DO; |
|
4684 } else if (eeprom->type == e1000_eeprom_spi) { |
|
4685 eecd |= E1000_EECD_DO; |
|
4686 } |
|
4687 do { |
|
4688 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
|
4689 * and then raising and then lowering the clock (the SK bit controls |
|
4690 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
|
4691 * by setting "DI" to "0" and then raising and then lowering the clock. |
|
4692 */ |
|
4693 eecd &= ~E1000_EECD_DI; |
|
4694 |
|
4695 if (data & mask) |
|
4696 eecd |= E1000_EECD_DI; |
|
4697 |
|
4698 E1000_WRITE_REG(hw, EECD, eecd); |
|
4699 E1000_WRITE_FLUSH(hw); |
|
4700 |
|
4701 udelay(eeprom->delay_usec); |
|
4702 |
|
4703 e1000_raise_ee_clk(hw, &eecd); |
|
4704 e1000_lower_ee_clk(hw, &eecd); |
|
4705 |
|
4706 mask = mask >> 1; |
|
4707 |
|
4708 } while (mask); |
|
4709 |
|
4710 /* We leave the "DI" bit set to "0" when we leave this routine. */ |
|
4711 eecd &= ~E1000_EECD_DI; |
|
4712 E1000_WRITE_REG(hw, EECD, eecd); |
|
4713 } |
|
4714 |
|
4715 /****************************************************************************** |
|
4716 * Shift data bits in from the EEPROM |
|
4717 * |
|
4718 * hw - Struct containing variables accessed by shared code |
|
4719 *****************************************************************************/ |
|
4720 static uint16_t |
|
4721 e1000_shift_in_ee_bits(struct e1000_hw *hw, |
|
4722 uint16_t count) |
|
4723 { |
|
4724 uint32_t eecd; |
|
4725 uint32_t i; |
|
4726 uint16_t data; |
|
4727 |
|
4728 /* In order to read a register from the EEPROM, we need to shift 'count' |
|
4729 * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
|
4730 * input to the EEPROM (setting the SK bit), and then reading the value of |
|
4731 * the "DO" bit. During this "shifting in" process the "DI" bit should |
|
4732 * always be clear. |
|
4733 */ |
|
4734 |
|
4735 eecd = E1000_READ_REG(hw, EECD); |
|
4736 |
|
4737 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
|
4738 data = 0; |
|
4739 |
|
4740 for (i = 0; i < count; i++) { |
|
4741 data = data << 1; |
|
4742 e1000_raise_ee_clk(hw, &eecd); |
|
4743 |
|
4744 eecd = E1000_READ_REG(hw, EECD); |
|
4745 |
|
4746 eecd &= ~(E1000_EECD_DI); |
|
4747 if (eecd & E1000_EECD_DO) |
|
4748 data |= 1; |
|
4749 |
|
4750 e1000_lower_ee_clk(hw, &eecd); |
|
4751 } |
|
4752 |
|
4753 return data; |
|
4754 } |
|
4755 |
|
4756 /****************************************************************************** |
|
4757 * Prepares EEPROM for access |
|
4758 * |
|
4759 * hw - Struct containing variables accessed by shared code |
|
4760 * |
|
4761 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
|
4762 * function should be called before issuing a command to the EEPROM. |
|
4763 *****************************************************************************/ |
|
4764 static int32_t |
|
4765 e1000_acquire_eeprom(struct e1000_hw *hw) |
|
4766 { |
|
4767 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4768 uint32_t eecd, i=0; |
|
4769 |
|
4770 DEBUGFUNC("e1000_acquire_eeprom"); |
|
4771 |
|
4772 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
|
4773 return -E1000_ERR_SWFW_SYNC; |
|
4774 eecd = E1000_READ_REG(hw, EECD); |
|
4775 |
|
4776 if (hw->mac_type != e1000_82573) { |
|
4777 /* Request EEPROM Access */ |
|
4778 if (hw->mac_type > e1000_82544) { |
|
4779 eecd |= E1000_EECD_REQ; |
|
4780 E1000_WRITE_REG(hw, EECD, eecd); |
|
4781 eecd = E1000_READ_REG(hw, EECD); |
|
4782 while ((!(eecd & E1000_EECD_GNT)) && |
|
4783 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
|
4784 i++; |
|
4785 udelay(5); |
|
4786 eecd = E1000_READ_REG(hw, EECD); |
|
4787 } |
|
4788 if (!(eecd & E1000_EECD_GNT)) { |
|
4789 eecd &= ~E1000_EECD_REQ; |
|
4790 E1000_WRITE_REG(hw, EECD, eecd); |
|
4791 DEBUGOUT("Could not acquire EEPROM grant\n"); |
|
4792 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
4793 return -E1000_ERR_EEPROM; |
|
4794 } |
|
4795 } |
|
4796 } |
|
4797 |
|
4798 /* Setup EEPROM for Read/Write */ |
|
4799 |
|
4800 if (eeprom->type == e1000_eeprom_microwire) { |
|
4801 /* Clear SK and DI */ |
|
4802 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
|
4803 E1000_WRITE_REG(hw, EECD, eecd); |
|
4804 |
|
4805 /* Set CS */ |
|
4806 eecd |= E1000_EECD_CS; |
|
4807 E1000_WRITE_REG(hw, EECD, eecd); |
|
4808 } else if (eeprom->type == e1000_eeprom_spi) { |
|
4809 /* Clear SK and CS */ |
|
4810 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
4811 E1000_WRITE_REG(hw, EECD, eecd); |
|
4812 udelay(1); |
|
4813 } |
|
4814 |
|
4815 return E1000_SUCCESS; |
|
4816 } |
|
4817 |
|
4818 /****************************************************************************** |
|
4819 * Returns EEPROM to a "standby" state |
|
4820 * |
|
4821 * hw - Struct containing variables accessed by shared code |
|
4822 *****************************************************************************/ |
|
4823 static void |
|
4824 e1000_standby_eeprom(struct e1000_hw *hw) |
|
4825 { |
|
4826 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4827 uint32_t eecd; |
|
4828 |
|
4829 eecd = E1000_READ_REG(hw, EECD); |
|
4830 |
|
4831 if (eeprom->type == e1000_eeprom_microwire) { |
|
4832 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
|
4833 E1000_WRITE_REG(hw, EECD, eecd); |
|
4834 E1000_WRITE_FLUSH(hw); |
|
4835 udelay(eeprom->delay_usec); |
|
4836 |
|
4837 /* Clock high */ |
|
4838 eecd |= E1000_EECD_SK; |
|
4839 E1000_WRITE_REG(hw, EECD, eecd); |
|
4840 E1000_WRITE_FLUSH(hw); |
|
4841 udelay(eeprom->delay_usec); |
|
4842 |
|
4843 /* Select EEPROM */ |
|
4844 eecd |= E1000_EECD_CS; |
|
4845 E1000_WRITE_REG(hw, EECD, eecd); |
|
4846 E1000_WRITE_FLUSH(hw); |
|
4847 udelay(eeprom->delay_usec); |
|
4848 |
|
4849 /* Clock low */ |
|
4850 eecd &= ~E1000_EECD_SK; |
|
4851 E1000_WRITE_REG(hw, EECD, eecd); |
|
4852 E1000_WRITE_FLUSH(hw); |
|
4853 udelay(eeprom->delay_usec); |
|
4854 } else if (eeprom->type == e1000_eeprom_spi) { |
|
4855 /* Toggle CS to flush commands */ |
|
4856 eecd |= E1000_EECD_CS; |
|
4857 E1000_WRITE_REG(hw, EECD, eecd); |
|
4858 E1000_WRITE_FLUSH(hw); |
|
4859 udelay(eeprom->delay_usec); |
|
4860 eecd &= ~E1000_EECD_CS; |
|
4861 E1000_WRITE_REG(hw, EECD, eecd); |
|
4862 E1000_WRITE_FLUSH(hw); |
|
4863 udelay(eeprom->delay_usec); |
|
4864 } |
|
4865 } |
|
4866 |
|
4867 /****************************************************************************** |
|
4868 * Terminates a command by inverting the EEPROM's chip select pin |
|
4869 * |
|
4870 * hw - Struct containing variables accessed by shared code |
|
4871 *****************************************************************************/ |
|
4872 static void |
|
4873 e1000_release_eeprom(struct e1000_hw *hw) |
|
4874 { |
|
4875 uint32_t eecd; |
|
4876 |
|
4877 DEBUGFUNC("e1000_release_eeprom"); |
|
4878 |
|
4879 eecd = E1000_READ_REG(hw, EECD); |
|
4880 |
|
4881 if (hw->eeprom.type == e1000_eeprom_spi) { |
|
4882 eecd |= E1000_EECD_CS; /* Pull CS high */ |
|
4883 eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
|
4884 |
|
4885 E1000_WRITE_REG(hw, EECD, eecd); |
|
4886 |
|
4887 udelay(hw->eeprom.delay_usec); |
|
4888 } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
|
4889 /* cleanup eeprom */ |
|
4890 |
|
4891 /* CS on Microwire is active-high */ |
|
4892 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
|
4893 |
|
4894 E1000_WRITE_REG(hw, EECD, eecd); |
|
4895 |
|
4896 /* Rising edge of clock */ |
|
4897 eecd |= E1000_EECD_SK; |
|
4898 E1000_WRITE_REG(hw, EECD, eecd); |
|
4899 E1000_WRITE_FLUSH(hw); |
|
4900 udelay(hw->eeprom.delay_usec); |
|
4901 |
|
4902 /* Falling edge of clock */ |
|
4903 eecd &= ~E1000_EECD_SK; |
|
4904 E1000_WRITE_REG(hw, EECD, eecd); |
|
4905 E1000_WRITE_FLUSH(hw); |
|
4906 udelay(hw->eeprom.delay_usec); |
|
4907 } |
|
4908 |
|
4909 /* Stop requesting EEPROM access */ |
|
4910 if (hw->mac_type > e1000_82544) { |
|
4911 eecd &= ~E1000_EECD_REQ; |
|
4912 E1000_WRITE_REG(hw, EECD, eecd); |
|
4913 } |
|
4914 |
|
4915 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
4916 } |
|
4917 |
|
4918 /****************************************************************************** |
|
4919 * Reads a 16 bit word from the EEPROM. |
|
4920 * |
|
4921 * hw - Struct containing variables accessed by shared code |
|
4922 *****************************************************************************/ |
|
4923 static int32_t |
|
4924 e1000_spi_eeprom_ready(struct e1000_hw *hw) |
|
4925 { |
|
4926 uint16_t retry_count = 0; |
|
4927 uint8_t spi_stat_reg; |
|
4928 |
|
4929 DEBUGFUNC("e1000_spi_eeprom_ready"); |
|
4930 |
|
4931 /* Read "Status Register" repeatedly until the LSB is cleared. The |
|
4932 * EEPROM will signal that the command has been completed by clearing |
|
4933 * bit 0 of the internal status register. If it's not cleared within |
|
4934 * 5 milliseconds, then error out. |
|
4935 */ |
|
4936 retry_count = 0; |
|
4937 do { |
|
4938 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
|
4939 hw->eeprom.opcode_bits); |
|
4940 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); |
|
4941 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
|
4942 break; |
|
4943 |
|
4944 udelay(5); |
|
4945 retry_count += 5; |
|
4946 |
|
4947 e1000_standby_eeprom(hw); |
|
4948 } while (retry_count < EEPROM_MAX_RETRY_SPI); |
|
4949 |
|
4950 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
|
4951 * only 0-5mSec on 5V devices) |
|
4952 */ |
|
4953 if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
|
4954 DEBUGOUT("SPI EEPROM Status error\n"); |
|
4955 return -E1000_ERR_EEPROM; |
|
4956 } |
|
4957 |
|
4958 return E1000_SUCCESS; |
|
4959 } |
|
4960 |
|
4961 /****************************************************************************** |
|
4962 * Reads a 16 bit word from the EEPROM. |
|
4963 * |
|
4964 * hw - Struct containing variables accessed by shared code |
|
4965 * offset - offset of word in the EEPROM to read |
|
4966 * data - word read from the EEPROM |
|
4967 * words - number of words to read |
|
4968 *****************************************************************************/ |
|
4969 int32_t |
|
4970 e1000_read_eeprom(struct e1000_hw *hw, |
|
4971 uint16_t offset, |
|
4972 uint16_t words, |
|
4973 uint16_t *data) |
|
4974 { |
|
4975 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
4976 uint32_t i = 0; |
|
4977 |
|
4978 DEBUGFUNC("e1000_read_eeprom"); |
|
4979 |
|
4980 /* If eeprom is not yet detected, do so now */ |
|
4981 if (eeprom->word_size == 0) |
|
4982 e1000_init_eeprom_params(hw); |
|
4983 |
|
4984 /* A check for invalid values: offset too large, too many words, and not |
|
4985 * enough words. |
|
4986 */ |
|
4987 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
|
4988 (words == 0)) { |
|
4989 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); |
|
4990 return -E1000_ERR_EEPROM; |
|
4991 } |
|
4992 |
|
4993 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
|
4994 * directly. In this case, we need to acquire the EEPROM so that |
|
4995 * FW or other port software does not interrupt. |
|
4996 */ |
|
4997 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && |
|
4998 hw->eeprom.use_eerd == FALSE) { |
|
4999 /* Prepare the EEPROM for bit-bang reading */ |
|
5000 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
5001 return -E1000_ERR_EEPROM; |
|
5002 } |
|
5003 |
|
5004 /* Eerd register EEPROM access requires no eeprom aquire/release */ |
|
5005 if (eeprom->use_eerd == TRUE) |
|
5006 return e1000_read_eeprom_eerd(hw, offset, words, data); |
|
5007 |
|
5008 /* ICH EEPROM access is done via the ICH flash controller */ |
|
5009 if (eeprom->type == e1000_eeprom_ich8) |
|
5010 return e1000_read_eeprom_ich8(hw, offset, words, data); |
|
5011 |
|
5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
|
5013 * acquired the EEPROM at this point, so any returns should relase it */ |
|
5014 if (eeprom->type == e1000_eeprom_spi) { |
|
5015 uint16_t word_in; |
|
5016 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
|
5017 |
|
5018 if (e1000_spi_eeprom_ready(hw)) { |
|
5019 e1000_release_eeprom(hw); |
|
5020 return -E1000_ERR_EEPROM; |
|
5021 } |
|
5022 |
|
5023 e1000_standby_eeprom(hw); |
|
5024 |
|
5025 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
5026 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
5027 read_opcode |= EEPROM_A8_OPCODE_SPI; |
|
5028 |
|
5029 /* Send the READ command (opcode + addr) */ |
|
5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
|
5031 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); |
|
5032 |
|
5033 /* Read the data. The address of the eeprom internally increments with |
|
5034 * each byte (spi) being read, saving on the overhead of eeprom setup |
|
5035 * and tear-down. The address counter will roll over if reading beyond |
|
5036 * the size of the eeprom, thus allowing the entire memory to be read |
|
5037 * starting from any offset. */ |
|
5038 for (i = 0; i < words; i++) { |
|
5039 word_in = e1000_shift_in_ee_bits(hw, 16); |
|
5040 data[i] = (word_in >> 8) | (word_in << 8); |
|
5041 } |
|
5042 } else if (eeprom->type == e1000_eeprom_microwire) { |
|
5043 for (i = 0; i < words; i++) { |
|
5044 /* Send the READ command (opcode + addr) */ |
|
5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, |
|
5046 eeprom->opcode_bits); |
|
5047 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
|
5048 eeprom->address_bits); |
|
5049 |
|
5050 /* Read the data. For microwire, each word requires the overhead |
|
5051 * of eeprom setup and tear-down. */ |
|
5052 data[i] = e1000_shift_in_ee_bits(hw, 16); |
|
5053 e1000_standby_eeprom(hw); |
|
5054 } |
|
5055 } |
|
5056 |
|
5057 /* End this read operation */ |
|
5058 e1000_release_eeprom(hw); |
|
5059 |
|
5060 return E1000_SUCCESS; |
|
5061 } |
|
5062 |
|
5063 /****************************************************************************** |
|
5064 * Reads a 16 bit word from the EEPROM using the EERD register. |
|
5065 * |
|
5066 * hw - Struct containing variables accessed by shared code |
|
5067 * offset - offset of word in the EEPROM to read |
|
5068 * data - word read from the EEPROM |
|
5069 * words - number of words to read |
|
5070 *****************************************************************************/ |
|
5071 static int32_t |
|
5072 e1000_read_eeprom_eerd(struct e1000_hw *hw, |
|
5073 uint16_t offset, |
|
5074 uint16_t words, |
|
5075 uint16_t *data) |
|
5076 { |
|
5077 uint32_t i, eerd = 0; |
|
5078 int32_t error = 0; |
|
5079 |
|
5080 for (i = 0; i < words; i++) { |
|
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
|
5082 E1000_EEPROM_RW_REG_START; |
|
5083 |
|
5084 E1000_WRITE_REG(hw, EERD, eerd); |
|
5085 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
|
5086 |
|
5087 if (error) { |
|
5088 break; |
|
5089 } |
|
5090 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
|
5091 |
|
5092 } |
|
5093 |
|
5094 return error; |
|
5095 } |
|
5096 |
|
5097 /****************************************************************************** |
|
5098 * Writes a 16 bit word from the EEPROM using the EEWR register. |
|
5099 * |
|
5100 * hw - Struct containing variables accessed by shared code |
|
5101 * offset - offset of word in the EEPROM to read |
|
5102 * data - word read from the EEPROM |
|
5103 * words - number of words to read |
|
5104 *****************************************************************************/ |
|
5105 static int32_t |
|
5106 e1000_write_eeprom_eewr(struct e1000_hw *hw, |
|
5107 uint16_t offset, |
|
5108 uint16_t words, |
|
5109 uint16_t *data) |
|
5110 { |
|
5111 uint32_t register_value = 0; |
|
5112 uint32_t i = 0; |
|
5113 int32_t error = 0; |
|
5114 |
|
5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
|
5116 return -E1000_ERR_SWFW_SYNC; |
|
5117 |
|
5118 for (i = 0; i < words; i++) { |
|
5119 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
|
5120 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
|
5121 E1000_EEPROM_RW_REG_START; |
|
5122 |
|
5123 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
|
5124 if (error) { |
|
5125 break; |
|
5126 } |
|
5127 |
|
5128 E1000_WRITE_REG(hw, EEWR, register_value); |
|
5129 |
|
5130 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
|
5131 |
|
5132 if (error) { |
|
5133 break; |
|
5134 } |
|
5135 } |
|
5136 |
|
5137 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
|
5138 return error; |
|
5139 } |
|
5140 |
|
5141 /****************************************************************************** |
|
5142 * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
|
5143 * |
|
5144 * hw - Struct containing variables accessed by shared code |
|
5145 *****************************************************************************/ |
|
5146 static int32_t |
|
5147 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
|
5148 { |
|
5149 uint32_t attempts = 100000; |
|
5150 uint32_t i, reg = 0; |
|
5151 int32_t done = E1000_ERR_EEPROM; |
|
5152 |
|
5153 for (i = 0; i < attempts; i++) { |
|
5154 if (eerd == E1000_EEPROM_POLL_READ) |
|
5155 reg = E1000_READ_REG(hw, EERD); |
|
5156 else |
|
5157 reg = E1000_READ_REG(hw, EEWR); |
|
5158 |
|
5159 if (reg & E1000_EEPROM_RW_REG_DONE) { |
|
5160 done = E1000_SUCCESS; |
|
5161 break; |
|
5162 } |
|
5163 udelay(5); |
|
5164 } |
|
5165 |
|
5166 return done; |
|
5167 } |
|
5168 |
|
5169 /*************************************************************************** |
|
5170 * Description: Determines if the onboard NVM is FLASH or EEPROM. |
|
5171 * |
|
5172 * hw - Struct containing variables accessed by shared code |
|
5173 ****************************************************************************/ |
|
5174 static boolean_t |
|
5175 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
|
5176 { |
|
5177 uint32_t eecd = 0; |
|
5178 |
|
5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
|
5180 |
|
5181 if (hw->mac_type == e1000_ich8lan) |
|
5182 return FALSE; |
|
5183 |
|
5184 if (hw->mac_type == e1000_82573) { |
|
5185 eecd = E1000_READ_REG(hw, EECD); |
|
5186 |
|
5187 /* Isolate bits 15 & 16 */ |
|
5188 eecd = ((eecd >> 15) & 0x03); |
|
5189 |
|
5190 /* If both bits are set, device is Flash type */ |
|
5191 if (eecd == 0x03) { |
|
5192 return FALSE; |
|
5193 } |
|
5194 } |
|
5195 return TRUE; |
|
5196 } |
|
5197 |
|
5198 /****************************************************************************** |
|
5199 * Verifies that the EEPROM has a valid checksum |
|
5200 * |
|
5201 * hw - Struct containing variables accessed by shared code |
|
5202 * |
|
5203 * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
|
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
|
5205 * valid. |
|
5206 *****************************************************************************/ |
|
5207 int32_t |
|
5208 e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
|
5209 { |
|
5210 uint16_t checksum = 0; |
|
5211 uint16_t i, eeprom_data; |
|
5212 |
|
5213 DEBUGFUNC("e1000_validate_eeprom_checksum"); |
|
5214 |
|
5215 if ((hw->mac_type == e1000_82573) && |
|
5216 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { |
|
5217 /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
|
5218 * 10h-12h. Checksum may need to be fixed. */ |
|
5219 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); |
|
5220 if ((eeprom_data & 0x10) == 0) { |
|
5221 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum |
|
5222 * has already been fixed. If the checksum is still wrong and this |
|
5223 * bit is a 1, we need to return bad checksum. Otherwise, we need |
|
5224 * to set this bit to a 1 and update the checksum. */ |
|
5225 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); |
|
5226 if ((eeprom_data & 0x8000) == 0) { |
|
5227 eeprom_data |= 0x8000; |
|
5228 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); |
|
5229 e1000_update_eeprom_checksum(hw); |
|
5230 } |
|
5231 } |
|
5232 } |
|
5233 |
|
5234 if (hw->mac_type == e1000_ich8lan) { |
|
5235 /* Drivers must allocate the shadow ram structure for the |
|
5236 * EEPROM checksum to be updated. Otherwise, this bit as well |
|
5237 * as the checksum must both be set correctly for this |
|
5238 * validation to pass. |
|
5239 */ |
|
5240 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); |
|
5241 if ((eeprom_data & 0x40) == 0) { |
|
5242 eeprom_data |= 0x40; |
|
5243 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); |
|
5244 e1000_update_eeprom_checksum(hw); |
|
5245 } |
|
5246 } |
|
5247 |
|
5248 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
|
5249 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
5250 DEBUGOUT("EEPROM Read Error\n"); |
|
5251 return -E1000_ERR_EEPROM; |
|
5252 } |
|
5253 checksum += eeprom_data; |
|
5254 } |
|
5255 |
|
5256 if (checksum == (uint16_t) EEPROM_SUM) |
|
5257 return E1000_SUCCESS; |
|
5258 else { |
|
5259 DEBUGOUT("EEPROM Checksum Invalid\n"); |
|
5260 return -E1000_ERR_EEPROM; |
|
5261 } |
|
5262 } |
|
5263 |
|
5264 /****************************************************************************** |
|
5265 * Calculates the EEPROM checksum and writes it to the EEPROM |
|
5266 * |
|
5267 * hw - Struct containing variables accessed by shared code |
|
5268 * |
|
5269 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
|
5270 * Writes the difference to word offset 63 of the EEPROM. |
|
5271 *****************************************************************************/ |
|
5272 int32_t |
|
5273 e1000_update_eeprom_checksum(struct e1000_hw *hw) |
|
5274 { |
|
5275 uint32_t ctrl_ext; |
|
5276 uint16_t checksum = 0; |
|
5277 uint16_t i, eeprom_data; |
|
5278 |
|
5279 DEBUGFUNC("e1000_update_eeprom_checksum"); |
|
5280 |
|
5281 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
|
5282 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
|
5283 DEBUGOUT("EEPROM Read Error\n"); |
|
5284 return -E1000_ERR_EEPROM; |
|
5285 } |
|
5286 checksum += eeprom_data; |
|
5287 } |
|
5288 checksum = (uint16_t) EEPROM_SUM - checksum; |
|
5289 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
|
5290 DEBUGOUT("EEPROM Write Error\n"); |
|
5291 return -E1000_ERR_EEPROM; |
|
5292 } else if (hw->eeprom.type == e1000_eeprom_flash) { |
|
5293 e1000_commit_shadow_ram(hw); |
|
5294 } else if (hw->eeprom.type == e1000_eeprom_ich8) { |
|
5295 e1000_commit_shadow_ram(hw); |
|
5296 /* Reload the EEPROM, or else modifications will not appear |
|
5297 * until after next adapter reset. */ |
|
5298 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
5299 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
5300 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
5301 msleep(10); |
|
5302 } |
|
5303 return E1000_SUCCESS; |
|
5304 } |
|
5305 |
|
5306 /****************************************************************************** |
|
5307 * Parent function for writing words to the different EEPROM types. |
|
5308 * |
|
5309 * hw - Struct containing variables accessed by shared code |
|
5310 * offset - offset within the EEPROM to be written to |
|
5311 * words - number of words to write |
|
5312 * data - 16 bit word to be written to the EEPROM |
|
5313 * |
|
5314 * If e1000_update_eeprom_checksum is not called after this function, the |
|
5315 * EEPROM will most likely contain an invalid checksum. |
|
5316 *****************************************************************************/ |
|
5317 int32_t |
|
5318 e1000_write_eeprom(struct e1000_hw *hw, |
|
5319 uint16_t offset, |
|
5320 uint16_t words, |
|
5321 uint16_t *data) |
|
5322 { |
|
5323 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5324 int32_t status = 0; |
|
5325 |
|
5326 DEBUGFUNC("e1000_write_eeprom"); |
|
5327 |
|
5328 /* If eeprom is not yet detected, do so now */ |
|
5329 if (eeprom->word_size == 0) |
|
5330 e1000_init_eeprom_params(hw); |
|
5331 |
|
5332 /* A check for invalid values: offset too large, too many words, and not |
|
5333 * enough words. |
|
5334 */ |
|
5335 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
|
5336 (words == 0)) { |
|
5337 DEBUGOUT("\"words\" parameter out of bounds\n"); |
|
5338 return -E1000_ERR_EEPROM; |
|
5339 } |
|
5340 |
|
5341 /* 82573 writes only through eewr */ |
|
5342 if (eeprom->use_eewr == TRUE) |
|
5343 return e1000_write_eeprom_eewr(hw, offset, words, data); |
|
5344 |
|
5345 if (eeprom->type == e1000_eeprom_ich8) |
|
5346 return e1000_write_eeprom_ich8(hw, offset, words, data); |
|
5347 |
|
5348 /* Prepare the EEPROM for writing */ |
|
5349 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
|
5350 return -E1000_ERR_EEPROM; |
|
5351 |
|
5352 if (eeprom->type == e1000_eeprom_microwire) { |
|
5353 status = e1000_write_eeprom_microwire(hw, offset, words, data); |
|
5354 } else { |
|
5355 status = e1000_write_eeprom_spi(hw, offset, words, data); |
|
5356 msleep(10); |
|
5357 } |
|
5358 |
|
5359 /* Done with writing */ |
|
5360 e1000_release_eeprom(hw); |
|
5361 |
|
5362 return status; |
|
5363 } |
|
5364 |
|
5365 /****************************************************************************** |
|
5366 * Writes a 16 bit word to a given offset in an SPI EEPROM. |
|
5367 * |
|
5368 * hw - Struct containing variables accessed by shared code |
|
5369 * offset - offset within the EEPROM to be written to |
|
5370 * words - number of words to write |
|
5371 * data - pointer to array of 8 bit words to be written to the EEPROM |
|
5372 * |
|
5373 *****************************************************************************/ |
|
5374 static int32_t |
|
5375 e1000_write_eeprom_spi(struct e1000_hw *hw, |
|
5376 uint16_t offset, |
|
5377 uint16_t words, |
|
5378 uint16_t *data) |
|
5379 { |
|
5380 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5381 uint16_t widx = 0; |
|
5382 |
|
5383 DEBUGFUNC("e1000_write_eeprom_spi"); |
|
5384 |
|
5385 while (widx < words) { |
|
5386 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; |
|
5387 |
|
5388 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
|
5389 |
|
5390 e1000_standby_eeprom(hw); |
|
5391 |
|
5392 /* Send the WRITE ENABLE command (8 bit opcode ) */ |
|
5393 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
|
5394 eeprom->opcode_bits); |
|
5395 |
|
5396 e1000_standby_eeprom(hw); |
|
5397 |
|
5398 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
|
5399 if ((eeprom->address_bits == 8) && (offset >= 128)) |
|
5400 write_opcode |= EEPROM_A8_OPCODE_SPI; |
|
5401 |
|
5402 /* Send the Write command (8-bit opcode + addr) */ |
|
5403 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
|
5404 |
|
5405 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), |
|
5406 eeprom->address_bits); |
|
5407 |
|
5408 /* Send the data */ |
|
5409 |
|
5410 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
|
5411 while (widx < words) { |
|
5412 uint16_t word_out = data[widx]; |
|
5413 word_out = (word_out >> 8) | (word_out << 8); |
|
5414 e1000_shift_out_ee_bits(hw, word_out, 16); |
|
5415 widx++; |
|
5416 |
|
5417 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
|
5418 * operation, while the smaller eeproms are capable of an 8-byte |
|
5419 * PAGE WRITE operation. Break the inner loop to pass new address |
|
5420 */ |
|
5421 if ((((offset + widx)*2) % eeprom->page_size) == 0) { |
|
5422 e1000_standby_eeprom(hw); |
|
5423 break; |
|
5424 } |
|
5425 } |
|
5426 } |
|
5427 |
|
5428 return E1000_SUCCESS; |
|
5429 } |
|
5430 |
|
5431 /****************************************************************************** |
|
5432 * Writes a 16 bit word to a given offset in a Microwire EEPROM. |
|
5433 * |
|
5434 * hw - Struct containing variables accessed by shared code |
|
5435 * offset - offset within the EEPROM to be written to |
|
5436 * words - number of words to write |
|
5437 * data - pointer to array of 16 bit words to be written to the EEPROM |
|
5438 * |
|
5439 *****************************************************************************/ |
|
5440 static int32_t |
|
5441 e1000_write_eeprom_microwire(struct e1000_hw *hw, |
|
5442 uint16_t offset, |
|
5443 uint16_t words, |
|
5444 uint16_t *data) |
|
5445 { |
|
5446 struct e1000_eeprom_info *eeprom = &hw->eeprom; |
|
5447 uint32_t eecd; |
|
5448 uint16_t words_written = 0; |
|
5449 uint16_t i = 0; |
|
5450 |
|
5451 DEBUGFUNC("e1000_write_eeprom_microwire"); |
|
5452 |
|
5453 /* Send the write enable command to the EEPROM (3-bit opcode plus |
|
5454 * 6/8-bit dummy address beginning with 11). It's less work to include |
|
5455 * the 11 of the dummy address as part of the opcode than it is to shift |
|
5456 * it over the correct number of bits for the address. This puts the |
|
5457 * EEPROM into write/erase mode. |
|
5458 */ |
|
5459 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
|
5460 (uint16_t)(eeprom->opcode_bits + 2)); |
|
5461 |
|
5462 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
|
5463 |
|
5464 /* Prepare the EEPROM */ |
|
5465 e1000_standby_eeprom(hw); |
|
5466 |
|
5467 while (words_written < words) { |
|
5468 /* Send the Write command (3-bit opcode + addr) */ |
|
5469 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
|
5470 eeprom->opcode_bits); |
|
5471 |
|
5472 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), |
|
5473 eeprom->address_bits); |
|
5474 |
|
5475 /* Send the data */ |
|
5476 e1000_shift_out_ee_bits(hw, data[words_written], 16); |
|
5477 |
|
5478 /* Toggle the CS line. This in effect tells the EEPROM to execute |
|
5479 * the previous command. |
|
5480 */ |
|
5481 e1000_standby_eeprom(hw); |
|
5482 |
|
5483 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
|
5484 * signal that the command has been completed by raising the DO signal. |
|
5485 * If DO does not go high in 10 milliseconds, then error out. |
|
5486 */ |
|
5487 for (i = 0; i < 200; i++) { |
|
5488 eecd = E1000_READ_REG(hw, EECD); |
|
5489 if (eecd & E1000_EECD_DO) break; |
|
5490 udelay(50); |
|
5491 } |
|
5492 if (i == 200) { |
|
5493 DEBUGOUT("EEPROM Write did not complete\n"); |
|
5494 return -E1000_ERR_EEPROM; |
|
5495 } |
|
5496 |
|
5497 /* Recover from write */ |
|
5498 e1000_standby_eeprom(hw); |
|
5499 |
|
5500 words_written++; |
|
5501 } |
|
5502 |
|
5503 /* Send the write disable command to the EEPROM (3-bit opcode plus |
|
5504 * 6/8-bit dummy address beginning with 10). It's less work to include |
|
5505 * the 10 of the dummy address as part of the opcode than it is to shift |
|
5506 * it over the correct number of bits for the address. This takes the |
|
5507 * EEPROM out of write/erase mode. |
|
5508 */ |
|
5509 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
|
5510 (uint16_t)(eeprom->opcode_bits + 2)); |
|
5511 |
|
5512 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
|
5513 |
|
5514 return E1000_SUCCESS; |
|
5515 } |
|
5516 |
|
5517 /****************************************************************************** |
|
5518 * Flushes the cached eeprom to NVM. This is done by saving the modified values |
|
5519 * in the eeprom cache and the non modified values in the currently active bank |
|
5520 * to the new bank. |
|
5521 * |
|
5522 * hw - Struct containing variables accessed by shared code |
|
5523 * offset - offset of word in the EEPROM to read |
|
5524 * data - word read from the EEPROM |
|
5525 * words - number of words to read |
|
5526 *****************************************************************************/ |
|
5527 static int32_t |
|
5528 e1000_commit_shadow_ram(struct e1000_hw *hw) |
|
5529 { |
|
5530 uint32_t attempts = 100000; |
|
5531 uint32_t eecd = 0; |
|
5532 uint32_t flop = 0; |
|
5533 uint32_t i = 0; |
|
5534 int32_t error = E1000_SUCCESS; |
|
5535 uint32_t old_bank_offset = 0; |
|
5536 uint32_t new_bank_offset = 0; |
|
5537 uint8_t low_byte = 0; |
|
5538 uint8_t high_byte = 0; |
|
5539 boolean_t sector_write_failed = FALSE; |
|
5540 |
|
5541 if (hw->mac_type == e1000_82573) { |
|
5542 /* The flop register will be used to determine if flash type is STM */ |
|
5543 flop = E1000_READ_REG(hw, FLOP); |
|
5544 for (i=0; i < attempts; i++) { |
|
5545 eecd = E1000_READ_REG(hw, EECD); |
|
5546 if ((eecd & E1000_EECD_FLUPD) == 0) { |
|
5547 break; |
|
5548 } |
|
5549 udelay(5); |
|
5550 } |
|
5551 |
|
5552 if (i == attempts) { |
|
5553 return -E1000_ERR_EEPROM; |
|
5554 } |
|
5555 |
|
5556 /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
|
5557 if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
|
5558 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
|
5559 } |
|
5560 |
|
5561 /* Perform the flash update */ |
|
5562 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
|
5563 |
|
5564 for (i=0; i < attempts; i++) { |
|
5565 eecd = E1000_READ_REG(hw, EECD); |
|
5566 if ((eecd & E1000_EECD_FLUPD) == 0) { |
|
5567 break; |
|
5568 } |
|
5569 udelay(5); |
|
5570 } |
|
5571 |
|
5572 if (i == attempts) { |
|
5573 return -E1000_ERR_EEPROM; |
|
5574 } |
|
5575 } |
|
5576 |
|
5577 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { |
|
5578 /* We're writing to the opposite bank so if we're on bank 1, |
|
5579 * write to bank 0 etc. We also need to erase the segment that |
|
5580 * is going to be written */ |
|
5581 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { |
|
5582 new_bank_offset = hw->flash_bank_size * 2; |
|
5583 old_bank_offset = 0; |
|
5584 e1000_erase_ich8_4k_segment(hw, 1); |
|
5585 } else { |
|
5586 old_bank_offset = hw->flash_bank_size * 2; |
|
5587 new_bank_offset = 0; |
|
5588 e1000_erase_ich8_4k_segment(hw, 0); |
|
5589 } |
|
5590 |
|
5591 sector_write_failed = FALSE; |
|
5592 /* Loop for every byte in the shadow RAM, |
|
5593 * which is in units of words. */ |
|
5594 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
|
5595 /* Determine whether to write the value stored |
|
5596 * in the other NVM bank or a modified value stored |
|
5597 * in the shadow RAM */ |
|
5598 if (hw->eeprom_shadow_ram[i].modified == TRUE) { |
|
5599 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; |
|
5600 udelay(100); |
|
5601 error = e1000_verify_write_ich8_byte(hw, |
|
5602 (i << 1) + new_bank_offset, low_byte); |
|
5603 |
|
5604 if (error != E1000_SUCCESS) |
|
5605 sector_write_failed = TRUE; |
|
5606 else { |
|
5607 high_byte = |
|
5608 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); |
|
5609 udelay(100); |
|
5610 } |
|
5611 } else { |
|
5612 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, |
|
5613 &low_byte); |
|
5614 udelay(100); |
|
5615 error = e1000_verify_write_ich8_byte(hw, |
|
5616 (i << 1) + new_bank_offset, low_byte); |
|
5617 |
|
5618 if (error != E1000_SUCCESS) |
|
5619 sector_write_failed = TRUE; |
|
5620 else { |
|
5621 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
|
5622 &high_byte); |
|
5623 udelay(100); |
|
5624 } |
|
5625 } |
|
5626 |
|
5627 /* If the write of the low byte was successful, go ahread and |
|
5628 * write the high byte while checking to make sure that if it |
|
5629 * is the signature byte, then it is handled properly */ |
|
5630 if (sector_write_failed == FALSE) { |
|
5631 /* If the word is 0x13, then make sure the signature bits |
|
5632 * (15:14) are 11b until the commit has completed. |
|
5633 * This will allow us to write 10b which indicates the |
|
5634 * signature is valid. We want to do this after the write |
|
5635 * has completed so that we don't mark the segment valid |
|
5636 * while the write is still in progress */ |
|
5637 if (i == E1000_ICH_NVM_SIG_WORD) |
|
5638 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; |
|
5639 |
|
5640 error = e1000_verify_write_ich8_byte(hw, |
|
5641 (i << 1) + new_bank_offset + 1, high_byte); |
|
5642 if (error != E1000_SUCCESS) |
|
5643 sector_write_failed = TRUE; |
|
5644 |
|
5645 } else { |
|
5646 /* If the write failed then break from the loop and |
|
5647 * return an error */ |
|
5648 break; |
|
5649 } |
|
5650 } |
|
5651 |
|
5652 /* Don't bother writing the segment valid bits if sector |
|
5653 * programming failed. */ |
|
5654 if (sector_write_failed == FALSE) { |
|
5655 /* Finally validate the new segment by setting bit 15:14 |
|
5656 * to 10b in word 0x13 , this can be done without an |
|
5657 * erase as well since these bits are 11 to start with |
|
5658 * and we need to change bit 14 to 0b */ |
|
5659 e1000_read_ich8_byte(hw, |
|
5660 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
|
5661 &high_byte); |
|
5662 high_byte &= 0xBF; |
|
5663 error = e1000_verify_write_ich8_byte(hw, |
|
5664 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); |
|
5665 /* And invalidate the previously valid segment by setting |
|
5666 * its signature word (0x13) high_byte to 0b. This can be |
|
5667 * done without an erase because flash erase sets all bits |
|
5668 * to 1's. We can write 1's to 0's without an erase */ |
|
5669 if (error == E1000_SUCCESS) { |
|
5670 error = e1000_verify_write_ich8_byte(hw, |
|
5671 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); |
|
5672 } |
|
5673 |
|
5674 /* Clear the now not used entry in the cache */ |
|
5675 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
|
5676 hw->eeprom_shadow_ram[i].modified = FALSE; |
|
5677 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
|
5678 } |
|
5679 } |
|
5680 } |
|
5681 |
|
5682 return error; |
|
5683 } |
|
5684 |
|
5685 /****************************************************************************** |
|
5686 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
|
5687 * second function of dual function devices |
|
5688 * |
|
5689 * hw - Struct containing variables accessed by shared code |
|
5690 *****************************************************************************/ |
|
5691 int32_t |
|
5692 e1000_read_mac_addr(struct e1000_hw * hw) |
|
5693 { |
|
5694 uint16_t offset; |
|
5695 uint16_t eeprom_data, i; |
|
5696 |
|
5697 DEBUGFUNC("e1000_read_mac_addr"); |
|
5698 |
|
5699 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
|
5700 offset = i >> 1; |
|
5701 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
|
5702 DEBUGOUT("EEPROM Read Error\n"); |
|
5703 return -E1000_ERR_EEPROM; |
|
5704 } |
|
5705 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
|
5706 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
|
5707 } |
|
5708 |
|
5709 switch (hw->mac_type) { |
|
5710 default: |
|
5711 break; |
|
5712 case e1000_82546: |
|
5713 case e1000_82546_rev_3: |
|
5714 case e1000_82571: |
|
5715 case e1000_80003es2lan: |
|
5716 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
|
5717 hw->perm_mac_addr[5] ^= 0x01; |
|
5718 break; |
|
5719 } |
|
5720 |
|
5721 for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
|
5722 hw->mac_addr[i] = hw->perm_mac_addr[i]; |
|
5723 return E1000_SUCCESS; |
|
5724 } |
|
5725 |
|
5726 /****************************************************************************** |
|
5727 * Initializes receive address filters. |
|
5728 * |
|
5729 * hw - Struct containing variables accessed by shared code |
|
5730 * |
|
5731 * Places the MAC address in receive address register 0 and clears the rest |
|
5732 * of the receive addresss registers. Clears the multicast table. Assumes |
|
5733 * the receiver is in reset when the routine is called. |
|
5734 *****************************************************************************/ |
|
5735 static void |
|
5736 e1000_init_rx_addrs(struct e1000_hw *hw) |
|
5737 { |
|
5738 uint32_t i; |
|
5739 uint32_t rar_num; |
|
5740 |
|
5741 DEBUGFUNC("e1000_init_rx_addrs"); |
|
5742 |
|
5743 /* Setup the receive address. */ |
|
5744 DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
|
5745 |
|
5746 e1000_rar_set(hw, hw->mac_addr, 0); |
|
5747 |
|
5748 rar_num = E1000_RAR_ENTRIES; |
|
5749 |
|
5750 /* Reserve a spot for the Locally Administered Address to work around |
|
5751 * an 82571 issue in which a reset on one port will reload the MAC on |
|
5752 * the other port. */ |
|
5753 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
|
5754 rar_num -= 1; |
|
5755 if (hw->mac_type == e1000_ich8lan) |
|
5756 rar_num = E1000_RAR_ENTRIES_ICH8LAN; |
|
5757 |
|
5758 /* Zero out the other 15 receive addresses. */ |
|
5759 DEBUGOUT("Clearing RAR[1-15]\n"); |
|
5760 for (i = 1; i < rar_num; i++) { |
|
5761 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
|
5762 E1000_WRITE_FLUSH(hw); |
|
5763 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
|
5764 E1000_WRITE_FLUSH(hw); |
|
5765 } |
|
5766 } |
|
5767 |
|
5768 /****************************************************************************** |
|
5769 * Hashes an address to determine its location in the multicast table |
|
5770 * |
|
5771 * hw - Struct containing variables accessed by shared code |
|
5772 * mc_addr - the multicast address to hash |
|
5773 *****************************************************************************/ |
|
5774 uint32_t |
|
5775 e1000_hash_mc_addr(struct e1000_hw *hw, |
|
5776 uint8_t *mc_addr) |
|
5777 { |
|
5778 uint32_t hash_value = 0; |
|
5779 |
|
5780 /* The portion of the address that is used for the hash table is |
|
5781 * determined by the mc_filter_type setting. |
|
5782 */ |
|
5783 switch (hw->mc_filter_type) { |
|
5784 /* [0] [1] [2] [3] [4] [5] |
|
5785 * 01 AA 00 12 34 56 |
|
5786 * LSB MSB |
|
5787 */ |
|
5788 case 0: |
|
5789 if (hw->mac_type == e1000_ich8lan) { |
|
5790 /* [47:38] i.e. 0x158 for above example address */ |
|
5791 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); |
|
5792 } else { |
|
5793 /* [47:36] i.e. 0x563 for above example address */ |
|
5794 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
|
5795 } |
|
5796 break; |
|
5797 case 1: |
|
5798 if (hw->mac_type == e1000_ich8lan) { |
|
5799 /* [46:37] i.e. 0x2B1 for above example address */ |
|
5800 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); |
|
5801 } else { |
|
5802 /* [46:35] i.e. 0xAC6 for above example address */ |
|
5803 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); |
|
5804 } |
|
5805 break; |
|
5806 case 2: |
|
5807 if (hw->mac_type == e1000_ich8lan) { |
|
5808 /*[45:36] i.e. 0x163 for above example address */ |
|
5809 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
|
5810 } else { |
|
5811 /* [45:34] i.e. 0x5D8 for above example address */ |
|
5812 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
|
5813 } |
|
5814 break; |
|
5815 case 3: |
|
5816 if (hw->mac_type == e1000_ich8lan) { |
|
5817 /* [43:34] i.e. 0x18D for above example address */ |
|
5818 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
|
5819 } else { |
|
5820 /* [43:32] i.e. 0x634 for above example address */ |
|
5821 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); |
|
5822 } |
|
5823 break; |
|
5824 } |
|
5825 |
|
5826 hash_value &= 0xFFF; |
|
5827 if (hw->mac_type == e1000_ich8lan) |
|
5828 hash_value &= 0x3FF; |
|
5829 |
|
5830 return hash_value; |
|
5831 } |
|
5832 |
|
5833 /****************************************************************************** |
|
5834 * Sets the bit in the multicast table corresponding to the hash value. |
|
5835 * |
|
5836 * hw - Struct containing variables accessed by shared code |
|
5837 * hash_value - Multicast address hash value |
|
5838 *****************************************************************************/ |
|
5839 void |
|
5840 e1000_mta_set(struct e1000_hw *hw, |
|
5841 uint32_t hash_value) |
|
5842 { |
|
5843 uint32_t hash_bit, hash_reg; |
|
5844 uint32_t mta; |
|
5845 uint32_t temp; |
|
5846 |
|
5847 /* The MTA is a register array of 128 32-bit registers. |
|
5848 * It is treated like an array of 4096 bits. We want to set |
|
5849 * bit BitArray[hash_value]. So we figure out what register |
|
5850 * the bit is in, read it, OR in the new bit, then write |
|
5851 * back the new value. The register is determined by the |
|
5852 * upper 7 bits of the hash value and the bit within that |
|
5853 * register are determined by the lower 5 bits of the value. |
|
5854 */ |
|
5855 hash_reg = (hash_value >> 5) & 0x7F; |
|
5856 if (hw->mac_type == e1000_ich8lan) |
|
5857 hash_reg &= 0x1F; |
|
5858 |
|
5859 hash_bit = hash_value & 0x1F; |
|
5860 |
|
5861 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); |
|
5862 |
|
5863 mta |= (1 << hash_bit); |
|
5864 |
|
5865 /* If we are on an 82544 and we are trying to write an odd offset |
|
5866 * in the MTA, save off the previous entry before writing and |
|
5867 * restore the old value after writing. |
|
5868 */ |
|
5869 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { |
|
5870 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
|
5871 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
|
5872 E1000_WRITE_FLUSH(hw); |
|
5873 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
|
5874 E1000_WRITE_FLUSH(hw); |
|
5875 } else { |
|
5876 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
|
5877 E1000_WRITE_FLUSH(hw); |
|
5878 } |
|
5879 } |
|
5880 |
|
5881 /****************************************************************************** |
|
5882 * Puts an ethernet address into a receive address register. |
|
5883 * |
|
5884 * hw - Struct containing variables accessed by shared code |
|
5885 * addr - Address to put into receive address register |
|
5886 * index - Receive address register to write |
|
5887 *****************************************************************************/ |
|
5888 void |
|
5889 e1000_rar_set(struct e1000_hw *hw, |
|
5890 uint8_t *addr, |
|
5891 uint32_t index) |
|
5892 { |
|
5893 uint32_t rar_low, rar_high; |
|
5894 |
|
5895 /* HW expects these in little endian so we reverse the byte order |
|
5896 * from network order (big endian) to little endian |
|
5897 */ |
|
5898 rar_low = ((uint32_t) addr[0] | |
|
5899 ((uint32_t) addr[1] << 8) | |
|
5900 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); |
|
5901 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); |
|
5902 |
|
5903 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
|
5904 * unit hang. |
|
5905 * |
|
5906 * Description: |
|
5907 * If there are any Rx frames queued up or otherwise present in the HW |
|
5908 * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
|
5909 * hang. To work around this issue, we have to disable receives and |
|
5910 * flush out all Rx frames before we enable RSS. To do so, we modify we |
|
5911 * redirect all Rx traffic to manageability and then reset the HW. |
|
5912 * This flushes away Rx frames, and (since the redirections to |
|
5913 * manageability persists across resets) keeps new ones from coming in |
|
5914 * while we work. Then, we clear the Address Valid AV bit for all MAC |
|
5915 * addresses and undo the re-direction to manageability. |
|
5916 * Now, frames are coming in again, but the MAC won't accept them, so |
|
5917 * far so good. We now proceed to initialize RSS (if necessary) and |
|
5918 * configure the Rx unit. Last, we re-enable the AV bits and continue |
|
5919 * on our merry way. |
|
5920 */ |
|
5921 switch (hw->mac_type) { |
|
5922 case e1000_82571: |
|
5923 case e1000_82572: |
|
5924 case e1000_80003es2lan: |
|
5925 if (hw->leave_av_bit_off == TRUE) |
|
5926 break; |
|
5927 default: |
|
5928 /* Indicate to hardware the Address is Valid. */ |
|
5929 rar_high |= E1000_RAH_AV; |
|
5930 break; |
|
5931 } |
|
5932 |
|
5933 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
|
5934 E1000_WRITE_FLUSH(hw); |
|
5935 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
|
5936 E1000_WRITE_FLUSH(hw); |
|
5937 } |
|
5938 |
|
5939 /****************************************************************************** |
|
5940 * Writes a value to the specified offset in the VLAN filter table. |
|
5941 * |
|
5942 * hw - Struct containing variables accessed by shared code |
|
5943 * offset - Offset in VLAN filer table to write |
|
5944 * value - Value to write into VLAN filter table |
|
5945 *****************************************************************************/ |
|
5946 void |
|
5947 e1000_write_vfta(struct e1000_hw *hw, |
|
5948 uint32_t offset, |
|
5949 uint32_t value) |
|
5950 { |
|
5951 uint32_t temp; |
|
5952 |
|
5953 if (hw->mac_type == e1000_ich8lan) |
|
5954 return; |
|
5955 |
|
5956 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
|
5957 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
|
5958 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
5959 E1000_WRITE_FLUSH(hw); |
|
5960 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
|
5961 E1000_WRITE_FLUSH(hw); |
|
5962 } else { |
|
5963 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
|
5964 E1000_WRITE_FLUSH(hw); |
|
5965 } |
|
5966 } |
|
5967 |
|
5968 /****************************************************************************** |
|
5969 * Clears the VLAN filer table |
|
5970 * |
|
5971 * hw - Struct containing variables accessed by shared code |
|
5972 *****************************************************************************/ |
|
5973 static void |
|
5974 e1000_clear_vfta(struct e1000_hw *hw) |
|
5975 { |
|
5976 uint32_t offset; |
|
5977 uint32_t vfta_value = 0; |
|
5978 uint32_t vfta_offset = 0; |
|
5979 uint32_t vfta_bit_in_reg = 0; |
|
5980 |
|
5981 if (hw->mac_type == e1000_ich8lan) |
|
5982 return; |
|
5983 |
|
5984 if (hw->mac_type == e1000_82573) { |
|
5985 if (hw->mng_cookie.vlan_id != 0) { |
|
5986 /* The VFTA is a 4096b bit-field, each identifying a single VLAN |
|
5987 * ID. The following operations determine which 32b entry |
|
5988 * (i.e. offset) into the array we want to set the VLAN ID |
|
5989 * (i.e. bit) of the manageability unit. */ |
|
5990 vfta_offset = (hw->mng_cookie.vlan_id >> |
|
5991 E1000_VFTA_ENTRY_SHIFT) & |
|
5992 E1000_VFTA_ENTRY_MASK; |
|
5993 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
|
5994 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
|
5995 } |
|
5996 } |
|
5997 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
5998 /* If the offset we want to clear is the same offset of the |
|
5999 * manageability VLAN ID, then clear all bits except that of the |
|
6000 * manageability unit */ |
|
6001 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
6002 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
|
6003 E1000_WRITE_FLUSH(hw); |
|
6004 } |
|
6005 } |
|
6006 |
|
6007 static int32_t |
|
6008 e1000_id_led_init(struct e1000_hw * hw) |
|
6009 { |
|
6010 uint32_t ledctl; |
|
6011 const uint32_t ledctl_mask = 0x000000FF; |
|
6012 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
|
6013 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
|
6014 uint16_t eeprom_data, i, temp; |
|
6015 const uint16_t led_mask = 0x0F; |
|
6016 |
|
6017 DEBUGFUNC("e1000_id_led_init"); |
|
6018 |
|
6019 if (hw->mac_type < e1000_82540) { |
|
6020 /* Nothing to do */ |
|
6021 return E1000_SUCCESS; |
|
6022 } |
|
6023 |
|
6024 ledctl = E1000_READ_REG(hw, LEDCTL); |
|
6025 hw->ledctl_default = ledctl; |
|
6026 hw->ledctl_mode1 = hw->ledctl_default; |
|
6027 hw->ledctl_mode2 = hw->ledctl_default; |
|
6028 |
|
6029 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
|
6030 DEBUGOUT("EEPROM Read Error\n"); |
|
6031 return -E1000_ERR_EEPROM; |
|
6032 } |
|
6033 |
|
6034 if ((hw->mac_type == e1000_82573) && |
|
6035 (eeprom_data == ID_LED_RESERVED_82573)) |
|
6036 eeprom_data = ID_LED_DEFAULT_82573; |
|
6037 else if ((eeprom_data == ID_LED_RESERVED_0000) || |
|
6038 (eeprom_data == ID_LED_RESERVED_FFFF)) { |
|
6039 if (hw->mac_type == e1000_ich8lan) |
|
6040 eeprom_data = ID_LED_DEFAULT_ICH8LAN; |
|
6041 else |
|
6042 eeprom_data = ID_LED_DEFAULT; |
|
6043 } |
|
6044 |
|
6045 for (i = 0; i < 4; i++) { |
|
6046 temp = (eeprom_data >> (i << 2)) & led_mask; |
|
6047 switch (temp) { |
|
6048 case ID_LED_ON1_DEF2: |
|
6049 case ID_LED_ON1_ON2: |
|
6050 case ID_LED_ON1_OFF2: |
|
6051 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
6052 hw->ledctl_mode1 |= ledctl_on << (i << 3); |
|
6053 break; |
|
6054 case ID_LED_OFF1_DEF2: |
|
6055 case ID_LED_OFF1_ON2: |
|
6056 case ID_LED_OFF1_OFF2: |
|
6057 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
|
6058 hw->ledctl_mode1 |= ledctl_off << (i << 3); |
|
6059 break; |
|
6060 default: |
|
6061 /* Do nothing */ |
|
6062 break; |
|
6063 } |
|
6064 switch (temp) { |
|
6065 case ID_LED_DEF1_ON2: |
|
6066 case ID_LED_ON1_ON2: |
|
6067 case ID_LED_OFF1_ON2: |
|
6068 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
6069 hw->ledctl_mode2 |= ledctl_on << (i << 3); |
|
6070 break; |
|
6071 case ID_LED_DEF1_OFF2: |
|
6072 case ID_LED_ON1_OFF2: |
|
6073 case ID_LED_OFF1_OFF2: |
|
6074 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
|
6075 hw->ledctl_mode2 |= ledctl_off << (i << 3); |
|
6076 break; |
|
6077 default: |
|
6078 /* Do nothing */ |
|
6079 break; |
|
6080 } |
|
6081 } |
|
6082 return E1000_SUCCESS; |
|
6083 } |
|
6084 |
|
6085 /****************************************************************************** |
|
6086 * Prepares SW controlable LED for use and saves the current state of the LED. |
|
6087 * |
|
6088 * hw - Struct containing variables accessed by shared code |
|
6089 *****************************************************************************/ |
|
6090 int32_t |
|
6091 e1000_setup_led(struct e1000_hw *hw) |
|
6092 { |
|
6093 uint32_t ledctl; |
|
6094 int32_t ret_val = E1000_SUCCESS; |
|
6095 |
|
6096 DEBUGFUNC("e1000_setup_led"); |
|
6097 |
|
6098 switch (hw->mac_type) { |
|
6099 case e1000_82542_rev2_0: |
|
6100 case e1000_82542_rev2_1: |
|
6101 case e1000_82543: |
|
6102 case e1000_82544: |
|
6103 /* No setup necessary */ |
|
6104 break; |
|
6105 case e1000_82541: |
|
6106 case e1000_82547: |
|
6107 case e1000_82541_rev_2: |
|
6108 case e1000_82547_rev_2: |
|
6109 /* Turn off PHY Smart Power Down (if enabled) */ |
|
6110 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6111 &hw->phy_spd_default); |
|
6112 if (ret_val) |
|
6113 return ret_val; |
|
6114 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6115 (uint16_t)(hw->phy_spd_default & |
|
6116 ~IGP01E1000_GMII_SPD)); |
|
6117 if (ret_val) |
|
6118 return ret_val; |
|
6119 /* Fall Through */ |
|
6120 default: |
|
6121 if (hw->media_type == e1000_media_type_fiber) { |
|
6122 ledctl = E1000_READ_REG(hw, LEDCTL); |
|
6123 /* Save current LEDCTL settings */ |
|
6124 hw->ledctl_default = ledctl; |
|
6125 /* Turn off LED0 */ |
|
6126 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
|
6127 E1000_LEDCTL_LED0_BLINK | |
|
6128 E1000_LEDCTL_LED0_MODE_MASK); |
|
6129 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
|
6130 E1000_LEDCTL_LED0_MODE_SHIFT); |
|
6131 E1000_WRITE_REG(hw, LEDCTL, ledctl); |
|
6132 } else if (hw->media_type == e1000_media_type_copper) |
|
6133 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
|
6134 break; |
|
6135 } |
|
6136 |
|
6137 return E1000_SUCCESS; |
|
6138 } |
|
6139 |
|
6140 |
|
6141 /****************************************************************************** |
|
6142 * Used on 82571 and later Si that has LED blink bits. |
|
6143 * Callers must use their own timer and should have already called |
|
6144 * e1000_id_led_init() |
|
6145 * Call e1000_cleanup led() to stop blinking |
|
6146 * |
|
6147 * hw - Struct containing variables accessed by shared code |
|
6148 *****************************************************************************/ |
|
6149 int32_t |
|
6150 e1000_blink_led_start(struct e1000_hw *hw) |
|
6151 { |
|
6152 int16_t i; |
|
6153 uint32_t ledctl_blink = 0; |
|
6154 |
|
6155 DEBUGFUNC("e1000_id_led_blink_on"); |
|
6156 |
|
6157 if (hw->mac_type < e1000_82571) { |
|
6158 /* Nothing to do */ |
|
6159 return E1000_SUCCESS; |
|
6160 } |
|
6161 if (hw->media_type == e1000_media_type_fiber) { |
|
6162 /* always blink LED0 for PCI-E fiber */ |
|
6163 ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
|
6164 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
|
6165 } else { |
|
6166 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ |
|
6167 ledctl_blink = hw->ledctl_mode2; |
|
6168 for (i=0; i < 4; i++) |
|
6169 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
6170 E1000_LEDCTL_MODE_LED_ON) |
|
6171 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); |
|
6172 } |
|
6173 |
|
6174 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); |
|
6175 |
|
6176 return E1000_SUCCESS; |
|
6177 } |
|
6178 |
|
6179 /****************************************************************************** |
|
6180 * Restores the saved state of the SW controlable LED. |
|
6181 * |
|
6182 * hw - Struct containing variables accessed by shared code |
|
6183 *****************************************************************************/ |
|
6184 int32_t |
|
6185 e1000_cleanup_led(struct e1000_hw *hw) |
|
6186 { |
|
6187 int32_t ret_val = E1000_SUCCESS; |
|
6188 |
|
6189 DEBUGFUNC("e1000_cleanup_led"); |
|
6190 |
|
6191 switch (hw->mac_type) { |
|
6192 case e1000_82542_rev2_0: |
|
6193 case e1000_82542_rev2_1: |
|
6194 case e1000_82543: |
|
6195 case e1000_82544: |
|
6196 /* No cleanup necessary */ |
|
6197 break; |
|
6198 case e1000_82541: |
|
6199 case e1000_82547: |
|
6200 case e1000_82541_rev_2: |
|
6201 case e1000_82547_rev_2: |
|
6202 /* Turn on PHY Smart Power Down (if previously enabled) */ |
|
6203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
|
6204 hw->phy_spd_default); |
|
6205 if (ret_val) |
|
6206 return ret_val; |
|
6207 /* Fall Through */ |
|
6208 default: |
|
6209 if (hw->phy_type == e1000_phy_ife) { |
|
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
|
6211 break; |
|
6212 } |
|
6213 /* Restore LEDCTL settings */ |
|
6214 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); |
|
6215 break; |
|
6216 } |
|
6217 |
|
6218 return E1000_SUCCESS; |
|
6219 } |
|
6220 |
|
6221 /****************************************************************************** |
|
6222 * Turns on the software controllable LED |
|
6223 * |
|
6224 * hw - Struct containing variables accessed by shared code |
|
6225 *****************************************************************************/ |
|
6226 int32_t |
|
6227 e1000_led_on(struct e1000_hw *hw) |
|
6228 { |
|
6229 uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
|
6230 |
|
6231 DEBUGFUNC("e1000_led_on"); |
|
6232 |
|
6233 switch (hw->mac_type) { |
|
6234 case e1000_82542_rev2_0: |
|
6235 case e1000_82542_rev2_1: |
|
6236 case e1000_82543: |
|
6237 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
6238 ctrl |= E1000_CTRL_SWDPIN0; |
|
6239 ctrl |= E1000_CTRL_SWDPIO0; |
|
6240 break; |
|
6241 case e1000_82544: |
|
6242 if (hw->media_type == e1000_media_type_fiber) { |
|
6243 /* Set SW Defineable Pin 0 to turn on the LED */ |
|
6244 ctrl |= E1000_CTRL_SWDPIN0; |
|
6245 ctrl |= E1000_CTRL_SWDPIO0; |
|
6246 } else { |
|
6247 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
6248 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6249 ctrl |= E1000_CTRL_SWDPIO0; |
|
6250 } |
|
6251 break; |
|
6252 default: |
|
6253 if (hw->media_type == e1000_media_type_fiber) { |
|
6254 /* Clear SW Defineable Pin 0 to turn on the LED */ |
|
6255 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6256 ctrl |= E1000_CTRL_SWDPIO0; |
|
6257 } else if (hw->phy_type == e1000_phy_ife) { |
|
6258 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
6259 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
|
6260 } else if (hw->media_type == e1000_media_type_copper) { |
|
6261 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
|
6262 return E1000_SUCCESS; |
|
6263 } |
|
6264 break; |
|
6265 } |
|
6266 |
|
6267 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
6268 |
|
6269 return E1000_SUCCESS; |
|
6270 } |
|
6271 |
|
6272 /****************************************************************************** |
|
6273 * Turns off the software controllable LED |
|
6274 * |
|
6275 * hw - Struct containing variables accessed by shared code |
|
6276 *****************************************************************************/ |
|
6277 int32_t |
|
6278 e1000_led_off(struct e1000_hw *hw) |
|
6279 { |
|
6280 uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
|
6281 |
|
6282 DEBUGFUNC("e1000_led_off"); |
|
6283 |
|
6284 switch (hw->mac_type) { |
|
6285 case e1000_82542_rev2_0: |
|
6286 case e1000_82542_rev2_1: |
|
6287 case e1000_82543: |
|
6288 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
6289 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6290 ctrl |= E1000_CTRL_SWDPIO0; |
|
6291 break; |
|
6292 case e1000_82544: |
|
6293 if (hw->media_type == e1000_media_type_fiber) { |
|
6294 /* Clear SW Defineable Pin 0 to turn off the LED */ |
|
6295 ctrl &= ~E1000_CTRL_SWDPIN0; |
|
6296 ctrl |= E1000_CTRL_SWDPIO0; |
|
6297 } else { |
|
6298 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
6299 ctrl |= E1000_CTRL_SWDPIN0; |
|
6300 ctrl |= E1000_CTRL_SWDPIO0; |
|
6301 } |
|
6302 break; |
|
6303 default: |
|
6304 if (hw->media_type == e1000_media_type_fiber) { |
|
6305 /* Set SW Defineable Pin 0 to turn off the LED */ |
|
6306 ctrl |= E1000_CTRL_SWDPIN0; |
|
6307 ctrl |= E1000_CTRL_SWDPIO0; |
|
6308 } else if (hw->phy_type == e1000_phy_ife) { |
|
6309 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
|
6310 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); |
|
6311 } else if (hw->media_type == e1000_media_type_copper) { |
|
6312 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
|
6313 return E1000_SUCCESS; |
|
6314 } |
|
6315 break; |
|
6316 } |
|
6317 |
|
6318 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
6319 |
|
6320 return E1000_SUCCESS; |
|
6321 } |
|
6322 |
|
6323 /****************************************************************************** |
|
6324 * Clears all hardware statistics counters. |
|
6325 * |
|
6326 * hw - Struct containing variables accessed by shared code |
|
6327 *****************************************************************************/ |
|
6328 static void |
|
6329 e1000_clear_hw_cntrs(struct e1000_hw *hw) |
|
6330 { |
|
6331 volatile uint32_t temp; |
|
6332 |
|
6333 temp = E1000_READ_REG(hw, CRCERRS); |
|
6334 temp = E1000_READ_REG(hw, SYMERRS); |
|
6335 temp = E1000_READ_REG(hw, MPC); |
|
6336 temp = E1000_READ_REG(hw, SCC); |
|
6337 temp = E1000_READ_REG(hw, ECOL); |
|
6338 temp = E1000_READ_REG(hw, MCC); |
|
6339 temp = E1000_READ_REG(hw, LATECOL); |
|
6340 temp = E1000_READ_REG(hw, COLC); |
|
6341 temp = E1000_READ_REG(hw, DC); |
|
6342 temp = E1000_READ_REG(hw, SEC); |
|
6343 temp = E1000_READ_REG(hw, RLEC); |
|
6344 temp = E1000_READ_REG(hw, XONRXC); |
|
6345 temp = E1000_READ_REG(hw, XONTXC); |
|
6346 temp = E1000_READ_REG(hw, XOFFRXC); |
|
6347 temp = E1000_READ_REG(hw, XOFFTXC); |
|
6348 temp = E1000_READ_REG(hw, FCRUC); |
|
6349 |
|
6350 if (hw->mac_type != e1000_ich8lan) { |
|
6351 temp = E1000_READ_REG(hw, PRC64); |
|
6352 temp = E1000_READ_REG(hw, PRC127); |
|
6353 temp = E1000_READ_REG(hw, PRC255); |
|
6354 temp = E1000_READ_REG(hw, PRC511); |
|
6355 temp = E1000_READ_REG(hw, PRC1023); |
|
6356 temp = E1000_READ_REG(hw, PRC1522); |
|
6357 } |
|
6358 |
|
6359 temp = E1000_READ_REG(hw, GPRC); |
|
6360 temp = E1000_READ_REG(hw, BPRC); |
|
6361 temp = E1000_READ_REG(hw, MPRC); |
|
6362 temp = E1000_READ_REG(hw, GPTC); |
|
6363 temp = E1000_READ_REG(hw, GORCL); |
|
6364 temp = E1000_READ_REG(hw, GORCH); |
|
6365 temp = E1000_READ_REG(hw, GOTCL); |
|
6366 temp = E1000_READ_REG(hw, GOTCH); |
|
6367 temp = E1000_READ_REG(hw, RNBC); |
|
6368 temp = E1000_READ_REG(hw, RUC); |
|
6369 temp = E1000_READ_REG(hw, RFC); |
|
6370 temp = E1000_READ_REG(hw, ROC); |
|
6371 temp = E1000_READ_REG(hw, RJC); |
|
6372 temp = E1000_READ_REG(hw, TORL); |
|
6373 temp = E1000_READ_REG(hw, TORH); |
|
6374 temp = E1000_READ_REG(hw, TOTL); |
|
6375 temp = E1000_READ_REG(hw, TOTH); |
|
6376 temp = E1000_READ_REG(hw, TPR); |
|
6377 temp = E1000_READ_REG(hw, TPT); |
|
6378 |
|
6379 if (hw->mac_type != e1000_ich8lan) { |
|
6380 temp = E1000_READ_REG(hw, PTC64); |
|
6381 temp = E1000_READ_REG(hw, PTC127); |
|
6382 temp = E1000_READ_REG(hw, PTC255); |
|
6383 temp = E1000_READ_REG(hw, PTC511); |
|
6384 temp = E1000_READ_REG(hw, PTC1023); |
|
6385 temp = E1000_READ_REG(hw, PTC1522); |
|
6386 } |
|
6387 |
|
6388 temp = E1000_READ_REG(hw, MPTC); |
|
6389 temp = E1000_READ_REG(hw, BPTC); |
|
6390 |
|
6391 if (hw->mac_type < e1000_82543) return; |
|
6392 |
|
6393 temp = E1000_READ_REG(hw, ALGNERRC); |
|
6394 temp = E1000_READ_REG(hw, RXERRC); |
|
6395 temp = E1000_READ_REG(hw, TNCRS); |
|
6396 temp = E1000_READ_REG(hw, CEXTERR); |
|
6397 temp = E1000_READ_REG(hw, TSCTC); |
|
6398 temp = E1000_READ_REG(hw, TSCTFC); |
|
6399 |
|
6400 if (hw->mac_type <= e1000_82544) return; |
|
6401 |
|
6402 temp = E1000_READ_REG(hw, MGTPRC); |
|
6403 temp = E1000_READ_REG(hw, MGTPDC); |
|
6404 temp = E1000_READ_REG(hw, MGTPTC); |
|
6405 |
|
6406 if (hw->mac_type <= e1000_82547_rev_2) return; |
|
6407 |
|
6408 temp = E1000_READ_REG(hw, IAC); |
|
6409 temp = E1000_READ_REG(hw, ICRXOC); |
|
6410 |
|
6411 if (hw->mac_type == e1000_ich8lan) return; |
|
6412 |
|
6413 temp = E1000_READ_REG(hw, ICRXPTC); |
|
6414 temp = E1000_READ_REG(hw, ICRXATC); |
|
6415 temp = E1000_READ_REG(hw, ICTXPTC); |
|
6416 temp = E1000_READ_REG(hw, ICTXATC); |
|
6417 temp = E1000_READ_REG(hw, ICTXQEC); |
|
6418 temp = E1000_READ_REG(hw, ICTXQMTC); |
|
6419 temp = E1000_READ_REG(hw, ICRXDMTC); |
|
6420 } |
|
6421 |
|
6422 /****************************************************************************** |
|
6423 * Resets Adaptive IFS to its default state. |
|
6424 * |
|
6425 * hw - Struct containing variables accessed by shared code |
|
6426 * |
|
6427 * Call this after e1000_init_hw. You may override the IFS defaults by setting |
|
6428 * hw->ifs_params_forced to TRUE. However, you must initialize hw-> |
|
6429 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
|
6430 * before calling this function. |
|
6431 *****************************************************************************/ |
|
6432 void |
|
6433 e1000_reset_adaptive(struct e1000_hw *hw) |
|
6434 { |
|
6435 DEBUGFUNC("e1000_reset_adaptive"); |
|
6436 |
|
6437 if (hw->adaptive_ifs) { |
|
6438 if (!hw->ifs_params_forced) { |
|
6439 hw->current_ifs_val = 0; |
|
6440 hw->ifs_min_val = IFS_MIN; |
|
6441 hw->ifs_max_val = IFS_MAX; |
|
6442 hw->ifs_step_size = IFS_STEP; |
|
6443 hw->ifs_ratio = IFS_RATIO; |
|
6444 } |
|
6445 hw->in_ifs_mode = FALSE; |
|
6446 E1000_WRITE_REG(hw, AIT, 0); |
|
6447 } else { |
|
6448 DEBUGOUT("Not in Adaptive IFS mode!\n"); |
|
6449 } |
|
6450 } |
|
6451 |
|
6452 /****************************************************************************** |
|
6453 * Called during the callback/watchdog routine to update IFS value based on |
|
6454 * the ratio of transmits to collisions. |
|
6455 * |
|
6456 * hw - Struct containing variables accessed by shared code |
|
6457 * tx_packets - Number of transmits since last callback |
|
6458 * total_collisions - Number of collisions since last callback |
|
6459 *****************************************************************************/ |
|
6460 void |
|
6461 e1000_update_adaptive(struct e1000_hw *hw) |
|
6462 { |
|
6463 DEBUGFUNC("e1000_update_adaptive"); |
|
6464 |
|
6465 if (hw->adaptive_ifs) { |
|
6466 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { |
|
6467 if (hw->tx_packet_delta > MIN_NUM_XMITS) { |
|
6468 hw->in_ifs_mode = TRUE; |
|
6469 if (hw->current_ifs_val < hw->ifs_max_val) { |
|
6470 if (hw->current_ifs_val == 0) |
|
6471 hw->current_ifs_val = hw->ifs_min_val; |
|
6472 else |
|
6473 hw->current_ifs_val += hw->ifs_step_size; |
|
6474 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); |
|
6475 } |
|
6476 } |
|
6477 } else { |
|
6478 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
|
6479 hw->current_ifs_val = 0; |
|
6480 hw->in_ifs_mode = FALSE; |
|
6481 E1000_WRITE_REG(hw, AIT, 0); |
|
6482 } |
|
6483 } |
|
6484 } else { |
|
6485 DEBUGOUT("Not in Adaptive IFS mode!\n"); |
|
6486 } |
|
6487 } |
|
6488 |
|
6489 /****************************************************************************** |
|
6490 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
|
6491 * |
|
6492 * hw - Struct containing variables accessed by shared code |
|
6493 * frame_len - The length of the frame in question |
|
6494 * mac_addr - The Ethernet destination address of the frame in question |
|
6495 *****************************************************************************/ |
|
6496 void |
|
6497 e1000_tbi_adjust_stats(struct e1000_hw *hw, |
|
6498 struct e1000_hw_stats *stats, |
|
6499 uint32_t frame_len, |
|
6500 uint8_t *mac_addr) |
|
6501 { |
|
6502 uint64_t carry_bit; |
|
6503 |
|
6504 /* First adjust the frame length. */ |
|
6505 frame_len--; |
|
6506 /* We need to adjust the statistics counters, since the hardware |
|
6507 * counters overcount this packet as a CRC error and undercount |
|
6508 * the packet as a good packet |
|
6509 */ |
|
6510 /* This packet should not be counted as a CRC error. */ |
|
6511 stats->crcerrs--; |
|
6512 /* This packet does count as a Good Packet Received. */ |
|
6513 stats->gprc++; |
|
6514 |
|
6515 /* Adjust the Good Octets received counters */ |
|
6516 carry_bit = 0x80000000 & stats->gorcl; |
|
6517 stats->gorcl += frame_len; |
|
6518 /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
|
6519 * Received Count) was one before the addition, |
|
6520 * AND it is zero after, then we lost the carry out, |
|
6521 * need to add one to Gorch (Good Octets Received Count High). |
|
6522 * This could be simplified if all environments supported |
|
6523 * 64-bit integers. |
|
6524 */ |
|
6525 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
|
6526 stats->gorch++; |
|
6527 /* Is this a broadcast or multicast? Check broadcast first, |
|
6528 * since the test for a multicast frame will test positive on |
|
6529 * a broadcast frame. |
|
6530 */ |
|
6531 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
|
6532 /* Broadcast packet */ |
|
6533 stats->bprc++; |
|
6534 else if (*mac_addr & 0x01) |
|
6535 /* Multicast packet */ |
|
6536 stats->mprc++; |
|
6537 |
|
6538 if (frame_len == hw->max_frame_size) { |
|
6539 /* In this case, the hardware has overcounted the number of |
|
6540 * oversize frames. |
|
6541 */ |
|
6542 if (stats->roc > 0) |
|
6543 stats->roc--; |
|
6544 } |
|
6545 |
|
6546 /* Adjust the bin counters when the extra byte put the frame in the |
|
6547 * wrong bin. Remember that the frame_len was adjusted above. |
|
6548 */ |
|
6549 if (frame_len == 64) { |
|
6550 stats->prc64++; |
|
6551 stats->prc127--; |
|
6552 } else if (frame_len == 127) { |
|
6553 stats->prc127++; |
|
6554 stats->prc255--; |
|
6555 } else if (frame_len == 255) { |
|
6556 stats->prc255++; |
|
6557 stats->prc511--; |
|
6558 } else if (frame_len == 511) { |
|
6559 stats->prc511++; |
|
6560 stats->prc1023--; |
|
6561 } else if (frame_len == 1023) { |
|
6562 stats->prc1023++; |
|
6563 stats->prc1522--; |
|
6564 } else if (frame_len == 1522) { |
|
6565 stats->prc1522++; |
|
6566 } |
|
6567 } |
|
6568 |
|
6569 /****************************************************************************** |
|
6570 * Gets the current PCI bus type, speed, and width of the hardware |
|
6571 * |
|
6572 * hw - Struct containing variables accessed by shared code |
|
6573 *****************************************************************************/ |
|
6574 void |
|
6575 e1000_get_bus_info(struct e1000_hw *hw) |
|
6576 { |
|
6577 int32_t ret_val; |
|
6578 uint16_t pci_ex_link_status; |
|
6579 uint32_t status; |
|
6580 |
|
6581 switch (hw->mac_type) { |
|
6582 case e1000_82542_rev2_0: |
|
6583 case e1000_82542_rev2_1: |
|
6584 hw->bus_type = e1000_bus_type_pci; |
|
6585 hw->bus_speed = e1000_bus_speed_unknown; |
|
6586 hw->bus_width = e1000_bus_width_unknown; |
|
6587 break; |
|
6588 case e1000_82571: |
|
6589 case e1000_82572: |
|
6590 case e1000_82573: |
|
6591 case e1000_80003es2lan: |
|
6592 hw->bus_type = e1000_bus_type_pci_express; |
|
6593 hw->bus_speed = e1000_bus_speed_2500; |
|
6594 ret_val = e1000_read_pcie_cap_reg(hw, |
|
6595 PCI_EX_LINK_STATUS, |
|
6596 &pci_ex_link_status); |
|
6597 if (ret_val) |
|
6598 hw->bus_width = e1000_bus_width_unknown; |
|
6599 else |
|
6600 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> |
|
6601 PCI_EX_LINK_WIDTH_SHIFT; |
|
6602 break; |
|
6603 case e1000_ich8lan: |
|
6604 hw->bus_type = e1000_bus_type_pci_express; |
|
6605 hw->bus_speed = e1000_bus_speed_2500; |
|
6606 hw->bus_width = e1000_bus_width_pciex_1; |
|
6607 break; |
|
6608 default: |
|
6609 status = E1000_READ_REG(hw, STATUS); |
|
6610 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
|
6611 e1000_bus_type_pcix : e1000_bus_type_pci; |
|
6612 |
|
6613 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
|
6614 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
|
6615 e1000_bus_speed_66 : e1000_bus_speed_120; |
|
6616 } else if (hw->bus_type == e1000_bus_type_pci) { |
|
6617 hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
|
6618 e1000_bus_speed_66 : e1000_bus_speed_33; |
|
6619 } else { |
|
6620 switch (status & E1000_STATUS_PCIX_SPEED) { |
|
6621 case E1000_STATUS_PCIX_SPEED_66: |
|
6622 hw->bus_speed = e1000_bus_speed_66; |
|
6623 break; |
|
6624 case E1000_STATUS_PCIX_SPEED_100: |
|
6625 hw->bus_speed = e1000_bus_speed_100; |
|
6626 break; |
|
6627 case E1000_STATUS_PCIX_SPEED_133: |
|
6628 hw->bus_speed = e1000_bus_speed_133; |
|
6629 break; |
|
6630 default: |
|
6631 hw->bus_speed = e1000_bus_speed_reserved; |
|
6632 break; |
|
6633 } |
|
6634 } |
|
6635 hw->bus_width = (status & E1000_STATUS_BUS64) ? |
|
6636 e1000_bus_width_64 : e1000_bus_width_32; |
|
6637 break; |
|
6638 } |
|
6639 } |
|
6640 |
|
6641 /****************************************************************************** |
|
6642 * Writes a value to one of the devices registers using port I/O (as opposed to |
|
6643 * memory mapped I/O). Only 82544 and newer devices support port I/O. |
|
6644 * |
|
6645 * hw - Struct containing variables accessed by shared code |
|
6646 * offset - offset to write to |
|
6647 * value - value to write |
|
6648 *****************************************************************************/ |
|
6649 static void |
|
6650 e1000_write_reg_io(struct e1000_hw *hw, |
|
6651 uint32_t offset, |
|
6652 uint32_t value) |
|
6653 { |
|
6654 unsigned long io_addr = hw->io_base; |
|
6655 unsigned long io_data = hw->io_base + 4; |
|
6656 |
|
6657 e1000_io_write(hw, io_addr, offset); |
|
6658 e1000_io_write(hw, io_data, value); |
|
6659 } |
|
6660 |
|
6661 /****************************************************************************** |
|
6662 * Estimates the cable length. |
|
6663 * |
|
6664 * hw - Struct containing variables accessed by shared code |
|
6665 * min_length - The estimated minimum length |
|
6666 * max_length - The estimated maximum length |
|
6667 * |
|
6668 * returns: - E1000_ERR_XXX |
|
6669 * E1000_SUCCESS |
|
6670 * |
|
6671 * This function always returns a ranged length (minimum & maximum). |
|
6672 * So for M88 phy's, this function interprets the one value returned from the |
|
6673 * register to the minimum and maximum range. |
|
6674 * For IGP phy's, the function calculates the range by the AGC registers. |
|
6675 *****************************************************************************/ |
|
6676 static int32_t |
|
6677 e1000_get_cable_length(struct e1000_hw *hw, |
|
6678 uint16_t *min_length, |
|
6679 uint16_t *max_length) |
|
6680 { |
|
6681 int32_t ret_val; |
|
6682 uint16_t agc_value = 0; |
|
6683 uint16_t i, phy_data; |
|
6684 uint16_t cable_length; |
|
6685 |
|
6686 DEBUGFUNC("e1000_get_cable_length"); |
|
6687 |
|
6688 *min_length = *max_length = 0; |
|
6689 |
|
6690 /* Use old method for Phy older than IGP */ |
|
6691 if (hw->phy_type == e1000_phy_m88) { |
|
6692 |
|
6693 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6694 &phy_data); |
|
6695 if (ret_val) |
|
6696 return ret_val; |
|
6697 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
6698 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
6699 |
|
6700 /* Convert the enum value to ranged values */ |
|
6701 switch (cable_length) { |
|
6702 case e1000_cable_length_50: |
|
6703 *min_length = 0; |
|
6704 *max_length = e1000_igp_cable_length_50; |
|
6705 break; |
|
6706 case e1000_cable_length_50_80: |
|
6707 *min_length = e1000_igp_cable_length_50; |
|
6708 *max_length = e1000_igp_cable_length_80; |
|
6709 break; |
|
6710 case e1000_cable_length_80_110: |
|
6711 *min_length = e1000_igp_cable_length_80; |
|
6712 *max_length = e1000_igp_cable_length_110; |
|
6713 break; |
|
6714 case e1000_cable_length_110_140: |
|
6715 *min_length = e1000_igp_cable_length_110; |
|
6716 *max_length = e1000_igp_cable_length_140; |
|
6717 break; |
|
6718 case e1000_cable_length_140: |
|
6719 *min_length = e1000_igp_cable_length_140; |
|
6720 *max_length = e1000_igp_cable_length_170; |
|
6721 break; |
|
6722 default: |
|
6723 return -E1000_ERR_PHY; |
|
6724 break; |
|
6725 } |
|
6726 } else if (hw->phy_type == e1000_phy_gg82563) { |
|
6727 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
|
6728 &phy_data); |
|
6729 if (ret_val) |
|
6730 return ret_val; |
|
6731 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; |
|
6732 |
|
6733 switch (cable_length) { |
|
6734 case e1000_gg_cable_length_60: |
|
6735 *min_length = 0; |
|
6736 *max_length = e1000_igp_cable_length_60; |
|
6737 break; |
|
6738 case e1000_gg_cable_length_60_115: |
|
6739 *min_length = e1000_igp_cable_length_60; |
|
6740 *max_length = e1000_igp_cable_length_115; |
|
6741 break; |
|
6742 case e1000_gg_cable_length_115_150: |
|
6743 *min_length = e1000_igp_cable_length_115; |
|
6744 *max_length = e1000_igp_cable_length_150; |
|
6745 break; |
|
6746 case e1000_gg_cable_length_150: |
|
6747 *min_length = e1000_igp_cable_length_150; |
|
6748 *max_length = e1000_igp_cable_length_180; |
|
6749 break; |
|
6750 default: |
|
6751 return -E1000_ERR_PHY; |
|
6752 break; |
|
6753 } |
|
6754 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
|
6755 uint16_t cur_agc_value; |
|
6756 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
|
6757 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
6758 {IGP01E1000_PHY_AGC_A, |
|
6759 IGP01E1000_PHY_AGC_B, |
|
6760 IGP01E1000_PHY_AGC_C, |
|
6761 IGP01E1000_PHY_AGC_D}; |
|
6762 /* Read the AGC registers for all channels */ |
|
6763 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
6764 |
|
6765 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
6766 if (ret_val) |
|
6767 return ret_val; |
|
6768 |
|
6769 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
|
6770 |
|
6771 /* Value bound check. */ |
|
6772 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || |
|
6773 (cur_agc_value == 0)) |
|
6774 return -E1000_ERR_PHY; |
|
6775 |
|
6776 agc_value += cur_agc_value; |
|
6777 |
|
6778 /* Update minimal AGC value. */ |
|
6779 if (min_agc_value > cur_agc_value) |
|
6780 min_agc_value = cur_agc_value; |
|
6781 } |
|
6782 |
|
6783 /* Remove the minimal AGC result for length < 50m */ |
|
6784 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
|
6785 agc_value -= min_agc_value; |
|
6786 |
|
6787 /* Get the average length of the remaining 3 channels */ |
|
6788 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
|
6789 } else { |
|
6790 /* Get the average length of all the 4 channels. */ |
|
6791 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
|
6792 } |
|
6793 |
|
6794 /* Set the range of the calculated length. */ |
|
6795 *min_length = ((e1000_igp_cable_length_table[agc_value] - |
|
6796 IGP01E1000_AGC_RANGE) > 0) ? |
|
6797 (e1000_igp_cable_length_table[agc_value] - |
|
6798 IGP01E1000_AGC_RANGE) : 0; |
|
6799 *max_length = e1000_igp_cable_length_table[agc_value] + |
|
6800 IGP01E1000_AGC_RANGE; |
|
6801 } else if (hw->phy_type == e1000_phy_igp_2 || |
|
6802 hw->phy_type == e1000_phy_igp_3) { |
|
6803 uint16_t cur_agc_index, max_agc_index = 0; |
|
6804 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; |
|
6805 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
|
6806 {IGP02E1000_PHY_AGC_A, |
|
6807 IGP02E1000_PHY_AGC_B, |
|
6808 IGP02E1000_PHY_AGC_C, |
|
6809 IGP02E1000_PHY_AGC_D}; |
|
6810 /* Read the AGC registers for all channels */ |
|
6811 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
|
6812 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
|
6813 if (ret_val) |
|
6814 return ret_val; |
|
6815 |
|
6816 /* Getting bits 15:9, which represent the combination of course and |
|
6817 * fine gain values. The result is a number that can be put into |
|
6818 * the lookup table to obtain the approximate cable length. */ |
|
6819 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
|
6820 IGP02E1000_AGC_LENGTH_MASK; |
|
6821 |
|
6822 /* Array index bound check. */ |
|
6823 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || |
|
6824 (cur_agc_index == 0)) |
|
6825 return -E1000_ERR_PHY; |
|
6826 |
|
6827 /* Remove min & max AGC values from calculation. */ |
|
6828 if (e1000_igp_2_cable_length_table[min_agc_index] > |
|
6829 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
6830 min_agc_index = cur_agc_index; |
|
6831 if (e1000_igp_2_cable_length_table[max_agc_index] < |
|
6832 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
6833 max_agc_index = cur_agc_index; |
|
6834 |
|
6835 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
|
6836 } |
|
6837 |
|
6838 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
|
6839 e1000_igp_2_cable_length_table[max_agc_index]); |
|
6840 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
|
6841 |
|
6842 /* Calculate cable length with the error range of +/- 10 meters. */ |
|
6843 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
|
6844 (agc_value - IGP02E1000_AGC_RANGE) : 0; |
|
6845 *max_length = agc_value + IGP02E1000_AGC_RANGE; |
|
6846 } |
|
6847 |
|
6848 return E1000_SUCCESS; |
|
6849 } |
|
6850 |
|
6851 /****************************************************************************** |
|
6852 * Check the cable polarity |
|
6853 * |
|
6854 * hw - Struct containing variables accessed by shared code |
|
6855 * polarity - output parameter : 0 - Polarity is not reversed |
|
6856 * 1 - Polarity is reversed. |
|
6857 * |
|
6858 * returns: - E1000_ERR_XXX |
|
6859 * E1000_SUCCESS |
|
6860 * |
|
6861 * For phy's older then IGP, this function simply reads the polarity bit in the |
|
6862 * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
|
6863 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
|
6864 * return 0. If the link speed is 1000 Mbps the polarity status is in the |
|
6865 * IGP01E1000_PHY_PCS_INIT_REG. |
|
6866 *****************************************************************************/ |
|
6867 static int32_t |
|
6868 e1000_check_polarity(struct e1000_hw *hw, |
|
6869 e1000_rev_polarity *polarity) |
|
6870 { |
|
6871 int32_t ret_val; |
|
6872 uint16_t phy_data; |
|
6873 |
|
6874 DEBUGFUNC("e1000_check_polarity"); |
|
6875 |
|
6876 if ((hw->phy_type == e1000_phy_m88) || |
|
6877 (hw->phy_type == e1000_phy_gg82563)) { |
|
6878 /* return the Polarity bit in the Status register. */ |
|
6879 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6880 &phy_data); |
|
6881 if (ret_val) |
|
6882 return ret_val; |
|
6883 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
|
6884 M88E1000_PSSR_REV_POLARITY_SHIFT) ? |
|
6885 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
6886 |
|
6887 } else if (hw->phy_type == e1000_phy_igp || |
|
6888 hw->phy_type == e1000_phy_igp_3 || |
|
6889 hw->phy_type == e1000_phy_igp_2) { |
|
6890 /* Read the Status register to check the speed */ |
|
6891 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
|
6892 &phy_data); |
|
6893 if (ret_val) |
|
6894 return ret_val; |
|
6895 |
|
6896 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
|
6897 * find the polarity status */ |
|
6898 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
|
6899 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
6900 |
|
6901 /* Read the GIG initialization PCS register (0x00B4) */ |
|
6902 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
|
6903 &phy_data); |
|
6904 if (ret_val) |
|
6905 return ret_val; |
|
6906 |
|
6907 /* Check the polarity bits */ |
|
6908 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
|
6909 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
6910 } else { |
|
6911 /* For 10 Mbps, read the polarity bit in the status register. (for |
|
6912 * 100 Mbps this bit is always 0) */ |
|
6913 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
|
6914 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
6915 } |
|
6916 } else if (hw->phy_type == e1000_phy_ife) { |
|
6917 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, |
|
6918 &phy_data); |
|
6919 if (ret_val) |
|
6920 return ret_val; |
|
6921 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> |
|
6922 IFE_PESC_POLARITY_REVERSED_SHIFT) ? |
|
6923 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
|
6924 } |
|
6925 return E1000_SUCCESS; |
|
6926 } |
|
6927 |
|
6928 /****************************************************************************** |
|
6929 * Check if Downshift occured |
|
6930 * |
|
6931 * hw - Struct containing variables accessed by shared code |
|
6932 * downshift - output parameter : 0 - No Downshift ocured. |
|
6933 * 1 - Downshift ocured. |
|
6934 * |
|
6935 * returns: - E1000_ERR_XXX |
|
6936 * E1000_SUCCESS |
|
6937 * |
|
6938 * For phy's older then IGP, this function reads the Downshift bit in the Phy |
|
6939 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
|
6940 * Link Health register. In IGP this bit is latched high, so the driver must |
|
6941 * read it immediately after link is established. |
|
6942 *****************************************************************************/ |
|
6943 static int32_t |
|
6944 e1000_check_downshift(struct e1000_hw *hw) |
|
6945 { |
|
6946 int32_t ret_val; |
|
6947 uint16_t phy_data; |
|
6948 |
|
6949 DEBUGFUNC("e1000_check_downshift"); |
|
6950 |
|
6951 if (hw->phy_type == e1000_phy_igp || |
|
6952 hw->phy_type == e1000_phy_igp_3 || |
|
6953 hw->phy_type == e1000_phy_igp_2) { |
|
6954 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
|
6955 &phy_data); |
|
6956 if (ret_val) |
|
6957 return ret_val; |
|
6958 |
|
6959 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
|
6960 } else if ((hw->phy_type == e1000_phy_m88) || |
|
6961 (hw->phy_type == e1000_phy_gg82563)) { |
|
6962 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
|
6963 &phy_data); |
|
6964 if (ret_val) |
|
6965 return ret_val; |
|
6966 |
|
6967 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
|
6968 M88E1000_PSSR_DOWNSHIFT_SHIFT; |
|
6969 } else if (hw->phy_type == e1000_phy_ife) { |
|
6970 /* e1000_phy_ife supports 10/100 speed only */ |
|
6971 hw->speed_downgraded = FALSE; |
|
6972 } |
|
6973 |
|
6974 return E1000_SUCCESS; |
|
6975 } |
|
6976 |
|
6977 /***************************************************************************** |
|
6978 * |
|
6979 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
|
6980 * gigabit link is achieved to improve link quality. |
|
6981 * |
|
6982 * hw: Struct containing variables accessed by shared code |
|
6983 * |
|
6984 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
6985 * E1000_SUCCESS at any other case. |
|
6986 * |
|
6987 ****************************************************************************/ |
|
6988 |
|
6989 static int32_t |
|
6990 e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
|
6991 boolean_t link_up) |
|
6992 { |
|
6993 int32_t ret_val; |
|
6994 uint16_t phy_data, phy_saved_data, speed, duplex, i; |
|
6995 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
|
6996 {IGP01E1000_PHY_AGC_PARAM_A, |
|
6997 IGP01E1000_PHY_AGC_PARAM_B, |
|
6998 IGP01E1000_PHY_AGC_PARAM_C, |
|
6999 IGP01E1000_PHY_AGC_PARAM_D}; |
|
7000 uint16_t min_length, max_length; |
|
7001 |
|
7002 DEBUGFUNC("e1000_config_dsp_after_link_change"); |
|
7003 |
|
7004 if (hw->phy_type != e1000_phy_igp) |
|
7005 return E1000_SUCCESS; |
|
7006 |
|
7007 if (link_up) { |
|
7008 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
|
7009 if (ret_val) { |
|
7010 DEBUGOUT("Error getting link speed and duplex\n"); |
|
7011 return ret_val; |
|
7012 } |
|
7013 |
|
7014 if (speed == SPEED_1000) { |
|
7015 |
|
7016 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
|
7017 if (ret_val) |
|
7018 return ret_val; |
|
7019 |
|
7020 if ((hw->dsp_config_state == e1000_dsp_config_enabled) && |
|
7021 min_length >= e1000_igp_cable_length_50) { |
|
7022 |
|
7023 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
7024 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
|
7025 &phy_data); |
|
7026 if (ret_val) |
|
7027 return ret_val; |
|
7028 |
|
7029 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
7030 |
|
7031 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], |
|
7032 phy_data); |
|
7033 if (ret_val) |
|
7034 return ret_val; |
|
7035 } |
|
7036 hw->dsp_config_state = e1000_dsp_config_activated; |
|
7037 } |
|
7038 |
|
7039 if ((hw->ffe_config_state == e1000_ffe_config_enabled) && |
|
7040 (min_length < e1000_igp_cable_length_50)) { |
|
7041 |
|
7042 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
|
7043 uint32_t idle_errs = 0; |
|
7044 |
|
7045 /* clear previous idle error counts */ |
|
7046 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
7047 &phy_data); |
|
7048 if (ret_val) |
|
7049 return ret_val; |
|
7050 |
|
7051 for (i = 0; i < ffe_idle_err_timeout; i++) { |
|
7052 udelay(1000); |
|
7053 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
|
7054 &phy_data); |
|
7055 if (ret_val) |
|
7056 return ret_val; |
|
7057 |
|
7058 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
|
7059 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
|
7060 hw->ffe_config_state = e1000_ffe_config_active; |
|
7061 |
|
7062 ret_val = e1000_write_phy_reg(hw, |
|
7063 IGP01E1000_PHY_DSP_FFE, |
|
7064 IGP01E1000_PHY_DSP_FFE_CM_CP); |
|
7065 if (ret_val) |
|
7066 return ret_val; |
|
7067 break; |
|
7068 } |
|
7069 |
|
7070 if (idle_errs) |
|
7071 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
|
7072 } |
|
7073 } |
|
7074 } |
|
7075 } else { |
|
7076 if (hw->dsp_config_state == e1000_dsp_config_activated) { |
|
7077 /* Save off the current value of register 0x2F5B to be restored at |
|
7078 * the end of the routines. */ |
|
7079 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
7080 |
|
7081 if (ret_val) |
|
7082 return ret_val; |
|
7083 |
|
7084 /* Disable the PHY transmitter */ |
|
7085 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
7086 |
|
7087 if (ret_val) |
|
7088 return ret_val; |
|
7089 |
|
7090 mdelay(20); |
|
7091 |
|
7092 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7093 IGP01E1000_IEEE_FORCE_GIGA); |
|
7094 if (ret_val) |
|
7095 return ret_val; |
|
7096 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
|
7097 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
|
7098 if (ret_val) |
|
7099 return ret_val; |
|
7100 |
|
7101 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
|
7102 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
|
7103 |
|
7104 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); |
|
7105 if (ret_val) |
|
7106 return ret_val; |
|
7107 } |
|
7108 |
|
7109 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7110 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
7111 if (ret_val) |
|
7112 return ret_val; |
|
7113 |
|
7114 mdelay(20); |
|
7115 |
|
7116 /* Now enable the transmitter */ |
|
7117 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
7118 |
|
7119 if (ret_val) |
|
7120 return ret_val; |
|
7121 |
|
7122 hw->dsp_config_state = e1000_dsp_config_enabled; |
|
7123 } |
|
7124 |
|
7125 if (hw->ffe_config_state == e1000_ffe_config_active) { |
|
7126 /* Save off the current value of register 0x2F5B to be restored at |
|
7127 * the end of the routines. */ |
|
7128 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
|
7129 |
|
7130 if (ret_val) |
|
7131 return ret_val; |
|
7132 |
|
7133 /* Disable the PHY transmitter */ |
|
7134 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
|
7135 |
|
7136 if (ret_val) |
|
7137 return ret_val; |
|
7138 |
|
7139 mdelay(20); |
|
7140 |
|
7141 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7142 IGP01E1000_IEEE_FORCE_GIGA); |
|
7143 if (ret_val) |
|
7144 return ret_val; |
|
7145 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
|
7146 IGP01E1000_PHY_DSP_FFE_DEFAULT); |
|
7147 if (ret_val) |
|
7148 return ret_val; |
|
7149 |
|
7150 ret_val = e1000_write_phy_reg(hw, 0x0000, |
|
7151 IGP01E1000_IEEE_RESTART_AUTONEG); |
|
7152 if (ret_val) |
|
7153 return ret_val; |
|
7154 |
|
7155 mdelay(20); |
|
7156 |
|
7157 /* Now enable the transmitter */ |
|
7158 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
|
7159 |
|
7160 if (ret_val) |
|
7161 return ret_val; |
|
7162 |
|
7163 hw->ffe_config_state = e1000_ffe_config_enabled; |
|
7164 } |
|
7165 } |
|
7166 return E1000_SUCCESS; |
|
7167 } |
|
7168 |
|
7169 /***************************************************************************** |
|
7170 * Set PHY to class A mode |
|
7171 * Assumes the following operations will follow to enable the new class mode. |
|
7172 * 1. Do a PHY soft reset |
|
7173 * 2. Restart auto-negotiation or force link. |
|
7174 * |
|
7175 * hw - Struct containing variables accessed by shared code |
|
7176 ****************************************************************************/ |
|
7177 static int32_t |
|
7178 e1000_set_phy_mode(struct e1000_hw *hw) |
|
7179 { |
|
7180 int32_t ret_val; |
|
7181 uint16_t eeprom_data; |
|
7182 |
|
7183 DEBUGFUNC("e1000_set_phy_mode"); |
|
7184 |
|
7185 if ((hw->mac_type == e1000_82545_rev_3) && |
|
7186 (hw->media_type == e1000_media_type_copper)) { |
|
7187 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
|
7188 if (ret_val) { |
|
7189 return ret_val; |
|
7190 } |
|
7191 |
|
7192 if ((eeprom_data != EEPROM_RESERVED_WORD) && |
|
7193 (eeprom_data & EEPROM_PHY_CLASS_A)) { |
|
7194 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
|
7195 if (ret_val) |
|
7196 return ret_val; |
|
7197 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); |
|
7198 if (ret_val) |
|
7199 return ret_val; |
|
7200 |
|
7201 hw->phy_reset_disable = FALSE; |
|
7202 } |
|
7203 } |
|
7204 |
|
7205 return E1000_SUCCESS; |
|
7206 } |
|
7207 |
|
7208 /***************************************************************************** |
|
7209 * |
|
7210 * This function sets the lplu state according to the active flag. When |
|
7211 * activating lplu this function also disables smart speed and vise versa. |
|
7212 * lplu will not be activated unless the device autonegotiation advertisment |
|
7213 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
7214 * hw: Struct containing variables accessed by shared code |
|
7215 * active - true to enable lplu false to disable lplu. |
|
7216 * |
|
7217 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
7218 * E1000_SUCCESS at any other case. |
|
7219 * |
|
7220 ****************************************************************************/ |
|
7221 |
|
7222 static int32_t |
|
7223 e1000_set_d3_lplu_state(struct e1000_hw *hw, |
|
7224 boolean_t active) |
|
7225 { |
|
7226 uint32_t phy_ctrl = 0; |
|
7227 int32_t ret_val; |
|
7228 uint16_t phy_data; |
|
7229 DEBUGFUNC("e1000_set_d3_lplu_state"); |
|
7230 |
|
7231 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
|
7232 && hw->phy_type != e1000_phy_igp_3) |
|
7233 return E1000_SUCCESS; |
|
7234 |
|
7235 /* During driver activity LPLU should not be used or it will attain link |
|
7236 * from the lowest speeds starting from 10Mbps. The capability is used for |
|
7237 * Dx transitions and states */ |
|
7238 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
|
7239 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
|
7240 if (ret_val) |
|
7241 return ret_val; |
|
7242 } else if (hw->mac_type == e1000_ich8lan) { |
|
7243 /* MAC writes into PHY register based on the state transition |
|
7244 * and start auto-negotiation. SW driver can overwrite the settings |
|
7245 * in CSR PHY power control E1000_PHY_CTRL register. */ |
|
7246 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
|
7247 } else { |
|
7248 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
|
7249 if (ret_val) |
|
7250 return ret_val; |
|
7251 } |
|
7252 |
|
7253 if (!active) { |
|
7254 if (hw->mac_type == e1000_82541_rev_2 || |
|
7255 hw->mac_type == e1000_82547_rev_2) { |
|
7256 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
|
7257 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
|
7258 if (ret_val) |
|
7259 return ret_val; |
|
7260 } else { |
|
7261 if (hw->mac_type == e1000_ich8lan) { |
|
7262 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
|
7263 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7264 } else { |
|
7265 phy_data &= ~IGP02E1000_PM_D3_LPLU; |
|
7266 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
|
7267 phy_data); |
|
7268 if (ret_val) |
|
7269 return ret_val; |
|
7270 } |
|
7271 } |
|
7272 |
|
7273 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
|
7274 * Dx states where the power conservation is most important. During |
|
7275 * driver activity we should enable SmartSpeed, so performance is |
|
7276 * maintained. */ |
|
7277 if (hw->smart_speed == e1000_smart_speed_on) { |
|
7278 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7279 &phy_data); |
|
7280 if (ret_val) |
|
7281 return ret_val; |
|
7282 |
|
7283 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
7284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7285 phy_data); |
|
7286 if (ret_val) |
|
7287 return ret_val; |
|
7288 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
7289 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7290 &phy_data); |
|
7291 if (ret_val) |
|
7292 return ret_val; |
|
7293 |
|
7294 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7296 phy_data); |
|
7297 if (ret_val) |
|
7298 return ret_val; |
|
7299 } |
|
7300 |
|
7301 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
|
7302 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
|
7303 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
|
7304 |
|
7305 if (hw->mac_type == e1000_82541_rev_2 || |
|
7306 hw->mac_type == e1000_82547_rev_2) { |
|
7307 phy_data |= IGP01E1000_GMII_FLEX_SPD; |
|
7308 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
|
7309 if (ret_val) |
|
7310 return ret_val; |
|
7311 } else { |
|
7312 if (hw->mac_type == e1000_ich8lan) { |
|
7313 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
|
7314 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7315 } else { |
|
7316 phy_data |= IGP02E1000_PM_D3_LPLU; |
|
7317 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
|
7318 phy_data); |
|
7319 if (ret_val) |
|
7320 return ret_val; |
|
7321 } |
|
7322 } |
|
7323 |
|
7324 /* When LPLU is enabled we should disable SmartSpeed */ |
|
7325 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
7326 if (ret_val) |
|
7327 return ret_val; |
|
7328 |
|
7329 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7330 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
|
7331 if (ret_val) |
|
7332 return ret_val; |
|
7333 |
|
7334 } |
|
7335 return E1000_SUCCESS; |
|
7336 } |
|
7337 |
|
7338 /***************************************************************************** |
|
7339 * |
|
7340 * This function sets the lplu d0 state according to the active flag. When |
|
7341 * activating lplu this function also disables smart speed and vise versa. |
|
7342 * lplu will not be activated unless the device autonegotiation advertisment |
|
7343 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
7344 * hw: Struct containing variables accessed by shared code |
|
7345 * active - true to enable lplu false to disable lplu. |
|
7346 * |
|
7347 * returns: - E1000_ERR_PHY if fail to read/write the PHY |
|
7348 * E1000_SUCCESS at any other case. |
|
7349 * |
|
7350 ****************************************************************************/ |
|
7351 |
|
7352 static int32_t |
|
7353 e1000_set_d0_lplu_state(struct e1000_hw *hw, |
|
7354 boolean_t active) |
|
7355 { |
|
7356 uint32_t phy_ctrl = 0; |
|
7357 int32_t ret_val; |
|
7358 uint16_t phy_data; |
|
7359 DEBUGFUNC("e1000_set_d0_lplu_state"); |
|
7360 |
|
7361 if (hw->mac_type <= e1000_82547_rev_2) |
|
7362 return E1000_SUCCESS; |
|
7363 |
|
7364 if (hw->mac_type == e1000_ich8lan) { |
|
7365 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
|
7366 } else { |
|
7367 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
|
7368 if (ret_val) |
|
7369 return ret_val; |
|
7370 } |
|
7371 |
|
7372 if (!active) { |
|
7373 if (hw->mac_type == e1000_ich8lan) { |
|
7374 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
|
7375 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7376 } else { |
|
7377 phy_data &= ~IGP02E1000_PM_D0_LPLU; |
|
7378 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
|
7379 if (ret_val) |
|
7380 return ret_val; |
|
7381 } |
|
7382 |
|
7383 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
|
7384 * Dx states where the power conservation is most important. During |
|
7385 * driver activity we should enable SmartSpeed, so performance is |
|
7386 * maintained. */ |
|
7387 if (hw->smart_speed == e1000_smart_speed_on) { |
|
7388 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7389 &phy_data); |
|
7390 if (ret_val) |
|
7391 return ret_val; |
|
7392 |
|
7393 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
7394 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7395 phy_data); |
|
7396 if (ret_val) |
|
7397 return ret_val; |
|
7398 } else if (hw->smart_speed == e1000_smart_speed_off) { |
|
7399 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7400 &phy_data); |
|
7401 if (ret_val) |
|
7402 return ret_val; |
|
7403 |
|
7404 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7405 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
7406 phy_data); |
|
7407 if (ret_val) |
|
7408 return ret_val; |
|
7409 } |
|
7410 |
|
7411 |
|
7412 } else { |
|
7413 |
|
7414 if (hw->mac_type == e1000_ich8lan) { |
|
7415 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
|
7416 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
7417 } else { |
|
7418 phy_data |= IGP02E1000_PM_D0_LPLU; |
|
7419 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
|
7420 if (ret_val) |
|
7421 return ret_val; |
|
7422 } |
|
7423 |
|
7424 /* When LPLU is enabled we should disable SmartSpeed */ |
|
7425 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
7426 if (ret_val) |
|
7427 return ret_val; |
|
7428 |
|
7429 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
7430 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
|
7431 if (ret_val) |
|
7432 return ret_val; |
|
7433 |
|
7434 } |
|
7435 return E1000_SUCCESS; |
|
7436 } |
|
7437 |
|
7438 /****************************************************************************** |
|
7439 * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
|
7440 * |
|
7441 * hw - Struct containing variables accessed by shared code |
|
7442 *****************************************************************************/ |
|
7443 static int32_t |
|
7444 e1000_set_vco_speed(struct e1000_hw *hw) |
|
7445 { |
|
7446 int32_t ret_val; |
|
7447 uint16_t default_page = 0; |
|
7448 uint16_t phy_data; |
|
7449 |
|
7450 DEBUGFUNC("e1000_set_vco_speed"); |
|
7451 |
|
7452 switch (hw->mac_type) { |
|
7453 case e1000_82545_rev_3: |
|
7454 case e1000_82546_rev_3: |
|
7455 break; |
|
7456 default: |
|
7457 return E1000_SUCCESS; |
|
7458 } |
|
7459 |
|
7460 /* Set PHY register 30, page 5, bit 8 to 0 */ |
|
7461 |
|
7462 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
|
7463 if (ret_val) |
|
7464 return ret_val; |
|
7465 |
|
7466 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
|
7467 if (ret_val) |
|
7468 return ret_val; |
|
7469 |
|
7470 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
7471 if (ret_val) |
|
7472 return ret_val; |
|
7473 |
|
7474 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
|
7475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
7476 if (ret_val) |
|
7477 return ret_val; |
|
7478 |
|
7479 /* Set PHY register 30, page 4, bit 11 to 1 */ |
|
7480 |
|
7481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
|
7482 if (ret_val) |
|
7483 return ret_val; |
|
7484 |
|
7485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
|
7486 if (ret_val) |
|
7487 return ret_val; |
|
7488 |
|
7489 phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
|
7490 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
|
7491 if (ret_val) |
|
7492 return ret_val; |
|
7493 |
|
7494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
|
7495 if (ret_val) |
|
7496 return ret_val; |
|
7497 |
|
7498 return E1000_SUCCESS; |
|
7499 } |
|
7500 |
|
7501 |
|
7502 /***************************************************************************** |
|
7503 * This function reads the cookie from ARC ram. |
|
7504 * |
|
7505 * returns: - E1000_SUCCESS . |
|
7506 ****************************************************************************/ |
|
7507 static int32_t |
|
7508 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
|
7509 { |
|
7510 uint8_t i; |
|
7511 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
|
7512 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
|
7513 |
|
7514 length = (length >> 2); |
|
7515 offset = (offset >> 2); |
|
7516 |
|
7517 for (i = 0; i < length; i++) { |
|
7518 *((uint32_t *) buffer + i) = |
|
7519 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
|
7520 } |
|
7521 return E1000_SUCCESS; |
|
7522 } |
|
7523 |
|
7524 |
|
7525 /***************************************************************************** |
|
7526 * This function checks whether the HOST IF is enabled for command operaton |
|
7527 * and also checks whether the previous command is completed. |
|
7528 * It busy waits in case of previous command is not completed. |
|
7529 * |
|
7530 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
|
7531 * timeout |
|
7532 * - E1000_SUCCESS for success. |
|
7533 ****************************************************************************/ |
|
7534 static int32_t |
|
7535 e1000_mng_enable_host_if(struct e1000_hw * hw) |
|
7536 { |
|
7537 uint32_t hicr; |
|
7538 uint8_t i; |
|
7539 |
|
7540 /* Check that the host interface is enabled. */ |
|
7541 hicr = E1000_READ_REG(hw, HICR); |
|
7542 if ((hicr & E1000_HICR_EN) == 0) { |
|
7543 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); |
|
7544 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
7545 } |
|
7546 /* check the previous command is completed */ |
|
7547 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
|
7548 hicr = E1000_READ_REG(hw, HICR); |
|
7549 if (!(hicr & E1000_HICR_C)) |
|
7550 break; |
|
7551 mdelay(1); |
|
7552 } |
|
7553 |
|
7554 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
|
7555 DEBUGOUT("Previous command timeout failed .\n"); |
|
7556 return -E1000_ERR_HOST_INTERFACE_COMMAND; |
|
7557 } |
|
7558 return E1000_SUCCESS; |
|
7559 } |
|
7560 |
|
7561 /***************************************************************************** |
|
7562 * This function writes the buffer content at the offset given on the host if. |
|
7563 * It also does alignment considerations to do the writes in most efficient way. |
|
7564 * Also fills up the sum of the buffer in *buffer parameter. |
|
7565 * |
|
7566 * returns - E1000_SUCCESS for success. |
|
7567 ****************************************************************************/ |
|
7568 static int32_t |
|
7569 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
|
7570 uint16_t length, uint16_t offset, uint8_t *sum) |
|
7571 { |
|
7572 uint8_t *tmp; |
|
7573 uint8_t *bufptr = buffer; |
|
7574 uint32_t data = 0; |
|
7575 uint16_t remaining, i, j, prev_bytes; |
|
7576 |
|
7577 /* sum = only sum of the data and it is not checksum */ |
|
7578 |
|
7579 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { |
|
7580 return -E1000_ERR_PARAM; |
|
7581 } |
|
7582 |
|
7583 tmp = (uint8_t *)&data; |
|
7584 prev_bytes = offset & 0x3; |
|
7585 offset &= 0xFFFC; |
|
7586 offset >>= 2; |
|
7587 |
|
7588 if (prev_bytes) { |
|
7589 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); |
|
7590 for (j = prev_bytes; j < sizeof(uint32_t); j++) { |
|
7591 *(tmp + j) = *bufptr++; |
|
7592 *sum += *(tmp + j); |
|
7593 } |
|
7594 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); |
|
7595 length -= j - prev_bytes; |
|
7596 offset++; |
|
7597 } |
|
7598 |
|
7599 remaining = length & 0x3; |
|
7600 length -= remaining; |
|
7601 |
|
7602 /* Calculate length in DWORDs */ |
|
7603 length >>= 2; |
|
7604 |
|
7605 /* The device driver writes the relevant command block into the |
|
7606 * ram area. */ |
|
7607 for (i = 0; i < length; i++) { |
|
7608 for (j = 0; j < sizeof(uint32_t); j++) { |
|
7609 *(tmp + j) = *bufptr++; |
|
7610 *sum += *(tmp + j); |
|
7611 } |
|
7612 |
|
7613 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
|
7614 } |
|
7615 if (remaining) { |
|
7616 for (j = 0; j < sizeof(uint32_t); j++) { |
|
7617 if (j < remaining) |
|
7618 *(tmp + j) = *bufptr++; |
|
7619 else |
|
7620 *(tmp + j) = 0; |
|
7621 |
|
7622 *sum += *(tmp + j); |
|
7623 } |
|
7624 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
|
7625 } |
|
7626 |
|
7627 return E1000_SUCCESS; |
|
7628 } |
|
7629 |
|
7630 |
|
7631 /***************************************************************************** |
|
7632 * This function writes the command header after does the checksum calculation. |
|
7633 * |
|
7634 * returns - E1000_SUCCESS for success. |
|
7635 ****************************************************************************/ |
|
7636 static int32_t |
|
7637 e1000_mng_write_cmd_header(struct e1000_hw * hw, |
|
7638 struct e1000_host_mng_command_header * hdr) |
|
7639 { |
|
7640 uint16_t i; |
|
7641 uint8_t sum; |
|
7642 uint8_t *buffer; |
|
7643 |
|
7644 /* Write the whole command header structure which includes sum of |
|
7645 * the buffer */ |
|
7646 |
|
7647 uint16_t length = sizeof(struct e1000_host_mng_command_header); |
|
7648 |
|
7649 sum = hdr->checksum; |
|
7650 hdr->checksum = 0; |
|
7651 |
|
7652 buffer = (uint8_t *) hdr; |
|
7653 i = length; |
|
7654 while (i--) |
|
7655 sum += buffer[i]; |
|
7656 |
|
7657 hdr->checksum = 0 - sum; |
|
7658 |
|
7659 length >>= 2; |
|
7660 /* The device driver writes the relevant command block into the ram area. */ |
|
7661 for (i = 0; i < length; i++) { |
|
7662 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
|
7663 E1000_WRITE_FLUSH(hw); |
|
7664 } |
|
7665 |
|
7666 return E1000_SUCCESS; |
|
7667 } |
|
7668 |
|
7669 |
|
7670 /***************************************************************************** |
|
7671 * This function indicates to ARC that a new command is pending which completes |
|
7672 * one write operation by the driver. |
|
7673 * |
|
7674 * returns - E1000_SUCCESS for success. |
|
7675 ****************************************************************************/ |
|
7676 static int32_t |
|
7677 e1000_mng_write_commit(struct e1000_hw * hw) |
|
7678 { |
|
7679 uint32_t hicr; |
|
7680 |
|
7681 hicr = E1000_READ_REG(hw, HICR); |
|
7682 /* Setting this bit tells the ARC that a new command is pending. */ |
|
7683 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); |
|
7684 |
|
7685 return E1000_SUCCESS; |
|
7686 } |
|
7687 |
|
7688 |
|
7689 /***************************************************************************** |
|
7690 * This function checks the mode of the firmware. |
|
7691 * |
|
7692 * returns - TRUE when the mode is IAMT or FALSE. |
|
7693 ****************************************************************************/ |
|
7694 boolean_t |
|
7695 e1000_check_mng_mode(struct e1000_hw *hw) |
|
7696 { |
|
7697 uint32_t fwsm; |
|
7698 |
|
7699 fwsm = E1000_READ_REG(hw, FWSM); |
|
7700 |
|
7701 if (hw->mac_type == e1000_ich8lan) { |
|
7702 if ((fwsm & E1000_FWSM_MODE_MASK) == |
|
7703 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
|
7704 return TRUE; |
|
7705 } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
|
7706 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
|
7707 return TRUE; |
|
7708 |
|
7709 return FALSE; |
|
7710 } |
|
7711 |
|
7712 |
|
7713 /***************************************************************************** |
|
7714 * This function writes the dhcp info . |
|
7715 ****************************************************************************/ |
|
7716 int32_t |
|
7717 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, |
|
7718 uint16_t length) |
|
7719 { |
|
7720 int32_t ret_val; |
|
7721 struct e1000_host_mng_command_header hdr; |
|
7722 |
|
7723 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
|
7724 hdr.command_length = length; |
|
7725 hdr.reserved1 = 0; |
|
7726 hdr.reserved2 = 0; |
|
7727 hdr.checksum = 0; |
|
7728 |
|
7729 ret_val = e1000_mng_enable_host_if(hw); |
|
7730 if (ret_val == E1000_SUCCESS) { |
|
7731 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), |
|
7732 &(hdr.checksum)); |
|
7733 if (ret_val == E1000_SUCCESS) { |
|
7734 ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
|
7735 if (ret_val == E1000_SUCCESS) |
|
7736 ret_val = e1000_mng_write_commit(hw); |
|
7737 } |
|
7738 } |
|
7739 return ret_val; |
|
7740 } |
|
7741 |
|
7742 |
|
7743 /***************************************************************************** |
|
7744 * This function calculates the checksum. |
|
7745 * |
|
7746 * returns - checksum of buffer contents. |
|
7747 ****************************************************************************/ |
|
7748 static uint8_t |
|
7749 e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
|
7750 { |
|
7751 uint8_t sum = 0; |
|
7752 uint32_t i; |
|
7753 |
|
7754 if (!buffer) |
|
7755 return 0; |
|
7756 |
|
7757 for (i=0; i < length; i++) |
|
7758 sum += buffer[i]; |
|
7759 |
|
7760 return (uint8_t) (0 - sum); |
|
7761 } |
|
7762 |
|
7763 /***************************************************************************** |
|
7764 * This function checks whether tx pkt filtering needs to be enabled or not. |
|
7765 * |
|
7766 * returns - TRUE for packet filtering or FALSE. |
|
7767 ****************************************************************************/ |
|
7768 boolean_t |
|
7769 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) |
|
7770 { |
|
7771 /* called in init as well as watchdog timer functions */ |
|
7772 |
|
7773 int32_t ret_val, checksum; |
|
7774 boolean_t tx_filter = FALSE; |
|
7775 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
|
7776 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); |
|
7777 |
|
7778 if (e1000_check_mng_mode(hw)) { |
|
7779 ret_val = e1000_mng_enable_host_if(hw); |
|
7780 if (ret_val == E1000_SUCCESS) { |
|
7781 ret_val = e1000_host_if_read_cookie(hw, buffer); |
|
7782 if (ret_val == E1000_SUCCESS) { |
|
7783 checksum = hdr->checksum; |
|
7784 hdr->checksum = 0; |
|
7785 if ((hdr->signature == E1000_IAMT_SIGNATURE) && |
|
7786 checksum == e1000_calculate_mng_checksum((char *)buffer, |
|
7787 E1000_MNG_DHCP_COOKIE_LENGTH)) { |
|
7788 if (hdr->status & |
|
7789 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) |
|
7790 tx_filter = TRUE; |
|
7791 } else |
|
7792 tx_filter = TRUE; |
|
7793 } else |
|
7794 tx_filter = TRUE; |
|
7795 } |
|
7796 } |
|
7797 |
|
7798 hw->tx_pkt_filtering = tx_filter; |
|
7799 return tx_filter; |
|
7800 } |
|
7801 |
|
7802 /****************************************************************************** |
|
7803 * Verifies the hardware needs to allow ARPs to be processed by the host |
|
7804 * |
|
7805 * hw - Struct containing variables accessed by shared code |
|
7806 * |
|
7807 * returns: - TRUE/FALSE |
|
7808 * |
|
7809 *****************************************************************************/ |
|
7810 uint32_t |
|
7811 e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
|
7812 { |
|
7813 uint32_t manc; |
|
7814 uint32_t fwsm, factps; |
|
7815 |
|
7816 if (hw->asf_firmware_present) { |
|
7817 manc = E1000_READ_REG(hw, MANC); |
|
7818 |
|
7819 if (!(manc & E1000_MANC_RCV_TCO_EN) || |
|
7820 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
|
7821 return FALSE; |
|
7822 if (e1000_arc_subsystem_valid(hw) == TRUE) { |
|
7823 fwsm = E1000_READ_REG(hw, FWSM); |
|
7824 factps = E1000_READ_REG(hw, FACTPS); |
|
7825 |
|
7826 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == |
|
7827 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) |
|
7828 return TRUE; |
|
7829 } else |
|
7830 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
|
7831 return TRUE; |
|
7832 } |
|
7833 return FALSE; |
|
7834 } |
|
7835 |
|
7836 static int32_t |
|
7837 e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
|
7838 { |
|
7839 int32_t ret_val; |
|
7840 uint16_t mii_status_reg; |
|
7841 uint16_t i; |
|
7842 |
|
7843 /* Polarity reversal workaround for forced 10F/10H links. */ |
|
7844 |
|
7845 /* Disable the transmitter on the PHY */ |
|
7846 |
|
7847 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
7848 if (ret_val) |
|
7849 return ret_val; |
|
7850 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
|
7851 if (ret_val) |
|
7852 return ret_val; |
|
7853 |
|
7854 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
7855 if (ret_val) |
|
7856 return ret_val; |
|
7857 |
|
7858 /* This loop will early-out if the NO link condition has been met. */ |
|
7859 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
7860 /* Read the MII Status Register and wait for Link Status bit |
|
7861 * to be clear. |
|
7862 */ |
|
7863 |
|
7864 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7865 if (ret_val) |
|
7866 return ret_val; |
|
7867 |
|
7868 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7869 if (ret_val) |
|
7870 return ret_val; |
|
7871 |
|
7872 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
|
7873 mdelay(100); |
|
7874 } |
|
7875 |
|
7876 /* Recommended delay time after link has been lost */ |
|
7877 mdelay(1000); |
|
7878 |
|
7879 /* Now we will re-enable th transmitter on the PHY */ |
|
7880 |
|
7881 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
|
7882 if (ret_val) |
|
7883 return ret_val; |
|
7884 mdelay(50); |
|
7885 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
|
7886 if (ret_val) |
|
7887 return ret_val; |
|
7888 mdelay(50); |
|
7889 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
|
7890 if (ret_val) |
|
7891 return ret_val; |
|
7892 mdelay(50); |
|
7893 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
|
7894 if (ret_val) |
|
7895 return ret_val; |
|
7896 |
|
7897 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
|
7898 if (ret_val) |
|
7899 return ret_val; |
|
7900 |
|
7901 /* This loop will early-out if the link condition has been met. */ |
|
7902 for (i = PHY_FORCE_TIME; i > 0; i--) { |
|
7903 /* Read the MII Status Register and wait for Link Status bit |
|
7904 * to be set. |
|
7905 */ |
|
7906 |
|
7907 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7908 if (ret_val) |
|
7909 return ret_val; |
|
7910 |
|
7911 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
|
7912 if (ret_val) |
|
7913 return ret_val; |
|
7914 |
|
7915 if (mii_status_reg & MII_SR_LINK_STATUS) break; |
|
7916 mdelay(100); |
|
7917 } |
|
7918 return E1000_SUCCESS; |
|
7919 } |
|
7920 |
|
7921 /*************************************************************************** |
|
7922 * |
|
7923 * Disables PCI-Express master access. |
|
7924 * |
|
7925 * hw: Struct containing variables accessed by shared code |
|
7926 * |
|
7927 * returns: - none. |
|
7928 * |
|
7929 ***************************************************************************/ |
|
7930 static void |
|
7931 e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
|
7932 { |
|
7933 uint32_t ctrl; |
|
7934 |
|
7935 DEBUGFUNC("e1000_set_pci_express_master_disable"); |
|
7936 |
|
7937 if (hw->bus_type != e1000_bus_type_pci_express) |
|
7938 return; |
|
7939 |
|
7940 ctrl = E1000_READ_REG(hw, CTRL); |
|
7941 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
|
7942 E1000_WRITE_REG(hw, CTRL, ctrl); |
|
7943 } |
|
7944 |
|
7945 /******************************************************************************* |
|
7946 * |
|
7947 * Disables PCI-Express master access and verifies there are no pending requests |
|
7948 * |
|
7949 * hw: Struct containing variables accessed by shared code |
|
7950 * |
|
7951 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't |
|
7952 * caused the master requests to be disabled. |
|
7953 * E1000_SUCCESS master requests disabled. |
|
7954 * |
|
7955 ******************************************************************************/ |
|
7956 int32_t |
|
7957 e1000_disable_pciex_master(struct e1000_hw *hw) |
|
7958 { |
|
7959 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
|
7960 |
|
7961 DEBUGFUNC("e1000_disable_pciex_master"); |
|
7962 |
|
7963 if (hw->bus_type != e1000_bus_type_pci_express) |
|
7964 return E1000_SUCCESS; |
|
7965 |
|
7966 e1000_set_pci_express_master_disable(hw); |
|
7967 |
|
7968 while (timeout) { |
|
7969 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
|
7970 break; |
|
7971 else |
|
7972 udelay(100); |
|
7973 timeout--; |
|
7974 } |
|
7975 |
|
7976 if (!timeout) { |
|
7977 DEBUGOUT("Master requests are pending.\n"); |
|
7978 return -E1000_ERR_MASTER_REQUESTS_PENDING; |
|
7979 } |
|
7980 |
|
7981 return E1000_SUCCESS; |
|
7982 } |
|
7983 |
|
7984 /******************************************************************************* |
|
7985 * |
|
7986 * Check for EEPROM Auto Read bit done. |
|
7987 * |
|
7988 * hw: Struct containing variables accessed by shared code |
|
7989 * |
|
7990 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
7991 * E1000_SUCCESS at any other case. |
|
7992 * |
|
7993 ******************************************************************************/ |
|
7994 static int32_t |
|
7995 e1000_get_auto_rd_done(struct e1000_hw *hw) |
|
7996 { |
|
7997 int32_t timeout = AUTO_READ_DONE_TIMEOUT; |
|
7998 |
|
7999 DEBUGFUNC("e1000_get_auto_rd_done"); |
|
8000 |
|
8001 switch (hw->mac_type) { |
|
8002 default: |
|
8003 msleep(5); |
|
8004 break; |
|
8005 case e1000_82571: |
|
8006 case e1000_82572: |
|
8007 case e1000_82573: |
|
8008 case e1000_80003es2lan: |
|
8009 case e1000_ich8lan: |
|
8010 while (timeout) { |
|
8011 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) |
|
8012 break; |
|
8013 else msleep(1); |
|
8014 timeout--; |
|
8015 } |
|
8016 |
|
8017 if (!timeout) { |
|
8018 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
|
8019 return -E1000_ERR_RESET; |
|
8020 } |
|
8021 break; |
|
8022 } |
|
8023 |
|
8024 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
|
8025 * Need to wait for PHY configuration completion before accessing NVM |
|
8026 * and PHY. */ |
|
8027 if (hw->mac_type == e1000_82573) |
|
8028 msleep(25); |
|
8029 |
|
8030 return E1000_SUCCESS; |
|
8031 } |
|
8032 |
|
8033 /*************************************************************************** |
|
8034 * Checks if the PHY configuration is done |
|
8035 * |
|
8036 * hw: Struct containing variables accessed by shared code |
|
8037 * |
|
8038 * returns: - E1000_ERR_RESET if fail to reset MAC |
|
8039 * E1000_SUCCESS at any other case. |
|
8040 * |
|
8041 ***************************************************************************/ |
|
8042 static int32_t |
|
8043 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
8044 { |
|
8045 int32_t timeout = PHY_CFG_TIMEOUT; |
|
8046 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; |
|
8047 |
|
8048 DEBUGFUNC("e1000_get_phy_cfg_done"); |
|
8049 |
|
8050 switch (hw->mac_type) { |
|
8051 default: |
|
8052 mdelay(10); |
|
8053 break; |
|
8054 case e1000_80003es2lan: |
|
8055 /* Separate *_CFG_DONE_* bit for each port */ |
|
8056 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
|
8057 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
|
8058 /* Fall Through */ |
|
8059 case e1000_82571: |
|
8060 case e1000_82572: |
|
8061 while (timeout) { |
|
8062 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
|
8063 break; |
|
8064 else |
|
8065 msleep(1); |
|
8066 timeout--; |
|
8067 } |
|
8068 if (!timeout) { |
|
8069 DEBUGOUT("MNG configuration cycle has not completed.\n"); |
|
8070 return -E1000_ERR_RESET; |
|
8071 } |
|
8072 break; |
|
8073 } |
|
8074 |
|
8075 return E1000_SUCCESS; |
|
8076 } |
|
8077 |
|
8078 /*************************************************************************** |
|
8079 * |
|
8080 * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
|
8081 * adapter or Eeprom access. |
|
8082 * |
|
8083 * hw: Struct containing variables accessed by shared code |
|
8084 * |
|
8085 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
|
8086 * E1000_SUCCESS at any other case. |
|
8087 * |
|
8088 ***************************************************************************/ |
|
8089 static int32_t |
|
8090 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
|
8091 { |
|
8092 int32_t timeout; |
|
8093 uint32_t swsm; |
|
8094 |
|
8095 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); |
|
8096 |
|
8097 if (!hw->eeprom_semaphore_present) |
|
8098 return E1000_SUCCESS; |
|
8099 |
|
8100 if (hw->mac_type == e1000_80003es2lan) { |
|
8101 /* Get the SW semaphore. */ |
|
8102 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) |
|
8103 return -E1000_ERR_EEPROM; |
|
8104 } |
|
8105 |
|
8106 /* Get the FW semaphore. */ |
|
8107 timeout = hw->eeprom.word_size + 1; |
|
8108 while (timeout) { |
|
8109 swsm = E1000_READ_REG(hw, SWSM); |
|
8110 swsm |= E1000_SWSM_SWESMBI; |
|
8111 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8112 /* if we managed to set the bit we got the semaphore. */ |
|
8113 swsm = E1000_READ_REG(hw, SWSM); |
|
8114 if (swsm & E1000_SWSM_SWESMBI) |
|
8115 break; |
|
8116 |
|
8117 udelay(50); |
|
8118 timeout--; |
|
8119 } |
|
8120 |
|
8121 if (!timeout) { |
|
8122 /* Release semaphores */ |
|
8123 e1000_put_hw_eeprom_semaphore(hw); |
|
8124 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); |
|
8125 return -E1000_ERR_EEPROM; |
|
8126 } |
|
8127 |
|
8128 return E1000_SUCCESS; |
|
8129 } |
|
8130 |
|
8131 /*************************************************************************** |
|
8132 * This function clears HW semaphore bits. |
|
8133 * |
|
8134 * hw: Struct containing variables accessed by shared code |
|
8135 * |
|
8136 * returns: - None. |
|
8137 * |
|
8138 ***************************************************************************/ |
|
8139 static void |
|
8140 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
|
8141 { |
|
8142 uint32_t swsm; |
|
8143 |
|
8144 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); |
|
8145 |
|
8146 if (!hw->eeprom_semaphore_present) |
|
8147 return; |
|
8148 |
|
8149 swsm = E1000_READ_REG(hw, SWSM); |
|
8150 if (hw->mac_type == e1000_80003es2lan) { |
|
8151 /* Release both semaphores. */ |
|
8152 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
8153 } else |
|
8154 swsm &= ~(E1000_SWSM_SWESMBI); |
|
8155 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8156 } |
|
8157 |
|
8158 /*************************************************************************** |
|
8159 * |
|
8160 * Obtaining software semaphore bit (SMBI) before resetting PHY. |
|
8161 * |
|
8162 * hw: Struct containing variables accessed by shared code |
|
8163 * |
|
8164 * returns: - E1000_ERR_RESET if fail to obtain semaphore. |
|
8165 * E1000_SUCCESS at any other case. |
|
8166 * |
|
8167 ***************************************************************************/ |
|
8168 static int32_t |
|
8169 e1000_get_software_semaphore(struct e1000_hw *hw) |
|
8170 { |
|
8171 int32_t timeout = hw->eeprom.word_size + 1; |
|
8172 uint32_t swsm; |
|
8173 |
|
8174 DEBUGFUNC("e1000_get_software_semaphore"); |
|
8175 |
|
8176 if (hw->mac_type != e1000_80003es2lan) { |
|
8177 return E1000_SUCCESS; |
|
8178 } |
|
8179 |
|
8180 while (timeout) { |
|
8181 swsm = E1000_READ_REG(hw, SWSM); |
|
8182 /* If SMBI bit cleared, it is now set and we hold the semaphore */ |
|
8183 if (!(swsm & E1000_SWSM_SMBI)) |
|
8184 break; |
|
8185 mdelay(1); |
|
8186 timeout--; |
|
8187 } |
|
8188 |
|
8189 if (!timeout) { |
|
8190 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
|
8191 return -E1000_ERR_RESET; |
|
8192 } |
|
8193 |
|
8194 return E1000_SUCCESS; |
|
8195 } |
|
8196 |
|
8197 /*************************************************************************** |
|
8198 * |
|
8199 * Release semaphore bit (SMBI). |
|
8200 * |
|
8201 * hw: Struct containing variables accessed by shared code |
|
8202 * |
|
8203 ***************************************************************************/ |
|
8204 static void |
|
8205 e1000_release_software_semaphore(struct e1000_hw *hw) |
|
8206 { |
|
8207 uint32_t swsm; |
|
8208 |
|
8209 DEBUGFUNC("e1000_release_software_semaphore"); |
|
8210 |
|
8211 if (hw->mac_type != e1000_80003es2lan) { |
|
8212 return; |
|
8213 } |
|
8214 |
|
8215 swsm = E1000_READ_REG(hw, SWSM); |
|
8216 /* Release the SW semaphores.*/ |
|
8217 swsm &= ~E1000_SWSM_SMBI; |
|
8218 E1000_WRITE_REG(hw, SWSM, swsm); |
|
8219 } |
|
8220 |
|
8221 /****************************************************************************** |
|
8222 * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
|
8223 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
|
8224 * the caller to figure out how to deal with it. |
|
8225 * |
|
8226 * hw - Struct containing variables accessed by shared code |
|
8227 * |
|
8228 * returns: - E1000_BLK_PHY_RESET |
|
8229 * E1000_SUCCESS |
|
8230 * |
|
8231 *****************************************************************************/ |
|
8232 int32_t |
|
8233 e1000_check_phy_reset_block(struct e1000_hw *hw) |
|
8234 { |
|
8235 uint32_t manc = 0; |
|
8236 uint32_t fwsm = 0; |
|
8237 |
|
8238 if (hw->mac_type == e1000_ich8lan) { |
|
8239 fwsm = E1000_READ_REG(hw, FWSM); |
|
8240 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS |
|
8241 : E1000_BLK_PHY_RESET; |
|
8242 } |
|
8243 |
|
8244 if (hw->mac_type > e1000_82547_rev_2) |
|
8245 manc = E1000_READ_REG(hw, MANC); |
|
8246 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
|
8247 E1000_BLK_PHY_RESET : E1000_SUCCESS; |
|
8248 } |
|
8249 |
|
8250 static uint8_t |
|
8251 e1000_arc_subsystem_valid(struct e1000_hw *hw) |
|
8252 { |
|
8253 uint32_t fwsm; |
|
8254 |
|
8255 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC |
|
8256 * may not be provided a DMA clock when no manageability features are |
|
8257 * enabled. We do not want to perform any reads/writes to these registers |
|
8258 * if this is the case. We read FWSM to determine the manageability mode. |
|
8259 */ |
|
8260 switch (hw->mac_type) { |
|
8261 case e1000_82571: |
|
8262 case e1000_82572: |
|
8263 case e1000_82573: |
|
8264 case e1000_80003es2lan: |
|
8265 fwsm = E1000_READ_REG(hw, FWSM); |
|
8266 if ((fwsm & E1000_FWSM_MODE_MASK) != 0) |
|
8267 return TRUE; |
|
8268 break; |
|
8269 case e1000_ich8lan: |
|
8270 return TRUE; |
|
8271 default: |
|
8272 break; |
|
8273 } |
|
8274 return FALSE; |
|
8275 } |
|
8276 |
|
8277 |
|
8278 /****************************************************************************** |
|
8279 * Configure PCI-Ex no-snoop |
|
8280 * |
|
8281 * hw - Struct containing variables accessed by shared code. |
|
8282 * no_snoop - Bitmap of no-snoop events. |
|
8283 * |
|
8284 * returns: E1000_SUCCESS |
|
8285 * |
|
8286 *****************************************************************************/ |
|
8287 static int32_t |
|
8288 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) |
|
8289 { |
|
8290 uint32_t gcr_reg = 0; |
|
8291 |
|
8292 DEBUGFUNC("e1000_set_pci_ex_no_snoop"); |
|
8293 |
|
8294 if (hw->bus_type == e1000_bus_type_unknown) |
|
8295 e1000_get_bus_info(hw); |
|
8296 |
|
8297 if (hw->bus_type != e1000_bus_type_pci_express) |
|
8298 return E1000_SUCCESS; |
|
8299 |
|
8300 if (no_snoop) { |
|
8301 gcr_reg = E1000_READ_REG(hw, GCR); |
|
8302 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); |
|
8303 gcr_reg |= no_snoop; |
|
8304 E1000_WRITE_REG(hw, GCR, gcr_reg); |
|
8305 } |
|
8306 if (hw->mac_type == e1000_ich8lan) { |
|
8307 uint32_t ctrl_ext; |
|
8308 |
|
8309 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); |
|
8310 |
|
8311 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
|
8312 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
|
8313 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
|
8314 } |
|
8315 |
|
8316 return E1000_SUCCESS; |
|
8317 } |
|
8318 |
|
8319 /*************************************************************************** |
|
8320 * |
|
8321 * Get software semaphore FLAG bit (SWFLAG). |
|
8322 * SWFLAG is used to synchronize the access to all shared resource between |
|
8323 * SW, FW and HW. |
|
8324 * |
|
8325 * hw: Struct containing variables accessed by shared code |
|
8326 * |
|
8327 ***************************************************************************/ |
|
8328 static int32_t |
|
8329 e1000_get_software_flag(struct e1000_hw *hw) |
|
8330 { |
|
8331 int32_t timeout = PHY_CFG_TIMEOUT; |
|
8332 uint32_t extcnf_ctrl; |
|
8333 |
|
8334 DEBUGFUNC("e1000_get_software_flag"); |
|
8335 |
|
8336 if (hw->mac_type == e1000_ich8lan) { |
|
8337 while (timeout) { |
|
8338 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8339 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
|
8340 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
8341 |
|
8342 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8343 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
|
8344 break; |
|
8345 mdelay(1); |
|
8346 timeout--; |
|
8347 } |
|
8348 |
|
8349 if (!timeout) { |
|
8350 DEBUGOUT("FW or HW locks the resource too long.\n"); |
|
8351 return -E1000_ERR_CONFIG; |
|
8352 } |
|
8353 } |
|
8354 |
|
8355 return E1000_SUCCESS; |
|
8356 } |
|
8357 |
|
8358 /*************************************************************************** |
|
8359 * |
|
8360 * Release software semaphore FLAG bit (SWFLAG). |
|
8361 * SWFLAG is used to synchronize the access to all shared resource between |
|
8362 * SW, FW and HW. |
|
8363 * |
|
8364 * hw: Struct containing variables accessed by shared code |
|
8365 * |
|
8366 ***************************************************************************/ |
|
8367 static void |
|
8368 e1000_release_software_flag(struct e1000_hw *hw) |
|
8369 { |
|
8370 uint32_t extcnf_ctrl; |
|
8371 |
|
8372 DEBUGFUNC("e1000_release_software_flag"); |
|
8373 |
|
8374 if (hw->mac_type == e1000_ich8lan) { |
|
8375 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); |
|
8376 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
|
8377 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
|
8378 } |
|
8379 |
|
8380 return; |
|
8381 } |
|
8382 |
|
8383 /****************************************************************************** |
|
8384 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access |
|
8385 * register. |
|
8386 * |
|
8387 * hw - Struct containing variables accessed by shared code |
|
8388 * offset - offset of word in the EEPROM to read |
|
8389 * data - word read from the EEPROM |
|
8390 * words - number of words to read |
|
8391 *****************************************************************************/ |
|
8392 static int32_t |
|
8393 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
|
8394 uint16_t *data) |
|
8395 { |
|
8396 int32_t error = E1000_SUCCESS; |
|
8397 uint32_t flash_bank = 0; |
|
8398 uint32_t act_offset = 0; |
|
8399 uint32_t bank_offset = 0; |
|
8400 uint16_t word = 0; |
|
8401 uint16_t i = 0; |
|
8402 |
|
8403 /* We need to know which is the valid flash bank. In the event |
|
8404 * that we didn't allocate eeprom_shadow_ram, we may not be |
|
8405 * managing flash_bank. So it cannot be trusted and needs |
|
8406 * to be updated with each read. |
|
8407 */ |
|
8408 /* Value of bit 22 corresponds to the flash bank we're on. */ |
|
8409 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; |
|
8410 |
|
8411 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ |
|
8412 bank_offset = flash_bank * (hw->flash_bank_size * 2); |
|
8413 |
|
8414 error = e1000_get_software_flag(hw); |
|
8415 if (error != E1000_SUCCESS) |
|
8416 return error; |
|
8417 |
|
8418 for (i = 0; i < words; i++) { |
|
8419 if (hw->eeprom_shadow_ram != NULL && |
|
8420 hw->eeprom_shadow_ram[offset+i].modified == TRUE) { |
|
8421 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; |
|
8422 } else { |
|
8423 /* The NVM part needs a byte offset, hence * 2 */ |
|
8424 act_offset = bank_offset + ((offset + i) * 2); |
|
8425 error = e1000_read_ich8_word(hw, act_offset, &word); |
|
8426 if (error != E1000_SUCCESS) |
|
8427 break; |
|
8428 data[i] = word; |
|
8429 } |
|
8430 } |
|
8431 |
|
8432 e1000_release_software_flag(hw); |
|
8433 |
|
8434 return error; |
|
8435 } |
|
8436 |
|
8437 /****************************************************************************** |
|
8438 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access |
|
8439 * register. Actually, writes are written to the shadow ram cache in the hw |
|
8440 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to |
|
8441 * the NVM, which occurs when the NVM checksum is updated. |
|
8442 * |
|
8443 * hw - Struct containing variables accessed by shared code |
|
8444 * offset - offset of word in the EEPROM to write |
|
8445 * words - number of words to write |
|
8446 * data - words to write to the EEPROM |
|
8447 *****************************************************************************/ |
|
8448 static int32_t |
|
8449 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
|
8450 uint16_t *data) |
|
8451 { |
|
8452 uint32_t i = 0; |
|
8453 int32_t error = E1000_SUCCESS; |
|
8454 |
|
8455 error = e1000_get_software_flag(hw); |
|
8456 if (error != E1000_SUCCESS) |
|
8457 return error; |
|
8458 |
|
8459 /* A driver can write to the NVM only if it has eeprom_shadow_ram |
|
8460 * allocated. Subsequent reads to the modified words are read from |
|
8461 * this cached structure as well. Writes will only go into this |
|
8462 * cached structure unless it's followed by a call to |
|
8463 * e1000_update_eeprom_checksum() where it will commit the changes |
|
8464 * and clear the "modified" field. |
|
8465 */ |
|
8466 if (hw->eeprom_shadow_ram != NULL) { |
|
8467 for (i = 0; i < words; i++) { |
|
8468 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { |
|
8469 hw->eeprom_shadow_ram[offset+i].modified = TRUE; |
|
8470 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; |
|
8471 } else { |
|
8472 error = -E1000_ERR_EEPROM; |
|
8473 break; |
|
8474 } |
|
8475 } |
|
8476 } else { |
|
8477 /* Drivers have the option to not allocate eeprom_shadow_ram as long |
|
8478 * as they don't perform any NVM writes. An attempt in doing so |
|
8479 * will result in this error. |
|
8480 */ |
|
8481 error = -E1000_ERR_EEPROM; |
|
8482 } |
|
8483 |
|
8484 e1000_release_software_flag(hw); |
|
8485 |
|
8486 return error; |
|
8487 } |
|
8488 |
|
8489 /****************************************************************************** |
|
8490 * This function does initial flash setup so that a new read/write/erase cycle |
|
8491 * can be started. |
|
8492 * |
|
8493 * hw - The pointer to the hw structure |
|
8494 ****************************************************************************/ |
|
8495 static int32_t |
|
8496 e1000_ich8_cycle_init(struct e1000_hw *hw) |
|
8497 { |
|
8498 union ich8_hws_flash_status hsfsts; |
|
8499 int32_t error = E1000_ERR_EEPROM; |
|
8500 int32_t i = 0; |
|
8501 |
|
8502 DEBUGFUNC("e1000_ich8_cycle_init"); |
|
8503 |
|
8504 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8505 |
|
8506 /* May be check the Flash Des Valid bit in Hw status */ |
|
8507 if (hsfsts.hsf_status.fldesvalid == 0) { |
|
8508 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); |
|
8509 return error; |
|
8510 } |
|
8511 |
|
8512 /* Clear FCERR in Hw status by writing 1 */ |
|
8513 /* Clear DAEL in Hw status by writing a 1 */ |
|
8514 hsfsts.hsf_status.flcerr = 1; |
|
8515 hsfsts.hsf_status.dael = 1; |
|
8516 |
|
8517 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
|
8518 |
|
8519 /* Either we should have a hardware SPI cycle in progress bit to check |
|
8520 * against, in order to start a new cycle or FDONE bit should be changed |
|
8521 * in the hardware so that it is 1 after harware reset, which can then be |
|
8522 * used as an indication whether a cycle is in progress or has been |
|
8523 * completed .. we should also have some software semaphore mechanism to |
|
8524 * guard FDONE or the cycle in progress bit so that two threads access to |
|
8525 * those bits can be sequentiallized or a way so that 2 threads dont |
|
8526 * start the cycle at the same time */ |
|
8527 |
|
8528 if (hsfsts.hsf_status.flcinprog == 0) { |
|
8529 /* There is no cycle running at present, so we can start a cycle */ |
|
8530 /* Begin by setting Flash Cycle Done. */ |
|
8531 hsfsts.hsf_status.flcdone = 1; |
|
8532 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
|
8533 error = E1000_SUCCESS; |
|
8534 } else { |
|
8535 /* otherwise poll for sometime so the current cycle has a chance |
|
8536 * to end before giving up. */ |
|
8537 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { |
|
8538 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8539 if (hsfsts.hsf_status.flcinprog == 0) { |
|
8540 error = E1000_SUCCESS; |
|
8541 break; |
|
8542 } |
|
8543 udelay(1); |
|
8544 } |
|
8545 if (error == E1000_SUCCESS) { |
|
8546 /* Successful in waiting for previous cycle to timeout, |
|
8547 * now set the Flash Cycle Done. */ |
|
8548 hsfsts.hsf_status.flcdone = 1; |
|
8549 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
|
8550 } else { |
|
8551 DEBUGOUT("Flash controller busy, cannot get access"); |
|
8552 } |
|
8553 } |
|
8554 return error; |
|
8555 } |
|
8556 |
|
8557 /****************************************************************************** |
|
8558 * This function starts a flash cycle and waits for its completion |
|
8559 * |
|
8560 * hw - The pointer to the hw structure |
|
8561 ****************************************************************************/ |
|
8562 static int32_t |
|
8563 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) |
|
8564 { |
|
8565 union ich8_hws_flash_ctrl hsflctl; |
|
8566 union ich8_hws_flash_status hsfsts; |
|
8567 int32_t error = E1000_ERR_EEPROM; |
|
8568 uint32_t i = 0; |
|
8569 |
|
8570 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
|
8571 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
|
8572 hsflctl.hsf_ctrl.flcgo = 1; |
|
8573 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
|
8574 |
|
8575 /* wait till FDONE bit is set to 1 */ |
|
8576 do { |
|
8577 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8578 if (hsfsts.hsf_status.flcdone == 1) |
|
8579 break; |
|
8580 udelay(1); |
|
8581 i++; |
|
8582 } while (i < timeout); |
|
8583 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { |
|
8584 error = E1000_SUCCESS; |
|
8585 } |
|
8586 return error; |
|
8587 } |
|
8588 |
|
8589 /****************************************************************************** |
|
8590 * Reads a byte or word from the NVM using the ICH8 flash access registers. |
|
8591 * |
|
8592 * hw - The pointer to the hw structure |
|
8593 * index - The index of the byte or word to read. |
|
8594 * size - Size of data to read, 1=byte 2=word |
|
8595 * data - Pointer to the word to store the value read. |
|
8596 *****************************************************************************/ |
|
8597 static int32_t |
|
8598 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, |
|
8599 uint32_t size, uint16_t* data) |
|
8600 { |
|
8601 union ich8_hws_flash_status hsfsts; |
|
8602 union ich8_hws_flash_ctrl hsflctl; |
|
8603 uint32_t flash_linear_address; |
|
8604 uint32_t flash_data = 0; |
|
8605 int32_t error = -E1000_ERR_EEPROM; |
|
8606 int32_t count = 0; |
|
8607 |
|
8608 DEBUGFUNC("e1000_read_ich8_data"); |
|
8609 |
|
8610 if (size < 1 || size > 2 || data == NULL || |
|
8611 index > ICH_FLASH_LINEAR_ADDR_MASK) |
|
8612 return error; |
|
8613 |
|
8614 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
|
8615 hw->flash_base_addr; |
|
8616 |
|
8617 do { |
|
8618 udelay(1); |
|
8619 /* Steps */ |
|
8620 error = e1000_ich8_cycle_init(hw); |
|
8621 if (error != E1000_SUCCESS) |
|
8622 break; |
|
8623 |
|
8624 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
|
8625 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
8626 hsflctl.hsf_ctrl.fldbcount = size - 1; |
|
8627 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
|
8628 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
|
8629 |
|
8630 /* Write the last 24 bits of index into Flash Linear address field in |
|
8631 * Flash Address */ |
|
8632 /* TODO: TBD maybe check the index against the size of flash */ |
|
8633 |
|
8634 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
|
8635 |
|
8636 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
|
8637 |
|
8638 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole |
|
8639 * sequence a few more times, else read in (shift in) the Flash Data0, |
|
8640 * the order is least significant byte first msb to lsb */ |
|
8641 if (error == E1000_SUCCESS) { |
|
8642 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); |
|
8643 if (size == 1) { |
|
8644 *data = (uint8_t)(flash_data & 0x000000FF); |
|
8645 } else if (size == 2) { |
|
8646 *data = (uint16_t)(flash_data & 0x0000FFFF); |
|
8647 } |
|
8648 break; |
|
8649 } else { |
|
8650 /* If we've gotten here, then things are probably completely hosed, |
|
8651 * but if the error condition is detected, it won't hurt to give |
|
8652 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
|
8653 */ |
|
8654 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8655 if (hsfsts.hsf_status.flcerr == 1) { |
|
8656 /* Repeat for some time before giving up. */ |
|
8657 continue; |
|
8658 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
8659 DEBUGOUT("Timeout error - flash cycle did not complete."); |
|
8660 break; |
|
8661 } |
|
8662 } |
|
8663 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
|
8664 |
|
8665 return error; |
|
8666 } |
|
8667 |
|
8668 /****************************************************************************** |
|
8669 * Writes One /two bytes to the NVM using the ICH8 flash access registers. |
|
8670 * |
|
8671 * hw - The pointer to the hw structure |
|
8672 * index - The index of the byte/word to read. |
|
8673 * size - Size of data to read, 1=byte 2=word |
|
8674 * data - The byte(s) to write to the NVM. |
|
8675 *****************************************************************************/ |
|
8676 static int32_t |
|
8677 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, |
|
8678 uint16_t data) |
|
8679 { |
|
8680 union ich8_hws_flash_status hsfsts; |
|
8681 union ich8_hws_flash_ctrl hsflctl; |
|
8682 uint32_t flash_linear_address; |
|
8683 uint32_t flash_data = 0; |
|
8684 int32_t error = -E1000_ERR_EEPROM; |
|
8685 int32_t count = 0; |
|
8686 |
|
8687 DEBUGFUNC("e1000_write_ich8_data"); |
|
8688 |
|
8689 if (size < 1 || size > 2 || data > size * 0xff || |
|
8690 index > ICH_FLASH_LINEAR_ADDR_MASK) |
|
8691 return error; |
|
8692 |
|
8693 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
|
8694 hw->flash_base_addr; |
|
8695 |
|
8696 do { |
|
8697 udelay(1); |
|
8698 /* Steps */ |
|
8699 error = e1000_ich8_cycle_init(hw); |
|
8700 if (error != E1000_SUCCESS) |
|
8701 break; |
|
8702 |
|
8703 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
|
8704 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
|
8705 hsflctl.hsf_ctrl.fldbcount = size -1; |
|
8706 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
|
8707 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
|
8708 |
|
8709 /* Write the last 24 bits of index into Flash Linear address field in |
|
8710 * Flash Address */ |
|
8711 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
|
8712 |
|
8713 if (size == 1) |
|
8714 flash_data = (uint32_t)data & 0x00FF; |
|
8715 else |
|
8716 flash_data = (uint32_t)data; |
|
8717 |
|
8718 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); |
|
8719 |
|
8720 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole |
|
8721 * sequence a few more times else done */ |
|
8722 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
|
8723 if (error == E1000_SUCCESS) { |
|
8724 break; |
|
8725 } else { |
|
8726 /* If we're here, then things are most likely completely hosed, |
|
8727 * but if the error condition is detected, it won't hurt to give |
|
8728 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
|
8729 */ |
|
8730 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8731 if (hsfsts.hsf_status.flcerr == 1) { |
|
8732 /* Repeat for some time before giving up. */ |
|
8733 continue; |
|
8734 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
8735 DEBUGOUT("Timeout error - flash cycle did not complete."); |
|
8736 break; |
|
8737 } |
|
8738 } |
|
8739 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
|
8740 |
|
8741 return error; |
|
8742 } |
|
8743 |
|
8744 /****************************************************************************** |
|
8745 * Reads a single byte from the NVM using the ICH8 flash access registers. |
|
8746 * |
|
8747 * hw - pointer to e1000_hw structure |
|
8748 * index - The index of the byte to read. |
|
8749 * data - Pointer to a byte to store the value read. |
|
8750 *****************************************************************************/ |
|
8751 static int32_t |
|
8752 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) |
|
8753 { |
|
8754 int32_t status = E1000_SUCCESS; |
|
8755 uint16_t word = 0; |
|
8756 |
|
8757 status = e1000_read_ich8_data(hw, index, 1, &word); |
|
8758 if (status == E1000_SUCCESS) { |
|
8759 *data = (uint8_t)word; |
|
8760 } |
|
8761 |
|
8762 return status; |
|
8763 } |
|
8764 |
|
8765 /****************************************************************************** |
|
8766 * Writes a single byte to the NVM using the ICH8 flash access registers. |
|
8767 * Performs verification by reading back the value and then going through |
|
8768 * a retry algorithm before giving up. |
|
8769 * |
|
8770 * hw - pointer to e1000_hw structure |
|
8771 * index - The index of the byte to write. |
|
8772 * byte - The byte to write to the NVM. |
|
8773 *****************************************************************************/ |
|
8774 static int32_t |
|
8775 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) |
|
8776 { |
|
8777 int32_t error = E1000_SUCCESS; |
|
8778 int32_t program_retries = 0; |
|
8779 |
|
8780 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); |
|
8781 |
|
8782 error = e1000_write_ich8_byte(hw, index, byte); |
|
8783 |
|
8784 if (error != E1000_SUCCESS) { |
|
8785 for (program_retries = 0; program_retries < 100; program_retries++) { |
|
8786 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); |
|
8787 error = e1000_write_ich8_byte(hw, index, byte); |
|
8788 udelay(100); |
|
8789 if (error == E1000_SUCCESS) |
|
8790 break; |
|
8791 } |
|
8792 } |
|
8793 |
|
8794 if (program_retries == 100) |
|
8795 error = E1000_ERR_EEPROM; |
|
8796 |
|
8797 return error; |
|
8798 } |
|
8799 |
|
8800 /****************************************************************************** |
|
8801 * Writes a single byte to the NVM using the ICH8 flash access registers. |
|
8802 * |
|
8803 * hw - pointer to e1000_hw structure |
|
8804 * index - The index of the byte to read. |
|
8805 * data - The byte to write to the NVM. |
|
8806 *****************************************************************************/ |
|
8807 static int32_t |
|
8808 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) |
|
8809 { |
|
8810 int32_t status = E1000_SUCCESS; |
|
8811 uint16_t word = (uint16_t)data; |
|
8812 |
|
8813 status = e1000_write_ich8_data(hw, index, 1, word); |
|
8814 |
|
8815 return status; |
|
8816 } |
|
8817 |
|
8818 /****************************************************************************** |
|
8819 * Reads a word from the NVM using the ICH8 flash access registers. |
|
8820 * |
|
8821 * hw - pointer to e1000_hw structure |
|
8822 * index - The starting byte index of the word to read. |
|
8823 * data - Pointer to a word to store the value read. |
|
8824 *****************************************************************************/ |
|
8825 static int32_t |
|
8826 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) |
|
8827 { |
|
8828 int32_t status = E1000_SUCCESS; |
|
8829 status = e1000_read_ich8_data(hw, index, 2, data); |
|
8830 return status; |
|
8831 } |
|
8832 |
|
8833 /****************************************************************************** |
|
8834 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 |
|
8835 * based. |
|
8836 * |
|
8837 * hw - pointer to e1000_hw structure |
|
8838 * bank - 0 for first bank, 1 for second bank |
|
8839 * |
|
8840 * Note that this function may actually erase as much as 8 or 64 KBytes. The |
|
8841 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the |
|
8842 * bank size may be 4, 8 or 64 KBytes |
|
8843 *****************************************************************************/ |
|
8844 static int32_t |
|
8845 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) |
|
8846 { |
|
8847 union ich8_hws_flash_status hsfsts; |
|
8848 union ich8_hws_flash_ctrl hsflctl; |
|
8849 uint32_t flash_linear_address; |
|
8850 int32_t count = 0; |
|
8851 int32_t error = E1000_ERR_EEPROM; |
|
8852 int32_t iteration; |
|
8853 int32_t sub_sector_size = 0; |
|
8854 int32_t bank_size; |
|
8855 int32_t j = 0; |
|
8856 int32_t error_flag = 0; |
|
8857 |
|
8858 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8859 |
|
8860 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ |
|
8861 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 |
|
8862 * consecutive sectors. The start index for the nth Hw sector can be |
|
8863 * calculated as bank * 4096 + n * 256 |
|
8864 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
|
8865 * The start index for the nth Hw sector can be calculated |
|
8866 * as bank * 4096 |
|
8867 * 10: The HW sector is 8K bytes |
|
8868 * 11: The Hw sector size is 64K bytes */ |
|
8869 if (hsfsts.hsf_status.berasesz == 0x0) { |
|
8870 /* Hw sector size 256 */ |
|
8871 sub_sector_size = ICH_FLASH_SEG_SIZE_256; |
|
8872 bank_size = ICH_FLASH_SECTOR_SIZE; |
|
8873 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; |
|
8874 } else if (hsfsts.hsf_status.berasesz == 0x1) { |
|
8875 bank_size = ICH_FLASH_SEG_SIZE_4K; |
|
8876 iteration = 1; |
|
8877 } else if (hsfsts.hsf_status.berasesz == 0x3) { |
|
8878 bank_size = ICH_FLASH_SEG_SIZE_64K; |
|
8879 iteration = 1; |
|
8880 } else { |
|
8881 return error; |
|
8882 } |
|
8883 |
|
8884 for (j = 0; j < iteration ; j++) { |
|
8885 do { |
|
8886 count++; |
|
8887 /* Steps */ |
|
8888 error = e1000_ich8_cycle_init(hw); |
|
8889 if (error != E1000_SUCCESS) { |
|
8890 error_flag = 1; |
|
8891 break; |
|
8892 } |
|
8893 |
|
8894 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash |
|
8895 * Control */ |
|
8896 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
|
8897 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; |
|
8898 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
|
8899 |
|
8900 /* Write the last 24 bits of an index within the block into Flash |
|
8901 * Linear address field in Flash Address. This probably needs to |
|
8902 * be calculated here based off the on-chip erase sector size and |
|
8903 * the software bank size (4, 8 or 64 KBytes) */ |
|
8904 flash_linear_address = bank * bank_size + j * sub_sector_size; |
|
8905 flash_linear_address += hw->flash_base_addr; |
|
8906 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; |
|
8907 |
|
8908 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
|
8909 |
|
8910 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); |
|
8911 /* Check if FCERR is set to 1. If 1, clear it and try the whole |
|
8912 * sequence a few more times else Done */ |
|
8913 if (error == E1000_SUCCESS) { |
|
8914 break; |
|
8915 } else { |
|
8916 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
|
8917 if (hsfsts.hsf_status.flcerr == 1) { |
|
8918 /* repeat for some time before giving up */ |
|
8919 continue; |
|
8920 } else if (hsfsts.hsf_status.flcdone == 0) { |
|
8921 error_flag = 1; |
|
8922 break; |
|
8923 } |
|
8924 } |
|
8925 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); |
|
8926 if (error_flag == 1) |
|
8927 break; |
|
8928 } |
|
8929 if (error_flag != 1) |
|
8930 error = E1000_SUCCESS; |
|
8931 return error; |
|
8932 } |
|
8933 |
|
8934 static int32_t |
|
8935 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
|
8936 uint32_t cnf_base_addr, uint32_t cnf_size) |
|
8937 { |
|
8938 uint32_t ret_val = E1000_SUCCESS; |
|
8939 uint16_t word_addr, reg_data, reg_addr; |
|
8940 uint16_t i; |
|
8941 |
|
8942 /* cnf_base_addr is in DWORD */ |
|
8943 word_addr = (uint16_t)(cnf_base_addr << 1); |
|
8944 |
|
8945 /* cnf_size is returned in size of dwords */ |
|
8946 for (i = 0; i < cnf_size; i++) { |
|
8947 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); |
|
8948 if (ret_val) |
|
8949 return ret_val; |
|
8950 |
|
8951 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); |
|
8952 if (ret_val) |
|
8953 return ret_val; |
|
8954 |
|
8955 ret_val = e1000_get_software_flag(hw); |
|
8956 if (ret_val != E1000_SUCCESS) |
|
8957 return ret_val; |
|
8958 |
|
8959 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); |
|
8960 |
|
8961 e1000_release_software_flag(hw); |
|
8962 } |
|
8963 |
|
8964 return ret_val; |
|
8965 } |
|
8966 |
|
8967 |
|
8968 /****************************************************************************** |
|
8969 * This function initializes the PHY from the NVM on ICH8 platforms. This |
|
8970 * is needed due to an issue where the NVM configuration is not properly |
|
8971 * autoloaded after power transitions. Therefore, after each PHY reset, we |
|
8972 * will load the configuration data out of the NVM manually. |
|
8973 * |
|
8974 * hw: Struct containing variables accessed by shared code |
|
8975 *****************************************************************************/ |
|
8976 static int32_t |
|
8977 e1000_init_lcd_from_nvm(struct e1000_hw *hw) |
|
8978 { |
|
8979 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; |
|
8980 |
|
8981 if (hw->phy_type != e1000_phy_igp_3) |
|
8982 return E1000_SUCCESS; |
|
8983 |
|
8984 /* Check if SW needs configure the PHY */ |
|
8985 reg_data = E1000_READ_REG(hw, FEXTNVM); |
|
8986 if (!(reg_data & FEXTNVM_SW_CONFIG)) |
|
8987 return E1000_SUCCESS; |
|
8988 |
|
8989 /* Wait for basic configuration completes before proceeding*/ |
|
8990 loop = 0; |
|
8991 do { |
|
8992 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; |
|
8993 udelay(100); |
|
8994 loop++; |
|
8995 } while ((!reg_data) && (loop < 50)); |
|
8996 |
|
8997 /* Clear the Init Done bit for the next init event */ |
|
8998 reg_data = E1000_READ_REG(hw, STATUS); |
|
8999 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; |
|
9000 E1000_WRITE_REG(hw, STATUS, reg_data); |
|
9001 |
|
9002 /* Make sure HW does not configure LCD from PHY extended configuration |
|
9003 before SW configuration */ |
|
9004 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
9005 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { |
|
9006 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); |
|
9007 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; |
|
9008 cnf_size >>= 16; |
|
9009 if (cnf_size) { |
|
9010 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
|
9011 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; |
|
9012 /* cnf_base_addr is in DWORD */ |
|
9013 cnf_base_addr >>= 16; |
|
9014 |
|
9015 /* Configure LCD from extended configuration region. */ |
|
9016 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, |
|
9017 cnf_size); |
|
9018 if (ret_val) |
|
9019 return ret_val; |
|
9020 } |
|
9021 } |
|
9022 |
|
9023 return E1000_SUCCESS; |
|
9024 } |
|
9025 |