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1 /****************************************************************************** |
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2 * |
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3 * $Id$ |
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4 * |
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5 * Copyright (C) 2006 Florian Pose, Ingenieurgemeinschaft IgH |
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6 * |
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7 * This file is part of the IgH EtherCAT Master. |
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8 * |
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9 * The IgH EtherCAT Master is free software; you can redistribute it |
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10 * and/or modify it under the terms of the GNU General Public License |
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11 * as published by the Free Software Foundation; either version 2 of the |
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12 * License, or (at your option) any later version. |
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13 * |
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14 * The IgH EtherCAT Master is distributed in the hope that it will be |
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15 * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 * GNU General Public License for more details. |
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18 * |
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19 * You should have received a copy of the GNU General Public License |
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20 * along with the IgH EtherCAT Master; if not, write to the Free Software |
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21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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22 * |
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23 * The right to use EtherCAT Technology is granted and comes free of |
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24 * charge under condition of compatibility of product made by |
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25 * Licensee. People intending to distribute/sell products based on the |
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26 * code, have to sign an agreement to guarantee that products using |
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27 * software based on IgH EtherCAT master stay compatible with the actual |
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28 * EtherCAT specification (which are released themselves as an open |
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29 * standard) as the (only) precondition to have the right to use EtherCAT |
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30 * Technology, IP and trade marks. |
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31 * |
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32 *****************************************************************************/ |
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33 |
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34 /* |
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35 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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36 * |
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37 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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38 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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39 * Copyright (c) a lot of people too. Please respect their work. |
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40 * |
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41 * See MAINTAINERS file for support contact information. |
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42 */ |
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43 |
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44 #include <linux/module.h> |
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45 #include <linux/moduleparam.h> |
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46 #include <linux/pci.h> |
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47 #include <linux/netdevice.h> |
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48 #include <linux/etherdevice.h> |
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49 #include <linux/delay.h> |
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50 #include <linux/ethtool.h> |
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51 #include <linux/mii.h> |
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52 #include <linux/if_vlan.h> |
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53 #include <linux/crc32.h> |
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54 #include <linux/in.h> |
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55 #include <linux/ip.h> |
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56 #include <linux/tcp.h> |
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57 #include <linux/init.h> |
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58 #include <linux/dma-mapping.h> |
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59 |
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60 #include <asm/system.h> |
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61 #include <asm/io.h> |
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62 #include <asm/irq.h> |
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63 |
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64 #ifdef CONFIG_R8169_NAPI |
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65 #define NAPI_SUFFIX "-NAPI" |
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66 #else |
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67 #define NAPI_SUFFIX "" |
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68 #endif |
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69 |
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70 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX |
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71 #define MODULENAME "r8169" |
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72 #define PFX MODULENAME ": " |
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73 |
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74 #include "../globals.h" |
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75 #include "ecdev.h" |
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76 |
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77 #ifdef RTL8169_DEBUG |
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78 #define assert(expr) \ |
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79 if (!(expr)) { \ |
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80 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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81 #expr,__FILE__,__FUNCTION__,__LINE__); \ |
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82 } |
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83 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) |
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84 #else |
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85 #define assert(expr) do {} while (0) |
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86 #define dprintk(fmt, args...) do {} while (0) |
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87 #endif /* RTL8169_DEBUG */ |
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88 |
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89 #define R8169_MSG_DEFAULT \ |
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90 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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91 |
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92 #define TX_BUFFS_AVAIL(tp) \ |
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93 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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94 |
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95 #ifdef CONFIG_R8169_NAPI |
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96 #define rtl8169_rx_skb netif_receive_skb |
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97 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb |
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98 #define rtl8169_rx_quota(count, quota) min(count, quota) |
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99 #else |
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100 #define rtl8169_rx_skb netif_rx |
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101 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx |
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102 #define rtl8169_rx_quota(count, quota) count |
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103 #endif |
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104 |
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105 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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106 static const int max_interrupt_work = 20; |
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107 |
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108 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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109 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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110 static const int multicast_filter_limit = 32; |
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111 |
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112 /* MAC address length */ |
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113 #define MAC_ADDR_LEN 6 |
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114 |
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115 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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116 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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117 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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118 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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119 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
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120 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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121 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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122 |
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123 #define R8169_REGS_SIZE 256 |
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124 #define R8169_NAPI_WEIGHT 64 |
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125 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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126 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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127 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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128 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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129 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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130 |
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131 #define RTL8169_TX_TIMEOUT (6*HZ) |
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132 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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133 |
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134 /* write/read MMIO register */ |
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135 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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136 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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137 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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138 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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139 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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140 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
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141 |
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142 enum mac_version { |
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143 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
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144 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
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145 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
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146 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
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147 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
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148 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
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149 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
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150 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf |
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151 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec |
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152 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 |
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153 RTL_GIGA_MAC_VER_15 = 0x0f // 8101 |
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154 }; |
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155 |
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156 enum phy_version { |
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157 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */ |
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158 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */ |
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159 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */ |
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160 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */ |
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161 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */ |
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162 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ |
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163 }; |
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164 |
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165 #define _R(NAME,MAC,MASK) \ |
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166 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
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167 |
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168 static const struct { |
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169 const char *name; |
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170 u8 mac_version; |
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171 u32 RxConfigMask; /* Clears the bits supported by this chip */ |
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172 } rtl_chip_info[] = { |
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173 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
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174 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S |
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175 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S |
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176 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB |
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177 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd |
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178 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
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179 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
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180 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
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181 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
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182 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
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183 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139 |
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184 }; |
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185 #undef _R |
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186 |
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187 enum cfg_version { |
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188 RTL_CFG_0 = 0x00, |
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189 RTL_CFG_1, |
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190 RTL_CFG_2 |
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191 }; |
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192 |
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193 static void rtl_hw_start_8169(struct net_device *); |
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194 static void rtl_hw_start_8168(struct net_device *); |
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195 static void rtl_hw_start_8101(struct net_device *); |
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196 |
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197 static struct pci_device_id rtl8169_pci_tbl[] = { |
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198 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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199 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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200 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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201 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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202 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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203 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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204 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 }, |
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205 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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206 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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207 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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208 {0,}, |
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209 }; |
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210 |
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211 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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212 |
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213 static int rx_copybreak = 200; |
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214 static int use_dac; |
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215 static struct { |
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216 u32 msg_enable; |
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217 } debug = { -1 }; |
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218 |
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219 enum rtl_registers { |
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220 MAC0 = 0, /* Ethernet hardware address. */ |
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221 MAC4 = 4, |
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222 MAR0 = 8, /* Multicast filter. */ |
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223 CounterAddrLow = 0x10, |
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224 CounterAddrHigh = 0x14, |
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225 TxDescStartAddrLow = 0x20, |
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226 TxDescStartAddrHigh = 0x24, |
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227 TxHDescStartAddrLow = 0x28, |
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228 TxHDescStartAddrHigh = 0x2c, |
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229 FLASH = 0x30, |
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230 ERSR = 0x36, |
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231 ChipCmd = 0x37, |
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232 TxPoll = 0x38, |
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233 IntrMask = 0x3c, |
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234 IntrStatus = 0x3e, |
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235 TxConfig = 0x40, |
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236 RxConfig = 0x44, |
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237 RxMissed = 0x4c, |
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238 Cfg9346 = 0x50, |
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239 Config0 = 0x51, |
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240 Config1 = 0x52, |
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241 Config2 = 0x53, |
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242 Config3 = 0x54, |
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243 Config4 = 0x55, |
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244 Config5 = 0x56, |
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245 MultiIntr = 0x5c, |
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246 PHYAR = 0x60, |
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247 TBICSR = 0x64, |
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248 TBI_ANAR = 0x68, |
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249 TBI_LPAR = 0x6a, |
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250 PHYstatus = 0x6c, |
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251 RxMaxSize = 0xda, |
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252 CPlusCmd = 0xe0, |
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253 IntrMitigate = 0xe2, |
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254 RxDescAddrLow = 0xe4, |
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255 RxDescAddrHigh = 0xe8, |
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256 EarlyTxThres = 0xec, |
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257 FuncEvent = 0xf0, |
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258 FuncEventMask = 0xf4, |
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259 FuncPresetState = 0xf8, |
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260 FuncForceEvent = 0xfc, |
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261 }; |
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262 |
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263 enum rtl_register_content { |
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264 /* InterruptStatusBits */ |
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265 SYSErr = 0x8000, |
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266 PCSTimeout = 0x4000, |
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267 SWInt = 0x0100, |
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268 TxDescUnavail = 0x0080, |
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269 RxFIFOOver = 0x0040, |
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270 LinkChg = 0x0020, |
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271 RxOverflow = 0x0010, |
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272 TxErr = 0x0008, |
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273 TxOK = 0x0004, |
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274 RxErr = 0x0002, |
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275 RxOK = 0x0001, |
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276 |
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277 /* RxStatusDesc */ |
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278 RxFOVF = (1 << 23), |
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279 RxRWT = (1 << 22), |
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280 RxRES = (1 << 21), |
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281 RxRUNT = (1 << 20), |
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282 RxCRC = (1 << 19), |
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283 |
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284 /* ChipCmdBits */ |
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285 CmdReset = 0x10, |
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286 CmdRxEnb = 0x08, |
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287 CmdTxEnb = 0x04, |
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288 RxBufEmpty = 0x01, |
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289 |
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290 /* TXPoll register p.5 */ |
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291 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
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292 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
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293 FSWInt = 0x01, /* Forced software interrupt */ |
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294 |
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295 /* Cfg9346Bits */ |
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296 Cfg9346_Lock = 0x00, |
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297 Cfg9346_Unlock = 0xc0, |
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298 |
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299 /* rx_mode_bits */ |
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300 AcceptErr = 0x20, |
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301 AcceptRunt = 0x10, |
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302 AcceptBroadcast = 0x08, |
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303 AcceptMulticast = 0x04, |
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304 AcceptMyPhys = 0x02, |
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305 AcceptAllPhys = 0x01, |
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306 |
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307 /* RxConfigBits */ |
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308 RxCfgFIFOShift = 13, |
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309 RxCfgDMAShift = 8, |
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310 |
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311 /* TxConfigBits */ |
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312 TxInterFrameGapShift = 24, |
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313 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
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314 |
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315 /* Config1 register p.24 */ |
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316 PMEnable = (1 << 0), /* Power Management Enable */ |
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317 |
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318 /* Config2 register p. 25 */ |
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319 PCI_Clock_66MHz = 0x01, |
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320 PCI_Clock_33MHz = 0x00, |
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321 |
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322 /* Config3 register p.25 */ |
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323 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
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324 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
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325 |
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326 /* Config5 register p.27 */ |
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327 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
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328 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
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329 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
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330 LanWake = (1 << 1), /* LanWake enable/disable */ |
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331 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
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332 |
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333 /* TBICSR p.28 */ |
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334 TBIReset = 0x80000000, |
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335 TBILoopback = 0x40000000, |
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336 TBINwEnable = 0x20000000, |
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337 TBINwRestart = 0x10000000, |
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338 TBILinkOk = 0x02000000, |
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339 TBINwComplete = 0x01000000, |
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340 |
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341 /* CPlusCmd p.31 */ |
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342 PktCntrDisable = (1 << 7), // 8168 |
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343 RxVlan = (1 << 6), |
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344 RxChkSum = (1 << 5), |
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345 PCIDAC = (1 << 4), |
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346 PCIMulRW = (1 << 3), |
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347 INTT_0 = 0x0000, // 8168 |
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348 INTT_1 = 0x0001, // 8168 |
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349 INTT_2 = 0x0002, // 8168 |
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350 INTT_3 = 0x0003, // 8168 |
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351 |
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352 /* rtl8169_PHYstatus */ |
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353 TBI_Enable = 0x80, |
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354 TxFlowCtrl = 0x40, |
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355 RxFlowCtrl = 0x20, |
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356 _1000bpsF = 0x10, |
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357 _100bps = 0x08, |
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358 _10bps = 0x04, |
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359 LinkStatus = 0x02, |
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360 FullDup = 0x01, |
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361 |
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362 /* _TBICSRBit */ |
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363 TBILinkOK = 0x02000000, |
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364 |
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365 /* DumpCounterCommand */ |
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366 CounterDump = 0x8, |
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367 }; |
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368 |
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369 enum desc_status_bit { |
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370 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
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371 RingEnd = (1 << 30), /* End of descriptor ring */ |
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372 FirstFrag = (1 << 29), /* First segment of a packet */ |
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373 LastFrag = (1 << 28), /* Final segment of a packet */ |
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374 |
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375 /* Tx private */ |
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376 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
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377 MSSShift = 16, /* MSS value position */ |
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378 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
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379 IPCS = (1 << 18), /* Calculate IP checksum */ |
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380 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
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381 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
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382 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
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383 |
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384 /* Rx private */ |
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385 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
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386 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
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387 |
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388 #define RxProtoUDP (PID1) |
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389 #define RxProtoTCP (PID0) |
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390 #define RxProtoIP (PID1 | PID0) |
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391 #define RxProtoMask RxProtoIP |
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392 |
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393 IPFail = (1 << 16), /* IP checksum failed */ |
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394 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
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395 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
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396 RxVlanTag = (1 << 16), /* VLAN tag available */ |
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397 }; |
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398 |
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399 #define RsvdMask 0x3fffc000 |
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400 |
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401 struct TxDesc { |
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402 __le32 opts1; |
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403 __le32 opts2; |
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404 __le64 addr; |
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405 }; |
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406 |
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407 struct RxDesc { |
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408 __le32 opts1; |
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409 __le32 opts2; |
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410 __le64 addr; |
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411 }; |
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412 |
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413 struct ring_info { |
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414 struct sk_buff *skb; |
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415 u32 len; |
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416 u8 __pad[sizeof(void *) - sizeof(u32)]; |
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417 }; |
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418 |
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419 struct rtl8169_private { |
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420 void __iomem *mmio_addr; /* memory map physical address */ |
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421 struct pci_dev *pci_dev; /* Index of PCI device */ |
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422 struct net_device *dev; |
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423 struct net_device_stats stats; /* statistics of net device */ |
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424 spinlock_t lock; /* spin lock flag */ |
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425 u32 msg_enable; |
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426 int chipset; |
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427 int mac_version; |
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428 int phy_version; |
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429 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
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430 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
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431 u32 dirty_rx; |
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432 u32 dirty_tx; |
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433 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
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434 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
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435 dma_addr_t TxPhyAddr; |
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436 dma_addr_t RxPhyAddr; |
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437 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
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438 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
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439 unsigned align; |
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440 unsigned rx_buf_sz; |
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441 struct timer_list timer; |
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442 u16 cp_cmd; |
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443 u16 intr_event; |
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444 u16 napi_event; |
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445 u16 intr_mask; |
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446 int phy_auto_nego_reg; |
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447 int phy_1000_ctrl_reg; |
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448 #ifdef CONFIG_R8169_VLAN |
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449 struct vlan_group *vlgrp; |
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450 #endif |
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451 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
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452 void (*get_settings)(struct net_device *, struct ethtool_cmd *); |
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453 void (*phy_reset_enable)(void __iomem *); |
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454 void (*hw_start)(struct net_device *); |
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455 unsigned int (*phy_reset_pending)(void __iomem *); |
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456 unsigned int (*link_ok)(void __iomem *); |
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457 struct delayed_work task; |
|
458 unsigned wol_enabled : 1; |
|
459 |
|
460 ec_device_t *ecdev; |
|
461 }; |
|
462 |
|
463 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
464 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet/EtherCAT driver"); |
|
465 module_param(rx_copybreak, int, 0); |
|
466 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
|
467 module_param(use_dac, int, 0); |
|
468 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
469 module_param_named(debug, debug.msg_enable, int, 0); |
|
470 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
471 MODULE_LICENSE("GPL"); |
|
472 MODULE_VERSION(RTL8169_VERSION); |
|
473 |
|
474 void ec_poll(struct net_device *); |
|
475 |
|
476 static int rtl8169_open(struct net_device *dev); |
|
477 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); |
|
478 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
479 static int rtl8169_init_ring(struct net_device *dev); |
|
480 static void rtl_hw_start(struct net_device *dev); |
|
481 static int rtl8169_close(struct net_device *dev); |
|
482 static void rtl_set_rx_mode(struct net_device *dev); |
|
483 static void rtl8169_tx_timeout(struct net_device *dev); |
|
484 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
485 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
486 void __iomem *); |
|
487 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
488 static void rtl8169_down(struct net_device *dev); |
|
489 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
490 |
|
491 #ifdef CONFIG_R8169_NAPI |
|
492 static int rtl8169_poll(struct net_device *dev, int *budget); |
|
493 #endif |
|
494 |
|
495 static const unsigned int rtl8169_rx_config = |
|
496 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
497 |
|
498 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
499 { |
|
500 int i; |
|
501 |
|
502 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value); |
|
503 |
|
504 for (i = 20; i > 0; i--) { |
|
505 /* |
|
506 * Check if the RTL8169 has completed writing to the specified |
|
507 * MII register. |
|
508 */ |
|
509 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
510 break; |
|
511 udelay(25); |
|
512 } |
|
513 } |
|
514 |
|
515 static int mdio_read(void __iomem *ioaddr, int reg_addr) |
|
516 { |
|
517 int i, value = -1; |
|
518 |
|
519 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16); |
|
520 |
|
521 for (i = 20; i > 0; i--) { |
|
522 /* |
|
523 * Check if the RTL8169 has completed retrieving data from |
|
524 * the specified MII register. |
|
525 */ |
|
526 if (RTL_R32(PHYAR) & 0x80000000) { |
|
527 value = (int) (RTL_R32(PHYAR) & 0xFFFF); |
|
528 break; |
|
529 } |
|
530 udelay(25); |
|
531 } |
|
532 return value; |
|
533 } |
|
534 |
|
535 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
536 { |
|
537 RTL_W16(IntrMask, 0x0000); |
|
538 |
|
539 RTL_W16(IntrStatus, 0xffff); |
|
540 } |
|
541 |
|
542 static void rtl8169_asic_down(void __iomem *ioaddr) |
|
543 { |
|
544 RTL_W8(ChipCmd, 0x00); |
|
545 rtl8169_irq_mask_and_ack(ioaddr); |
|
546 RTL_R16(CPlusCmd); |
|
547 } |
|
548 |
|
549 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
550 { |
|
551 return RTL_R32(TBICSR) & TBIReset; |
|
552 } |
|
553 |
|
554 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
555 { |
|
556 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
557 } |
|
558 |
|
559 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
560 { |
|
561 return RTL_R32(TBICSR) & TBILinkOk; |
|
562 } |
|
563 |
|
564 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
565 { |
|
566 return RTL_R8(PHYstatus) & LinkStatus; |
|
567 } |
|
568 |
|
569 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
570 { |
|
571 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
572 } |
|
573 |
|
574 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
575 { |
|
576 unsigned int val; |
|
577 |
|
578 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
579 mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
580 } |
|
581 |
|
582 static void rtl8169_check_link_status(struct net_device *dev, |
|
583 struct rtl8169_private *tp, |
|
584 void __iomem *ioaddr) |
|
585 { |
|
586 unsigned long flags; |
|
587 |
|
588 spin_lock_irqsave(&tp->lock, flags); |
|
589 |
|
590 if (tp->link_ok(ioaddr)) { |
|
591 if(tp->ecdev) { |
|
592 ecdev_set_link(tp->ecdev, 1); |
|
593 } else { |
|
594 netif_carrier_on(dev); |
|
595 if (netif_msg_ifup(tp)) |
|
596 printk(KERN_INFO PFX "%s: link up\n", dev->name); |
|
597 } |
|
598 } else { |
|
599 if(tp->ecdev) { |
|
600 ecdev_set_link(tp->ecdev, 0); |
|
601 } else { |
|
602 if (netif_msg_ifdown(tp)) |
|
603 printk(KERN_INFO PFX "%s: link down\n", dev->name); |
|
604 netif_carrier_off(dev); |
|
605 } |
|
606 } |
|
607 spin_unlock_irqrestore(&tp->lock, flags); |
|
608 } |
|
609 |
|
610 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
611 { |
|
612 struct rtl8169_private *tp = netdev_priv(dev); |
|
613 void __iomem *ioaddr = tp->mmio_addr; |
|
614 u8 options; |
|
615 |
|
616 wol->wolopts = 0; |
|
617 |
|
618 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
619 wol->supported = WAKE_ANY; |
|
620 |
|
621 spin_lock_irq(&tp->lock); |
|
622 |
|
623 options = RTL_R8(Config1); |
|
624 if (!(options & PMEnable)) |
|
625 goto out_unlock; |
|
626 |
|
627 options = RTL_R8(Config3); |
|
628 if (options & LinkUp) |
|
629 wol->wolopts |= WAKE_PHY; |
|
630 if (options & MagicPacket) |
|
631 wol->wolopts |= WAKE_MAGIC; |
|
632 |
|
633 options = RTL_R8(Config5); |
|
634 if (options & UWF) |
|
635 wol->wolopts |= WAKE_UCAST; |
|
636 if (options & BWF) |
|
637 wol->wolopts |= WAKE_BCAST; |
|
638 if (options & MWF) |
|
639 wol->wolopts |= WAKE_MCAST; |
|
640 |
|
641 out_unlock: |
|
642 spin_unlock_irq(&tp->lock); |
|
643 } |
|
644 |
|
645 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
646 { |
|
647 struct rtl8169_private *tp = netdev_priv(dev); |
|
648 void __iomem *ioaddr = tp->mmio_addr; |
|
649 unsigned int i; |
|
650 static struct { |
|
651 u32 opt; |
|
652 u16 reg; |
|
653 u8 mask; |
|
654 } cfg[] = { |
|
655 { WAKE_ANY, Config1, PMEnable }, |
|
656 { WAKE_PHY, Config3, LinkUp }, |
|
657 { WAKE_MAGIC, Config3, MagicPacket }, |
|
658 { WAKE_UCAST, Config5, UWF }, |
|
659 { WAKE_BCAST, Config5, BWF }, |
|
660 { WAKE_MCAST, Config5, MWF }, |
|
661 { WAKE_ANY, Config5, LanWake } |
|
662 }; |
|
663 |
|
664 spin_lock_irq(&tp->lock); |
|
665 |
|
666 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
667 |
|
668 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
669 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
670 if (wol->wolopts & cfg[i].opt) |
|
671 options |= cfg[i].mask; |
|
672 RTL_W8(cfg[i].reg, options); |
|
673 } |
|
674 |
|
675 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
676 |
|
677 tp->wol_enabled = (wol->wolopts) ? 1 : 0; |
|
678 |
|
679 spin_unlock_irq(&tp->lock); |
|
680 |
|
681 return 0; |
|
682 } |
|
683 |
|
684 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
685 struct ethtool_drvinfo *info) |
|
686 { |
|
687 struct rtl8169_private *tp = netdev_priv(dev); |
|
688 |
|
689 strcpy(info->driver, MODULENAME); |
|
690 strcpy(info->version, RTL8169_VERSION); |
|
691 strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
692 } |
|
693 |
|
694 static int rtl8169_get_regs_len(struct net_device *dev) |
|
695 { |
|
696 return R8169_REGS_SIZE; |
|
697 } |
|
698 |
|
699 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
700 u8 autoneg, u16 speed, u8 duplex) |
|
701 { |
|
702 struct rtl8169_private *tp = netdev_priv(dev); |
|
703 void __iomem *ioaddr = tp->mmio_addr; |
|
704 int ret = 0; |
|
705 u32 reg; |
|
706 |
|
707 reg = RTL_R32(TBICSR); |
|
708 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
709 (duplex == DUPLEX_FULL)) { |
|
710 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
711 } else if (autoneg == AUTONEG_ENABLE) |
|
712 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
713 else { |
|
714 if (netif_msg_link(tp)) { |
|
715 printk(KERN_WARNING "%s: " |
|
716 "incorrect speed setting refused in TBI mode\n", |
|
717 dev->name); |
|
718 } |
|
719 ret = -EOPNOTSUPP; |
|
720 } |
|
721 |
|
722 return ret; |
|
723 } |
|
724 |
|
725 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
726 u8 autoneg, u16 speed, u8 duplex) |
|
727 { |
|
728 struct rtl8169_private *tp = netdev_priv(dev); |
|
729 void __iomem *ioaddr = tp->mmio_addr; |
|
730 int auto_nego, giga_ctrl; |
|
731 |
|
732 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
733 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
734 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
735 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
736 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
737 |
|
738 if (autoneg == AUTONEG_ENABLE) { |
|
739 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
740 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
741 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
742 } else { |
|
743 if (speed == SPEED_10) |
|
744 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
|
745 else if (speed == SPEED_100) |
|
746 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
|
747 else if (speed == SPEED_1000) |
|
748 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
749 |
|
750 if (duplex == DUPLEX_HALF) |
|
751 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
|
752 |
|
753 if (duplex == DUPLEX_FULL) |
|
754 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
|
755 |
|
756 /* This tweak comes straight from Realtek's driver. */ |
|
757 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && |
|
758 (tp->mac_version == RTL_GIGA_MAC_VER_13)) { |
|
759 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
|
760 } |
|
761 } |
|
762 |
|
763 /* The 8100e/8101e do Fast Ethernet only. */ |
|
764 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
765 (tp->mac_version == RTL_GIGA_MAC_VER_14) || |
|
766 (tp->mac_version == RTL_GIGA_MAC_VER_15)) { |
|
767 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
|
768 netif_msg_link(tp)) { |
|
769 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
|
770 dev->name); |
|
771 } |
|
772 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
773 } |
|
774 |
|
775 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
776 |
|
777 if (tp->mac_version == RTL_GIGA_MAC_VER_12) { |
|
778 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */ |
|
779 mdio_write(ioaddr, 0x1f, 0x0000); |
|
780 mdio_write(ioaddr, 0x0e, 0x0000); |
|
781 } |
|
782 |
|
783 tp->phy_auto_nego_reg = auto_nego; |
|
784 tp->phy_1000_ctrl_reg = giga_ctrl; |
|
785 |
|
786 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
787 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
788 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); |
|
789 return 0; |
|
790 } |
|
791 |
|
792 static int rtl8169_set_speed(struct net_device *dev, |
|
793 u8 autoneg, u16 speed, u8 duplex) |
|
794 { |
|
795 struct rtl8169_private *tp = netdev_priv(dev); |
|
796 int ret; |
|
797 |
|
798 ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
799 |
|
800 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
801 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
802 |
|
803 return ret; |
|
804 } |
|
805 |
|
806 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
807 { |
|
808 struct rtl8169_private *tp = netdev_priv(dev); |
|
809 unsigned long flags; |
|
810 int ret; |
|
811 |
|
812 spin_lock_irqsave(&tp->lock, flags); |
|
813 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
814 spin_unlock_irqrestore(&tp->lock, flags); |
|
815 |
|
816 return ret; |
|
817 } |
|
818 |
|
819 static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
820 { |
|
821 struct rtl8169_private *tp = netdev_priv(dev); |
|
822 |
|
823 return tp->cp_cmd & RxChkSum; |
|
824 } |
|
825 |
|
826 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
827 { |
|
828 struct rtl8169_private *tp = netdev_priv(dev); |
|
829 void __iomem *ioaddr = tp->mmio_addr; |
|
830 unsigned long flags; |
|
831 |
|
832 spin_lock_irqsave(&tp->lock, flags); |
|
833 |
|
834 if (data) |
|
835 tp->cp_cmd |= RxChkSum; |
|
836 else |
|
837 tp->cp_cmd &= ~RxChkSum; |
|
838 |
|
839 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
840 RTL_R16(CPlusCmd); |
|
841 |
|
842 spin_unlock_irqrestore(&tp->lock, flags); |
|
843 |
|
844 return 0; |
|
845 } |
|
846 |
|
847 #ifdef CONFIG_R8169_VLAN |
|
848 |
|
849 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
850 struct sk_buff *skb) |
|
851 { |
|
852 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? |
|
853 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
854 } |
|
855 |
|
856 static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
857 struct vlan_group *grp) |
|
858 { |
|
859 struct rtl8169_private *tp = netdev_priv(dev); |
|
860 void __iomem *ioaddr = tp->mmio_addr; |
|
861 unsigned long flags; |
|
862 |
|
863 spin_lock_irqsave(&tp->lock, flags); |
|
864 tp->vlgrp = grp; |
|
865 if (tp->vlgrp) |
|
866 tp->cp_cmd |= RxVlan; |
|
867 else |
|
868 tp->cp_cmd &= ~RxVlan; |
|
869 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
870 RTL_R16(CPlusCmd); |
|
871 spin_unlock_irqrestore(&tp->lock, flags); |
|
872 } |
|
873 |
|
874 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
875 struct sk_buff *skb) |
|
876 { |
|
877 u32 opts2 = le32_to_cpu(desc->opts2); |
|
878 int ret; |
|
879 |
|
880 if (tp->vlgrp && (opts2 & RxVlanTag)) { |
|
881 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff)); |
|
882 ret = 0; |
|
883 } else |
|
884 ret = -1; |
|
885 desc->opts2 = 0; |
|
886 return ret; |
|
887 } |
|
888 |
|
889 #else /* !CONFIG_R8169_VLAN */ |
|
890 |
|
891 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
892 struct sk_buff *skb) |
|
893 { |
|
894 return 0; |
|
895 } |
|
896 |
|
897 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
898 struct sk_buff *skb) |
|
899 { |
|
900 return -1; |
|
901 } |
|
902 |
|
903 #endif |
|
904 |
|
905 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
906 { |
|
907 struct rtl8169_private *tp = netdev_priv(dev); |
|
908 void __iomem *ioaddr = tp->mmio_addr; |
|
909 u32 status; |
|
910 |
|
911 cmd->supported = |
|
912 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
913 cmd->port = PORT_FIBRE; |
|
914 cmd->transceiver = XCVR_INTERNAL; |
|
915 |
|
916 status = RTL_R32(TBICSR); |
|
917 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
918 cmd->autoneg = !!(status & TBINwEnable); |
|
919 |
|
920 cmd->speed = SPEED_1000; |
|
921 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
922 } |
|
923 |
|
924 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
925 { |
|
926 struct rtl8169_private *tp = netdev_priv(dev); |
|
927 void __iomem *ioaddr = tp->mmio_addr; |
|
928 u8 status; |
|
929 |
|
930 cmd->supported = SUPPORTED_10baseT_Half | |
|
931 SUPPORTED_10baseT_Full | |
|
932 SUPPORTED_100baseT_Half | |
|
933 SUPPORTED_100baseT_Full | |
|
934 SUPPORTED_1000baseT_Full | |
|
935 SUPPORTED_Autoneg | |
|
936 SUPPORTED_TP; |
|
937 |
|
938 cmd->autoneg = 1; |
|
939 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg; |
|
940 |
|
941 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) |
|
942 cmd->advertising |= ADVERTISED_10baseT_Half; |
|
943 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) |
|
944 cmd->advertising |= ADVERTISED_10baseT_Full; |
|
945 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF) |
|
946 cmd->advertising |= ADVERTISED_100baseT_Half; |
|
947 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL) |
|
948 cmd->advertising |= ADVERTISED_100baseT_Full; |
|
949 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) |
|
950 cmd->advertising |= ADVERTISED_1000baseT_Full; |
|
951 |
|
952 status = RTL_R8(PHYstatus); |
|
953 |
|
954 if (status & _1000bpsF) |
|
955 cmd->speed = SPEED_1000; |
|
956 else if (status & _100bps) |
|
957 cmd->speed = SPEED_100; |
|
958 else if (status & _10bps) |
|
959 cmd->speed = SPEED_10; |
|
960 |
|
961 if (status & TxFlowCtrl) |
|
962 cmd->advertising |= ADVERTISED_Asym_Pause; |
|
963 if (status & RxFlowCtrl) |
|
964 cmd->advertising |= ADVERTISED_Pause; |
|
965 |
|
966 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ? |
|
967 DUPLEX_FULL : DUPLEX_HALF; |
|
968 } |
|
969 |
|
970 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
971 { |
|
972 struct rtl8169_private *tp = netdev_priv(dev); |
|
973 unsigned long flags; |
|
974 |
|
975 spin_lock_irqsave(&tp->lock, flags); |
|
976 |
|
977 tp->get_settings(dev, cmd); |
|
978 |
|
979 spin_unlock_irqrestore(&tp->lock, flags); |
|
980 return 0; |
|
981 } |
|
982 |
|
983 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
984 void *p) |
|
985 { |
|
986 struct rtl8169_private *tp = netdev_priv(dev); |
|
987 unsigned long flags; |
|
988 |
|
989 if (regs->len > R8169_REGS_SIZE) |
|
990 regs->len = R8169_REGS_SIZE; |
|
991 |
|
992 spin_lock_irqsave(&tp->lock, flags); |
|
993 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
994 spin_unlock_irqrestore(&tp->lock, flags); |
|
995 } |
|
996 |
|
997 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
998 { |
|
999 struct rtl8169_private *tp = netdev_priv(dev); |
|
1000 |
|
1001 return tp->msg_enable; |
|
1002 } |
|
1003 |
|
1004 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1005 { |
|
1006 struct rtl8169_private *tp = netdev_priv(dev); |
|
1007 |
|
1008 tp->msg_enable = value; |
|
1009 } |
|
1010 |
|
1011 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1012 "tx_packets", |
|
1013 "rx_packets", |
|
1014 "tx_errors", |
|
1015 "rx_errors", |
|
1016 "rx_missed", |
|
1017 "align_errors", |
|
1018 "tx_single_collisions", |
|
1019 "tx_multi_collisions", |
|
1020 "unicast", |
|
1021 "broadcast", |
|
1022 "multicast", |
|
1023 "tx_aborted", |
|
1024 "tx_underrun", |
|
1025 }; |
|
1026 |
|
1027 struct rtl8169_counters { |
|
1028 u64 tx_packets; |
|
1029 u64 rx_packets; |
|
1030 u64 tx_errors; |
|
1031 u32 rx_errors; |
|
1032 u16 rx_missed; |
|
1033 u16 align_errors; |
|
1034 u32 tx_one_collision; |
|
1035 u32 tx_multi_collision; |
|
1036 u64 rx_unicast; |
|
1037 u64 rx_broadcast; |
|
1038 u32 rx_multicast; |
|
1039 u16 tx_aborted; |
|
1040 u16 tx_underun; |
|
1041 }; |
|
1042 |
|
1043 static int rtl8169_get_stats_count(struct net_device *dev) |
|
1044 { |
|
1045 return ARRAY_SIZE(rtl8169_gstrings); |
|
1046 } |
|
1047 |
|
1048 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1049 struct ethtool_stats *stats, u64 *data) |
|
1050 { |
|
1051 struct rtl8169_private *tp = netdev_priv(dev); |
|
1052 void __iomem *ioaddr = tp->mmio_addr; |
|
1053 struct rtl8169_counters *counters; |
|
1054 dma_addr_t paddr; |
|
1055 u32 cmd; |
|
1056 |
|
1057 ASSERT_RTNL(); |
|
1058 |
|
1059 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); |
|
1060 if (!counters) |
|
1061 return; |
|
1062 |
|
1063 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1064 cmd = (u64)paddr & DMA_32BIT_MASK; |
|
1065 RTL_W32(CounterAddrLow, cmd); |
|
1066 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1067 |
|
1068 while (RTL_R32(CounterAddrLow) & CounterDump) { |
|
1069 if (msleep_interruptible(1)) |
|
1070 break; |
|
1071 } |
|
1072 |
|
1073 RTL_W32(CounterAddrLow, 0); |
|
1074 RTL_W32(CounterAddrHigh, 0); |
|
1075 |
|
1076 data[0] = le64_to_cpu(counters->tx_packets); |
|
1077 data[1] = le64_to_cpu(counters->rx_packets); |
|
1078 data[2] = le64_to_cpu(counters->tx_errors); |
|
1079 data[3] = le32_to_cpu(counters->rx_errors); |
|
1080 data[4] = le16_to_cpu(counters->rx_missed); |
|
1081 data[5] = le16_to_cpu(counters->align_errors); |
|
1082 data[6] = le32_to_cpu(counters->tx_one_collision); |
|
1083 data[7] = le32_to_cpu(counters->tx_multi_collision); |
|
1084 data[8] = le64_to_cpu(counters->rx_unicast); |
|
1085 data[9] = le64_to_cpu(counters->rx_broadcast); |
|
1086 data[10] = le32_to_cpu(counters->rx_multicast); |
|
1087 data[11] = le16_to_cpu(counters->tx_aborted); |
|
1088 data[12] = le16_to_cpu(counters->tx_underun); |
|
1089 |
|
1090 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
|
1091 } |
|
1092 |
|
1093 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1094 { |
|
1095 switch(stringset) { |
|
1096 case ETH_SS_STATS: |
|
1097 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1098 break; |
|
1099 } |
|
1100 } |
|
1101 |
|
1102 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1103 .get_drvinfo = rtl8169_get_drvinfo, |
|
1104 .get_regs_len = rtl8169_get_regs_len, |
|
1105 .get_link = ethtool_op_get_link, |
|
1106 .get_settings = rtl8169_get_settings, |
|
1107 .set_settings = rtl8169_set_settings, |
|
1108 .get_msglevel = rtl8169_get_msglevel, |
|
1109 .set_msglevel = rtl8169_set_msglevel, |
|
1110 .get_rx_csum = rtl8169_get_rx_csum, |
|
1111 .set_rx_csum = rtl8169_set_rx_csum, |
|
1112 .get_tx_csum = ethtool_op_get_tx_csum, |
|
1113 .set_tx_csum = ethtool_op_set_tx_csum, |
|
1114 .get_sg = ethtool_op_get_sg, |
|
1115 .set_sg = ethtool_op_set_sg, |
|
1116 .get_tso = ethtool_op_get_tso, |
|
1117 .set_tso = ethtool_op_set_tso, |
|
1118 .get_regs = rtl8169_get_regs, |
|
1119 .get_wol = rtl8169_get_wol, |
|
1120 .set_wol = rtl8169_set_wol, |
|
1121 .get_strings = rtl8169_get_strings, |
|
1122 .get_stats_count = rtl8169_get_stats_count, |
|
1123 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1124 }; |
|
1125 |
|
1126 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
|
1127 int bitnum, int bitval) |
|
1128 { |
|
1129 int val; |
|
1130 |
|
1131 val = mdio_read(ioaddr, reg); |
|
1132 val = (bitval == 1) ? |
|
1133 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); |
|
1134 mdio_write(ioaddr, reg, val & 0xffff); |
|
1135 } |
|
1136 |
|
1137 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1138 void __iomem *ioaddr) |
|
1139 { |
|
1140 /* |
|
1141 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1142 * but they can be identified more specifically through the test below |
|
1143 * if needed: |
|
1144 * |
|
1145 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1146 * |
|
1147 * Same thing for the 8101Eb and the 8101Ec: |
|
1148 * |
|
1149 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1150 */ |
|
1151 const struct { |
|
1152 u32 mask; |
|
1153 int mac_version; |
|
1154 } mac_info[] = { |
|
1155 { 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1156 { 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1157 { 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1158 { 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1159 { 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1160 { 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1161 { 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1162 { 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1163 { 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1164 { 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1165 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ |
|
1166 }, *p = mac_info; |
|
1167 u32 reg; |
|
1168 |
|
1169 reg = RTL_R32(TxConfig) & 0xfc800000; |
|
1170 while ((reg & p->mask) != p->mask) |
|
1171 p++; |
|
1172 tp->mac_version = p->mac_version; |
|
1173 } |
|
1174 |
|
1175 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1176 { |
|
1177 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1178 } |
|
1179 |
|
1180 static void rtl8169_get_phy_version(struct rtl8169_private *tp, |
|
1181 void __iomem *ioaddr) |
|
1182 { |
|
1183 const struct { |
|
1184 u16 mask; |
|
1185 u16 set; |
|
1186 int phy_version; |
|
1187 } phy_info[] = { |
|
1188 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G }, |
|
1189 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F }, |
|
1190 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E }, |
|
1191 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */ |
|
1192 }, *p = phy_info; |
|
1193 u16 reg; |
|
1194 |
|
1195 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff; |
|
1196 while ((reg & p->mask) != p->set) |
|
1197 p++; |
|
1198 tp->phy_version = p->phy_version; |
|
1199 } |
|
1200 |
|
1201 static void rtl8169_print_phy_version(struct rtl8169_private *tp) |
|
1202 { |
|
1203 struct { |
|
1204 int version; |
|
1205 char *msg; |
|
1206 u32 reg; |
|
1207 } phy_print[] = { |
|
1208 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 }, |
|
1209 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 }, |
|
1210 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 }, |
|
1211 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 }, |
|
1212 { 0, NULL, 0x0000 } |
|
1213 }, *p; |
|
1214 |
|
1215 for (p = phy_print; p->msg; p++) { |
|
1216 if (tp->phy_version == p->version) { |
|
1217 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg); |
|
1218 return; |
|
1219 } |
|
1220 } |
|
1221 dprintk("phy_version == Unknown\n"); |
|
1222 } |
|
1223 |
|
1224 static void rtl8169_hw_phy_config(struct net_device *dev) |
|
1225 { |
|
1226 struct rtl8169_private *tp = netdev_priv(dev); |
|
1227 void __iomem *ioaddr = tp->mmio_addr; |
|
1228 struct { |
|
1229 u16 regs[5]; /* Beware of bit-sign propagation */ |
|
1230 } phy_magic[5] = { { |
|
1231 { 0x0000, //w 4 15 12 0 |
|
1232 0x00a1, //w 3 15 0 00a1 |
|
1233 0x0008, //w 2 15 0 0008 |
|
1234 0x1020, //w 1 15 0 1020 |
|
1235 0x1000 } },{ //w 0 15 0 1000 |
|
1236 { 0x7000, //w 4 15 12 7 |
|
1237 0xff41, //w 3 15 0 ff41 |
|
1238 0xde60, //w 2 15 0 de60 |
|
1239 0x0140, //w 1 15 0 0140 |
|
1240 0x0077 } },{ //w 0 15 0 0077 |
|
1241 { 0xa000, //w 4 15 12 a |
|
1242 0xdf01, //w 3 15 0 df01 |
|
1243 0xdf20, //w 2 15 0 df20 |
|
1244 0xff95, //w 1 15 0 ff95 |
|
1245 0xfa00 } },{ //w 0 15 0 fa00 |
|
1246 { 0xb000, //w 4 15 12 b |
|
1247 0xff41, //w 3 15 0 ff41 |
|
1248 0xde20, //w 2 15 0 de20 |
|
1249 0x0140, //w 1 15 0 0140 |
|
1250 0x00bb } },{ //w 0 15 0 00bb |
|
1251 { 0xf000, //w 4 15 12 f |
|
1252 0xdf01, //w 3 15 0 df01 |
|
1253 0xdf20, //w 2 15 0 df20 |
|
1254 0xff95, //w 1 15 0 ff95 |
|
1255 0xbf00 } //w 0 15 0 bf00 |
|
1256 } |
|
1257 }, *p = phy_magic; |
|
1258 unsigned int i; |
|
1259 |
|
1260 rtl8169_print_mac_version(tp); |
|
1261 rtl8169_print_phy_version(tp); |
|
1262 |
|
1263 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
1264 return; |
|
1265 if (tp->phy_version >= RTL_GIGA_PHY_VER_H) |
|
1266 return; |
|
1267 |
|
1268 dprintk("MAC version != 0 && PHY version == 0 or 1\n"); |
|
1269 dprintk("Do final_reg2.cfg\n"); |
|
1270 |
|
1271 /* Shazam ! */ |
|
1272 |
|
1273 if (tp->mac_version == RTL_GIGA_MAC_VER_04) { |
|
1274 mdio_write(ioaddr, 31, 0x0002); |
|
1275 mdio_write(ioaddr, 1, 0x90d0); |
|
1276 mdio_write(ioaddr, 31, 0x0000); |
|
1277 return; |
|
1278 } |
|
1279 |
|
1280 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
1281 (tp->mac_version != RTL_GIGA_MAC_VER_03)) |
|
1282 return; |
|
1283 |
|
1284 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1 |
|
1285 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000 |
|
1286 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7 |
|
1287 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1288 |
|
1289 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { |
|
1290 int val, pos = 4; |
|
1291 |
|
1292 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); |
|
1293 mdio_write(ioaddr, pos, val); |
|
1294 while (--pos >= 0) |
|
1295 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); |
|
1296 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 |
|
1297 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
|
1298 } |
|
1299 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0 |
|
1300 } |
|
1301 |
|
1302 static void rtl8169_phy_timer(unsigned long __opaque) |
|
1303 { |
|
1304 struct net_device *dev = (struct net_device *)__opaque; |
|
1305 struct rtl8169_private *tp = netdev_priv(dev); |
|
1306 struct timer_list *timer = &tp->timer; |
|
1307 void __iomem *ioaddr = tp->mmio_addr; |
|
1308 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
1309 |
|
1310 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
1311 assert(tp->phy_version < RTL_GIGA_PHY_VER_H); |
|
1312 |
|
1313 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
1314 return; |
|
1315 |
|
1316 spin_lock_irq(&tp->lock); |
|
1317 |
|
1318 if (tp->phy_reset_pending(ioaddr)) { |
|
1319 /* |
|
1320 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
1321 * Let's delay the execution of the timer for a few ticks. |
|
1322 */ |
|
1323 timeout = HZ/10; |
|
1324 goto out_mod_timer; |
|
1325 } |
|
1326 |
|
1327 if (tp->link_ok(ioaddr)) |
|
1328 goto out_unlock; |
|
1329 |
|
1330 if (netif_msg_link(tp)) |
|
1331 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); |
|
1332 |
|
1333 tp->phy_reset_enable(ioaddr); |
|
1334 |
|
1335 out_mod_timer: |
|
1336 mod_timer(timer, jiffies + timeout); |
|
1337 out_unlock: |
|
1338 spin_unlock_irq(&tp->lock); |
|
1339 } |
|
1340 |
|
1341 static inline void rtl8169_delete_timer(struct net_device *dev) |
|
1342 { |
|
1343 struct rtl8169_private *tp = netdev_priv(dev); |
|
1344 struct timer_list *timer = &tp->timer; |
|
1345 |
|
1346 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || |
|
1347 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
|
1348 return; |
|
1349 |
|
1350 del_timer_sync(timer); |
|
1351 } |
|
1352 |
|
1353 static inline void rtl8169_request_timer(struct net_device *dev) |
|
1354 { |
|
1355 struct rtl8169_private *tp = netdev_priv(dev); |
|
1356 struct timer_list *timer = &tp->timer; |
|
1357 |
|
1358 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || |
|
1359 (tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
|
1360 return; |
|
1361 |
|
1362 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1363 } |
|
1364 |
|
1365 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
1366 /* |
|
1367 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
1368 * without having to re-enable interrupts. It's not called while |
|
1369 * the interrupt routine is executing. |
|
1370 */ |
|
1371 static void rtl8169_netpoll(struct net_device *dev) |
|
1372 { |
|
1373 struct rtl8169_private *tp = netdev_priv(dev); |
|
1374 struct pci_dev *pdev = tp->pci_dev; |
|
1375 |
|
1376 disable_irq(pdev->irq); |
|
1377 rtl8169_interrupt(pdev->irq, dev); |
|
1378 enable_irq(pdev->irq); |
|
1379 } |
|
1380 #endif |
|
1381 |
|
1382 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
1383 void __iomem *ioaddr) |
|
1384 { |
|
1385 iounmap(ioaddr); |
|
1386 pci_release_regions(pdev); |
|
1387 pci_disable_device(pdev); |
|
1388 free_netdev(dev); |
|
1389 } |
|
1390 |
|
1391 static void rtl8169_phy_reset(struct net_device *dev, |
|
1392 struct rtl8169_private *tp) |
|
1393 { |
|
1394 void __iomem *ioaddr = tp->mmio_addr; |
|
1395 unsigned int i; |
|
1396 |
|
1397 tp->phy_reset_enable(ioaddr); |
|
1398 for (i = 0; i < 100; i++) { |
|
1399 if (!tp->phy_reset_pending(ioaddr)) |
|
1400 return; |
|
1401 msleep(1); |
|
1402 } |
|
1403 if (netif_msg_link(tp)) |
|
1404 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); |
|
1405 } |
|
1406 |
|
1407 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
1408 { |
|
1409 void __iomem *ioaddr = tp->mmio_addr; |
|
1410 |
|
1411 rtl8169_hw_phy_config(dev); |
|
1412 |
|
1413 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1414 RTL_W8(0x82, 0x01); |
|
1415 |
|
1416 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
1417 |
|
1418 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
1419 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
1420 |
|
1421 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
1422 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
1423 RTL_W8(0x82, 0x01); |
|
1424 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
1425 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
1426 } |
|
1427 |
|
1428 rtl8169_phy_reset(dev, tp); |
|
1429 |
|
1430 /* |
|
1431 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
1432 * only 8101. Don't panic. |
|
1433 */ |
|
1434 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
1435 |
|
1436 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) |
|
1437 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); |
|
1438 } |
|
1439 |
|
1440 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
1441 { |
|
1442 void __iomem *ioaddr = tp->mmio_addr; |
|
1443 u32 high; |
|
1444 u32 low; |
|
1445 |
|
1446 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
1447 high = addr[4] | (addr[5] << 8); |
|
1448 |
|
1449 spin_lock_irq(&tp->lock); |
|
1450 |
|
1451 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1452 RTL_W32(MAC0, low); |
|
1453 RTL_W32(MAC4, high); |
|
1454 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1455 |
|
1456 spin_unlock_irq(&tp->lock); |
|
1457 } |
|
1458 |
|
1459 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
1460 { |
|
1461 struct rtl8169_private *tp = netdev_priv(dev); |
|
1462 struct sockaddr *addr = p; |
|
1463 |
|
1464 if (!is_valid_ether_addr(addr->sa_data)) |
|
1465 return -EADDRNOTAVAIL; |
|
1466 |
|
1467 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
1468 |
|
1469 rtl_rar_set(tp, dev->dev_addr); |
|
1470 |
|
1471 return 0; |
|
1472 } |
|
1473 |
|
1474 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
1475 { |
|
1476 struct rtl8169_private *tp = netdev_priv(dev); |
|
1477 struct mii_ioctl_data *data = if_mii(ifr); |
|
1478 |
|
1479 if (!netif_running(dev)) |
|
1480 return -ENODEV; |
|
1481 |
|
1482 switch (cmd) { |
|
1483 case SIOCGMIIPHY: |
|
1484 data->phy_id = 32; /* Internal PHY */ |
|
1485 return 0; |
|
1486 |
|
1487 case SIOCGMIIREG: |
|
1488 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
1489 return 0; |
|
1490 |
|
1491 case SIOCSMIIREG: |
|
1492 if (!capable(CAP_NET_ADMIN)) |
|
1493 return -EPERM; |
|
1494 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
1495 return 0; |
|
1496 } |
|
1497 return -EOPNOTSUPP; |
|
1498 } |
|
1499 |
|
1500 static const struct rtl_cfg_info { |
|
1501 void (*hw_start)(struct net_device *); |
|
1502 unsigned int region; |
|
1503 unsigned int align; |
|
1504 u16 intr_event; |
|
1505 u16 napi_event; |
|
1506 } rtl_cfg_infos [] = { |
|
1507 [RTL_CFG_0] = { |
|
1508 .hw_start = rtl_hw_start_8169, |
|
1509 .region = 1, |
|
1510 .align = 0, |
|
1511 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1512 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1513 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow |
|
1514 }, |
|
1515 [RTL_CFG_1] = { |
|
1516 .hw_start = rtl_hw_start_8168, |
|
1517 .region = 2, |
|
1518 .align = 8, |
|
1519 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
1520 TxErr | TxOK | RxOK | RxErr, |
|
1521 .napi_event = TxErr | TxOK | RxOK | RxOverflow |
|
1522 }, |
|
1523 [RTL_CFG_2] = { |
|
1524 .hw_start = rtl_hw_start_8101, |
|
1525 .region = 2, |
|
1526 .align = 8, |
|
1527 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
1528 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
1529 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow |
|
1530 } |
|
1531 }; |
|
1532 |
|
1533 static int __devinit |
|
1534 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
1535 { |
|
1536 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
1537 const unsigned int region = cfg->region; |
|
1538 struct rtl8169_private *tp; |
|
1539 struct net_device *dev; |
|
1540 void __iomem *ioaddr; |
|
1541 unsigned int i; |
|
1542 int rc; |
|
1543 |
|
1544 if (netif_msg_drv(&debug)) { |
|
1545 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
1546 MODULENAME, RTL8169_VERSION); |
|
1547 } |
|
1548 |
|
1549 dev = alloc_etherdev(sizeof (*tp)); |
|
1550 if (!dev) { |
|
1551 if (netif_msg_drv(&debug)) |
|
1552 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
1553 rc = -ENOMEM; |
|
1554 goto out; |
|
1555 } |
|
1556 |
|
1557 SET_MODULE_OWNER(dev); |
|
1558 SET_NETDEV_DEV(dev, &pdev->dev); |
|
1559 tp = netdev_priv(dev); |
|
1560 tp->dev = dev; |
|
1561 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
1562 |
|
1563 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
1564 rc = pci_enable_device(pdev); |
|
1565 if (rc < 0) { |
|
1566 if (netif_msg_probe(tp)) |
|
1567 dev_err(&pdev->dev, "enable failure\n"); |
|
1568 goto err_out_free_dev_1; |
|
1569 } |
|
1570 |
|
1571 rc = pci_set_mwi(pdev); |
|
1572 if (rc < 0) |
|
1573 goto err_out_disable_2; |
|
1574 |
|
1575 /* make sure PCI base addr 1 is MMIO */ |
|
1576 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
1577 if (netif_msg_probe(tp)) { |
|
1578 dev_err(&pdev->dev, |
|
1579 "region #%d not an MMIO resource, aborting\n", |
|
1580 region); |
|
1581 } |
|
1582 rc = -ENODEV; |
|
1583 goto err_out_mwi_3; |
|
1584 } |
|
1585 |
|
1586 /* check for weird/broken PCI region reporting */ |
|
1587 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
1588 if (netif_msg_probe(tp)) { |
|
1589 dev_err(&pdev->dev, |
|
1590 "Invalid PCI region size(s), aborting\n"); |
|
1591 } |
|
1592 rc = -ENODEV; |
|
1593 goto err_out_mwi_3; |
|
1594 } |
|
1595 |
|
1596 rc = pci_request_regions(pdev, MODULENAME); |
|
1597 if (rc < 0) { |
|
1598 if (netif_msg_probe(tp)) |
|
1599 dev_err(&pdev->dev, "could not request regions.\n"); |
|
1600 goto err_out_mwi_3; |
|
1601 } |
|
1602 |
|
1603 tp->cp_cmd = PCIMulRW | RxChkSum; |
|
1604 |
|
1605 if ((sizeof(dma_addr_t) > 4) && |
|
1606 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { |
|
1607 tp->cp_cmd |= PCIDAC; |
|
1608 dev->features |= NETIF_F_HIGHDMA; |
|
1609 } else { |
|
1610 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
|
1611 if (rc < 0) { |
|
1612 if (netif_msg_probe(tp)) { |
|
1613 dev_err(&pdev->dev, |
|
1614 "DMA configuration failed.\n"); |
|
1615 } |
|
1616 goto err_out_free_res_4; |
|
1617 } |
|
1618 } |
|
1619 |
|
1620 pci_set_master(pdev); |
|
1621 |
|
1622 /* ioremap MMIO region */ |
|
1623 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
1624 if (!ioaddr) { |
|
1625 if (netif_msg_probe(tp)) |
|
1626 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
1627 rc = -EIO; |
|
1628 goto err_out_free_res_4; |
|
1629 } |
|
1630 |
|
1631 /* Unneeded ? Don't mess with Mrs. Murphy. */ |
|
1632 rtl8169_irq_mask_and_ack(ioaddr); |
|
1633 |
|
1634 /* Soft reset the chip. */ |
|
1635 RTL_W8(ChipCmd, CmdReset); |
|
1636 |
|
1637 /* Check that the chip has finished the reset. */ |
|
1638 for (i = 0; i < 100; i++) { |
|
1639 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
1640 break; |
|
1641 msleep_interruptible(1); |
|
1642 } |
|
1643 |
|
1644 /* Identify chip attached to board */ |
|
1645 rtl8169_get_mac_version(tp, ioaddr); |
|
1646 rtl8169_get_phy_version(tp, ioaddr); |
|
1647 |
|
1648 rtl8169_print_mac_version(tp); |
|
1649 rtl8169_print_phy_version(tp); |
|
1650 |
|
1651 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { |
|
1652 if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
1653 break; |
|
1654 } |
|
1655 if (i < 0) { |
|
1656 /* Unknown chip: assume array element #0, original RTL-8169 */ |
|
1657 if (netif_msg_probe(tp)) { |
|
1658 dev_printk(KERN_DEBUG, &pdev->dev, |
|
1659 "unknown chip version, assuming %s\n", |
|
1660 rtl_chip_info[0].name); |
|
1661 } |
|
1662 i++; |
|
1663 } |
|
1664 tp->chipset = i; |
|
1665 |
|
1666 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1667 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
1668 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
1669 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1670 |
|
1671 if (RTL_R8(PHYstatus) & TBI_Enable) { |
|
1672 tp->set_speed = rtl8169_set_speed_tbi; |
|
1673 tp->get_settings = rtl8169_gset_tbi; |
|
1674 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
1675 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
1676 tp->link_ok = rtl8169_tbi_link_ok; |
|
1677 |
|
1678 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
1679 } else { |
|
1680 tp->set_speed = rtl8169_set_speed_xmii; |
|
1681 tp->get_settings = rtl8169_gset_xmii; |
|
1682 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
1683 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
1684 tp->link_ok = rtl8169_xmii_link_ok; |
|
1685 |
|
1686 dev->do_ioctl = rtl8169_ioctl; |
|
1687 } |
|
1688 |
|
1689 /* Get MAC address. FIXME: read EEPROM */ |
|
1690 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
1691 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
1692 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
1693 |
|
1694 dev->open = rtl8169_open; |
|
1695 dev->hard_start_xmit = rtl8169_start_xmit; |
|
1696 dev->get_stats = rtl8169_get_stats; |
|
1697 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
1698 dev->stop = rtl8169_close; |
|
1699 dev->tx_timeout = rtl8169_tx_timeout; |
|
1700 dev->set_multicast_list = rtl_set_rx_mode; |
|
1701 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
1702 dev->irq = pdev->irq; |
|
1703 dev->base_addr = (unsigned long) ioaddr; |
|
1704 dev->change_mtu = rtl8169_change_mtu; |
|
1705 dev->set_mac_address = rtl_set_mac_address; |
|
1706 |
|
1707 #ifdef CONFIG_R8169_NAPI |
|
1708 dev->poll = rtl8169_poll; |
|
1709 dev->weight = R8169_NAPI_WEIGHT; |
|
1710 #endif |
|
1711 |
|
1712 #ifdef CONFIG_R8169_VLAN |
|
1713 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
1714 dev->vlan_rx_register = rtl8169_vlan_rx_register; |
|
1715 #endif |
|
1716 |
|
1717 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
1718 dev->poll_controller = rtl8169_netpoll; |
|
1719 #endif |
|
1720 |
|
1721 tp->intr_mask = 0xffff; |
|
1722 tp->pci_dev = pdev; |
|
1723 tp->mmio_addr = ioaddr; |
|
1724 tp->align = cfg->align; |
|
1725 tp->hw_start = cfg->hw_start; |
|
1726 tp->intr_event = cfg->intr_event; |
|
1727 tp->napi_event = cfg->napi_event; |
|
1728 |
|
1729 init_timer(&tp->timer); |
|
1730 tp->timer.data = (unsigned long) dev; |
|
1731 tp->timer.function = rtl8169_phy_timer; |
|
1732 |
|
1733 spin_lock_init(&tp->lock); |
|
1734 |
|
1735 // offer device to EtherCAT master module |
|
1736 if (ecdev_offer(dev, ec_poll, THIS_MODULE, &tp->ecdev)) { |
|
1737 printk(KERN_ERR PFX "Failed to offer device.\n"); |
|
1738 goto err_out_unmap_5; |
|
1739 } |
|
1740 |
|
1741 if (!tp->ecdev) { |
|
1742 printk(KERN_INFO "about to register device named %s (%p)...\n", dev->name, dev); |
|
1743 i = register_netdev (dev); |
|
1744 if (i) goto err_out_unmap_5; |
|
1745 } |
|
1746 |
|
1747 pci_set_drvdata(pdev, dev); |
|
1748 |
|
1749 if (netif_msg_probe(tp)) { |
|
1750 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
|
1751 |
|
1752 printk(KERN_INFO "%s: %s at 0x%lx, " |
|
1753 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
|
1754 "XID %08x IRQ %d\n", |
|
1755 dev->name, |
|
1756 rtl_chip_info[tp->chipset].name, |
|
1757 dev->base_addr, |
|
1758 dev->dev_addr[0], dev->dev_addr[1], |
|
1759 dev->dev_addr[2], dev->dev_addr[3], |
|
1760 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
|
1761 } |
|
1762 |
|
1763 rtl8169_init_phy(dev, tp); |
|
1764 |
|
1765 if (tp->ecdev && ecdev_open(tp->ecdev)) { |
|
1766 ecdev_withdraw(tp->ecdev); |
|
1767 goto err_out_unmap_5; |
|
1768 } |
|
1769 |
|
1770 out: |
|
1771 return rc; |
|
1772 |
|
1773 err_out_unmap_5: |
|
1774 iounmap(ioaddr); |
|
1775 err_out_free_res_4: |
|
1776 pci_release_regions(pdev); |
|
1777 err_out_mwi_3: |
|
1778 pci_clear_mwi(pdev); |
|
1779 err_out_disable_2: |
|
1780 pci_disable_device(pdev); |
|
1781 err_out_free_dev_1: |
|
1782 free_netdev(dev); |
|
1783 goto out; |
|
1784 } |
|
1785 |
|
1786 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
1787 { |
|
1788 struct net_device *dev = pci_get_drvdata(pdev); |
|
1789 struct rtl8169_private *tp = netdev_priv(dev); |
|
1790 |
|
1791 flush_scheduled_work(); |
|
1792 |
|
1793 |
|
1794 if (tp->ecdev) { |
|
1795 ecdev_close(tp->ecdev); |
|
1796 ecdev_withdraw(tp->ecdev); |
|
1797 } |
|
1798 else { |
|
1799 unregister_netdev (dev); |
|
1800 } |
|
1801 |
|
1802 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
1803 pci_set_drvdata(pdev, NULL); |
|
1804 } |
|
1805 |
|
1806 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
|
1807 struct net_device *dev) |
|
1808 { |
|
1809 unsigned int mtu = dev->mtu; |
|
1810 |
|
1811 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; |
|
1812 } |
|
1813 |
|
1814 static int rtl8169_open(struct net_device *dev) |
|
1815 { |
|
1816 struct rtl8169_private *tp = netdev_priv(dev); |
|
1817 struct pci_dev *pdev = tp->pci_dev; |
|
1818 int retval = -ENOMEM; |
|
1819 |
|
1820 |
|
1821 rtl8169_set_rxbufsize(tp, dev); |
|
1822 |
|
1823 /* |
|
1824 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
1825 * pci_alloc_consistent provides more. |
|
1826 */ |
|
1827 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, |
|
1828 &tp->TxPhyAddr); |
|
1829 if (!tp->TxDescArray) |
|
1830 goto out; |
|
1831 |
|
1832 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, |
|
1833 &tp->RxPhyAddr); |
|
1834 if (!tp->RxDescArray) |
|
1835 goto err_free_tx_0; |
|
1836 |
|
1837 retval = rtl8169_init_ring(dev); |
|
1838 if (retval < 0) |
|
1839 goto err_free_rx_1; |
|
1840 |
|
1841 INIT_DELAYED_WORK(&tp->task, NULL); |
|
1842 |
|
1843 smp_mb(); |
|
1844 |
|
1845 if (!tp->ecdev) { |
|
1846 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED, |
|
1847 dev->name, dev); |
|
1848 if (retval < 0) |
|
1849 goto err_release_ring_2; |
|
1850 } |
|
1851 |
|
1852 rtl_hw_start(dev); |
|
1853 |
|
1854 rtl8169_request_timer(dev); |
|
1855 |
|
1856 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
1857 out: |
|
1858 return retval; |
|
1859 |
|
1860 err_release_ring_2: |
|
1861 rtl8169_rx_clear(tp); |
|
1862 err_free_rx_1: |
|
1863 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
1864 tp->RxPhyAddr); |
|
1865 err_free_tx_0: |
|
1866 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
1867 tp->TxPhyAddr); |
|
1868 goto out; |
|
1869 } |
|
1870 |
|
1871 static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
1872 { |
|
1873 /* Disable interrupts */ |
|
1874 rtl8169_irq_mask_and_ack(ioaddr); |
|
1875 |
|
1876 /* Reset the chipset */ |
|
1877 RTL_W8(ChipCmd, CmdReset); |
|
1878 |
|
1879 /* PCI commit */ |
|
1880 RTL_R8(ChipCmd); |
|
1881 } |
|
1882 |
|
1883 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
1884 { |
|
1885 void __iomem *ioaddr = tp->mmio_addr; |
|
1886 u32 cfg = rtl8169_rx_config; |
|
1887 |
|
1888 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
1889 RTL_W32(RxConfig, cfg); |
|
1890 |
|
1891 /* Set DMA burst size and Interframe Gap Time */ |
|
1892 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
1893 (InterFrameGap << TxInterFrameGapShift)); |
|
1894 } |
|
1895 |
|
1896 static void rtl_hw_start(struct net_device *dev) |
|
1897 { |
|
1898 struct rtl8169_private *tp = netdev_priv(dev); |
|
1899 void __iomem *ioaddr = tp->mmio_addr; |
|
1900 unsigned int i; |
|
1901 |
|
1902 /* Soft reset the chip. */ |
|
1903 RTL_W8(ChipCmd, CmdReset); |
|
1904 |
|
1905 /* Check that the chip has finished the reset. */ |
|
1906 for (i = 0; i < 100; i++) { |
|
1907 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
1908 break; |
|
1909 msleep_interruptible(1); |
|
1910 } |
|
1911 |
|
1912 tp->hw_start(dev); |
|
1913 |
|
1914 if(!tp->ecdev) { |
|
1915 netif_start_queue(dev); |
|
1916 } |
|
1917 } |
|
1918 |
|
1919 |
|
1920 void ec_poll(struct net_device *dev) |
|
1921 { |
|
1922 rtl8169_interrupt(0, dev); |
|
1923 } |
|
1924 |
|
1925 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
1926 void __iomem *ioaddr) |
|
1927 { |
|
1928 /* |
|
1929 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
1930 * register to be written before TxDescAddrLow to work. |
|
1931 * Switching from MMIO to I/O access fixes the issue as well. |
|
1932 */ |
|
1933 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
1934 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); |
|
1935 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
1936 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); |
|
1937 } |
|
1938 |
|
1939 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
1940 { |
|
1941 u16 cmd; |
|
1942 |
|
1943 cmd = RTL_R16(CPlusCmd); |
|
1944 RTL_W16(CPlusCmd, cmd); |
|
1945 return cmd; |
|
1946 } |
|
1947 |
|
1948 static void rtl_set_rx_max_size(void __iomem *ioaddr) |
|
1949 { |
|
1950 /* Low hurts. Let's disable the filtering. */ |
|
1951 RTL_W16(RxMaxSize, 16383); |
|
1952 } |
|
1953 |
|
1954 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
1955 { |
|
1956 struct { |
|
1957 u32 mac_version; |
|
1958 u32 clk; |
|
1959 u32 val; |
|
1960 } cfg2_info [] = { |
|
1961 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
1962 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
1963 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
1964 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
1965 }, *p = cfg2_info; |
|
1966 unsigned int i; |
|
1967 u32 clk; |
|
1968 |
|
1969 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
1970 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) { |
|
1971 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
1972 RTL_W32(0x7c, p->val); |
|
1973 break; |
|
1974 } |
|
1975 } |
|
1976 } |
|
1977 |
|
1978 static void rtl_hw_start_8169(struct net_device *dev) |
|
1979 { |
|
1980 struct rtl8169_private *tp = netdev_priv(dev); |
|
1981 void __iomem *ioaddr = tp->mmio_addr; |
|
1982 struct pci_dev *pdev = tp->pci_dev; |
|
1983 |
|
1984 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
1985 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
1986 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
1987 } |
|
1988 |
|
1989 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1990 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
1991 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
1992 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
1993 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
1994 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
1995 |
|
1996 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
1997 |
|
1998 rtl_set_rx_max_size(ioaddr); |
|
1999 |
|
2000 rtl_set_rx_tx_config_registers(tp); |
|
2001 |
|
2002 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2003 |
|
2004 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
2005 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
2006 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. " |
|
2007 "Bit-3 and bit-14 MUST be 1\n"); |
|
2008 tp->cp_cmd |= (1 << 14); |
|
2009 } |
|
2010 |
|
2011 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2012 |
|
2013 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
2014 |
|
2015 /* |
|
2016 * Undocumented corner. Supposedly: |
|
2017 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
2018 */ |
|
2019 RTL_W16(IntrMitigate, 0x0000); |
|
2020 |
|
2021 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2022 |
|
2023 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2024 |
|
2025 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
2026 RTL_R8(IntrMask); |
|
2027 |
|
2028 RTL_W32(RxMissed, 0); |
|
2029 |
|
2030 rtl_set_rx_mode(dev); |
|
2031 |
|
2032 /* no early-rx interrupts */ |
|
2033 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2034 |
|
2035 /* Enable all known interrupts by setting the interrupt mask. */ |
|
2036 if(!tp->ecdev) { |
|
2037 RTL_W16(IntrMask, tp->intr_event); |
|
2038 } |
|
2039 |
|
2040 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2041 } |
|
2042 |
|
2043 static void rtl_hw_start_8168(struct net_device *dev) |
|
2044 { |
|
2045 struct rtl8169_private *tp = netdev_priv(dev); |
|
2046 void __iomem *ioaddr = tp->mmio_addr; |
|
2047 struct pci_dev *pdev = tp->pci_dev; |
|
2048 u8 ctl; |
|
2049 |
|
2050 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2051 |
|
2052 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2053 |
|
2054 rtl_set_rx_max_size(ioaddr); |
|
2055 |
|
2056 rtl_set_rx_tx_config_registers(tp); |
|
2057 |
|
2058 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
2059 |
|
2060 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2061 |
|
2062 /* Tx performance tweak. */ |
|
2063 pci_read_config_byte(pdev, 0x69, &ctl); |
|
2064 ctl = (ctl & ~0x70) | 0x50; |
|
2065 pci_write_config_byte(pdev, 0x69, ctl); |
|
2066 |
|
2067 RTL_W16(IntrMitigate, 0x5151); |
|
2068 |
|
2069 /* Work around for RxFIFO overflow. */ |
|
2070 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
2071 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
2072 tp->intr_event &= ~RxOverflow; |
|
2073 } |
|
2074 |
|
2075 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2076 |
|
2077 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2078 |
|
2079 RTL_R8(IntrMask); |
|
2080 |
|
2081 RTL_W32(RxMissed, 0); |
|
2082 |
|
2083 rtl_set_rx_mode(dev); |
|
2084 |
|
2085 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2086 |
|
2087 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
2088 |
|
2089 if(!tp->ecdev) { |
|
2090 RTL_W16(IntrMask, tp->intr_event); |
|
2091 } |
|
2092 } |
|
2093 |
|
2094 static void rtl_hw_start_8101(struct net_device *dev) |
|
2095 { |
|
2096 struct rtl8169_private *tp = netdev_priv(dev); |
|
2097 void __iomem *ioaddr = tp->mmio_addr; |
|
2098 struct pci_dev *pdev = tp->pci_dev; |
|
2099 |
|
2100 if (tp->mac_version == RTL_GIGA_MAC_VER_13) { |
|
2101 pci_write_config_word(pdev, 0x68, 0x00); |
|
2102 pci_write_config_word(pdev, 0x69, 0x08); |
|
2103 } |
|
2104 |
|
2105 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2106 |
|
2107 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
2108 |
|
2109 rtl_set_rx_max_size(ioaddr); |
|
2110 |
|
2111 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
2112 |
|
2113 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2114 |
|
2115 RTL_W16(IntrMitigate, 0x0000); |
|
2116 |
|
2117 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
2118 |
|
2119 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2120 rtl_set_rx_tx_config_registers(tp); |
|
2121 |
|
2122 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2123 |
|
2124 RTL_R8(IntrMask); |
|
2125 |
|
2126 RTL_W32(RxMissed, 0); |
|
2127 |
|
2128 rtl_set_rx_mode(dev); |
|
2129 |
|
2130 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
2131 |
|
2132 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
2133 |
|
2134 if(!tp->ecdev) { |
|
2135 RTL_W16(IntrMask, tp->intr_event); |
|
2136 } |
|
2137 } |
|
2138 |
|
2139 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
2140 { |
|
2141 struct rtl8169_private *tp = netdev_priv(dev); |
|
2142 int ret = 0; |
|
2143 |
|
2144 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
2145 return -EINVAL; |
|
2146 |
|
2147 dev->mtu = new_mtu; |
|
2148 |
|
2149 if (!netif_running(dev)) |
|
2150 goto out; |
|
2151 |
|
2152 rtl8169_down(dev); |
|
2153 |
|
2154 rtl8169_set_rxbufsize(tp, dev); |
|
2155 |
|
2156 ret = rtl8169_init_ring(dev); |
|
2157 if (ret < 0) |
|
2158 goto out; |
|
2159 |
|
2160 netif_poll_enable(dev); |
|
2161 |
|
2162 rtl_hw_start(dev); |
|
2163 |
|
2164 rtl8169_request_timer(dev); |
|
2165 |
|
2166 out: |
|
2167 return ret; |
|
2168 } |
|
2169 |
|
2170 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
2171 { |
|
2172 desc->addr = 0x0badbadbadbadbadull; |
|
2173 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
2174 } |
|
2175 |
|
2176 static void rtl8169_free_rx_skb(struct rtl8169_private *tp, |
|
2177 struct sk_buff **sk_buff, struct RxDesc *desc) |
|
2178 { |
|
2179 struct pci_dev *pdev = tp->pci_dev; |
|
2180 |
|
2181 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, |
|
2182 PCI_DMA_FROMDEVICE); |
|
2183 if(!tp->ecdev) { |
|
2184 dev_kfree_skb(*sk_buff); |
|
2185 *sk_buff = NULL; |
|
2186 } |
|
2187 rtl8169_make_unusable_by_asic(desc); |
|
2188 } |
|
2189 |
|
2190 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
2191 { |
|
2192 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
2193 |
|
2194 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
2195 } |
|
2196 |
|
2197 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
2198 u32 rx_buf_sz) |
|
2199 { |
|
2200 desc->addr = cpu_to_le64(mapping); |
|
2201 wmb(); |
|
2202 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
2203 } |
|
2204 |
|
2205 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
|
2206 struct net_device *dev, |
|
2207 struct RxDesc *desc, int rx_buf_sz, |
|
2208 unsigned int align) |
|
2209 { |
|
2210 struct sk_buff *skb; |
|
2211 dma_addr_t mapping; |
|
2212 unsigned int pad; |
|
2213 |
|
2214 pad = align ? align : NET_IP_ALIGN; |
|
2215 |
|
2216 skb = netdev_alloc_skb(dev, rx_buf_sz + pad); |
|
2217 if (!skb) |
|
2218 goto err_out; |
|
2219 |
|
2220 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
|
2221 |
|
2222 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
2223 PCI_DMA_FROMDEVICE); |
|
2224 |
|
2225 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
2226 out: |
|
2227 return skb; |
|
2228 |
|
2229 err_out: |
|
2230 rtl8169_make_unusable_by_asic(desc); |
|
2231 goto out; |
|
2232 } |
|
2233 |
|
2234 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
2235 { |
|
2236 unsigned int i; |
|
2237 |
|
2238 for (i = 0; i < NUM_RX_DESC; i++) { |
|
2239 if (tp->Rx_skbuff[i]) { |
|
2240 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, |
|
2241 tp->RxDescArray + i); |
|
2242 } |
|
2243 } |
|
2244 } |
|
2245 |
|
2246 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, |
|
2247 u32 start, u32 end) |
|
2248 { |
|
2249 u32 cur; |
|
2250 |
|
2251 for (cur = start; end - cur != 0; cur++) { |
|
2252 struct sk_buff *skb; |
|
2253 unsigned int i = cur % NUM_RX_DESC; |
|
2254 |
|
2255 WARN_ON((s32)(end - cur) < 0); |
|
2256 |
|
2257 if (tp->Rx_skbuff[i]) |
|
2258 continue; |
|
2259 |
|
2260 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
|
2261 tp->RxDescArray + i, |
|
2262 tp->rx_buf_sz, tp->align); |
|
2263 if (!skb) |
|
2264 break; |
|
2265 |
|
2266 tp->Rx_skbuff[i] = skb; |
|
2267 } |
|
2268 return cur - start; |
|
2269 } |
|
2270 |
|
2271 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
2272 { |
|
2273 desc->opts1 |= cpu_to_le32(RingEnd); |
|
2274 } |
|
2275 |
|
2276 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
2277 { |
|
2278 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
2279 } |
|
2280 |
|
2281 static int rtl8169_init_ring(struct net_device *dev) |
|
2282 { |
|
2283 struct rtl8169_private *tp = netdev_priv(dev); |
|
2284 |
|
2285 rtl8169_init_ring_indexes(tp); |
|
2286 |
|
2287 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
2288 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); |
|
2289 |
|
2290 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) |
|
2291 goto err_out; |
|
2292 |
|
2293 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
2294 |
|
2295 return 0; |
|
2296 |
|
2297 err_out: |
|
2298 rtl8169_rx_clear(tp); |
|
2299 return -ENOMEM; |
|
2300 } |
|
2301 |
|
2302 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, |
|
2303 struct TxDesc *desc) |
|
2304 { |
|
2305 unsigned int len = tx_skb->len; |
|
2306 |
|
2307 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); |
|
2308 desc->opts1 = 0x00; |
|
2309 desc->opts2 = 0x00; |
|
2310 desc->addr = 0x00; |
|
2311 tx_skb->len = 0; |
|
2312 } |
|
2313 |
|
2314 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
2315 { |
|
2316 unsigned int i; |
|
2317 |
|
2318 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { |
|
2319 unsigned int entry = i % NUM_TX_DESC; |
|
2320 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
2321 unsigned int len = tx_skb->len; |
|
2322 |
|
2323 if (len) { |
|
2324 struct sk_buff *skb = tx_skb->skb; |
|
2325 |
|
2326 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, |
|
2327 tp->TxDescArray + entry); |
|
2328 if (skb) { |
|
2329 if(!tp->ecdev) { |
|
2330 dev_kfree_skb(skb); |
|
2331 tx_skb->skb = NULL; |
|
2332 } |
|
2333 } |
|
2334 tp->stats.tx_dropped++; |
|
2335 } |
|
2336 } |
|
2337 tp->cur_tx = tp->dirty_tx = 0; |
|
2338 } |
|
2339 |
|
2340 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
2341 { |
|
2342 struct rtl8169_private *tp = netdev_priv(dev); |
|
2343 |
|
2344 PREPARE_DELAYED_WORK(&tp->task, task); |
|
2345 schedule_delayed_work(&tp->task, 4); |
|
2346 } |
|
2347 |
|
2348 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
2349 { |
|
2350 struct rtl8169_private *tp = netdev_priv(dev); |
|
2351 void __iomem *ioaddr = tp->mmio_addr; |
|
2352 |
|
2353 synchronize_irq(dev->irq); |
|
2354 |
|
2355 /* Wait for any pending NAPI task to complete */ |
|
2356 netif_poll_disable(dev); |
|
2357 |
|
2358 rtl8169_irq_mask_and_ack(ioaddr); |
|
2359 |
|
2360 netif_poll_enable(dev); |
|
2361 } |
|
2362 |
|
2363 static void rtl8169_reinit_task(struct work_struct *work) |
|
2364 { |
|
2365 struct rtl8169_private *tp = |
|
2366 container_of(work, struct rtl8169_private, task.work); |
|
2367 struct net_device *dev = tp->dev; |
|
2368 int ret; |
|
2369 |
|
2370 rtnl_lock(); |
|
2371 |
|
2372 if (!netif_running(dev)) |
|
2373 goto out_unlock; |
|
2374 |
|
2375 rtl8169_wait_for_quiescence(dev); |
|
2376 rtl8169_close(dev); |
|
2377 |
|
2378 ret = rtl8169_open(dev); |
|
2379 if (unlikely(ret < 0)) { |
|
2380 if (net_ratelimit() && netif_msg_drv(tp)) { |
|
2381 printk(PFX KERN_ERR "%s: reinit failure (status = %d)." |
|
2382 " Rescheduling.\n", dev->name, ret); |
|
2383 } |
|
2384 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2385 } |
|
2386 |
|
2387 out_unlock: |
|
2388 rtnl_unlock(); |
|
2389 } |
|
2390 |
|
2391 static void rtl8169_reset_task(struct work_struct *work) |
|
2392 { |
|
2393 struct rtl8169_private *tp = |
|
2394 container_of(work, struct rtl8169_private, task.work); |
|
2395 struct net_device *dev = tp->dev; |
|
2396 |
|
2397 rtnl_lock(); |
|
2398 |
|
2399 if (!netif_running(dev)) |
|
2400 goto out_unlock; |
|
2401 |
|
2402 rtl8169_wait_for_quiescence(dev); |
|
2403 |
|
2404 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr); |
|
2405 rtl8169_tx_clear(tp); |
|
2406 |
|
2407 if (tp->dirty_rx == tp->cur_rx) { |
|
2408 rtl8169_init_ring_indexes(tp); |
|
2409 rtl_hw_start(dev); |
|
2410 netif_wake_queue(dev); |
|
2411 } else { |
|
2412 if (net_ratelimit() && netif_msg_intr(tp)) { |
|
2413 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n", |
|
2414 dev->name); |
|
2415 } |
|
2416 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2417 } |
|
2418 |
|
2419 out_unlock: |
|
2420 rtnl_unlock(); |
|
2421 } |
|
2422 |
|
2423 static void rtl8169_tx_timeout(struct net_device *dev) |
|
2424 { |
|
2425 struct rtl8169_private *tp = netdev_priv(dev); |
|
2426 |
|
2427 rtl8169_hw_reset(tp->mmio_addr); |
|
2428 |
|
2429 /* Let's wait a bit while any (async) irq lands on */ |
|
2430 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2431 } |
|
2432 |
|
2433 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
2434 u32 opts1) |
|
2435 { |
|
2436 struct skb_shared_info *info = skb_shinfo(skb); |
|
2437 unsigned int cur_frag, entry; |
|
2438 struct TxDesc * uninitialized_var(txd); |
|
2439 |
|
2440 entry = tp->cur_tx; |
|
2441 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
2442 skb_frag_t *frag = info->frags + cur_frag; |
|
2443 dma_addr_t mapping; |
|
2444 u32 status, len; |
|
2445 void *addr; |
|
2446 |
|
2447 entry = (entry + 1) % NUM_TX_DESC; |
|
2448 |
|
2449 txd = tp->TxDescArray + entry; |
|
2450 len = frag->size; |
|
2451 addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
2452 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); |
|
2453 |
|
2454 /* anti gcc 2.95.3 bugware (sic) */ |
|
2455 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2456 |
|
2457 txd->opts1 = cpu_to_le32(status); |
|
2458 txd->addr = cpu_to_le64(mapping); |
|
2459 |
|
2460 tp->tx_skb[entry].len = len; |
|
2461 } |
|
2462 |
|
2463 if (cur_frag) { |
|
2464 tp->tx_skb[entry].skb = skb; |
|
2465 txd->opts1 |= cpu_to_le32(LastFrag); |
|
2466 } |
|
2467 |
|
2468 return cur_frag; |
|
2469 } |
|
2470 |
|
2471 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
2472 { |
|
2473 if (dev->features & NETIF_F_TSO) { |
|
2474 u32 mss = skb_shinfo(skb)->gso_size; |
|
2475 |
|
2476 if (mss) |
|
2477 return LargeSend | ((mss & MSSMask) << MSSShift); |
|
2478 } |
|
2479 if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
2480 const struct iphdr *ip = ip_hdr(skb); |
|
2481 |
|
2482 if (ip->protocol == IPPROTO_TCP) |
|
2483 return IPCS | TCPCS; |
|
2484 else if (ip->protocol == IPPROTO_UDP) |
|
2485 return IPCS | UDPCS; |
|
2486 WARN_ON(1); /* we need a WARN() */ |
|
2487 } |
|
2488 return 0; |
|
2489 } |
|
2490 |
|
2491 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
2492 { |
|
2493 struct rtl8169_private *tp = netdev_priv(dev); |
|
2494 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; |
|
2495 struct TxDesc *txd = tp->TxDescArray + entry; |
|
2496 void __iomem *ioaddr = tp->mmio_addr; |
|
2497 dma_addr_t mapping; |
|
2498 u32 status, len; |
|
2499 u32 opts1; |
|
2500 int ret = NETDEV_TX_OK; |
|
2501 |
|
2502 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
2503 if (netif_msg_drv(tp)) { |
|
2504 printk(KERN_ERR |
|
2505 "%s: BUG! Tx Ring full when queue awake!\n", |
|
2506 dev->name); |
|
2507 } |
|
2508 goto err_stop; |
|
2509 } |
|
2510 |
|
2511 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
2512 goto err_stop; |
|
2513 |
|
2514 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
2515 |
|
2516 frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
2517 if (frags) { |
|
2518 len = skb_headlen(skb); |
|
2519 opts1 |= FirstFrag; |
|
2520 } else { |
|
2521 len = skb->len; |
|
2522 |
|
2523 if (unlikely(len < ETH_ZLEN)) { |
|
2524 if (skb_padto(skb, ETH_ZLEN)) |
|
2525 goto err_update_stats; |
|
2526 len = ETH_ZLEN; |
|
2527 } |
|
2528 |
|
2529 opts1 |= FirstFrag | LastFrag; |
|
2530 tp->tx_skb[entry].skb = skb; |
|
2531 } |
|
2532 |
|
2533 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
|
2534 |
|
2535 tp->tx_skb[entry].len = len; |
|
2536 txd->addr = cpu_to_le64(mapping); |
|
2537 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
2538 |
|
2539 wmb(); |
|
2540 |
|
2541 /* anti gcc 2.95.3 bugware (sic) */ |
|
2542 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
2543 txd->opts1 = cpu_to_le32(status); |
|
2544 |
|
2545 dev->trans_start = jiffies; |
|
2546 |
|
2547 tp->cur_tx += frags + 1; |
|
2548 |
|
2549 smp_wmb(); |
|
2550 |
|
2551 RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
2552 |
|
2553 if(!tp->ecdev) { |
|
2554 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
2555 netif_stop_queue(dev); |
|
2556 smp_rmb(); |
|
2557 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
2558 netif_wake_queue(dev); |
|
2559 } |
|
2560 } |
|
2561 |
|
2562 out: |
|
2563 return ret; |
|
2564 |
|
2565 err_stop: |
|
2566 if(!tp->ecdev) { |
|
2567 netif_stop_queue(dev); |
|
2568 } |
|
2569 ret = NETDEV_TX_BUSY; |
|
2570 err_update_stats: |
|
2571 tp->stats.tx_dropped++; |
|
2572 goto out; |
|
2573 } |
|
2574 |
|
2575 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
2576 { |
|
2577 struct rtl8169_private *tp = netdev_priv(dev); |
|
2578 struct pci_dev *pdev = tp->pci_dev; |
|
2579 void __iomem *ioaddr = tp->mmio_addr; |
|
2580 u16 pci_status, pci_cmd; |
|
2581 |
|
2582 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
2583 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
2584 |
|
2585 if (netif_msg_intr(tp)) { |
|
2586 printk(KERN_ERR |
|
2587 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", |
|
2588 dev->name, pci_cmd, pci_status); |
|
2589 } |
|
2590 |
|
2591 /* |
|
2592 * The recovery sequence below admits a very elaborated explanation: |
|
2593 * - it seems to work; |
|
2594 * - I did not see what else could be done; |
|
2595 * - it makes iop3xx happy. |
|
2596 * |
|
2597 * Feel free to adjust to your needs. |
|
2598 */ |
|
2599 if (pdev->broken_parity_status) |
|
2600 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
2601 else |
|
2602 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
2603 |
|
2604 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
2605 |
|
2606 pci_write_config_word(pdev, PCI_STATUS, |
|
2607 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
2608 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
2609 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
2610 |
|
2611 /* The infamous DAC f*ckup only happens at boot time */ |
|
2612 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
2613 if (netif_msg_intr(tp)) |
|
2614 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); |
|
2615 tp->cp_cmd &= ~PCIDAC; |
|
2616 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
2617 dev->features &= ~NETIF_F_HIGHDMA; |
|
2618 } |
|
2619 |
|
2620 rtl8169_hw_reset(ioaddr); |
|
2621 |
|
2622 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
2623 } |
|
2624 |
|
2625 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
2626 struct rtl8169_private *tp, |
|
2627 void __iomem *ioaddr) |
|
2628 { |
|
2629 unsigned int dirty_tx, tx_left; |
|
2630 |
|
2631 dirty_tx = tp->dirty_tx; |
|
2632 smp_rmb(); |
|
2633 tx_left = tp->cur_tx - dirty_tx; |
|
2634 |
|
2635 while (tx_left > 0) { |
|
2636 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
2637 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
2638 u32 len = tx_skb->len; |
|
2639 u32 status; |
|
2640 |
|
2641 rmb(); |
|
2642 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
2643 if (status & DescOwn) |
|
2644 break; |
|
2645 |
|
2646 tp->stats.tx_bytes += len; |
|
2647 tp->stats.tx_packets++; |
|
2648 |
|
2649 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); |
|
2650 |
|
2651 if (status & LastFrag) { |
|
2652 if(!tp->ecdev) { |
|
2653 dev_kfree_skb_irq(tx_skb->skb); |
|
2654 tx_skb->skb = NULL; |
|
2655 } |
|
2656 } |
|
2657 dirty_tx++; |
|
2658 tx_left--; |
|
2659 } |
|
2660 |
|
2661 if (tp->dirty_tx != dirty_tx) { |
|
2662 tp->dirty_tx = dirty_tx; |
|
2663 smp_wmb(); |
|
2664 |
|
2665 if (!tp->ecdev) { |
|
2666 if (netif_queue_stopped(dev) && |
|
2667 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
2668 netif_wake_queue(dev); |
|
2669 } |
|
2670 } |
|
2671 /* |
|
2672 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
2673 * too close. Let's kick an extra TxPoll request when a burst |
|
2674 * of start_xmit activity is detected (if it is not detected, |
|
2675 * it is slow enough). -- FR |
|
2676 */ |
|
2677 smp_rmb(); |
|
2678 if (tp->cur_tx != dirty_tx) |
|
2679 RTL_W8(TxPoll, NPQ); |
|
2680 } |
|
2681 } |
|
2682 |
|
2683 static inline int rtl8169_fragmented_frame(u32 status) |
|
2684 { |
|
2685 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
2686 } |
|
2687 |
|
2688 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
|
2689 { |
|
2690 u32 opts1 = le32_to_cpu(desc->opts1); |
|
2691 u32 status = opts1 & RxProtoMask; |
|
2692 |
|
2693 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
2694 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || |
|
2695 ((status == RxProtoIP) && !(opts1 & IPFail))) |
|
2696 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
2697 else |
|
2698 skb->ip_summed = CHECKSUM_NONE; |
|
2699 } |
|
2700 |
|
2701 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
|
2702 struct rtl8169_private *tp, int pkt_size, |
|
2703 dma_addr_t addr) |
|
2704 { |
|
2705 struct sk_buff *skb; |
|
2706 bool done = false; |
|
2707 |
|
2708 if (pkt_size >= rx_copybreak) |
|
2709 goto out; |
|
2710 |
|
2711 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
|
2712 if (!skb) |
|
2713 goto out; |
|
2714 |
|
2715 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
|
2716 PCI_DMA_FROMDEVICE); |
|
2717 skb_reserve(skb, NET_IP_ALIGN); |
|
2718 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
|
2719 *sk_buff = skb; |
|
2720 done = true; |
|
2721 out: |
|
2722 return done; |
|
2723 } |
|
2724 |
|
2725 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
2726 struct rtl8169_private *tp, |
|
2727 void __iomem *ioaddr) |
|
2728 { |
|
2729 unsigned int cur_rx, rx_left; |
|
2730 unsigned int delta, count; |
|
2731 |
|
2732 cur_rx = tp->cur_rx; |
|
2733 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
2734 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota); |
|
2735 |
|
2736 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
2737 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
2738 struct RxDesc *desc = tp->RxDescArray + entry; |
|
2739 u32 status; |
|
2740 |
|
2741 rmb(); |
|
2742 status = le32_to_cpu(desc->opts1); |
|
2743 |
|
2744 if (status & DescOwn) |
|
2745 break; |
|
2746 if (unlikely(status & RxRES)) { |
|
2747 if(!tp->ecdev) { |
|
2748 if (netif_msg_rx_err(tp)) { |
|
2749 printk(KERN_INFO |
|
2750 "%s: Rx ERROR. status = %08x\n", |
|
2751 dev->name, status); |
|
2752 } |
|
2753 } |
|
2754 tp->stats.rx_errors++; |
|
2755 if (status & (RxRWT | RxRUNT)) |
|
2756 tp->stats.rx_length_errors++; |
|
2757 if (status & RxCRC) |
|
2758 tp->stats.rx_crc_errors++; |
|
2759 if (status & RxFOVF) { |
|
2760 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
2761 tp->stats.rx_fifo_errors++; |
|
2762 } |
|
2763 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2764 } else { |
|
2765 struct sk_buff *skb = tp->Rx_skbuff[entry]; |
|
2766 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
2767 int pkt_size = (status & 0x00001FFF) - 4; |
|
2768 struct pci_dev *pdev = tp->pci_dev; |
|
2769 |
|
2770 /* |
|
2771 * The driver does not support incoming fragmented |
|
2772 * frames. They are seen as a symptom of over-mtu |
|
2773 * sized frames. |
|
2774 */ |
|
2775 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
2776 tp->stats.rx_dropped++; |
|
2777 tp->stats.rx_length_errors++; |
|
2778 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2779 continue; |
|
2780 } |
|
2781 |
|
2782 rtl8169_rx_csum(skb, desc); |
|
2783 |
|
2784 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
|
2785 pci_dma_sync_single_for_device(pdev, addr, |
|
2786 pkt_size, PCI_DMA_FROMDEVICE); |
|
2787 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
2788 } else { |
|
2789 pci_unmap_single(pdev, addr, pkt_size, |
|
2790 PCI_DMA_FROMDEVICE); |
|
2791 tp->Rx_skbuff[entry] = NULL; |
|
2792 } |
|
2793 |
|
2794 |
|
2795 if (tp->ecdev) { |
|
2796 ecdev_receive(tp->ecdev, skb->data, pkt_size); |
|
2797 dev->last_rx = jiffies; |
|
2798 tp->stats.rx_bytes += pkt_size; |
|
2799 tp->stats.rx_packets++; |
|
2800 } |
|
2801 else { |
|
2802 |
|
2803 skb_put(skb, pkt_size); |
|
2804 skb->protocol = eth_type_trans(skb, dev); |
|
2805 |
|
2806 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) |
|
2807 rtl8169_rx_skb(skb); |
|
2808 |
|
2809 dev->last_rx = jiffies; |
|
2810 tp->stats.rx_bytes += pkt_size; |
|
2811 tp->stats.rx_packets++; |
|
2812 } |
|
2813 } |
|
2814 |
|
2815 /* Work around for AMD plateform. */ |
|
2816 if ((desc->opts2 & 0xfffe000) && |
|
2817 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
2818 desc->opts2 = 0; |
|
2819 cur_rx++; |
|
2820 } |
|
2821 } |
|
2822 |
|
2823 count = cur_rx - tp->cur_rx; |
|
2824 tp->cur_rx = cur_rx; |
|
2825 |
|
2826 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); |
|
2827 if (!delta && count && netif_msg_intr(tp)) |
|
2828 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
|
2829 tp->dirty_rx += delta; |
|
2830 |
|
2831 /* |
|
2832 * FIXME: until there is periodic timer to try and refill the ring, |
|
2833 * a temporary shortage may definitely kill the Rx process. |
|
2834 * - disable the asic to try and avoid an overflow and kick it again |
|
2835 * after refill ? |
|
2836 * - how do others driver handle this condition (Uh oh...). |
|
2837 */ |
|
2838 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
|
2839 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
|
2840 |
|
2841 return count; |
|
2842 } |
|
2843 |
|
2844 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
2845 { |
|
2846 struct net_device *dev = dev_instance; |
|
2847 struct rtl8169_private *tp = netdev_priv(dev); |
|
2848 int boguscnt = max_interrupt_work; |
|
2849 void __iomem *ioaddr = tp->mmio_addr; |
|
2850 int status; |
|
2851 int handled = 0; |
|
2852 |
|
2853 do { |
|
2854 if (tp->ecdev) { |
|
2855 status = RTL_R16(IntrStatus); |
|
2856 } else { |
|
2857 status = RTL_R16(IntrStatus); |
|
2858 |
|
2859 /* hotplug/major error/no more work/shared irq */ |
|
2860 if ((status == 0xFFFF) || !status) |
|
2861 break; |
|
2862 |
|
2863 handled = 1; |
|
2864 |
|
2865 if (unlikely(!netif_running(dev))) { |
|
2866 rtl8169_asic_down(ioaddr); |
|
2867 goto out; |
|
2868 } |
|
2869 status &= tp->intr_mask; |
|
2870 RTL_W16(IntrStatus, |
|
2871 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
2872 |
|
2873 if (!(status & tp->intr_event)) |
|
2874 break; |
|
2875 |
|
2876 /* Work around for rx fifo overflow */ |
|
2877 if (unlikely(status & RxFIFOOver) && |
|
2878 (tp->mac_version == RTL_GIGA_MAC_VER_11)) { |
|
2879 netif_stop_queue(dev); |
|
2880 rtl8169_tx_timeout(dev); |
|
2881 break; |
|
2882 } |
|
2883 |
|
2884 if (unlikely(status & SYSErr)) { |
|
2885 rtl8169_pcierr_interrupt(dev); |
|
2886 break; |
|
2887 } |
|
2888 } |
|
2889 |
|
2890 |
|
2891 if (status & LinkChg) |
|
2892 rtl8169_check_link_status(dev, tp, ioaddr); |
|
2893 |
|
2894 #ifdef CONFIG_R8169_NAPI |
|
2895 if (status & tp->napi_event) { |
|
2896 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
2897 tp->intr_mask = ~tp->napi_event; |
|
2898 |
|
2899 if (likely(netif_rx_schedule_prep(dev))) |
|
2900 __netif_rx_schedule(dev); |
|
2901 else if (netif_msg_intr(tp)) { |
|
2902 printk(KERN_INFO "%s: interrupt %04x in poll\n", |
|
2903 dev->name, status); |
|
2904 } |
|
2905 } |
|
2906 break; |
|
2907 #else |
|
2908 /* Rx interrupt */ |
|
2909 if (status & (RxOK | RxOverflow | RxFIFOOver)) |
|
2910 rtl8169_rx_interrupt(dev, tp, ioaddr); |
|
2911 |
|
2912 /* Tx interrupt */ |
|
2913 if (status & (TxOK | TxErr)) |
|
2914 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
2915 #endif |
|
2916 |
|
2917 boguscnt--; |
|
2918 } while (boguscnt > 0); |
|
2919 |
|
2920 if (!tp->ecdev) { |
|
2921 if (boguscnt <= 0) { |
|
2922 if (netif_msg_intr(tp) && net_ratelimit() ) { |
|
2923 printk(KERN_WARNING |
|
2924 "%s: Too much work at interrupt!\n", dev->name); |
|
2925 } |
|
2926 /* Clear all interrupt sources. */ |
|
2927 RTL_W16(IntrStatus, 0xffff); |
|
2928 } |
|
2929 } |
|
2930 out: |
|
2931 return IRQ_RETVAL(handled); |
|
2932 } |
|
2933 |
|
2934 #ifdef CONFIG_R8169_NAPI |
|
2935 static int rtl8169_poll(struct net_device *dev, int *budget) |
|
2936 { |
|
2937 unsigned int work_done, work_to_do = min(*budget, dev->quota); |
|
2938 struct rtl8169_private *tp = netdev_priv(dev); |
|
2939 void __iomem *ioaddr = tp->mmio_addr; |
|
2940 |
|
2941 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr); |
|
2942 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
2943 |
|
2944 *budget -= work_done; |
|
2945 dev->quota -= work_done; |
|
2946 |
|
2947 if (work_done < work_to_do) { |
|
2948 if (!tp->ecdev) { |
|
2949 netif_rx_complete(dev); |
|
2950 } |
|
2951 tp->intr_mask = 0xffff; |
|
2952 /* |
|
2953 * 20040426: the barrier is not strictly required but the |
|
2954 * behavior of the irq handler could be less predictable |
|
2955 * without it. Btw, the lack of flush for the posted pci |
|
2956 * write is safe - FR |
|
2957 */ |
|
2958 smp_wmb(); |
|
2959 if(!tp->ecdev) { |
|
2960 RTL_W16(IntrMask, tp->intr_event); |
|
2961 } |
|
2962 } |
|
2963 |
|
2964 return (work_done >= work_to_do); |
|
2965 } |
|
2966 #endif |
|
2967 |
|
2968 static void rtl8169_down(struct net_device *dev) |
|
2969 { |
|
2970 struct rtl8169_private *tp = netdev_priv(dev); |
|
2971 void __iomem *ioaddr = tp->mmio_addr; |
|
2972 unsigned int poll_locked = 0; |
|
2973 unsigned int intrmask; |
|
2974 |
|
2975 rtl8169_delete_timer(dev); |
|
2976 |
|
2977 |
|
2978 if (!tp->ecdev) { |
|
2979 netif_stop_queue(dev); |
|
2980 } |
|
2981 |
|
2982 core_down: |
|
2983 spin_lock_irq(&tp->lock); |
|
2984 |
|
2985 rtl8169_asic_down(ioaddr); |
|
2986 |
|
2987 /* Update the error counts. */ |
|
2988 tp->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
2989 RTL_W32(RxMissed, 0); |
|
2990 |
|
2991 spin_unlock_irq(&tp->lock); |
|
2992 |
|
2993 synchronize_irq(dev->irq); |
|
2994 |
|
2995 if (!poll_locked) { |
|
2996 if (!tp->ecdev) { |
|
2997 netif_poll_disable(dev); |
|
2998 } |
|
2999 poll_locked++; |
|
3000 } |
|
3001 |
|
3002 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
3003 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
3004 |
|
3005 /* |
|
3006 * And now for the 50k$ question: are IRQ disabled or not ? |
|
3007 * |
|
3008 * Two paths lead here: |
|
3009 * 1) dev->close |
|
3010 * -> netif_running() is available to sync the current code and the |
|
3011 * IRQ handler. See rtl8169_interrupt for details. |
|
3012 * 2) dev->change_mtu |
|
3013 * -> rtl8169_poll can not be issued again and re-enable the |
|
3014 * interruptions. Let's simply issue the IRQ down sequence again. |
|
3015 * |
|
3016 * No loop if hotpluged or major error (0xffff). |
|
3017 */ |
|
3018 intrmask = RTL_R16(IntrMask); |
|
3019 if (intrmask && (intrmask != 0xffff)) |
|
3020 goto core_down; |
|
3021 |
|
3022 rtl8169_tx_clear(tp); |
|
3023 |
|
3024 rtl8169_rx_clear(tp); |
|
3025 } |
|
3026 |
|
3027 static int rtl8169_close(struct net_device *dev) |
|
3028 { |
|
3029 struct rtl8169_private *tp = netdev_priv(dev); |
|
3030 struct pci_dev *pdev = tp->pci_dev; |
|
3031 |
|
3032 rtl8169_down(dev); |
|
3033 |
|
3034 if (!tp->ecdev) { |
|
3035 free_irq(dev->irq, dev); |
|
3036 netif_poll_enable(dev); |
|
3037 } |
|
3038 |
|
3039 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3040 tp->RxPhyAddr); |
|
3041 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3042 tp->TxPhyAddr); |
|
3043 tp->TxDescArray = NULL; |
|
3044 tp->RxDescArray = NULL; |
|
3045 |
|
3046 return 0; |
|
3047 } |
|
3048 |
|
3049 static void rtl_set_rx_mode(struct net_device *dev) |
|
3050 { |
|
3051 struct rtl8169_private *tp = netdev_priv(dev); |
|
3052 void __iomem *ioaddr = tp->mmio_addr; |
|
3053 unsigned long flags; |
|
3054 u32 mc_filter[2]; /* Multicast hash filter */ |
|
3055 int rx_mode; |
|
3056 u32 tmp = 0; |
|
3057 |
|
3058 if (dev->flags & IFF_PROMISC) { |
|
3059 /* Unconditionally log net taps. */ |
|
3060 if (!tp->ecdev) { |
|
3061 if (netif_msg_link(tp)) { |
|
3062 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", |
|
3063 dev->name); |
|
3064 } |
|
3065 } |
|
3066 rx_mode = |
|
3067 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
3068 AcceptAllPhys; |
|
3069 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3070 } else if ((dev->mc_count > multicast_filter_limit) |
|
3071 || (dev->flags & IFF_ALLMULTI)) { |
|
3072 /* Too many to filter perfectly -- accept all multicasts. */ |
|
3073 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
3074 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
3075 } else { |
|
3076 struct dev_mc_list *mclist; |
|
3077 unsigned int i; |
|
3078 |
|
3079 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
3080 mc_filter[1] = mc_filter[0] = 0; |
|
3081 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; |
|
3082 i++, mclist = mclist->next) { |
|
3083 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; |
|
3084 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
3085 rx_mode |= AcceptMulticast; |
|
3086 } |
|
3087 } |
|
3088 |
|
3089 spin_lock_irqsave(&tp->lock, flags); |
|
3090 |
|
3091 tmp = rtl8169_rx_config | rx_mode | |
|
3092 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3093 |
|
3094 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
3095 (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
3096 (tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
3097 (tp->mac_version == RTL_GIGA_MAC_VER_14) || |
|
3098 (tp->mac_version == RTL_GIGA_MAC_VER_15)) { |
|
3099 mc_filter[0] = 0xffffffff; |
|
3100 mc_filter[1] = 0xffffffff; |
|
3101 } |
|
3102 |
|
3103 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
3104 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
3105 |
|
3106 RTL_W32(RxConfig, tmp); |
|
3107 |
|
3108 spin_unlock_irqrestore(&tp->lock, flags); |
|
3109 } |
|
3110 |
|
3111 /** |
|
3112 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
3113 * @dev: The Ethernet Device to get statistics for |
|
3114 * |
|
3115 * Get TX/RX statistics for rtl8169 |
|
3116 */ |
|
3117 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
3118 { |
|
3119 struct rtl8169_private *tp = netdev_priv(dev); |
|
3120 void __iomem *ioaddr = tp->mmio_addr; |
|
3121 unsigned long flags; |
|
3122 |
|
3123 if (netif_running(dev)) { |
|
3124 spin_lock_irqsave(&tp->lock, flags); |
|
3125 tp->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
3126 RTL_W32(RxMissed, 0); |
|
3127 spin_unlock_irqrestore(&tp->lock, flags); |
|
3128 } |
|
3129 |
|
3130 return &tp->stats; |
|
3131 } |
|
3132 |
|
3133 #ifdef CONFIG_PM |
|
3134 |
|
3135 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) |
|
3136 { |
|
3137 struct net_device *dev = pci_get_drvdata(pdev); |
|
3138 struct rtl8169_private *tp = netdev_priv(dev); |
|
3139 void __iomem *ioaddr = tp->mmio_addr; |
|
3140 |
|
3141 if (!netif_running(dev)) |
|
3142 goto out_pci_suspend; |
|
3143 |
|
3144 netif_device_detach(dev); |
|
3145 netif_stop_queue(dev); |
|
3146 |
|
3147 spin_lock_irq(&tp->lock); |
|
3148 |
|
3149 rtl8169_asic_down(ioaddr); |
|
3150 |
|
3151 tp->stats.rx_missed_errors += RTL_R32(RxMissed); |
|
3152 RTL_W32(RxMissed, 0); |
|
3153 |
|
3154 spin_unlock_irq(&tp->lock); |
|
3155 |
|
3156 out_pci_suspend: |
|
3157 pci_save_state(pdev); |
|
3158 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled); |
|
3159 pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
|
3160 |
|
3161 return 0; |
|
3162 } |
|
3163 |
|
3164 static int rtl8169_resume(struct pci_dev *pdev) |
|
3165 { |
|
3166 struct net_device *dev = pci_get_drvdata(pdev); |
|
3167 |
|
3168 pci_set_power_state(pdev, PCI_D0); |
|
3169 pci_restore_state(pdev); |
|
3170 pci_enable_wake(pdev, PCI_D0, 0); |
|
3171 |
|
3172 if (!netif_running(dev)) |
|
3173 goto out; |
|
3174 |
|
3175 netif_device_attach(dev); |
|
3176 |
|
3177 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
3178 out: |
|
3179 return 0; |
|
3180 } |
|
3181 |
|
3182 #endif /* CONFIG_PM */ |
|
3183 |
|
3184 static struct pci_driver rtl8169_pci_driver = { |
|
3185 .name = MODULENAME, |
|
3186 .id_table = rtl8169_pci_tbl, |
|
3187 .probe = rtl8169_init_one, |
|
3188 .remove = __devexit_p(rtl8169_remove_one), |
|
3189 #ifdef CONFIG_PM |
|
3190 .suspend = rtl8169_suspend, |
|
3191 .resume = rtl8169_resume, |
|
3192 #endif |
|
3193 }; |
|
3194 |
|
3195 static int __init rtl8169_init_module(void) |
|
3196 { |
|
3197 return pci_register_driver(&rtl8169_pci_driver); |
|
3198 } |
|
3199 |
|
3200 static void __exit rtl8169_cleanup_module(void) |
|
3201 { |
|
3202 pci_unregister_driver(&rtl8169_pci_driver); |
|
3203 } |
|
3204 |
|
3205 module_init(rtl8169_init_module); |
|
3206 module_exit(rtl8169_cleanup_module); |