|
1 /* |
|
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
|
3 * |
|
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
|
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
|
6 * Copyright (c) a lot of people too. Please respect their work. |
|
7 * |
|
8 * See MAINTAINERS file for support contact information. |
|
9 */ |
|
10 |
|
11 #include <linux/module.h> |
|
12 #include <linux/moduleparam.h> |
|
13 #include <linux/pci.h> |
|
14 #include <linux/netdevice.h> |
|
15 #include <linux/etherdevice.h> |
|
16 #include <linux/delay.h> |
|
17 #include <linux/ethtool.h> |
|
18 #include <linux/mii.h> |
|
19 #include <linux/if_vlan.h> |
|
20 #include <linux/crc32.h> |
|
21 #include <linux/in.h> |
|
22 #include <linux/ip.h> |
|
23 #include <linux/tcp.h> |
|
24 #include <linux/init.h> |
|
25 #include <linux/interrupt.h> |
|
26 #include <linux/dma-mapping.h> |
|
27 #include <linux/pm_runtime.h> |
|
28 #include <linux/firmware.h> |
|
29 #include <linux/pci-aspm.h> |
|
30 #include <linux/prefetch.h> |
|
31 |
|
32 #include <asm/io.h> |
|
33 #include <asm/irq.h> |
|
34 #include "../globals.h" |
|
35 #include "ecdev.h" |
|
36 |
|
37 #define RTL8169_VERSION "2.3LK-NAPI" |
|
38 #define MODULENAME "ec_r8169" |
|
39 #define PFX MODULENAME ": " |
|
40 |
|
41 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
|
42 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
|
43 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
|
44 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" |
|
45 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
|
46 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
|
47 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" |
|
48 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
|
49 |
|
50 #ifdef RTL8169_DEBUG |
|
51 #define assert(expr) \ |
|
52 if (!(expr)) { \ |
|
53 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
|
54 #expr,__FILE__,__func__,__LINE__); \ |
|
55 } |
|
56 #define dprintk(fmt, args...) \ |
|
57 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
|
58 #else |
|
59 #define assert(expr) do {} while (0) |
|
60 #define dprintk(fmt, args...) do {} while (0) |
|
61 #endif /* RTL8169_DEBUG */ |
|
62 |
|
63 #define R8169_MSG_DEFAULT \ |
|
64 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
|
65 |
|
66 #define TX_SLOTS_AVAIL(tp) \ |
|
67 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) |
|
68 |
|
69 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ |
|
70 #define TX_FRAGS_READY_FOR(tp,nr_frags) \ |
|
71 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) |
|
72 |
|
73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
|
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
|
75 static const int multicast_filter_limit = 32; |
|
76 |
|
77 #define MAX_READ_REQUEST_SHIFT 12 |
|
78 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
|
79 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
|
80 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
|
81 |
|
82 #define R8169_REGS_SIZE 256 |
|
83 #define R8169_NAPI_WEIGHT 64 |
|
84 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
|
85 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
|
86 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
|
87 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
|
88 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
|
89 |
|
90 #define RTL8169_TX_TIMEOUT (6*HZ) |
|
91 #define RTL8169_PHY_TIMEOUT (10*HZ) |
|
92 |
|
93 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
|
94 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
|
95 #define RTL_EEPROM_SIG_ADDR 0x0000 |
|
96 |
|
97 /* write/read MMIO register */ |
|
98 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
|
99 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
|
100 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
|
101 #define RTL_R8(reg) readb (ioaddr + (reg)) |
|
102 #define RTL_R16(reg) readw (ioaddr + (reg)) |
|
103 #define RTL_R32(reg) readl (ioaddr + (reg)) |
|
104 |
|
105 enum mac_version { |
|
106 RTL_GIGA_MAC_VER_01 = 0, |
|
107 RTL_GIGA_MAC_VER_02, |
|
108 RTL_GIGA_MAC_VER_03, |
|
109 RTL_GIGA_MAC_VER_04, |
|
110 RTL_GIGA_MAC_VER_05, |
|
111 RTL_GIGA_MAC_VER_06, |
|
112 RTL_GIGA_MAC_VER_07, |
|
113 RTL_GIGA_MAC_VER_08, |
|
114 RTL_GIGA_MAC_VER_09, |
|
115 RTL_GIGA_MAC_VER_10, |
|
116 RTL_GIGA_MAC_VER_11, |
|
117 RTL_GIGA_MAC_VER_12, |
|
118 RTL_GIGA_MAC_VER_13, |
|
119 RTL_GIGA_MAC_VER_14, |
|
120 RTL_GIGA_MAC_VER_15, |
|
121 RTL_GIGA_MAC_VER_16, |
|
122 RTL_GIGA_MAC_VER_17, |
|
123 RTL_GIGA_MAC_VER_18, |
|
124 RTL_GIGA_MAC_VER_19, |
|
125 RTL_GIGA_MAC_VER_20, |
|
126 RTL_GIGA_MAC_VER_21, |
|
127 RTL_GIGA_MAC_VER_22, |
|
128 RTL_GIGA_MAC_VER_23, |
|
129 RTL_GIGA_MAC_VER_24, |
|
130 RTL_GIGA_MAC_VER_25, |
|
131 RTL_GIGA_MAC_VER_26, |
|
132 RTL_GIGA_MAC_VER_27, |
|
133 RTL_GIGA_MAC_VER_28, |
|
134 RTL_GIGA_MAC_VER_29, |
|
135 RTL_GIGA_MAC_VER_30, |
|
136 RTL_GIGA_MAC_VER_31, |
|
137 RTL_GIGA_MAC_VER_32, |
|
138 RTL_GIGA_MAC_VER_33, |
|
139 RTL_GIGA_MAC_VER_34, |
|
140 RTL_GIGA_MAC_VER_35, |
|
141 RTL_GIGA_MAC_VER_36, |
|
142 RTL_GIGA_MAC_NONE = 0xff, |
|
143 }; |
|
144 |
|
145 enum rtl_tx_desc_version { |
|
146 RTL_TD_0 = 0, |
|
147 RTL_TD_1 = 1, |
|
148 }; |
|
149 |
|
150 #define JUMBO_1K ETH_DATA_LEN |
|
151 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) |
|
152 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) |
|
153 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) |
|
154 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) |
|
155 |
|
156 #define _R(NAME,TD,FW,SZ,B) { \ |
|
157 .name = NAME, \ |
|
158 .txd_version = TD, \ |
|
159 .fw_name = FW, \ |
|
160 .jumbo_max = SZ, \ |
|
161 .jumbo_tx_csum = B \ |
|
162 } |
|
163 |
|
164 static const struct { |
|
165 const char *name; |
|
166 enum rtl_tx_desc_version txd_version; |
|
167 const char *fw_name; |
|
168 u16 jumbo_max; |
|
169 bool jumbo_tx_csum; |
|
170 } rtl_chip_infos[] = { |
|
171 /* PCI devices. */ |
|
172 [RTL_GIGA_MAC_VER_01] = |
|
173 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
|
174 [RTL_GIGA_MAC_VER_02] = |
|
175 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
|
176 [RTL_GIGA_MAC_VER_03] = |
|
177 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
|
178 [RTL_GIGA_MAC_VER_04] = |
|
179 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
|
180 [RTL_GIGA_MAC_VER_05] = |
|
181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
|
182 [RTL_GIGA_MAC_VER_06] = |
|
183 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
|
184 /* PCI-E devices. */ |
|
185 [RTL_GIGA_MAC_VER_07] = |
|
186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
|
187 [RTL_GIGA_MAC_VER_08] = |
|
188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
|
189 [RTL_GIGA_MAC_VER_09] = |
|
190 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
|
191 [RTL_GIGA_MAC_VER_10] = |
|
192 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
|
193 [RTL_GIGA_MAC_VER_11] = |
|
194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
|
195 [RTL_GIGA_MAC_VER_12] = |
|
196 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
|
197 [RTL_GIGA_MAC_VER_13] = |
|
198 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
|
199 [RTL_GIGA_MAC_VER_14] = |
|
200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
|
201 [RTL_GIGA_MAC_VER_15] = |
|
202 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
|
203 [RTL_GIGA_MAC_VER_16] = |
|
204 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
|
205 [RTL_GIGA_MAC_VER_17] = |
|
206 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
|
207 [RTL_GIGA_MAC_VER_18] = |
|
208 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
|
209 [RTL_GIGA_MAC_VER_19] = |
|
210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
|
211 [RTL_GIGA_MAC_VER_20] = |
|
212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
|
213 [RTL_GIGA_MAC_VER_21] = |
|
214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
|
215 [RTL_GIGA_MAC_VER_22] = |
|
216 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
|
217 [RTL_GIGA_MAC_VER_23] = |
|
218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
|
219 [RTL_GIGA_MAC_VER_24] = |
|
220 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
|
221 [RTL_GIGA_MAC_VER_25] = |
|
222 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
|
223 JUMBO_9K, false), |
|
224 [RTL_GIGA_MAC_VER_26] = |
|
225 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
|
226 JUMBO_9K, false), |
|
227 [RTL_GIGA_MAC_VER_27] = |
|
228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
|
229 [RTL_GIGA_MAC_VER_28] = |
|
230 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
|
231 [RTL_GIGA_MAC_VER_29] = |
|
232 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
|
233 JUMBO_1K, true), |
|
234 [RTL_GIGA_MAC_VER_30] = |
|
235 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
|
236 JUMBO_1K, true), |
|
237 [RTL_GIGA_MAC_VER_31] = |
|
238 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
|
239 [RTL_GIGA_MAC_VER_32] = |
|
240 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
|
241 JUMBO_9K, false), |
|
242 [RTL_GIGA_MAC_VER_33] = |
|
243 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
|
244 JUMBO_9K, false), |
|
245 [RTL_GIGA_MAC_VER_34] = |
|
246 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
|
247 JUMBO_9K, false), |
|
248 [RTL_GIGA_MAC_VER_35] = |
|
249 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
|
250 JUMBO_9K, false), |
|
251 [RTL_GIGA_MAC_VER_36] = |
|
252 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
|
253 JUMBO_9K, false), |
|
254 }; |
|
255 #undef _R |
|
256 |
|
257 enum cfg_version { |
|
258 RTL_CFG_0 = 0x00, |
|
259 RTL_CFG_1, |
|
260 RTL_CFG_2 |
|
261 }; |
|
262 |
|
263 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
|
264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
|
265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
|
266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
|
267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
|
268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
|
269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
|
270 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
|
271 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
|
272 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
|
273 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
|
274 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
|
275 { 0x0001, 0x8168, |
|
276 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
|
277 {0,}, |
|
278 }; |
|
279 |
|
280 /* prevent driver from being loaded automatically */ |
|
281 //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
|
282 |
|
283 static int rx_buf_sz = 16383; |
|
284 static int use_dac; |
|
285 static struct { |
|
286 u32 msg_enable; |
|
287 } debug = { -1 }; |
|
288 |
|
289 enum rtl_registers { |
|
290 MAC0 = 0, /* Ethernet hardware address. */ |
|
291 MAC4 = 4, |
|
292 MAR0 = 8, /* Multicast filter. */ |
|
293 CounterAddrLow = 0x10, |
|
294 CounterAddrHigh = 0x14, |
|
295 TxDescStartAddrLow = 0x20, |
|
296 TxDescStartAddrHigh = 0x24, |
|
297 TxHDescStartAddrLow = 0x28, |
|
298 TxHDescStartAddrHigh = 0x2c, |
|
299 FLASH = 0x30, |
|
300 ERSR = 0x36, |
|
301 ChipCmd = 0x37, |
|
302 TxPoll = 0x38, |
|
303 IntrMask = 0x3c, |
|
304 IntrStatus = 0x3e, |
|
305 |
|
306 TxConfig = 0x40, |
|
307 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
|
308 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ |
|
309 |
|
310 RxConfig = 0x44, |
|
311 #define RX128_INT_EN (1 << 15) /* 8111c and later */ |
|
312 #define RX_MULTI_EN (1 << 14) /* 8111c only */ |
|
313 #define RXCFG_FIFO_SHIFT 13 |
|
314 /* No threshold before first PCI xfer */ |
|
315 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) |
|
316 #define RXCFG_DMA_SHIFT 8 |
|
317 /* Unlimited maximum PCI burst. */ |
|
318 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) |
|
319 |
|
320 RxMissed = 0x4c, |
|
321 Cfg9346 = 0x50, |
|
322 Config0 = 0x51, |
|
323 Config1 = 0x52, |
|
324 Config2 = 0x53, |
|
325 #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
|
326 |
|
327 Config3 = 0x54, |
|
328 Config4 = 0x55, |
|
329 Config5 = 0x56, |
|
330 MultiIntr = 0x5c, |
|
331 PHYAR = 0x60, |
|
332 PHYstatus = 0x6c, |
|
333 RxMaxSize = 0xda, |
|
334 CPlusCmd = 0xe0, |
|
335 IntrMitigate = 0xe2, |
|
336 RxDescAddrLow = 0xe4, |
|
337 RxDescAddrHigh = 0xe8, |
|
338 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
|
339 |
|
340 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ |
|
341 |
|
342 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ |
|
343 |
|
344 #define TxPacketMax (8064 >> 7) |
|
345 #define EarlySize 0x27 |
|
346 |
|
347 FuncEvent = 0xf0, |
|
348 FuncEventMask = 0xf4, |
|
349 FuncPresetState = 0xf8, |
|
350 FuncForceEvent = 0xfc, |
|
351 }; |
|
352 |
|
353 enum rtl8110_registers { |
|
354 TBICSR = 0x64, |
|
355 TBI_ANAR = 0x68, |
|
356 TBI_LPAR = 0x6a, |
|
357 }; |
|
358 |
|
359 enum rtl8168_8101_registers { |
|
360 CSIDR = 0x64, |
|
361 CSIAR = 0x68, |
|
362 #define CSIAR_FLAG 0x80000000 |
|
363 #define CSIAR_WRITE_CMD 0x80000000 |
|
364 #define CSIAR_BYTE_ENABLE 0x0f |
|
365 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
|
366 #define CSIAR_ADDR_MASK 0x0fff |
|
367 PMCH = 0x6f, |
|
368 EPHYAR = 0x80, |
|
369 #define EPHYAR_FLAG 0x80000000 |
|
370 #define EPHYAR_WRITE_CMD 0x80000000 |
|
371 #define EPHYAR_REG_MASK 0x1f |
|
372 #define EPHYAR_REG_SHIFT 16 |
|
373 #define EPHYAR_DATA_MASK 0xffff |
|
374 DLLPR = 0xd0, |
|
375 #define PFM_EN (1 << 6) |
|
376 DBG_REG = 0xd1, |
|
377 #define FIX_NAK_1 (1 << 4) |
|
378 #define FIX_NAK_2 (1 << 3) |
|
379 TWSI = 0xd2, |
|
380 MCU = 0xd3, |
|
381 #define NOW_IS_OOB (1 << 7) |
|
382 #define EN_NDP (1 << 3) |
|
383 #define EN_OOB_RESET (1 << 2) |
|
384 EFUSEAR = 0xdc, |
|
385 #define EFUSEAR_FLAG 0x80000000 |
|
386 #define EFUSEAR_WRITE_CMD 0x80000000 |
|
387 #define EFUSEAR_READ_CMD 0x00000000 |
|
388 #define EFUSEAR_REG_MASK 0x03ff |
|
389 #define EFUSEAR_REG_SHIFT 8 |
|
390 #define EFUSEAR_DATA_MASK 0xff |
|
391 }; |
|
392 |
|
393 enum rtl8168_registers { |
|
394 LED_FREQ = 0x1a, |
|
395 EEE_LED = 0x1b, |
|
396 ERIDR = 0x70, |
|
397 ERIAR = 0x74, |
|
398 #define ERIAR_FLAG 0x80000000 |
|
399 #define ERIAR_WRITE_CMD 0x80000000 |
|
400 #define ERIAR_READ_CMD 0x00000000 |
|
401 #define ERIAR_ADDR_BYTE_ALIGN 4 |
|
402 #define ERIAR_TYPE_SHIFT 16 |
|
403 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
|
404 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) |
|
405 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) |
|
406 #define ERIAR_MASK_SHIFT 12 |
|
407 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) |
|
408 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) |
|
409 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
|
410 EPHY_RXER_NUM = 0x7c, |
|
411 OCPDR = 0xb0, /* OCP GPHY access */ |
|
412 #define OCPDR_WRITE_CMD 0x80000000 |
|
413 #define OCPDR_READ_CMD 0x00000000 |
|
414 #define OCPDR_REG_MASK 0x7f |
|
415 #define OCPDR_GPHY_REG_SHIFT 16 |
|
416 #define OCPDR_DATA_MASK 0xffff |
|
417 OCPAR = 0xb4, |
|
418 #define OCPAR_FLAG 0x80000000 |
|
419 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 |
|
420 #define OCPAR_GPHY_READ_CMD 0x0000f060 |
|
421 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
|
422 MISC = 0xf0, /* 8168e only. */ |
|
423 #define TXPLA_RST (1 << 29) |
|
424 #define PWM_EN (1 << 22) |
|
425 }; |
|
426 |
|
427 enum rtl_register_content { |
|
428 /* InterruptStatusBits */ |
|
429 SYSErr = 0x8000, |
|
430 PCSTimeout = 0x4000, |
|
431 SWInt = 0x0100, |
|
432 TxDescUnavail = 0x0080, |
|
433 RxFIFOOver = 0x0040, |
|
434 LinkChg = 0x0020, |
|
435 RxOverflow = 0x0010, |
|
436 TxErr = 0x0008, |
|
437 TxOK = 0x0004, |
|
438 RxErr = 0x0002, |
|
439 RxOK = 0x0001, |
|
440 |
|
441 /* RxStatusDesc */ |
|
442 RxBOVF = (1 << 24), |
|
443 RxFOVF = (1 << 23), |
|
444 RxRWT = (1 << 22), |
|
445 RxRES = (1 << 21), |
|
446 RxRUNT = (1 << 20), |
|
447 RxCRC = (1 << 19), |
|
448 |
|
449 /* ChipCmdBits */ |
|
450 StopReq = 0x80, |
|
451 CmdReset = 0x10, |
|
452 CmdRxEnb = 0x08, |
|
453 CmdTxEnb = 0x04, |
|
454 RxBufEmpty = 0x01, |
|
455 |
|
456 /* TXPoll register p.5 */ |
|
457 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
458 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
459 FSWInt = 0x01, /* Forced software interrupt */ |
|
460 |
|
461 /* Cfg9346Bits */ |
|
462 Cfg9346_Lock = 0x00, |
|
463 Cfg9346_Unlock = 0xc0, |
|
464 |
|
465 /* rx_mode_bits */ |
|
466 AcceptErr = 0x20, |
|
467 AcceptRunt = 0x10, |
|
468 AcceptBroadcast = 0x08, |
|
469 AcceptMulticast = 0x04, |
|
470 AcceptMyPhys = 0x02, |
|
471 AcceptAllPhys = 0x01, |
|
472 #define RX_CONFIG_ACCEPT_MASK 0x3f |
|
473 |
|
474 /* TxConfigBits */ |
|
475 TxInterFrameGapShift = 24, |
|
476 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
477 |
|
478 /* Config1 register p.24 */ |
|
479 LEDS1 = (1 << 7), |
|
480 LEDS0 = (1 << 6), |
|
481 Speed_down = (1 << 4), |
|
482 MEMMAP = (1 << 3), |
|
483 IOMAP = (1 << 2), |
|
484 VPD = (1 << 1), |
|
485 PMEnable = (1 << 0), /* Power Management Enable */ |
|
486 |
|
487 /* Config2 register p. 25 */ |
|
488 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
|
489 PCI_Clock_66MHz = 0x01, |
|
490 PCI_Clock_33MHz = 0x00, |
|
491 |
|
492 /* Config3 register p.25 */ |
|
493 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
494 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
495 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
|
496 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
|
497 |
|
498 /* Config4 register */ |
|
499 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ |
|
500 |
|
501 /* Config5 register p.27 */ |
|
502 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
503 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
504 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
505 Spi_en = (1 << 3), |
|
506 LanWake = (1 << 1), /* LanWake enable/disable */ |
|
507 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
508 |
|
509 /* TBICSR p.28 */ |
|
510 TBIReset = 0x80000000, |
|
511 TBILoopback = 0x40000000, |
|
512 TBINwEnable = 0x20000000, |
|
513 TBINwRestart = 0x10000000, |
|
514 TBILinkOk = 0x02000000, |
|
515 TBINwComplete = 0x01000000, |
|
516 |
|
517 /* CPlusCmd p.31 */ |
|
518 EnableBist = (1 << 15), // 8168 8101 |
|
519 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
|
520 Normal_mode = (1 << 13), // unused |
|
521 Force_half_dup = (1 << 12), // 8168 8101 |
|
522 Force_rxflow_en = (1 << 11), // 8168 8101 |
|
523 Force_txflow_en = (1 << 10), // 8168 8101 |
|
524 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
|
525 ASF = (1 << 8), // 8168 8101 |
|
526 PktCntrDisable = (1 << 7), // 8168 8101 |
|
527 Mac_dbgo_sel = 0x001c, // 8168 |
|
528 RxVlan = (1 << 6), |
|
529 RxChkSum = (1 << 5), |
|
530 PCIDAC = (1 << 4), |
|
531 PCIMulRW = (1 << 3), |
|
532 INTT_0 = 0x0000, // 8168 |
|
533 INTT_1 = 0x0001, // 8168 |
|
534 INTT_2 = 0x0002, // 8168 |
|
535 INTT_3 = 0x0003, // 8168 |
|
536 |
|
537 /* rtl8169_PHYstatus */ |
|
538 TBI_Enable = 0x80, |
|
539 TxFlowCtrl = 0x40, |
|
540 RxFlowCtrl = 0x20, |
|
541 _1000bpsF = 0x10, |
|
542 _100bps = 0x08, |
|
543 _10bps = 0x04, |
|
544 LinkStatus = 0x02, |
|
545 FullDup = 0x01, |
|
546 |
|
547 /* _TBICSRBit */ |
|
548 TBILinkOK = 0x02000000, |
|
549 |
|
550 /* DumpCounterCommand */ |
|
551 CounterDump = 0x8, |
|
552 }; |
|
553 |
|
554 enum rtl_desc_bit { |
|
555 /* First doubleword. */ |
|
556 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
557 RingEnd = (1 << 30), /* End of descriptor ring */ |
|
558 FirstFrag = (1 << 29), /* First segment of a packet */ |
|
559 LastFrag = (1 << 28), /* Final segment of a packet */ |
|
560 }; |
|
561 |
|
562 /* Generic case. */ |
|
563 enum rtl_tx_desc_bit { |
|
564 /* First doubleword. */ |
|
565 TD_LSO = (1 << 27), /* Large Send Offload */ |
|
566 #define TD_MSS_MAX 0x07ffu /* MSS value */ |
|
567 |
|
568 /* Second doubleword. */ |
|
569 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
570 }; |
|
571 |
|
572 /* 8169, 8168b and 810x except 8102e. */ |
|
573 enum rtl_tx_desc_bit_0 { |
|
574 /* First doubleword. */ |
|
575 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ |
|
576 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
577 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
578 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ |
|
579 }; |
|
580 |
|
581 /* 8102e, 8168c and beyond. */ |
|
582 enum rtl_tx_desc_bit_1 { |
|
583 /* Second doubleword. */ |
|
584 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
|
585 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ |
|
586 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
|
587 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ |
|
588 }; |
|
589 |
|
590 static const struct rtl_tx_desc_info { |
|
591 struct { |
|
592 u32 udp; |
|
593 u32 tcp; |
|
594 } checksum; |
|
595 u16 mss_shift; |
|
596 u16 opts_offset; |
|
597 } tx_desc_info [] = { |
|
598 [RTL_TD_0] = { |
|
599 .checksum = { |
|
600 .udp = TD0_IP_CS | TD0_UDP_CS, |
|
601 .tcp = TD0_IP_CS | TD0_TCP_CS |
|
602 }, |
|
603 .mss_shift = TD0_MSS_SHIFT, |
|
604 .opts_offset = 0 |
|
605 }, |
|
606 [RTL_TD_1] = { |
|
607 .checksum = { |
|
608 .udp = TD1_IP_CS | TD1_UDP_CS, |
|
609 .tcp = TD1_IP_CS | TD1_TCP_CS |
|
610 }, |
|
611 .mss_shift = TD1_MSS_SHIFT, |
|
612 .opts_offset = 1 |
|
613 } |
|
614 }; |
|
615 |
|
616 enum rtl_rx_desc_bit { |
|
617 /* Rx private */ |
|
618 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
619 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
620 |
|
621 #define RxProtoUDP (PID1) |
|
622 #define RxProtoTCP (PID0) |
|
623 #define RxProtoIP (PID1 | PID0) |
|
624 #define RxProtoMask RxProtoIP |
|
625 |
|
626 IPFail = (1 << 16), /* IP checksum failed */ |
|
627 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
628 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
629 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
630 }; |
|
631 |
|
632 #define RsvdMask 0x3fffc000 |
|
633 |
|
634 struct TxDesc { |
|
635 __le32 opts1; |
|
636 __le32 opts2; |
|
637 __le64 addr; |
|
638 }; |
|
639 |
|
640 struct RxDesc { |
|
641 __le32 opts1; |
|
642 __le32 opts2; |
|
643 __le64 addr; |
|
644 }; |
|
645 |
|
646 struct ring_info { |
|
647 struct sk_buff *skb; |
|
648 u32 len; |
|
649 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
650 }; |
|
651 |
|
652 enum features { |
|
653 RTL_FEATURE_WOL = (1 << 0), |
|
654 RTL_FEATURE_MSI = (1 << 1), |
|
655 RTL_FEATURE_GMII = (1 << 2), |
|
656 }; |
|
657 |
|
658 struct rtl8169_counters { |
|
659 __le64 tx_packets; |
|
660 __le64 rx_packets; |
|
661 __le64 tx_errors; |
|
662 __le32 rx_errors; |
|
663 __le16 rx_missed; |
|
664 __le16 align_errors; |
|
665 __le32 tx_one_collision; |
|
666 __le32 tx_multi_collision; |
|
667 __le64 rx_unicast; |
|
668 __le64 rx_broadcast; |
|
669 __le32 rx_multicast; |
|
670 __le16 tx_aborted; |
|
671 __le16 tx_underun; |
|
672 }; |
|
673 |
|
674 enum rtl_flag { |
|
675 RTL_FLAG_TASK_ENABLED, |
|
676 RTL_FLAG_TASK_SLOW_PENDING, |
|
677 RTL_FLAG_TASK_RESET_PENDING, |
|
678 RTL_FLAG_TASK_PHY_PENDING, |
|
679 RTL_FLAG_MAX |
|
680 }; |
|
681 |
|
682 struct rtl8169_stats { |
|
683 u64 packets; |
|
684 u64 bytes; |
|
685 struct u64_stats_sync syncp; |
|
686 }; |
|
687 |
|
688 struct rtl8169_private { |
|
689 void __iomem *mmio_addr; /* memory map physical address */ |
|
690 struct pci_dev *pci_dev; |
|
691 struct net_device *dev; |
|
692 struct napi_struct napi; |
|
693 u32 msg_enable; |
|
694 u16 txd_version; |
|
695 u16 mac_version; |
|
696 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
697 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
698 u32 dirty_rx; |
|
699 u32 dirty_tx; |
|
700 struct rtl8169_stats rx_stats; |
|
701 struct rtl8169_stats tx_stats; |
|
702 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
703 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
704 dma_addr_t TxPhyAddr; |
|
705 dma_addr_t RxPhyAddr; |
|
706 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
707 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
708 struct timer_list timer; |
|
709 u16 cp_cmd; |
|
710 |
|
711 u16 event_slow; |
|
712 |
|
713 struct mdio_ops { |
|
714 void (*write)(void __iomem *, int, int); |
|
715 int (*read)(void __iomem *, int); |
|
716 } mdio_ops; |
|
717 |
|
718 struct pll_power_ops { |
|
719 void (*down)(struct rtl8169_private *); |
|
720 void (*up)(struct rtl8169_private *); |
|
721 } pll_power_ops; |
|
722 |
|
723 struct jumbo_ops { |
|
724 void (*enable)(struct rtl8169_private *); |
|
725 void (*disable)(struct rtl8169_private *); |
|
726 } jumbo_ops; |
|
727 |
|
728 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
|
729 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
730 void (*phy_reset_enable)(struct rtl8169_private *tp); |
|
731 void (*hw_start)(struct net_device *); |
|
732 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
|
733 unsigned int (*link_ok)(void __iomem *); |
|
734 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
735 |
|
736 struct { |
|
737 DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
|
738 struct mutex mutex; |
|
739 struct work_struct work; |
|
740 } wk; |
|
741 |
|
742 unsigned features; |
|
743 |
|
744 struct mii_if_info mii; |
|
745 struct rtl8169_counters counters; |
|
746 u32 saved_wolopts; |
|
747 |
|
748 ec_device_t *ecdev; |
|
749 unsigned long ec_watchdog_jiffies; |
|
750 u32 opts1_mask; |
|
751 |
|
752 struct rtl_fw { |
|
753 const struct firmware *fw; |
|
754 |
|
755 #define RTL_VER_SIZE 32 |
|
756 |
|
757 char version[RTL_VER_SIZE]; |
|
758 |
|
759 struct rtl_fw_phy_action { |
|
760 __le32 *code; |
|
761 size_t size; |
|
762 } phy_action; |
|
763 } *rtl_fw; |
|
764 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
|
765 }; |
|
766 |
|
767 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
768 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver (EtherCAT)"); |
|
769 module_param(use_dac, int, 0); |
|
770 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
771 module_param_named(debug, debug.msg_enable, int, 0); |
|
772 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
773 MODULE_LICENSE("GPL"); |
|
774 MODULE_VERSION(EC_MASTER_VERSION); |
|
775 MODULE_FIRMWARE(FIRMWARE_8168D_1); |
|
776 MODULE_FIRMWARE(FIRMWARE_8168D_2); |
|
777 MODULE_FIRMWARE(FIRMWARE_8168E_1); |
|
778 MODULE_FIRMWARE(FIRMWARE_8168E_2); |
|
779 MODULE_FIRMWARE(FIRMWARE_8168E_3); |
|
780 MODULE_FIRMWARE(FIRMWARE_8105E_1); |
|
781 MODULE_FIRMWARE(FIRMWARE_8168F_1); |
|
782 MODULE_FIRMWARE(FIRMWARE_8168F_2); |
|
783 |
|
784 static void rtl_lock_work(struct rtl8169_private *tp) |
|
785 { |
|
786 mutex_lock(&tp->wk.mutex); |
|
787 } |
|
788 |
|
789 static void rtl_unlock_work(struct rtl8169_private *tp) |
|
790 { |
|
791 mutex_unlock(&tp->wk.mutex); |
|
792 } |
|
793 |
|
794 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
795 { |
|
796 int cap = pci_pcie_cap(pdev); |
|
797 |
|
798 if (cap) { |
|
799 u16 ctl; |
|
800 |
|
801 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
802 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
803 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
804 } |
|
805 } |
|
806 |
|
807 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
|
808 { |
|
809 void __iomem *ioaddr = tp->mmio_addr; |
|
810 int i; |
|
811 |
|
812 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
813 for (i = 0; i < 20; i++) { |
|
814 udelay(100); |
|
815 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
816 break; |
|
817 } |
|
818 return RTL_R32(OCPDR); |
|
819 } |
|
820 |
|
821 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) |
|
822 { |
|
823 void __iomem *ioaddr = tp->mmio_addr; |
|
824 int i; |
|
825 |
|
826 RTL_W32(OCPDR, data); |
|
827 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
828 for (i = 0; i < 20; i++) { |
|
829 udelay(100); |
|
830 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) |
|
831 break; |
|
832 } |
|
833 } |
|
834 |
|
835 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
|
836 { |
|
837 void __iomem *ioaddr = tp->mmio_addr; |
|
838 int i; |
|
839 |
|
840 RTL_W8(ERIDR, cmd); |
|
841 RTL_W32(ERIAR, 0x800010e8); |
|
842 msleep(2); |
|
843 for (i = 0; i < 5; i++) { |
|
844 udelay(100); |
|
845 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
846 break; |
|
847 } |
|
848 |
|
849 ocp_write(tp, 0x1, 0x30, 0x00000001); |
|
850 } |
|
851 |
|
852 #define OOB_CMD_RESET 0x00 |
|
853 #define OOB_CMD_DRIVER_START 0x05 |
|
854 #define OOB_CMD_DRIVER_STOP 0x06 |
|
855 |
|
856 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
|
857 { |
|
858 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; |
|
859 } |
|
860 |
|
861 static void rtl8168_driver_start(struct rtl8169_private *tp) |
|
862 { |
|
863 u16 reg; |
|
864 int i; |
|
865 |
|
866 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
|
867 |
|
868 reg = rtl8168_get_ocp_reg(tp); |
|
869 |
|
870 for (i = 0; i < 10; i++) { |
|
871 msleep(10); |
|
872 if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
|
873 break; |
|
874 } |
|
875 } |
|
876 |
|
877 static void rtl8168_driver_stop(struct rtl8169_private *tp) |
|
878 { |
|
879 u16 reg; |
|
880 int i; |
|
881 |
|
882 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); |
|
883 |
|
884 reg = rtl8168_get_ocp_reg(tp); |
|
885 |
|
886 for (i = 0; i < 10; i++) { |
|
887 msleep(10); |
|
888 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
|
889 break; |
|
890 } |
|
891 } |
|
892 |
|
893 static int r8168dp_check_dash(struct rtl8169_private *tp) |
|
894 { |
|
895 u16 reg = rtl8168_get_ocp_reg(tp); |
|
896 |
|
897 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
|
898 } |
|
899 |
|
900 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
901 { |
|
902 int i; |
|
903 |
|
904 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
905 |
|
906 for (i = 20; i > 0; i--) { |
|
907 /* |
|
908 * Check if the RTL8169 has completed writing to the specified |
|
909 * MII register. |
|
910 */ |
|
911 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
912 break; |
|
913 udelay(25); |
|
914 } |
|
915 /* |
|
916 * According to hardware specs a 20us delay is required after write |
|
917 * complete indication, but before sending next command. |
|
918 */ |
|
919 udelay(20); |
|
920 } |
|
921 |
|
922 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
923 { |
|
924 int i, value = -1; |
|
925 |
|
926 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
927 |
|
928 for (i = 20; i > 0; i--) { |
|
929 /* |
|
930 * Check if the RTL8169 has completed retrieving data from |
|
931 * the specified MII register. |
|
932 */ |
|
933 if (RTL_R32(PHYAR) & 0x80000000) { |
|
934 value = RTL_R32(PHYAR) & 0xffff; |
|
935 break; |
|
936 } |
|
937 udelay(25); |
|
938 } |
|
939 /* |
|
940 * According to hardware specs a 20us delay is required after read |
|
941 * complete indication, but before sending next command. |
|
942 */ |
|
943 udelay(20); |
|
944 |
|
945 return value; |
|
946 } |
|
947 |
|
948 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
|
949 { |
|
950 int i; |
|
951 |
|
952 RTL_W32(OCPDR, data | |
|
953 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
|
954 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
|
955 RTL_W32(EPHY_RXER_NUM, 0); |
|
956 |
|
957 for (i = 0; i < 100; i++) { |
|
958 mdelay(1); |
|
959 if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) |
|
960 break; |
|
961 } |
|
962 } |
|
963 |
|
964 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
965 { |
|
966 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | |
|
967 (value & OCPDR_DATA_MASK)); |
|
968 } |
|
969 |
|
970 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
971 { |
|
972 int i; |
|
973 |
|
974 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); |
|
975 |
|
976 mdelay(1); |
|
977 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); |
|
978 RTL_W32(EPHY_RXER_NUM, 0); |
|
979 |
|
980 for (i = 0; i < 100; i++) { |
|
981 mdelay(1); |
|
982 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
983 break; |
|
984 } |
|
985 |
|
986 return RTL_R32(OCPDR) & OCPDR_DATA_MASK; |
|
987 } |
|
988 |
|
989 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
|
990 |
|
991 static void r8168dp_2_mdio_start(void __iomem *ioaddr) |
|
992 { |
|
993 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
|
994 } |
|
995 |
|
996 static void r8168dp_2_mdio_stop(void __iomem *ioaddr) |
|
997 { |
|
998 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
|
999 } |
|
1000 |
|
1001 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
1002 { |
|
1003 r8168dp_2_mdio_start(ioaddr); |
|
1004 |
|
1005 r8169_mdio_write(ioaddr, reg_addr, value); |
|
1006 |
|
1007 r8168dp_2_mdio_stop(ioaddr); |
|
1008 } |
|
1009 |
|
1010 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
1011 { |
|
1012 int value; |
|
1013 |
|
1014 r8168dp_2_mdio_start(ioaddr); |
|
1015 |
|
1016 value = r8169_mdio_read(ioaddr, reg_addr); |
|
1017 |
|
1018 r8168dp_2_mdio_stop(ioaddr); |
|
1019 |
|
1020 return value; |
|
1021 } |
|
1022 |
|
1023 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
|
1024 { |
|
1025 tp->mdio_ops.write(tp->mmio_addr, location, val); |
|
1026 } |
|
1027 |
|
1028 static int rtl_readphy(struct rtl8169_private *tp, int location) |
|
1029 { |
|
1030 return tp->mdio_ops.read(tp->mmio_addr, location); |
|
1031 } |
|
1032 |
|
1033 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) |
|
1034 { |
|
1035 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); |
|
1036 } |
|
1037 |
|
1038 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
|
1039 { |
|
1040 int val; |
|
1041 |
|
1042 val = rtl_readphy(tp, reg_addr); |
|
1043 rtl_writephy(tp, reg_addr, (val | p) & ~m); |
|
1044 } |
|
1045 |
|
1046 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
1047 int val) |
|
1048 { |
|
1049 struct rtl8169_private *tp = netdev_priv(dev); |
|
1050 |
|
1051 rtl_writephy(tp, location, val); |
|
1052 } |
|
1053 |
|
1054 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
1055 { |
|
1056 struct rtl8169_private *tp = netdev_priv(dev); |
|
1057 |
|
1058 return rtl_readphy(tp, location); |
|
1059 } |
|
1060 |
|
1061 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
1062 { |
|
1063 unsigned int i; |
|
1064 |
|
1065 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
1066 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1067 |
|
1068 for (i = 0; i < 100; i++) { |
|
1069 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
1070 break; |
|
1071 udelay(10); |
|
1072 } |
|
1073 } |
|
1074 |
|
1075 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
1076 { |
|
1077 u16 value = 0xffff; |
|
1078 unsigned int i; |
|
1079 |
|
1080 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1081 |
|
1082 for (i = 0; i < 100; i++) { |
|
1083 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
1084 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
1085 break; |
|
1086 } |
|
1087 udelay(10); |
|
1088 } |
|
1089 |
|
1090 return value; |
|
1091 } |
|
1092 |
|
1093 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
1094 { |
|
1095 unsigned int i; |
|
1096 |
|
1097 RTL_W32(CSIDR, value); |
|
1098 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
1099 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1100 |
|
1101 for (i = 0; i < 100; i++) { |
|
1102 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
1103 break; |
|
1104 udelay(10); |
|
1105 } |
|
1106 } |
|
1107 |
|
1108 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
1109 { |
|
1110 u32 value = ~0x00; |
|
1111 unsigned int i; |
|
1112 |
|
1113 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
1114 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1115 |
|
1116 for (i = 0; i < 100; i++) { |
|
1117 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
1118 value = RTL_R32(CSIDR); |
|
1119 break; |
|
1120 } |
|
1121 udelay(10); |
|
1122 } |
|
1123 |
|
1124 return value; |
|
1125 } |
|
1126 |
|
1127 static |
|
1128 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) |
|
1129 { |
|
1130 unsigned int i; |
|
1131 |
|
1132 BUG_ON((addr & 3) || (mask == 0)); |
|
1133 RTL_W32(ERIDR, val); |
|
1134 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); |
|
1135 |
|
1136 for (i = 0; i < 100; i++) { |
|
1137 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
1138 break; |
|
1139 udelay(100); |
|
1140 } |
|
1141 } |
|
1142 |
|
1143 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) |
|
1144 { |
|
1145 u32 value = ~0x00; |
|
1146 unsigned int i; |
|
1147 |
|
1148 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); |
|
1149 |
|
1150 for (i = 0; i < 100; i++) { |
|
1151 if (RTL_R32(ERIAR) & ERIAR_FLAG) { |
|
1152 value = RTL_R32(ERIDR); |
|
1153 break; |
|
1154 } |
|
1155 udelay(100); |
|
1156 } |
|
1157 |
|
1158 return value; |
|
1159 } |
|
1160 |
|
1161 static void |
|
1162 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) |
|
1163 { |
|
1164 u32 val; |
|
1165 |
|
1166 val = rtl_eri_read(ioaddr, addr, type); |
|
1167 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); |
|
1168 } |
|
1169 |
|
1170 struct exgmac_reg { |
|
1171 u16 addr; |
|
1172 u16 mask; |
|
1173 u32 val; |
|
1174 }; |
|
1175 |
|
1176 static void rtl_write_exgmac_batch(void __iomem *ioaddr, |
|
1177 const struct exgmac_reg *r, int len) |
|
1178 { |
|
1179 while (len-- > 0) { |
|
1180 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
|
1181 r++; |
|
1182 } |
|
1183 } |
|
1184 |
|
1185 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
|
1186 { |
|
1187 u8 value = 0xff; |
|
1188 unsigned int i; |
|
1189 |
|
1190 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
1191 |
|
1192 for (i = 0; i < 300; i++) { |
|
1193 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { |
|
1194 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; |
|
1195 break; |
|
1196 } |
|
1197 udelay(100); |
|
1198 } |
|
1199 |
|
1200 return value; |
|
1201 } |
|
1202 |
|
1203 static u16 rtl_get_events(struct rtl8169_private *tp) |
|
1204 { |
|
1205 void __iomem *ioaddr = tp->mmio_addr; |
|
1206 |
|
1207 return RTL_R16(IntrStatus); |
|
1208 } |
|
1209 |
|
1210 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) |
|
1211 { |
|
1212 void __iomem *ioaddr = tp->mmio_addr; |
|
1213 |
|
1214 RTL_W16(IntrStatus, bits); |
|
1215 mmiowb(); |
|
1216 } |
|
1217 |
|
1218 static void rtl_irq_disable(struct rtl8169_private *tp) |
|
1219 { |
|
1220 void __iomem *ioaddr = tp->mmio_addr; |
|
1221 |
|
1222 RTL_W16(IntrMask, 0); |
|
1223 mmiowb(); |
|
1224 } |
|
1225 |
|
1226 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
|
1227 { |
|
1228 void __iomem *ioaddr = tp->mmio_addr; |
|
1229 |
|
1230 RTL_W16(IntrMask, bits); |
|
1231 } |
|
1232 |
|
1233 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
|
1234 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) |
|
1235 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) |
|
1236 |
|
1237 static void rtl_irq_enable_all(struct rtl8169_private *tp) |
|
1238 { |
|
1239 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1240 } |
|
1241 |
|
1242 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
|
1243 { |
|
1244 void __iomem *ioaddr = tp->mmio_addr; |
|
1245 |
|
1246 rtl_irq_disable(tp); |
|
1247 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1248 RTL_R8(ChipCmd); |
|
1249 } |
|
1250 |
|
1251 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
|
1252 { |
|
1253 void __iomem *ioaddr = tp->mmio_addr; |
|
1254 |
|
1255 return RTL_R32(TBICSR) & TBIReset; |
|
1256 } |
|
1257 |
|
1258 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
|
1259 { |
|
1260 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
|
1261 } |
|
1262 |
|
1263 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
1264 { |
|
1265 return RTL_R32(TBICSR) & TBILinkOk; |
|
1266 } |
|
1267 |
|
1268 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
1269 { |
|
1270 return RTL_R8(PHYstatus) & LinkStatus; |
|
1271 } |
|
1272 |
|
1273 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
|
1274 { |
|
1275 void __iomem *ioaddr = tp->mmio_addr; |
|
1276 |
|
1277 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
1278 } |
|
1279 |
|
1280 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
|
1281 { |
|
1282 unsigned int val; |
|
1283 |
|
1284 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
|
1285 rtl_writephy(tp, MII_BMCR, val & 0xffff); |
|
1286 } |
|
1287 |
|
1288 static void rtl_link_chg_patch(struct rtl8169_private *tp) |
|
1289 { |
|
1290 void __iomem *ioaddr = tp->mmio_addr; |
|
1291 struct net_device *dev = tp->dev; |
|
1292 |
|
1293 if (!netif_running(dev)) |
|
1294 return; |
|
1295 |
|
1296 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
1297 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1298 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1299 0x00000011, ERIAR_EXGMAC); |
|
1300 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1301 0x00000005, ERIAR_EXGMAC); |
|
1302 } else if (RTL_R8(PHYstatus) & _100bps) { |
|
1303 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1304 0x0000001f, ERIAR_EXGMAC); |
|
1305 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1306 0x00000005, ERIAR_EXGMAC); |
|
1307 } else { |
|
1308 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1309 0x0000001f, ERIAR_EXGMAC); |
|
1310 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1311 0x0000003f, ERIAR_EXGMAC); |
|
1312 } |
|
1313 /* Reset packet filter */ |
|
1314 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
|
1315 ERIAR_EXGMAC); |
|
1316 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
|
1317 ERIAR_EXGMAC); |
|
1318 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
1319 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
1320 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1321 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1322 0x00000011, ERIAR_EXGMAC); |
|
1323 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1324 0x00000005, ERIAR_EXGMAC); |
|
1325 } else { |
|
1326 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1327 0x0000001f, ERIAR_EXGMAC); |
|
1328 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1329 0x0000003f, ERIAR_EXGMAC); |
|
1330 } |
|
1331 } |
|
1332 } |
|
1333 |
|
1334 static void __rtl8169_check_link_status(struct net_device *dev, |
|
1335 struct rtl8169_private *tp, |
|
1336 void __iomem *ioaddr, bool pm) |
|
1337 { |
|
1338 if (tp->ecdev) { |
|
1339 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
1340 return; |
|
1341 } |
|
1342 |
|
1343 if (tp->link_ok(ioaddr)) { |
|
1344 rtl_link_chg_patch(tp); |
|
1345 /* This is to cancel a scheduled suspend if there's one. */ |
|
1346 if (pm) |
|
1347 pm_request_resume(&tp->pci_dev->dev); |
|
1348 netif_carrier_on(dev); |
|
1349 if (net_ratelimit()) |
|
1350 netif_info(tp, ifup, dev, "link up\n"); |
|
1351 } else { |
|
1352 netif_carrier_off(dev); |
|
1353 netif_info(tp, ifdown, dev, "link down\n"); |
|
1354 if (pm) |
|
1355 pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
|
1356 } |
|
1357 } |
|
1358 |
|
1359 static void rtl8169_check_link_status(struct net_device *dev, |
|
1360 struct rtl8169_private *tp, |
|
1361 void __iomem *ioaddr) |
|
1362 { |
|
1363 __rtl8169_check_link_status(dev, tp, ioaddr, false); |
|
1364 } |
|
1365 |
|
1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
1367 |
|
1368 static u32 __rtl8169_get_wol(struct rtl8169_private *tp) |
|
1369 { |
|
1370 void __iomem *ioaddr = tp->mmio_addr; |
|
1371 u8 options; |
|
1372 u32 wolopts = 0; |
|
1373 |
|
1374 options = RTL_R8(Config1); |
|
1375 if (!(options & PMEnable)) |
|
1376 return 0; |
|
1377 |
|
1378 options = RTL_R8(Config3); |
|
1379 if (options & LinkUp) |
|
1380 wolopts |= WAKE_PHY; |
|
1381 if (options & MagicPacket) |
|
1382 wolopts |= WAKE_MAGIC; |
|
1383 |
|
1384 options = RTL_R8(Config5); |
|
1385 if (options & UWF) |
|
1386 wolopts |= WAKE_UCAST; |
|
1387 if (options & BWF) |
|
1388 wolopts |= WAKE_BCAST; |
|
1389 if (options & MWF) |
|
1390 wolopts |= WAKE_MCAST; |
|
1391 |
|
1392 return wolopts; |
|
1393 } |
|
1394 |
|
1395 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1396 { |
|
1397 struct rtl8169_private *tp = netdev_priv(dev); |
|
1398 |
|
1399 rtl_lock_work(tp); |
|
1400 |
|
1401 wol->supported = WAKE_ANY; |
|
1402 wol->wolopts = __rtl8169_get_wol(tp); |
|
1403 |
|
1404 rtl_unlock_work(tp); |
|
1405 } |
|
1406 |
|
1407 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) |
|
1408 { |
|
1409 void __iomem *ioaddr = tp->mmio_addr; |
|
1410 unsigned int i; |
|
1411 static const struct { |
|
1412 u32 opt; |
|
1413 u16 reg; |
|
1414 u8 mask; |
|
1415 } cfg[] = { |
|
1416 { WAKE_PHY, Config3, LinkUp }, |
|
1417 { WAKE_MAGIC, Config3, MagicPacket }, |
|
1418 { WAKE_UCAST, Config5, UWF }, |
|
1419 { WAKE_BCAST, Config5, BWF }, |
|
1420 { WAKE_MCAST, Config5, MWF }, |
|
1421 { WAKE_ANY, Config5, LanWake } |
|
1422 }; |
|
1423 u8 options; |
|
1424 |
|
1425 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1426 |
|
1427 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
1428 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
1429 if (wolopts & cfg[i].opt) |
|
1430 options |= cfg[i].mask; |
|
1431 RTL_W8(cfg[i].reg, options); |
|
1432 } |
|
1433 |
|
1434 switch (tp->mac_version) { |
|
1435 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: |
|
1436 options = RTL_R8(Config1) & ~PMEnable; |
|
1437 if (wolopts) |
|
1438 options |= PMEnable; |
|
1439 RTL_W8(Config1, options); |
|
1440 break; |
|
1441 default: |
|
1442 options = RTL_R8(Config2) & ~PME_SIGNAL; |
|
1443 if (wolopts) |
|
1444 options |= PME_SIGNAL; |
|
1445 RTL_W8(Config2, options); |
|
1446 break; |
|
1447 } |
|
1448 |
|
1449 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1450 } |
|
1451 |
|
1452 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1453 { |
|
1454 struct rtl8169_private *tp = netdev_priv(dev); |
|
1455 |
|
1456 rtl_lock_work(tp); |
|
1457 |
|
1458 if (wol->wolopts) |
|
1459 tp->features |= RTL_FEATURE_WOL; |
|
1460 else |
|
1461 tp->features &= ~RTL_FEATURE_WOL; |
|
1462 __rtl8169_set_wol(tp, wol->wolopts); |
|
1463 |
|
1464 rtl_unlock_work(tp); |
|
1465 |
|
1466 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
1467 |
|
1468 return 0; |
|
1469 } |
|
1470 |
|
1471 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
|
1472 { |
|
1473 return rtl_chip_infos[tp->mac_version].fw_name; |
|
1474 } |
|
1475 |
|
1476 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
1477 struct ethtool_drvinfo *info) |
|
1478 { |
|
1479 struct rtl8169_private *tp = netdev_priv(dev); |
|
1480 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
1481 |
|
1482 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
|
1483 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); |
|
1484 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
|
1485 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
|
1486 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
1487 strlcpy(info->fw_version, rtl_fw->version, |
|
1488 sizeof(info->fw_version)); |
|
1489 } |
|
1490 |
|
1491 static int rtl8169_get_regs_len(struct net_device *dev) |
|
1492 { |
|
1493 return R8169_REGS_SIZE; |
|
1494 } |
|
1495 |
|
1496 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
1497 u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
|
1498 { |
|
1499 struct rtl8169_private *tp = netdev_priv(dev); |
|
1500 void __iomem *ioaddr = tp->mmio_addr; |
|
1501 int ret = 0; |
|
1502 u32 reg; |
|
1503 |
|
1504 reg = RTL_R32(TBICSR); |
|
1505 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
1506 (duplex == DUPLEX_FULL)) { |
|
1507 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
1508 } else if (autoneg == AUTONEG_ENABLE) |
|
1509 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
1510 else { |
|
1511 netif_warn(tp, link, dev, |
|
1512 "incorrect speed setting refused in TBI mode\n"); |
|
1513 ret = -EOPNOTSUPP; |
|
1514 } |
|
1515 |
|
1516 return ret; |
|
1517 } |
|
1518 |
|
1519 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
1520 u8 autoneg, u16 speed, u8 duplex, u32 adv) |
|
1521 { |
|
1522 struct rtl8169_private *tp = netdev_priv(dev); |
|
1523 int giga_ctrl, bmcr; |
|
1524 int rc = -EINVAL; |
|
1525 |
|
1526 rtl_writephy(tp, 0x1f, 0x0000); |
|
1527 |
|
1528 if (autoneg == AUTONEG_ENABLE) { |
|
1529 int auto_nego; |
|
1530 |
|
1531 auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
|
1532 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
1533 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
1534 |
|
1535 if (adv & ADVERTISED_10baseT_Half) |
|
1536 auto_nego |= ADVERTISE_10HALF; |
|
1537 if (adv & ADVERTISED_10baseT_Full) |
|
1538 auto_nego |= ADVERTISE_10FULL; |
|
1539 if (adv & ADVERTISED_100baseT_Half) |
|
1540 auto_nego |= ADVERTISE_100HALF; |
|
1541 if (adv & ADVERTISED_100baseT_Full) |
|
1542 auto_nego |= ADVERTISE_100FULL; |
|
1543 |
|
1544 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
1545 |
|
1546 giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
|
1547 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
1548 |
|
1549 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
1550 if (tp->mii.supports_gmii) { |
|
1551 if (adv & ADVERTISED_1000baseT_Half) |
|
1552 giga_ctrl |= ADVERTISE_1000HALF; |
|
1553 if (adv & ADVERTISED_1000baseT_Full) |
|
1554 giga_ctrl |= ADVERTISE_1000FULL; |
|
1555 } else if (adv & (ADVERTISED_1000baseT_Half | |
|
1556 ADVERTISED_1000baseT_Full)) { |
|
1557 netif_info(tp, link, dev, |
|
1558 "PHY does not support 1000Mbps\n"); |
|
1559 goto out; |
|
1560 } |
|
1561 |
|
1562 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
1563 |
|
1564 rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
|
1565 rtl_writephy(tp, MII_CTRL1000, giga_ctrl); |
|
1566 } else { |
|
1567 giga_ctrl = 0; |
|
1568 |
|
1569 if (speed == SPEED_10) |
|
1570 bmcr = 0; |
|
1571 else if (speed == SPEED_100) |
|
1572 bmcr = BMCR_SPEED100; |
|
1573 else |
|
1574 goto out; |
|
1575 |
|
1576 if (duplex == DUPLEX_FULL) |
|
1577 bmcr |= BMCR_FULLDPLX; |
|
1578 } |
|
1579 |
|
1580 rtl_writephy(tp, MII_BMCR, bmcr); |
|
1581 |
|
1582 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
1583 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
1584 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
1585 rtl_writephy(tp, 0x17, 0x2138); |
|
1586 rtl_writephy(tp, 0x0e, 0x0260); |
|
1587 } else { |
|
1588 rtl_writephy(tp, 0x17, 0x2108); |
|
1589 rtl_writephy(tp, 0x0e, 0x0000); |
|
1590 } |
|
1591 } |
|
1592 |
|
1593 rc = 0; |
|
1594 out: |
|
1595 return rc; |
|
1596 } |
|
1597 |
|
1598 static int rtl8169_set_speed(struct net_device *dev, |
|
1599 u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
|
1600 { |
|
1601 struct rtl8169_private *tp = netdev_priv(dev); |
|
1602 int ret; |
|
1603 |
|
1604 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
|
1605 if (ret < 0) |
|
1606 goto out; |
|
1607 |
|
1608 if (!tp->ecdev && netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
|
1609 (advertising & ADVERTISED_1000baseT_Full)) { |
|
1610 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1611 } |
|
1612 out: |
|
1613 return ret; |
|
1614 } |
|
1615 |
|
1616 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1617 { |
|
1618 struct rtl8169_private *tp = netdev_priv(dev); |
|
1619 int ret; |
|
1620 |
|
1621 if (!tp->ecdev) { |
|
1622 del_timer_sync(&tp->timer); |
|
1623 } |
|
1624 |
|
1625 rtl_lock_work(tp); |
|
1626 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
|
1627 cmd->duplex, cmd->advertising); |
|
1628 rtl_unlock_work(tp); |
|
1629 |
|
1630 return ret; |
|
1631 } |
|
1632 |
|
1633 static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
|
1634 netdev_features_t features) |
|
1635 { |
|
1636 struct rtl8169_private *tp = netdev_priv(dev); |
|
1637 |
|
1638 if (dev->mtu > TD_MSS_MAX) |
|
1639 features &= ~NETIF_F_ALL_TSO; |
|
1640 |
|
1641 if (dev->mtu > JUMBO_1K && |
|
1642 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) |
|
1643 features &= ~NETIF_F_IP_CSUM; |
|
1644 |
|
1645 return features; |
|
1646 } |
|
1647 |
|
1648 static void __rtl8169_set_features(struct net_device *dev, |
|
1649 netdev_features_t features) |
|
1650 { |
|
1651 struct rtl8169_private *tp = netdev_priv(dev); |
|
1652 netdev_features_t changed = features ^ dev->features; |
|
1653 void __iomem *ioaddr = tp->mmio_addr; |
|
1654 |
|
1655 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX))) |
|
1656 return; |
|
1657 |
|
1658 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) { |
|
1659 if (features & NETIF_F_RXCSUM) |
|
1660 tp->cp_cmd |= RxChkSum; |
|
1661 else |
|
1662 tp->cp_cmd &= ~RxChkSum; |
|
1663 |
|
1664 if (dev->features & NETIF_F_HW_VLAN_RX) |
|
1665 tp->cp_cmd |= RxVlan; |
|
1666 else |
|
1667 tp->cp_cmd &= ~RxVlan; |
|
1668 |
|
1669 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1670 RTL_R16(CPlusCmd); |
|
1671 } |
|
1672 if (changed & NETIF_F_RXALL) { |
|
1673 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt)); |
|
1674 if (features & NETIF_F_RXALL) |
|
1675 tmp |= (AcceptErr | AcceptRunt); |
|
1676 RTL_W32(RxConfig, tmp); |
|
1677 } |
|
1678 } |
|
1679 |
|
1680 static int rtl8169_set_features(struct net_device *dev, |
|
1681 netdev_features_t features) |
|
1682 { |
|
1683 struct rtl8169_private *tp = netdev_priv(dev); |
|
1684 |
|
1685 rtl_lock_work(tp); |
|
1686 __rtl8169_set_features(dev, features); |
|
1687 rtl_unlock_work(tp); |
|
1688 |
|
1689 return 0; |
|
1690 } |
|
1691 |
|
1692 |
|
1693 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1694 struct sk_buff *skb) |
|
1695 { |
|
1696 return (vlan_tx_tag_present(skb)) ? |
|
1697 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1698 } |
|
1699 |
|
1700 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
|
1701 { |
|
1702 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1703 |
|
1704 if (opts2 & RxVlanTag) |
|
1705 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); |
|
1706 |
|
1707 desc->opts2 = 0; |
|
1708 } |
|
1709 |
|
1710 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1711 { |
|
1712 struct rtl8169_private *tp = netdev_priv(dev); |
|
1713 void __iomem *ioaddr = tp->mmio_addr; |
|
1714 u32 status; |
|
1715 |
|
1716 cmd->supported = |
|
1717 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1718 cmd->port = PORT_FIBRE; |
|
1719 cmd->transceiver = XCVR_INTERNAL; |
|
1720 |
|
1721 status = RTL_R32(TBICSR); |
|
1722 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1723 cmd->autoneg = !!(status & TBINwEnable); |
|
1724 |
|
1725 ethtool_cmd_speed_set(cmd, SPEED_1000); |
|
1726 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1727 |
|
1728 return 0; |
|
1729 } |
|
1730 |
|
1731 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1732 { |
|
1733 struct rtl8169_private *tp = netdev_priv(dev); |
|
1734 |
|
1735 return mii_ethtool_gset(&tp->mii, cmd); |
|
1736 } |
|
1737 |
|
1738 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1739 { |
|
1740 struct rtl8169_private *tp = netdev_priv(dev); |
|
1741 int rc; |
|
1742 |
|
1743 rtl_lock_work(tp); |
|
1744 rc = tp->get_settings(dev, cmd); |
|
1745 rtl_unlock_work(tp); |
|
1746 |
|
1747 return rc; |
|
1748 } |
|
1749 |
|
1750 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1751 void *p) |
|
1752 { |
|
1753 struct rtl8169_private *tp = netdev_priv(dev); |
|
1754 |
|
1755 if (regs->len > R8169_REGS_SIZE) |
|
1756 regs->len = R8169_REGS_SIZE; |
|
1757 |
|
1758 rtl_lock_work(tp); |
|
1759 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1760 rtl_unlock_work(tp); |
|
1761 } |
|
1762 |
|
1763 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1764 { |
|
1765 struct rtl8169_private *tp = netdev_priv(dev); |
|
1766 |
|
1767 return tp->msg_enable; |
|
1768 } |
|
1769 |
|
1770 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1771 { |
|
1772 struct rtl8169_private *tp = netdev_priv(dev); |
|
1773 |
|
1774 tp->msg_enable = value; |
|
1775 } |
|
1776 |
|
1777 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1778 "tx_packets", |
|
1779 "rx_packets", |
|
1780 "tx_errors", |
|
1781 "rx_errors", |
|
1782 "rx_missed", |
|
1783 "align_errors", |
|
1784 "tx_single_collisions", |
|
1785 "tx_multi_collisions", |
|
1786 "unicast", |
|
1787 "broadcast", |
|
1788 "multicast", |
|
1789 "tx_aborted", |
|
1790 "tx_underrun", |
|
1791 }; |
|
1792 |
|
1793 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1794 { |
|
1795 switch (sset) { |
|
1796 case ETH_SS_STATS: |
|
1797 return ARRAY_SIZE(rtl8169_gstrings); |
|
1798 default: |
|
1799 return -EOPNOTSUPP; |
|
1800 } |
|
1801 } |
|
1802 |
|
1803 static void rtl8169_update_counters(struct net_device *dev) |
|
1804 { |
|
1805 struct rtl8169_private *tp = netdev_priv(dev); |
|
1806 void __iomem *ioaddr = tp->mmio_addr; |
|
1807 struct device *d = &tp->pci_dev->dev; |
|
1808 struct rtl8169_counters *counters; |
|
1809 dma_addr_t paddr; |
|
1810 u32 cmd; |
|
1811 int wait = 1000; |
|
1812 |
|
1813 /* |
|
1814 * Some chips are unable to dump tally counters when the receiver |
|
1815 * is disabled. |
|
1816 */ |
|
1817 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1818 return; |
|
1819 |
|
1820 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
|
1821 if (!counters) |
|
1822 return; |
|
1823 |
|
1824 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1825 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1826 RTL_W32(CounterAddrLow, cmd); |
|
1827 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1828 |
|
1829 while (wait--) { |
|
1830 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1831 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1832 break; |
|
1833 } |
|
1834 udelay(10); |
|
1835 } |
|
1836 |
|
1837 RTL_W32(CounterAddrLow, 0); |
|
1838 RTL_W32(CounterAddrHigh, 0); |
|
1839 |
|
1840 dma_free_coherent(d, sizeof(*counters), counters, paddr); |
|
1841 } |
|
1842 |
|
1843 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1844 struct ethtool_stats *stats, u64 *data) |
|
1845 { |
|
1846 struct rtl8169_private *tp = netdev_priv(dev); |
|
1847 |
|
1848 ASSERT_RTNL(); |
|
1849 |
|
1850 rtl8169_update_counters(dev); |
|
1851 |
|
1852 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1853 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1854 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1855 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1856 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1857 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1858 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1859 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1860 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1861 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1862 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1863 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1864 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1865 } |
|
1866 |
|
1867 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1868 { |
|
1869 switch(stringset) { |
|
1870 case ETH_SS_STATS: |
|
1871 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1872 break; |
|
1873 } |
|
1874 } |
|
1875 |
|
1876 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1877 .get_drvinfo = rtl8169_get_drvinfo, |
|
1878 .get_regs_len = rtl8169_get_regs_len, |
|
1879 .get_link = ethtool_op_get_link, |
|
1880 .get_settings = rtl8169_get_settings, |
|
1881 .set_settings = rtl8169_set_settings, |
|
1882 .get_msglevel = rtl8169_get_msglevel, |
|
1883 .set_msglevel = rtl8169_set_msglevel, |
|
1884 .get_regs = rtl8169_get_regs, |
|
1885 .get_wol = rtl8169_get_wol, |
|
1886 .set_wol = rtl8169_set_wol, |
|
1887 .get_strings = rtl8169_get_strings, |
|
1888 .get_sset_count = rtl8169_get_sset_count, |
|
1889 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1890 }; |
|
1891 |
|
1892 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1893 struct net_device *dev, u8 default_version) |
|
1894 { |
|
1895 void __iomem *ioaddr = tp->mmio_addr; |
|
1896 /* |
|
1897 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1898 * but they can be identified more specifically through the test below |
|
1899 * if needed: |
|
1900 * |
|
1901 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1902 * |
|
1903 * Same thing for the 8101Eb and the 8101Ec: |
|
1904 * |
|
1905 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1906 */ |
|
1907 static const struct rtl_mac_info { |
|
1908 u32 mask; |
|
1909 u32 val; |
|
1910 int mac_version; |
|
1911 } mac_info[] = { |
|
1912 /* 8168F family. */ |
|
1913 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
|
1914 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, |
|
1915 |
|
1916 /* 8168E family. */ |
|
1917 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
|
1918 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
|
1919 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, |
|
1920 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, |
|
1921 |
|
1922 /* 8168D family. */ |
|
1923 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
1924 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
1925 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
1926 |
|
1927 /* 8168DP family. */ |
|
1928 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
1929 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, |
|
1930 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
|
1931 |
|
1932 /* 8168C family. */ |
|
1933 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
|
1934 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1935 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1936 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1937 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1938 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1939 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1940 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1941 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1942 |
|
1943 /* 8168B family. */ |
|
1944 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1945 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1946 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1947 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1948 |
|
1949 /* 8101 family. */ |
|
1950 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
|
1951 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
|
1952 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, |
|
1953 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, |
|
1954 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1955 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1956 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1957 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1958 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1959 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1960 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1961 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1962 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1963 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1964 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1965 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1966 /* FIXME: where did these entries come from ? -- FR */ |
|
1967 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1968 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1969 |
|
1970 /* 8110 family. */ |
|
1971 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1972 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1973 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1974 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1975 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1976 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1977 |
|
1978 /* Catch-all */ |
|
1979 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1980 }; |
|
1981 const struct rtl_mac_info *p = mac_info; |
|
1982 u32 reg; |
|
1983 |
|
1984 reg = RTL_R32(TxConfig); |
|
1985 while ((reg & p->mask) != p->val) |
|
1986 p++; |
|
1987 tp->mac_version = p->mac_version; |
|
1988 |
|
1989 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
1990 netif_notice(tp, probe, dev, |
|
1991 "unknown MAC, using family default\n"); |
|
1992 tp->mac_version = default_version; |
|
1993 } |
|
1994 } |
|
1995 |
|
1996 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1997 { |
|
1998 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1999 } |
|
2000 |
|
2001 struct phy_reg { |
|
2002 u16 reg; |
|
2003 u16 val; |
|
2004 }; |
|
2005 |
|
2006 static void rtl_writephy_batch(struct rtl8169_private *tp, |
|
2007 const struct phy_reg *regs, int len) |
|
2008 { |
|
2009 while (len-- > 0) { |
|
2010 rtl_writephy(tp, regs->reg, regs->val); |
|
2011 regs++; |
|
2012 } |
|
2013 } |
|
2014 |
|
2015 #define PHY_READ 0x00000000 |
|
2016 #define PHY_DATA_OR 0x10000000 |
|
2017 #define PHY_DATA_AND 0x20000000 |
|
2018 #define PHY_BJMPN 0x30000000 |
|
2019 #define PHY_READ_EFUSE 0x40000000 |
|
2020 #define PHY_READ_MAC_BYTE 0x50000000 |
|
2021 #define PHY_WRITE_MAC_BYTE 0x60000000 |
|
2022 #define PHY_CLEAR_READCOUNT 0x70000000 |
|
2023 #define PHY_WRITE 0x80000000 |
|
2024 #define PHY_READCOUNT_EQ_SKIP 0x90000000 |
|
2025 #define PHY_COMP_EQ_SKIPN 0xa0000000 |
|
2026 #define PHY_COMP_NEQ_SKIPN 0xb0000000 |
|
2027 #define PHY_WRITE_PREVIOUS 0xc0000000 |
|
2028 #define PHY_SKIPN 0xd0000000 |
|
2029 #define PHY_DELAY_MS 0xe0000000 |
|
2030 #define PHY_WRITE_ERI_WORD 0xf0000000 |
|
2031 |
|
2032 struct fw_info { |
|
2033 u32 magic; |
|
2034 char version[RTL_VER_SIZE]; |
|
2035 __le32 fw_start; |
|
2036 __le32 fw_len; |
|
2037 u8 chksum; |
|
2038 } __packed; |
|
2039 |
|
2040 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
|
2041 |
|
2042 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2043 { |
|
2044 const struct firmware *fw = rtl_fw->fw; |
|
2045 struct fw_info *fw_info = (struct fw_info *)fw->data; |
|
2046 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2047 char *version = rtl_fw->version; |
|
2048 bool rc = false; |
|
2049 |
|
2050 if (fw->size < FW_OPCODE_SIZE) |
|
2051 goto out; |
|
2052 |
|
2053 if (!fw_info->magic) { |
|
2054 size_t i, size, start; |
|
2055 u8 checksum = 0; |
|
2056 |
|
2057 if (fw->size < sizeof(*fw_info)) |
|
2058 goto out; |
|
2059 |
|
2060 for (i = 0; i < fw->size; i++) |
|
2061 checksum += fw->data[i]; |
|
2062 if (checksum != 0) |
|
2063 goto out; |
|
2064 |
|
2065 start = le32_to_cpu(fw_info->fw_start); |
|
2066 if (start > fw->size) |
|
2067 goto out; |
|
2068 |
|
2069 size = le32_to_cpu(fw_info->fw_len); |
|
2070 if (size > (fw->size - start) / FW_OPCODE_SIZE) |
|
2071 goto out; |
|
2072 |
|
2073 memcpy(version, fw_info->version, RTL_VER_SIZE); |
|
2074 |
|
2075 pa->code = (__le32 *)(fw->data + start); |
|
2076 pa->size = size; |
|
2077 } else { |
|
2078 if (fw->size % FW_OPCODE_SIZE) |
|
2079 goto out; |
|
2080 |
|
2081 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); |
|
2082 |
|
2083 pa->code = (__le32 *)fw->data; |
|
2084 pa->size = fw->size / FW_OPCODE_SIZE; |
|
2085 } |
|
2086 version[RTL_VER_SIZE - 1] = 0; |
|
2087 |
|
2088 rc = true; |
|
2089 out: |
|
2090 return rc; |
|
2091 } |
|
2092 |
|
2093 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
|
2094 struct rtl_fw_phy_action *pa) |
|
2095 { |
|
2096 bool rc = false; |
|
2097 size_t index; |
|
2098 |
|
2099 for (index = 0; index < pa->size; index++) { |
|
2100 u32 action = le32_to_cpu(pa->code[index]); |
|
2101 u32 regno = (action & 0x0fff0000) >> 16; |
|
2102 |
|
2103 switch(action & 0xf0000000) { |
|
2104 case PHY_READ: |
|
2105 case PHY_DATA_OR: |
|
2106 case PHY_DATA_AND: |
|
2107 case PHY_READ_EFUSE: |
|
2108 case PHY_CLEAR_READCOUNT: |
|
2109 case PHY_WRITE: |
|
2110 case PHY_WRITE_PREVIOUS: |
|
2111 case PHY_DELAY_MS: |
|
2112 break; |
|
2113 |
|
2114 case PHY_BJMPN: |
|
2115 if (regno > index) { |
|
2116 netif_err(tp, ifup, tp->dev, |
|
2117 "Out of range of firmware\n"); |
|
2118 goto out; |
|
2119 } |
|
2120 break; |
|
2121 case PHY_READCOUNT_EQ_SKIP: |
|
2122 if (index + 2 >= pa->size) { |
|
2123 netif_err(tp, ifup, tp->dev, |
|
2124 "Out of range of firmware\n"); |
|
2125 goto out; |
|
2126 } |
|
2127 break; |
|
2128 case PHY_COMP_EQ_SKIPN: |
|
2129 case PHY_COMP_NEQ_SKIPN: |
|
2130 case PHY_SKIPN: |
|
2131 if (index + 1 + regno >= pa->size) { |
|
2132 netif_err(tp, ifup, tp->dev, |
|
2133 "Out of range of firmware\n"); |
|
2134 goto out; |
|
2135 } |
|
2136 break; |
|
2137 |
|
2138 case PHY_READ_MAC_BYTE: |
|
2139 case PHY_WRITE_MAC_BYTE: |
|
2140 case PHY_WRITE_ERI_WORD: |
|
2141 default: |
|
2142 netif_err(tp, ifup, tp->dev, |
|
2143 "Invalid action 0x%08x\n", action); |
|
2144 goto out; |
|
2145 } |
|
2146 } |
|
2147 rc = true; |
|
2148 out: |
|
2149 return rc; |
|
2150 } |
|
2151 |
|
2152 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2153 { |
|
2154 struct net_device *dev = tp->dev; |
|
2155 int rc = -EINVAL; |
|
2156 |
|
2157 if (!rtl_fw_format_ok(tp, rtl_fw)) { |
|
2158 netif_err(tp, ifup, dev, "invalid firwmare\n"); |
|
2159 goto out; |
|
2160 } |
|
2161 |
|
2162 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) |
|
2163 rc = 0; |
|
2164 out: |
|
2165 return rc; |
|
2166 } |
|
2167 |
|
2168 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2169 { |
|
2170 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2171 u32 predata, count; |
|
2172 size_t index; |
|
2173 |
|
2174 predata = count = 0; |
|
2175 |
|
2176 for (index = 0; index < pa->size; ) { |
|
2177 u32 action = le32_to_cpu(pa->code[index]); |
|
2178 u32 data = action & 0x0000ffff; |
|
2179 u32 regno = (action & 0x0fff0000) >> 16; |
|
2180 |
|
2181 if (!action) |
|
2182 break; |
|
2183 |
|
2184 switch(action & 0xf0000000) { |
|
2185 case PHY_READ: |
|
2186 predata = rtl_readphy(tp, regno); |
|
2187 count++; |
|
2188 index++; |
|
2189 break; |
|
2190 case PHY_DATA_OR: |
|
2191 predata |= data; |
|
2192 index++; |
|
2193 break; |
|
2194 case PHY_DATA_AND: |
|
2195 predata &= data; |
|
2196 index++; |
|
2197 break; |
|
2198 case PHY_BJMPN: |
|
2199 index -= regno; |
|
2200 break; |
|
2201 case PHY_READ_EFUSE: |
|
2202 predata = rtl8168d_efuse_read(tp->mmio_addr, regno); |
|
2203 index++; |
|
2204 break; |
|
2205 case PHY_CLEAR_READCOUNT: |
|
2206 count = 0; |
|
2207 index++; |
|
2208 break; |
|
2209 case PHY_WRITE: |
|
2210 rtl_writephy(tp, regno, data); |
|
2211 index++; |
|
2212 break; |
|
2213 case PHY_READCOUNT_EQ_SKIP: |
|
2214 index += (count == data) ? 2 : 1; |
|
2215 break; |
|
2216 case PHY_COMP_EQ_SKIPN: |
|
2217 if (predata == data) |
|
2218 index += regno; |
|
2219 index++; |
|
2220 break; |
|
2221 case PHY_COMP_NEQ_SKIPN: |
|
2222 if (predata != data) |
|
2223 index += regno; |
|
2224 index++; |
|
2225 break; |
|
2226 case PHY_WRITE_PREVIOUS: |
|
2227 rtl_writephy(tp, regno, predata); |
|
2228 index++; |
|
2229 break; |
|
2230 case PHY_SKIPN: |
|
2231 index += regno + 1; |
|
2232 break; |
|
2233 case PHY_DELAY_MS: |
|
2234 mdelay(data); |
|
2235 index++; |
|
2236 break; |
|
2237 |
|
2238 case PHY_READ_MAC_BYTE: |
|
2239 case PHY_WRITE_MAC_BYTE: |
|
2240 case PHY_WRITE_ERI_WORD: |
|
2241 default: |
|
2242 BUG(); |
|
2243 } |
|
2244 } |
|
2245 } |
|
2246 |
|
2247 static void rtl_release_firmware(struct rtl8169_private *tp) |
|
2248 { |
|
2249 if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
|
2250 release_firmware(tp->rtl_fw->fw); |
|
2251 kfree(tp->rtl_fw); |
|
2252 } |
|
2253 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
2254 } |
|
2255 |
|
2256 static void rtl_apply_firmware(struct rtl8169_private *tp) |
|
2257 { |
|
2258 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
2259 |
|
2260 /* TODO: release firmware once rtl_phy_write_fw signals failures. */ |
|
2261 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
2262 rtl_phy_write_fw(tp, rtl_fw); |
|
2263 } |
|
2264 |
|
2265 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) |
|
2266 { |
|
2267 if (rtl_readphy(tp, reg) != val) |
|
2268 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); |
|
2269 else |
|
2270 rtl_apply_firmware(tp); |
|
2271 } |
|
2272 |
|
2273 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
|
2274 { |
|
2275 static const struct phy_reg phy_reg_init[] = { |
|
2276 { 0x1f, 0x0001 }, |
|
2277 { 0x06, 0x006e }, |
|
2278 { 0x08, 0x0708 }, |
|
2279 { 0x15, 0x4000 }, |
|
2280 { 0x18, 0x65c7 }, |
|
2281 |
|
2282 { 0x1f, 0x0001 }, |
|
2283 { 0x03, 0x00a1 }, |
|
2284 { 0x02, 0x0008 }, |
|
2285 { 0x01, 0x0120 }, |
|
2286 { 0x00, 0x1000 }, |
|
2287 { 0x04, 0x0800 }, |
|
2288 { 0x04, 0x0000 }, |
|
2289 |
|
2290 { 0x03, 0xff41 }, |
|
2291 { 0x02, 0xdf60 }, |
|
2292 { 0x01, 0x0140 }, |
|
2293 { 0x00, 0x0077 }, |
|
2294 { 0x04, 0x7800 }, |
|
2295 { 0x04, 0x7000 }, |
|
2296 |
|
2297 { 0x03, 0x802f }, |
|
2298 { 0x02, 0x4f02 }, |
|
2299 { 0x01, 0x0409 }, |
|
2300 { 0x00, 0xf0f9 }, |
|
2301 { 0x04, 0x9800 }, |
|
2302 { 0x04, 0x9000 }, |
|
2303 |
|
2304 { 0x03, 0xdf01 }, |
|
2305 { 0x02, 0xdf20 }, |
|
2306 { 0x01, 0xff95 }, |
|
2307 { 0x00, 0xba00 }, |
|
2308 { 0x04, 0xa800 }, |
|
2309 { 0x04, 0xa000 }, |
|
2310 |
|
2311 { 0x03, 0xff41 }, |
|
2312 { 0x02, 0xdf20 }, |
|
2313 { 0x01, 0x0140 }, |
|
2314 { 0x00, 0x00bb }, |
|
2315 { 0x04, 0xb800 }, |
|
2316 { 0x04, 0xb000 }, |
|
2317 |
|
2318 { 0x03, 0xdf41 }, |
|
2319 { 0x02, 0xdc60 }, |
|
2320 { 0x01, 0x6340 }, |
|
2321 { 0x00, 0x007d }, |
|
2322 { 0x04, 0xd800 }, |
|
2323 { 0x04, 0xd000 }, |
|
2324 |
|
2325 { 0x03, 0xdf01 }, |
|
2326 { 0x02, 0xdf20 }, |
|
2327 { 0x01, 0x100a }, |
|
2328 { 0x00, 0xa0ff }, |
|
2329 { 0x04, 0xf800 }, |
|
2330 { 0x04, 0xf000 }, |
|
2331 |
|
2332 { 0x1f, 0x0000 }, |
|
2333 { 0x0b, 0x0000 }, |
|
2334 { 0x00, 0x9200 } |
|
2335 }; |
|
2336 |
|
2337 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2338 } |
|
2339 |
|
2340 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
|
2341 { |
|
2342 static const struct phy_reg phy_reg_init[] = { |
|
2343 { 0x1f, 0x0002 }, |
|
2344 { 0x01, 0x90d0 }, |
|
2345 { 0x1f, 0x0000 } |
|
2346 }; |
|
2347 |
|
2348 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2349 } |
|
2350 |
|
2351 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
|
2352 { |
|
2353 struct pci_dev *pdev = tp->pci_dev; |
|
2354 |
|
2355 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
|
2356 (pdev->subsystem_device != 0xe000)) |
|
2357 return; |
|
2358 |
|
2359 rtl_writephy(tp, 0x1f, 0x0001); |
|
2360 rtl_writephy(tp, 0x10, 0xf01b); |
|
2361 rtl_writephy(tp, 0x1f, 0x0000); |
|
2362 } |
|
2363 |
|
2364 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
|
2365 { |
|
2366 static const struct phy_reg phy_reg_init[] = { |
|
2367 { 0x1f, 0x0001 }, |
|
2368 { 0x04, 0x0000 }, |
|
2369 { 0x03, 0x00a1 }, |
|
2370 { 0x02, 0x0008 }, |
|
2371 { 0x01, 0x0120 }, |
|
2372 { 0x00, 0x1000 }, |
|
2373 { 0x04, 0x0800 }, |
|
2374 { 0x04, 0x9000 }, |
|
2375 { 0x03, 0x802f }, |
|
2376 { 0x02, 0x4f02 }, |
|
2377 { 0x01, 0x0409 }, |
|
2378 { 0x00, 0xf099 }, |
|
2379 { 0x04, 0x9800 }, |
|
2380 { 0x04, 0xa000 }, |
|
2381 { 0x03, 0xdf01 }, |
|
2382 { 0x02, 0xdf20 }, |
|
2383 { 0x01, 0xff95 }, |
|
2384 { 0x00, 0xba00 }, |
|
2385 { 0x04, 0xa800 }, |
|
2386 { 0x04, 0xf000 }, |
|
2387 { 0x03, 0xdf01 }, |
|
2388 { 0x02, 0xdf20 }, |
|
2389 { 0x01, 0x101a }, |
|
2390 { 0x00, 0xa0ff }, |
|
2391 { 0x04, 0xf800 }, |
|
2392 { 0x04, 0x0000 }, |
|
2393 { 0x1f, 0x0000 }, |
|
2394 |
|
2395 { 0x1f, 0x0001 }, |
|
2396 { 0x10, 0xf41b }, |
|
2397 { 0x14, 0xfb54 }, |
|
2398 { 0x18, 0xf5c7 }, |
|
2399 { 0x1f, 0x0000 }, |
|
2400 |
|
2401 { 0x1f, 0x0001 }, |
|
2402 { 0x17, 0x0cc0 }, |
|
2403 { 0x1f, 0x0000 } |
|
2404 }; |
|
2405 |
|
2406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2407 |
|
2408 rtl8169scd_hw_phy_config_quirk(tp); |
|
2409 } |
|
2410 |
|
2411 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
|
2412 { |
|
2413 static const struct phy_reg phy_reg_init[] = { |
|
2414 { 0x1f, 0x0001 }, |
|
2415 { 0x04, 0x0000 }, |
|
2416 { 0x03, 0x00a1 }, |
|
2417 { 0x02, 0x0008 }, |
|
2418 { 0x01, 0x0120 }, |
|
2419 { 0x00, 0x1000 }, |
|
2420 { 0x04, 0x0800 }, |
|
2421 { 0x04, 0x9000 }, |
|
2422 { 0x03, 0x802f }, |
|
2423 { 0x02, 0x4f02 }, |
|
2424 { 0x01, 0x0409 }, |
|
2425 { 0x00, 0xf099 }, |
|
2426 { 0x04, 0x9800 }, |
|
2427 { 0x04, 0xa000 }, |
|
2428 { 0x03, 0xdf01 }, |
|
2429 { 0x02, 0xdf20 }, |
|
2430 { 0x01, 0xff95 }, |
|
2431 { 0x00, 0xba00 }, |
|
2432 { 0x04, 0xa800 }, |
|
2433 { 0x04, 0xf000 }, |
|
2434 { 0x03, 0xdf01 }, |
|
2435 { 0x02, 0xdf20 }, |
|
2436 { 0x01, 0x101a }, |
|
2437 { 0x00, 0xa0ff }, |
|
2438 { 0x04, 0xf800 }, |
|
2439 { 0x04, 0x0000 }, |
|
2440 { 0x1f, 0x0000 }, |
|
2441 |
|
2442 { 0x1f, 0x0001 }, |
|
2443 { 0x0b, 0x8480 }, |
|
2444 { 0x1f, 0x0000 }, |
|
2445 |
|
2446 { 0x1f, 0x0001 }, |
|
2447 { 0x18, 0x67c7 }, |
|
2448 { 0x04, 0x2000 }, |
|
2449 { 0x03, 0x002f }, |
|
2450 { 0x02, 0x4360 }, |
|
2451 { 0x01, 0x0109 }, |
|
2452 { 0x00, 0x3022 }, |
|
2453 { 0x04, 0x2800 }, |
|
2454 { 0x1f, 0x0000 }, |
|
2455 |
|
2456 { 0x1f, 0x0001 }, |
|
2457 { 0x17, 0x0cc0 }, |
|
2458 { 0x1f, 0x0000 } |
|
2459 }; |
|
2460 |
|
2461 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2462 } |
|
2463 |
|
2464 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
|
2465 { |
|
2466 static const struct phy_reg phy_reg_init[] = { |
|
2467 { 0x10, 0xf41b }, |
|
2468 { 0x1f, 0x0000 } |
|
2469 }; |
|
2470 |
|
2471 rtl_writephy(tp, 0x1f, 0x0001); |
|
2472 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2473 |
|
2474 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2475 } |
|
2476 |
|
2477 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
|
2478 { |
|
2479 static const struct phy_reg phy_reg_init[] = { |
|
2480 { 0x1f, 0x0001 }, |
|
2481 { 0x10, 0xf41b }, |
|
2482 { 0x1f, 0x0000 } |
|
2483 }; |
|
2484 |
|
2485 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2486 } |
|
2487 |
|
2488 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
|
2489 { |
|
2490 static const struct phy_reg phy_reg_init[] = { |
|
2491 { 0x1f, 0x0000 }, |
|
2492 { 0x1d, 0x0f00 }, |
|
2493 { 0x1f, 0x0002 }, |
|
2494 { 0x0c, 0x1ec8 }, |
|
2495 { 0x1f, 0x0000 } |
|
2496 }; |
|
2497 |
|
2498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2499 } |
|
2500 |
|
2501 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
|
2502 { |
|
2503 static const struct phy_reg phy_reg_init[] = { |
|
2504 { 0x1f, 0x0001 }, |
|
2505 { 0x1d, 0x3d98 }, |
|
2506 { 0x1f, 0x0000 } |
|
2507 }; |
|
2508 |
|
2509 rtl_writephy(tp, 0x1f, 0x0000); |
|
2510 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2511 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2512 |
|
2513 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2514 } |
|
2515 |
|
2516 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
|
2517 { |
|
2518 static const struct phy_reg phy_reg_init[] = { |
|
2519 { 0x1f, 0x0001 }, |
|
2520 { 0x12, 0x2300 }, |
|
2521 { 0x1f, 0x0002 }, |
|
2522 { 0x00, 0x88d4 }, |
|
2523 { 0x01, 0x82b1 }, |
|
2524 { 0x03, 0x7002 }, |
|
2525 { 0x08, 0x9e30 }, |
|
2526 { 0x09, 0x01f0 }, |
|
2527 { 0x0a, 0x5500 }, |
|
2528 { 0x0c, 0x00c8 }, |
|
2529 { 0x1f, 0x0003 }, |
|
2530 { 0x12, 0xc096 }, |
|
2531 { 0x16, 0x000a }, |
|
2532 { 0x1f, 0x0000 }, |
|
2533 { 0x1f, 0x0000 }, |
|
2534 { 0x09, 0x2000 }, |
|
2535 { 0x09, 0x0000 } |
|
2536 }; |
|
2537 |
|
2538 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2539 |
|
2540 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2541 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2542 rtl_writephy(tp, 0x1f, 0x0000); |
|
2543 } |
|
2544 |
|
2545 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
|
2546 { |
|
2547 static const struct phy_reg phy_reg_init[] = { |
|
2548 { 0x1f, 0x0001 }, |
|
2549 { 0x12, 0x2300 }, |
|
2550 { 0x03, 0x802f }, |
|
2551 { 0x02, 0x4f02 }, |
|
2552 { 0x01, 0x0409 }, |
|
2553 { 0x00, 0xf099 }, |
|
2554 { 0x04, 0x9800 }, |
|
2555 { 0x04, 0x9000 }, |
|
2556 { 0x1d, 0x3d98 }, |
|
2557 { 0x1f, 0x0002 }, |
|
2558 { 0x0c, 0x7eb8 }, |
|
2559 { 0x06, 0x0761 }, |
|
2560 { 0x1f, 0x0003 }, |
|
2561 { 0x16, 0x0f0a }, |
|
2562 { 0x1f, 0x0000 } |
|
2563 }; |
|
2564 |
|
2565 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2566 |
|
2567 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2568 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2569 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2570 rtl_writephy(tp, 0x1f, 0x0000); |
|
2571 } |
|
2572 |
|
2573 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
|
2574 { |
|
2575 static const struct phy_reg phy_reg_init[] = { |
|
2576 { 0x1f, 0x0001 }, |
|
2577 { 0x12, 0x2300 }, |
|
2578 { 0x1d, 0x3d98 }, |
|
2579 { 0x1f, 0x0002 }, |
|
2580 { 0x0c, 0x7eb8 }, |
|
2581 { 0x06, 0x5461 }, |
|
2582 { 0x1f, 0x0003 }, |
|
2583 { 0x16, 0x0f0a }, |
|
2584 { 0x1f, 0x0000 } |
|
2585 }; |
|
2586 |
|
2587 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2588 |
|
2589 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2590 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2591 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2592 rtl_writephy(tp, 0x1f, 0x0000); |
|
2593 } |
|
2594 |
|
2595 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
|
2596 { |
|
2597 rtl8168c_3_hw_phy_config(tp); |
|
2598 } |
|
2599 |
|
2600 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
|
2601 { |
|
2602 static const struct phy_reg phy_reg_init_0[] = { |
|
2603 /* Channel Estimation */ |
|
2604 { 0x1f, 0x0001 }, |
|
2605 { 0x06, 0x4064 }, |
|
2606 { 0x07, 0x2863 }, |
|
2607 { 0x08, 0x059c }, |
|
2608 { 0x09, 0x26b4 }, |
|
2609 { 0x0a, 0x6a19 }, |
|
2610 { 0x0b, 0xdcc8 }, |
|
2611 { 0x10, 0xf06d }, |
|
2612 { 0x14, 0x7f68 }, |
|
2613 { 0x18, 0x7fd9 }, |
|
2614 { 0x1c, 0xf0ff }, |
|
2615 { 0x1d, 0x3d9c }, |
|
2616 { 0x1f, 0x0003 }, |
|
2617 { 0x12, 0xf49f }, |
|
2618 { 0x13, 0x070b }, |
|
2619 { 0x1a, 0x05ad }, |
|
2620 { 0x14, 0x94c0 }, |
|
2621 |
|
2622 /* |
|
2623 * Tx Error Issue |
|
2624 * Enhance line driver power |
|
2625 */ |
|
2626 { 0x1f, 0x0002 }, |
|
2627 { 0x06, 0x5561 }, |
|
2628 { 0x1f, 0x0005 }, |
|
2629 { 0x05, 0x8332 }, |
|
2630 { 0x06, 0x5561 }, |
|
2631 |
|
2632 /* |
|
2633 * Can not link to 1Gbps with bad cable |
|
2634 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2635 */ |
|
2636 { 0x1f, 0x0001 }, |
|
2637 { 0x17, 0x0cc0 }, |
|
2638 |
|
2639 { 0x1f, 0x0000 }, |
|
2640 { 0x0d, 0xf880 } |
|
2641 }; |
|
2642 void __iomem *ioaddr = tp->mmio_addr; |
|
2643 |
|
2644 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2645 |
|
2646 /* |
|
2647 * Rx Error Issue |
|
2648 * Fine Tune Switching regulator parameter |
|
2649 */ |
|
2650 rtl_writephy(tp, 0x1f, 0x0002); |
|
2651 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); |
|
2652 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); |
|
2653 |
|
2654 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2655 static const struct phy_reg phy_reg_init[] = { |
|
2656 { 0x1f, 0x0002 }, |
|
2657 { 0x05, 0x669a }, |
|
2658 { 0x1f, 0x0005 }, |
|
2659 { 0x05, 0x8330 }, |
|
2660 { 0x06, 0x669a }, |
|
2661 { 0x1f, 0x0002 } |
|
2662 }; |
|
2663 int val; |
|
2664 |
|
2665 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2666 |
|
2667 val = rtl_readphy(tp, 0x0d); |
|
2668 |
|
2669 if ((val & 0x00ff) != 0x006c) { |
|
2670 static const u32 set[] = { |
|
2671 0x0065, 0x0066, 0x0067, 0x0068, |
|
2672 0x0069, 0x006a, 0x006b, 0x006c |
|
2673 }; |
|
2674 int i; |
|
2675 |
|
2676 rtl_writephy(tp, 0x1f, 0x0002); |
|
2677 |
|
2678 val &= 0xff00; |
|
2679 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2680 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2681 } |
|
2682 } else { |
|
2683 static const struct phy_reg phy_reg_init[] = { |
|
2684 { 0x1f, 0x0002 }, |
|
2685 { 0x05, 0x6662 }, |
|
2686 { 0x1f, 0x0005 }, |
|
2687 { 0x05, 0x8330 }, |
|
2688 { 0x06, 0x6662 } |
|
2689 }; |
|
2690 |
|
2691 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2692 } |
|
2693 |
|
2694 /* RSET couple improve */ |
|
2695 rtl_writephy(tp, 0x1f, 0x0002); |
|
2696 rtl_patchphy(tp, 0x0d, 0x0300); |
|
2697 rtl_patchphy(tp, 0x0f, 0x0010); |
|
2698 |
|
2699 /* Fine tune PLL performance */ |
|
2700 rtl_writephy(tp, 0x1f, 0x0002); |
|
2701 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2702 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2703 |
|
2704 rtl_writephy(tp, 0x1f, 0x0005); |
|
2705 rtl_writephy(tp, 0x05, 0x001b); |
|
2706 |
|
2707 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); |
|
2708 |
|
2709 rtl_writephy(tp, 0x1f, 0x0000); |
|
2710 } |
|
2711 |
|
2712 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
|
2713 { |
|
2714 static const struct phy_reg phy_reg_init_0[] = { |
|
2715 /* Channel Estimation */ |
|
2716 { 0x1f, 0x0001 }, |
|
2717 { 0x06, 0x4064 }, |
|
2718 { 0x07, 0x2863 }, |
|
2719 { 0x08, 0x059c }, |
|
2720 { 0x09, 0x26b4 }, |
|
2721 { 0x0a, 0x6a19 }, |
|
2722 { 0x0b, 0xdcc8 }, |
|
2723 { 0x10, 0xf06d }, |
|
2724 { 0x14, 0x7f68 }, |
|
2725 { 0x18, 0x7fd9 }, |
|
2726 { 0x1c, 0xf0ff }, |
|
2727 { 0x1d, 0x3d9c }, |
|
2728 { 0x1f, 0x0003 }, |
|
2729 { 0x12, 0xf49f }, |
|
2730 { 0x13, 0x070b }, |
|
2731 { 0x1a, 0x05ad }, |
|
2732 { 0x14, 0x94c0 }, |
|
2733 |
|
2734 /* |
|
2735 * Tx Error Issue |
|
2736 * Enhance line driver power |
|
2737 */ |
|
2738 { 0x1f, 0x0002 }, |
|
2739 { 0x06, 0x5561 }, |
|
2740 { 0x1f, 0x0005 }, |
|
2741 { 0x05, 0x8332 }, |
|
2742 { 0x06, 0x5561 }, |
|
2743 |
|
2744 /* |
|
2745 * Can not link to 1Gbps with bad cable |
|
2746 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2747 */ |
|
2748 { 0x1f, 0x0001 }, |
|
2749 { 0x17, 0x0cc0 }, |
|
2750 |
|
2751 { 0x1f, 0x0000 }, |
|
2752 { 0x0d, 0xf880 } |
|
2753 }; |
|
2754 void __iomem *ioaddr = tp->mmio_addr; |
|
2755 |
|
2756 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2757 |
|
2758 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2759 static const struct phy_reg phy_reg_init[] = { |
|
2760 { 0x1f, 0x0002 }, |
|
2761 { 0x05, 0x669a }, |
|
2762 { 0x1f, 0x0005 }, |
|
2763 { 0x05, 0x8330 }, |
|
2764 { 0x06, 0x669a }, |
|
2765 |
|
2766 { 0x1f, 0x0002 } |
|
2767 }; |
|
2768 int val; |
|
2769 |
|
2770 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2771 |
|
2772 val = rtl_readphy(tp, 0x0d); |
|
2773 if ((val & 0x00ff) != 0x006c) { |
|
2774 static const u32 set[] = { |
|
2775 0x0065, 0x0066, 0x0067, 0x0068, |
|
2776 0x0069, 0x006a, 0x006b, 0x006c |
|
2777 }; |
|
2778 int i; |
|
2779 |
|
2780 rtl_writephy(tp, 0x1f, 0x0002); |
|
2781 |
|
2782 val &= 0xff00; |
|
2783 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2784 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2785 } |
|
2786 } else { |
|
2787 static const struct phy_reg phy_reg_init[] = { |
|
2788 { 0x1f, 0x0002 }, |
|
2789 { 0x05, 0x2642 }, |
|
2790 { 0x1f, 0x0005 }, |
|
2791 { 0x05, 0x8330 }, |
|
2792 { 0x06, 0x2642 } |
|
2793 }; |
|
2794 |
|
2795 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2796 } |
|
2797 |
|
2798 /* Fine tune PLL performance */ |
|
2799 rtl_writephy(tp, 0x1f, 0x0002); |
|
2800 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2801 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2802 |
|
2803 /* Switching regulator Slew rate */ |
|
2804 rtl_writephy(tp, 0x1f, 0x0002); |
|
2805 rtl_patchphy(tp, 0x0f, 0x0017); |
|
2806 |
|
2807 rtl_writephy(tp, 0x1f, 0x0005); |
|
2808 rtl_writephy(tp, 0x05, 0x001b); |
|
2809 |
|
2810 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); |
|
2811 |
|
2812 rtl_writephy(tp, 0x1f, 0x0000); |
|
2813 } |
|
2814 |
|
2815 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
|
2816 { |
|
2817 static const struct phy_reg phy_reg_init[] = { |
|
2818 { 0x1f, 0x0002 }, |
|
2819 { 0x10, 0x0008 }, |
|
2820 { 0x0d, 0x006c }, |
|
2821 |
|
2822 { 0x1f, 0x0000 }, |
|
2823 { 0x0d, 0xf880 }, |
|
2824 |
|
2825 { 0x1f, 0x0001 }, |
|
2826 { 0x17, 0x0cc0 }, |
|
2827 |
|
2828 { 0x1f, 0x0001 }, |
|
2829 { 0x0b, 0xa4d8 }, |
|
2830 { 0x09, 0x281c }, |
|
2831 { 0x07, 0x2883 }, |
|
2832 { 0x0a, 0x6b35 }, |
|
2833 { 0x1d, 0x3da4 }, |
|
2834 { 0x1c, 0xeffd }, |
|
2835 { 0x14, 0x7f52 }, |
|
2836 { 0x18, 0x7fc6 }, |
|
2837 { 0x08, 0x0601 }, |
|
2838 { 0x06, 0x4063 }, |
|
2839 { 0x10, 0xf074 }, |
|
2840 { 0x1f, 0x0003 }, |
|
2841 { 0x13, 0x0789 }, |
|
2842 { 0x12, 0xf4bd }, |
|
2843 { 0x1a, 0x04fd }, |
|
2844 { 0x14, 0x84b0 }, |
|
2845 { 0x1f, 0x0000 }, |
|
2846 { 0x00, 0x9200 }, |
|
2847 |
|
2848 { 0x1f, 0x0005 }, |
|
2849 { 0x01, 0x0340 }, |
|
2850 { 0x1f, 0x0001 }, |
|
2851 { 0x04, 0x4000 }, |
|
2852 { 0x03, 0x1d21 }, |
|
2853 { 0x02, 0x0c32 }, |
|
2854 { 0x01, 0x0200 }, |
|
2855 { 0x00, 0x5554 }, |
|
2856 { 0x04, 0x4800 }, |
|
2857 { 0x04, 0x4000 }, |
|
2858 { 0x04, 0xf000 }, |
|
2859 { 0x03, 0xdf01 }, |
|
2860 { 0x02, 0xdf20 }, |
|
2861 { 0x01, 0x101a }, |
|
2862 { 0x00, 0xa0ff }, |
|
2863 { 0x04, 0xf800 }, |
|
2864 { 0x04, 0xf000 }, |
|
2865 { 0x1f, 0x0000 }, |
|
2866 |
|
2867 { 0x1f, 0x0007 }, |
|
2868 { 0x1e, 0x0023 }, |
|
2869 { 0x16, 0x0000 }, |
|
2870 { 0x1f, 0x0000 } |
|
2871 }; |
|
2872 |
|
2873 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2874 } |
|
2875 |
|
2876 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
|
2877 { |
|
2878 static const struct phy_reg phy_reg_init[] = { |
|
2879 { 0x1f, 0x0001 }, |
|
2880 { 0x17, 0x0cc0 }, |
|
2881 |
|
2882 { 0x1f, 0x0007 }, |
|
2883 { 0x1e, 0x002d }, |
|
2884 { 0x18, 0x0040 }, |
|
2885 { 0x1f, 0x0000 } |
|
2886 }; |
|
2887 |
|
2888 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2889 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2890 } |
|
2891 |
|
2892 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
|
2893 { |
|
2894 static const struct phy_reg phy_reg_init[] = { |
|
2895 /* Enable Delay cap */ |
|
2896 { 0x1f, 0x0005 }, |
|
2897 { 0x05, 0x8b80 }, |
|
2898 { 0x06, 0xc896 }, |
|
2899 { 0x1f, 0x0000 }, |
|
2900 |
|
2901 /* Channel estimation fine tune */ |
|
2902 { 0x1f, 0x0001 }, |
|
2903 { 0x0b, 0x6c20 }, |
|
2904 { 0x07, 0x2872 }, |
|
2905 { 0x1c, 0xefff }, |
|
2906 { 0x1f, 0x0003 }, |
|
2907 { 0x14, 0x6420 }, |
|
2908 { 0x1f, 0x0000 }, |
|
2909 |
|
2910 /* Update PFM & 10M TX idle timer */ |
|
2911 { 0x1f, 0x0007 }, |
|
2912 { 0x1e, 0x002f }, |
|
2913 { 0x15, 0x1919 }, |
|
2914 { 0x1f, 0x0000 }, |
|
2915 |
|
2916 { 0x1f, 0x0007 }, |
|
2917 { 0x1e, 0x00ac }, |
|
2918 { 0x18, 0x0006 }, |
|
2919 { 0x1f, 0x0000 } |
|
2920 }; |
|
2921 |
|
2922 rtl_apply_firmware(tp); |
|
2923 |
|
2924 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2925 |
|
2926 /* DCO enable for 10M IDLE Power */ |
|
2927 rtl_writephy(tp, 0x1f, 0x0007); |
|
2928 rtl_writephy(tp, 0x1e, 0x0023); |
|
2929 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
2930 rtl_writephy(tp, 0x1f, 0x0000); |
|
2931 |
|
2932 /* For impedance matching */ |
|
2933 rtl_writephy(tp, 0x1f, 0x0002); |
|
2934 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); |
|
2935 rtl_writephy(tp, 0x1f, 0x0000); |
|
2936 |
|
2937 /* PHY auto speed down */ |
|
2938 rtl_writephy(tp, 0x1f, 0x0007); |
|
2939 rtl_writephy(tp, 0x1e, 0x002d); |
|
2940 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); |
|
2941 rtl_writephy(tp, 0x1f, 0x0000); |
|
2942 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
2943 |
|
2944 rtl_writephy(tp, 0x1f, 0x0005); |
|
2945 rtl_writephy(tp, 0x05, 0x8b86); |
|
2946 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
2947 rtl_writephy(tp, 0x1f, 0x0000); |
|
2948 |
|
2949 rtl_writephy(tp, 0x1f, 0x0005); |
|
2950 rtl_writephy(tp, 0x05, 0x8b85); |
|
2951 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
2952 rtl_writephy(tp, 0x1f, 0x0007); |
|
2953 rtl_writephy(tp, 0x1e, 0x0020); |
|
2954 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); |
|
2955 rtl_writephy(tp, 0x1f, 0x0006); |
|
2956 rtl_writephy(tp, 0x00, 0x5a00); |
|
2957 rtl_writephy(tp, 0x1f, 0x0000); |
|
2958 rtl_writephy(tp, 0x0d, 0x0007); |
|
2959 rtl_writephy(tp, 0x0e, 0x003c); |
|
2960 rtl_writephy(tp, 0x0d, 0x4007); |
|
2961 rtl_writephy(tp, 0x0e, 0x0000); |
|
2962 rtl_writephy(tp, 0x0d, 0x0000); |
|
2963 } |
|
2964 |
|
2965 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
|
2966 { |
|
2967 static const struct phy_reg phy_reg_init[] = { |
|
2968 /* Enable Delay cap */ |
|
2969 { 0x1f, 0x0004 }, |
|
2970 { 0x1f, 0x0007 }, |
|
2971 { 0x1e, 0x00ac }, |
|
2972 { 0x18, 0x0006 }, |
|
2973 { 0x1f, 0x0002 }, |
|
2974 { 0x1f, 0x0000 }, |
|
2975 { 0x1f, 0x0000 }, |
|
2976 |
|
2977 /* Channel estimation fine tune */ |
|
2978 { 0x1f, 0x0003 }, |
|
2979 { 0x09, 0xa20f }, |
|
2980 { 0x1f, 0x0000 }, |
|
2981 { 0x1f, 0x0000 }, |
|
2982 |
|
2983 /* Green Setting */ |
|
2984 { 0x1f, 0x0005 }, |
|
2985 { 0x05, 0x8b5b }, |
|
2986 { 0x06, 0x9222 }, |
|
2987 { 0x05, 0x8b6d }, |
|
2988 { 0x06, 0x8000 }, |
|
2989 { 0x05, 0x8b76 }, |
|
2990 { 0x06, 0x8000 }, |
|
2991 { 0x1f, 0x0000 } |
|
2992 }; |
|
2993 |
|
2994 rtl_apply_firmware(tp); |
|
2995 |
|
2996 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2997 |
|
2998 /* For 4-corner performance improve */ |
|
2999 rtl_writephy(tp, 0x1f, 0x0005); |
|
3000 rtl_writephy(tp, 0x05, 0x8b80); |
|
3001 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
3002 rtl_writephy(tp, 0x1f, 0x0000); |
|
3003 |
|
3004 /* PHY auto speed down */ |
|
3005 rtl_writephy(tp, 0x1f, 0x0004); |
|
3006 rtl_writephy(tp, 0x1f, 0x0007); |
|
3007 rtl_writephy(tp, 0x1e, 0x002d); |
|
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3009 rtl_writephy(tp, 0x1f, 0x0002); |
|
3010 rtl_writephy(tp, 0x1f, 0x0000); |
|
3011 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3012 |
|
3013 /* improve 10M EEE waveform */ |
|
3014 rtl_writephy(tp, 0x1f, 0x0005); |
|
3015 rtl_writephy(tp, 0x05, 0x8b86); |
|
3016 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3017 rtl_writephy(tp, 0x1f, 0x0000); |
|
3018 |
|
3019 /* Improve 2-pair detection performance */ |
|
3020 rtl_writephy(tp, 0x1f, 0x0005); |
|
3021 rtl_writephy(tp, 0x05, 0x8b85); |
|
3022 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3023 rtl_writephy(tp, 0x1f, 0x0000); |
|
3024 |
|
3025 /* EEE setting */ |
|
3026 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, |
|
3027 ERIAR_EXGMAC); |
|
3028 rtl_writephy(tp, 0x1f, 0x0005); |
|
3029 rtl_writephy(tp, 0x05, 0x8b85); |
|
3030 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
3031 rtl_writephy(tp, 0x1f, 0x0004); |
|
3032 rtl_writephy(tp, 0x1f, 0x0007); |
|
3033 rtl_writephy(tp, 0x1e, 0x0020); |
|
3034 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
|
3035 rtl_writephy(tp, 0x1f, 0x0002); |
|
3036 rtl_writephy(tp, 0x1f, 0x0000); |
|
3037 rtl_writephy(tp, 0x0d, 0x0007); |
|
3038 rtl_writephy(tp, 0x0e, 0x003c); |
|
3039 rtl_writephy(tp, 0x0d, 0x4007); |
|
3040 rtl_writephy(tp, 0x0e, 0x0000); |
|
3041 rtl_writephy(tp, 0x0d, 0x0000); |
|
3042 |
|
3043 /* Green feature */ |
|
3044 rtl_writephy(tp, 0x1f, 0x0003); |
|
3045 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); |
|
3046 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); |
|
3047 rtl_writephy(tp, 0x1f, 0x0000); |
|
3048 } |
|
3049 |
|
3050 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
|
3051 { |
|
3052 static const struct phy_reg phy_reg_init[] = { |
|
3053 /* Channel estimation fine tune */ |
|
3054 { 0x1f, 0x0003 }, |
|
3055 { 0x09, 0xa20f }, |
|
3056 { 0x1f, 0x0000 }, |
|
3057 |
|
3058 /* Modify green table for giga & fnet */ |
|
3059 { 0x1f, 0x0005 }, |
|
3060 { 0x05, 0x8b55 }, |
|
3061 { 0x06, 0x0000 }, |
|
3062 { 0x05, 0x8b5e }, |
|
3063 { 0x06, 0x0000 }, |
|
3064 { 0x05, 0x8b67 }, |
|
3065 { 0x06, 0x0000 }, |
|
3066 { 0x05, 0x8b70 }, |
|
3067 { 0x06, 0x0000 }, |
|
3068 { 0x1f, 0x0000 }, |
|
3069 { 0x1f, 0x0007 }, |
|
3070 { 0x1e, 0x0078 }, |
|
3071 { 0x17, 0x0000 }, |
|
3072 { 0x19, 0x00fb }, |
|
3073 { 0x1f, 0x0000 }, |
|
3074 |
|
3075 /* Modify green table for 10M */ |
|
3076 { 0x1f, 0x0005 }, |
|
3077 { 0x05, 0x8b79 }, |
|
3078 { 0x06, 0xaa00 }, |
|
3079 { 0x1f, 0x0000 }, |
|
3080 |
|
3081 /* Disable hiimpedance detection (RTCT) */ |
|
3082 { 0x1f, 0x0003 }, |
|
3083 { 0x01, 0x328a }, |
|
3084 { 0x1f, 0x0000 } |
|
3085 }; |
|
3086 |
|
3087 rtl_apply_firmware(tp); |
|
3088 |
|
3089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3090 |
|
3091 /* For 4-corner performance improve */ |
|
3092 rtl_writephy(tp, 0x1f, 0x0005); |
|
3093 rtl_writephy(tp, 0x05, 0x8b80); |
|
3094 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3095 rtl_writephy(tp, 0x1f, 0x0000); |
|
3096 |
|
3097 /* PHY auto speed down */ |
|
3098 rtl_writephy(tp, 0x1f, 0x0007); |
|
3099 rtl_writephy(tp, 0x1e, 0x002d); |
|
3100 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3101 rtl_writephy(tp, 0x1f, 0x0000); |
|
3102 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3103 |
|
3104 /* Improve 10M EEE waveform */ |
|
3105 rtl_writephy(tp, 0x1f, 0x0005); |
|
3106 rtl_writephy(tp, 0x05, 0x8b86); |
|
3107 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3108 rtl_writephy(tp, 0x1f, 0x0000); |
|
3109 |
|
3110 /* Improve 2-pair detection performance */ |
|
3111 rtl_writephy(tp, 0x1f, 0x0005); |
|
3112 rtl_writephy(tp, 0x05, 0x8b85); |
|
3113 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3114 rtl_writephy(tp, 0x1f, 0x0000); |
|
3115 } |
|
3116 |
|
3117 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) |
|
3118 { |
|
3119 rtl_apply_firmware(tp); |
|
3120 |
|
3121 /* For 4-corner performance improve */ |
|
3122 rtl_writephy(tp, 0x1f, 0x0005); |
|
3123 rtl_writephy(tp, 0x05, 0x8b80); |
|
3124 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3125 rtl_writephy(tp, 0x1f, 0x0000); |
|
3126 |
|
3127 /* PHY auto speed down */ |
|
3128 rtl_writephy(tp, 0x1f, 0x0007); |
|
3129 rtl_writephy(tp, 0x1e, 0x002d); |
|
3130 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3131 rtl_writephy(tp, 0x1f, 0x0000); |
|
3132 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3133 |
|
3134 /* Improve 10M EEE waveform */ |
|
3135 rtl_writephy(tp, 0x1f, 0x0005); |
|
3136 rtl_writephy(tp, 0x05, 0x8b86); |
|
3137 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3138 rtl_writephy(tp, 0x1f, 0x0000); |
|
3139 } |
|
3140 |
|
3141 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
|
3142 { |
|
3143 static const struct phy_reg phy_reg_init[] = { |
|
3144 { 0x1f, 0x0003 }, |
|
3145 { 0x08, 0x441d }, |
|
3146 { 0x01, 0x9100 }, |
|
3147 { 0x1f, 0x0000 } |
|
3148 }; |
|
3149 |
|
3150 rtl_writephy(tp, 0x1f, 0x0000); |
|
3151 rtl_patchphy(tp, 0x11, 1 << 12); |
|
3152 rtl_patchphy(tp, 0x19, 1 << 13); |
|
3153 rtl_patchphy(tp, 0x10, 1 << 15); |
|
3154 |
|
3155 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3156 } |
|
3157 |
|
3158 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
|
3159 { |
|
3160 static const struct phy_reg phy_reg_init[] = { |
|
3161 { 0x1f, 0x0005 }, |
|
3162 { 0x1a, 0x0000 }, |
|
3163 { 0x1f, 0x0000 }, |
|
3164 |
|
3165 { 0x1f, 0x0004 }, |
|
3166 { 0x1c, 0x0000 }, |
|
3167 { 0x1f, 0x0000 }, |
|
3168 |
|
3169 { 0x1f, 0x0001 }, |
|
3170 { 0x15, 0x7701 }, |
|
3171 { 0x1f, 0x0000 } |
|
3172 }; |
|
3173 |
|
3174 /* Disable ALDPS before ram code */ |
|
3175 rtl_writephy(tp, 0x1f, 0x0000); |
|
3176 rtl_writephy(tp, 0x18, 0x0310); |
|
3177 msleep(100); |
|
3178 |
|
3179 rtl_apply_firmware(tp); |
|
3180 |
|
3181 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3182 } |
|
3183 |
|
3184 static void rtl_hw_phy_config(struct net_device *dev) |
|
3185 { |
|
3186 struct rtl8169_private *tp = netdev_priv(dev); |
|
3187 |
|
3188 rtl8169_print_mac_version(tp); |
|
3189 |
|
3190 switch (tp->mac_version) { |
|
3191 case RTL_GIGA_MAC_VER_01: |
|
3192 break; |
|
3193 case RTL_GIGA_MAC_VER_02: |
|
3194 case RTL_GIGA_MAC_VER_03: |
|
3195 rtl8169s_hw_phy_config(tp); |
|
3196 break; |
|
3197 case RTL_GIGA_MAC_VER_04: |
|
3198 rtl8169sb_hw_phy_config(tp); |
|
3199 break; |
|
3200 case RTL_GIGA_MAC_VER_05: |
|
3201 rtl8169scd_hw_phy_config(tp); |
|
3202 break; |
|
3203 case RTL_GIGA_MAC_VER_06: |
|
3204 rtl8169sce_hw_phy_config(tp); |
|
3205 break; |
|
3206 case RTL_GIGA_MAC_VER_07: |
|
3207 case RTL_GIGA_MAC_VER_08: |
|
3208 case RTL_GIGA_MAC_VER_09: |
|
3209 rtl8102e_hw_phy_config(tp); |
|
3210 break; |
|
3211 case RTL_GIGA_MAC_VER_11: |
|
3212 rtl8168bb_hw_phy_config(tp); |
|
3213 break; |
|
3214 case RTL_GIGA_MAC_VER_12: |
|
3215 rtl8168bef_hw_phy_config(tp); |
|
3216 break; |
|
3217 case RTL_GIGA_MAC_VER_17: |
|
3218 rtl8168bef_hw_phy_config(tp); |
|
3219 break; |
|
3220 case RTL_GIGA_MAC_VER_18: |
|
3221 rtl8168cp_1_hw_phy_config(tp); |
|
3222 break; |
|
3223 case RTL_GIGA_MAC_VER_19: |
|
3224 rtl8168c_1_hw_phy_config(tp); |
|
3225 break; |
|
3226 case RTL_GIGA_MAC_VER_20: |
|
3227 rtl8168c_2_hw_phy_config(tp); |
|
3228 break; |
|
3229 case RTL_GIGA_MAC_VER_21: |
|
3230 rtl8168c_3_hw_phy_config(tp); |
|
3231 break; |
|
3232 case RTL_GIGA_MAC_VER_22: |
|
3233 rtl8168c_4_hw_phy_config(tp); |
|
3234 break; |
|
3235 case RTL_GIGA_MAC_VER_23: |
|
3236 case RTL_GIGA_MAC_VER_24: |
|
3237 rtl8168cp_2_hw_phy_config(tp); |
|
3238 break; |
|
3239 case RTL_GIGA_MAC_VER_25: |
|
3240 rtl8168d_1_hw_phy_config(tp); |
|
3241 break; |
|
3242 case RTL_GIGA_MAC_VER_26: |
|
3243 rtl8168d_2_hw_phy_config(tp); |
|
3244 break; |
|
3245 case RTL_GIGA_MAC_VER_27: |
|
3246 rtl8168d_3_hw_phy_config(tp); |
|
3247 break; |
|
3248 case RTL_GIGA_MAC_VER_28: |
|
3249 rtl8168d_4_hw_phy_config(tp); |
|
3250 break; |
|
3251 case RTL_GIGA_MAC_VER_29: |
|
3252 case RTL_GIGA_MAC_VER_30: |
|
3253 rtl8105e_hw_phy_config(tp); |
|
3254 break; |
|
3255 case RTL_GIGA_MAC_VER_31: |
|
3256 /* None. */ |
|
3257 break; |
|
3258 case RTL_GIGA_MAC_VER_32: |
|
3259 case RTL_GIGA_MAC_VER_33: |
|
3260 rtl8168e_1_hw_phy_config(tp); |
|
3261 break; |
|
3262 case RTL_GIGA_MAC_VER_34: |
|
3263 rtl8168e_2_hw_phy_config(tp); |
|
3264 break; |
|
3265 case RTL_GIGA_MAC_VER_35: |
|
3266 rtl8168f_1_hw_phy_config(tp); |
|
3267 break; |
|
3268 case RTL_GIGA_MAC_VER_36: |
|
3269 rtl8168f_2_hw_phy_config(tp); |
|
3270 break; |
|
3271 |
|
3272 default: |
|
3273 break; |
|
3274 } |
|
3275 } |
|
3276 |
|
3277 static void rtl_phy_work(struct rtl8169_private *tp) |
|
3278 { |
|
3279 struct timer_list *timer = &tp->timer; |
|
3280 void __iomem *ioaddr = tp->mmio_addr; |
|
3281 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
3282 |
|
3283 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
3284 |
|
3285 if (tp->phy_reset_pending(tp)) { |
|
3286 /* |
|
3287 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
3288 * Let's delay the execution of the timer for a few ticks. |
|
3289 */ |
|
3290 timeout = HZ/10; |
|
3291 goto out_mod_timer; |
|
3292 } |
|
3293 |
|
3294 if (tp->link_ok(ioaddr)) |
|
3295 return; |
|
3296 |
|
3297 netif_warn(tp, link, tp->dev, "PHY reset until link up\n"); |
|
3298 |
|
3299 tp->phy_reset_enable(tp); |
|
3300 |
|
3301 out_mod_timer: |
|
3302 mod_timer(timer, jiffies + timeout); |
|
3303 } |
|
3304 |
|
3305 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) |
|
3306 { |
|
3307 if (!test_and_set_bit(flag, tp->wk.flags)) |
|
3308 schedule_work(&tp->wk.work); |
|
3309 } |
|
3310 |
|
3311 static void rtl8169_phy_timer(unsigned long __opaque) |
|
3312 { |
|
3313 struct net_device *dev = (struct net_device *)__opaque; |
|
3314 struct rtl8169_private *tp = netdev_priv(dev); |
|
3315 |
|
3316 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
|
3317 } |
|
3318 |
|
3319 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
3320 void __iomem *ioaddr) |
|
3321 { |
|
3322 iounmap(ioaddr); |
|
3323 pci_release_regions(pdev); |
|
3324 pci_clear_mwi(pdev); |
|
3325 pci_disable_device(pdev); |
|
3326 free_netdev(dev); |
|
3327 } |
|
3328 |
|
3329 static void rtl8169_phy_reset(struct net_device *dev, |
|
3330 struct rtl8169_private *tp) |
|
3331 { |
|
3332 unsigned int i; |
|
3333 |
|
3334 tp->phy_reset_enable(tp); |
|
3335 for (i = 0; i < 100; i++) { |
|
3336 if (!tp->phy_reset_pending(tp)) |
|
3337 return; |
|
3338 msleep(1); |
|
3339 } |
|
3340 netif_err(tp, link, dev, "PHY reset failed\n"); |
|
3341 } |
|
3342 |
|
3343 static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
|
3344 { |
|
3345 void __iomem *ioaddr = tp->mmio_addr; |
|
3346 |
|
3347 return (tp->mac_version == RTL_GIGA_MAC_VER_01) && |
|
3348 (RTL_R8(PHYstatus) & TBI_Enable); |
|
3349 } |
|
3350 |
|
3351 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
3352 { |
|
3353 void __iomem *ioaddr = tp->mmio_addr; |
|
3354 |
|
3355 rtl_hw_phy_config(dev); |
|
3356 |
|
3357 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
3358 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3359 RTL_W8(0x82, 0x01); |
|
3360 } |
|
3361 |
|
3362 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
3363 |
|
3364 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
3365 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3366 |
|
3367 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
3368 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3369 RTL_W8(0x82, 0x01); |
|
3370 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
3371 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
3372 } |
|
3373 |
|
3374 rtl8169_phy_reset(dev, tp); |
|
3375 |
|
3376 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
|
3377 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
3378 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | |
|
3379 (tp->mii.supports_gmii ? |
|
3380 ADVERTISED_1000baseT_Half | |
|
3381 ADVERTISED_1000baseT_Full : 0)); |
|
3382 |
|
3383 if (rtl_tbi_enabled(tp)) |
|
3384 netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
|
3385 } |
|
3386 |
|
3387 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
3388 { |
|
3389 void __iomem *ioaddr = tp->mmio_addr; |
|
3390 u32 high; |
|
3391 u32 low; |
|
3392 |
|
3393 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
3394 high = addr[4] | (addr[5] << 8); |
|
3395 |
|
3396 rtl_lock_work(tp); |
|
3397 |
|
3398 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3399 |
|
3400 RTL_W32(MAC4, high); |
|
3401 RTL_R32(MAC4); |
|
3402 |
|
3403 RTL_W32(MAC0, low); |
|
3404 RTL_R32(MAC0); |
|
3405 |
|
3406 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
3407 const struct exgmac_reg e[] = { |
|
3408 { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, |
|
3409 { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, |
|
3410 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, |
|
3411 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | |
|
3412 low >> 16 }, |
|
3413 }; |
|
3414 |
|
3415 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); |
|
3416 } |
|
3417 |
|
3418 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3419 |
|
3420 rtl_unlock_work(tp); |
|
3421 } |
|
3422 |
|
3423 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
3424 { |
|
3425 struct rtl8169_private *tp = netdev_priv(dev); |
|
3426 struct sockaddr *addr = p; |
|
3427 |
|
3428 if (!is_valid_ether_addr(addr->sa_data)) |
|
3429 return -EADDRNOTAVAIL; |
|
3430 |
|
3431 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
3432 |
|
3433 rtl_rar_set(tp, dev->dev_addr); |
|
3434 |
|
3435 return 0; |
|
3436 } |
|
3437 |
|
3438 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
3439 { |
|
3440 struct rtl8169_private *tp = netdev_priv(dev); |
|
3441 struct mii_ioctl_data *data = if_mii(ifr); |
|
3442 |
|
3443 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
3444 } |
|
3445 |
|
3446 static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
|
3447 struct mii_ioctl_data *data, int cmd) |
|
3448 { |
|
3449 switch (cmd) { |
|
3450 case SIOCGMIIPHY: |
|
3451 data->phy_id = 32; /* Internal PHY */ |
|
3452 return 0; |
|
3453 |
|
3454 case SIOCGMIIREG: |
|
3455 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
|
3456 return 0; |
|
3457 |
|
3458 case SIOCSMIIREG: |
|
3459 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
|
3460 return 0; |
|
3461 } |
|
3462 return -EOPNOTSUPP; |
|
3463 } |
|
3464 |
|
3465 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
3466 { |
|
3467 return -EOPNOTSUPP; |
|
3468 } |
|
3469 |
|
3470 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
3471 { |
|
3472 if (tp->features & RTL_FEATURE_MSI) { |
|
3473 pci_disable_msi(pdev); |
|
3474 tp->features &= ~RTL_FEATURE_MSI; |
|
3475 } |
|
3476 } |
|
3477 |
|
3478 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
|
3479 { |
|
3480 struct mdio_ops *ops = &tp->mdio_ops; |
|
3481 |
|
3482 switch (tp->mac_version) { |
|
3483 case RTL_GIGA_MAC_VER_27: |
|
3484 ops->write = r8168dp_1_mdio_write; |
|
3485 ops->read = r8168dp_1_mdio_read; |
|
3486 break; |
|
3487 case RTL_GIGA_MAC_VER_28: |
|
3488 case RTL_GIGA_MAC_VER_31: |
|
3489 ops->write = r8168dp_2_mdio_write; |
|
3490 ops->read = r8168dp_2_mdio_read; |
|
3491 break; |
|
3492 default: |
|
3493 ops->write = r8169_mdio_write; |
|
3494 ops->read = r8169_mdio_read; |
|
3495 break; |
|
3496 } |
|
3497 } |
|
3498 |
|
3499 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
|
3500 { |
|
3501 void __iomem *ioaddr = tp->mmio_addr; |
|
3502 |
|
3503 switch (tp->mac_version) { |
|
3504 case RTL_GIGA_MAC_VER_25: |
|
3505 case RTL_GIGA_MAC_VER_26: |
|
3506 case RTL_GIGA_MAC_VER_29: |
|
3507 case RTL_GIGA_MAC_VER_30: |
|
3508 case RTL_GIGA_MAC_VER_32: |
|
3509 case RTL_GIGA_MAC_VER_33: |
|
3510 case RTL_GIGA_MAC_VER_34: |
|
3511 RTL_W32(RxConfig, RTL_R32(RxConfig) | |
|
3512 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
|
3513 break; |
|
3514 default: |
|
3515 break; |
|
3516 } |
|
3517 } |
|
3518 |
|
3519 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) |
|
3520 { |
|
3521 if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) |
|
3522 return false; |
|
3523 |
|
3524 rtl_writephy(tp, 0x1f, 0x0000); |
|
3525 rtl_writephy(tp, MII_BMCR, 0x0000); |
|
3526 |
|
3527 rtl_wol_suspend_quirk(tp); |
|
3528 |
|
3529 return true; |
|
3530 } |
|
3531 |
|
3532 static void r810x_phy_power_down(struct rtl8169_private *tp) |
|
3533 { |
|
3534 rtl_writephy(tp, 0x1f, 0x0000); |
|
3535 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3536 } |
|
3537 |
|
3538 static void r810x_phy_power_up(struct rtl8169_private *tp) |
|
3539 { |
|
3540 rtl_writephy(tp, 0x1f, 0x0000); |
|
3541 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3542 } |
|
3543 |
|
3544 static void r810x_pll_power_down(struct rtl8169_private *tp) |
|
3545 { |
|
3546 if (rtl_wol_pll_power_down(tp)) |
|
3547 return; |
|
3548 |
|
3549 r810x_phy_power_down(tp); |
|
3550 } |
|
3551 |
|
3552 static void r810x_pll_power_up(struct rtl8169_private *tp) |
|
3553 { |
|
3554 r810x_phy_power_up(tp); |
|
3555 } |
|
3556 |
|
3557 static void r8168_phy_power_up(struct rtl8169_private *tp) |
|
3558 { |
|
3559 rtl_writephy(tp, 0x1f, 0x0000); |
|
3560 switch (tp->mac_version) { |
|
3561 case RTL_GIGA_MAC_VER_11: |
|
3562 case RTL_GIGA_MAC_VER_12: |
|
3563 case RTL_GIGA_MAC_VER_17: |
|
3564 case RTL_GIGA_MAC_VER_18: |
|
3565 case RTL_GIGA_MAC_VER_19: |
|
3566 case RTL_GIGA_MAC_VER_20: |
|
3567 case RTL_GIGA_MAC_VER_21: |
|
3568 case RTL_GIGA_MAC_VER_22: |
|
3569 case RTL_GIGA_MAC_VER_23: |
|
3570 case RTL_GIGA_MAC_VER_24: |
|
3571 case RTL_GIGA_MAC_VER_25: |
|
3572 case RTL_GIGA_MAC_VER_26: |
|
3573 case RTL_GIGA_MAC_VER_27: |
|
3574 case RTL_GIGA_MAC_VER_28: |
|
3575 case RTL_GIGA_MAC_VER_31: |
|
3576 rtl_writephy(tp, 0x0e, 0x0000); |
|
3577 break; |
|
3578 default: |
|
3579 break; |
|
3580 } |
|
3581 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3582 } |
|
3583 |
|
3584 static void r8168_phy_power_down(struct rtl8169_private *tp) |
|
3585 { |
|
3586 rtl_writephy(tp, 0x1f, 0x0000); |
|
3587 switch (tp->mac_version) { |
|
3588 case RTL_GIGA_MAC_VER_32: |
|
3589 case RTL_GIGA_MAC_VER_33: |
|
3590 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
|
3591 break; |
|
3592 |
|
3593 case RTL_GIGA_MAC_VER_11: |
|
3594 case RTL_GIGA_MAC_VER_12: |
|
3595 case RTL_GIGA_MAC_VER_17: |
|
3596 case RTL_GIGA_MAC_VER_18: |
|
3597 case RTL_GIGA_MAC_VER_19: |
|
3598 case RTL_GIGA_MAC_VER_20: |
|
3599 case RTL_GIGA_MAC_VER_21: |
|
3600 case RTL_GIGA_MAC_VER_22: |
|
3601 case RTL_GIGA_MAC_VER_23: |
|
3602 case RTL_GIGA_MAC_VER_24: |
|
3603 case RTL_GIGA_MAC_VER_25: |
|
3604 case RTL_GIGA_MAC_VER_26: |
|
3605 case RTL_GIGA_MAC_VER_27: |
|
3606 case RTL_GIGA_MAC_VER_28: |
|
3607 case RTL_GIGA_MAC_VER_31: |
|
3608 rtl_writephy(tp, 0x0e, 0x0200); |
|
3609 default: |
|
3610 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3611 break; |
|
3612 } |
|
3613 } |
|
3614 |
|
3615 static void r8168_pll_power_down(struct rtl8169_private *tp) |
|
3616 { |
|
3617 void __iomem *ioaddr = tp->mmio_addr; |
|
3618 |
|
3619 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3620 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3621 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3622 r8168dp_check_dash(tp)) { |
|
3623 return; |
|
3624 } |
|
3625 |
|
3626 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
|
3627 tp->mac_version == RTL_GIGA_MAC_VER_24) && |
|
3628 (RTL_R16(CPlusCmd) & ASF)) { |
|
3629 return; |
|
3630 } |
|
3631 |
|
3632 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
|
3633 tp->mac_version == RTL_GIGA_MAC_VER_33) |
|
3634 rtl_ephy_write(ioaddr, 0x19, 0xff64); |
|
3635 |
|
3636 if (rtl_wol_pll_power_down(tp)) |
|
3637 return; |
|
3638 |
|
3639 r8168_phy_power_down(tp); |
|
3640 |
|
3641 switch (tp->mac_version) { |
|
3642 case RTL_GIGA_MAC_VER_25: |
|
3643 case RTL_GIGA_MAC_VER_26: |
|
3644 case RTL_GIGA_MAC_VER_27: |
|
3645 case RTL_GIGA_MAC_VER_28: |
|
3646 case RTL_GIGA_MAC_VER_31: |
|
3647 case RTL_GIGA_MAC_VER_32: |
|
3648 case RTL_GIGA_MAC_VER_33: |
|
3649 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
|
3650 break; |
|
3651 } |
|
3652 } |
|
3653 |
|
3654 static void r8168_pll_power_up(struct rtl8169_private *tp) |
|
3655 { |
|
3656 void __iomem *ioaddr = tp->mmio_addr; |
|
3657 |
|
3658 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3659 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3660 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3661 r8168dp_check_dash(tp)) { |
|
3662 return; |
|
3663 } |
|
3664 |
|
3665 switch (tp->mac_version) { |
|
3666 case RTL_GIGA_MAC_VER_25: |
|
3667 case RTL_GIGA_MAC_VER_26: |
|
3668 case RTL_GIGA_MAC_VER_27: |
|
3669 case RTL_GIGA_MAC_VER_28: |
|
3670 case RTL_GIGA_MAC_VER_31: |
|
3671 case RTL_GIGA_MAC_VER_32: |
|
3672 case RTL_GIGA_MAC_VER_33: |
|
3673 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
|
3674 break; |
|
3675 } |
|
3676 |
|
3677 r8168_phy_power_up(tp); |
|
3678 } |
|
3679 |
|
3680 static void rtl_generic_op(struct rtl8169_private *tp, |
|
3681 void (*op)(struct rtl8169_private *)) |
|
3682 { |
|
3683 if (op) |
|
3684 op(tp); |
|
3685 } |
|
3686 |
|
3687 static void rtl_pll_power_down(struct rtl8169_private *tp) |
|
3688 { |
|
3689 rtl_generic_op(tp, tp->pll_power_ops.down); |
|
3690 } |
|
3691 |
|
3692 static void rtl_pll_power_up(struct rtl8169_private *tp) |
|
3693 { |
|
3694 rtl_generic_op(tp, tp->pll_power_ops.up); |
|
3695 } |
|
3696 |
|
3697 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) |
|
3698 { |
|
3699 struct pll_power_ops *ops = &tp->pll_power_ops; |
|
3700 |
|
3701 switch (tp->mac_version) { |
|
3702 case RTL_GIGA_MAC_VER_07: |
|
3703 case RTL_GIGA_MAC_VER_08: |
|
3704 case RTL_GIGA_MAC_VER_09: |
|
3705 case RTL_GIGA_MAC_VER_10: |
|
3706 case RTL_GIGA_MAC_VER_16: |
|
3707 case RTL_GIGA_MAC_VER_29: |
|
3708 case RTL_GIGA_MAC_VER_30: |
|
3709 ops->down = r810x_pll_power_down; |
|
3710 ops->up = r810x_pll_power_up; |
|
3711 break; |
|
3712 |
|
3713 case RTL_GIGA_MAC_VER_11: |
|
3714 case RTL_GIGA_MAC_VER_12: |
|
3715 case RTL_GIGA_MAC_VER_17: |
|
3716 case RTL_GIGA_MAC_VER_18: |
|
3717 case RTL_GIGA_MAC_VER_19: |
|
3718 case RTL_GIGA_MAC_VER_20: |
|
3719 case RTL_GIGA_MAC_VER_21: |
|
3720 case RTL_GIGA_MAC_VER_22: |
|
3721 case RTL_GIGA_MAC_VER_23: |
|
3722 case RTL_GIGA_MAC_VER_24: |
|
3723 case RTL_GIGA_MAC_VER_25: |
|
3724 case RTL_GIGA_MAC_VER_26: |
|
3725 case RTL_GIGA_MAC_VER_27: |
|
3726 case RTL_GIGA_MAC_VER_28: |
|
3727 case RTL_GIGA_MAC_VER_31: |
|
3728 case RTL_GIGA_MAC_VER_32: |
|
3729 case RTL_GIGA_MAC_VER_33: |
|
3730 case RTL_GIGA_MAC_VER_34: |
|
3731 case RTL_GIGA_MAC_VER_35: |
|
3732 case RTL_GIGA_MAC_VER_36: |
|
3733 ops->down = r8168_pll_power_down; |
|
3734 ops->up = r8168_pll_power_up; |
|
3735 break; |
|
3736 |
|
3737 default: |
|
3738 ops->down = NULL; |
|
3739 ops->up = NULL; |
|
3740 break; |
|
3741 } |
|
3742 } |
|
3743 |
|
3744 static void rtl_init_rxcfg(struct rtl8169_private *tp) |
|
3745 { |
|
3746 void __iomem *ioaddr = tp->mmio_addr; |
|
3747 |
|
3748 switch (tp->mac_version) { |
|
3749 case RTL_GIGA_MAC_VER_01: |
|
3750 case RTL_GIGA_MAC_VER_02: |
|
3751 case RTL_GIGA_MAC_VER_03: |
|
3752 case RTL_GIGA_MAC_VER_04: |
|
3753 case RTL_GIGA_MAC_VER_05: |
|
3754 case RTL_GIGA_MAC_VER_06: |
|
3755 case RTL_GIGA_MAC_VER_10: |
|
3756 case RTL_GIGA_MAC_VER_11: |
|
3757 case RTL_GIGA_MAC_VER_12: |
|
3758 case RTL_GIGA_MAC_VER_13: |
|
3759 case RTL_GIGA_MAC_VER_14: |
|
3760 case RTL_GIGA_MAC_VER_15: |
|
3761 case RTL_GIGA_MAC_VER_16: |
|
3762 case RTL_GIGA_MAC_VER_17: |
|
3763 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
|
3764 break; |
|
3765 case RTL_GIGA_MAC_VER_18: |
|
3766 case RTL_GIGA_MAC_VER_19: |
|
3767 case RTL_GIGA_MAC_VER_20: |
|
3768 case RTL_GIGA_MAC_VER_21: |
|
3769 case RTL_GIGA_MAC_VER_22: |
|
3770 case RTL_GIGA_MAC_VER_23: |
|
3771 case RTL_GIGA_MAC_VER_24: |
|
3772 case RTL_GIGA_MAC_VER_34: |
|
3773 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
|
3774 break; |
|
3775 default: |
|
3776 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); |
|
3777 break; |
|
3778 } |
|
3779 } |
|
3780 |
|
3781 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
3782 { |
|
3783 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
3784 } |
|
3785 |
|
3786 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3787 { |
|
3788 void __iomem *ioaddr = tp->mmio_addr; |
|
3789 |
|
3790 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3791 rtl_generic_op(tp, tp->jumbo_ops.enable); |
|
3792 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3793 } |
|
3794 |
|
3795 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3796 { |
|
3797 void __iomem *ioaddr = tp->mmio_addr; |
|
3798 |
|
3799 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3800 rtl_generic_op(tp, tp->jumbo_ops.disable); |
|
3801 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3802 } |
|
3803 |
|
3804 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3805 { |
|
3806 void __iomem *ioaddr = tp->mmio_addr; |
|
3807 |
|
3808 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3809 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); |
|
3810 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
3811 } |
|
3812 |
|
3813 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3814 { |
|
3815 void __iomem *ioaddr = tp->mmio_addr; |
|
3816 |
|
3817 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3818 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); |
|
3819 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3820 } |
|
3821 |
|
3822 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3823 { |
|
3824 void __iomem *ioaddr = tp->mmio_addr; |
|
3825 |
|
3826 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3827 } |
|
3828 |
|
3829 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3830 { |
|
3831 void __iomem *ioaddr = tp->mmio_addr; |
|
3832 |
|
3833 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3834 } |
|
3835 |
|
3836 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3837 { |
|
3838 void __iomem *ioaddr = tp->mmio_addr; |
|
3839 |
|
3840 RTL_W8(MaxTxPacketSize, 0x3f); |
|
3841 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3842 RTL_W8(Config4, RTL_R8(Config4) | 0x01); |
|
3843 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
3844 } |
|
3845 |
|
3846 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3847 { |
|
3848 void __iomem *ioaddr = tp->mmio_addr; |
|
3849 |
|
3850 RTL_W8(MaxTxPacketSize, 0x0c); |
|
3851 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3852 RTL_W8(Config4, RTL_R8(Config4) & ~0x01); |
|
3853 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3854 } |
|
3855 |
|
3856 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3857 { |
|
3858 rtl_tx_performance_tweak(tp->pci_dev, |
|
3859 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3860 } |
|
3861 |
|
3862 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3863 { |
|
3864 rtl_tx_performance_tweak(tp->pci_dev, |
|
3865 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3866 } |
|
3867 |
|
3868 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3869 { |
|
3870 void __iomem *ioaddr = tp->mmio_addr; |
|
3871 |
|
3872 r8168b_0_hw_jumbo_enable(tp); |
|
3873 |
|
3874 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); |
|
3875 } |
|
3876 |
|
3877 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3878 { |
|
3879 void __iomem *ioaddr = tp->mmio_addr; |
|
3880 |
|
3881 r8168b_0_hw_jumbo_disable(tp); |
|
3882 |
|
3883 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
3884 } |
|
3885 |
|
3886 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) |
|
3887 { |
|
3888 struct jumbo_ops *ops = &tp->jumbo_ops; |
|
3889 |
|
3890 switch (tp->mac_version) { |
|
3891 case RTL_GIGA_MAC_VER_11: |
|
3892 ops->disable = r8168b_0_hw_jumbo_disable; |
|
3893 ops->enable = r8168b_0_hw_jumbo_enable; |
|
3894 break; |
|
3895 case RTL_GIGA_MAC_VER_12: |
|
3896 case RTL_GIGA_MAC_VER_17: |
|
3897 ops->disable = r8168b_1_hw_jumbo_disable; |
|
3898 ops->enable = r8168b_1_hw_jumbo_enable; |
|
3899 break; |
|
3900 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ |
|
3901 case RTL_GIGA_MAC_VER_19: |
|
3902 case RTL_GIGA_MAC_VER_20: |
|
3903 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ |
|
3904 case RTL_GIGA_MAC_VER_22: |
|
3905 case RTL_GIGA_MAC_VER_23: |
|
3906 case RTL_GIGA_MAC_VER_24: |
|
3907 case RTL_GIGA_MAC_VER_25: |
|
3908 case RTL_GIGA_MAC_VER_26: |
|
3909 ops->disable = r8168c_hw_jumbo_disable; |
|
3910 ops->enable = r8168c_hw_jumbo_enable; |
|
3911 break; |
|
3912 case RTL_GIGA_MAC_VER_27: |
|
3913 case RTL_GIGA_MAC_VER_28: |
|
3914 ops->disable = r8168dp_hw_jumbo_disable; |
|
3915 ops->enable = r8168dp_hw_jumbo_enable; |
|
3916 break; |
|
3917 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ |
|
3918 case RTL_GIGA_MAC_VER_32: |
|
3919 case RTL_GIGA_MAC_VER_33: |
|
3920 case RTL_GIGA_MAC_VER_34: |
|
3921 ops->disable = r8168e_hw_jumbo_disable; |
|
3922 ops->enable = r8168e_hw_jumbo_enable; |
|
3923 break; |
|
3924 |
|
3925 /* |
|
3926 * No action needed for jumbo frames with 8169. |
|
3927 * No jumbo for 810x at all. |
|
3928 */ |
|
3929 default: |
|
3930 ops->disable = NULL; |
|
3931 ops->enable = NULL; |
|
3932 break; |
|
3933 } |
|
3934 } |
|
3935 |
|
3936 static void rtl_hw_reset(struct rtl8169_private *tp) |
|
3937 { |
|
3938 void __iomem *ioaddr = tp->mmio_addr; |
|
3939 int i; |
|
3940 |
|
3941 /* Soft reset the chip. */ |
|
3942 RTL_W8(ChipCmd, CmdReset); |
|
3943 |
|
3944 /* Check that the chip has finished the reset. */ |
|
3945 for (i = 0; i < 100; i++) { |
|
3946 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3947 break; |
|
3948 udelay(100); |
|
3949 } |
|
3950 } |
|
3951 |
|
3952 static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
|
3953 { |
|
3954 struct rtl_fw *rtl_fw; |
|
3955 const char *name; |
|
3956 int rc = -ENOMEM; |
|
3957 |
|
3958 name = rtl_lookup_firmware_name(tp); |
|
3959 if (!name) |
|
3960 goto out_no_firmware; |
|
3961 |
|
3962 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
|
3963 if (!rtl_fw) |
|
3964 goto err_warn; |
|
3965 |
|
3966 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
|
3967 if (rc < 0) |
|
3968 goto err_free; |
|
3969 |
|
3970 rc = rtl_check_firmware(tp, rtl_fw); |
|
3971 if (rc < 0) |
|
3972 goto err_release_firmware; |
|
3973 |
|
3974 tp->rtl_fw = rtl_fw; |
|
3975 out: |
|
3976 return; |
|
3977 |
|
3978 err_release_firmware: |
|
3979 release_firmware(rtl_fw->fw); |
|
3980 err_free: |
|
3981 kfree(rtl_fw); |
|
3982 err_warn: |
|
3983 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", |
|
3984 name, rc); |
|
3985 out_no_firmware: |
|
3986 tp->rtl_fw = NULL; |
|
3987 goto out; |
|
3988 } |
|
3989 |
|
3990 static void rtl_request_firmware(struct rtl8169_private *tp) |
|
3991 { |
|
3992 if (IS_ERR(tp->rtl_fw)) |
|
3993 rtl_request_uncached_firmware(tp); |
|
3994 } |
|
3995 |
|
3996 static void rtl_rx_close(struct rtl8169_private *tp) |
|
3997 { |
|
3998 void __iomem *ioaddr = tp->mmio_addr; |
|
3999 |
|
4000 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
|
4001 } |
|
4002 |
|
4003 static void rtl8169_hw_reset(struct rtl8169_private *tp) |
|
4004 { |
|
4005 void __iomem *ioaddr = tp->mmio_addr; |
|
4006 |
|
4007 /* Disable interrupts */ |
|
4008 rtl8169_irq_mask_and_ack(tp); |
|
4009 |
|
4010 rtl_rx_close(tp); |
|
4011 |
|
4012 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4013 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4014 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4015 while (RTL_R8(TxPoll) & NPQ) |
|
4016 udelay(20); |
|
4017 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
|
4018 tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
4019 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
4020 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4021 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
|
4022 udelay(100); |
|
4023 } else { |
|
4024 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4025 udelay(100); |
|
4026 } |
|
4027 |
|
4028 rtl_hw_reset(tp); |
|
4029 } |
|
4030 |
|
4031 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
4032 { |
|
4033 void __iomem *ioaddr = tp->mmio_addr; |
|
4034 |
|
4035 /* Set DMA burst size and Interframe Gap Time */ |
|
4036 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4037 (InterFrameGap << TxInterFrameGapShift)); |
|
4038 } |
|
4039 |
|
4040 static void rtl_hw_start(struct net_device *dev) |
|
4041 { |
|
4042 struct rtl8169_private *tp = netdev_priv(dev); |
|
4043 |
|
4044 tp->hw_start(dev); |
|
4045 |
|
4046 if (!tp->ecdev) { |
|
4047 rtl_irq_enable_all(tp); |
|
4048 } |
|
4049 } |
|
4050 |
|
4051 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
4052 void __iomem *ioaddr) |
|
4053 { |
|
4054 /* |
|
4055 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
4056 * register to be written before TxDescAddrLow to work. |
|
4057 * Switching from MMIO to I/O access fixes the issue as well. |
|
4058 */ |
|
4059 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
4060 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
4061 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
4062 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
4063 } |
|
4064 |
|
4065 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
4066 { |
|
4067 u16 cmd; |
|
4068 |
|
4069 cmd = RTL_R16(CPlusCmd); |
|
4070 RTL_W16(CPlusCmd, cmd); |
|
4071 return cmd; |
|
4072 } |
|
4073 |
|
4074 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
4075 { |
|
4076 /* Low hurts. Let's disable the filtering. */ |
|
4077 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
4078 } |
|
4079 |
|
4080 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
4081 { |
|
4082 static const struct rtl_cfg2_info { |
|
4083 u32 mac_version; |
|
4084 u32 clk; |
|
4085 u32 val; |
|
4086 } cfg2_info [] = { |
|
4087 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
4088 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
4089 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
4090 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
4091 }; |
|
4092 const struct rtl_cfg2_info *p = cfg2_info; |
|
4093 unsigned int i; |
|
4094 u32 clk; |
|
4095 |
|
4096 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
4097 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
4098 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
4099 RTL_W32(0x7c, p->val); |
|
4100 break; |
|
4101 } |
|
4102 } |
|
4103 } |
|
4104 |
|
4105 static void rtl_set_rx_mode(struct net_device *dev) |
|
4106 { |
|
4107 struct rtl8169_private *tp = netdev_priv(dev); |
|
4108 void __iomem *ioaddr = tp->mmio_addr; |
|
4109 u32 mc_filter[2]; /* Multicast hash filter */ |
|
4110 int rx_mode; |
|
4111 u32 tmp = 0; |
|
4112 |
|
4113 if (dev->flags & IFF_PROMISC) { |
|
4114 /* Unconditionally log net taps. */ |
|
4115 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
|
4116 rx_mode = |
|
4117 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
4118 AcceptAllPhys; |
|
4119 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4120 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
4121 (dev->flags & IFF_ALLMULTI)) { |
|
4122 /* Too many to filter perfectly -- accept all multicasts. */ |
|
4123 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
4124 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4125 } else { |
|
4126 struct netdev_hw_addr *ha; |
|
4127 |
|
4128 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
4129 mc_filter[1] = mc_filter[0] = 0; |
|
4130 netdev_for_each_mc_addr(ha, dev) { |
|
4131 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
4132 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
4133 rx_mode |= AcceptMulticast; |
|
4134 } |
|
4135 } |
|
4136 |
|
4137 if (dev->features & NETIF_F_RXALL) |
|
4138 rx_mode |= (AcceptErr | AcceptRunt); |
|
4139 |
|
4140 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
|
4141 |
|
4142 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
4143 u32 data = mc_filter[0]; |
|
4144 |
|
4145 mc_filter[0] = swab32(mc_filter[1]); |
|
4146 mc_filter[1] = swab32(data); |
|
4147 } |
|
4148 |
|
4149 if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
|
4150 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4151 |
|
4152 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
4153 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
4154 |
|
4155 RTL_W32(RxConfig, tmp); |
|
4156 } |
|
4157 |
|
4158 static void rtl_hw_start_8169(struct net_device *dev) |
|
4159 { |
|
4160 struct rtl8169_private *tp = netdev_priv(dev); |
|
4161 void __iomem *ioaddr = tp->mmio_addr; |
|
4162 struct pci_dev *pdev = tp->pci_dev; |
|
4163 |
|
4164 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
4165 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
4166 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
4167 } |
|
4168 |
|
4169 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4170 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4171 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4172 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4173 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4174 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4175 |
|
4176 rtl_init_rxcfg(tp); |
|
4177 |
|
4178 RTL_W8(EarlyTxThres, NoEarlyTx); |
|
4179 |
|
4180 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4181 |
|
4182 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4183 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4184 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4185 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4186 rtl_set_rx_tx_config_registers(tp); |
|
4187 |
|
4188 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
4189 |
|
4190 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4191 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
4192 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
4193 "Bit-3 and bit-14 MUST be 1\n"); |
|
4194 tp->cp_cmd |= (1 << 14); |
|
4195 } |
|
4196 |
|
4197 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4198 |
|
4199 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
4200 |
|
4201 /* |
|
4202 * Undocumented corner. Supposedly: |
|
4203 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
4204 */ |
|
4205 RTL_W16(IntrMitigate, 0x0000); |
|
4206 |
|
4207 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4208 |
|
4209 if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
|
4210 tp->mac_version != RTL_GIGA_MAC_VER_02 && |
|
4211 tp->mac_version != RTL_GIGA_MAC_VER_03 && |
|
4212 tp->mac_version != RTL_GIGA_MAC_VER_04) { |
|
4213 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4214 rtl_set_rx_tx_config_registers(tp); |
|
4215 } |
|
4216 |
|
4217 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4218 |
|
4219 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
4220 RTL_R8(IntrMask); |
|
4221 |
|
4222 RTL_W32(RxMissed, 0); |
|
4223 |
|
4224 rtl_set_rx_mode(dev); |
|
4225 |
|
4226 /* no early-rx interrupts */ |
|
4227 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4228 } |
|
4229 |
|
4230 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
|
4231 { |
|
4232 u32 csi; |
|
4233 |
|
4234 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
4235 rtl_csi_write(ioaddr, 0x070c, csi | bits); |
|
4236 } |
|
4237 |
|
4238 static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
|
4239 { |
|
4240 rtl_csi_access_enable(ioaddr, 0x17000000); |
|
4241 } |
|
4242 |
|
4243 static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
|
4244 { |
|
4245 rtl_csi_access_enable(ioaddr, 0x27000000); |
|
4246 } |
|
4247 |
|
4248 struct ephy_info { |
|
4249 unsigned int offset; |
|
4250 u16 mask; |
|
4251 u16 bits; |
|
4252 }; |
|
4253 |
|
4254 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
|
4255 { |
|
4256 u16 w; |
|
4257 |
|
4258 while (len-- > 0) { |
|
4259 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
4260 rtl_ephy_write(ioaddr, e->offset, w); |
|
4261 e++; |
|
4262 } |
|
4263 } |
|
4264 |
|
4265 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
4266 { |
|
4267 int cap = pci_pcie_cap(pdev); |
|
4268 |
|
4269 if (cap) { |
|
4270 u16 ctl; |
|
4271 |
|
4272 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4273 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4274 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4275 } |
|
4276 } |
|
4277 |
|
4278 static void rtl_enable_clock_request(struct pci_dev *pdev) |
|
4279 { |
|
4280 int cap = pci_pcie_cap(pdev); |
|
4281 |
|
4282 if (cap) { |
|
4283 u16 ctl; |
|
4284 |
|
4285 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4286 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4287 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4288 } |
|
4289 } |
|
4290 |
|
4291 #define R8168_CPCMD_QUIRK_MASK (\ |
|
4292 EnableBist | \ |
|
4293 Mac_dbgo_oe | \ |
|
4294 Force_half_dup | \ |
|
4295 Force_rxflow_en | \ |
|
4296 Force_txflow_en | \ |
|
4297 Cxpl_dbg_sel | \ |
|
4298 ASF | \ |
|
4299 PktCntrDisable | \ |
|
4300 Mac_dbgo_sel) |
|
4301 |
|
4302 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4303 { |
|
4304 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4305 |
|
4306 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4307 |
|
4308 rtl_tx_performance_tweak(pdev, |
|
4309 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4310 } |
|
4311 |
|
4312 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4313 { |
|
4314 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4315 |
|
4316 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4317 |
|
4318 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
4319 } |
|
4320 |
|
4321 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4322 { |
|
4323 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
4324 |
|
4325 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4326 |
|
4327 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4328 |
|
4329 rtl_disable_clock_request(pdev); |
|
4330 |
|
4331 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4332 } |
|
4333 |
|
4334 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4335 { |
|
4336 static const struct ephy_info e_info_8168cp[] = { |
|
4337 { 0x01, 0, 0x0001 }, |
|
4338 { 0x02, 0x0800, 0x1000 }, |
|
4339 { 0x03, 0, 0x0042 }, |
|
4340 { 0x06, 0x0080, 0x0000 }, |
|
4341 { 0x07, 0, 0x2000 } |
|
4342 }; |
|
4343 |
|
4344 rtl_csi_access_enable_2(ioaddr); |
|
4345 |
|
4346 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
4347 |
|
4348 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4349 } |
|
4350 |
|
4351 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4352 { |
|
4353 rtl_csi_access_enable_2(ioaddr); |
|
4354 |
|
4355 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4356 |
|
4357 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4358 |
|
4359 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4360 } |
|
4361 |
|
4362 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4363 { |
|
4364 rtl_csi_access_enable_2(ioaddr); |
|
4365 |
|
4366 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4367 |
|
4368 /* Magic. */ |
|
4369 RTL_W8(DBG_REG, 0x20); |
|
4370 |
|
4371 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4372 |
|
4373 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4374 |
|
4375 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4376 } |
|
4377 |
|
4378 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4379 { |
|
4380 static const struct ephy_info e_info_8168c_1[] = { |
|
4381 { 0x02, 0x0800, 0x1000 }, |
|
4382 { 0x03, 0, 0x0002 }, |
|
4383 { 0x06, 0x0080, 0x0000 } |
|
4384 }; |
|
4385 |
|
4386 rtl_csi_access_enable_2(ioaddr); |
|
4387 |
|
4388 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
4389 |
|
4390 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
4391 |
|
4392 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4393 } |
|
4394 |
|
4395 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4396 { |
|
4397 static const struct ephy_info e_info_8168c_2[] = { |
|
4398 { 0x01, 0, 0x0001 }, |
|
4399 { 0x03, 0x0400, 0x0220 } |
|
4400 }; |
|
4401 |
|
4402 rtl_csi_access_enable_2(ioaddr); |
|
4403 |
|
4404 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
4405 |
|
4406 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4407 } |
|
4408 |
|
4409 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4410 { |
|
4411 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4412 } |
|
4413 |
|
4414 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4415 { |
|
4416 rtl_csi_access_enable_2(ioaddr); |
|
4417 |
|
4418 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4419 } |
|
4420 |
|
4421 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4422 { |
|
4423 rtl_csi_access_enable_2(ioaddr); |
|
4424 |
|
4425 rtl_disable_clock_request(pdev); |
|
4426 |
|
4427 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4428 |
|
4429 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4430 |
|
4431 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4432 } |
|
4433 |
|
4434 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4435 { |
|
4436 rtl_csi_access_enable_1(ioaddr); |
|
4437 |
|
4438 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4439 |
|
4440 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4441 |
|
4442 rtl_disable_clock_request(pdev); |
|
4443 } |
|
4444 |
|
4445 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4446 { |
|
4447 static const struct ephy_info e_info_8168d_4[] = { |
|
4448 { 0x0b, ~0, 0x48 }, |
|
4449 { 0x19, 0x20, 0x50 }, |
|
4450 { 0x0c, ~0, 0x20 } |
|
4451 }; |
|
4452 int i; |
|
4453 |
|
4454 rtl_csi_access_enable_1(ioaddr); |
|
4455 |
|
4456 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4457 |
|
4458 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4459 |
|
4460 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { |
|
4461 const struct ephy_info *e = e_info_8168d_4 + i; |
|
4462 u16 w; |
|
4463 |
|
4464 w = rtl_ephy_read(ioaddr, e->offset); |
|
4465 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); |
|
4466 } |
|
4467 |
|
4468 rtl_enable_clock_request(pdev); |
|
4469 } |
|
4470 |
|
4471 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4472 { |
|
4473 static const struct ephy_info e_info_8168e_1[] = { |
|
4474 { 0x00, 0x0200, 0x0100 }, |
|
4475 { 0x00, 0x0000, 0x0004 }, |
|
4476 { 0x06, 0x0002, 0x0001 }, |
|
4477 { 0x06, 0x0000, 0x0030 }, |
|
4478 { 0x07, 0x0000, 0x2000 }, |
|
4479 { 0x00, 0x0000, 0x0020 }, |
|
4480 { 0x03, 0x5800, 0x2000 }, |
|
4481 { 0x03, 0x0000, 0x0001 }, |
|
4482 { 0x01, 0x0800, 0x1000 }, |
|
4483 { 0x07, 0x0000, 0x4000 }, |
|
4484 { 0x1e, 0x0000, 0x2000 }, |
|
4485 { 0x19, 0xffff, 0xfe6c }, |
|
4486 { 0x0a, 0x0000, 0x0040 } |
|
4487 }; |
|
4488 |
|
4489 rtl_csi_access_enable_2(ioaddr); |
|
4490 |
|
4491 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
|
4492 |
|
4493 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4494 |
|
4495 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4496 |
|
4497 rtl_disable_clock_request(pdev); |
|
4498 |
|
4499 /* Reset tx FIFO pointer */ |
|
4500 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
|
4501 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); |
|
4502 |
|
4503 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4504 } |
|
4505 |
|
4506 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4507 { |
|
4508 static const struct ephy_info e_info_8168e_2[] = { |
|
4509 { 0x09, 0x0000, 0x0080 }, |
|
4510 { 0x19, 0x0000, 0x0224 } |
|
4511 }; |
|
4512 |
|
4513 rtl_csi_access_enable_1(ioaddr); |
|
4514 |
|
4515 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
|
4516 |
|
4517 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4518 |
|
4519 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4520 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4521 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4522 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4523 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4524 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); |
|
4525 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4526 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4527 ERIAR_EXGMAC); |
|
4528 |
|
4529 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4530 |
|
4531 rtl_disable_clock_request(pdev); |
|
4532 |
|
4533 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4534 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4535 |
|
4536 /* Adjust EEE LED frequency */ |
|
4537 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4538 |
|
4539 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4540 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4541 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4542 } |
|
4543 |
|
4544 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4545 { |
|
4546 static const struct ephy_info e_info_8168f_1[] = { |
|
4547 { 0x06, 0x00c0, 0x0020 }, |
|
4548 { 0x08, 0x0001, 0x0002 }, |
|
4549 { 0x09, 0x0000, 0x0080 }, |
|
4550 { 0x19, 0x0000, 0x0224 } |
|
4551 }; |
|
4552 |
|
4553 rtl_csi_access_enable_1(ioaddr); |
|
4554 |
|
4555 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
|
4556 |
|
4557 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4558 |
|
4559 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4560 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4561 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4562 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4563 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
4564 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
4565 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4566 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4567 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4568 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); |
|
4569 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4570 ERIAR_EXGMAC); |
|
4571 |
|
4572 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4573 |
|
4574 rtl_disable_clock_request(pdev); |
|
4575 |
|
4576 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4577 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4578 |
|
4579 /* Adjust EEE LED frequency */ |
|
4580 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4581 |
|
4582 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4583 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4584 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4585 } |
|
4586 |
|
4587 static void rtl_hw_start_8168(struct net_device *dev) |
|
4588 { |
|
4589 struct rtl8169_private *tp = netdev_priv(dev); |
|
4590 void __iomem *ioaddr = tp->mmio_addr; |
|
4591 struct pci_dev *pdev = tp->pci_dev; |
|
4592 |
|
4593 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4594 |
|
4595 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4596 |
|
4597 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4598 |
|
4599 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
4600 |
|
4601 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4602 |
|
4603 RTL_W16(IntrMitigate, 0x5151); |
|
4604 |
|
4605 /* Work around for RxFIFO overflow. */ |
|
4606 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
4607 tp->event_slow |= RxFIFOOver | PCSTimeout; |
|
4608 tp->event_slow &= ~RxOverflow; |
|
4609 } |
|
4610 |
|
4611 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4612 |
|
4613 rtl_set_rx_mode(dev); |
|
4614 |
|
4615 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4616 (InterFrameGap << TxInterFrameGapShift)); |
|
4617 |
|
4618 RTL_R8(IntrMask); |
|
4619 |
|
4620 switch (tp->mac_version) { |
|
4621 case RTL_GIGA_MAC_VER_11: |
|
4622 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4623 break; |
|
4624 |
|
4625 case RTL_GIGA_MAC_VER_12: |
|
4626 case RTL_GIGA_MAC_VER_17: |
|
4627 rtl_hw_start_8168bef(ioaddr, pdev); |
|
4628 break; |
|
4629 |
|
4630 case RTL_GIGA_MAC_VER_18: |
|
4631 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
4632 break; |
|
4633 |
|
4634 case RTL_GIGA_MAC_VER_19: |
|
4635 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
4636 break; |
|
4637 |
|
4638 case RTL_GIGA_MAC_VER_20: |
|
4639 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4640 break; |
|
4641 |
|
4642 case RTL_GIGA_MAC_VER_21: |
|
4643 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
4644 break; |
|
4645 |
|
4646 case RTL_GIGA_MAC_VER_22: |
|
4647 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
4648 break; |
|
4649 |
|
4650 case RTL_GIGA_MAC_VER_23: |
|
4651 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
4652 break; |
|
4653 |
|
4654 case RTL_GIGA_MAC_VER_24: |
|
4655 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
4656 break; |
|
4657 |
|
4658 case RTL_GIGA_MAC_VER_25: |
|
4659 case RTL_GIGA_MAC_VER_26: |
|
4660 case RTL_GIGA_MAC_VER_27: |
|
4661 rtl_hw_start_8168d(ioaddr, pdev); |
|
4662 break; |
|
4663 |
|
4664 case RTL_GIGA_MAC_VER_28: |
|
4665 rtl_hw_start_8168d_4(ioaddr, pdev); |
|
4666 break; |
|
4667 |
|
4668 case RTL_GIGA_MAC_VER_31: |
|
4669 rtl_hw_start_8168dp(ioaddr, pdev); |
|
4670 break; |
|
4671 |
|
4672 case RTL_GIGA_MAC_VER_32: |
|
4673 case RTL_GIGA_MAC_VER_33: |
|
4674 rtl_hw_start_8168e_1(ioaddr, pdev); |
|
4675 break; |
|
4676 case RTL_GIGA_MAC_VER_34: |
|
4677 rtl_hw_start_8168e_2(ioaddr, pdev); |
|
4678 break; |
|
4679 |
|
4680 case RTL_GIGA_MAC_VER_35: |
|
4681 case RTL_GIGA_MAC_VER_36: |
|
4682 rtl_hw_start_8168f_1(ioaddr, pdev); |
|
4683 break; |
|
4684 |
|
4685 default: |
|
4686 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
4687 dev->name, tp->mac_version); |
|
4688 break; |
|
4689 } |
|
4690 |
|
4691 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4692 |
|
4693 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4694 |
|
4695 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4696 } |
|
4697 |
|
4698 #define R810X_CPCMD_QUIRK_MASK (\ |
|
4699 EnableBist | \ |
|
4700 Mac_dbgo_oe | \ |
|
4701 Force_half_dup | \ |
|
4702 Force_rxflow_en | \ |
|
4703 Force_txflow_en | \ |
|
4704 Cxpl_dbg_sel | \ |
|
4705 ASF | \ |
|
4706 PktCntrDisable | \ |
|
4707 Mac_dbgo_sel) |
|
4708 |
|
4709 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4710 { |
|
4711 static const struct ephy_info e_info_8102e_1[] = { |
|
4712 { 0x01, 0, 0x6e65 }, |
|
4713 { 0x02, 0, 0x091f }, |
|
4714 { 0x03, 0, 0xc2f9 }, |
|
4715 { 0x06, 0, 0xafb5 }, |
|
4716 { 0x07, 0, 0x0e00 }, |
|
4717 { 0x19, 0, 0xec80 }, |
|
4718 { 0x01, 0, 0x2e65 }, |
|
4719 { 0x01, 0, 0x6e65 } |
|
4720 }; |
|
4721 u8 cfg1; |
|
4722 |
|
4723 rtl_csi_access_enable_2(ioaddr); |
|
4724 |
|
4725 RTL_W8(DBG_REG, FIX_NAK_1); |
|
4726 |
|
4727 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4728 |
|
4729 RTL_W8(Config1, |
|
4730 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
4731 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4732 |
|
4733 cfg1 = RTL_R8(Config1); |
|
4734 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
4735 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
4736 |
|
4737 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
4738 } |
|
4739 |
|
4740 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4741 { |
|
4742 rtl_csi_access_enable_2(ioaddr); |
|
4743 |
|
4744 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4745 |
|
4746 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
4747 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4748 } |
|
4749 |
|
4750 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4751 { |
|
4752 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
4753 |
|
4754 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
4755 } |
|
4756 |
|
4757 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4758 { |
|
4759 static const struct ephy_info e_info_8105e_1[] = { |
|
4760 { 0x07, 0, 0x4000 }, |
|
4761 { 0x19, 0, 0x0200 }, |
|
4762 { 0x19, 0, 0x0020 }, |
|
4763 { 0x1e, 0, 0x2000 }, |
|
4764 { 0x03, 0, 0x0001 }, |
|
4765 { 0x19, 0, 0x0100 }, |
|
4766 { 0x19, 0, 0x0004 }, |
|
4767 { 0x0a, 0, 0x0020 } |
|
4768 }; |
|
4769 |
|
4770 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
4771 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
4772 |
|
4773 /* Disable Early Tally Counter */ |
|
4774 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
|
4775 |
|
4776 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
|
4777 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4778 |
|
4779 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
|
4780 } |
|
4781 |
|
4782 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4783 { |
|
4784 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
4785 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); |
|
4786 } |
|
4787 |
|
4788 static void rtl_hw_start_8101(struct net_device *dev) |
|
4789 { |
|
4790 struct rtl8169_private *tp = netdev_priv(dev); |
|
4791 void __iomem *ioaddr = tp->mmio_addr; |
|
4792 struct pci_dev *pdev = tp->pci_dev; |
|
4793 |
|
4794 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
|
4795 tp->event_slow &= ~RxFIFOOver; |
|
4796 |
|
4797 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
|
4798 tp->mac_version == RTL_GIGA_MAC_VER_16) { |
|
4799 int cap = pci_pcie_cap(pdev); |
|
4800 |
|
4801 if (cap) { |
|
4802 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
4803 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4804 } |
|
4805 } |
|
4806 |
|
4807 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4808 |
|
4809 switch (tp->mac_version) { |
|
4810 case RTL_GIGA_MAC_VER_07: |
|
4811 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
4812 break; |
|
4813 |
|
4814 case RTL_GIGA_MAC_VER_08: |
|
4815 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
4816 break; |
|
4817 |
|
4818 case RTL_GIGA_MAC_VER_09: |
|
4819 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
4820 break; |
|
4821 |
|
4822 case RTL_GIGA_MAC_VER_29: |
|
4823 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
4824 break; |
|
4825 case RTL_GIGA_MAC_VER_30: |
|
4826 rtl_hw_start_8105e_2(ioaddr, pdev); |
|
4827 break; |
|
4828 } |
|
4829 |
|
4830 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4831 |
|
4832 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4833 |
|
4834 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4835 |
|
4836 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
|
4837 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4838 |
|
4839 RTL_W16(IntrMitigate, 0x0000); |
|
4840 |
|
4841 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4842 |
|
4843 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4844 rtl_set_rx_tx_config_registers(tp); |
|
4845 |
|
4846 RTL_R8(IntrMask); |
|
4847 |
|
4848 rtl_set_rx_mode(dev); |
|
4849 |
|
4850 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
4851 } |
|
4852 |
|
4853 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
4854 { |
|
4855 struct rtl8169_private *tp = netdev_priv(dev); |
|
4856 |
|
4857 if (new_mtu < ETH_ZLEN || |
|
4858 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) |
|
4859 return -EINVAL; |
|
4860 |
|
4861 if (new_mtu > ETH_DATA_LEN) |
|
4862 rtl_hw_jumbo_enable(tp); |
|
4863 else |
|
4864 rtl_hw_jumbo_disable(tp); |
|
4865 |
|
4866 dev->mtu = new_mtu; |
|
4867 netdev_update_features(dev); |
|
4868 |
|
4869 return 0; |
|
4870 } |
|
4871 |
|
4872 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
4873 { |
|
4874 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
4875 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
4876 } |
|
4877 |
|
4878 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
|
4879 void **data_buff, struct RxDesc *desc) |
|
4880 { |
|
4881 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
|
4882 DMA_FROM_DEVICE); |
|
4883 |
|
4884 kfree(*data_buff); |
|
4885 *data_buff = NULL; |
|
4886 rtl8169_make_unusable_by_asic(desc); |
|
4887 } |
|
4888 |
|
4889 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
4890 { |
|
4891 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
4892 |
|
4893 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
4894 } |
|
4895 |
|
4896 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
4897 u32 rx_buf_sz) |
|
4898 { |
|
4899 desc->addr = cpu_to_le64(mapping); |
|
4900 wmb(); |
|
4901 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
4902 } |
|
4903 |
|
4904 static inline void *rtl8169_align(void *data) |
|
4905 { |
|
4906 return (void *)ALIGN((long)data, 16); |
|
4907 } |
|
4908 |
|
4909 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
|
4910 struct RxDesc *desc) |
|
4911 { |
|
4912 void *data; |
|
4913 dma_addr_t mapping; |
|
4914 struct device *d = &tp->pci_dev->dev; |
|
4915 struct net_device *dev = tp->dev; |
|
4916 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
|
4917 |
|
4918 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
|
4919 if (!data) |
|
4920 return NULL; |
|
4921 |
|
4922 if (rtl8169_align(data) != data) { |
|
4923 kfree(data); |
|
4924 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); |
|
4925 if (!data) |
|
4926 return NULL; |
|
4927 } |
|
4928 |
|
4929 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
|
4930 DMA_FROM_DEVICE); |
|
4931 if (unlikely(dma_mapping_error(d, mapping))) { |
|
4932 if (net_ratelimit()) |
|
4933 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); |
|
4934 goto err_out; |
|
4935 } |
|
4936 |
|
4937 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
4938 return data; |
|
4939 |
|
4940 err_out: |
|
4941 kfree(data); |
|
4942 return NULL; |
|
4943 } |
|
4944 |
|
4945 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
4946 { |
|
4947 unsigned int i; |
|
4948 |
|
4949 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4950 if (tp->Rx_databuff[i]) { |
|
4951 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, |
|
4952 tp->RxDescArray + i); |
|
4953 } |
|
4954 } |
|
4955 } |
|
4956 |
|
4957 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
4958 { |
|
4959 desc->opts1 |= cpu_to_le32(RingEnd); |
|
4960 } |
|
4961 |
|
4962 static int rtl8169_rx_fill(struct rtl8169_private *tp) |
|
4963 { |
|
4964 unsigned int i; |
|
4965 |
|
4966 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4967 void *data; |
|
4968 |
|
4969 if (tp->Rx_databuff[i]) |
|
4970 continue; |
|
4971 |
|
4972 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
|
4973 if (!data) { |
|
4974 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); |
|
4975 goto err_out; |
|
4976 } |
|
4977 tp->Rx_databuff[i] = data; |
|
4978 } |
|
4979 |
|
4980 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
4981 return 0; |
|
4982 |
|
4983 err_out: |
|
4984 rtl8169_rx_clear(tp); |
|
4985 return -ENOMEM; |
|
4986 } |
|
4987 |
|
4988 static int rtl8169_init_ring(struct net_device *dev) |
|
4989 { |
|
4990 struct rtl8169_private *tp = netdev_priv(dev); |
|
4991 |
|
4992 rtl8169_init_ring_indexes(tp); |
|
4993 |
|
4994 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
4995 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
|
4996 |
|
4997 return rtl8169_rx_fill(tp); |
|
4998 } |
|
4999 |
|
5000 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
|
5001 struct TxDesc *desc) |
|
5002 { |
|
5003 unsigned int len = tx_skb->len; |
|
5004 |
|
5005 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
|
5006 |
|
5007 desc->opts1 = 0x00; |
|
5008 desc->opts2 = 0x00; |
|
5009 desc->addr = 0x00; |
|
5010 tx_skb->len = 0; |
|
5011 } |
|
5012 |
|
5013 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
|
5014 unsigned int n) |
|
5015 { |
|
5016 unsigned int i; |
|
5017 |
|
5018 for (i = 0; i < n; i++) { |
|
5019 unsigned int entry = (start + i) % NUM_TX_DESC; |
|
5020 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5021 unsigned int len = tx_skb->len; |
|
5022 |
|
5023 if (len) { |
|
5024 struct sk_buff *skb = tx_skb->skb; |
|
5025 |
|
5026 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5027 tp->TxDescArray + entry); |
|
5028 if (skb) { |
|
5029 tp->dev->stats.tx_dropped++; |
|
5030 if (!tp->ecdev) { |
|
5031 dev_kfree_skb(skb); |
|
5032 } |
|
5033 tx_skb->skb = NULL; |
|
5034 } |
|
5035 } |
|
5036 } |
|
5037 } |
|
5038 |
|
5039 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
5040 { |
|
5041 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); |
|
5042 tp->cur_tx = tp->dirty_tx = 0; |
|
5043 } |
|
5044 |
|
5045 static void rtl_reset_work(struct rtl8169_private *tp) |
|
5046 { |
|
5047 struct net_device *dev = tp->dev; |
|
5048 int i; |
|
5049 |
|
5050 napi_disable(&tp->napi); |
|
5051 netif_stop_queue(dev); |
|
5052 synchronize_sched(); |
|
5053 |
|
5054 rtl8169_hw_reset(tp); |
|
5055 |
|
5056 for (i = 0; i < NUM_RX_DESC; i++) |
|
5057 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); |
|
5058 |
|
5059 rtl8169_tx_clear(tp); |
|
5060 rtl8169_init_ring_indexes(tp); |
|
5061 |
|
5062 napi_enable(&tp->napi); |
|
5063 rtl_hw_start(dev); |
|
5064 netif_wake_queue(dev); |
|
5065 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
5066 } |
|
5067 |
|
5068 static void rtl8169_tx_timeout(struct net_device *dev) |
|
5069 { |
|
5070 struct rtl8169_private *tp = netdev_priv(dev); |
|
5071 |
|
5072 if (!tp->ecdev) { |
|
5073 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5074 } |
|
5075 } |
|
5076 |
|
5077 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
5078 u32 *opts) |
|
5079 { |
|
5080 struct skb_shared_info *info = skb_shinfo(skb); |
|
5081 unsigned int cur_frag, entry; |
|
5082 struct TxDesc * uninitialized_var(txd); |
|
5083 struct device *d = &tp->pci_dev->dev; |
|
5084 |
|
5085 entry = tp->cur_tx; |
|
5086 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
5087 const skb_frag_t *frag = info->frags + cur_frag; |
|
5088 dma_addr_t mapping; |
|
5089 u32 status, len; |
|
5090 void *addr; |
|
5091 |
|
5092 entry = (entry + 1) % NUM_TX_DESC; |
|
5093 |
|
5094 txd = tp->TxDescArray + entry; |
|
5095 len = skb_frag_size(frag); |
|
5096 addr = skb_frag_address(frag); |
|
5097 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
|
5098 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5099 if (net_ratelimit()) |
|
5100 netif_err(tp, drv, tp->dev, |
|
5101 "Failed to map TX fragments DMA!\n"); |
|
5102 goto err_out; |
|
5103 } |
|
5104 |
|
5105 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5106 status = opts[0] | len | |
|
5107 (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5108 |
|
5109 txd->opts1 = cpu_to_le32(status); |
|
5110 txd->opts2 = cpu_to_le32(opts[1]); |
|
5111 txd->addr = cpu_to_le64(mapping); |
|
5112 |
|
5113 tp->tx_skb[entry].len = len; |
|
5114 } |
|
5115 |
|
5116 if (cur_frag) { |
|
5117 tp->tx_skb[entry].skb = skb; |
|
5118 txd->opts1 |= cpu_to_le32(LastFrag); |
|
5119 } |
|
5120 |
|
5121 return cur_frag; |
|
5122 |
|
5123 err_out: |
|
5124 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); |
|
5125 return -EIO; |
|
5126 } |
|
5127 |
|
5128 static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
|
5129 struct sk_buff *skb, u32 *opts) |
|
5130 { |
|
5131 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
|
5132 u32 mss = skb_shinfo(skb)->gso_size; |
|
5133 int offset = info->opts_offset; |
|
5134 |
|
5135 if (mss) { |
|
5136 opts[0] |= TD_LSO; |
|
5137 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; |
|
5138 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
5139 const struct iphdr *ip = ip_hdr(skb); |
|
5140 |
|
5141 if (ip->protocol == IPPROTO_TCP) |
|
5142 opts[offset] |= info->checksum.tcp; |
|
5143 else if (ip->protocol == IPPROTO_UDP) |
|
5144 opts[offset] |= info->checksum.udp; |
|
5145 else |
|
5146 WARN_ON_ONCE(1); |
|
5147 } |
|
5148 } |
|
5149 |
|
5150 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
5151 struct net_device *dev) |
|
5152 { |
|
5153 struct rtl8169_private *tp = netdev_priv(dev); |
|
5154 unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
|
5155 struct TxDesc *txd = tp->TxDescArray + entry; |
|
5156 void __iomem *ioaddr = tp->mmio_addr; |
|
5157 struct device *d = &tp->pci_dev->dev; |
|
5158 dma_addr_t mapping; |
|
5159 u32 status, len; |
|
5160 u32 opts[2]; |
|
5161 int frags; |
|
5162 |
|
5163 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
|
5164 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
|
5165 goto err_stop_0; |
|
5166 } |
|
5167 |
|
5168 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
5169 goto err_stop_0; |
|
5170 |
|
5171 len = skb_headlen(skb); |
|
5172 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
|
5173 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5174 if (net_ratelimit()) |
|
5175 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); |
|
5176 goto err_dma_0; |
|
5177 } |
|
5178 |
|
5179 tp->tx_skb[entry].len = len; |
|
5180 txd->addr = cpu_to_le64(mapping); |
|
5181 |
|
5182 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
5183 opts[0] = DescOwn; |
|
5184 |
|
5185 rtl8169_tso_csum(tp, skb, opts); |
|
5186 |
|
5187 frags = rtl8169_xmit_frags(tp, skb, opts); |
|
5188 if (frags < 0) |
|
5189 goto err_dma_1; |
|
5190 else if (frags) |
|
5191 opts[0] |= FirstFrag; |
|
5192 else { |
|
5193 opts[0] |= FirstFrag | LastFrag; |
|
5194 tp->tx_skb[entry].skb = skb; |
|
5195 } |
|
5196 |
|
5197 txd->opts2 = cpu_to_le32(opts[1]); |
|
5198 |
|
5199 skb_tx_timestamp(skb); |
|
5200 |
|
5201 wmb(); |
|
5202 |
|
5203 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5204 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5205 txd->opts1 = cpu_to_le32(status); |
|
5206 |
|
5207 tp->cur_tx += frags + 1; |
|
5208 |
|
5209 wmb(); |
|
5210 |
|
5211 RTL_W8(TxPoll, NPQ); |
|
5212 |
|
5213 mmiowb(); |
|
5214 |
|
5215 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5216 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
|
5217 * not miss a ring update when it notices a stopped queue. |
|
5218 */ |
|
5219 smp_wmb(); |
|
5220 if (!tp->ecdev) { |
|
5221 netif_stop_queue(dev); |
|
5222 } |
|
5223 /* Sync with rtl_tx: |
|
5224 * - publish queue status and cur_tx ring index (write barrier) |
|
5225 * - refresh dirty_tx ring index (read barrier). |
|
5226 * May the current thread have a pessimistic view of the ring |
|
5227 * status and forget to wake up queue, a racing rtl_tx thread |
|
5228 * can't. |
|
5229 */ |
|
5230 smp_mb(); |
|
5231 if (!tp->ecdev && TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
|
5232 netif_wake_queue(dev); |
|
5233 } |
|
5234 |
|
5235 return NETDEV_TX_OK; |
|
5236 |
|
5237 err_dma_1: |
|
5238 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
|
5239 err_dma_0: |
|
5240 if (!tp->ecdev) { |
|
5241 dev_kfree_skb(skb); |
|
5242 } |
|
5243 dev->stats.tx_dropped++; |
|
5244 return NETDEV_TX_OK; |
|
5245 |
|
5246 err_stop_0: |
|
5247 if (!tp->ecdev) { |
|
5248 netif_stop_queue(dev); |
|
5249 } |
|
5250 dev->stats.tx_dropped++; |
|
5251 return NETDEV_TX_BUSY; |
|
5252 } |
|
5253 |
|
5254 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
5255 { |
|
5256 struct rtl8169_private *tp = netdev_priv(dev); |
|
5257 struct pci_dev *pdev = tp->pci_dev; |
|
5258 u16 pci_status, pci_cmd; |
|
5259 |
|
5260 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
5261 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
5262 |
|
5263 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
|
5264 pci_cmd, pci_status); |
|
5265 |
|
5266 /* |
|
5267 * The recovery sequence below admits a very elaborated explanation: |
|
5268 * - it seems to work; |
|
5269 * - I did not see what else could be done; |
|
5270 * - it makes iop3xx happy. |
|
5271 * |
|
5272 * Feel free to adjust to your needs. |
|
5273 */ |
|
5274 if (pdev->broken_parity_status) |
|
5275 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
5276 else |
|
5277 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
5278 |
|
5279 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
5280 |
|
5281 pci_write_config_word(pdev, PCI_STATUS, |
|
5282 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
5283 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
5284 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
5285 |
|
5286 /* The infamous DAC f*ckup only happens at boot time */ |
|
5287 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
5288 void __iomem *ioaddr = tp->mmio_addr; |
|
5289 |
|
5290 netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
|
5291 tp->cp_cmd &= ~PCIDAC; |
|
5292 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5293 dev->features &= ~NETIF_F_HIGHDMA; |
|
5294 } |
|
5295 |
|
5296 rtl8169_hw_reset(tp); |
|
5297 |
|
5298 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5299 } |
|
5300 |
|
5301 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
|
5302 { |
|
5303 unsigned int dirty_tx, tx_left; |
|
5304 |
|
5305 dirty_tx = tp->dirty_tx; |
|
5306 smp_rmb(); |
|
5307 tx_left = tp->cur_tx - dirty_tx; |
|
5308 |
|
5309 while (tx_left > 0) { |
|
5310 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
5311 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5312 u32 status; |
|
5313 |
|
5314 rmb(); |
|
5315 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
5316 if (status & DescOwn) |
|
5317 break; |
|
5318 |
|
5319 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5320 tp->TxDescArray + entry); |
|
5321 if (status & LastFrag) { |
|
5322 u64_stats_update_begin(&tp->tx_stats.syncp); |
|
5323 tp->tx_stats.packets++; |
|
5324 tp->tx_stats.bytes += tx_skb->skb->len; |
|
5325 u64_stats_update_end(&tp->tx_stats.syncp); |
|
5326 if (!tp->ecdev) { |
|
5327 dev_kfree_skb(tx_skb->skb); |
|
5328 } |
|
5329 tx_skb->skb = NULL; |
|
5330 } |
|
5331 dirty_tx++; |
|
5332 tx_left--; |
|
5333 } |
|
5334 |
|
5335 if (tp->dirty_tx != dirty_tx) { |
|
5336 tp->dirty_tx = dirty_tx; |
|
5337 /* Sync with rtl8169_start_xmit: |
|
5338 * - publish dirty_tx ring index (write barrier) |
|
5339 * - refresh cur_tx ring index and queue status (read barrier) |
|
5340 * May the current thread miss the stopped queue condition, |
|
5341 * a racing xmit thread can only have a right view of the |
|
5342 * ring status. |
|
5343 */ |
|
5344 smp_mb(); |
|
5345 if (!tp->ecdev && netif_queue_stopped(dev) && |
|
5346 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5347 netif_wake_queue(dev); |
|
5348 } |
|
5349 /* |
|
5350 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
5351 * too close. Let's kick an extra TxPoll request when a burst |
|
5352 * of start_xmit activity is detected (if it is not detected, |
|
5353 * it is slow enough). -- FR |
|
5354 */ |
|
5355 if (tp->cur_tx != dirty_tx) { |
|
5356 void __iomem *ioaddr = tp->mmio_addr; |
|
5357 |
|
5358 RTL_W8(TxPoll, NPQ); |
|
5359 } |
|
5360 } |
|
5361 } |
|
5362 |
|
5363 static inline int rtl8169_fragmented_frame(u32 status) |
|
5364 { |
|
5365 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
5366 } |
|
5367 |
|
5368 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
|
5369 { |
|
5370 u32 status = opts1 & RxProtoMask; |
|
5371 |
|
5372 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
5373 ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
|
5374 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
5375 else |
|
5376 skb_checksum_none_assert(skb); |
|
5377 } |
|
5378 |
|
5379 static struct sk_buff *rtl8169_try_rx_copy(void *data, |
|
5380 struct rtl8169_private *tp, |
|
5381 int pkt_size, |
|
5382 dma_addr_t addr) |
|
5383 { |
|
5384 struct sk_buff *skb; |
|
5385 struct device *d = &tp->pci_dev->dev; |
|
5386 |
|
5387 data = rtl8169_align(data); |
|
5388 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5389 prefetch(data); |
|
5390 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); |
|
5391 if (skb) |
|
5392 memcpy(skb->data, data, pkt_size); |
|
5393 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5394 |
|
5395 return skb; |
|
5396 } |
|
5397 |
|
5398 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
|
5399 { |
|
5400 unsigned int cur_rx, rx_left; |
|
5401 unsigned int count; |
|
5402 |
|
5403 cur_rx = tp->cur_rx; |
|
5404 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
5405 rx_left = min(rx_left, budget); |
|
5406 |
|
5407 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
5408 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
5409 struct RxDesc *desc = tp->RxDescArray + entry; |
|
5410 u32 status; |
|
5411 |
|
5412 rmb(); |
|
5413 status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
|
5414 |
|
5415 if (status & DescOwn) |
|
5416 break; |
|
5417 if (unlikely(status & RxRES)) { |
|
5418 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
|
5419 status); |
|
5420 dev->stats.rx_errors++; |
|
5421 if (status & (RxRWT | RxRUNT)) |
|
5422 dev->stats.rx_length_errors++; |
|
5423 if (status & RxCRC) |
|
5424 dev->stats.rx_crc_errors++; |
|
5425 if (status & RxFOVF) { |
|
5426 if (!tp->ecdev) { |
|
5427 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5428 } |
|
5429 dev->stats.rx_fifo_errors++; |
|
5430 } |
|
5431 if ((status & (RxRUNT | RxCRC)) && |
|
5432 !(status & (RxRWT | RxFOVF)) && |
|
5433 (dev->features & NETIF_F_RXALL)) |
|
5434 goto process_pkt; |
|
5435 |
|
5436 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5437 } else { |
|
5438 struct sk_buff *skb; |
|
5439 dma_addr_t addr; |
|
5440 int pkt_size; |
|
5441 |
|
5442 process_pkt: |
|
5443 addr = le64_to_cpu(desc->addr); |
|
5444 if (likely(!(dev->features & NETIF_F_RXFCS))) |
|
5445 pkt_size = (status & 0x00003fff) - 4; |
|
5446 else |
|
5447 pkt_size = status & 0x00003fff; |
|
5448 |
|
5449 /* |
|
5450 * The driver does not support incoming fragmented |
|
5451 * frames. They are seen as a symptom of over-mtu |
|
5452 * sized frames. |
|
5453 */ |
|
5454 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
5455 dev->stats.rx_dropped++; |
|
5456 dev->stats.rx_length_errors++; |
|
5457 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5458 continue; |
|
5459 } |
|
5460 |
|
5461 if (tp->ecdev) { |
|
5462 struct device *d = &tp->pci_dev->dev; |
|
5463 |
|
5464 /* reusing parts of rtl8169_try_rx_copy() */ |
|
5465 tp->Rx_databuff[entry] = rtl8169_align(tp->Rx_databuff[entry]); |
|
5466 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5467 prefetch(tp->Rx_databuff[entry]); |
|
5468 |
|
5469 ecdev_receive(tp->ecdev, tp->Rx_databuff[entry], pkt_size); |
|
5470 |
|
5471 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5472 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5473 |
|
5474 rtl8169_rx_csum(tp->Rx_databuff[entry], status); |
|
5475 |
|
5476 // No need to detect link status as |
|
5477 // long as frames are received: Reset watchdog. |
|
5478 tp->ec_watchdog_jiffies = jiffies; |
|
5479 } |
|
5480 else { |
|
5481 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
|
5482 tp, pkt_size, addr); |
|
5483 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5484 if (!skb) { |
|
5485 dev->stats.rx_dropped++; |
|
5486 continue; |
|
5487 } |
|
5488 |
|
5489 rtl8169_rx_csum(skb, status); |
|
5490 skb_put(skb, pkt_size); |
|
5491 skb->protocol = eth_type_trans(skb, dev); |
|
5492 |
|
5493 rtl8169_rx_vlan_tag(desc, skb); |
|
5494 |
|
5495 napi_gro_receive(&tp->napi, skb); |
|
5496 } |
|
5497 |
|
5498 u64_stats_update_begin(&tp->rx_stats.syncp); |
|
5499 tp->rx_stats.packets++; |
|
5500 tp->rx_stats.bytes += pkt_size; |
|
5501 u64_stats_update_end(&tp->rx_stats.syncp); |
|
5502 } |
|
5503 |
|
5504 /* Work around for AMD plateform. */ |
|
5505 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
5506 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
5507 desc->opts2 = 0; |
|
5508 cur_rx++; |
|
5509 } |
|
5510 } |
|
5511 |
|
5512 count = cur_rx - tp->cur_rx; |
|
5513 tp->cur_rx = cur_rx; |
|
5514 |
|
5515 tp->dirty_rx += count; |
|
5516 |
|
5517 return count; |
|
5518 } |
|
5519 |
|
5520 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
5521 { |
|
5522 struct net_device *dev = dev_instance; |
|
5523 struct rtl8169_private *tp = netdev_priv(dev); |
|
5524 int handled = 0; |
|
5525 u16 status; |
|
5526 |
|
5527 status = rtl_get_events(tp); |
|
5528 if (status && status != 0xffff) { |
|
5529 status &= RTL_EVENT_NAPI | tp->event_slow; |
|
5530 if (status) { |
|
5531 handled = 1; |
|
5532 |
|
5533 rtl_irq_disable(tp); |
|
5534 napi_schedule(&tp->napi); |
|
5535 } |
|
5536 } |
|
5537 return IRQ_RETVAL(handled); |
|
5538 } |
|
5539 |
|
5540 /* |
|
5541 * Workqueue context. |
|
5542 */ |
|
5543 static void rtl_slow_event_work(struct rtl8169_private *tp) |
|
5544 { |
|
5545 struct net_device *dev = tp->dev; |
|
5546 u16 status; |
|
5547 |
|
5548 status = rtl_get_events(tp) & tp->event_slow; |
|
5549 rtl_ack_events(tp, status); |
|
5550 |
|
5551 if (unlikely(!tp->ecdev && status & RxFIFOOver)) { |
|
5552 switch (tp->mac_version) { |
|
5553 /* Work around for rx fifo overflow */ |
|
5554 case RTL_GIGA_MAC_VER_11: |
|
5555 netif_stop_queue(dev); |
|
5556 /* XXX - Hack alert. See rtl_task(). */ |
|
5557 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); |
|
5558 default: |
|
5559 break; |
|
5560 } |
|
5561 } |
|
5562 |
|
5563 if (unlikely(!tp->ecdev && status & SYSErr)) |
|
5564 rtl8169_pcierr_interrupt(dev); |
|
5565 |
|
5566 if (status & LinkChg) |
|
5567 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); |
|
5568 |
|
5569 if (!tp->ecdev) { |
|
5570 napi_disable(&tp->napi); |
|
5571 rtl_irq_disable(tp); |
|
5572 |
|
5573 napi_enable(&tp->napi); |
|
5574 napi_schedule(&tp->napi); |
|
5575 } |
|
5576 } |
|
5577 |
|
5578 static void rtl_task(struct work_struct *work) |
|
5579 { |
|
5580 static const struct { |
|
5581 int bitnr; |
|
5582 void (*action)(struct rtl8169_private *); |
|
5583 } rtl_work[] = { |
|
5584 /* XXX - keep rtl_slow_event_work() as first element. */ |
|
5585 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
|
5586 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, |
|
5587 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } |
|
5588 }; |
|
5589 struct rtl8169_private *tp = |
|
5590 container_of(work, struct rtl8169_private, wk.work); |
|
5591 struct net_device *dev = tp->dev; |
|
5592 int i; |
|
5593 |
|
5594 rtl_lock_work(tp); |
|
5595 |
|
5596 if (!netif_running(dev) || |
|
5597 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) |
|
5598 goto out_unlock; |
|
5599 |
|
5600 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { |
|
5601 bool pending; |
|
5602 |
|
5603 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
|
5604 if (pending) |
|
5605 rtl_work[i].action(tp); |
|
5606 } |
|
5607 |
|
5608 out_unlock: |
|
5609 rtl_unlock_work(tp); |
|
5610 } |
|
5611 |
|
5612 static void ec_poll(struct net_device *dev) |
|
5613 { |
|
5614 struct rtl8169_private *tp = netdev_priv(dev); |
|
5615 u16 status; |
|
5616 |
|
5617 status = rtl_get_events(tp); |
|
5618 rtl_ack_events(tp, status & ~tp->event_slow); |
|
5619 |
|
5620 if (status & RTL_EVENT_NAPI_RX) { |
|
5621 rtl_rx(dev, tp, 100); // FIXME |
|
5622 } |
|
5623 |
|
5624 if (status & RTL_EVENT_NAPI_TX) { |
|
5625 rtl_tx(dev, tp); |
|
5626 } |
|
5627 |
|
5628 if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { |
|
5629 void __iomem *ioaddr = tp->mmio_addr; |
|
5630 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
5631 tp->ec_watchdog_jiffies = jiffies; |
|
5632 } |
|
5633 } |
|
5634 |
|
5635 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
5636 { |
|
5637 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
5638 struct net_device *dev = tp->dev; |
|
5639 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
|
5640 int work_done= 0; |
|
5641 u16 status; |
|
5642 |
|
5643 status = rtl_get_events(tp); |
|
5644 rtl_ack_events(tp, status & ~tp->event_slow); |
|
5645 |
|
5646 if (status & RTL_EVENT_NAPI_RX) |
|
5647 work_done = rtl_rx(dev, tp, (u32) budget); |
|
5648 |
|
5649 if (status & RTL_EVENT_NAPI_TX) |
|
5650 rtl_tx(dev, tp); |
|
5651 |
|
5652 if (status & tp->event_slow) { |
|
5653 enable_mask &= ~tp->event_slow; |
|
5654 |
|
5655 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); |
|
5656 } |
|
5657 |
|
5658 if (work_done < budget) { |
|
5659 napi_complete(napi); |
|
5660 |
|
5661 rtl_irq_enable(tp, enable_mask); |
|
5662 mmiowb(); |
|
5663 } |
|
5664 |
|
5665 return work_done; |
|
5666 } |
|
5667 |
|
5668 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
5669 { |
|
5670 struct rtl8169_private *tp = netdev_priv(dev); |
|
5671 |
|
5672 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
5673 return; |
|
5674 |
|
5675 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
5676 RTL_W32(RxMissed, 0); |
|
5677 } |
|
5678 |
|
5679 static void rtl8169_down(struct net_device *dev) |
|
5680 { |
|
5681 struct rtl8169_private *tp = netdev_priv(dev); |
|
5682 void __iomem *ioaddr = tp->mmio_addr; |
|
5683 |
|
5684 if (!tp->ecdev) { |
|
5685 del_timer_sync(&tp->timer); |
|
5686 |
|
5687 napi_disable(&tp->napi); |
|
5688 netif_stop_queue(dev); |
|
5689 } |
|
5690 |
|
5691 rtl8169_hw_reset(tp); |
|
5692 /* |
|
5693 * At this point device interrupts can not be enabled in any function, |
|
5694 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
|
5695 * and napi is disabled (rtl8169_poll). |
|
5696 */ |
|
5697 rtl8169_rx_missed(dev, ioaddr); |
|
5698 |
|
5699 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
5700 synchronize_sched(); |
|
5701 |
|
5702 rtl8169_tx_clear(tp); |
|
5703 |
|
5704 rtl8169_rx_clear(tp); |
|
5705 |
|
5706 rtl_pll_power_down(tp); |
|
5707 } |
|
5708 |
|
5709 static int rtl8169_close(struct net_device *dev) |
|
5710 { |
|
5711 struct rtl8169_private *tp = netdev_priv(dev); |
|
5712 struct pci_dev *pdev = tp->pci_dev; |
|
5713 |
|
5714 pm_runtime_get_sync(&pdev->dev); |
|
5715 |
|
5716 /* Update counters before going down */ |
|
5717 rtl8169_update_counters(dev); |
|
5718 |
|
5719 rtl_lock_work(tp); |
|
5720 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5721 |
|
5722 rtl8169_down(dev); |
|
5723 rtl_unlock_work(tp); |
|
5724 |
|
5725 if (!tp->ecdev) { |
|
5726 free_irq(pdev->irq, dev); |
|
5727 } |
|
5728 |
|
5729 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
5730 tp->RxPhyAddr); |
|
5731 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
5732 tp->TxPhyAddr); |
|
5733 tp->TxDescArray = NULL; |
|
5734 tp->RxDescArray = NULL; |
|
5735 |
|
5736 pm_runtime_put_sync(&pdev->dev); |
|
5737 |
|
5738 return 0; |
|
5739 } |
|
5740 |
|
5741 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
5742 static void rtl8169_netpoll(struct net_device *dev) |
|
5743 { |
|
5744 struct rtl8169_private *tp = netdev_priv(dev); |
|
5745 |
|
5746 rtl8169_interrupt(tp->pci_dev->irq, dev); |
|
5747 } |
|
5748 #endif |
|
5749 |
|
5750 static int rtl_open(struct net_device *dev) |
|
5751 { |
|
5752 struct rtl8169_private *tp = netdev_priv(dev); |
|
5753 void __iomem *ioaddr = tp->mmio_addr; |
|
5754 struct pci_dev *pdev = tp->pci_dev; |
|
5755 int retval = -ENOMEM; |
|
5756 |
|
5757 pm_runtime_get_sync(&pdev->dev); |
|
5758 |
|
5759 /* |
|
5760 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
5761 * dma_alloc_coherent provides more. |
|
5762 */ |
|
5763 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
|
5764 &tp->TxPhyAddr, GFP_KERNEL); |
|
5765 if (!tp->TxDescArray) |
|
5766 goto err_pm_runtime_put; |
|
5767 |
|
5768 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
|
5769 &tp->RxPhyAddr, GFP_KERNEL); |
|
5770 if (!tp->RxDescArray) |
|
5771 goto err_free_tx_0; |
|
5772 |
|
5773 retval = rtl8169_init_ring(dev); |
|
5774 if (retval < 0) |
|
5775 goto err_free_rx_1; |
|
5776 |
|
5777 INIT_WORK(&tp->wk.work, rtl_task); |
|
5778 |
|
5779 smp_mb(); |
|
5780 |
|
5781 rtl_request_firmware(tp); |
|
5782 |
|
5783 if (!tp->ecdev) { |
|
5784 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
5785 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
5786 dev->name, dev); |
|
5787 if (retval < 0) |
|
5788 goto err_release_fw_2; |
|
5789 } |
|
5790 |
|
5791 rtl_lock_work(tp); |
|
5792 |
|
5793 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5794 |
|
5795 if (!tp->ecdev) { |
|
5796 napi_enable(&tp->napi); |
|
5797 } |
|
5798 |
|
5799 rtl8169_init_phy(dev, tp); |
|
5800 |
|
5801 __rtl8169_set_features(dev, dev->features); |
|
5802 |
|
5803 rtl_pll_power_up(tp); |
|
5804 |
|
5805 rtl_hw_start(dev); |
|
5806 |
|
5807 if (!tp->ecdev) { |
|
5808 netif_start_queue(dev); |
|
5809 } |
|
5810 |
|
5811 rtl_unlock_work(tp); |
|
5812 |
|
5813 tp->saved_wolopts = 0; |
|
5814 pm_runtime_put_noidle(&pdev->dev); |
|
5815 |
|
5816 rtl8169_check_link_status(dev, tp, ioaddr); |
|
5817 out: |
|
5818 return retval; |
|
5819 |
|
5820 err_release_fw_2: |
|
5821 rtl_release_firmware(tp); |
|
5822 rtl8169_rx_clear(tp); |
|
5823 err_free_rx_1: |
|
5824 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
5825 tp->RxPhyAddr); |
|
5826 tp->RxDescArray = NULL; |
|
5827 err_free_tx_0: |
|
5828 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
5829 tp->TxPhyAddr); |
|
5830 tp->TxDescArray = NULL; |
|
5831 err_pm_runtime_put: |
|
5832 pm_runtime_put_noidle(&pdev->dev); |
|
5833 goto out; |
|
5834 } |
|
5835 |
|
5836 static struct rtnl_link_stats64 * |
|
5837 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
|
5838 { |
|
5839 struct rtl8169_private *tp = netdev_priv(dev); |
|
5840 void __iomem *ioaddr = tp->mmio_addr; |
|
5841 unsigned int start; |
|
5842 |
|
5843 if (netif_running(dev)) |
|
5844 rtl8169_rx_missed(dev, ioaddr); |
|
5845 |
|
5846 do { |
|
5847 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); |
|
5848 stats->rx_packets = tp->rx_stats.packets; |
|
5849 stats->rx_bytes = tp->rx_stats.bytes; |
|
5850 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); |
|
5851 |
|
5852 |
|
5853 do { |
|
5854 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); |
|
5855 stats->tx_packets = tp->tx_stats.packets; |
|
5856 stats->tx_bytes = tp->tx_stats.bytes; |
|
5857 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); |
|
5858 |
|
5859 stats->rx_dropped = dev->stats.rx_dropped; |
|
5860 stats->tx_dropped = dev->stats.tx_dropped; |
|
5861 stats->rx_length_errors = dev->stats.rx_length_errors; |
|
5862 stats->rx_errors = dev->stats.rx_errors; |
|
5863 stats->rx_crc_errors = dev->stats.rx_crc_errors; |
|
5864 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; |
|
5865 stats->rx_missed_errors = dev->stats.rx_missed_errors; |
|
5866 |
|
5867 return stats; |
|
5868 } |
|
5869 |
|
5870 static void rtl8169_net_suspend(struct net_device *dev) |
|
5871 { |
|
5872 struct rtl8169_private *tp = netdev_priv(dev); |
|
5873 |
|
5874 if (!netif_running(dev)) |
|
5875 return; |
|
5876 |
|
5877 netif_device_detach(dev); |
|
5878 netif_stop_queue(dev); |
|
5879 |
|
5880 rtl_lock_work(tp); |
|
5881 napi_disable(&tp->napi); |
|
5882 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5883 rtl_unlock_work(tp); |
|
5884 |
|
5885 rtl_pll_power_down(tp); |
|
5886 } |
|
5887 |
|
5888 #ifdef CONFIG_PM |
|
5889 |
|
5890 static int rtl8169_suspend(struct device *device) |
|
5891 { |
|
5892 struct pci_dev *pdev = to_pci_dev(device); |
|
5893 struct net_device *dev = pci_get_drvdata(pdev); |
|
5894 struct rtl8169_private *tp = netdev_priv(dev); |
|
5895 |
|
5896 if (tp->ecdev) { |
|
5897 return -EBUSY; |
|
5898 } |
|
5899 |
|
5900 rtl8169_net_suspend(dev); |
|
5901 |
|
5902 return 0; |
|
5903 } |
|
5904 |
|
5905 static void __rtl8169_resume(struct net_device *dev) |
|
5906 { |
|
5907 struct rtl8169_private *tp = netdev_priv(dev); |
|
5908 |
|
5909 netif_device_attach(dev); |
|
5910 |
|
5911 rtl_pll_power_up(tp); |
|
5912 |
|
5913 rtl_lock_work(tp); |
|
5914 napi_enable(&tp->napi); |
|
5915 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5916 rtl_unlock_work(tp); |
|
5917 |
|
5918 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5919 } |
|
5920 |
|
5921 static int rtl8169_resume(struct device *device) |
|
5922 { |
|
5923 struct pci_dev *pdev = to_pci_dev(device); |
|
5924 struct net_device *dev = pci_get_drvdata(pdev); |
|
5925 struct rtl8169_private *tp = netdev_priv(dev); |
|
5926 |
|
5927 if (tp->ecdev) { |
|
5928 return -EBUSY; |
|
5929 } |
|
5930 |
|
5931 rtl8169_init_phy(dev, tp); |
|
5932 |
|
5933 if (netif_running(dev)) |
|
5934 __rtl8169_resume(dev); |
|
5935 |
|
5936 return 0; |
|
5937 } |
|
5938 |
|
5939 static int rtl8169_runtime_suspend(struct device *device) |
|
5940 { |
|
5941 struct pci_dev *pdev = to_pci_dev(device); |
|
5942 struct net_device *dev = pci_get_drvdata(pdev); |
|
5943 struct rtl8169_private *tp = netdev_priv(dev); |
|
5944 |
|
5945 if (tp->ecdev) { |
|
5946 return -EBUSY; |
|
5947 } |
|
5948 |
|
5949 if (!tp->TxDescArray) |
|
5950 return 0; |
|
5951 |
|
5952 rtl_lock_work(tp); |
|
5953 tp->saved_wolopts = __rtl8169_get_wol(tp); |
|
5954 __rtl8169_set_wol(tp, WAKE_ANY); |
|
5955 rtl_unlock_work(tp); |
|
5956 |
|
5957 rtl8169_net_suspend(dev); |
|
5958 |
|
5959 return 0; |
|
5960 } |
|
5961 |
|
5962 static int rtl8169_runtime_resume(struct device *device) |
|
5963 { |
|
5964 struct pci_dev *pdev = to_pci_dev(device); |
|
5965 struct net_device *dev = pci_get_drvdata(pdev); |
|
5966 struct rtl8169_private *tp = netdev_priv(dev); |
|
5967 |
|
5968 if (tp->ecdev) { |
|
5969 return -EBUSY; |
|
5970 } |
|
5971 |
|
5972 if (!tp->TxDescArray) |
|
5973 return 0; |
|
5974 |
|
5975 rtl_lock_work(tp); |
|
5976 __rtl8169_set_wol(tp, tp->saved_wolopts); |
|
5977 tp->saved_wolopts = 0; |
|
5978 rtl_unlock_work(tp); |
|
5979 |
|
5980 rtl8169_init_phy(dev, tp); |
|
5981 |
|
5982 __rtl8169_resume(dev); |
|
5983 |
|
5984 return 0; |
|
5985 } |
|
5986 |
|
5987 static int rtl8169_runtime_idle(struct device *device) |
|
5988 { |
|
5989 struct pci_dev *pdev = to_pci_dev(device); |
|
5990 struct net_device *dev = pci_get_drvdata(pdev); |
|
5991 struct rtl8169_private *tp = netdev_priv(dev); |
|
5992 |
|
5993 return tp->TxDescArray ? -EBUSY : 0; |
|
5994 } |
|
5995 |
|
5996 static const struct dev_pm_ops rtl8169_pm_ops = { |
|
5997 .suspend = rtl8169_suspend, |
|
5998 .resume = rtl8169_resume, |
|
5999 .freeze = rtl8169_suspend, |
|
6000 .thaw = rtl8169_resume, |
|
6001 .poweroff = rtl8169_suspend, |
|
6002 .restore = rtl8169_resume, |
|
6003 .runtime_suspend = rtl8169_runtime_suspend, |
|
6004 .runtime_resume = rtl8169_runtime_resume, |
|
6005 .runtime_idle = rtl8169_runtime_idle, |
|
6006 }; |
|
6007 |
|
6008 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
6009 |
|
6010 #else /* !CONFIG_PM */ |
|
6011 |
|
6012 #define RTL8169_PM_OPS NULL |
|
6013 |
|
6014 #endif /* !CONFIG_PM */ |
|
6015 |
|
6016 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
|
6017 { |
|
6018 void __iomem *ioaddr = tp->mmio_addr; |
|
6019 |
|
6020 /* WoL fails with 8168b when the receiver is disabled. */ |
|
6021 switch (tp->mac_version) { |
|
6022 case RTL_GIGA_MAC_VER_11: |
|
6023 case RTL_GIGA_MAC_VER_12: |
|
6024 case RTL_GIGA_MAC_VER_17: |
|
6025 pci_clear_master(tp->pci_dev); |
|
6026 |
|
6027 RTL_W8(ChipCmd, CmdRxEnb); |
|
6028 /* PCI commit */ |
|
6029 RTL_R8(ChipCmd); |
|
6030 break; |
|
6031 default: |
|
6032 break; |
|
6033 } |
|
6034 } |
|
6035 |
|
6036 static void rtl_shutdown(struct pci_dev *pdev) |
|
6037 { |
|
6038 struct net_device *dev = pci_get_drvdata(pdev); |
|
6039 struct rtl8169_private *tp = netdev_priv(dev); |
|
6040 struct device *d = &pdev->dev; |
|
6041 |
|
6042 pm_runtime_get_sync(d); |
|
6043 |
|
6044 rtl8169_net_suspend(dev); |
|
6045 |
|
6046 /* Restore original MAC address */ |
|
6047 rtl_rar_set(tp, dev->perm_addr); |
|
6048 |
|
6049 rtl8169_hw_reset(tp); |
|
6050 |
|
6051 if (system_state == SYSTEM_POWER_OFF) { |
|
6052 if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
|
6053 rtl_wol_suspend_quirk(tp); |
|
6054 rtl_wol_shutdown_quirk(tp); |
|
6055 } |
|
6056 |
|
6057 pci_wake_from_d3(pdev, true); |
|
6058 pci_set_power_state(pdev, PCI_D3hot); |
|
6059 } |
|
6060 |
|
6061 pm_runtime_put_noidle(d); |
|
6062 } |
|
6063 |
|
6064 static void __devexit rtl_remove_one(struct pci_dev *pdev) |
|
6065 { |
|
6066 struct net_device *dev = pci_get_drvdata(pdev); |
|
6067 struct rtl8169_private *tp = netdev_priv(dev); |
|
6068 |
|
6069 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6070 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6071 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6072 rtl8168_driver_stop(tp); |
|
6073 } |
|
6074 |
|
6075 cancel_work_sync(&tp->wk.work); |
|
6076 |
|
6077 if (tp->ecdev) { |
|
6078 ecdev_close(tp->ecdev); |
|
6079 ecdev_withdraw(tp->ecdev); |
|
6080 } else { |
|
6081 netif_napi_del(&tp->napi); |
|
6082 |
|
6083 unregister_netdev(dev); |
|
6084 } |
|
6085 |
|
6086 rtl_release_firmware(tp); |
|
6087 |
|
6088 if (pci_dev_run_wake(pdev)) |
|
6089 pm_runtime_get_noresume(&pdev->dev); |
|
6090 |
|
6091 /* restore original MAC address */ |
|
6092 rtl_rar_set(tp, dev->perm_addr); |
|
6093 |
|
6094 rtl_disable_msi(pdev, tp); |
|
6095 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
6096 pci_set_drvdata(pdev, NULL); |
|
6097 } |
|
6098 |
|
6099 static const struct net_device_ops rtl_netdev_ops = { |
|
6100 .ndo_open = rtl_open, |
|
6101 .ndo_stop = rtl8169_close, |
|
6102 .ndo_get_stats64 = rtl8169_get_stats64, |
|
6103 .ndo_start_xmit = rtl8169_start_xmit, |
|
6104 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
6105 .ndo_validate_addr = eth_validate_addr, |
|
6106 .ndo_change_mtu = rtl8169_change_mtu, |
|
6107 .ndo_fix_features = rtl8169_fix_features, |
|
6108 .ndo_set_features = rtl8169_set_features, |
|
6109 .ndo_set_mac_address = rtl_set_mac_address, |
|
6110 .ndo_do_ioctl = rtl8169_ioctl, |
|
6111 .ndo_set_rx_mode = rtl_set_rx_mode, |
|
6112 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
6113 .ndo_poll_controller = rtl8169_netpoll, |
|
6114 #endif |
|
6115 |
|
6116 }; |
|
6117 |
|
6118 static const struct rtl_cfg_info { |
|
6119 void (*hw_start)(struct net_device *); |
|
6120 unsigned int region; |
|
6121 unsigned int align; |
|
6122 u16 event_slow; |
|
6123 unsigned features; |
|
6124 u8 default_ver; |
|
6125 } rtl_cfg_infos [] = { |
|
6126 [RTL_CFG_0] = { |
|
6127 .hw_start = rtl_hw_start_8169, |
|
6128 .region = 1, |
|
6129 .align = 0, |
|
6130 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, |
|
6131 .features = RTL_FEATURE_GMII, |
|
6132 .default_ver = RTL_GIGA_MAC_VER_01, |
|
6133 }, |
|
6134 [RTL_CFG_1] = { |
|
6135 .hw_start = rtl_hw_start_8168, |
|
6136 .region = 2, |
|
6137 .align = 8, |
|
6138 .event_slow = SYSErr | LinkChg | RxOverflow, |
|
6139 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
6140 .default_ver = RTL_GIGA_MAC_VER_11, |
|
6141 }, |
|
6142 [RTL_CFG_2] = { |
|
6143 .hw_start = rtl_hw_start_8101, |
|
6144 .region = 2, |
|
6145 .align = 8, |
|
6146 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | |
|
6147 PCSTimeout, |
|
6148 .features = RTL_FEATURE_MSI, |
|
6149 .default_ver = RTL_GIGA_MAC_VER_13, |
|
6150 } |
|
6151 }; |
|
6152 |
|
6153 /* Cfg9346_Unlock assumed. */ |
|
6154 static unsigned rtl_try_msi(struct rtl8169_private *tp, |
|
6155 const struct rtl_cfg_info *cfg) |
|
6156 { |
|
6157 void __iomem *ioaddr = tp->mmio_addr; |
|
6158 unsigned msi = 0; |
|
6159 u8 cfg2; |
|
6160 |
|
6161 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
6162 if (cfg->features & RTL_FEATURE_MSI) { |
|
6163 if (pci_enable_msi(tp->pci_dev)) { |
|
6164 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); |
|
6165 } else { |
|
6166 cfg2 |= MSIEnable; |
|
6167 msi = RTL_FEATURE_MSI; |
|
6168 } |
|
6169 } |
|
6170 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
6171 RTL_W8(Config2, cfg2); |
|
6172 return msi; |
|
6173 } |
|
6174 |
|
6175 static int __devinit |
|
6176 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
6177 { |
|
6178 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
6179 const unsigned int region = cfg->region; |
|
6180 struct rtl8169_private *tp; |
|
6181 struct mii_if_info *mii; |
|
6182 struct net_device *dev; |
|
6183 void __iomem *ioaddr; |
|
6184 int chipset, i; |
|
6185 int rc; |
|
6186 |
|
6187 if (netif_msg_drv(&debug)) { |
|
6188 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
6189 MODULENAME, RTL8169_VERSION); |
|
6190 } |
|
6191 |
|
6192 dev = alloc_etherdev(sizeof (*tp)); |
|
6193 if (!dev) { |
|
6194 rc = -ENOMEM; |
|
6195 goto out; |
|
6196 } |
|
6197 |
|
6198 SET_NETDEV_DEV(dev, &pdev->dev); |
|
6199 dev->netdev_ops = &rtl_netdev_ops; |
|
6200 tp = netdev_priv(dev); |
|
6201 tp->dev = dev; |
|
6202 tp->pci_dev = pdev; |
|
6203 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
6204 |
|
6205 mii = &tp->mii; |
|
6206 mii->dev = dev; |
|
6207 mii->mdio_read = rtl_mdio_read; |
|
6208 mii->mdio_write = rtl_mdio_write; |
|
6209 mii->phy_id_mask = 0x1f; |
|
6210 mii->reg_num_mask = 0x1f; |
|
6211 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
6212 |
|
6213 /* disable ASPM completely as that cause random device stop working |
|
6214 * problems as well as full system hangs for some PCIe devices users */ |
|
6215 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
|
6216 PCIE_LINK_STATE_CLKPM); |
|
6217 |
|
6218 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
6219 rc = pci_enable_device(pdev); |
|
6220 if (rc < 0) { |
|
6221 netif_err(tp, probe, dev, "enable failure\n"); |
|
6222 goto err_out_free_dev_1; |
|
6223 } |
|
6224 |
|
6225 if (pci_set_mwi(pdev) < 0) |
|
6226 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
|
6227 |
|
6228 /* make sure PCI base addr 1 is MMIO */ |
|
6229 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
6230 netif_err(tp, probe, dev, |
|
6231 "region #%d not an MMIO resource, aborting\n", |
|
6232 region); |
|
6233 rc = -ENODEV; |
|
6234 goto err_out_mwi_2; |
|
6235 } |
|
6236 |
|
6237 /* check for weird/broken PCI region reporting */ |
|
6238 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
6239 netif_err(tp, probe, dev, |
|
6240 "Invalid PCI region size(s), aborting\n"); |
|
6241 rc = -ENODEV; |
|
6242 goto err_out_mwi_2; |
|
6243 } |
|
6244 |
|
6245 rc = pci_request_regions(pdev, MODULENAME); |
|
6246 if (rc < 0) { |
|
6247 netif_err(tp, probe, dev, "could not request regions\n"); |
|
6248 goto err_out_mwi_2; |
|
6249 } |
|
6250 |
|
6251 tp->cp_cmd = RxChkSum; |
|
6252 |
|
6253 if ((sizeof(dma_addr_t) > 4) && |
|
6254 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
6255 tp->cp_cmd |= PCIDAC; |
|
6256 dev->features |= NETIF_F_HIGHDMA; |
|
6257 } else { |
|
6258 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
6259 if (rc < 0) { |
|
6260 netif_err(tp, probe, dev, "DMA configuration failed\n"); |
|
6261 goto err_out_free_res_3; |
|
6262 } |
|
6263 } |
|
6264 |
|
6265 /* ioremap MMIO region */ |
|
6266 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
6267 if (!ioaddr) { |
|
6268 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
|
6269 rc = -EIO; |
|
6270 goto err_out_free_res_3; |
|
6271 } |
|
6272 tp->mmio_addr = ioaddr; |
|
6273 |
|
6274 if (!pci_is_pcie(pdev)) |
|
6275 netif_info(tp, probe, dev, "not PCI Express\n"); |
|
6276 |
|
6277 /* Identify chip attached to board */ |
|
6278 rtl8169_get_mac_version(tp, dev, cfg->default_ver); |
|
6279 |
|
6280 rtl_init_rxcfg(tp); |
|
6281 |
|
6282 rtl_irq_disable(tp); |
|
6283 |
|
6284 rtl_hw_reset(tp); |
|
6285 |
|
6286 rtl_ack_events(tp, 0xffff); |
|
6287 |
|
6288 pci_set_master(pdev); |
|
6289 |
|
6290 /* |
|
6291 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
6292 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
6293 */ |
|
6294 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6295 tp->cp_cmd |= RxVlan; |
|
6296 |
|
6297 rtl_init_mdio_ops(tp); |
|
6298 rtl_init_pll_power_ops(tp); |
|
6299 rtl_init_jumbo_ops(tp); |
|
6300 |
|
6301 rtl8169_print_mac_version(tp); |
|
6302 |
|
6303 chipset = tp->mac_version; |
|
6304 tp->txd_version = rtl_chip_infos[chipset].txd_version; |
|
6305 |
|
6306 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
6307 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
6308 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
6309 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
6310 tp->features |= RTL_FEATURE_WOL; |
|
6311 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
6312 tp->features |= RTL_FEATURE_WOL; |
|
6313 tp->features |= rtl_try_msi(tp, cfg); |
|
6314 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
6315 |
|
6316 if (rtl_tbi_enabled(tp)) { |
|
6317 tp->set_speed = rtl8169_set_speed_tbi; |
|
6318 tp->get_settings = rtl8169_gset_tbi; |
|
6319 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
6320 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
6321 tp->link_ok = rtl8169_tbi_link_ok; |
|
6322 tp->do_ioctl = rtl_tbi_ioctl; |
|
6323 } else { |
|
6324 tp->set_speed = rtl8169_set_speed_xmii; |
|
6325 tp->get_settings = rtl8169_gset_xmii; |
|
6326 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
6327 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
6328 tp->link_ok = rtl8169_xmii_link_ok; |
|
6329 tp->do_ioctl = rtl_xmii_ioctl; |
|
6330 } |
|
6331 |
|
6332 mutex_init(&tp->wk.mutex); |
|
6333 |
|
6334 /* Get MAC address */ |
|
6335 for (i = 0; i < ETH_ALEN; i++) |
|
6336 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
6337 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
6338 |
|
6339 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
6340 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
6341 |
|
6342 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
6343 |
|
6344 /* don't enable SG, IP_CSUM and TSO by default - it might not work |
|
6345 * properly for all devices */ |
|
6346 dev->features |= NETIF_F_RXCSUM | |
|
6347 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6348 |
|
6349 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6350 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6351 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6352 NETIF_F_HIGHDMA; |
|
6353 |
|
6354 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6355 /* 8110SCd requires hardware Rx VLAN - disallow toggling */ |
|
6356 dev->hw_features &= ~NETIF_F_HW_VLAN_RX; |
|
6357 |
|
6358 dev->hw_features |= NETIF_F_RXALL; |
|
6359 dev->hw_features |= NETIF_F_RXFCS; |
|
6360 |
|
6361 tp->hw_start = cfg->hw_start; |
|
6362 tp->event_slow = cfg->event_slow; |
|
6363 |
|
6364 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
|
6365 ~(RxBOVF | RxFOVF) : ~0; |
|
6366 |
|
6367 init_timer(&tp->timer); |
|
6368 tp->timer.data = (unsigned long) dev; |
|
6369 tp->timer.function = rtl8169_phy_timer; |
|
6370 |
|
6371 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
6372 |
|
6373 // offer device to EtherCAT master module |
|
6374 tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
6375 tp->ec_watchdog_jiffies = jiffies; |
|
6376 |
|
6377 if (!tp->ecdev) { |
|
6378 rc = register_netdev(dev); |
|
6379 if (rc < 0) |
|
6380 goto err_out_msi_4; |
|
6381 } |
|
6382 |
|
6383 pci_set_drvdata(pdev, dev); |
|
6384 |
|
6385 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
|
6386 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, |
|
6387 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); |
|
6388 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
|
6389 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " |
|
6390 "tx checksumming: %s]\n", |
|
6391 rtl_chip_infos[chipset].jumbo_max, |
|
6392 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); |
|
6393 } |
|
6394 |
|
6395 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6396 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6397 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6398 rtl8168_driver_start(tp); |
|
6399 } |
|
6400 |
|
6401 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
6402 |
|
6403 if (pci_dev_run_wake(pdev)) |
|
6404 pm_runtime_put_noidle(&pdev->dev); |
|
6405 |
|
6406 netif_carrier_off(dev); |
|
6407 |
|
6408 if (tp->ecdev && ecdev_open(tp->ecdev)) { |
|
6409 ecdev_withdraw(tp->ecdev); |
|
6410 goto err_out_msi_4; |
|
6411 } |
|
6412 |
|
6413 out: |
|
6414 return rc; |
|
6415 |
|
6416 err_out_msi_4: |
|
6417 netif_napi_del(&tp->napi); |
|
6418 rtl_disable_msi(pdev, tp); |
|
6419 iounmap(ioaddr); |
|
6420 err_out_free_res_3: |
|
6421 pci_release_regions(pdev); |
|
6422 err_out_mwi_2: |
|
6423 pci_clear_mwi(pdev); |
|
6424 pci_disable_device(pdev); |
|
6425 err_out_free_dev_1: |
|
6426 free_netdev(dev); |
|
6427 goto out; |
|
6428 } |
|
6429 |
|
6430 static struct pci_driver rtl8169_pci_driver = { |
|
6431 .name = MODULENAME, |
|
6432 .id_table = rtl8169_pci_tbl, |
|
6433 .probe = rtl_init_one, |
|
6434 .remove = __devexit_p(rtl_remove_one), |
|
6435 .shutdown = rtl_shutdown, |
|
6436 .driver.pm = RTL8169_PM_OPS, |
|
6437 }; |
|
6438 |
|
6439 static int __init rtl8169_init_module(void) |
|
6440 { |
|
6441 return pci_register_driver(&rtl8169_pci_driver); |
|
6442 } |
|
6443 |
|
6444 static void __exit rtl8169_cleanup_module(void) |
|
6445 { |
|
6446 pci_unregister_driver(&rtl8169_pci_driver); |
|
6447 } |
|
6448 |
|
6449 module_init(rtl8169_init_module); |
|
6450 module_exit(rtl8169_cleanup_module); |