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1 /******************************************************************************* |
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2 |
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3 |
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4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms of the GNU General Public License as published by the Free |
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8 Software Foundation; either version 2 of the License, or (at your option) |
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9 any later version. |
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10 |
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11 This program is distributed in the hope that it will be useful, but WITHOUT |
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12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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14 more details. |
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15 |
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16 You should have received a copy of the GNU General Public License along with |
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17 this program; if not, write to the Free Software Foundation, Inc., 59 |
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18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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19 |
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20 The full GNU General Public License is included in this distribution in the |
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21 file called LICENSE. |
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22 |
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23 Contact Information: |
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24 Linux NICS <linux.nics@intel.com> |
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25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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27 |
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28 *******************************************************************************/ |
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29 |
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30 |
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31 /* glue for the OS independent part of e1000 |
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32 * includes register access macros |
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33 */ |
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34 |
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35 #ifndef _E1000_OSDEP_H_ |
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36 #define _E1000_OSDEP_H_ |
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37 |
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38 #include <linux/types.h> |
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39 #include <linux/pci.h> |
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40 #include <linux/delay.h> |
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41 #include <asm/io.h> |
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42 #include <linux/interrupt.h> |
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43 #include <linux/sched.h> |
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44 |
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45 #ifndef msec_delay |
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46 #define msec_delay(x) do { if(in_interrupt()) { \ |
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47 /* Don't mdelay in interrupt context! */ \ |
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48 BUG(); \ |
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49 } else { \ |
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50 msleep(x); \ |
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51 } } while (0) |
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52 |
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53 /* Some workarounds require millisecond delays and are run during interrupt |
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54 * context. Most notably, when establishing link, the phy may need tweaking |
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55 * but cannot process phy register reads/writes faster than millisecond |
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56 * intervals...and we establish link due to a "link status change" interrupt. |
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57 */ |
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58 #define msec_delay_irq(x) mdelay(x) |
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59 #endif |
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60 |
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61 #define PCI_COMMAND_REGISTER PCI_COMMAND |
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62 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE |
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63 |
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64 typedef enum { |
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65 #undef FALSE |
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66 FALSE = 0, |
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67 #undef TRUE |
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68 TRUE = 1 |
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69 } boolean_t; |
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70 |
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71 #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) |
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72 |
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73 #ifdef DBG |
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74 #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") |
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75 #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) |
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76 #else |
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77 #define DEBUGOUT(S) |
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78 #define DEBUGOUT1(S, A...) |
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79 #endif |
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80 |
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81 #define DEBUGFUNC(F) DEBUGOUT(F) |
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82 #define DEBUGOUT2 DEBUGOUT1 |
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83 #define DEBUGOUT3 DEBUGOUT2 |
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84 #define DEBUGOUT7 DEBUGOUT3 |
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85 |
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86 |
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87 #define E1000_WRITE_REG(a, reg, value) ( \ |
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88 writel((value), ((a)->hw_addr + \ |
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89 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))) |
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90 |
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91 #define E1000_READ_REG(a, reg) ( \ |
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92 readl((a)->hw_addr + \ |
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93 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))) |
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94 |
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95 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ |
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96 writel((value), ((a)->hw_addr + \ |
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97 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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98 ((offset) << 2)))) |
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99 |
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100 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ |
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101 readl((a)->hw_addr + \ |
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102 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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103 ((offset) << 2))) |
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104 |
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105 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY |
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106 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY |
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107 |
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108 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ |
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109 writew((value), ((a)->hw_addr + \ |
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110 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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111 ((offset) << 1)))) |
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112 |
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113 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ |
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114 readw((a)->hw_addr + \ |
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115 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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116 ((offset) << 1))) |
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117 |
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118 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ |
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119 writeb((value), ((a)->hw_addr + \ |
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120 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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121 (offset)))) |
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122 |
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123 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ |
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124 readb((a)->hw_addr + \ |
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125 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
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126 (offset))) |
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127 |
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128 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) |
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129 |
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130 #define E1000_WRITE_ICH8_REG(a, reg, value) ( \ |
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131 writel((value), ((a)->flash_address + reg))) |
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132 |
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133 #define E1000_READ_ICH8_REG(a, reg) ( \ |
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134 readl((a)->flash_address + reg)) |
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135 |
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136 #define E1000_WRITE_ICH8_REG16(a, reg, value) ( \ |
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137 writew((value), ((a)->flash_address + reg))) |
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138 |
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139 #define E1000_READ_ICH8_REG16(a, reg) ( \ |
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140 readw((a)->flash_address + reg)) |
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141 |
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142 |
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143 #endif /* _E1000_OSDEP_H_ */ |