1 /*******************************************************************************

     2 

     3   

     4   Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.

     5   

     6   This program is free software; you can redistribute it and/or modify it 

     7   under the terms of the GNU General Public License as published by the Free 

     8   Software Foundation; either version 2 of the License, or (at your option) 

     9   any later version.

    10   

    11   This program is distributed in the hope that it will be useful, but WITHOUT 

    12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 

    13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 

    14   more details.

    15   

    16   You should have received a copy of the GNU General Public License along with

    17   this program; if not, write to the Free Software Foundation, Inc., 59 

    18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    19   

    20   The full GNU General Public License is included in this distribution in the

    21   file called LICENSE.

    22   

    23   Contact Information:

    24   Linux NICS <linux.nics@intel.com>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 

    30 /* glue for the OS independent part of e1000

    31  * includes register access macros

    32  */

    33 

    34 #ifndef _E1000_OSDEP_H_

    35 #define _E1000_OSDEP_H_

    36 

    37 #include <linux/types.h>

    38 #include <linux/pci.h>

    39 #include <linux/delay.h>

    40 #include <asm/io.h>

    41 #include <linux/interrupt.h>

    42 #include <linux/sched.h>

    43 

    44 #ifndef msec_delay

    45 #define msec_delay(x)	do { if(in_interrupt()) { \

    46 				/* Don't mdelay in interrupt context! */ \

    47 	                	BUG(); \

    48 			} else { \

    49 				msleep(x); \

    50 			} } while(0)

    51 

    52 /* Some workarounds require millisecond delays and are run during interrupt

    53  * context.  Most notably, when establishing link, the phy may need tweaking

    54  * but cannot process phy register reads/writes faster than millisecond

    55  * intervals...and we establish link due to a "link status change" interrupt.

    56  */

    57 #define msec_delay_irq(x) mdelay(x)

    58 #endif

    59 

    60 #define PCI_COMMAND_REGISTER   PCI_COMMAND

    61 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE

    62 

    63 typedef enum {

    64 #undef FALSE

    65     FALSE = 0,

    66 #undef TRUE

    67     TRUE = 1

    68 } boolean_t;

    69 

    70 #define MSGOUT(S, A, B)	printk(KERN_DEBUG S "\n", A, B)

    71 

    72 #ifdef DBG

    73 #define DEBUGOUT(S)		printk(KERN_DEBUG S "\n")

    74 #define DEBUGOUT1(S, A...)	printk(KERN_DEBUG S "\n", A)

    75 #else

    76 #define DEBUGOUT(S)

    77 #define DEBUGOUT1(S, A...)

    78 #endif

    79 

    80 #define DEBUGFUNC(F) DEBUGOUT(F)

    81 #define DEBUGOUT2 DEBUGOUT1

    82 #define DEBUGOUT3 DEBUGOUT2

    83 #define DEBUGOUT7 DEBUGOUT3

    84 

    85 

    86 #define E1000_WRITE_REG(a, reg, value) ( \

    87     writel((value), ((a)->hw_addr + \

    88         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))

    89 

    90 #define E1000_READ_REG(a, reg) ( \

    91     readl((a)->hw_addr + \

    92         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))

    93 

    94 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \

    95     writel((value), ((a)->hw_addr + \

    96         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

    97         ((offset) << 2))))

    98 

    99 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \

   100     readl((a)->hw_addr + \

   101         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

   102         ((offset) << 2)))

   103 

   104 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY

   105 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY

   106 

   107 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \

   108     writew((value), ((a)->hw_addr + \

   109         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

   110         ((offset) << 1))))

   111 

   112 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \

   113     readw((a)->hw_addr + \

   114         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

   115         ((offset) << 1)))

   116 

   117 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \

   118     writeb((value), ((a)->hw_addr + \

   119         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

   120         (offset))))

   121 

   122 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \

   123     readb((a)->hw_addr + \

   124         (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \

   125         (offset)))

   126 

   127 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)

   128 

   129 #endif /* _E1000_OSDEP_H_ */