1 /*******************************************************************************

     2 

     3   

     4   Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.

     5   

     6   This program is free software; you can redistribute it and/or modify it 

     7   under the terms of the GNU General Public License as published by the Free 

     8   Software Foundation; either version 2 of the License, or (at your option) 

     9   any later version.

    10   

    11   This program is distributed in the hope that it will be useful, but WITHOUT 

    12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 

    13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 

    14   more details.

    15   

    16   You should have received a copy of the GNU General Public License along with

    17   this program; if not, write to the Free Software Foundation, Inc., 59 

    18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    19   

    20   The full GNU General Public License is included in this distribution in the

    21   file called LICENSE.

    22   

    23   Contact Information:

    24   Linux NICS <linux.nics@intel.com>

    25   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    26   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    27 

    28 *******************************************************************************/

    29 

    30 /* e1000_hw.c

    31  * Shared functions for accessing and configuring the MAC

    32  */

    33 

    34 #include "e1000_hw-2.6.18-ethercat.h"

    35 

    36 static int32_t e1000_set_phy_type(struct e1000_hw *hw);

    37 static void e1000_phy_init_script(struct e1000_hw *hw);

    38 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);

    39 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    40 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    41 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    42 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);

    43 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    44 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    45 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,

    46                                      uint16_t count);

    47 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    48 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);

    49 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,

    50                                       uint16_t words, uint16_t *data);

    51 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,

    52                                             uint16_t offset, uint16_t words,

    53                                             uint16_t *data);

    54 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);

    55 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    56 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    57 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,

    58                                     uint16_t count);

    59 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,

    60                                       uint16_t phy_data);

    61 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,

    62                                      uint16_t *phy_data);

    63 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);

    64 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);

    65 static void e1000_release_eeprom(struct e1000_hw *hw);

    66 static void e1000_standby_eeprom(struct e1000_hw *hw);

    67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);

    68 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    69 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);

    70 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);

    71 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);

    72 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);

    73 static int32_t e1000_check_downshift(struct e1000_hw *hw);

    74 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);

    75 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    76 static void e1000_clear_vfta(struct e1000_hw *hw);

    77 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);

    78 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    79 						  boolean_t link_up);

    80 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);

    81 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);

    82 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);

    83 static int32_t e1000_get_cable_length(struct e1000_hw *hw,

    84 				      uint16_t *min_length,

    85 				      uint16_t *max_length);

    86 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);

    87 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);

    88 static int32_t e1000_id_led_init(struct e1000_hw * hw);

    89 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    90 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);

    91 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);

    92 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);

    93 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,

    94 				      uint16_t words, uint16_t *data);

    95 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);

    96 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);

    97 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);

    98 

    99 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,

   100 			       uint32_t value);

   101 

   102 #define E1000_WRITE_REG_IO(a, reg, val) \

   103 	    e1000_write_reg_io((a), E1000_##reg, val)

   104 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,

   105                                                uint16_t duplex);

   106 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);

   107 

   108 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,

   109 					   uint32_t segment);

   110 static int32_t e1000_get_software_flag(struct e1000_hw *hw);

   111 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);

   112 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);

   113 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);

   114 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,

   115 				      uint16_t words, uint16_t *data);

   116 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,

   117 				    uint8_t* data);

   118 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,

   119 				    uint16_t *data);

   120 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,

   121 				   uint16_t *data);

   122 static void e1000_release_software_flag(struct e1000_hw *hw);

   123 static void e1000_release_software_semaphore(struct e1000_hw *hw);

   124 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,

   125 					 uint32_t no_snoop);

   126 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,

   127 					    uint32_t index, uint8_t byte);

   128 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,

   129 				       uint16_t words, uint16_t *data);

   130 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,

   131 				     uint8_t data);

   132 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,

   133 				    uint16_t data);

   134 

   135 /* IGP cable length table */

   136 static const

   137 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

   138     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

   139       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

   140       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

   141       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   142       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   143       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   144       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   145       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};

   146 

   147 static const

   148 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =

   149     { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,

   150       0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,

   151       6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,

   152       21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,

   153       40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,

   154       60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,

   155       83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,

   156       104, 109, 114, 118, 121, 124};

   157 

   158 

   159 /******************************************************************************

   160  * Set the phy type member in the hw struct.

   161  *

   162  * hw - Struct containing variables accessed by shared code

   163  *****************************************************************************/

   164 int32_t

   165 e1000_set_phy_type(struct e1000_hw *hw)

   166 {

   167     DEBUGFUNC("e1000_set_phy_type");

   168 

   169     if(hw->mac_type == e1000_undefined)

   170         return -E1000_ERR_PHY_TYPE;

   171 

   172     switch(hw->phy_id) {

   173     case M88E1000_E_PHY_ID:

   174     case M88E1000_I_PHY_ID:

   175     case M88E1011_I_PHY_ID:

   176     case M88E1111_I_PHY_ID:

   177         hw->phy_type = e1000_phy_m88;

   178         break;

   179     case IGP01E1000_I_PHY_ID:

   180         if(hw->mac_type == e1000_82541 ||

   181            hw->mac_type == e1000_82541_rev_2 ||

   182            hw->mac_type == e1000_82547 ||

   183            hw->mac_type == e1000_82547_rev_2) {

   184             hw->phy_type = e1000_phy_igp;

   185             break;

   186         }

   187     case IGP03E1000_E_PHY_ID:

   188         hw->phy_type = e1000_phy_igp_3;

   189         break;

   190     case IFE_E_PHY_ID:

   191     case IFE_PLUS_E_PHY_ID:

   192     case IFE_C_E_PHY_ID:

   193         hw->phy_type = e1000_phy_ife;

   194         break;

   195     case GG82563_E_PHY_ID:

   196         if (hw->mac_type == e1000_80003es2lan) {

   197             hw->phy_type = e1000_phy_gg82563;

   198             break;

   199         }

   200         /* Fall Through */

   201     default:

   202         /* Should never have loaded on this device */

   203         hw->phy_type = e1000_phy_undefined;

   204         return -E1000_ERR_PHY_TYPE;

   205     }

   206 

   207     return E1000_SUCCESS;

   208 }

   209 

   210 /******************************************************************************

   211  * IGP phy init script - initializes the GbE PHY

   212  *

   213  * hw - Struct containing variables accessed by shared code

   214  *****************************************************************************/

   215 static void

   216 e1000_phy_init_script(struct e1000_hw *hw)

   217 {

   218     uint32_t ret_val;

   219     uint16_t phy_saved_data;

   220 

   221     DEBUGFUNC("e1000_phy_init_script");

   222 

   223     if(hw->phy_init_script) {

   224         msec_delay(20);

   225 

   226         /* Save off the current value of register 0x2F5B to be restored at

   227          * the end of this routine. */

   228         ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   229 

   230         /* Disabled the PHY transmitter */

   231         e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   232 

   233         msec_delay(20);

   234 

   235         e1000_write_phy_reg(hw,0x0000,0x0140);

   236 

   237         msec_delay(5);

   238 

   239         switch(hw->mac_type) {

   240         case e1000_82541:

   241         case e1000_82547:

   242             e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   243 

   244             e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   245 

   246             e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   247 

   248             e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   249 

   250             e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   251 

   252             e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   253 

   254             e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   255 

   256             e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   257 

   258             e1000_write_phy_reg(hw, 0x2010, 0x0008);

   259             break;

   260 

   261         case e1000_82541_rev_2:

   262         case e1000_82547_rev_2:

   263             e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   264             break;

   265         default:

   266             break;

   267         }

   268 

   269         e1000_write_phy_reg(hw, 0x0000, 0x3300);

   270 

   271         msec_delay(20);

   272 

   273         /* Now enable the transmitter */

   274         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   275 

   276         if(hw->mac_type == e1000_82547) {

   277             uint16_t fused, fine, coarse;

   278 

   279             /* Move to analog registers page */

   280             e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);

   281 

   282             if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   283                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);

   284 

   285                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   286                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   287 

   288                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   289                     coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;

   290                     fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   291                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   292                     fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   293 

   294                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   295                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   296                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   297 

   298                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);

   299                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,

   300                                     IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   301             }

   302         }

   303     }

   304 }

   305 

   306 /******************************************************************************

   307  * Set the mac type member in the hw struct.

   308  *

   309  * hw - Struct containing variables accessed by shared code

   310  *****************************************************************************/

   311 int32_t

   312 e1000_set_mac_type(struct e1000_hw *hw)

   313 {

   314     DEBUGFUNC("e1000_set_mac_type");

   315 

   316     switch (hw->device_id) {

   317     case E1000_DEV_ID_82542:

   318         switch (hw->revision_id) {

   319         case E1000_82542_2_0_REV_ID:

   320             hw->mac_type = e1000_82542_rev2_0;

   321             break;

   322         case E1000_82542_2_1_REV_ID:

   323             hw->mac_type = e1000_82542_rev2_1;

   324             break;

   325         default:

   326             /* Invalid 82542 revision ID */

   327             return -E1000_ERR_MAC_TYPE;

   328         }

   329         break;

   330     case E1000_DEV_ID_82543GC_FIBER:

   331     case E1000_DEV_ID_82543GC_COPPER:

   332         hw->mac_type = e1000_82543;

   333         break;

   334     case E1000_DEV_ID_82544EI_COPPER:

   335     case E1000_DEV_ID_82544EI_FIBER:

   336     case E1000_DEV_ID_82544GC_COPPER:

   337     case E1000_DEV_ID_82544GC_LOM:

   338         hw->mac_type = e1000_82544;

   339         break;

   340     case E1000_DEV_ID_82540EM:

   341     case E1000_DEV_ID_82540EM_LOM:

   342     case E1000_DEV_ID_82540EP:

   343     case E1000_DEV_ID_82540EP_LOM:

   344     case E1000_DEV_ID_82540EP_LP:

   345         hw->mac_type = e1000_82540;

   346         break;

   347     case E1000_DEV_ID_82545EM_COPPER:

   348     case E1000_DEV_ID_82545EM_FIBER:

   349         hw->mac_type = e1000_82545;

   350         break;

   351     case E1000_DEV_ID_82545GM_COPPER:

   352     case E1000_DEV_ID_82545GM_FIBER:

   353     case E1000_DEV_ID_82545GM_SERDES:

   354         hw->mac_type = e1000_82545_rev_3;

   355         break;

   356     case E1000_DEV_ID_82546EB_COPPER:

   357     case E1000_DEV_ID_82546EB_FIBER:

   358     case E1000_DEV_ID_82546EB_QUAD_COPPER:

   359         hw->mac_type = e1000_82546;

   360         break;

   361     case E1000_DEV_ID_82546GB_COPPER:

   362     case E1000_DEV_ID_82546GB_FIBER:

   363     case E1000_DEV_ID_82546GB_SERDES:

   364     case E1000_DEV_ID_82546GB_PCIE:

   365     case E1000_DEV_ID_82546GB_QUAD_COPPER:

   366     case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   367         hw->mac_type = e1000_82546_rev_3;

   368         break;

   369     case E1000_DEV_ID_82541EI:

   370     case E1000_DEV_ID_82541EI_MOBILE:

   371     case E1000_DEV_ID_82541ER_LOM:

   372         hw->mac_type = e1000_82541;

   373         break;

   374     case E1000_DEV_ID_82541ER:

   375     case E1000_DEV_ID_82541GI:

   376     case E1000_DEV_ID_82541GI_LF:

   377     case E1000_DEV_ID_82541GI_MOBILE:

   378         hw->mac_type = e1000_82541_rev_2;

   379         break;

   380     case E1000_DEV_ID_82547EI:

   381     case E1000_DEV_ID_82547EI_MOBILE:

   382         hw->mac_type = e1000_82547;

   383         break;

   384     case E1000_DEV_ID_82547GI:

   385         hw->mac_type = e1000_82547_rev_2;

   386         break;

   387     case E1000_DEV_ID_82571EB_COPPER:

   388     case E1000_DEV_ID_82571EB_FIBER:

   389     case E1000_DEV_ID_82571EB_SERDES:

   390             hw->mac_type = e1000_82571;

   391         break;

   392     case E1000_DEV_ID_82572EI_COPPER:

   393     case E1000_DEV_ID_82572EI_FIBER:

   394     case E1000_DEV_ID_82572EI_SERDES:

   395     case E1000_DEV_ID_82572EI:

   396         hw->mac_type = e1000_82572;

   397         break;

   398     case E1000_DEV_ID_82573E:

   399     case E1000_DEV_ID_82573E_IAMT:

   400     case E1000_DEV_ID_82573L:

   401         hw->mac_type = e1000_82573;

   402         break;

   403     case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:

   404     case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:

   405     case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:

   406     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   407         hw->mac_type = e1000_80003es2lan;

   408         break;

   409     case E1000_DEV_ID_ICH8_IGP_M_AMT:

   410     case E1000_DEV_ID_ICH8_IGP_AMT:

   411     case E1000_DEV_ID_ICH8_IGP_C:

   412     case E1000_DEV_ID_ICH8_IFE:

   413     case E1000_DEV_ID_ICH8_IGP_M:

   414         hw->mac_type = e1000_ich8lan;

   415         break;

   416     default:

   417         /* Should never have loaded on this device */

   418         return -E1000_ERR_MAC_TYPE;

   419     }

   420 

   421     switch(hw->mac_type) {

   422     case e1000_ich8lan:

   423         hw->swfwhw_semaphore_present = TRUE;

   424         hw->asf_firmware_present = TRUE;

   425         break;

   426     case e1000_80003es2lan:

   427         hw->swfw_sync_present = TRUE;

   428         /* fall through */

   429     case e1000_82571:

   430     case e1000_82572:

   431     case e1000_82573:

   432         hw->eeprom_semaphore_present = TRUE;

   433         /* fall through */

   434     case e1000_82541:

   435     case e1000_82547:

   436     case e1000_82541_rev_2:

   437     case e1000_82547_rev_2:

   438         hw->asf_firmware_present = TRUE;

   439         break;

   440     default:

   441         break;

   442     }

   443 

   444     return E1000_SUCCESS;

   445 }

   446 

   447 /*****************************************************************************

   448  * Set media type and TBI compatibility.

   449  *

   450  * hw - Struct containing variables accessed by shared code

   451  * **************************************************************************/

   452 void

   453 e1000_set_media_type(struct e1000_hw *hw)

   454 {

   455     uint32_t status;

   456 

   457     DEBUGFUNC("e1000_set_media_type");

   458 

   459     if(hw->mac_type != e1000_82543) {

   460         /* tbi_compatibility is only valid on 82543 */

   461         hw->tbi_compatibility_en = FALSE;

   462     }

   463 

   464     switch (hw->device_id) {

   465     case E1000_DEV_ID_82545GM_SERDES:

   466     case E1000_DEV_ID_82546GB_SERDES:

   467     case E1000_DEV_ID_82571EB_SERDES:

   468     case E1000_DEV_ID_82572EI_SERDES:

   469     case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:

   470         hw->media_type = e1000_media_type_internal_serdes;

   471         break;

   472     default:

   473         switch (hw->mac_type) {

   474         case e1000_82542_rev2_0:

   475         case e1000_82542_rev2_1:

   476             hw->media_type = e1000_media_type_fiber;

   477             break;

   478         case e1000_ich8lan:

   479         case e1000_82573:

   480             /* The STATUS_TBIMODE bit is reserved or reused for the this

   481              * device.

   482              */

   483             hw->media_type = e1000_media_type_copper;

   484             break;

   485         default:

   486             status = E1000_READ_REG(hw, STATUS);

   487             if (status & E1000_STATUS_TBIMODE) {

   488                 hw->media_type = e1000_media_type_fiber;

   489                 /* tbi_compatibility not valid on fiber */

   490                 hw->tbi_compatibility_en = FALSE;

   491             } else {

   492                 hw->media_type = e1000_media_type_copper;

   493             }

   494             break;

   495         }

   496     }

   497 }

   498 

   499 /******************************************************************************

   500  * Reset the transmit and receive units; mask and clear all interrupts.

   501  *

   502  * hw - Struct containing variables accessed by shared code

   503  *****************************************************************************/

   504 int32_t

   505 e1000_reset_hw(struct e1000_hw *hw)

   506 {

   507     uint32_t ctrl;

   508     uint32_t ctrl_ext;

   509     uint32_t icr;

   510     uint32_t manc;

   511     uint32_t led_ctrl;

   512     uint32_t timeout;

   513     uint32_t extcnf_ctrl;

   514     int32_t ret_val;

   515 

   516     DEBUGFUNC("e1000_reset_hw");

   517 

   518     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   519     if(hw->mac_type == e1000_82542_rev2_0) {

   520         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   521         e1000_pci_clear_mwi(hw);

   522     }

   523 

   524     if(hw->bus_type == e1000_bus_type_pci_express) {

   525         /* Prevent the PCI-E bus from sticking if there is no TLP connection

   526          * on the last TLP read/write transaction when MAC is reset.

   527          */

   528         if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {

   529             DEBUGOUT("PCI-E Master disable polling has failed.\n");

   530         }

   531     }

   532 

   533     /* Clear interrupt mask to stop board from generating interrupts */

   534     DEBUGOUT("Masking off all interrupts\n");

   535     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   536 

   537     /* Disable the Transmit and Receive units.  Then delay to allow

   538      * any pending transactions to complete before we hit the MAC with

   539      * the global reset.

   540      */

   541     E1000_WRITE_REG(hw, RCTL, 0);

   542     E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);

   543     E1000_WRITE_FLUSH(hw);

   544 

   545     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   546     hw->tbi_compatibility_on = FALSE;

   547 

   548     /* Delay to allow any outstanding PCI transactions to complete before

   549      * resetting the device

   550      */

   551     msec_delay(10);

   552 

   553     ctrl = E1000_READ_REG(hw, CTRL);

   554 

   555     /* Must reset the PHY before resetting the MAC */

   556     if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   557         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));

   558         msec_delay(5);

   559     }

   560 

   561     /* Must acquire the MDIO ownership before MAC reset.

   562      * Ownership defaults to firmware after a reset. */

   563     if(hw->mac_type == e1000_82573) {

   564         timeout = 10;

   565 

   566         extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   567         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   568 

   569         do {

   570             E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);

   571             extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   572 

   573             if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   574                 break;

   575             else

   576                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   577 

   578             msec_delay(2);

   579             timeout--;

   580         } while(timeout);

   581     }

   582 

   583     /* Workaround for ICH8 bit corruption issue in FIFO memory */

   584     if (hw->mac_type == e1000_ich8lan) {

   585         /* Set Tx and Rx buffer allocation to 8k apiece. */

   586         E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);

   587         /* Set Packet Buffer Size to 16k. */

   588         E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);

   589     }

   590 

   591     /* Issue a global reset to the MAC.  This will reset the chip's

   592      * transmit, receive, DMA, and link units.  It will not effect

   593      * the current PCI configuration.  The global reset bit is self-

   594      * clearing, and should clear within a microsecond.

   595      */

   596     DEBUGOUT("Issuing a global reset to MAC\n");

   597 

   598     switch(hw->mac_type) {

   599         case e1000_82544:

   600         case e1000_82540:

   601         case e1000_82545:

   602         case e1000_82546:

   603         case e1000_82541:

   604         case e1000_82541_rev_2:

   605             /* These controllers can't ack the 64-bit write when issuing the

   606              * reset, so use IO-mapping as a workaround to issue the reset */

   607             E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   608             break;

   609         case e1000_82545_rev_3:

   610         case e1000_82546_rev_3:

   611             /* Reset is performed on a shadow of the control register */

   612             E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));

   613             break;

   614         case e1000_ich8lan:

   615             if (!hw->phy_reset_disable &&

   616                 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {

   617                 /* e1000_ich8lan PHY HW reset requires MAC CORE reset

   618                  * at the same time to make sure the interface between

   619                  * MAC and the external PHY is reset.

   620                  */

   621                 ctrl |= E1000_CTRL_PHY_RST;

   622             }

   623 

   624             e1000_get_software_flag(hw);

   625             E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   626             msec_delay(5);

   627             break;

   628         default:

   629             E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   630             break;

   631     }

   632 

   633     /* After MAC reset, force reload of EEPROM to restore power-on settings to

   634      * device.  Later controllers reload the EEPROM automatically, so just wait

   635      * for reload to complete.

   636      */

   637     switch(hw->mac_type) {

   638         case e1000_82542_rev2_0:

   639         case e1000_82542_rev2_1:

   640         case e1000_82543:

   641         case e1000_82544:

   642             /* Wait for reset to complete */

   643             udelay(10);

   644             ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   645             ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   646             E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   647             E1000_WRITE_FLUSH(hw);

   648             /* Wait for EEPROM reload */

   649             msec_delay(2);

   650             break;

   651         case e1000_82541:

   652         case e1000_82541_rev_2:

   653         case e1000_82547:

   654         case e1000_82547_rev_2:

   655             /* Wait for EEPROM reload */

   656             msec_delay(20);

   657             break;

   658         case e1000_82573:

   659             if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {

   660                 udelay(10);

   661                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   662                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   663                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   664                 E1000_WRITE_FLUSH(hw);

   665             }

   666             /* fall through */

   667         case e1000_82571:

   668         case e1000_82572:

   669         case e1000_ich8lan:

   670         case e1000_80003es2lan:

   671             ret_val = e1000_get_auto_rd_done(hw);

   672             if(ret_val)

   673                 /* We don't want to continue accessing MAC registers. */

   674                 return ret_val;

   675             break;

   676         default:

   677             /* Wait for EEPROM reload (it happens automatically) */

   678             msec_delay(5);

   679             break;

   680     }

   681 

   682     /* Disable HW ARPs on ASF enabled adapters */

   683     if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {

   684         manc = E1000_READ_REG(hw, MANC);

   685         manc &= ~(E1000_MANC_ARP_EN);

   686         E1000_WRITE_REG(hw, MANC, manc);

   687     }

   688 

   689     if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   690         e1000_phy_init_script(hw);

   691 

   692         /* Configure activity LED after PHY reset */

   693         led_ctrl = E1000_READ_REG(hw, LEDCTL);

   694         led_ctrl &= IGP_ACTIVITY_LED_MASK;

   695         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   696         E1000_WRITE_REG(hw, LEDCTL, led_ctrl);

   697     }

   698 

   699     /* Clear interrupt mask to stop board from generating interrupts */

   700     DEBUGOUT("Masking off all interrupts\n");

   701     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   702 

   703     /* Clear any pending interrupt events. */

   704     icr = E1000_READ_REG(hw, ICR);

   705 

   706     /* If MWI was previously enabled, reenable it. */

   707     if(hw->mac_type == e1000_82542_rev2_0) {

   708         if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)

   709             e1000_pci_set_mwi(hw);

   710     }

   711 

   712     if (hw->mac_type == e1000_ich8lan) {

   713         uint32_t kab = E1000_READ_REG(hw, KABGTXD);

   714         kab |= E1000_KABGTXD_BGSQLBIAS;

   715         E1000_WRITE_REG(hw, KABGTXD, kab);

   716     }

   717 

   718     return E1000_SUCCESS;

   719 }

   720 

   721 /******************************************************************************

   722  * Performs basic configuration of the adapter.

   723  *

   724  * hw - Struct containing variables accessed by shared code

   725  *

   726  * Assumes that the controller has previously been reset and is in a

   727  * post-reset uninitialized state. Initializes the receive address registers,

   728  * multicast table, and VLAN filter table. Calls routines to setup link

   729  * configuration and flow control settings. Clears all on-chip counters. Leaves

   730  * the transmit and receive units disabled and uninitialized.

   731  *****************************************************************************/

   732 int32_t

   733 e1000_init_hw(struct e1000_hw *hw)

   734 {

   735     uint32_t ctrl;

   736     uint32_t i;

   737     int32_t ret_val;

   738     uint16_t pcix_cmd_word;

   739     uint16_t pcix_stat_hi_word;

   740     uint16_t cmd_mmrbc;

   741     uint16_t stat_mmrbc;

   742     uint32_t mta_size;

   743     uint32_t reg_data;

   744     uint32_t ctrl_ext;

   745 

   746     DEBUGFUNC("e1000_init_hw");

   747 

   748     /* Initialize Identification LED */

   749     ret_val = e1000_id_led_init(hw);

   750     if(ret_val) {

   751         DEBUGOUT("Error Initializing Identification LED\n");

   752         return ret_val;

   753     }

   754 

   755     /* Set the media type and TBI compatibility */

   756     e1000_set_media_type(hw);

   757 

   758     /* Disabling VLAN filtering. */

   759     DEBUGOUT("Initializing the IEEE VLAN\n");

   760     /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */

   761     if (hw->mac_type != e1000_ich8lan) {

   762         if (hw->mac_type < e1000_82545_rev_3)

   763             E1000_WRITE_REG(hw, VET, 0);

   764         e1000_clear_vfta(hw);

   765     }

   766 

   767     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   768     if(hw->mac_type == e1000_82542_rev2_0) {

   769         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   770         e1000_pci_clear_mwi(hw);

   771         E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);

   772         E1000_WRITE_FLUSH(hw);

   773         msec_delay(5);

   774     }

   775 

   776     /* Setup the receive address. This involves initializing all of the Receive

   777      * Address Registers (RARs 0 - 15).

   778      */

   779     e1000_init_rx_addrs(hw);

   780 

   781     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   782     if(hw->mac_type == e1000_82542_rev2_0) {

   783         E1000_WRITE_REG(hw, RCTL, 0);

   784         E1000_WRITE_FLUSH(hw);

   785         msec_delay(1);

   786         if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)

   787             e1000_pci_set_mwi(hw);

   788     }

   789 

   790     /* Zero out the Multicast HASH table */

   791     DEBUGOUT("Zeroing the MTA\n");

   792     mta_size = E1000_MC_TBL_SIZE;

   793     if (hw->mac_type == e1000_ich8lan)

   794         mta_size = E1000_MC_TBL_SIZE_ICH8LAN;

   795     for(i = 0; i < mta_size; i++) {

   796         E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   797         /* use write flush to prevent Memory Write Block (MWB) from

   798          * occuring when accessing our register space */

   799         E1000_WRITE_FLUSH(hw);

   800     }

   801 

   802     /* Set the PCI priority bit correctly in the CTRL register.  This

   803      * determines if the adapter gives priority to receives, or if it

   804      * gives equal priority to transmits and receives.  Valid only on

   805      * 82542 and 82543 silicon.

   806      */

   807     if(hw->dma_fairness && hw->mac_type <= e1000_82543) {

   808         ctrl = E1000_READ_REG(hw, CTRL);

   809         E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);

   810     }

   811 

   812     switch(hw->mac_type) {

   813     case e1000_82545_rev_3:

   814     case e1000_82546_rev_3:

   815         break;

   816     default:

   817         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   818         if(hw->bus_type == e1000_bus_type_pcix) {

   819             e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);

   820             e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,

   821                 &pcix_stat_hi_word);

   822             cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>

   823                 PCIX_COMMAND_MMRBC_SHIFT;

   824             stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>

   825                 PCIX_STATUS_HI_MMRBC_SHIFT;

   826             if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)

   827                 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;

   828             if(cmd_mmrbc > stat_mmrbc) {

   829                 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;

   830                 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;

   831                 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,

   832                     &pcix_cmd_word);

   833             }

   834         }

   835         break;

   836     }

   837 

   838     /* More time needed for PHY to initialize */

   839     if (hw->mac_type == e1000_ich8lan)

   840         msec_delay(15);

   841 

   842     /* Call a subroutine to configure the link and setup flow control. */

   843     ret_val = e1000_setup_link(hw);

   844 

   845     /* Set the transmit descriptor write-back policy */

   846     if(hw->mac_type > e1000_82544) {

   847         ctrl = E1000_READ_REG(hw, TXDCTL);

   848         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

   849         switch (hw->mac_type) {

   850         default:

   851             break;

   852         case e1000_82571:

   853         case e1000_82572:

   854         case e1000_82573:

   855         case e1000_ich8lan:

   856         case e1000_80003es2lan:

   857             ctrl |= E1000_TXDCTL_COUNT_DESC;

   858             break;

   859         }

   860         E1000_WRITE_REG(hw, TXDCTL, ctrl);

   861     }

   862 

   863     if (hw->mac_type == e1000_82573) {

   864         e1000_enable_tx_pkt_filtering(hw);

   865     }

   866 

   867     switch (hw->mac_type) {

   868     default:

   869         break;

   870     case e1000_80003es2lan:

   871         /* Enable retransmit on late collisions */

   872         reg_data = E1000_READ_REG(hw, TCTL);

   873         reg_data |= E1000_TCTL_RTLC;

   874         E1000_WRITE_REG(hw, TCTL, reg_data);

   875 

   876         /* Configure Gigabit Carry Extend Padding */

   877         reg_data = E1000_READ_REG(hw, TCTL_EXT);

   878         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;

   879         reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;

   880         E1000_WRITE_REG(hw, TCTL_EXT, reg_data);

   881 

   882         /* Configure Transmit Inter-Packet Gap */

   883         reg_data = E1000_READ_REG(hw, TIPG);

   884         reg_data &= ~E1000_TIPG_IPGT_MASK;

   885         reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;

   886         E1000_WRITE_REG(hw, TIPG, reg_data);

   887 

   888         reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);

   889         reg_data &= ~0x00100000;

   890         E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);

   891         /* Fall through */

   892     case e1000_82571:

   893     case e1000_82572:

   894     case e1000_ich8lan:

   895         ctrl = E1000_READ_REG(hw, TXDCTL1);

   896         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

   897         if(hw->mac_type >= e1000_82571)

   898             ctrl |= E1000_TXDCTL_COUNT_DESC;

   899         E1000_WRITE_REG(hw, TXDCTL1, ctrl);

   900         break;

   901     }

   902 

   903 

   904 

   905     if (hw->mac_type == e1000_82573) {

   906         uint32_t gcr = E1000_READ_REG(hw, GCR);

   907         gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

   908         E1000_WRITE_REG(hw, GCR, gcr);

   909     }

   910 

   911     /* Clear all of the statistics registers (clear on read).  It is

   912      * important that we do this after we have tried to establish link

   913      * because the symbol error count will increment wildly if there

   914      * is no link.

   915      */

   916     e1000_clear_hw_cntrs(hw);

   917 

   918     /* ICH8 No-snoop bits are opposite polarity.

   919      * Set to snoop by default after reset. */

   920     if (hw->mac_type == e1000_ich8lan)

   921         e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);

   922 

   923     if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   924         hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   925         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   926         /* Relaxed ordering must be disabled to avoid a parity

   927          * error crash in a PCI slot. */

   928         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   929         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   930     }

   931 

   932     return ret_val;

   933 }

   934 

   935 /******************************************************************************

   936  * Adjust SERDES output amplitude based on EEPROM setting.

   937  *

   938  * hw - Struct containing variables accessed by shared code.

   939  *****************************************************************************/

   940 static int32_t

   941 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   942 {

   943     uint16_t eeprom_data;

   944     int32_t  ret_val;

   945 

   946     DEBUGFUNC("e1000_adjust_serdes_amplitude");

   947 

   948     if(hw->media_type != e1000_media_type_internal_serdes)

   949         return E1000_SUCCESS;

   950 

   951     switch(hw->mac_type) {

   952     case e1000_82545_rev_3:

   953     case e1000_82546_rev_3:

   954         break;

   955     default:

   956         return E1000_SUCCESS;

   957     }

   958 

   959     ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);

   960     if (ret_val) {

   961         return ret_val;

   962     }

   963 

   964     if(eeprom_data != EEPROM_RESERVED_WORD) {

   965         /* Adjust SERDES output amplitude only. */

   966         eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   967         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   968         if(ret_val)

   969             return ret_val;

   970     }

   971 

   972     return E1000_SUCCESS;

   973 }

   974 

   975 /******************************************************************************

   976  * Configures flow control and link settings.

   977  *

   978  * hw - Struct containing variables accessed by shared code

   979  *

   980  * Determines which flow control settings to use. Calls the apropriate media-

   981  * specific link configuration function. Configures the flow control settings.

   982  * Assuming the adapter has a valid link partner, a valid link should be

   983  * established. Assumes the hardware has previously been reset and the

   984  * transmitter and receiver are not enabled.

   985  *****************************************************************************/

   986 int32_t

   987 e1000_setup_link(struct e1000_hw *hw)

   988 {

   989     uint32_t ctrl_ext;

   990     int32_t ret_val;

   991     uint16_t eeprom_data;

   992 

   993     DEBUGFUNC("e1000_setup_link");

   994 

   995     /* In the case of the phy reset being blocked, we already have a link.

   996      * We do not have to set it up again. */

   997     if (e1000_check_phy_reset_block(hw))

   998         return E1000_SUCCESS;

   999 

  1000     /* Read and store word 0x0F of the EEPROM. This word contains bits

  1001      * that determine the hardware's default PAUSE (flow control) mode,

  1002      * a bit that determines whether the HW defaults to enabling or

  1003      * disabling auto-negotiation, and the direction of the

  1004      * SW defined pins. If there is no SW over-ride of the flow

  1005      * control setting, then the variable hw->fc will

  1006      * be initialized based on a value in the EEPROM.

  1007      */

  1008     if (hw->fc == e1000_fc_default) {

  1009         switch (hw->mac_type) {

  1010         case e1000_ich8lan:

  1011         case e1000_82573:

  1012             hw->fc = e1000_fc_full;

  1013             break;

  1014         default:

  1015             ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

  1016                                         1, &eeprom_data);

  1017             if (ret_val) {

  1018                 DEBUGOUT("EEPROM Read Error\n");

  1019                 return -E1000_ERR_EEPROM;

  1020             }

  1021             if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

  1022                 hw->fc = e1000_fc_none;

  1023             else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

  1024                     EEPROM_WORD0F_ASM_DIR)

  1025                 hw->fc = e1000_fc_tx_pause;

  1026             else

  1027                 hw->fc = e1000_fc_full;

  1028             break;

  1029         }

  1030     }

  1031 

  1032     /* We want to save off the original Flow Control configuration just

  1033      * in case we get disconnected and then reconnected into a different

  1034      * hub or switch with different Flow Control capabilities.

  1035      */

  1036     if(hw->mac_type == e1000_82542_rev2_0)

  1037         hw->fc &= (~e1000_fc_tx_pause);

  1038 

  1039     if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

  1040         hw->fc &= (~e1000_fc_rx_pause);

  1041 

  1042     hw->original_fc = hw->fc;

  1043 

  1044     DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);

  1045 

  1046     /* Take the 4 bits from EEPROM word 0x0F that determine the initial

  1047      * polarity value for the SW controlled pins, and setup the

  1048      * Extended Device Control reg with that info.

  1049      * This is needed because one of the SW controlled pins is used for

  1050      * signal detection.  So this should be done before e1000_setup_pcs_link()

  1051      * or e1000_phy_setup() is called.

  1052      */

  1053     if (hw->mac_type == e1000_82543) {

  1054 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

  1055 									1, &eeprom_data);

  1056 		if (ret_val) {

  1057 			DEBUGOUT("EEPROM Read Error\n");

  1058 			return -E1000_ERR_EEPROM;

  1059 		}

  1060         ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

  1061                     SWDPIO__EXT_SHIFT);

  1062         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

  1063     }

  1064 

  1065     /* Call the necessary subroutine to configure the link. */

  1066     ret_val = (hw->media_type == e1000_media_type_copper) ?

  1067               e1000_setup_copper_link(hw) :

  1068               e1000_setup_fiber_serdes_link(hw);

  1069 

  1070     /* Initialize the flow control address, type, and PAUSE timer

  1071      * registers to their default values.  This is done even if flow

  1072      * control is disabled, because it does not hurt anything to

  1073      * initialize these registers.

  1074      */

  1075     DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");

  1076 

  1077     /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */

  1078     if (hw->mac_type != e1000_ich8lan) {

  1079         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);

  1080         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);

  1081         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);

  1082     }

  1083 

  1084     E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);

  1085 

  1086     /* Set the flow control receive threshold registers.  Normally,

  1087      * these registers will be set to a default threshold that may be

  1088      * adjusted later by the driver's runtime code.  However, if the

  1089      * ability to transmit pause frames in not enabled, then these

  1090      * registers will be set to 0.

  1091      */

  1092     if(!(hw->fc & e1000_fc_tx_pause)) {

  1093         E1000_WRITE_REG(hw, FCRTL, 0);

  1094         E1000_WRITE_REG(hw, FCRTH, 0);

  1095     } else {

  1096         /* We need to set up the Receive Threshold high and low water marks

  1097          * as well as (optionally) enabling the transmission of XON frames.

  1098          */

  1099         if(hw->fc_send_xon) {

  1100             E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

  1101             E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);

  1102         } else {

  1103             E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);

  1104             E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);

  1105         }

  1106     }

  1107     return ret_val;

  1108 }

  1109 

  1110 /******************************************************************************

  1111  * Sets up link for a fiber based or serdes based adapter

  1112  *

  1113  * hw - Struct containing variables accessed by shared code

  1114  *

  1115  * Manipulates Physical Coding Sublayer functions in order to configure

  1116  * link. Assumes the hardware has been previously reset and the transmitter

  1117  * and receiver are not enabled.

  1118  *****************************************************************************/

  1119 static int32_t

  1120 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

  1121 {

  1122     uint32_t ctrl;

  1123     uint32_t status;

  1124     uint32_t txcw = 0;

  1125     uint32_t i;

  1126     uint32_t signal = 0;

  1127     int32_t ret_val;

  1128 

  1129     DEBUGFUNC("e1000_setup_fiber_serdes_link");

  1130 

  1131     /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists

  1132      * until explicitly turned off or a power cycle is performed.  A read to

  1133      * the register does not indicate its status.  Therefore, we ensure

  1134      * loopback mode is disabled during initialization.

  1135      */

  1136     if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)