1 /*******************************************************************************

     2 

     3   

     4   Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.

     5   

     6   This program is free software; you can redistribute it and/or modify it 

     7   under the terms of the GNU General Public License as published by the Free 

     8   Software Foundation; either version 2 of the License, or (at your option) 

     9   any later version.

    10   

    11   This program is distributed in the hope that it will be useful, but WITHOUT 

    12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 

    13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 

    14   more details.

    15   

    16   You should have received a copy of the GNU General Public License along with

    17   this program; if not, write to the Free Software Foundation, Inc., 59 

    18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    19   

    20   The full GNU General Public License is included in this distribution in the

    21   file called LICENSE.

    22   

    23   Contact Information:

    24   Linux NICS <linux.nics@intel.com>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000_hw-2.6.13-ethercat.h"

    34 

    35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);

    36 static void e1000_phy_init_script(struct e1000_hw *hw);

    37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);

    38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);

    42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);

    44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,

    45                                      uint16_t count);

    46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);

    48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,

    49                                       uint16_t words, uint16_t *data);

    50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,

    51                                             uint16_t offset, uint16_t words,

    52                                             uint16_t *data);

    53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);

    54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);

    56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,

    57                                     uint16_t count);

    58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,

    59                                       uint16_t phy_data);

    60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,

    61                                      uint16_t *phy_data);

    62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);

    63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);

    64 static void e1000_release_eeprom(struct e1000_hw *hw);

    65 static void e1000_standby_eeprom(struct e1000_hw *hw);

    66 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);

    67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);

    69 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);

    70 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);

    71 

    72 /* IGP cable length table */

    73 static const

    74 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =

    75     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    76       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    77       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    78       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

    79       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

    80       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,

    81       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

    82       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};

    83 

    84 static const

    85 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =

    86     { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,

    87       22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,

    88       32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,

    89       43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,

    90       57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,

    91       73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,

    92       91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,

    93       108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};

    94 

    95 

    96 /******************************************************************************

    97  * Set the phy type member in the hw struct.

    98  *

    99  * hw - Struct containing variables accessed by shared code

   100  *****************************************************************************/

   101 int32_t

   102 e1000_set_phy_type(struct e1000_hw *hw)

   103 {

   104     DEBUGFUNC("e1000_set_phy_type");

   105 

   106     if(hw->mac_type == e1000_undefined)

   107         return -E1000_ERR_PHY_TYPE;

   108 

   109     switch(hw->phy_id) {

   110     case M88E1000_E_PHY_ID:

   111     case M88E1000_I_PHY_ID:

   112     case M88E1011_I_PHY_ID:

   113     case M88E1111_I_PHY_ID:

   114         hw->phy_type = e1000_phy_m88;

   115         break;

   116     case IGP01E1000_I_PHY_ID:

   117         if(hw->mac_type == e1000_82541 ||

   118            hw->mac_type == e1000_82541_rev_2 ||

   119            hw->mac_type == e1000_82547 ||

   120            hw->mac_type == e1000_82547_rev_2) {

   121             hw->phy_type = e1000_phy_igp;

   122             break;

   123         }

   124         /* Fall Through */

   125     default:

   126         /* Should never have loaded on this device */

   127         hw->phy_type = e1000_phy_undefined;

   128         return -E1000_ERR_PHY_TYPE;

   129     }

   130 

   131     return E1000_SUCCESS;

   132 }

   133 

   134 /******************************************************************************

   135  * IGP phy init script - initializes the GbE PHY

   136  *

   137  * hw - Struct containing variables accessed by shared code

   138  *****************************************************************************/

   139 static void

   140 e1000_phy_init_script(struct e1000_hw *hw)

   141 {

   142     uint32_t ret_val;

   143     uint16_t phy_saved_data;

   144 

   145     DEBUGFUNC("e1000_phy_init_script");

   146 

   147     if(hw->phy_init_script) {

   148         msec_delay(20);

   149 

   150         /* Save off the current value of register 0x2F5B to be restored at

   151          * the end of this routine. */

   152         ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   153 

   154         /* Disabled the PHY transmitter */

   155         e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   156 

   157         msec_delay(20);

   158 

   159         e1000_write_phy_reg(hw,0x0000,0x0140);

   160 

   161         msec_delay(5);

   162 

   163         switch(hw->mac_type) {

   164         case e1000_82541:

   165         case e1000_82547:

   166             e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   167 

   168             e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   169 

   170             e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   171 

   172             e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   173 

   174             e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   175 

   176             e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   177 

   178             e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   179 

   180             e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   181 

   182             e1000_write_phy_reg(hw, 0x2010, 0x0008);

   183             break;

   184 

   185         case e1000_82541_rev_2:

   186         case e1000_82547_rev_2:

   187             e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   188             break;

   189         default:

   190             break;

   191         }

   192 

   193         e1000_write_phy_reg(hw, 0x0000, 0x3300);

   194 

   195         msec_delay(20);

   196 

   197         /* Now enable the transmitter */

   198         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   199 

   200         if(hw->mac_type == e1000_82547) {

   201             uint16_t fused, fine, coarse;

   202 

   203             /* Move to analog registers page */

   204             e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);

   205 

   206             if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   207                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);

   208 

   209                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   210                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   211 

   212                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   213                     coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;

   214                     fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   215                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   216                     fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   217 

   218                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   219                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   220                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   221 

   222                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);

   223                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,

   224                                     IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   225             }

   226         }

   227     }

   228 }

   229 

   230 /******************************************************************************

   231  * Set the mac type member in the hw struct.

   232  *

   233  * hw - Struct containing variables accessed by shared code

   234  *****************************************************************************/

   235 int32_t

   236 e1000_set_mac_type(struct e1000_hw *hw)

   237 {

   238     DEBUGFUNC("e1000_set_mac_type");

   239 

   240     switch (hw->device_id) {

   241     case E1000_DEV_ID_82542:

   242         switch (hw->revision_id) {

   243         case E1000_82542_2_0_REV_ID:

   244             hw->mac_type = e1000_82542_rev2_0;

   245             break;

   246         case E1000_82542_2_1_REV_ID:

   247             hw->mac_type = e1000_82542_rev2_1;

   248             break;

   249         default:

   250             /* Invalid 82542 revision ID */

   251             return -E1000_ERR_MAC_TYPE;

   252         }

   253         break;

   254     case E1000_DEV_ID_82543GC_FIBER:

   255     case E1000_DEV_ID_82543GC_COPPER:

   256         hw->mac_type = e1000_82543;

   257         break;

   258     case E1000_DEV_ID_82544EI_COPPER:

   259     case E1000_DEV_ID_82544EI_FIBER:

   260     case E1000_DEV_ID_82544GC_COPPER:

   261     case E1000_DEV_ID_82544GC_LOM:

   262         hw->mac_type = e1000_82544;

   263         break;

   264     case E1000_DEV_ID_82540EM:

   265     case E1000_DEV_ID_82540EM_LOM:

   266     case E1000_DEV_ID_82540EP:

   267     case E1000_DEV_ID_82540EP_LOM:

   268     case E1000_DEV_ID_82540EP_LP:

   269         hw->mac_type = e1000_82540;

   270         break;

   271     case E1000_DEV_ID_82545EM_COPPER:

   272     case E1000_DEV_ID_82545EM_FIBER:

   273         hw->mac_type = e1000_82545;

   274         break;

   275     case E1000_DEV_ID_82545GM_COPPER:

   276     case E1000_DEV_ID_82545GM_FIBER:

   277     case E1000_DEV_ID_82545GM_SERDES:

   278         hw->mac_type = e1000_82545_rev_3;

   279         break;

   280     case E1000_DEV_ID_82546EB_COPPER:

   281     case E1000_DEV_ID_82546EB_FIBER:

   282     case E1000_DEV_ID_82546EB_QUAD_COPPER:

   283         hw->mac_type = e1000_82546;

   284         break;

   285     case E1000_DEV_ID_82546GB_COPPER:

   286     case E1000_DEV_ID_82546GB_FIBER:

   287     case E1000_DEV_ID_82546GB_SERDES:

   288     case E1000_DEV_ID_82546GB_PCIE:

   289     case E1000_DEV_ID_82546GB_QUAD_COPPER:

   290         hw->mac_type = e1000_82546_rev_3;

   291         break;

   292     case E1000_DEV_ID_82541EI:

   293     case E1000_DEV_ID_82541EI_MOBILE:

   294         hw->mac_type = e1000_82541;

   295         break;

   296     case E1000_DEV_ID_82541ER:

   297     case E1000_DEV_ID_82541GI:

   298     case E1000_DEV_ID_82541GI_LF:

   299     case E1000_DEV_ID_82541GI_MOBILE:

   300         hw->mac_type = e1000_82541_rev_2;

   301         break;

   302     case E1000_DEV_ID_82547EI:

   303         hw->mac_type = e1000_82547;

   304         break;

   305     case E1000_DEV_ID_82547GI:

   306         hw->mac_type = e1000_82547_rev_2;

   307         break;

   308     case E1000_DEV_ID_82573E:

   309     case E1000_DEV_ID_82573E_IAMT:

   310         hw->mac_type = e1000_82573;

   311         break;

   312     default:

   313         /* Should never have loaded on this device */

   314         return -E1000_ERR_MAC_TYPE;

   315     }

   316 

   317     switch(hw->mac_type) {

   318     case e1000_82573:

   319         hw->eeprom_semaphore_present = TRUE;

   320         /* fall through */

   321     case e1000_82541:

   322     case e1000_82547:

   323     case e1000_82541_rev_2:

   324     case e1000_82547_rev_2:

   325         hw->asf_firmware_present = TRUE;

   326         break;

   327     default:

   328         break;

   329     }

   330 

   331     return E1000_SUCCESS;

   332 }

   333 

   334 /*****************************************************************************

   335  * Set media type and TBI compatibility.

   336  *

   337  * hw - Struct containing variables accessed by shared code

   338  * **************************************************************************/

   339 void

   340 e1000_set_media_type(struct e1000_hw *hw)

   341 {

   342     uint32_t status;

   343 

   344     DEBUGFUNC("e1000_set_media_type");

   345 

   346     if(hw->mac_type != e1000_82543) {

   347         /* tbi_compatibility is only valid on 82543 */

   348         hw->tbi_compatibility_en = FALSE;

   349     }

   350 

   351     switch (hw->device_id) {

   352     case E1000_DEV_ID_82545GM_SERDES:

   353     case E1000_DEV_ID_82546GB_SERDES:

   354         hw->media_type = e1000_media_type_internal_serdes;

   355         break;

   356     default:

   357         switch (hw->mac_type) {

   358         case e1000_82542_rev2_0:

   359         case e1000_82542_rev2_1:

   360             hw->media_type = e1000_media_type_fiber;

   361             break;

   362         case e1000_82573:

   363             /* The STATUS_TBIMODE bit is reserved or reused for the this

   364              * device.

   365              */

   366             hw->media_type = e1000_media_type_copper;

   367             break;

   368         default:

   369             status = E1000_READ_REG(hw, STATUS);

   370             if (status & E1000_STATUS_TBIMODE) {

   371                 hw->media_type = e1000_media_type_fiber;

   372                 /* tbi_compatibility not valid on fiber */

   373                 hw->tbi_compatibility_en = FALSE;

   374             } else {

   375                 hw->media_type = e1000_media_type_copper;

   376             }

   377             break;

   378         }

   379     }

   380 }

   381 

   382 /******************************************************************************

   383  * Reset the transmit and receive units; mask and clear all interrupts.

   384  *

   385  * hw - Struct containing variables accessed by shared code

   386  *****************************************************************************/

   387 int32_t

   388 e1000_reset_hw(struct e1000_hw *hw)

   389 {

   390     uint32_t ctrl;

   391     uint32_t ctrl_ext;

   392     uint32_t icr;

   393     uint32_t manc;

   394     uint32_t led_ctrl;

   395     uint32_t timeout;

   396     uint32_t extcnf_ctrl;

   397     int32_t ret_val;

   398 

   399     DEBUGFUNC("e1000_reset_hw");

   400 

   401     /* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   402     if(hw->mac_type == e1000_82542_rev2_0) {

   403         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   404         e1000_pci_clear_mwi(hw);

   405     }

   406 

   407     if(hw->bus_type == e1000_bus_type_pci_express) {

   408         /* Prevent the PCI-E bus from sticking if there is no TLP connection

   409          * on the last TLP read/write transaction when MAC is reset.

   410          */

   411         if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {

   412             DEBUGOUT("PCI-E Master disable polling has failed.\n");

   413         }

   414     }

   415 

   416     /* Clear interrupt mask to stop board from generating interrupts */

   417     DEBUGOUT("Masking off all interrupts\n");

   418     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   419 

   420     /* Disable the Transmit and Receive units.  Then delay to allow

   421      * any pending transactions to complete before we hit the MAC with

   422      * the global reset.

   423      */

   424     E1000_WRITE_REG(hw, RCTL, 0);

   425     E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);

   426     E1000_WRITE_FLUSH(hw);

   427 

   428     /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   429     hw->tbi_compatibility_on = FALSE;

   430 

   431     /* Delay to allow any outstanding PCI transactions to complete before

   432      * resetting the device

   433      */

   434     msec_delay(10);

   435 

   436     ctrl = E1000_READ_REG(hw, CTRL);

   437 

   438     /* Must reset the PHY before resetting the MAC */

   439     if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   440         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));

   441         msec_delay(5);

   442     }

   443 

   444     /* Must acquire the MDIO ownership before MAC reset.

   445      * Ownership defaults to firmware after a reset. */

   446     if(hw->mac_type == e1000_82573) {

   447         timeout = 10;

   448 

   449         extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   450         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   451 

   452         do {

   453             E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);

   454             extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);

   455 

   456             if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   457                 break;

   458             else

   459                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   460 

   461             msec_delay(2);

   462             timeout--;

   463         } while(timeout);

   464     }

   465 

   466     /* Issue a global reset to the MAC.  This will reset the chip's

   467      * transmit, receive, DMA, and link units.  It will not effect

   468      * the current PCI configuration.  The global reset bit is self-

   469      * clearing, and should clear within a microsecond.

   470      */

   471     DEBUGOUT("Issuing a global reset to MAC\n");

   472 

   473     switch(hw->mac_type) {

   474         case e1000_82544:

   475         case e1000_82540:

   476         case e1000_82545:

   477         case e1000_82546:

   478         case e1000_82541:

   479         case e1000_82541_rev_2:

   480             /* These controllers can't ack the 64-bit write when issuing the

   481              * reset, so use IO-mapping as a workaround to issue the reset */

   482             E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   483             break;

   484         case e1000_82545_rev_3:

   485         case e1000_82546_rev_3:

   486             /* Reset is performed on a shadow of the control register */

   487             E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));

   488             break;

   489         default:

   490             E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

   491             break;

   492     }

   493 

   494     /* After MAC reset, force reload of EEPROM to restore power-on settings to

   495      * device.  Later controllers reload the EEPROM automatically, so just wait

   496      * for reload to complete.

   497      */

   498     switch(hw->mac_type) {

   499         case e1000_82542_rev2_0:

   500         case e1000_82542_rev2_1:

   501         case e1000_82543:

   502         case e1000_82544:

   503             /* Wait for reset to complete */

   504             udelay(10);

   505             ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   506             ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   507             E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   508             E1000_WRITE_FLUSH(hw);

   509             /* Wait for EEPROM reload */

   510             msec_delay(2);

   511             break;

   512         case e1000_82541:

   513         case e1000_82541_rev_2:

   514         case e1000_82547:

   515         case e1000_82547_rev_2:

   516             /* Wait for EEPROM reload */

   517             msec_delay(20);

   518             break;

   519         case e1000_82573:

   520             udelay(10);

   521             ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);

   522             ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   523             E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   524             E1000_WRITE_FLUSH(hw);

   525             /* fall through */

   526             ret_val = e1000_get_auto_rd_done(hw);

   527             if(ret_val)

   528                 /* We don't want to continue accessing MAC registers. */

   529                 return ret_val;

   530             break;

   531         default:

   532             /* Wait for EEPROM reload (it happens automatically) */

   533             msec_delay(5);

   534             break;

   535     }

   536 

   537     /* Disable HW ARPs on ASF enabled adapters */

   538     if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {

   539         manc = E1000_READ_REG(hw, MANC);

   540         manc &= ~(E1000_MANC_ARP_EN);

   541         E1000_WRITE_REG(hw, MANC, manc);

   542     }

   543 

   544     if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   545         e1000_phy_init_script(hw);

   546 

   547         /* Configure activity LED after PHY reset */

   548         led_ctrl = E1000_READ_REG(hw, LEDCTL);

   549         led_ctrl &= IGP_ACTIVITY_LED_MASK;

   550         led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   551         E1000_WRITE_REG(hw, LEDCTL, led_ctrl);

   552     }

   553 

   554     /* Clear interrupt mask to stop board from generating interrupts */

   555     DEBUGOUT("Masking off all interrupts\n");

   556     E1000_WRITE_REG(hw, IMC, 0xffffffff);

   557 

   558     /* Clear any pending interrupt events. */

   559     icr = E1000_READ_REG(hw, ICR);

   560 

   561     /* If MWI was previously enabled, reenable it. */

   562     if(hw->mac_type == e1000_82542_rev2_0) {

   563         if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)

   564             e1000_pci_set_mwi(hw);

   565     }

   566 

   567     return E1000_SUCCESS;

   568 }

   569 

   570 /******************************************************************************

   571  * Performs basic configuration of the adapter.

   572  *

   573  * hw - Struct containing variables accessed by shared code

   574  *

   575  * Assumes that the controller has previously been reset and is in a

   576  * post-reset uninitialized state. Initializes the receive address registers,

   577  * multicast table, and VLAN filter table. Calls routines to setup link

   578  * configuration and flow control settings. Clears all on-chip counters. Leaves

   579  * the transmit and receive units disabled and uninitialized.

   580  *****************************************************************************/

   581 int32_t

   582 e1000_init_hw(struct e1000_hw *hw)

   583 {

   584     uint32_t ctrl;

   585     uint32_t i;

   586     int32_t ret_val;

   587     uint16_t pcix_cmd_word;

   588     uint16_t pcix_stat_hi_word;

   589     uint16_t cmd_mmrbc;

   590     uint16_t stat_mmrbc;

   591     uint32_t mta_size;

   592 

   593     DEBUGFUNC("e1000_init_hw");

   594 

   595     /* Initialize Identification LED */

   596     ret_val = e1000_id_led_init(hw);

   597     if(ret_val) {

   598         DEBUGOUT("Error Initializing Identification LED\n");

   599         return ret_val;

   600     }

   601 

   602     /* Set the media type and TBI compatibility */

   603     e1000_set_media_type(hw);

   604 

   605     /* Disabling VLAN filtering. */

   606     DEBUGOUT("Initializing the IEEE VLAN\n");

   607     if (hw->mac_type < e1000_82545_rev_3)

   608         E1000_WRITE_REG(hw, VET, 0);

   609     e1000_clear_vfta(hw);

   610 

   611     /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   612     if(hw->mac_type == e1000_82542_rev2_0) {

   613         DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");

   614         e1000_pci_clear_mwi(hw);

   615         E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);

   616         E1000_WRITE_FLUSH(hw);

   617         msec_delay(5);

   618     }

   619 

   620     /* Setup the receive address. This involves initializing all of the Receive

   621      * Address Registers (RARs 0 - 15).

   622      */

   623     e1000_init_rx_addrs(hw);

   624 

   625     /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   626     if(hw->mac_type == e1000_82542_rev2_0) {

   627         E1000_WRITE_REG(hw, RCTL, 0);

   628         E1000_WRITE_FLUSH(hw);

   629         msec_delay(1);

   630         if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)

   631             e1000_pci_set_mwi(hw);

   632     }

   633 

   634     /* Zero out the Multicast HASH table */

   635     DEBUGOUT("Zeroing the MTA\n");

   636     mta_size = E1000_MC_TBL_SIZE;

   637     for(i = 0; i < mta_size; i++)

   638         E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   639 

   640     /* Set the PCI priority bit correctly in the CTRL register.  This

   641      * determines if the adapter gives priority to receives, or if it

   642      * gives equal priority to transmits and receives.  Valid only on

   643      * 82542 and 82543 silicon.

   644      */

   645     if(hw->dma_fairness && hw->mac_type <= e1000_82543) {

   646         ctrl = E1000_READ_REG(hw, CTRL);

   647         E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);

   648     }

   649 

   650     switch(hw->mac_type) {

   651     case e1000_82545_rev_3:

   652     case e1000_82546_rev_3:

   653         break;

   654     default:

   655         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   656         if(hw->bus_type == e1000_bus_type_pcix) {

   657             e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);

   658             e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,

   659                 &pcix_stat_hi_word);

   660             cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>

   661                 PCIX_COMMAND_MMRBC_SHIFT;

   662             stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>

   663                 PCIX_STATUS_HI_MMRBC_SHIFT;

   664             if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)

   665                 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;

   666             if(cmd_mmrbc > stat_mmrbc) {

   667                 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;

   668                 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;

   669                 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,

   670                     &pcix_cmd_word);

   671             }

   672         }

   673         break;

   674     }

   675 

   676     /* Call a subroutine to configure the link and setup flow control. */

   677     ret_val = e1000_setup_link(hw);

   678 

   679     /* Set the transmit descriptor write-back policy */

   680     if(hw->mac_type > e1000_82544) {

   681         ctrl = E1000_READ_REG(hw, TXDCTL);

   682         ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;

   683         switch (hw->mac_type) {

   684         default:

   685             break;

   686         case e1000_82573:

   687             ctrl |= E1000_TXDCTL_COUNT_DESC;

   688             break;

   689         }

   690         E1000_WRITE_REG(hw, TXDCTL, ctrl);

   691     }

   692 

   693     if (hw->mac_type == e1000_82573) {

   694         e1000_enable_tx_pkt_filtering(hw); 

   695     }

   696 

   697 

   698     /* Clear all of the statistics registers (clear on read).  It is

   699      * important that we do this after we have tried to establish link

   700      * because the symbol error count will increment wildly if there

   701      * is no link.

   702      */

   703     e1000_clear_hw_cntrs(hw);

   704 

   705     return ret_val;

   706 }

   707 

   708 /******************************************************************************

   709  * Adjust SERDES output amplitude based on EEPROM setting.

   710  *

   711  * hw - Struct containing variables accessed by shared code.

   712  *****************************************************************************/

   713 static int32_t

   714 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   715 {

   716     uint16_t eeprom_data;

   717     int32_t  ret_val;

   718 

   719     DEBUGFUNC("e1000_adjust_serdes_amplitude");

   720 

   721     if(hw->media_type != e1000_media_type_internal_serdes)

   722         return E1000_SUCCESS;

   723 

   724     switch(hw->mac_type) {

   725     case e1000_82545_rev_3:

   726     case e1000_82546_rev_3:

   727         break;

   728     default:

   729         return E1000_SUCCESS;

   730     }

   731 

   732     ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);

   733     if (ret_val) {

   734         return ret_val;

   735     }

   736 

   737     if(eeprom_data != EEPROM_RESERVED_WORD) {

   738         /* Adjust SERDES output amplitude only. */

   739         eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 

   740         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   741         if(ret_val)

   742             return ret_val;

   743     }

   744 

   745     return E1000_SUCCESS;

   746 }

   747 

   748 /******************************************************************************

   749  * Configures flow control and link settings.

   750  *

   751  * hw - Struct containing variables accessed by shared code

   752  *

   753  * Determines which flow control settings to use. Calls the apropriate media-

   754  * specific link configuration function. Configures the flow control settings.

   755  * Assuming the adapter has a valid link partner, a valid link should be

   756  * established. Assumes the hardware has previously been reset and the

   757  * transmitter and receiver are not enabled.

   758  *****************************************************************************/

   759 int32_t

   760 e1000_setup_link(struct e1000_hw *hw)

   761 {

   762     uint32_t ctrl_ext;

   763     int32_t ret_val;

   764     uint16_t eeprom_data;

   765 

   766     DEBUGFUNC("e1000_setup_link");

   767 

   768     /* Read and store word 0x0F of the EEPROM. This word contains bits

   769      * that determine the hardware's default PAUSE (flow control) mode,

   770      * a bit that determines whether the HW defaults to enabling or

   771      * disabling auto-negotiation, and the direction of the

   772      * SW defined pins. If there is no SW over-ride of the flow

   773      * control setting, then the variable hw->fc will

   774      * be initialized based on a value in the EEPROM.

   775      */

   776     if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {

   777         DEBUGOUT("EEPROM Read Error\n");

   778         return -E1000_ERR_EEPROM;

   779     }

   780 

   781     if(hw->fc == e1000_fc_default) {

   782         if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   783             hw->fc = e1000_fc_none;

   784         else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   785                 EEPROM_WORD0F_ASM_DIR)

   786             hw->fc = e1000_fc_tx_pause;

   787         else

   788             hw->fc = e1000_fc_full;

   789     }

   790 

   791     /* We want to save off the original Flow Control configuration just

   792      * in case we get disconnected and then reconnected into a different

   793      * hub or switch with different Flow Control capabilities.

   794      */

   795     if(hw->mac_type == e1000_82542_rev2_0)

   796         hw->fc &= (~e1000_fc_tx_pause);

   797 

   798     if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   799         hw->fc &= (~e1000_fc_rx_pause);

   800 

   801     hw->original_fc = hw->fc;

   802 

   803     DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);

   804 

   805     /* Take the 4 bits from EEPROM word 0x0F that determine the initial

   806      * polarity value for the SW controlled pins, and setup the

   807      * Extended Device Control reg with that info.

   808      * This is needed because one of the SW controlled pins is used for

   809      * signal detection.  So this should be done before e1000_setup_pcs_link()

   810      * or e1000_phy_setup() is called.

   811      */

   812     if(hw->mac_type == e1000_82543) {

   813         ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   814                     SWDPIO__EXT_SHIFT);

   815         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);

   816     }

   817 

   818     /* Call the necessary subroutine to configure the link. */

   819     ret_val = (hw->media_type == e1000_media_type_copper) ?

   820               e1000_setup_copper_link(hw) :

   821               e1000_setup_fiber_serdes_link(hw);

   822 

   823     /* Initialize the flow control address, type, and PAUSE timer

   824      * registers to their default values.  This is done even if flow

   825      * control is disabled, because it does not hurt anything to

   826      * initialize these registers.

   827      */

   828     DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");

   829 

   830     E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);

   831     E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   832     E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);

   833 

   834     E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);

   835 

   836     /* Set the flow control receive threshold registers.  Normally,

   837      * these registers will be set to a default threshold that may be

   838      * adjusted later by the driver's runtime code.  However, if the

   839      * ability to transmit pause frames in not enabled, then these

   840      * registers will be set to 0.

   841      */

   842     if(!(hw->fc & e1000_fc_tx_pause)) {

   843         E1000_WRITE_REG(hw, FCRTL, 0);

   844         E1000_WRITE_REG(hw, FCRTH, 0);

   845     } else {

   846         /* We need to set up the Receive Threshold high and low water marks

   847          * as well as (optionally) enabling the transmission of XON frames.

   848          */

   849         if(hw->fc_send_xon) {

   850             E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   851             E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);

   852         } else {

   853             E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);

   854             E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);

   855         }

   856     }

   857     return ret_val;

   858 }

   859 

   860 /******************************************************************************

   861  * Sets up link for a fiber based or serdes based adapter

   862  *

   863  * hw - Struct containing variables accessed by shared code

   864  *

   865  * Manipulates Physical Coding Sublayer functions in order to configure

   866  * link. Assumes the hardware has been previously reset and the transmitter

   867  * and receiver are not enabled.

   868  *****************************************************************************/

   869 static int32_t

   870 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   871 {

   872     uint32_t ctrl;

   873     uint32_t status;

   874     uint32_t txcw = 0;

   875     uint32_t i;

   876     uint32_t signal = 0;

   877     int32_t ret_val;

   878 

   879     DEBUGFUNC("e1000_setup_fiber_serdes_link");

   880 

   881     /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be

   882      * set when the optics detect a signal. On older adapters, it will be

   883      * cleared when there is a signal.  This applies to fiber media only.

   884      * If we're on serdes media, adjust the output amplitude to value set in

   885      * the EEPROM.

   886      */

   887     ctrl = E1000_READ_REG(hw, CTRL);

   888     if(hw->media_type == e1000_media_type_fiber)

   889         signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   890 

   891     ret_val = e1000_adjust_serdes_amplitude(hw);

   892     if(ret_val)

   893         return ret_val;

   894 

   895     /* Take the link out of reset */

   896     ctrl &= ~(E1000_CTRL_LRST);

   897 

   898     /* Adjust VCO speed to improve BER performance */

   899     ret_val = e1000_set_vco_speed(hw);

   900     if(ret_val)

   901         return ret_val;

   902 

   903     e1000_config_collision_dist(hw);

   904 

   905     /* Check for a software override of the flow control settings, and setup

   906      * the device accordingly.  If auto-negotiation is enabled, then software

   907      * will have to set the "PAUSE" bits to the correct value in the Tranmsit

   908      * Config Word Register (TXCW) and re-start auto-negotiation.  However, if

   909      * auto-negotiation is disabled, then software will have to manually

   910      * configure the two flow control enable bits in the CTRL register.

   911      *

   912      * The possible values of the "fc" parameter are:

   913      *      0:  Flow control is completely disabled

   914      *      1:  Rx flow control is enabled (we can receive pause frames, but

   915      *          not send pause frames).

   916      *      2:  Tx flow control is enabled (we can send pause frames but we do

   917      *          not support receiving pause frames).

   918      *      3:  Both Rx and TX flow control (symmetric) are enabled.

   919      */

   920     switch (hw->fc) {

   921     case e1000_fc_none:

   922         /* Flow control is completely disabled by a software over-ride. */

   923         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   924         break;

   925     case e1000_fc_rx_pause:

   926         /* RX Flow control is enabled and TX Flow control is disabled by a

   927          * software over-ride. Since there really isn't a way to advertise

   928          * that we are capable of RX Pause ONLY, we will advertise that we

   929          * support both symmetric and asymmetric RX PAUSE. Later, we will

   930          *  disable the adapter's ability to send PAUSE frames.

   931          */

   932         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   933         break;

   934     case e1000_fc_tx_pause:

   935         /* TX Flow control is enabled, and RX Flow control is disabled, by a

   936          * software over-ride.

   937          */

   938         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   939         break;

   940     case e1000_fc_full:

   941         /* Flow control (both RX and TX) is enabled by a software over-ride. */

   942         txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   943         break;

   944     default:

   945         DEBUGOUT("Flow control param set incorrectly\n");

   946         return -E1000_ERR_CONFIG;

   947         break;

   948     }

   949 

   950     /* Since auto-negotiation is enabled, take the link out of reset (the link

   951      * will be in reset, because we previously reset the chip). This will

   952      * restart auto-negotiation.  If auto-neogtiation is successful then the

   953      * link-up status bit will be set and the flow control enable bits (RFCE

   954      * and TFCE) will be set according to their negotiated value.

   955      */

   956     DEBUGOUT("Auto-negotiation enabled\n");

   957 

   958     E1000_WRITE_REG(hw, TXCW, txcw);

   959     E1000_WRITE_REG(hw, CTRL, ctrl);

   960     E1000_WRITE_FLUSH(hw);

   961 

   962     hw->txcw = txcw;

   963     msec_delay(1);

   964 

   965     /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"

   966      * indication in the Device Status Register.  Time-out if a link isn't

   967      * seen in 500 milliseconds seconds (Auto-negotiation should complete in

   968      * less than 500 milliseconds even if the other end is doing it in SW).

   969      * For internal serdes, we just assume a signal is present, then poll.

   970      */

   971     if(hw->media_type == e1000_media_type_internal_serdes ||

   972        (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   973         DEBUGOUT("Looking for Link\n");

   974         for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   975             msec_delay(10);

   976             status = E1000_READ_REG(hw, STATUS);

   977             if(status & E1000_STATUS_LU) break;

   978         }

   979         if(i == (LINK_UP_TIMEOUT / 10)) {

   980             DEBUGOUT("Never got a valid link from auto-neg!!!\n");

   981             hw->autoneg_failed = 1;

   982             /* AutoNeg failed to achieve a link, so we'll call

   983              * e1000_check_for_link. This routine will force the link up if

   984              * we detect a signal. This will allow us to communicate with

   985              * non-autonegotiating link partners.

   986              */

   987             ret_val = e1000_check_for_link(hw);

   988             if(ret_val) {

   989                 DEBUGOUT("Error while checking for link\n");

   990                 return ret_val;

   991             }

   992             hw->autoneg_failed = 0;

   993         } else {

   994             hw->autoneg_failed = 0;

   995             DEBUGOUT("Valid Link Found\n");

   996         }

   997     } else {

   998         DEBUGOUT("No Signal Detected\n");

   999     }

  1000     return E1000_SUCCESS;

  1001 }

  1002 

  1003 /******************************************************************************

  1004 * Make sure we have a valid PHY and change PHY mode before link setup.

  1005 *

  1006 * hw - Struct containing variables accessed by shared code

  1007 ******************************************************************************/

  1008 static int32_t

  1009 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1010 {

  1011     uint32_t ctrl;

  1012     int32_t ret_val;

  1013     uint16_t phy_data;

  1014 

  1015     DEBUGFUNC("e1000_copper_link_preconfig");

  1016 

  1017     ctrl = E1000_READ_REG(hw, CTRL);

  1018     /* With 82543, we need to force speed and duplex on the MAC equal to what

  1019      * the PHY speed and duplex configuration is. In addition, we need to

  1020      * perform a hardware reset on the PHY to take it out of reset.

  1021      */

  1022     if(hw->mac_type > e1000_82543) {

  1023         ctrl |= E1000_CTRL_SLU;

  1024         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1025         E1000_WRITE_REG(hw, CTRL, ctrl);

  1026     } else {

  1027         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1028         E1000_WRITE_REG(hw, CTRL, ctrl);

  1029         ret_val = e1000_phy_hw_reset(hw);

  1030         if(ret_val)

  1031             return ret_val;

  1032     }

  1033 

  1034     /* Make sure we have a valid PHY */

  1035     ret_val = e1000_detect_gig_phy(hw);

  1036     if(ret_val) {

  1037         DEBUGOUT("Error, did not detect valid phy.\n");

  1038         return ret_val;

  1039     }

  1040     DEBUGOUT1("Phy ID = %x \n", hw->phy_id);

  1041 

  1042     /* Set PHY to class A mode (if necessary) */

  1043     ret_val = e1000_set_phy_mode(hw);

  1044     if(ret_val)

  1045         return ret_val;

  1046 

  1047     if((hw->mac_type == e1000_82545_rev_3) ||

  1048        (hw->mac_type == e1000_82546_rev_3)) {

  1049         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1050         phy_data |= 0x00000008;

  1051         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1052     }

  1053 

  1054     if(hw->mac_type <= e1000_82543 ||

  1055        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1056        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)

  1057         hw->phy_reset_disable = FALSE;

  1058 

  1059    return E1000_SUCCESS;

  1060 }

  1061 

  1062 

  1063 /********************************************************************

  1064 * Copper link setup for e1000_phy_igp series.

  1065 *

  1066 * hw - Struct containing variables accessed by shared code

  1067 *********************************************************************/

  1068 static int32_t

  1069 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1070 {

  1071     uint32_t led_ctrl;

  1072     int32_t ret_val;

  1073     uint16_t phy_data;

  1074 

  1075     DEBUGFUNC("e1000_copper_link_igp_setup");

  1076 

  1077     if (hw->phy_reset_disable)

  1078         return E1000_SUCCESS;

  1079     

  1080     ret_val = e1000_phy_reset(hw);

  1081     if (ret_val) {

  1082         DEBUGOUT("Error Resetting the PHY\n");

  1083         return ret_val;

  1084     }

  1085 

  1086     /* Wait 10ms for MAC to configure PHY from eeprom settings */

  1087     msec_delay(15);

  1088 

  1089     /* Configure activity LED after PHY reset */

  1090     led_ctrl = E1000_READ_REG(hw, LEDCTL);

  1091     led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1092     led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1093     E1000_WRITE_REG(hw, LEDCTL, led_ctrl);

  1094 

  1095     /* disable lplu d3 during driver init */

  1096     ret_val = e1000_set_d3_lplu_state(hw, FALSE);

  1097     if (ret_val) {

  1098         DEBUGOUT("Error Disabling LPLU D3\n");

  1099         return ret_val;

  1100     }

  1101 

  1102     /* disable lplu d0 during driver init */

  1103     ret_val = e1000_set_d0_lplu_state(hw, FALSE);

  1104     if (ret_val) {

  1105         DEBUGOUT("Error Disabling LPLU D0\n");

  1106         return ret_val;

  1107     }

  1108     /* Configure mdi-mdix settings */

  1109     ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1110     if (ret_val)

  1111         return ret_val;

  1112 

  1113     if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

  1114         hw->dsp_config_state = e1000_dsp_config_disabled;

  1115         /* Force MDI for earlier revs of the IGP PHY */

  1116         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);

  1117         hw->mdix = 1;

  1118 

  1119     } else {

  1120         hw->dsp_config_state = e1000_dsp_config_enabled;

  1121         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;

  1122 

  1123         switch (hw->mdix) {

  1124         case 1:

  1125             phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;

  1126             break;

  1127         case 2:

  1128             phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;

  1129             break;

  1130         case 0:

  1131         default:

  1132             phy_data |= IGP01E1000_PSCR_AUTO_MDIX;

  1133             break;

  1134         }

  1135     }

  1136     ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);