devices/r8169-3.16-orig.c
branchstable-1.5
changeset 2588 792892ab4806
equal deleted inserted replaced
2587:afd76ee3aa87 2588:792892ab4806
       
     1 /*
       
     2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
       
     3  *
       
     4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
       
     5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
       
     6  * Copyright (c) a lot of people too. Please respect their work.
       
     7  *
       
     8  * See MAINTAINERS file for support contact information.
       
     9  */
       
    10 
       
    11 #include <linux/module.h>
       
    12 #include <linux/moduleparam.h>
       
    13 #include <linux/pci.h>
       
    14 #include <linux/netdevice.h>
       
    15 #include <linux/etherdevice.h>
       
    16 #include <linux/delay.h>
       
    17 #include <linux/ethtool.h>
       
    18 #include <linux/mii.h>
       
    19 #include <linux/if_vlan.h>
       
    20 #include <linux/crc32.h>
       
    21 #include <linux/in.h>
       
    22 #include <linux/ip.h>
       
    23 #include <linux/tcp.h>
       
    24 #include <linux/interrupt.h>
       
    25 #include <linux/dma-mapping.h>
       
    26 #include <linux/pm_runtime.h>
       
    27 #include <linux/firmware.h>
       
    28 #include <linux/pci-aspm.h>
       
    29 #include <linux/prefetch.h>
       
    30 
       
    31 #include <asm/io.h>
       
    32 #include <asm/irq.h>
       
    33 
       
    34 #define RTL8169_VERSION "2.3LK-NAPI"
       
    35 #define MODULENAME "r8169"
       
    36 #define PFX MODULENAME ": "
       
    37 
       
    38 #define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
       
    39 #define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
       
    40 #define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
       
    41 #define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
       
    42 #define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
       
    43 #define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
       
    44 #define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
       
    45 #define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
       
    46 #define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
       
    47 #define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
       
    48 #define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"
       
    49 #define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"
       
    50 #define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"
       
    51 #define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"
       
    52 #define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"
       
    53 
       
    54 #ifdef RTL8169_DEBUG
       
    55 #define assert(expr) \
       
    56 	if (!(expr)) {					\
       
    57 		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
       
    58 		#expr,__FILE__,__func__,__LINE__);		\
       
    59 	}
       
    60 #define dprintk(fmt, args...) \
       
    61 	do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
       
    62 #else
       
    63 #define assert(expr) do {} while (0)
       
    64 #define dprintk(fmt, args...)	do {} while (0)
       
    65 #endif /* RTL8169_DEBUG */
       
    66 
       
    67 #define R8169_MSG_DEFAULT \
       
    68 	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
       
    69 
       
    70 #define TX_SLOTS_AVAIL(tp) \
       
    71 	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
       
    72 
       
    73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
       
    74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
       
    75 	(TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
       
    76 
       
    77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
       
    78    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
       
    79 static const int multicast_filter_limit = 32;
       
    80 
       
    81 #define MAX_READ_REQUEST_SHIFT	12
       
    82 #define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */
       
    83 #define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
       
    84 
       
    85 #define R8169_REGS_SIZE		256
       
    86 #define R8169_NAPI_WEIGHT	64
       
    87 #define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
       
    88 #define NUM_RX_DESC	256U	/* Number of Rx descriptor registers */
       
    89 #define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
       
    90 #define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))
       
    91 
       
    92 #define RTL8169_TX_TIMEOUT	(6*HZ)
       
    93 #define RTL8169_PHY_TIMEOUT	(10*HZ)
       
    94 
       
    95 /* write/read MMIO register */
       
    96 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
       
    97 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
       
    98 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
       
    99 #define RTL_R8(reg)		readb (ioaddr + (reg))
       
   100 #define RTL_R16(reg)		readw (ioaddr + (reg))
       
   101 #define RTL_R32(reg)		readl (ioaddr + (reg))
       
   102 
       
   103 enum mac_version {
       
   104 	RTL_GIGA_MAC_VER_01 = 0,
       
   105 	RTL_GIGA_MAC_VER_02,
       
   106 	RTL_GIGA_MAC_VER_03,
       
   107 	RTL_GIGA_MAC_VER_04,
       
   108 	RTL_GIGA_MAC_VER_05,
       
   109 	RTL_GIGA_MAC_VER_06,
       
   110 	RTL_GIGA_MAC_VER_07,
       
   111 	RTL_GIGA_MAC_VER_08,
       
   112 	RTL_GIGA_MAC_VER_09,
       
   113 	RTL_GIGA_MAC_VER_10,
       
   114 	RTL_GIGA_MAC_VER_11,
       
   115 	RTL_GIGA_MAC_VER_12,
       
   116 	RTL_GIGA_MAC_VER_13,
       
   117 	RTL_GIGA_MAC_VER_14,
       
   118 	RTL_GIGA_MAC_VER_15,
       
   119 	RTL_GIGA_MAC_VER_16,
       
   120 	RTL_GIGA_MAC_VER_17,
       
   121 	RTL_GIGA_MAC_VER_18,
       
   122 	RTL_GIGA_MAC_VER_19,
       
   123 	RTL_GIGA_MAC_VER_20,
       
   124 	RTL_GIGA_MAC_VER_21,
       
   125 	RTL_GIGA_MAC_VER_22,
       
   126 	RTL_GIGA_MAC_VER_23,
       
   127 	RTL_GIGA_MAC_VER_24,
       
   128 	RTL_GIGA_MAC_VER_25,
       
   129 	RTL_GIGA_MAC_VER_26,
       
   130 	RTL_GIGA_MAC_VER_27,
       
   131 	RTL_GIGA_MAC_VER_28,
       
   132 	RTL_GIGA_MAC_VER_29,
       
   133 	RTL_GIGA_MAC_VER_30,
       
   134 	RTL_GIGA_MAC_VER_31,
       
   135 	RTL_GIGA_MAC_VER_32,
       
   136 	RTL_GIGA_MAC_VER_33,
       
   137 	RTL_GIGA_MAC_VER_34,
       
   138 	RTL_GIGA_MAC_VER_35,
       
   139 	RTL_GIGA_MAC_VER_36,
       
   140 	RTL_GIGA_MAC_VER_37,
       
   141 	RTL_GIGA_MAC_VER_38,
       
   142 	RTL_GIGA_MAC_VER_39,
       
   143 	RTL_GIGA_MAC_VER_40,
       
   144 	RTL_GIGA_MAC_VER_41,
       
   145 	RTL_GIGA_MAC_VER_42,
       
   146 	RTL_GIGA_MAC_VER_43,
       
   147 	RTL_GIGA_MAC_VER_44,
       
   148 	RTL_GIGA_MAC_NONE   = 0xff,
       
   149 };
       
   150 
       
   151 enum rtl_tx_desc_version {
       
   152 	RTL_TD_0	= 0,
       
   153 	RTL_TD_1	= 1,
       
   154 };
       
   155 
       
   156 #define JUMBO_1K	ETH_DATA_LEN
       
   157 #define JUMBO_4K	(4*1024 - ETH_HLEN - 2)
       
   158 #define JUMBO_6K	(6*1024 - ETH_HLEN - 2)
       
   159 #define JUMBO_7K	(7*1024 - ETH_HLEN - 2)
       
   160 #define JUMBO_9K	(9*1024 - ETH_HLEN - 2)
       
   161 
       
   162 #define _R(NAME,TD,FW,SZ,B) {	\
       
   163 	.name = NAME,		\
       
   164 	.txd_version = TD,	\
       
   165 	.fw_name = FW,		\
       
   166 	.jumbo_max = SZ,	\
       
   167 	.jumbo_tx_csum = B	\
       
   168 }
       
   169 
       
   170 static const struct {
       
   171 	const char *name;
       
   172 	enum rtl_tx_desc_version txd_version;
       
   173 	const char *fw_name;
       
   174 	u16 jumbo_max;
       
   175 	bool jumbo_tx_csum;
       
   176 } rtl_chip_infos[] = {
       
   177 	/* PCI devices. */
       
   178 	[RTL_GIGA_MAC_VER_01] =
       
   179 		_R("RTL8169",		RTL_TD_0, NULL, JUMBO_7K, true),
       
   180 	[RTL_GIGA_MAC_VER_02] =
       
   181 		_R("RTL8169s",		RTL_TD_0, NULL, JUMBO_7K, true),
       
   182 	[RTL_GIGA_MAC_VER_03] =
       
   183 		_R("RTL8110s",		RTL_TD_0, NULL, JUMBO_7K, true),
       
   184 	[RTL_GIGA_MAC_VER_04] =
       
   185 		_R("RTL8169sb/8110sb",	RTL_TD_0, NULL, JUMBO_7K, true),
       
   186 	[RTL_GIGA_MAC_VER_05] =
       
   187 		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
       
   188 	[RTL_GIGA_MAC_VER_06] =
       
   189 		_R("RTL8169sc/8110sc",	RTL_TD_0, NULL, JUMBO_7K, true),
       
   190 	/* PCI-E devices. */
       
   191 	[RTL_GIGA_MAC_VER_07] =
       
   192 		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
       
   193 	[RTL_GIGA_MAC_VER_08] =
       
   194 		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
       
   195 	[RTL_GIGA_MAC_VER_09] =
       
   196 		_R("RTL8102e",		RTL_TD_1, NULL, JUMBO_1K, true),
       
   197 	[RTL_GIGA_MAC_VER_10] =
       
   198 		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
       
   199 	[RTL_GIGA_MAC_VER_11] =
       
   200 		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
       
   201 	[RTL_GIGA_MAC_VER_12] =
       
   202 		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
       
   203 	[RTL_GIGA_MAC_VER_13] =
       
   204 		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
       
   205 	[RTL_GIGA_MAC_VER_14] =
       
   206 		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
       
   207 	[RTL_GIGA_MAC_VER_15] =
       
   208 		_R("RTL8100e",		RTL_TD_0, NULL, JUMBO_1K, true),
       
   209 	[RTL_GIGA_MAC_VER_16] =
       
   210 		_R("RTL8101e",		RTL_TD_0, NULL, JUMBO_1K, true),
       
   211 	[RTL_GIGA_MAC_VER_17] =
       
   212 		_R("RTL8168b/8111b",	RTL_TD_0, NULL, JUMBO_4K, false),
       
   213 	[RTL_GIGA_MAC_VER_18] =
       
   214 		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   215 	[RTL_GIGA_MAC_VER_19] =
       
   216 		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   217 	[RTL_GIGA_MAC_VER_20] =
       
   218 		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   219 	[RTL_GIGA_MAC_VER_21] =
       
   220 		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   221 	[RTL_GIGA_MAC_VER_22] =
       
   222 		_R("RTL8168c/8111c",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   223 	[RTL_GIGA_MAC_VER_23] =
       
   224 		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   225 	[RTL_GIGA_MAC_VER_24] =
       
   226 		_R("RTL8168cp/8111cp",	RTL_TD_1, NULL, JUMBO_6K, false),
       
   227 	[RTL_GIGA_MAC_VER_25] =
       
   228 		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_1,
       
   229 							JUMBO_9K, false),
       
   230 	[RTL_GIGA_MAC_VER_26] =
       
   231 		_R("RTL8168d/8111d",	RTL_TD_1, FIRMWARE_8168D_2,
       
   232 							JUMBO_9K, false),
       
   233 	[RTL_GIGA_MAC_VER_27] =
       
   234 		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
       
   235 	[RTL_GIGA_MAC_VER_28] =
       
   236 		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
       
   237 	[RTL_GIGA_MAC_VER_29] =
       
   238 		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
       
   239 							JUMBO_1K, true),
       
   240 	[RTL_GIGA_MAC_VER_30] =
       
   241 		_R("RTL8105e",		RTL_TD_1, FIRMWARE_8105E_1,
       
   242 							JUMBO_1K, true),
       
   243 	[RTL_GIGA_MAC_VER_31] =
       
   244 		_R("RTL8168dp/8111dp",	RTL_TD_1, NULL, JUMBO_9K, false),
       
   245 	[RTL_GIGA_MAC_VER_32] =
       
   246 		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_1,
       
   247 							JUMBO_9K, false),
       
   248 	[RTL_GIGA_MAC_VER_33] =
       
   249 		_R("RTL8168e/8111e",	RTL_TD_1, FIRMWARE_8168E_2,
       
   250 							JUMBO_9K, false),
       
   251 	[RTL_GIGA_MAC_VER_34] =
       
   252 		_R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
       
   253 							JUMBO_9K, false),
       
   254 	[RTL_GIGA_MAC_VER_35] =
       
   255 		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_1,
       
   256 							JUMBO_9K, false),
       
   257 	[RTL_GIGA_MAC_VER_36] =
       
   258 		_R("RTL8168f/8111f",	RTL_TD_1, FIRMWARE_8168F_2,
       
   259 							JUMBO_9K, false),
       
   260 	[RTL_GIGA_MAC_VER_37] =
       
   261 		_R("RTL8402",		RTL_TD_1, FIRMWARE_8402_1,
       
   262 							JUMBO_1K, true),
       
   263 	[RTL_GIGA_MAC_VER_38] =
       
   264 		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_1,
       
   265 							JUMBO_9K, false),
       
   266 	[RTL_GIGA_MAC_VER_39] =
       
   267 		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_1,
       
   268 							JUMBO_1K, true),
       
   269 	[RTL_GIGA_MAC_VER_40] =
       
   270 		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_2,
       
   271 							JUMBO_9K, false),
       
   272 	[RTL_GIGA_MAC_VER_41] =
       
   273 		_R("RTL8168g/8111g",	RTL_TD_1, NULL, JUMBO_9K, false),
       
   274 	[RTL_GIGA_MAC_VER_42] =
       
   275 		_R("RTL8168g/8111g",	RTL_TD_1, FIRMWARE_8168G_3,
       
   276 							JUMBO_9K, false),
       
   277 	[RTL_GIGA_MAC_VER_43] =
       
   278 		_R("RTL8106e",		RTL_TD_1, FIRMWARE_8106E_2,
       
   279 							JUMBO_1K, true),
       
   280 	[RTL_GIGA_MAC_VER_44] =
       
   281 		_R("RTL8411",		RTL_TD_1, FIRMWARE_8411_2,
       
   282 							JUMBO_9K, false),
       
   283 };
       
   284 #undef _R
       
   285 
       
   286 enum cfg_version {
       
   287 	RTL_CFG_0 = 0x00,
       
   288 	RTL_CFG_1,
       
   289 	RTL_CFG_2
       
   290 };
       
   291 
       
   292 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
       
   293 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
       
   294 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
       
   295 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
       
   296 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
       
   297 	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
       
   298 	{ PCI_VENDOR_ID_DLINK,			0x4300,
       
   299 		PCI_VENDOR_ID_DLINK, 0x4b10,		 0, 0, RTL_CFG_1 },
       
   300 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
       
   301 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4302), 0, 0, RTL_CFG_0 },
       
   302 	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
       
   303 	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
       
   304 	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
       
   305 		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
       
   306 	{ 0x0001,				0x8168,
       
   307 		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
       
   308 	{0,},
       
   309 };
       
   310 
       
   311 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
       
   312 
       
   313 static int rx_buf_sz = 16383;
       
   314 static int use_dac;
       
   315 static struct {
       
   316 	u32 msg_enable;
       
   317 } debug = { -1 };
       
   318 
       
   319 enum rtl_registers {
       
   320 	MAC0		= 0,	/* Ethernet hardware address. */
       
   321 	MAC4		= 4,
       
   322 	MAR0		= 8,	/* Multicast filter. */
       
   323 	CounterAddrLow		= 0x10,
       
   324 	CounterAddrHigh		= 0x14,
       
   325 	TxDescStartAddrLow	= 0x20,
       
   326 	TxDescStartAddrHigh	= 0x24,
       
   327 	TxHDescStartAddrLow	= 0x28,
       
   328 	TxHDescStartAddrHigh	= 0x2c,
       
   329 	FLASH		= 0x30,
       
   330 	ERSR		= 0x36,
       
   331 	ChipCmd		= 0x37,
       
   332 	TxPoll		= 0x38,
       
   333 	IntrMask	= 0x3c,
       
   334 	IntrStatus	= 0x3e,
       
   335 
       
   336 	TxConfig	= 0x40,
       
   337 #define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
       
   338 #define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
       
   339 
       
   340 	RxConfig	= 0x44,
       
   341 #define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
       
   342 #define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
       
   343 #define	RXCFG_FIFO_SHIFT		13
       
   344 					/* No threshold before first PCI xfer */
       
   345 #define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
       
   346 #define	RX_EARLY_OFF			(1 << 11)
       
   347 #define	RXCFG_DMA_SHIFT			8
       
   348 					/* Unlimited maximum PCI burst. */
       
   349 #define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
       
   350 
       
   351 	RxMissed	= 0x4c,
       
   352 	Cfg9346		= 0x50,
       
   353 	Config0		= 0x51,
       
   354 	Config1		= 0x52,
       
   355 	Config2		= 0x53,
       
   356 #define PME_SIGNAL			(1 << 5)	/* 8168c and later */
       
   357 
       
   358 	Config3		= 0x54,
       
   359 	Config4		= 0x55,
       
   360 	Config5		= 0x56,
       
   361 	MultiIntr	= 0x5c,
       
   362 	PHYAR		= 0x60,
       
   363 	PHYstatus	= 0x6c,
       
   364 	RxMaxSize	= 0xda,
       
   365 	CPlusCmd	= 0xe0,
       
   366 	IntrMitigate	= 0xe2,
       
   367 	RxDescAddrLow	= 0xe4,
       
   368 	RxDescAddrHigh	= 0xe8,
       
   369 	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */
       
   370 
       
   371 #define NoEarlyTx	0x3f	/* Max value : no early transmit. */
       
   372 
       
   373 	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */
       
   374 
       
   375 #define TxPacketMax	(8064 >> 7)
       
   376 #define EarlySize	0x27
       
   377 
       
   378 	FuncEvent	= 0xf0,
       
   379 	FuncEventMask	= 0xf4,
       
   380 	FuncPresetState	= 0xf8,
       
   381 	FuncForceEvent	= 0xfc,
       
   382 };
       
   383 
       
   384 enum rtl8110_registers {
       
   385 	TBICSR			= 0x64,
       
   386 	TBI_ANAR		= 0x68,
       
   387 	TBI_LPAR		= 0x6a,
       
   388 };
       
   389 
       
   390 enum rtl8168_8101_registers {
       
   391 	CSIDR			= 0x64,
       
   392 	CSIAR			= 0x68,
       
   393 #define	CSIAR_FLAG			0x80000000
       
   394 #define	CSIAR_WRITE_CMD			0x80000000
       
   395 #define	CSIAR_BYTE_ENABLE		0x0f
       
   396 #define	CSIAR_BYTE_ENABLE_SHIFT		12
       
   397 #define	CSIAR_ADDR_MASK			0x0fff
       
   398 #define CSIAR_FUNC_CARD			0x00000000
       
   399 #define CSIAR_FUNC_SDIO			0x00010000
       
   400 #define CSIAR_FUNC_NIC			0x00020000
       
   401 #define CSIAR_FUNC_NIC2			0x00010000
       
   402 	PMCH			= 0x6f,
       
   403 	EPHYAR			= 0x80,
       
   404 #define	EPHYAR_FLAG			0x80000000
       
   405 #define	EPHYAR_WRITE_CMD		0x80000000
       
   406 #define	EPHYAR_REG_MASK			0x1f
       
   407 #define	EPHYAR_REG_SHIFT		16
       
   408 #define	EPHYAR_DATA_MASK		0xffff
       
   409 	DLLPR			= 0xd0,
       
   410 #define	PFM_EN				(1 << 6)
       
   411 	DBG_REG			= 0xd1,
       
   412 #define	FIX_NAK_1			(1 << 4)
       
   413 #define	FIX_NAK_2			(1 << 3)
       
   414 	TWSI			= 0xd2,
       
   415 	MCU			= 0xd3,
       
   416 #define	NOW_IS_OOB			(1 << 7)
       
   417 #define	TX_EMPTY			(1 << 5)
       
   418 #define	RX_EMPTY			(1 << 4)
       
   419 #define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)
       
   420 #define	EN_NDP				(1 << 3)
       
   421 #define	EN_OOB_RESET			(1 << 2)
       
   422 #define	LINK_LIST_RDY			(1 << 1)
       
   423 	EFUSEAR			= 0xdc,
       
   424 #define	EFUSEAR_FLAG			0x80000000
       
   425 #define	EFUSEAR_WRITE_CMD		0x80000000
       
   426 #define	EFUSEAR_READ_CMD		0x00000000
       
   427 #define	EFUSEAR_REG_MASK		0x03ff
       
   428 #define	EFUSEAR_REG_SHIFT		8
       
   429 #define	EFUSEAR_DATA_MASK		0xff
       
   430 };
       
   431 
       
   432 enum rtl8168_registers {
       
   433 	LED_FREQ		= 0x1a,
       
   434 	EEE_LED			= 0x1b,
       
   435 	ERIDR			= 0x70,
       
   436 	ERIAR			= 0x74,
       
   437 #define ERIAR_FLAG			0x80000000
       
   438 #define ERIAR_WRITE_CMD			0x80000000
       
   439 #define ERIAR_READ_CMD			0x00000000
       
   440 #define ERIAR_ADDR_BYTE_ALIGN		4
       
   441 #define ERIAR_TYPE_SHIFT		16
       
   442 #define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
       
   443 #define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
       
   444 #define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
       
   445 #define ERIAR_MASK_SHIFT		12
       
   446 #define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
       
   447 #define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
       
   448 #define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)
       
   449 #define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
       
   450 	EPHY_RXER_NUM		= 0x7c,
       
   451 	OCPDR			= 0xb0,	/* OCP GPHY access */
       
   452 #define OCPDR_WRITE_CMD			0x80000000
       
   453 #define OCPDR_READ_CMD			0x00000000
       
   454 #define OCPDR_REG_MASK			0x7f
       
   455 #define OCPDR_GPHY_REG_SHIFT		16
       
   456 #define OCPDR_DATA_MASK			0xffff
       
   457 	OCPAR			= 0xb4,
       
   458 #define OCPAR_FLAG			0x80000000
       
   459 #define OCPAR_GPHY_WRITE_CMD		0x8000f060
       
   460 #define OCPAR_GPHY_READ_CMD		0x0000f060
       
   461 	GPHY_OCP		= 0xb8,
       
   462 	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
       
   463 	MISC			= 0xf0,	/* 8168e only. */
       
   464 #define TXPLA_RST			(1 << 29)
       
   465 #define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */
       
   466 #define PWM_EN				(1 << 22)
       
   467 #define RXDV_GATED_EN			(1 << 19)
       
   468 #define EARLY_TALLY_EN			(1 << 16)
       
   469 };
       
   470 
       
   471 enum rtl_register_content {
       
   472 	/* InterruptStatusBits */
       
   473 	SYSErr		= 0x8000,
       
   474 	PCSTimeout	= 0x4000,
       
   475 	SWInt		= 0x0100,
       
   476 	TxDescUnavail	= 0x0080,
       
   477 	RxFIFOOver	= 0x0040,
       
   478 	LinkChg		= 0x0020,
       
   479 	RxOverflow	= 0x0010,
       
   480 	TxErr		= 0x0008,
       
   481 	TxOK		= 0x0004,
       
   482 	RxErr		= 0x0002,
       
   483 	RxOK		= 0x0001,
       
   484 
       
   485 	/* RxStatusDesc */
       
   486 	RxBOVF	= (1 << 24),
       
   487 	RxFOVF	= (1 << 23),
       
   488 	RxRWT	= (1 << 22),
       
   489 	RxRES	= (1 << 21),
       
   490 	RxRUNT	= (1 << 20),
       
   491 	RxCRC	= (1 << 19),
       
   492 
       
   493 	/* ChipCmdBits */
       
   494 	StopReq		= 0x80,
       
   495 	CmdReset	= 0x10,
       
   496 	CmdRxEnb	= 0x08,
       
   497 	CmdTxEnb	= 0x04,
       
   498 	RxBufEmpty	= 0x01,
       
   499 
       
   500 	/* TXPoll register p.5 */
       
   501 	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
       
   502 	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
       
   503 	FSWInt		= 0x01,		/* Forced software interrupt */
       
   504 
       
   505 	/* Cfg9346Bits */
       
   506 	Cfg9346_Lock	= 0x00,
       
   507 	Cfg9346_Unlock	= 0xc0,
       
   508 
       
   509 	/* rx_mode_bits */
       
   510 	AcceptErr	= 0x20,
       
   511 	AcceptRunt	= 0x10,
       
   512 	AcceptBroadcast	= 0x08,
       
   513 	AcceptMulticast	= 0x04,
       
   514 	AcceptMyPhys	= 0x02,
       
   515 	AcceptAllPhys	= 0x01,
       
   516 #define RX_CONFIG_ACCEPT_MASK		0x3f
       
   517 
       
   518 	/* TxConfigBits */
       
   519 	TxInterFrameGapShift = 24,
       
   520 	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */
       
   521 
       
   522 	/* Config1 register p.24 */
       
   523 	LEDS1		= (1 << 7),
       
   524 	LEDS0		= (1 << 6),
       
   525 	Speed_down	= (1 << 4),
       
   526 	MEMMAP		= (1 << 3),
       
   527 	IOMAP		= (1 << 2),
       
   528 	VPD		= (1 << 1),
       
   529 	PMEnable	= (1 << 0),	/* Power Management Enable */
       
   530 
       
   531 	/* Config2 register p. 25 */
       
   532 	ClkReqEn	= (1 << 7),	/* Clock Request Enable */
       
   533 	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
       
   534 	PCI_Clock_66MHz = 0x01,
       
   535 	PCI_Clock_33MHz = 0x00,
       
   536 
       
   537 	/* Config3 register p.25 */
       
   538 	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
       
   539 	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
       
   540 	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
       
   541 	Rdy_to_L23	= (1 << 1),	/* L23 Enable */
       
   542 	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
       
   543 
       
   544 	/* Config4 register */
       
   545 	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */
       
   546 
       
   547 	/* Config5 register p.27 */
       
   548 	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
       
   549 	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
       
   550 	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
       
   551 	Spi_en		= (1 << 3),
       
   552 	LanWake		= (1 << 1),	/* LanWake enable/disable */
       
   553 	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
       
   554 	ASPM_en		= (1 << 0),	/* ASPM enable */
       
   555 
       
   556 	/* TBICSR p.28 */
       
   557 	TBIReset	= 0x80000000,
       
   558 	TBILoopback	= 0x40000000,
       
   559 	TBINwEnable	= 0x20000000,
       
   560 	TBINwRestart	= 0x10000000,
       
   561 	TBILinkOk	= 0x02000000,
       
   562 	TBINwComplete	= 0x01000000,
       
   563 
       
   564 	/* CPlusCmd p.31 */
       
   565 	EnableBist	= (1 << 15),	// 8168 8101
       
   566 	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
       
   567 	Normal_mode	= (1 << 13),	// unused
       
   568 	Force_half_dup	= (1 << 12),	// 8168 8101
       
   569 	Force_rxflow_en	= (1 << 11),	// 8168 8101
       
   570 	Force_txflow_en	= (1 << 10),	// 8168 8101
       
   571 	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
       
   572 	ASF		= (1 << 8),	// 8168 8101
       
   573 	PktCntrDisable	= (1 << 7),	// 8168 8101
       
   574 	Mac_dbgo_sel	= 0x001c,	// 8168
       
   575 	RxVlan		= (1 << 6),
       
   576 	RxChkSum	= (1 << 5),
       
   577 	PCIDAC		= (1 << 4),
       
   578 	PCIMulRW	= (1 << 3),
       
   579 	INTT_0		= 0x0000,	// 8168
       
   580 	INTT_1		= 0x0001,	// 8168
       
   581 	INTT_2		= 0x0002,	// 8168
       
   582 	INTT_3		= 0x0003,	// 8168
       
   583 
       
   584 	/* rtl8169_PHYstatus */
       
   585 	TBI_Enable	= 0x80,
       
   586 	TxFlowCtrl	= 0x40,
       
   587 	RxFlowCtrl	= 0x20,
       
   588 	_1000bpsF	= 0x10,
       
   589 	_100bps		= 0x08,
       
   590 	_10bps		= 0x04,
       
   591 	LinkStatus	= 0x02,
       
   592 	FullDup		= 0x01,
       
   593 
       
   594 	/* _TBICSRBit */
       
   595 	TBILinkOK	= 0x02000000,
       
   596 
       
   597 	/* DumpCounterCommand */
       
   598 	CounterDump	= 0x8,
       
   599 };
       
   600 
       
   601 enum rtl_desc_bit {
       
   602 	/* First doubleword. */
       
   603 	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
       
   604 	RingEnd		= (1 << 30), /* End of descriptor ring */
       
   605 	FirstFrag	= (1 << 29), /* First segment of a packet */
       
   606 	LastFrag	= (1 << 28), /* Final segment of a packet */
       
   607 };
       
   608 
       
   609 /* Generic case. */
       
   610 enum rtl_tx_desc_bit {
       
   611 	/* First doubleword. */
       
   612 	TD_LSO		= (1 << 27),		/* Large Send Offload */
       
   613 #define TD_MSS_MAX			0x07ffu	/* MSS value */
       
   614 
       
   615 	/* Second doubleword. */
       
   616 	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
       
   617 };
       
   618 
       
   619 /* 8169, 8168b and 810x except 8102e. */
       
   620 enum rtl_tx_desc_bit_0 {
       
   621 	/* First doubleword. */
       
   622 #define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
       
   623 	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
       
   624 	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
       
   625 	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
       
   626 };
       
   627 
       
   628 /* 8102e, 8168c and beyond. */
       
   629 enum rtl_tx_desc_bit_1 {
       
   630 	/* Second doubleword. */
       
   631 #define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
       
   632 	TD1_IP_CS	= (1 << 29),		/* Calculate IP checksum */
       
   633 	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
       
   634 	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
       
   635 };
       
   636 
       
   637 static const struct rtl_tx_desc_info {
       
   638 	struct {
       
   639 		u32 udp;
       
   640 		u32 tcp;
       
   641 	} checksum;
       
   642 	u16 mss_shift;
       
   643 	u16 opts_offset;
       
   644 } tx_desc_info [] = {
       
   645 	[RTL_TD_0] = {
       
   646 		.checksum = {
       
   647 			.udp	= TD0_IP_CS | TD0_UDP_CS,
       
   648 			.tcp	= TD0_IP_CS | TD0_TCP_CS
       
   649 		},
       
   650 		.mss_shift	= TD0_MSS_SHIFT,
       
   651 		.opts_offset	= 0
       
   652 	},
       
   653 	[RTL_TD_1] = {
       
   654 		.checksum = {
       
   655 			.udp	= TD1_IP_CS | TD1_UDP_CS,
       
   656 			.tcp	= TD1_IP_CS | TD1_TCP_CS
       
   657 		},
       
   658 		.mss_shift	= TD1_MSS_SHIFT,
       
   659 		.opts_offset	= 1
       
   660 	}
       
   661 };
       
   662 
       
   663 enum rtl_rx_desc_bit {
       
   664 	/* Rx private */
       
   665 	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
       
   666 	PID0		= (1 << 17), /* Protocol ID bit 2/2 */
       
   667 
       
   668 #define RxProtoUDP	(PID1)
       
   669 #define RxProtoTCP	(PID0)
       
   670 #define RxProtoIP	(PID1 | PID0)
       
   671 #define RxProtoMask	RxProtoIP
       
   672 
       
   673 	IPFail		= (1 << 16), /* IP checksum failed */
       
   674 	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
       
   675 	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
       
   676 	RxVlanTag	= (1 << 16), /* VLAN tag available */
       
   677 };
       
   678 
       
   679 #define RsvdMask	0x3fffc000
       
   680 
       
   681 struct TxDesc {
       
   682 	__le32 opts1;
       
   683 	__le32 opts2;
       
   684 	__le64 addr;
       
   685 };
       
   686 
       
   687 struct RxDesc {
       
   688 	__le32 opts1;
       
   689 	__le32 opts2;
       
   690 	__le64 addr;
       
   691 };
       
   692 
       
   693 struct ring_info {
       
   694 	struct sk_buff	*skb;
       
   695 	u32		len;
       
   696 	u8		__pad[sizeof(void *) - sizeof(u32)];
       
   697 };
       
   698 
       
   699 enum features {
       
   700 	RTL_FEATURE_WOL		= (1 << 0),
       
   701 	RTL_FEATURE_MSI		= (1 << 1),
       
   702 	RTL_FEATURE_GMII	= (1 << 2),
       
   703 };
       
   704 
       
   705 struct rtl8169_counters {
       
   706 	__le64	tx_packets;
       
   707 	__le64	rx_packets;
       
   708 	__le64	tx_errors;
       
   709 	__le32	rx_errors;
       
   710 	__le16	rx_missed;
       
   711 	__le16	align_errors;
       
   712 	__le32	tx_one_collision;
       
   713 	__le32	tx_multi_collision;
       
   714 	__le64	rx_unicast;
       
   715 	__le64	rx_broadcast;
       
   716 	__le32	rx_multicast;
       
   717 	__le16	tx_aborted;
       
   718 	__le16	tx_underun;
       
   719 };
       
   720 
       
   721 enum rtl_flag {
       
   722 	RTL_FLAG_TASK_ENABLED,
       
   723 	RTL_FLAG_TASK_SLOW_PENDING,
       
   724 	RTL_FLAG_TASK_RESET_PENDING,
       
   725 	RTL_FLAG_TASK_PHY_PENDING,
       
   726 	RTL_FLAG_MAX
       
   727 };
       
   728 
       
   729 struct rtl8169_stats {
       
   730 	u64			packets;
       
   731 	u64			bytes;
       
   732 	struct u64_stats_sync	syncp;
       
   733 };
       
   734 
       
   735 struct rtl8169_private {
       
   736 	void __iomem *mmio_addr;	/* memory map physical address */
       
   737 	struct pci_dev *pci_dev;
       
   738 	struct net_device *dev;
       
   739 	struct napi_struct napi;
       
   740 	u32 msg_enable;
       
   741 	u16 txd_version;
       
   742 	u16 mac_version;
       
   743 	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
       
   744 	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
       
   745 	u32 dirty_tx;
       
   746 	struct rtl8169_stats rx_stats;
       
   747 	struct rtl8169_stats tx_stats;
       
   748 	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
       
   749 	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
       
   750 	dma_addr_t TxPhyAddr;
       
   751 	dma_addr_t RxPhyAddr;
       
   752 	void *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
       
   753 	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
       
   754 	struct timer_list timer;
       
   755 	u16 cp_cmd;
       
   756 
       
   757 	u16 event_slow;
       
   758 
       
   759 	struct mdio_ops {
       
   760 		void (*write)(struct rtl8169_private *, int, int);
       
   761 		int (*read)(struct rtl8169_private *, int);
       
   762 	} mdio_ops;
       
   763 
       
   764 	struct pll_power_ops {
       
   765 		void (*down)(struct rtl8169_private *);
       
   766 		void (*up)(struct rtl8169_private *);
       
   767 	} pll_power_ops;
       
   768 
       
   769 	struct jumbo_ops {
       
   770 		void (*enable)(struct rtl8169_private *);
       
   771 		void (*disable)(struct rtl8169_private *);
       
   772 	} jumbo_ops;
       
   773 
       
   774 	struct csi_ops {
       
   775 		void (*write)(struct rtl8169_private *, int, int);
       
   776 		u32 (*read)(struct rtl8169_private *, int);
       
   777 	} csi_ops;
       
   778 
       
   779 	int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
       
   780 	int (*get_settings)(struct net_device *, struct ethtool_cmd *);
       
   781 	void (*phy_reset_enable)(struct rtl8169_private *tp);
       
   782 	void (*hw_start)(struct net_device *);
       
   783 	unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
       
   784 	unsigned int (*link_ok)(void __iomem *);
       
   785 	int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
       
   786 
       
   787 	struct {
       
   788 		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
       
   789 		struct mutex mutex;
       
   790 		struct work_struct work;
       
   791 	} wk;
       
   792 
       
   793 	unsigned features;
       
   794 
       
   795 	struct mii_if_info mii;
       
   796 	struct rtl8169_counters counters;
       
   797 	u32 saved_wolopts;
       
   798 	u32 opts1_mask;
       
   799 
       
   800 	struct rtl_fw {
       
   801 		const struct firmware *fw;
       
   802 
       
   803 #define RTL_VER_SIZE		32
       
   804 
       
   805 		char version[RTL_VER_SIZE];
       
   806 
       
   807 		struct rtl_fw_phy_action {
       
   808 			__le32 *code;
       
   809 			size_t size;
       
   810 		} phy_action;
       
   811 	} *rtl_fw;
       
   812 #define RTL_FIRMWARE_UNKNOWN	ERR_PTR(-EAGAIN)
       
   813 
       
   814 	u32 ocp_base;
       
   815 };
       
   816 
       
   817 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
       
   818 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
       
   819 module_param(use_dac, int, 0);
       
   820 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
       
   821 module_param_named(debug, debug.msg_enable, int, 0);
       
   822 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
       
   823 MODULE_LICENSE("GPL");
       
   824 MODULE_VERSION(RTL8169_VERSION);
       
   825 MODULE_FIRMWARE(FIRMWARE_8168D_1);
       
   826 MODULE_FIRMWARE(FIRMWARE_8168D_2);
       
   827 MODULE_FIRMWARE(FIRMWARE_8168E_1);
       
   828 MODULE_FIRMWARE(FIRMWARE_8168E_2);
       
   829 MODULE_FIRMWARE(FIRMWARE_8168E_3);
       
   830 MODULE_FIRMWARE(FIRMWARE_8105E_1);
       
   831 MODULE_FIRMWARE(FIRMWARE_8168F_1);
       
   832 MODULE_FIRMWARE(FIRMWARE_8168F_2);
       
   833 MODULE_FIRMWARE(FIRMWARE_8402_1);
       
   834 MODULE_FIRMWARE(FIRMWARE_8411_1);
       
   835 MODULE_FIRMWARE(FIRMWARE_8411_2);
       
   836 MODULE_FIRMWARE(FIRMWARE_8106E_1);
       
   837 MODULE_FIRMWARE(FIRMWARE_8106E_2);
       
   838 MODULE_FIRMWARE(FIRMWARE_8168G_2);
       
   839 MODULE_FIRMWARE(FIRMWARE_8168G_3);
       
   840 
       
   841 static void rtl_lock_work(struct rtl8169_private *tp)
       
   842 {
       
   843 	mutex_lock(&tp->wk.mutex);
       
   844 }
       
   845 
       
   846 static void rtl_unlock_work(struct rtl8169_private *tp)
       
   847 {
       
   848 	mutex_unlock(&tp->wk.mutex);
       
   849 }
       
   850 
       
   851 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
       
   852 {
       
   853 	pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
       
   854 					   PCI_EXP_DEVCTL_READRQ, force);
       
   855 }
       
   856 
       
   857 struct rtl_cond {
       
   858 	bool (*check)(struct rtl8169_private *);
       
   859 	const char *msg;
       
   860 };
       
   861 
       
   862 static void rtl_udelay(unsigned int d)
       
   863 {
       
   864 	udelay(d);
       
   865 }
       
   866 
       
   867 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
       
   868 			  void (*delay)(unsigned int), unsigned int d, int n,
       
   869 			  bool high)
       
   870 {
       
   871 	int i;
       
   872 
       
   873 	for (i = 0; i < n; i++) {
       
   874 		delay(d);
       
   875 		if (c->check(tp) == high)
       
   876 			return true;
       
   877 	}
       
   878 	netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
       
   879 		  c->msg, !high, n, d);
       
   880 	return false;
       
   881 }
       
   882 
       
   883 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
       
   884 				      const struct rtl_cond *c,
       
   885 				      unsigned int d, int n)
       
   886 {
       
   887 	return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
       
   888 }
       
   889 
       
   890 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
       
   891 				     const struct rtl_cond *c,
       
   892 				     unsigned int d, int n)
       
   893 {
       
   894 	return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
       
   895 }
       
   896 
       
   897 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
       
   898 				      const struct rtl_cond *c,
       
   899 				      unsigned int d, int n)
       
   900 {
       
   901 	return rtl_loop_wait(tp, c, msleep, d, n, true);
       
   902 }
       
   903 
       
   904 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
       
   905 				     const struct rtl_cond *c,
       
   906 				     unsigned int d, int n)
       
   907 {
       
   908 	return rtl_loop_wait(tp, c, msleep, d, n, false);
       
   909 }
       
   910 
       
   911 #define DECLARE_RTL_COND(name)				\
       
   912 static bool name ## _check(struct rtl8169_private *);	\
       
   913 							\
       
   914 static const struct rtl_cond name = {			\
       
   915 	.check	= name ## _check,			\
       
   916 	.msg	= #name					\
       
   917 };							\
       
   918 							\
       
   919 static bool name ## _check(struct rtl8169_private *tp)
       
   920 
       
   921 DECLARE_RTL_COND(rtl_ocpar_cond)
       
   922 {
       
   923 	void __iomem *ioaddr = tp->mmio_addr;
       
   924 
       
   925 	return RTL_R32(OCPAR) & OCPAR_FLAG;
       
   926 }
       
   927 
       
   928 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
       
   929 {
       
   930 	void __iomem *ioaddr = tp->mmio_addr;
       
   931 
       
   932 	RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
       
   933 
       
   934 	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
       
   935 		RTL_R32(OCPDR) : ~0;
       
   936 }
       
   937 
       
   938 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
       
   939 {
       
   940 	void __iomem *ioaddr = tp->mmio_addr;
       
   941 
       
   942 	RTL_W32(OCPDR, data);
       
   943 	RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
       
   944 
       
   945 	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
       
   946 }
       
   947 
       
   948 DECLARE_RTL_COND(rtl_eriar_cond)
       
   949 {
       
   950 	void __iomem *ioaddr = tp->mmio_addr;
       
   951 
       
   952 	return RTL_R32(ERIAR) & ERIAR_FLAG;
       
   953 }
       
   954 
       
   955 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
       
   956 {
       
   957 	void __iomem *ioaddr = tp->mmio_addr;
       
   958 
       
   959 	RTL_W8(ERIDR, cmd);
       
   960 	RTL_W32(ERIAR, 0x800010e8);
       
   961 	msleep(2);
       
   962 
       
   963 	if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
       
   964 		return;
       
   965 
       
   966 	ocp_write(tp, 0x1, 0x30, 0x00000001);
       
   967 }
       
   968 
       
   969 #define OOB_CMD_RESET		0x00
       
   970 #define OOB_CMD_DRIVER_START	0x05
       
   971 #define OOB_CMD_DRIVER_STOP	0x06
       
   972 
       
   973 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
       
   974 {
       
   975 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
       
   976 }
       
   977 
       
   978 DECLARE_RTL_COND(rtl_ocp_read_cond)
       
   979 {
       
   980 	u16 reg;
       
   981 
       
   982 	reg = rtl8168_get_ocp_reg(tp);
       
   983 
       
   984 	return ocp_read(tp, 0x0f, reg) & 0x00000800;
       
   985 }
       
   986 
       
   987 static void rtl8168_driver_start(struct rtl8169_private *tp)
       
   988 {
       
   989 	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
       
   990 
       
   991 	rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
       
   992 }
       
   993 
       
   994 static void rtl8168_driver_stop(struct rtl8169_private *tp)
       
   995 {
       
   996 	rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
       
   997 
       
   998 	rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
       
   999 }
       
  1000 
       
  1001 static int r8168dp_check_dash(struct rtl8169_private *tp)
       
  1002 {
       
  1003 	u16 reg = rtl8168_get_ocp_reg(tp);
       
  1004 
       
  1005 	return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
       
  1006 }
       
  1007 
       
  1008 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
       
  1009 {
       
  1010 	if (reg & 0xffff0001) {
       
  1011 		netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
       
  1012 		return true;
       
  1013 	}
       
  1014 	return false;
       
  1015 }
       
  1016 
       
  1017 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
       
  1018 {
       
  1019 	void __iomem *ioaddr = tp->mmio_addr;
       
  1020 
       
  1021 	return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
       
  1022 }
       
  1023 
       
  1024 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
       
  1025 {
       
  1026 	void __iomem *ioaddr = tp->mmio_addr;
       
  1027 
       
  1028 	if (rtl_ocp_reg_failure(tp, reg))
       
  1029 		return;
       
  1030 
       
  1031 	RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
       
  1032 
       
  1033 	rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
       
  1034 }
       
  1035 
       
  1036 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
       
  1037 {
       
  1038 	void __iomem *ioaddr = tp->mmio_addr;
       
  1039 
       
  1040 	if (rtl_ocp_reg_failure(tp, reg))
       
  1041 		return 0;
       
  1042 
       
  1043 	RTL_W32(GPHY_OCP, reg << 15);
       
  1044 
       
  1045 	return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
       
  1046 		(RTL_R32(GPHY_OCP) & 0xffff) : ~0;
       
  1047 }
       
  1048 
       
  1049 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
       
  1050 {
       
  1051 	void __iomem *ioaddr = tp->mmio_addr;
       
  1052 
       
  1053 	if (rtl_ocp_reg_failure(tp, reg))
       
  1054 		return;
       
  1055 
       
  1056 	RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
       
  1057 }
       
  1058 
       
  1059 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
       
  1060 {
       
  1061 	void __iomem *ioaddr = tp->mmio_addr;
       
  1062 
       
  1063 	if (rtl_ocp_reg_failure(tp, reg))
       
  1064 		return 0;
       
  1065 
       
  1066 	RTL_W32(OCPDR, reg << 15);
       
  1067 
       
  1068 	return RTL_R32(OCPDR);
       
  1069 }
       
  1070 
       
  1071 #define OCP_STD_PHY_BASE	0xa400
       
  1072 
       
  1073 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
       
  1074 {
       
  1075 	if (reg == 0x1f) {
       
  1076 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
       
  1077 		return;
       
  1078 	}
       
  1079 
       
  1080 	if (tp->ocp_base != OCP_STD_PHY_BASE)
       
  1081 		reg -= 0x10;
       
  1082 
       
  1083 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
       
  1084 }
       
  1085 
       
  1086 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
       
  1087 {
       
  1088 	if (tp->ocp_base != OCP_STD_PHY_BASE)
       
  1089 		reg -= 0x10;
       
  1090 
       
  1091 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
       
  1092 }
       
  1093 
       
  1094 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
       
  1095 {
       
  1096 	if (reg == 0x1f) {
       
  1097 		tp->ocp_base = value << 4;
       
  1098 		return;
       
  1099 	}
       
  1100 
       
  1101 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
       
  1102 }
       
  1103 
       
  1104 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
       
  1105 {
       
  1106 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
       
  1107 }
       
  1108 
       
  1109 DECLARE_RTL_COND(rtl_phyar_cond)
       
  1110 {
       
  1111 	void __iomem *ioaddr = tp->mmio_addr;
       
  1112 
       
  1113 	return RTL_R32(PHYAR) & 0x80000000;
       
  1114 }
       
  1115 
       
  1116 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
       
  1117 {
       
  1118 	void __iomem *ioaddr = tp->mmio_addr;
       
  1119 
       
  1120 	RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
       
  1121 
       
  1122 	rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
       
  1123 	/*
       
  1124 	 * According to hardware specs a 20us delay is required after write
       
  1125 	 * complete indication, but before sending next command.
       
  1126 	 */
       
  1127 	udelay(20);
       
  1128 }
       
  1129 
       
  1130 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
       
  1131 {
       
  1132 	void __iomem *ioaddr = tp->mmio_addr;
       
  1133 	int value;
       
  1134 
       
  1135 	RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
       
  1136 
       
  1137 	value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
       
  1138 		RTL_R32(PHYAR) & 0xffff : ~0;
       
  1139 
       
  1140 	/*
       
  1141 	 * According to hardware specs a 20us delay is required after read
       
  1142 	 * complete indication, but before sending next command.
       
  1143 	 */
       
  1144 	udelay(20);
       
  1145 
       
  1146 	return value;
       
  1147 }
       
  1148 
       
  1149 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
       
  1150 {
       
  1151 	void __iomem *ioaddr = tp->mmio_addr;
       
  1152 
       
  1153 	RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
       
  1154 	RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
       
  1155 	RTL_W32(EPHY_RXER_NUM, 0);
       
  1156 
       
  1157 	rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
       
  1158 }
       
  1159 
       
  1160 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
       
  1161 {
       
  1162 	r8168dp_1_mdio_access(tp, reg,
       
  1163 			      OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
       
  1164 }
       
  1165 
       
  1166 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
       
  1167 {
       
  1168 	void __iomem *ioaddr = tp->mmio_addr;
       
  1169 
       
  1170 	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
       
  1171 
       
  1172 	mdelay(1);
       
  1173 	RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
       
  1174 	RTL_W32(EPHY_RXER_NUM, 0);
       
  1175 
       
  1176 	return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
       
  1177 		RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
       
  1178 }
       
  1179 
       
  1180 #define R8168DP_1_MDIO_ACCESS_BIT	0x00020000
       
  1181 
       
  1182 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
       
  1183 {
       
  1184 	RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
       
  1185 }
       
  1186 
       
  1187 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
       
  1188 {
       
  1189 	RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
       
  1190 }
       
  1191 
       
  1192 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
       
  1193 {
       
  1194 	void __iomem *ioaddr = tp->mmio_addr;
       
  1195 
       
  1196 	r8168dp_2_mdio_start(ioaddr);
       
  1197 
       
  1198 	r8169_mdio_write(tp, reg, value);
       
  1199 
       
  1200 	r8168dp_2_mdio_stop(ioaddr);
       
  1201 }
       
  1202 
       
  1203 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
       
  1204 {
       
  1205 	void __iomem *ioaddr = tp->mmio_addr;
       
  1206 	int value;
       
  1207 
       
  1208 	r8168dp_2_mdio_start(ioaddr);
       
  1209 
       
  1210 	value = r8169_mdio_read(tp, reg);
       
  1211 
       
  1212 	r8168dp_2_mdio_stop(ioaddr);
       
  1213 
       
  1214 	return value;
       
  1215 }
       
  1216 
       
  1217 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
       
  1218 {
       
  1219 	tp->mdio_ops.write(tp, location, val);
       
  1220 }
       
  1221 
       
  1222 static int rtl_readphy(struct rtl8169_private *tp, int location)
       
  1223 {
       
  1224 	return tp->mdio_ops.read(tp, location);
       
  1225 }
       
  1226 
       
  1227 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
       
  1228 {
       
  1229 	rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
       
  1230 }
       
  1231 
       
  1232 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
       
  1233 {
       
  1234 	int val;
       
  1235 
       
  1236 	val = rtl_readphy(tp, reg_addr);
       
  1237 	rtl_writephy(tp, reg_addr, (val | p) & ~m);
       
  1238 }
       
  1239 
       
  1240 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
       
  1241 			   int val)
       
  1242 {
       
  1243 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1244 
       
  1245 	rtl_writephy(tp, location, val);
       
  1246 }
       
  1247 
       
  1248 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
       
  1249 {
       
  1250 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1251 
       
  1252 	return rtl_readphy(tp, location);
       
  1253 }
       
  1254 
       
  1255 DECLARE_RTL_COND(rtl_ephyar_cond)
       
  1256 {
       
  1257 	void __iomem *ioaddr = tp->mmio_addr;
       
  1258 
       
  1259 	return RTL_R32(EPHYAR) & EPHYAR_FLAG;
       
  1260 }
       
  1261 
       
  1262 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
       
  1263 {
       
  1264 	void __iomem *ioaddr = tp->mmio_addr;
       
  1265 
       
  1266 	RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
       
  1267 		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
       
  1268 
       
  1269 	rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
       
  1270 
       
  1271 	udelay(10);
       
  1272 }
       
  1273 
       
  1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
       
  1275 {
       
  1276 	void __iomem *ioaddr = tp->mmio_addr;
       
  1277 
       
  1278 	RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
       
  1279 
       
  1280 	return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
       
  1281 		RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
       
  1282 }
       
  1283 
       
  1284 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
       
  1285 			  u32 val, int type)
       
  1286 {
       
  1287 	void __iomem *ioaddr = tp->mmio_addr;
       
  1288 
       
  1289 	BUG_ON((addr & 3) || (mask == 0));
       
  1290 	RTL_W32(ERIDR, val);
       
  1291 	RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
       
  1292 
       
  1293 	rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
       
  1294 }
       
  1295 
       
  1296 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
       
  1297 {
       
  1298 	void __iomem *ioaddr = tp->mmio_addr;
       
  1299 
       
  1300 	RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
       
  1301 
       
  1302 	return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
       
  1303 		RTL_R32(ERIDR) : ~0;
       
  1304 }
       
  1305 
       
  1306 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
       
  1307 			 u32 m, int type)
       
  1308 {
       
  1309 	u32 val;
       
  1310 
       
  1311 	val = rtl_eri_read(tp, addr, type);
       
  1312 	rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
       
  1313 }
       
  1314 
       
  1315 struct exgmac_reg {
       
  1316 	u16 addr;
       
  1317 	u16 mask;
       
  1318 	u32 val;
       
  1319 };
       
  1320 
       
  1321 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
       
  1322 				   const struct exgmac_reg *r, int len)
       
  1323 {
       
  1324 	while (len-- > 0) {
       
  1325 		rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
       
  1326 		r++;
       
  1327 	}
       
  1328 }
       
  1329 
       
  1330 DECLARE_RTL_COND(rtl_efusear_cond)
       
  1331 {
       
  1332 	void __iomem *ioaddr = tp->mmio_addr;
       
  1333 
       
  1334 	return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
       
  1335 }
       
  1336 
       
  1337 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
       
  1338 {
       
  1339 	void __iomem *ioaddr = tp->mmio_addr;
       
  1340 
       
  1341 	RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
       
  1342 
       
  1343 	return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
       
  1344 		RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
       
  1345 }
       
  1346 
       
  1347 static u16 rtl_get_events(struct rtl8169_private *tp)
       
  1348 {
       
  1349 	void __iomem *ioaddr = tp->mmio_addr;
       
  1350 
       
  1351 	return RTL_R16(IntrStatus);
       
  1352 }
       
  1353 
       
  1354 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
       
  1355 {
       
  1356 	void __iomem *ioaddr = tp->mmio_addr;
       
  1357 
       
  1358 	RTL_W16(IntrStatus, bits);
       
  1359 	mmiowb();
       
  1360 }
       
  1361 
       
  1362 static void rtl_irq_disable(struct rtl8169_private *tp)
       
  1363 {
       
  1364 	void __iomem *ioaddr = tp->mmio_addr;
       
  1365 
       
  1366 	RTL_W16(IntrMask, 0);
       
  1367 	mmiowb();
       
  1368 }
       
  1369 
       
  1370 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
       
  1371 {
       
  1372 	void __iomem *ioaddr = tp->mmio_addr;
       
  1373 
       
  1374 	RTL_W16(IntrMask, bits);
       
  1375 }
       
  1376 
       
  1377 #define RTL_EVENT_NAPI_RX	(RxOK | RxErr)
       
  1378 #define RTL_EVENT_NAPI_TX	(TxOK | TxErr)
       
  1379 #define RTL_EVENT_NAPI		(RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
       
  1380 
       
  1381 static void rtl_irq_enable_all(struct rtl8169_private *tp)
       
  1382 {
       
  1383 	rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
       
  1384 }
       
  1385 
       
  1386 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
       
  1387 {
       
  1388 	void __iomem *ioaddr = tp->mmio_addr;
       
  1389 
       
  1390 	rtl_irq_disable(tp);
       
  1391 	rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
       
  1392 	RTL_R8(ChipCmd);
       
  1393 }
       
  1394 
       
  1395 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
       
  1396 {
       
  1397 	void __iomem *ioaddr = tp->mmio_addr;
       
  1398 
       
  1399 	return RTL_R32(TBICSR) & TBIReset;
       
  1400 }
       
  1401 
       
  1402 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
       
  1403 {
       
  1404 	return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
       
  1405 }
       
  1406 
       
  1407 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
       
  1408 {
       
  1409 	return RTL_R32(TBICSR) & TBILinkOk;
       
  1410 }
       
  1411 
       
  1412 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
       
  1413 {
       
  1414 	return RTL_R8(PHYstatus) & LinkStatus;
       
  1415 }
       
  1416 
       
  1417 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
       
  1418 {
       
  1419 	void __iomem *ioaddr = tp->mmio_addr;
       
  1420 
       
  1421 	RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
       
  1422 }
       
  1423 
       
  1424 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
       
  1425 {
       
  1426 	unsigned int val;
       
  1427 
       
  1428 	val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
       
  1429 	rtl_writephy(tp, MII_BMCR, val & 0xffff);
       
  1430 }
       
  1431 
       
  1432 static void rtl_link_chg_patch(struct rtl8169_private *tp)
       
  1433 {
       
  1434 	void __iomem *ioaddr = tp->mmio_addr;
       
  1435 	struct net_device *dev = tp->dev;
       
  1436 
       
  1437 	if (!netif_running(dev))
       
  1438 		return;
       
  1439 
       
  1440 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
       
  1441 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
       
  1442 		if (RTL_R8(PHYstatus) & _1000bpsF) {
       
  1443 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
       
  1444 				      ERIAR_EXGMAC);
       
  1445 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
       
  1446 				      ERIAR_EXGMAC);
       
  1447 		} else if (RTL_R8(PHYstatus) & _100bps) {
       
  1448 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
       
  1449 				      ERIAR_EXGMAC);
       
  1450 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
       
  1451 				      ERIAR_EXGMAC);
       
  1452 		} else {
       
  1453 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
       
  1454 				      ERIAR_EXGMAC);
       
  1455 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
       
  1456 				      ERIAR_EXGMAC);
       
  1457 		}
       
  1458 		/* Reset packet filter */
       
  1459 		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
       
  1460 			     ERIAR_EXGMAC);
       
  1461 		rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
       
  1462 			     ERIAR_EXGMAC);
       
  1463 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
       
  1464 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
       
  1465 		if (RTL_R8(PHYstatus) & _1000bpsF) {
       
  1466 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
       
  1467 				      ERIAR_EXGMAC);
       
  1468 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
       
  1469 				      ERIAR_EXGMAC);
       
  1470 		} else {
       
  1471 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
       
  1472 				      ERIAR_EXGMAC);
       
  1473 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
       
  1474 				      ERIAR_EXGMAC);
       
  1475 		}
       
  1476 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
       
  1477 		if (RTL_R8(PHYstatus) & _10bps) {
       
  1478 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
       
  1479 				      ERIAR_EXGMAC);
       
  1480 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
       
  1481 				      ERIAR_EXGMAC);
       
  1482 		} else {
       
  1483 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
       
  1484 				      ERIAR_EXGMAC);
       
  1485 		}
       
  1486 	}
       
  1487 }
       
  1488 
       
  1489 static void __rtl8169_check_link_status(struct net_device *dev,
       
  1490 					struct rtl8169_private *tp,
       
  1491 					void __iomem *ioaddr, bool pm)
       
  1492 {
       
  1493 	if (tp->link_ok(ioaddr)) {
       
  1494 		rtl_link_chg_patch(tp);
       
  1495 		/* This is to cancel a scheduled suspend if there's one. */
       
  1496 		if (pm)
       
  1497 			pm_request_resume(&tp->pci_dev->dev);
       
  1498 		netif_carrier_on(dev);
       
  1499 		if (net_ratelimit())
       
  1500 			netif_info(tp, ifup, dev, "link up\n");
       
  1501 	} else {
       
  1502 		netif_carrier_off(dev);
       
  1503 		netif_info(tp, ifdown, dev, "link down\n");
       
  1504 		if (pm)
       
  1505 			pm_schedule_suspend(&tp->pci_dev->dev, 5000);
       
  1506 	}
       
  1507 }
       
  1508 
       
  1509 static void rtl8169_check_link_status(struct net_device *dev,
       
  1510 				      struct rtl8169_private *tp,
       
  1511 				      void __iomem *ioaddr)
       
  1512 {
       
  1513 	__rtl8169_check_link_status(dev, tp, ioaddr, false);
       
  1514 }
       
  1515 
       
  1516 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
       
  1517 
       
  1518 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
       
  1519 {
       
  1520 	void __iomem *ioaddr = tp->mmio_addr;
       
  1521 	u8 options;
       
  1522 	u32 wolopts = 0;
       
  1523 
       
  1524 	options = RTL_R8(Config1);
       
  1525 	if (!(options & PMEnable))
       
  1526 		return 0;
       
  1527 
       
  1528 	options = RTL_R8(Config3);
       
  1529 	if (options & LinkUp)
       
  1530 		wolopts |= WAKE_PHY;
       
  1531 	if (options & MagicPacket)
       
  1532 		wolopts |= WAKE_MAGIC;
       
  1533 
       
  1534 	options = RTL_R8(Config5);
       
  1535 	if (options & UWF)
       
  1536 		wolopts |= WAKE_UCAST;
       
  1537 	if (options & BWF)
       
  1538 		wolopts |= WAKE_BCAST;
       
  1539 	if (options & MWF)
       
  1540 		wolopts |= WAKE_MCAST;
       
  1541 
       
  1542 	return wolopts;
       
  1543 }
       
  1544 
       
  1545 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  1546 {
       
  1547 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1548 
       
  1549 	rtl_lock_work(tp);
       
  1550 
       
  1551 	wol->supported = WAKE_ANY;
       
  1552 	wol->wolopts = __rtl8169_get_wol(tp);
       
  1553 
       
  1554 	rtl_unlock_work(tp);
       
  1555 }
       
  1556 
       
  1557 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
       
  1558 {
       
  1559 	void __iomem *ioaddr = tp->mmio_addr;
       
  1560 	unsigned int i;
       
  1561 	static const struct {
       
  1562 		u32 opt;
       
  1563 		u16 reg;
       
  1564 		u8  mask;
       
  1565 	} cfg[] = {
       
  1566 		{ WAKE_PHY,   Config3, LinkUp },
       
  1567 		{ WAKE_MAGIC, Config3, MagicPacket },
       
  1568 		{ WAKE_UCAST, Config5, UWF },
       
  1569 		{ WAKE_BCAST, Config5, BWF },
       
  1570 		{ WAKE_MCAST, Config5, MWF },
       
  1571 		{ WAKE_ANY,   Config5, LanWake }
       
  1572 	};
       
  1573 	u8 options;
       
  1574 
       
  1575 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  1576 
       
  1577 	for (i = 0; i < ARRAY_SIZE(cfg); i++) {
       
  1578 		options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
       
  1579 		if (wolopts & cfg[i].opt)
       
  1580 			options |= cfg[i].mask;
       
  1581 		RTL_W8(cfg[i].reg, options);
       
  1582 	}
       
  1583 
       
  1584 	switch (tp->mac_version) {
       
  1585 	case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
       
  1586 		options = RTL_R8(Config1) & ~PMEnable;
       
  1587 		if (wolopts)
       
  1588 			options |= PMEnable;
       
  1589 		RTL_W8(Config1, options);
       
  1590 		break;
       
  1591 	default:
       
  1592 		options = RTL_R8(Config2) & ~PME_SIGNAL;
       
  1593 		if (wolopts)
       
  1594 			options |= PME_SIGNAL;
       
  1595 		RTL_W8(Config2, options);
       
  1596 		break;
       
  1597 	}
       
  1598 
       
  1599 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  1600 }
       
  1601 
       
  1602 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  1603 {
       
  1604 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1605 
       
  1606 	rtl_lock_work(tp);
       
  1607 
       
  1608 	if (wol->wolopts)
       
  1609 		tp->features |= RTL_FEATURE_WOL;
       
  1610 	else
       
  1611 		tp->features &= ~RTL_FEATURE_WOL;
       
  1612 	__rtl8169_set_wol(tp, wol->wolopts);
       
  1613 
       
  1614 	rtl_unlock_work(tp);
       
  1615 
       
  1616 	device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
       
  1617 
       
  1618 	return 0;
       
  1619 }
       
  1620 
       
  1621 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
       
  1622 {
       
  1623 	return rtl_chip_infos[tp->mac_version].fw_name;
       
  1624 }
       
  1625 
       
  1626 static void rtl8169_get_drvinfo(struct net_device *dev,
       
  1627 				struct ethtool_drvinfo *info)
       
  1628 {
       
  1629 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1630 	struct rtl_fw *rtl_fw = tp->rtl_fw;
       
  1631 
       
  1632 	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
       
  1633 	strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
       
  1634 	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
       
  1635 	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
       
  1636 	if (!IS_ERR_OR_NULL(rtl_fw))
       
  1637 		strlcpy(info->fw_version, rtl_fw->version,
       
  1638 			sizeof(info->fw_version));
       
  1639 }
       
  1640 
       
  1641 static int rtl8169_get_regs_len(struct net_device *dev)
       
  1642 {
       
  1643 	return R8169_REGS_SIZE;
       
  1644 }
       
  1645 
       
  1646 static int rtl8169_set_speed_tbi(struct net_device *dev,
       
  1647 				 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
       
  1648 {
       
  1649 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1650 	void __iomem *ioaddr = tp->mmio_addr;
       
  1651 	int ret = 0;
       
  1652 	u32 reg;
       
  1653 
       
  1654 	reg = RTL_R32(TBICSR);
       
  1655 	if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
       
  1656 	    (duplex == DUPLEX_FULL)) {
       
  1657 		RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
       
  1658 	} else if (autoneg == AUTONEG_ENABLE)
       
  1659 		RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
       
  1660 	else {
       
  1661 		netif_warn(tp, link, dev,
       
  1662 			   "incorrect speed setting refused in TBI mode\n");
       
  1663 		ret = -EOPNOTSUPP;
       
  1664 	}
       
  1665 
       
  1666 	return ret;
       
  1667 }
       
  1668 
       
  1669 static int rtl8169_set_speed_xmii(struct net_device *dev,
       
  1670 				  u8 autoneg, u16 speed, u8 duplex, u32 adv)
       
  1671 {
       
  1672 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1673 	int giga_ctrl, bmcr;
       
  1674 	int rc = -EINVAL;
       
  1675 
       
  1676 	rtl_writephy(tp, 0x1f, 0x0000);
       
  1677 
       
  1678 	if (autoneg == AUTONEG_ENABLE) {
       
  1679 		int auto_nego;
       
  1680 
       
  1681 		auto_nego = rtl_readphy(tp, MII_ADVERTISE);
       
  1682 		auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
       
  1683 				ADVERTISE_100HALF | ADVERTISE_100FULL);
       
  1684 
       
  1685 		if (adv & ADVERTISED_10baseT_Half)
       
  1686 			auto_nego |= ADVERTISE_10HALF;
       
  1687 		if (adv & ADVERTISED_10baseT_Full)
       
  1688 			auto_nego |= ADVERTISE_10FULL;
       
  1689 		if (adv & ADVERTISED_100baseT_Half)
       
  1690 			auto_nego |= ADVERTISE_100HALF;
       
  1691 		if (adv & ADVERTISED_100baseT_Full)
       
  1692 			auto_nego |= ADVERTISE_100FULL;
       
  1693 
       
  1694 		auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
       
  1695 
       
  1696 		giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
       
  1697 		giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
       
  1698 
       
  1699 		/* The 8100e/8101e/8102e do Fast Ethernet only. */
       
  1700 		if (tp->mii.supports_gmii) {
       
  1701 			if (adv & ADVERTISED_1000baseT_Half)
       
  1702 				giga_ctrl |= ADVERTISE_1000HALF;
       
  1703 			if (adv & ADVERTISED_1000baseT_Full)
       
  1704 				giga_ctrl |= ADVERTISE_1000FULL;
       
  1705 		} else if (adv & (ADVERTISED_1000baseT_Half |
       
  1706 				  ADVERTISED_1000baseT_Full)) {
       
  1707 			netif_info(tp, link, dev,
       
  1708 				   "PHY does not support 1000Mbps\n");
       
  1709 			goto out;
       
  1710 		}
       
  1711 
       
  1712 		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
       
  1713 
       
  1714 		rtl_writephy(tp, MII_ADVERTISE, auto_nego);
       
  1715 		rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
       
  1716 	} else {
       
  1717 		giga_ctrl = 0;
       
  1718 
       
  1719 		if (speed == SPEED_10)
       
  1720 			bmcr = 0;
       
  1721 		else if (speed == SPEED_100)
       
  1722 			bmcr = BMCR_SPEED100;
       
  1723 		else
       
  1724 			goto out;
       
  1725 
       
  1726 		if (duplex == DUPLEX_FULL)
       
  1727 			bmcr |= BMCR_FULLDPLX;
       
  1728 	}
       
  1729 
       
  1730 	rtl_writephy(tp, MII_BMCR, bmcr);
       
  1731 
       
  1732 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
       
  1733 	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
       
  1734 		if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
       
  1735 			rtl_writephy(tp, 0x17, 0x2138);
       
  1736 			rtl_writephy(tp, 0x0e, 0x0260);
       
  1737 		} else {
       
  1738 			rtl_writephy(tp, 0x17, 0x2108);
       
  1739 			rtl_writephy(tp, 0x0e, 0x0000);
       
  1740 		}
       
  1741 	}
       
  1742 
       
  1743 	rc = 0;
       
  1744 out:
       
  1745 	return rc;
       
  1746 }
       
  1747 
       
  1748 static int rtl8169_set_speed(struct net_device *dev,
       
  1749 			     u8 autoneg, u16 speed, u8 duplex, u32 advertising)
       
  1750 {
       
  1751 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1752 	int ret;
       
  1753 
       
  1754 	ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
       
  1755 	if (ret < 0)
       
  1756 		goto out;
       
  1757 
       
  1758 	if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
       
  1759 	    (advertising & ADVERTISED_1000baseT_Full)) {
       
  1760 		mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
       
  1761 	}
       
  1762 out:
       
  1763 	return ret;
       
  1764 }
       
  1765 
       
  1766 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1767 {
       
  1768 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1769 	int ret;
       
  1770 
       
  1771 	del_timer_sync(&tp->timer);
       
  1772 
       
  1773 	rtl_lock_work(tp);
       
  1774 	ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
       
  1775 				cmd->duplex, cmd->advertising);
       
  1776 	rtl_unlock_work(tp);
       
  1777 
       
  1778 	return ret;
       
  1779 }
       
  1780 
       
  1781 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
       
  1782 	netdev_features_t features)
       
  1783 {
       
  1784 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1785 
       
  1786 	if (dev->mtu > TD_MSS_MAX)
       
  1787 		features &= ~NETIF_F_ALL_TSO;
       
  1788 
       
  1789 	if (dev->mtu > JUMBO_1K &&
       
  1790 	    !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
       
  1791 		features &= ~NETIF_F_IP_CSUM;
       
  1792 
       
  1793 	return features;
       
  1794 }
       
  1795 
       
  1796 static void __rtl8169_set_features(struct net_device *dev,
       
  1797 				   netdev_features_t features)
       
  1798 {
       
  1799 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1800 	netdev_features_t changed = features ^ dev->features;
       
  1801 	void __iomem *ioaddr = tp->mmio_addr;
       
  1802 
       
  1803 	if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
       
  1804 			 NETIF_F_HW_VLAN_CTAG_RX)))
       
  1805 		return;
       
  1806 
       
  1807 	if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
       
  1808 		if (features & NETIF_F_RXCSUM)
       
  1809 			tp->cp_cmd |= RxChkSum;
       
  1810 		else
       
  1811 			tp->cp_cmd &= ~RxChkSum;
       
  1812 
       
  1813 		if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
       
  1814 			tp->cp_cmd |= RxVlan;
       
  1815 		else
       
  1816 			tp->cp_cmd &= ~RxVlan;
       
  1817 
       
  1818 		RTL_W16(CPlusCmd, tp->cp_cmd);
       
  1819 		RTL_R16(CPlusCmd);
       
  1820 	}
       
  1821 	if (changed & NETIF_F_RXALL) {
       
  1822 		int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
       
  1823 		if (features & NETIF_F_RXALL)
       
  1824 			tmp |= (AcceptErr | AcceptRunt);
       
  1825 		RTL_W32(RxConfig, tmp);
       
  1826 	}
       
  1827 }
       
  1828 
       
  1829 static int rtl8169_set_features(struct net_device *dev,
       
  1830 				netdev_features_t features)
       
  1831 {
       
  1832 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1833 
       
  1834 	rtl_lock_work(tp);
       
  1835 	__rtl8169_set_features(dev, features);
       
  1836 	rtl_unlock_work(tp);
       
  1837 
       
  1838 	return 0;
       
  1839 }
       
  1840 
       
  1841 
       
  1842 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
       
  1843 {
       
  1844 	return (vlan_tx_tag_present(skb)) ?
       
  1845 		TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
       
  1846 }
       
  1847 
       
  1848 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
       
  1849 {
       
  1850 	u32 opts2 = le32_to_cpu(desc->opts2);
       
  1851 
       
  1852 	if (opts2 & RxVlanTag)
       
  1853 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
       
  1854 }
       
  1855 
       
  1856 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1857 {
       
  1858 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1859 	void __iomem *ioaddr = tp->mmio_addr;
       
  1860 	u32 status;
       
  1861 
       
  1862 	cmd->supported =
       
  1863 		SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
       
  1864 	cmd->port = PORT_FIBRE;
       
  1865 	cmd->transceiver = XCVR_INTERNAL;
       
  1866 
       
  1867 	status = RTL_R32(TBICSR);
       
  1868 	cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
       
  1869 	cmd->autoneg = !!(status & TBINwEnable);
       
  1870 
       
  1871 	ethtool_cmd_speed_set(cmd, SPEED_1000);
       
  1872 	cmd->duplex = DUPLEX_FULL; /* Always set */
       
  1873 
       
  1874 	return 0;
       
  1875 }
       
  1876 
       
  1877 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1878 {
       
  1879 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1880 
       
  1881 	return mii_ethtool_gset(&tp->mii, cmd);
       
  1882 }
       
  1883 
       
  1884 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  1885 {
       
  1886 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1887 	int rc;
       
  1888 
       
  1889 	rtl_lock_work(tp);
       
  1890 	rc = tp->get_settings(dev, cmd);
       
  1891 	rtl_unlock_work(tp);
       
  1892 
       
  1893 	return rc;
       
  1894 }
       
  1895 
       
  1896 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
       
  1897 			     void *p)
       
  1898 {
       
  1899 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1900 	u32 __iomem *data = tp->mmio_addr;
       
  1901 	u32 *dw = p;
       
  1902 	int i;
       
  1903 
       
  1904 	rtl_lock_work(tp);
       
  1905 	for (i = 0; i < R8169_REGS_SIZE; i += 4)
       
  1906 		memcpy_fromio(dw++, data++, 4);
       
  1907 	rtl_unlock_work(tp);
       
  1908 }
       
  1909 
       
  1910 static u32 rtl8169_get_msglevel(struct net_device *dev)
       
  1911 {
       
  1912 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1913 
       
  1914 	return tp->msg_enable;
       
  1915 }
       
  1916 
       
  1917 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
       
  1918 {
       
  1919 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1920 
       
  1921 	tp->msg_enable = value;
       
  1922 }
       
  1923 
       
  1924 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
       
  1925 	"tx_packets",
       
  1926 	"rx_packets",
       
  1927 	"tx_errors",
       
  1928 	"rx_errors",
       
  1929 	"rx_missed",
       
  1930 	"align_errors",
       
  1931 	"tx_single_collisions",
       
  1932 	"tx_multi_collisions",
       
  1933 	"unicast",
       
  1934 	"broadcast",
       
  1935 	"multicast",
       
  1936 	"tx_aborted",
       
  1937 	"tx_underrun",
       
  1938 };
       
  1939 
       
  1940 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
       
  1941 {
       
  1942 	switch (sset) {
       
  1943 	case ETH_SS_STATS:
       
  1944 		return ARRAY_SIZE(rtl8169_gstrings);
       
  1945 	default:
       
  1946 		return -EOPNOTSUPP;
       
  1947 	}
       
  1948 }
       
  1949 
       
  1950 DECLARE_RTL_COND(rtl_counters_cond)
       
  1951 {
       
  1952 	void __iomem *ioaddr = tp->mmio_addr;
       
  1953 
       
  1954 	return RTL_R32(CounterAddrLow) & CounterDump;
       
  1955 }
       
  1956 
       
  1957 static void rtl8169_update_counters(struct net_device *dev)
       
  1958 {
       
  1959 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1960 	void __iomem *ioaddr = tp->mmio_addr;
       
  1961 	struct device *d = &tp->pci_dev->dev;
       
  1962 	struct rtl8169_counters *counters;
       
  1963 	dma_addr_t paddr;
       
  1964 	u32 cmd;
       
  1965 
       
  1966 	/*
       
  1967 	 * Some chips are unable to dump tally counters when the receiver
       
  1968 	 * is disabled.
       
  1969 	 */
       
  1970 	if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
       
  1971 		return;
       
  1972 
       
  1973 	counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
       
  1974 	if (!counters)
       
  1975 		return;
       
  1976 
       
  1977 	RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
       
  1978 	cmd = (u64)paddr & DMA_BIT_MASK(32);
       
  1979 	RTL_W32(CounterAddrLow, cmd);
       
  1980 	RTL_W32(CounterAddrLow, cmd | CounterDump);
       
  1981 
       
  1982 	if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
       
  1983 		memcpy(&tp->counters, counters, sizeof(*counters));
       
  1984 
       
  1985 	RTL_W32(CounterAddrLow, 0);
       
  1986 	RTL_W32(CounterAddrHigh, 0);
       
  1987 
       
  1988 	dma_free_coherent(d, sizeof(*counters), counters, paddr);
       
  1989 }
       
  1990 
       
  1991 static void rtl8169_get_ethtool_stats(struct net_device *dev,
       
  1992 				      struct ethtool_stats *stats, u64 *data)
       
  1993 {
       
  1994 	struct rtl8169_private *tp = netdev_priv(dev);
       
  1995 
       
  1996 	ASSERT_RTNL();
       
  1997 
       
  1998 	rtl8169_update_counters(dev);
       
  1999 
       
  2000 	data[0] = le64_to_cpu(tp->counters.tx_packets);
       
  2001 	data[1] = le64_to_cpu(tp->counters.rx_packets);
       
  2002 	data[2] = le64_to_cpu(tp->counters.tx_errors);
       
  2003 	data[3] = le32_to_cpu(tp->counters.rx_errors);
       
  2004 	data[4] = le16_to_cpu(tp->counters.rx_missed);
       
  2005 	data[5] = le16_to_cpu(tp->counters.align_errors);
       
  2006 	data[6] = le32_to_cpu(tp->counters.tx_one_collision);
       
  2007 	data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
       
  2008 	data[8] = le64_to_cpu(tp->counters.rx_unicast);
       
  2009 	data[9] = le64_to_cpu(tp->counters.rx_broadcast);
       
  2010 	data[10] = le32_to_cpu(tp->counters.rx_multicast);
       
  2011 	data[11] = le16_to_cpu(tp->counters.tx_aborted);
       
  2012 	data[12] = le16_to_cpu(tp->counters.tx_underun);
       
  2013 }
       
  2014 
       
  2015 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
       
  2016 {
       
  2017 	switch(stringset) {
       
  2018 	case ETH_SS_STATS:
       
  2019 		memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
       
  2020 		break;
       
  2021 	}
       
  2022 }
       
  2023 
       
  2024 static const struct ethtool_ops rtl8169_ethtool_ops = {
       
  2025 	.get_drvinfo		= rtl8169_get_drvinfo,
       
  2026 	.get_regs_len		= rtl8169_get_regs_len,
       
  2027 	.get_link		= ethtool_op_get_link,
       
  2028 	.get_settings		= rtl8169_get_settings,
       
  2029 	.set_settings		= rtl8169_set_settings,
       
  2030 	.get_msglevel		= rtl8169_get_msglevel,
       
  2031 	.set_msglevel		= rtl8169_set_msglevel,
       
  2032 	.get_regs		= rtl8169_get_regs,
       
  2033 	.get_wol		= rtl8169_get_wol,
       
  2034 	.set_wol		= rtl8169_set_wol,
       
  2035 	.get_strings		= rtl8169_get_strings,
       
  2036 	.get_sset_count		= rtl8169_get_sset_count,
       
  2037 	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
       
  2038 	.get_ts_info		= ethtool_op_get_ts_info,
       
  2039 };
       
  2040 
       
  2041 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
       
  2042 				    struct net_device *dev, u8 default_version)
       
  2043 {
       
  2044 	void __iomem *ioaddr = tp->mmio_addr;
       
  2045 	/*
       
  2046 	 * The driver currently handles the 8168Bf and the 8168Be identically
       
  2047 	 * but they can be identified more specifically through the test below
       
  2048 	 * if needed:
       
  2049 	 *
       
  2050 	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
       
  2051 	 *
       
  2052 	 * Same thing for the 8101Eb and the 8101Ec:
       
  2053 	 *
       
  2054 	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
       
  2055 	 */
       
  2056 	static const struct rtl_mac_info {
       
  2057 		u32 mask;
       
  2058 		u32 val;
       
  2059 		int mac_version;
       
  2060 	} mac_info[] = {
       
  2061 		/* 8168G family. */
       
  2062 		{ 0x7cf00000, 0x5c800000,	RTL_GIGA_MAC_VER_44 },
       
  2063 		{ 0x7cf00000, 0x50900000,	RTL_GIGA_MAC_VER_42 },
       
  2064 		{ 0x7cf00000, 0x4c100000,	RTL_GIGA_MAC_VER_41 },
       
  2065 		{ 0x7cf00000, 0x4c000000,	RTL_GIGA_MAC_VER_40 },
       
  2066 
       
  2067 		/* 8168F family. */
       
  2068 		{ 0x7c800000, 0x48800000,	RTL_GIGA_MAC_VER_38 },
       
  2069 		{ 0x7cf00000, 0x48100000,	RTL_GIGA_MAC_VER_36 },
       
  2070 		{ 0x7cf00000, 0x48000000,	RTL_GIGA_MAC_VER_35 },
       
  2071 
       
  2072 		/* 8168E family. */
       
  2073 		{ 0x7c800000, 0x2c800000,	RTL_GIGA_MAC_VER_34 },
       
  2074 		{ 0x7cf00000, 0x2c200000,	RTL_GIGA_MAC_VER_33 },
       
  2075 		{ 0x7cf00000, 0x2c100000,	RTL_GIGA_MAC_VER_32 },
       
  2076 		{ 0x7c800000, 0x2c000000,	RTL_GIGA_MAC_VER_33 },
       
  2077 
       
  2078 		/* 8168D family. */
       
  2079 		{ 0x7cf00000, 0x28300000,	RTL_GIGA_MAC_VER_26 },
       
  2080 		{ 0x7cf00000, 0x28100000,	RTL_GIGA_MAC_VER_25 },
       
  2081 		{ 0x7c800000, 0x28000000,	RTL_GIGA_MAC_VER_26 },
       
  2082 
       
  2083 		/* 8168DP family. */
       
  2084 		{ 0x7cf00000, 0x28800000,	RTL_GIGA_MAC_VER_27 },
       
  2085 		{ 0x7cf00000, 0x28a00000,	RTL_GIGA_MAC_VER_28 },
       
  2086 		{ 0x7cf00000, 0x28b00000,	RTL_GIGA_MAC_VER_31 },
       
  2087 
       
  2088 		/* 8168C family. */
       
  2089 		{ 0x7cf00000, 0x3cb00000,	RTL_GIGA_MAC_VER_24 },
       
  2090 		{ 0x7cf00000, 0x3c900000,	RTL_GIGA_MAC_VER_23 },
       
  2091 		{ 0x7cf00000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
       
  2092 		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_24 },
       
  2093 		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
       
  2094 		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
       
  2095 		{ 0x7cf00000, 0x3c300000,	RTL_GIGA_MAC_VER_21 },
       
  2096 		{ 0x7cf00000, 0x3c400000,	RTL_GIGA_MAC_VER_22 },
       
  2097 		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_22 },
       
  2098 
       
  2099 		/* 8168B family. */
       
  2100 		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
       
  2101 		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
       
  2102 		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
       
  2103 		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },
       
  2104 
       
  2105 		/* 8101 family. */
       
  2106 		{ 0x7cf00000, 0x44900000,	RTL_GIGA_MAC_VER_39 },
       
  2107 		{ 0x7c800000, 0x44800000,	RTL_GIGA_MAC_VER_39 },
       
  2108 		{ 0x7c800000, 0x44000000,	RTL_GIGA_MAC_VER_37 },
       
  2109 		{ 0x7cf00000, 0x40b00000,	RTL_GIGA_MAC_VER_30 },
       
  2110 		{ 0x7cf00000, 0x40a00000,	RTL_GIGA_MAC_VER_30 },
       
  2111 		{ 0x7cf00000, 0x40900000,	RTL_GIGA_MAC_VER_29 },
       
  2112 		{ 0x7c800000, 0x40800000,	RTL_GIGA_MAC_VER_30 },
       
  2113 		{ 0x7cf00000, 0x34a00000,	RTL_GIGA_MAC_VER_09 },
       
  2114 		{ 0x7cf00000, 0x24a00000,	RTL_GIGA_MAC_VER_09 },
       
  2115 		{ 0x7cf00000, 0x34900000,	RTL_GIGA_MAC_VER_08 },
       
  2116 		{ 0x7cf00000, 0x24900000,	RTL_GIGA_MAC_VER_08 },
       
  2117 		{ 0x7cf00000, 0x34800000,	RTL_GIGA_MAC_VER_07 },
       
  2118 		{ 0x7cf00000, 0x24800000,	RTL_GIGA_MAC_VER_07 },
       
  2119 		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
       
  2120 		{ 0x7cf00000, 0x34300000,	RTL_GIGA_MAC_VER_10 },
       
  2121 		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
       
  2122 		{ 0x7c800000, 0x34800000,	RTL_GIGA_MAC_VER_09 },
       
  2123 		{ 0x7c800000, 0x24800000,	RTL_GIGA_MAC_VER_09 },
       
  2124 		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
       
  2125 		/* FIXME: where did these entries come from ? -- FR */
       
  2126 		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
       
  2127 		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },
       
  2128 
       
  2129 		/* 8110 family. */
       
  2130 		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
       
  2131 		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
       
  2132 		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
       
  2133 		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
       
  2134 		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
       
  2135 		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },
       
  2136 
       
  2137 		/* Catch-all */
       
  2138 		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_NONE   }
       
  2139 	};
       
  2140 	const struct rtl_mac_info *p = mac_info;
       
  2141 	u32 reg;
       
  2142 
       
  2143 	reg = RTL_R32(TxConfig);
       
  2144 	while ((reg & p->mask) != p->val)
       
  2145 		p++;
       
  2146 	tp->mac_version = p->mac_version;
       
  2147 
       
  2148 	if (tp->mac_version == RTL_GIGA_MAC_NONE) {
       
  2149 		netif_notice(tp, probe, dev,
       
  2150 			     "unknown MAC, using family default\n");
       
  2151 		tp->mac_version = default_version;
       
  2152 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
       
  2153 		tp->mac_version = tp->mii.supports_gmii ?
       
  2154 				  RTL_GIGA_MAC_VER_42 :
       
  2155 				  RTL_GIGA_MAC_VER_43;
       
  2156 	}
       
  2157 }
       
  2158 
       
  2159 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
       
  2160 {
       
  2161 	dprintk("mac_version = 0x%02x\n", tp->mac_version);
       
  2162 }
       
  2163 
       
  2164 struct phy_reg {
       
  2165 	u16 reg;
       
  2166 	u16 val;
       
  2167 };
       
  2168 
       
  2169 static void rtl_writephy_batch(struct rtl8169_private *tp,
       
  2170 			       const struct phy_reg *regs, int len)
       
  2171 {
       
  2172 	while (len-- > 0) {
       
  2173 		rtl_writephy(tp, regs->reg, regs->val);
       
  2174 		regs++;
       
  2175 	}
       
  2176 }
       
  2177 
       
  2178 #define PHY_READ		0x00000000
       
  2179 #define PHY_DATA_OR		0x10000000
       
  2180 #define PHY_DATA_AND		0x20000000
       
  2181 #define PHY_BJMPN		0x30000000
       
  2182 #define PHY_MDIO_CHG		0x40000000
       
  2183 #define PHY_CLEAR_READCOUNT	0x70000000
       
  2184 #define PHY_WRITE		0x80000000
       
  2185 #define PHY_READCOUNT_EQ_SKIP	0x90000000
       
  2186 #define PHY_COMP_EQ_SKIPN	0xa0000000
       
  2187 #define PHY_COMP_NEQ_SKIPN	0xb0000000
       
  2188 #define PHY_WRITE_PREVIOUS	0xc0000000
       
  2189 #define PHY_SKIPN		0xd0000000
       
  2190 #define PHY_DELAY_MS		0xe0000000
       
  2191 
       
  2192 struct fw_info {
       
  2193 	u32	magic;
       
  2194 	char	version[RTL_VER_SIZE];
       
  2195 	__le32	fw_start;
       
  2196 	__le32	fw_len;
       
  2197 	u8	chksum;
       
  2198 } __packed;
       
  2199 
       
  2200 #define FW_OPCODE_SIZE	sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
       
  2201 
       
  2202 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
       
  2203 {
       
  2204 	const struct firmware *fw = rtl_fw->fw;
       
  2205 	struct fw_info *fw_info = (struct fw_info *)fw->data;
       
  2206 	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
       
  2207 	char *version = rtl_fw->version;
       
  2208 	bool rc = false;
       
  2209 
       
  2210 	if (fw->size < FW_OPCODE_SIZE)
       
  2211 		goto out;
       
  2212 
       
  2213 	if (!fw_info->magic) {
       
  2214 		size_t i, size, start;
       
  2215 		u8 checksum = 0;
       
  2216 
       
  2217 		if (fw->size < sizeof(*fw_info))
       
  2218 			goto out;
       
  2219 
       
  2220 		for (i = 0; i < fw->size; i++)
       
  2221 			checksum += fw->data[i];
       
  2222 		if (checksum != 0)
       
  2223 			goto out;
       
  2224 
       
  2225 		start = le32_to_cpu(fw_info->fw_start);
       
  2226 		if (start > fw->size)
       
  2227 			goto out;
       
  2228 
       
  2229 		size = le32_to_cpu(fw_info->fw_len);
       
  2230 		if (size > (fw->size - start) / FW_OPCODE_SIZE)
       
  2231 			goto out;
       
  2232 
       
  2233 		memcpy(version, fw_info->version, RTL_VER_SIZE);
       
  2234 
       
  2235 		pa->code = (__le32 *)(fw->data + start);
       
  2236 		pa->size = size;
       
  2237 	} else {
       
  2238 		if (fw->size % FW_OPCODE_SIZE)
       
  2239 			goto out;
       
  2240 
       
  2241 		strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
       
  2242 
       
  2243 		pa->code = (__le32 *)fw->data;
       
  2244 		pa->size = fw->size / FW_OPCODE_SIZE;
       
  2245 	}
       
  2246 	version[RTL_VER_SIZE - 1] = 0;
       
  2247 
       
  2248 	rc = true;
       
  2249 out:
       
  2250 	return rc;
       
  2251 }
       
  2252 
       
  2253 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
       
  2254 			   struct rtl_fw_phy_action *pa)
       
  2255 {
       
  2256 	bool rc = false;
       
  2257 	size_t index;
       
  2258 
       
  2259 	for (index = 0; index < pa->size; index++) {
       
  2260 		u32 action = le32_to_cpu(pa->code[index]);
       
  2261 		u32 regno = (action & 0x0fff0000) >> 16;
       
  2262 
       
  2263 		switch(action & 0xf0000000) {
       
  2264 		case PHY_READ:
       
  2265 		case PHY_DATA_OR:
       
  2266 		case PHY_DATA_AND:
       
  2267 		case PHY_MDIO_CHG:
       
  2268 		case PHY_CLEAR_READCOUNT:
       
  2269 		case PHY_WRITE:
       
  2270 		case PHY_WRITE_PREVIOUS:
       
  2271 		case PHY_DELAY_MS:
       
  2272 			break;
       
  2273 
       
  2274 		case PHY_BJMPN:
       
  2275 			if (regno > index) {
       
  2276 				netif_err(tp, ifup, tp->dev,
       
  2277 					  "Out of range of firmware\n");
       
  2278 				goto out;
       
  2279 			}
       
  2280 			break;
       
  2281 		case PHY_READCOUNT_EQ_SKIP:
       
  2282 			if (index + 2 >= pa->size) {
       
  2283 				netif_err(tp, ifup, tp->dev,
       
  2284 					  "Out of range of firmware\n");
       
  2285 				goto out;
       
  2286 			}
       
  2287 			break;
       
  2288 		case PHY_COMP_EQ_SKIPN:
       
  2289 		case PHY_COMP_NEQ_SKIPN:
       
  2290 		case PHY_SKIPN:
       
  2291 			if (index + 1 + regno >= pa->size) {
       
  2292 				netif_err(tp, ifup, tp->dev,
       
  2293 					  "Out of range of firmware\n");
       
  2294 				goto out;
       
  2295 			}
       
  2296 			break;
       
  2297 
       
  2298 		default:
       
  2299 			netif_err(tp, ifup, tp->dev,
       
  2300 				  "Invalid action 0x%08x\n", action);
       
  2301 			goto out;
       
  2302 		}
       
  2303 	}
       
  2304 	rc = true;
       
  2305 out:
       
  2306 	return rc;
       
  2307 }
       
  2308 
       
  2309 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
       
  2310 {
       
  2311 	struct net_device *dev = tp->dev;
       
  2312 	int rc = -EINVAL;
       
  2313 
       
  2314 	if (!rtl_fw_format_ok(tp, rtl_fw)) {
       
  2315 		netif_err(tp, ifup, dev, "invalid firwmare\n");
       
  2316 		goto out;
       
  2317 	}
       
  2318 
       
  2319 	if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
       
  2320 		rc = 0;
       
  2321 out:
       
  2322 	return rc;
       
  2323 }
       
  2324 
       
  2325 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
       
  2326 {
       
  2327 	struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
       
  2328 	struct mdio_ops org, *ops = &tp->mdio_ops;
       
  2329 	u32 predata, count;
       
  2330 	size_t index;
       
  2331 
       
  2332 	predata = count = 0;
       
  2333 	org.write = ops->write;
       
  2334 	org.read = ops->read;
       
  2335 
       
  2336 	for (index = 0; index < pa->size; ) {
       
  2337 		u32 action = le32_to_cpu(pa->code[index]);
       
  2338 		u32 data = action & 0x0000ffff;
       
  2339 		u32 regno = (action & 0x0fff0000) >> 16;
       
  2340 
       
  2341 		if (!action)
       
  2342 			break;
       
  2343 
       
  2344 		switch(action & 0xf0000000) {
       
  2345 		case PHY_READ:
       
  2346 			predata = rtl_readphy(tp, regno);
       
  2347 			count++;
       
  2348 			index++;
       
  2349 			break;
       
  2350 		case PHY_DATA_OR:
       
  2351 			predata |= data;
       
  2352 			index++;
       
  2353 			break;
       
  2354 		case PHY_DATA_AND:
       
  2355 			predata &= data;
       
  2356 			index++;
       
  2357 			break;
       
  2358 		case PHY_BJMPN:
       
  2359 			index -= regno;
       
  2360 			break;
       
  2361 		case PHY_MDIO_CHG:
       
  2362 			if (data == 0) {
       
  2363 				ops->write = org.write;
       
  2364 				ops->read = org.read;
       
  2365 			} else if (data == 1) {
       
  2366 				ops->write = mac_mcu_write;
       
  2367 				ops->read = mac_mcu_read;
       
  2368 			}
       
  2369 
       
  2370 			index++;
       
  2371 			break;
       
  2372 		case PHY_CLEAR_READCOUNT:
       
  2373 			count = 0;
       
  2374 			index++;
       
  2375 			break;
       
  2376 		case PHY_WRITE:
       
  2377 			rtl_writephy(tp, regno, data);
       
  2378 			index++;
       
  2379 			break;
       
  2380 		case PHY_READCOUNT_EQ_SKIP:
       
  2381 			index += (count == data) ? 2 : 1;
       
  2382 			break;
       
  2383 		case PHY_COMP_EQ_SKIPN:
       
  2384 			if (predata == data)
       
  2385 				index += regno;
       
  2386 			index++;
       
  2387 			break;
       
  2388 		case PHY_COMP_NEQ_SKIPN:
       
  2389 			if (predata != data)
       
  2390 				index += regno;
       
  2391 			index++;
       
  2392 			break;
       
  2393 		case PHY_WRITE_PREVIOUS:
       
  2394 			rtl_writephy(tp, regno, predata);
       
  2395 			index++;
       
  2396 			break;
       
  2397 		case PHY_SKIPN:
       
  2398 			index += regno + 1;
       
  2399 			break;
       
  2400 		case PHY_DELAY_MS:
       
  2401 			mdelay(data);
       
  2402 			index++;
       
  2403 			break;
       
  2404 
       
  2405 		default:
       
  2406 			BUG();
       
  2407 		}
       
  2408 	}
       
  2409 
       
  2410 	ops->write = org.write;
       
  2411 	ops->read = org.read;
       
  2412 }
       
  2413 
       
  2414 static void rtl_release_firmware(struct rtl8169_private *tp)
       
  2415 {
       
  2416 	if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
       
  2417 		release_firmware(tp->rtl_fw->fw);
       
  2418 		kfree(tp->rtl_fw);
       
  2419 	}
       
  2420 	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
       
  2421 }
       
  2422 
       
  2423 static void rtl_apply_firmware(struct rtl8169_private *tp)
       
  2424 {
       
  2425 	struct rtl_fw *rtl_fw = tp->rtl_fw;
       
  2426 
       
  2427 	/* TODO: release firmware once rtl_phy_write_fw signals failures. */
       
  2428 	if (!IS_ERR_OR_NULL(rtl_fw))
       
  2429 		rtl_phy_write_fw(tp, rtl_fw);
       
  2430 }
       
  2431 
       
  2432 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
       
  2433 {
       
  2434 	if (rtl_readphy(tp, reg) != val)
       
  2435 		netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
       
  2436 	else
       
  2437 		rtl_apply_firmware(tp);
       
  2438 }
       
  2439 
       
  2440 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
       
  2441 {
       
  2442 	static const struct phy_reg phy_reg_init[] = {
       
  2443 		{ 0x1f, 0x0001 },
       
  2444 		{ 0x06, 0x006e },
       
  2445 		{ 0x08, 0x0708 },
       
  2446 		{ 0x15, 0x4000 },
       
  2447 		{ 0x18, 0x65c7 },
       
  2448 
       
  2449 		{ 0x1f, 0x0001 },
       
  2450 		{ 0x03, 0x00a1 },
       
  2451 		{ 0x02, 0x0008 },
       
  2452 		{ 0x01, 0x0120 },
       
  2453 		{ 0x00, 0x1000 },
       
  2454 		{ 0x04, 0x0800 },
       
  2455 		{ 0x04, 0x0000 },
       
  2456 
       
  2457 		{ 0x03, 0xff41 },
       
  2458 		{ 0x02, 0xdf60 },
       
  2459 		{ 0x01, 0x0140 },
       
  2460 		{ 0x00, 0x0077 },
       
  2461 		{ 0x04, 0x7800 },
       
  2462 		{ 0x04, 0x7000 },
       
  2463 
       
  2464 		{ 0x03, 0x802f },
       
  2465 		{ 0x02, 0x4f02 },
       
  2466 		{ 0x01, 0x0409 },
       
  2467 		{ 0x00, 0xf0f9 },
       
  2468 		{ 0x04, 0x9800 },
       
  2469 		{ 0x04, 0x9000 },
       
  2470 
       
  2471 		{ 0x03, 0xdf01 },
       
  2472 		{ 0x02, 0xdf20 },
       
  2473 		{ 0x01, 0xff95 },
       
  2474 		{ 0x00, 0xba00 },
       
  2475 		{ 0x04, 0xa800 },
       
  2476 		{ 0x04, 0xa000 },
       
  2477 
       
  2478 		{ 0x03, 0xff41 },
       
  2479 		{ 0x02, 0xdf20 },
       
  2480 		{ 0x01, 0x0140 },
       
  2481 		{ 0x00, 0x00bb },
       
  2482 		{ 0x04, 0xb800 },
       
  2483 		{ 0x04, 0xb000 },
       
  2484 
       
  2485 		{ 0x03, 0xdf41 },
       
  2486 		{ 0x02, 0xdc60 },
       
  2487 		{ 0x01, 0x6340 },
       
  2488 		{ 0x00, 0x007d },
       
  2489 		{ 0x04, 0xd800 },
       
  2490 		{ 0x04, 0xd000 },
       
  2491 
       
  2492 		{ 0x03, 0xdf01 },
       
  2493 		{ 0x02, 0xdf20 },
       
  2494 		{ 0x01, 0x100a },
       
  2495 		{ 0x00, 0xa0ff },
       
  2496 		{ 0x04, 0xf800 },
       
  2497 		{ 0x04, 0xf000 },
       
  2498 
       
  2499 		{ 0x1f, 0x0000 },
       
  2500 		{ 0x0b, 0x0000 },
       
  2501 		{ 0x00, 0x9200 }
       
  2502 	};
       
  2503 
       
  2504 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2505 }
       
  2506 
       
  2507 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
       
  2508 {
       
  2509 	static const struct phy_reg phy_reg_init[] = {
       
  2510 		{ 0x1f, 0x0002 },
       
  2511 		{ 0x01, 0x90d0 },
       
  2512 		{ 0x1f, 0x0000 }
       
  2513 	};
       
  2514 
       
  2515 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2516 }
       
  2517 
       
  2518 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
       
  2519 {
       
  2520 	struct pci_dev *pdev = tp->pci_dev;
       
  2521 
       
  2522 	if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
       
  2523 	    (pdev->subsystem_device != 0xe000))
       
  2524 		return;
       
  2525 
       
  2526 	rtl_writephy(tp, 0x1f, 0x0001);
       
  2527 	rtl_writephy(tp, 0x10, 0xf01b);
       
  2528 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2529 }
       
  2530 
       
  2531 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
       
  2532 {
       
  2533 	static const struct phy_reg phy_reg_init[] = {
       
  2534 		{ 0x1f, 0x0001 },
       
  2535 		{ 0x04, 0x0000 },
       
  2536 		{ 0x03, 0x00a1 },
       
  2537 		{ 0x02, 0x0008 },
       
  2538 		{ 0x01, 0x0120 },
       
  2539 		{ 0x00, 0x1000 },
       
  2540 		{ 0x04, 0x0800 },
       
  2541 		{ 0x04, 0x9000 },
       
  2542 		{ 0x03, 0x802f },
       
  2543 		{ 0x02, 0x4f02 },
       
  2544 		{ 0x01, 0x0409 },
       
  2545 		{ 0x00, 0xf099 },
       
  2546 		{ 0x04, 0x9800 },
       
  2547 		{ 0x04, 0xa000 },
       
  2548 		{ 0x03, 0xdf01 },
       
  2549 		{ 0x02, 0xdf20 },
       
  2550 		{ 0x01, 0xff95 },
       
  2551 		{ 0x00, 0xba00 },
       
  2552 		{ 0x04, 0xa800 },
       
  2553 		{ 0x04, 0xf000 },
       
  2554 		{ 0x03, 0xdf01 },
       
  2555 		{ 0x02, 0xdf20 },
       
  2556 		{ 0x01, 0x101a },
       
  2557 		{ 0x00, 0xa0ff },
       
  2558 		{ 0x04, 0xf800 },
       
  2559 		{ 0x04, 0x0000 },
       
  2560 		{ 0x1f, 0x0000 },
       
  2561 
       
  2562 		{ 0x1f, 0x0001 },
       
  2563 		{ 0x10, 0xf41b },
       
  2564 		{ 0x14, 0xfb54 },
       
  2565 		{ 0x18, 0xf5c7 },
       
  2566 		{ 0x1f, 0x0000 },
       
  2567 
       
  2568 		{ 0x1f, 0x0001 },
       
  2569 		{ 0x17, 0x0cc0 },
       
  2570 		{ 0x1f, 0x0000 }
       
  2571 	};
       
  2572 
       
  2573 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2574 
       
  2575 	rtl8169scd_hw_phy_config_quirk(tp);
       
  2576 }
       
  2577 
       
  2578 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
       
  2579 {
       
  2580 	static const struct phy_reg phy_reg_init[] = {
       
  2581 		{ 0x1f, 0x0001 },
       
  2582 		{ 0x04, 0x0000 },
       
  2583 		{ 0x03, 0x00a1 },
       
  2584 		{ 0x02, 0x0008 },
       
  2585 		{ 0x01, 0x0120 },
       
  2586 		{ 0x00, 0x1000 },
       
  2587 		{ 0x04, 0x0800 },
       
  2588 		{ 0x04, 0x9000 },
       
  2589 		{ 0x03, 0x802f },
       
  2590 		{ 0x02, 0x4f02 },
       
  2591 		{ 0x01, 0x0409 },
       
  2592 		{ 0x00, 0xf099 },
       
  2593 		{ 0x04, 0x9800 },
       
  2594 		{ 0x04, 0xa000 },
       
  2595 		{ 0x03, 0xdf01 },
       
  2596 		{ 0x02, 0xdf20 },
       
  2597 		{ 0x01, 0xff95 },
       
  2598 		{ 0x00, 0xba00 },
       
  2599 		{ 0x04, 0xa800 },
       
  2600 		{ 0x04, 0xf000 },
       
  2601 		{ 0x03, 0xdf01 },
       
  2602 		{ 0x02, 0xdf20 },
       
  2603 		{ 0x01, 0x101a },
       
  2604 		{ 0x00, 0xa0ff },
       
  2605 		{ 0x04, 0xf800 },
       
  2606 		{ 0x04, 0x0000 },
       
  2607 		{ 0x1f, 0x0000 },
       
  2608 
       
  2609 		{ 0x1f, 0x0001 },
       
  2610 		{ 0x0b, 0x8480 },
       
  2611 		{ 0x1f, 0x0000 },
       
  2612 
       
  2613 		{ 0x1f, 0x0001 },
       
  2614 		{ 0x18, 0x67c7 },
       
  2615 		{ 0x04, 0x2000 },
       
  2616 		{ 0x03, 0x002f },
       
  2617 		{ 0x02, 0x4360 },
       
  2618 		{ 0x01, 0x0109 },
       
  2619 		{ 0x00, 0x3022 },
       
  2620 		{ 0x04, 0x2800 },
       
  2621 		{ 0x1f, 0x0000 },
       
  2622 
       
  2623 		{ 0x1f, 0x0001 },
       
  2624 		{ 0x17, 0x0cc0 },
       
  2625 		{ 0x1f, 0x0000 }
       
  2626 	};
       
  2627 
       
  2628 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2629 }
       
  2630 
       
  2631 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
       
  2632 {
       
  2633 	static const struct phy_reg phy_reg_init[] = {
       
  2634 		{ 0x10, 0xf41b },
       
  2635 		{ 0x1f, 0x0000 }
       
  2636 	};
       
  2637 
       
  2638 	rtl_writephy(tp, 0x1f, 0x0001);
       
  2639 	rtl_patchphy(tp, 0x16, 1 << 0);
       
  2640 
       
  2641 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2642 }
       
  2643 
       
  2644 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
       
  2645 {
       
  2646 	static const struct phy_reg phy_reg_init[] = {
       
  2647 		{ 0x1f, 0x0001 },
       
  2648 		{ 0x10, 0xf41b },
       
  2649 		{ 0x1f, 0x0000 }
       
  2650 	};
       
  2651 
       
  2652 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2653 }
       
  2654 
       
  2655 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
       
  2656 {
       
  2657 	static const struct phy_reg phy_reg_init[] = {
       
  2658 		{ 0x1f, 0x0000 },
       
  2659 		{ 0x1d, 0x0f00 },
       
  2660 		{ 0x1f, 0x0002 },
       
  2661 		{ 0x0c, 0x1ec8 },
       
  2662 		{ 0x1f, 0x0000 }
       
  2663 	};
       
  2664 
       
  2665 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2666 }
       
  2667 
       
  2668 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
       
  2669 {
       
  2670 	static const struct phy_reg phy_reg_init[] = {
       
  2671 		{ 0x1f, 0x0001 },
       
  2672 		{ 0x1d, 0x3d98 },
       
  2673 		{ 0x1f, 0x0000 }
       
  2674 	};
       
  2675 
       
  2676 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2677 	rtl_patchphy(tp, 0x14, 1 << 5);
       
  2678 	rtl_patchphy(tp, 0x0d, 1 << 5);
       
  2679 
       
  2680 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2681 }
       
  2682 
       
  2683 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
       
  2684 {
       
  2685 	static const struct phy_reg phy_reg_init[] = {
       
  2686 		{ 0x1f, 0x0001 },
       
  2687 		{ 0x12, 0x2300 },
       
  2688 		{ 0x1f, 0x0002 },
       
  2689 		{ 0x00, 0x88d4 },
       
  2690 		{ 0x01, 0x82b1 },
       
  2691 		{ 0x03, 0x7002 },
       
  2692 		{ 0x08, 0x9e30 },
       
  2693 		{ 0x09, 0x01f0 },
       
  2694 		{ 0x0a, 0x5500 },
       
  2695 		{ 0x0c, 0x00c8 },
       
  2696 		{ 0x1f, 0x0003 },
       
  2697 		{ 0x12, 0xc096 },
       
  2698 		{ 0x16, 0x000a },
       
  2699 		{ 0x1f, 0x0000 },
       
  2700 		{ 0x1f, 0x0000 },
       
  2701 		{ 0x09, 0x2000 },
       
  2702 		{ 0x09, 0x0000 }
       
  2703 	};
       
  2704 
       
  2705 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2706 
       
  2707 	rtl_patchphy(tp, 0x14, 1 << 5);
       
  2708 	rtl_patchphy(tp, 0x0d, 1 << 5);
       
  2709 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2710 }
       
  2711 
       
  2712 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
       
  2713 {
       
  2714 	static const struct phy_reg phy_reg_init[] = {
       
  2715 		{ 0x1f, 0x0001 },
       
  2716 		{ 0x12, 0x2300 },
       
  2717 		{ 0x03, 0x802f },
       
  2718 		{ 0x02, 0x4f02 },
       
  2719 		{ 0x01, 0x0409 },
       
  2720 		{ 0x00, 0xf099 },
       
  2721 		{ 0x04, 0x9800 },
       
  2722 		{ 0x04, 0x9000 },
       
  2723 		{ 0x1d, 0x3d98 },
       
  2724 		{ 0x1f, 0x0002 },
       
  2725 		{ 0x0c, 0x7eb8 },
       
  2726 		{ 0x06, 0x0761 },
       
  2727 		{ 0x1f, 0x0003 },
       
  2728 		{ 0x16, 0x0f0a },
       
  2729 		{ 0x1f, 0x0000 }
       
  2730 	};
       
  2731 
       
  2732 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2733 
       
  2734 	rtl_patchphy(tp, 0x16, 1 << 0);
       
  2735 	rtl_patchphy(tp, 0x14, 1 << 5);
       
  2736 	rtl_patchphy(tp, 0x0d, 1 << 5);
       
  2737 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2738 }
       
  2739 
       
  2740 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
       
  2741 {
       
  2742 	static const struct phy_reg phy_reg_init[] = {
       
  2743 		{ 0x1f, 0x0001 },
       
  2744 		{ 0x12, 0x2300 },
       
  2745 		{ 0x1d, 0x3d98 },
       
  2746 		{ 0x1f, 0x0002 },
       
  2747 		{ 0x0c, 0x7eb8 },
       
  2748 		{ 0x06, 0x5461 },
       
  2749 		{ 0x1f, 0x0003 },
       
  2750 		{ 0x16, 0x0f0a },
       
  2751 		{ 0x1f, 0x0000 }
       
  2752 	};
       
  2753 
       
  2754 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2755 
       
  2756 	rtl_patchphy(tp, 0x16, 1 << 0);
       
  2757 	rtl_patchphy(tp, 0x14, 1 << 5);
       
  2758 	rtl_patchphy(tp, 0x0d, 1 << 5);
       
  2759 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2760 }
       
  2761 
       
  2762 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
       
  2763 {
       
  2764 	rtl8168c_3_hw_phy_config(tp);
       
  2765 }
       
  2766 
       
  2767 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
       
  2768 {
       
  2769 	static const struct phy_reg phy_reg_init_0[] = {
       
  2770 		/* Channel Estimation */
       
  2771 		{ 0x1f, 0x0001 },
       
  2772 		{ 0x06, 0x4064 },
       
  2773 		{ 0x07, 0x2863 },
       
  2774 		{ 0x08, 0x059c },
       
  2775 		{ 0x09, 0x26b4 },
       
  2776 		{ 0x0a, 0x6a19 },
       
  2777 		{ 0x0b, 0xdcc8 },
       
  2778 		{ 0x10, 0xf06d },
       
  2779 		{ 0x14, 0x7f68 },
       
  2780 		{ 0x18, 0x7fd9 },
       
  2781 		{ 0x1c, 0xf0ff },
       
  2782 		{ 0x1d, 0x3d9c },
       
  2783 		{ 0x1f, 0x0003 },
       
  2784 		{ 0x12, 0xf49f },
       
  2785 		{ 0x13, 0x070b },
       
  2786 		{ 0x1a, 0x05ad },
       
  2787 		{ 0x14, 0x94c0 },
       
  2788 
       
  2789 		/*
       
  2790 		 * Tx Error Issue
       
  2791 		 * Enhance line driver power
       
  2792 		 */
       
  2793 		{ 0x1f, 0x0002 },
       
  2794 		{ 0x06, 0x5561 },
       
  2795 		{ 0x1f, 0x0005 },
       
  2796 		{ 0x05, 0x8332 },
       
  2797 		{ 0x06, 0x5561 },
       
  2798 
       
  2799 		/*
       
  2800 		 * Can not link to 1Gbps with bad cable
       
  2801 		 * Decrease SNR threshold form 21.07dB to 19.04dB
       
  2802 		 */
       
  2803 		{ 0x1f, 0x0001 },
       
  2804 		{ 0x17, 0x0cc0 },
       
  2805 
       
  2806 		{ 0x1f, 0x0000 },
       
  2807 		{ 0x0d, 0xf880 }
       
  2808 	};
       
  2809 
       
  2810 	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
       
  2811 
       
  2812 	/*
       
  2813 	 * Rx Error Issue
       
  2814 	 * Fine Tune Switching regulator parameter
       
  2815 	 */
       
  2816 	rtl_writephy(tp, 0x1f, 0x0002);
       
  2817 	rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
       
  2818 	rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
       
  2819 
       
  2820 	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
       
  2821 		static const struct phy_reg phy_reg_init[] = {
       
  2822 			{ 0x1f, 0x0002 },
       
  2823 			{ 0x05, 0x669a },
       
  2824 			{ 0x1f, 0x0005 },
       
  2825 			{ 0x05, 0x8330 },
       
  2826 			{ 0x06, 0x669a },
       
  2827 			{ 0x1f, 0x0002 }
       
  2828 		};
       
  2829 		int val;
       
  2830 
       
  2831 		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2832 
       
  2833 		val = rtl_readphy(tp, 0x0d);
       
  2834 
       
  2835 		if ((val & 0x00ff) != 0x006c) {
       
  2836 			static const u32 set[] = {
       
  2837 				0x0065, 0x0066, 0x0067, 0x0068,
       
  2838 				0x0069, 0x006a, 0x006b, 0x006c
       
  2839 			};
       
  2840 			int i;
       
  2841 
       
  2842 			rtl_writephy(tp, 0x1f, 0x0002);
       
  2843 
       
  2844 			val &= 0xff00;
       
  2845 			for (i = 0; i < ARRAY_SIZE(set); i++)
       
  2846 				rtl_writephy(tp, 0x0d, val | set[i]);
       
  2847 		}
       
  2848 	} else {
       
  2849 		static const struct phy_reg phy_reg_init[] = {
       
  2850 			{ 0x1f, 0x0002 },
       
  2851 			{ 0x05, 0x6662 },
       
  2852 			{ 0x1f, 0x0005 },
       
  2853 			{ 0x05, 0x8330 },
       
  2854 			{ 0x06, 0x6662 }
       
  2855 		};
       
  2856 
       
  2857 		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2858 	}
       
  2859 
       
  2860 	/* RSET couple improve */
       
  2861 	rtl_writephy(tp, 0x1f, 0x0002);
       
  2862 	rtl_patchphy(tp, 0x0d, 0x0300);
       
  2863 	rtl_patchphy(tp, 0x0f, 0x0010);
       
  2864 
       
  2865 	/* Fine tune PLL performance */
       
  2866 	rtl_writephy(tp, 0x1f, 0x0002);
       
  2867 	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
       
  2868 	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
       
  2869 
       
  2870 	rtl_writephy(tp, 0x1f, 0x0005);
       
  2871 	rtl_writephy(tp, 0x05, 0x001b);
       
  2872 
       
  2873 	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
       
  2874 
       
  2875 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2876 }
       
  2877 
       
  2878 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
       
  2879 {
       
  2880 	static const struct phy_reg phy_reg_init_0[] = {
       
  2881 		/* Channel Estimation */
       
  2882 		{ 0x1f, 0x0001 },
       
  2883 		{ 0x06, 0x4064 },
       
  2884 		{ 0x07, 0x2863 },
       
  2885 		{ 0x08, 0x059c },
       
  2886 		{ 0x09, 0x26b4 },
       
  2887 		{ 0x0a, 0x6a19 },
       
  2888 		{ 0x0b, 0xdcc8 },
       
  2889 		{ 0x10, 0xf06d },
       
  2890 		{ 0x14, 0x7f68 },
       
  2891 		{ 0x18, 0x7fd9 },
       
  2892 		{ 0x1c, 0xf0ff },
       
  2893 		{ 0x1d, 0x3d9c },
       
  2894 		{ 0x1f, 0x0003 },
       
  2895 		{ 0x12, 0xf49f },
       
  2896 		{ 0x13, 0x070b },
       
  2897 		{ 0x1a, 0x05ad },
       
  2898 		{ 0x14, 0x94c0 },
       
  2899 
       
  2900 		/*
       
  2901 		 * Tx Error Issue
       
  2902 		 * Enhance line driver power
       
  2903 		 */
       
  2904 		{ 0x1f, 0x0002 },
       
  2905 		{ 0x06, 0x5561 },
       
  2906 		{ 0x1f, 0x0005 },
       
  2907 		{ 0x05, 0x8332 },
       
  2908 		{ 0x06, 0x5561 },
       
  2909 
       
  2910 		/*
       
  2911 		 * Can not link to 1Gbps with bad cable
       
  2912 		 * Decrease SNR threshold form 21.07dB to 19.04dB
       
  2913 		 */
       
  2914 		{ 0x1f, 0x0001 },
       
  2915 		{ 0x17, 0x0cc0 },
       
  2916 
       
  2917 		{ 0x1f, 0x0000 },
       
  2918 		{ 0x0d, 0xf880 }
       
  2919 	};
       
  2920 
       
  2921 	rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
       
  2922 
       
  2923 	if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
       
  2924 		static const struct phy_reg phy_reg_init[] = {
       
  2925 			{ 0x1f, 0x0002 },
       
  2926 			{ 0x05, 0x669a },
       
  2927 			{ 0x1f, 0x0005 },
       
  2928 			{ 0x05, 0x8330 },
       
  2929 			{ 0x06, 0x669a },
       
  2930 
       
  2931 			{ 0x1f, 0x0002 }
       
  2932 		};
       
  2933 		int val;
       
  2934 
       
  2935 		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2936 
       
  2937 		val = rtl_readphy(tp, 0x0d);
       
  2938 		if ((val & 0x00ff) != 0x006c) {
       
  2939 			static const u32 set[] = {
       
  2940 				0x0065, 0x0066, 0x0067, 0x0068,
       
  2941 				0x0069, 0x006a, 0x006b, 0x006c
       
  2942 			};
       
  2943 			int i;
       
  2944 
       
  2945 			rtl_writephy(tp, 0x1f, 0x0002);
       
  2946 
       
  2947 			val &= 0xff00;
       
  2948 			for (i = 0; i < ARRAY_SIZE(set); i++)
       
  2949 				rtl_writephy(tp, 0x0d, val | set[i]);
       
  2950 		}
       
  2951 	} else {
       
  2952 		static const struct phy_reg phy_reg_init[] = {
       
  2953 			{ 0x1f, 0x0002 },
       
  2954 			{ 0x05, 0x2642 },
       
  2955 			{ 0x1f, 0x0005 },
       
  2956 			{ 0x05, 0x8330 },
       
  2957 			{ 0x06, 0x2642 }
       
  2958 		};
       
  2959 
       
  2960 		rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  2961 	}
       
  2962 
       
  2963 	/* Fine tune PLL performance */
       
  2964 	rtl_writephy(tp, 0x1f, 0x0002);
       
  2965 	rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
       
  2966 	rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
       
  2967 
       
  2968 	/* Switching regulator Slew rate */
       
  2969 	rtl_writephy(tp, 0x1f, 0x0002);
       
  2970 	rtl_patchphy(tp, 0x0f, 0x0017);
       
  2971 
       
  2972 	rtl_writephy(tp, 0x1f, 0x0005);
       
  2973 	rtl_writephy(tp, 0x05, 0x001b);
       
  2974 
       
  2975 	rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
       
  2976 
       
  2977 	rtl_writephy(tp, 0x1f, 0x0000);
       
  2978 }
       
  2979 
       
  2980 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
       
  2981 {
       
  2982 	static const struct phy_reg phy_reg_init[] = {
       
  2983 		{ 0x1f, 0x0002 },
       
  2984 		{ 0x10, 0x0008 },
       
  2985 		{ 0x0d, 0x006c },
       
  2986 
       
  2987 		{ 0x1f, 0x0000 },
       
  2988 		{ 0x0d, 0xf880 },
       
  2989 
       
  2990 		{ 0x1f, 0x0001 },
       
  2991 		{ 0x17, 0x0cc0 },
       
  2992 
       
  2993 		{ 0x1f, 0x0001 },
       
  2994 		{ 0x0b, 0xa4d8 },
       
  2995 		{ 0x09, 0x281c },
       
  2996 		{ 0x07, 0x2883 },
       
  2997 		{ 0x0a, 0x6b35 },
       
  2998 		{ 0x1d, 0x3da4 },
       
  2999 		{ 0x1c, 0xeffd },
       
  3000 		{ 0x14, 0x7f52 },
       
  3001 		{ 0x18, 0x7fc6 },
       
  3002 		{ 0x08, 0x0601 },
       
  3003 		{ 0x06, 0x4063 },
       
  3004 		{ 0x10, 0xf074 },
       
  3005 		{ 0x1f, 0x0003 },
       
  3006 		{ 0x13, 0x0789 },
       
  3007 		{ 0x12, 0xf4bd },
       
  3008 		{ 0x1a, 0x04fd },
       
  3009 		{ 0x14, 0x84b0 },
       
  3010 		{ 0x1f, 0x0000 },
       
  3011 		{ 0x00, 0x9200 },
       
  3012 
       
  3013 		{ 0x1f, 0x0005 },
       
  3014 		{ 0x01, 0x0340 },
       
  3015 		{ 0x1f, 0x0001 },
       
  3016 		{ 0x04, 0x4000 },
       
  3017 		{ 0x03, 0x1d21 },
       
  3018 		{ 0x02, 0x0c32 },
       
  3019 		{ 0x01, 0x0200 },
       
  3020 		{ 0x00, 0x5554 },
       
  3021 		{ 0x04, 0x4800 },
       
  3022 		{ 0x04, 0x4000 },
       
  3023 		{ 0x04, 0xf000 },
       
  3024 		{ 0x03, 0xdf01 },
       
  3025 		{ 0x02, 0xdf20 },
       
  3026 		{ 0x01, 0x101a },
       
  3027 		{ 0x00, 0xa0ff },
       
  3028 		{ 0x04, 0xf800 },
       
  3029 		{ 0x04, 0xf000 },
       
  3030 		{ 0x1f, 0x0000 },
       
  3031 
       
  3032 		{ 0x1f, 0x0007 },
       
  3033 		{ 0x1e, 0x0023 },
       
  3034 		{ 0x16, 0x0000 },
       
  3035 		{ 0x1f, 0x0000 }
       
  3036 	};
       
  3037 
       
  3038 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3039 }
       
  3040 
       
  3041 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
       
  3042 {
       
  3043 	static const struct phy_reg phy_reg_init[] = {
       
  3044 		{ 0x1f, 0x0001 },
       
  3045 		{ 0x17, 0x0cc0 },
       
  3046 
       
  3047 		{ 0x1f, 0x0007 },
       
  3048 		{ 0x1e, 0x002d },
       
  3049 		{ 0x18, 0x0040 },
       
  3050 		{ 0x1f, 0x0000 }
       
  3051 	};
       
  3052 
       
  3053 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3054 	rtl_patchphy(tp, 0x0d, 1 << 5);
       
  3055 }
       
  3056 
       
  3057 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
       
  3058 {
       
  3059 	static const struct phy_reg phy_reg_init[] = {
       
  3060 		/* Enable Delay cap */
       
  3061 		{ 0x1f, 0x0005 },
       
  3062 		{ 0x05, 0x8b80 },
       
  3063 		{ 0x06, 0xc896 },
       
  3064 		{ 0x1f, 0x0000 },
       
  3065 
       
  3066 		/* Channel estimation fine tune */
       
  3067 		{ 0x1f, 0x0001 },
       
  3068 		{ 0x0b, 0x6c20 },
       
  3069 		{ 0x07, 0x2872 },
       
  3070 		{ 0x1c, 0xefff },
       
  3071 		{ 0x1f, 0x0003 },
       
  3072 		{ 0x14, 0x6420 },
       
  3073 		{ 0x1f, 0x0000 },
       
  3074 
       
  3075 		/* Update PFM & 10M TX idle timer */
       
  3076 		{ 0x1f, 0x0007 },
       
  3077 		{ 0x1e, 0x002f },
       
  3078 		{ 0x15, 0x1919 },
       
  3079 		{ 0x1f, 0x0000 },
       
  3080 
       
  3081 		{ 0x1f, 0x0007 },
       
  3082 		{ 0x1e, 0x00ac },
       
  3083 		{ 0x18, 0x0006 },
       
  3084 		{ 0x1f, 0x0000 }
       
  3085 	};
       
  3086 
       
  3087 	rtl_apply_firmware(tp);
       
  3088 
       
  3089 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3090 
       
  3091 	/* DCO enable for 10M IDLE Power */
       
  3092 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3093 	rtl_writephy(tp, 0x1e, 0x0023);
       
  3094 	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
       
  3095 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3096 
       
  3097 	/* For impedance matching */
       
  3098 	rtl_writephy(tp, 0x1f, 0x0002);
       
  3099 	rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
       
  3100 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3101 
       
  3102 	/* PHY auto speed down */
       
  3103 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3104 	rtl_writephy(tp, 0x1e, 0x002d);
       
  3105 	rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
       
  3106 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3107 	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
       
  3108 
       
  3109 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3110 	rtl_writephy(tp, 0x05, 0x8b86);
       
  3111 	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
       
  3112 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3113 
       
  3114 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3115 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3116 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
       
  3117 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3118 	rtl_writephy(tp, 0x1e, 0x0020);
       
  3119 	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
       
  3120 	rtl_writephy(tp, 0x1f, 0x0006);
       
  3121 	rtl_writephy(tp, 0x00, 0x5a00);
       
  3122 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3123 	rtl_writephy(tp, 0x0d, 0x0007);
       
  3124 	rtl_writephy(tp, 0x0e, 0x003c);
       
  3125 	rtl_writephy(tp, 0x0d, 0x4007);
       
  3126 	rtl_writephy(tp, 0x0e, 0x0000);
       
  3127 	rtl_writephy(tp, 0x0d, 0x0000);
       
  3128 }
       
  3129 
       
  3130 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
       
  3131 {
       
  3132 	const u16 w[] = {
       
  3133 		addr[0] | (addr[1] << 8),
       
  3134 		addr[2] | (addr[3] << 8),
       
  3135 		addr[4] | (addr[5] << 8)
       
  3136 	};
       
  3137 	const struct exgmac_reg e[] = {
       
  3138 		{ .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
       
  3139 		{ .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
       
  3140 		{ .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
       
  3141 		{ .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
       
  3142 	};
       
  3143 
       
  3144 	rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
       
  3145 }
       
  3146 
       
  3147 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
       
  3148 {
       
  3149 	static const struct phy_reg phy_reg_init[] = {
       
  3150 		/* Enable Delay cap */
       
  3151 		{ 0x1f, 0x0004 },
       
  3152 		{ 0x1f, 0x0007 },
       
  3153 		{ 0x1e, 0x00ac },
       
  3154 		{ 0x18, 0x0006 },
       
  3155 		{ 0x1f, 0x0002 },
       
  3156 		{ 0x1f, 0x0000 },
       
  3157 		{ 0x1f, 0x0000 },
       
  3158 
       
  3159 		/* Channel estimation fine tune */
       
  3160 		{ 0x1f, 0x0003 },
       
  3161 		{ 0x09, 0xa20f },
       
  3162 		{ 0x1f, 0x0000 },
       
  3163 		{ 0x1f, 0x0000 },
       
  3164 
       
  3165 		/* Green Setting */
       
  3166 		{ 0x1f, 0x0005 },
       
  3167 		{ 0x05, 0x8b5b },
       
  3168 		{ 0x06, 0x9222 },
       
  3169 		{ 0x05, 0x8b6d },
       
  3170 		{ 0x06, 0x8000 },
       
  3171 		{ 0x05, 0x8b76 },
       
  3172 		{ 0x06, 0x8000 },
       
  3173 		{ 0x1f, 0x0000 }
       
  3174 	};
       
  3175 
       
  3176 	rtl_apply_firmware(tp);
       
  3177 
       
  3178 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3179 
       
  3180 	/* For 4-corner performance improve */
       
  3181 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3182 	rtl_writephy(tp, 0x05, 0x8b80);
       
  3183 	rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
       
  3184 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3185 
       
  3186 	/* PHY auto speed down */
       
  3187 	rtl_writephy(tp, 0x1f, 0x0004);
       
  3188 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3189 	rtl_writephy(tp, 0x1e, 0x002d);
       
  3190 	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
       
  3191 	rtl_writephy(tp, 0x1f, 0x0002);
       
  3192 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3193 	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
       
  3194 
       
  3195 	/* improve 10M EEE waveform */
       
  3196 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3197 	rtl_writephy(tp, 0x05, 0x8b86);
       
  3198 	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
       
  3199 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3200 
       
  3201 	/* Improve 2-pair detection performance */
       
  3202 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3203 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3204 	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
       
  3205 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3206 
       
  3207 	/* EEE setting */
       
  3208 	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
       
  3209 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3210 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3211 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
       
  3212 	rtl_writephy(tp, 0x1f, 0x0004);
       
  3213 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3214 	rtl_writephy(tp, 0x1e, 0x0020);
       
  3215 	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
       
  3216 	rtl_writephy(tp, 0x1f, 0x0002);
       
  3217 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3218 	rtl_writephy(tp, 0x0d, 0x0007);
       
  3219 	rtl_writephy(tp, 0x0e, 0x003c);
       
  3220 	rtl_writephy(tp, 0x0d, 0x4007);
       
  3221 	rtl_writephy(tp, 0x0e, 0x0000);
       
  3222 	rtl_writephy(tp, 0x0d, 0x0000);
       
  3223 
       
  3224 	/* Green feature */
       
  3225 	rtl_writephy(tp, 0x1f, 0x0003);
       
  3226 	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
       
  3227 	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
       
  3228 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3229 
       
  3230 	/* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
       
  3231 	rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
       
  3232 }
       
  3233 
       
  3234 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
       
  3235 {
       
  3236 	/* For 4-corner performance improve */
       
  3237 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3238 	rtl_writephy(tp, 0x05, 0x8b80);
       
  3239 	rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
       
  3240 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3241 
       
  3242 	/* PHY auto speed down */
       
  3243 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3244 	rtl_writephy(tp, 0x1e, 0x002d);
       
  3245 	rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
       
  3246 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3247 	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
       
  3248 
       
  3249 	/* Improve 10M EEE waveform */
       
  3250 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3251 	rtl_writephy(tp, 0x05, 0x8b86);
       
  3252 	rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
       
  3253 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3254 }
       
  3255 
       
  3256 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
       
  3257 {
       
  3258 	static const struct phy_reg phy_reg_init[] = {
       
  3259 		/* Channel estimation fine tune */
       
  3260 		{ 0x1f, 0x0003 },
       
  3261 		{ 0x09, 0xa20f },
       
  3262 		{ 0x1f, 0x0000 },
       
  3263 
       
  3264 		/* Modify green table for giga & fnet */
       
  3265 		{ 0x1f, 0x0005 },
       
  3266 		{ 0x05, 0x8b55 },
       
  3267 		{ 0x06, 0x0000 },
       
  3268 		{ 0x05, 0x8b5e },
       
  3269 		{ 0x06, 0x0000 },
       
  3270 		{ 0x05, 0x8b67 },
       
  3271 		{ 0x06, 0x0000 },
       
  3272 		{ 0x05, 0x8b70 },
       
  3273 		{ 0x06, 0x0000 },
       
  3274 		{ 0x1f, 0x0000 },
       
  3275 		{ 0x1f, 0x0007 },
       
  3276 		{ 0x1e, 0x0078 },
       
  3277 		{ 0x17, 0x0000 },
       
  3278 		{ 0x19, 0x00fb },
       
  3279 		{ 0x1f, 0x0000 },
       
  3280 
       
  3281 		/* Modify green table for 10M */
       
  3282 		{ 0x1f, 0x0005 },
       
  3283 		{ 0x05, 0x8b79 },
       
  3284 		{ 0x06, 0xaa00 },
       
  3285 		{ 0x1f, 0x0000 },
       
  3286 
       
  3287 		/* Disable hiimpedance detection (RTCT) */
       
  3288 		{ 0x1f, 0x0003 },
       
  3289 		{ 0x01, 0x328a },
       
  3290 		{ 0x1f, 0x0000 }
       
  3291 	};
       
  3292 
       
  3293 	rtl_apply_firmware(tp);
       
  3294 
       
  3295 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3296 
       
  3297 	rtl8168f_hw_phy_config(tp);
       
  3298 
       
  3299 	/* Improve 2-pair detection performance */
       
  3300 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3301 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3302 	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
       
  3303 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3304 }
       
  3305 
       
  3306 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
       
  3307 {
       
  3308 	rtl_apply_firmware(tp);
       
  3309 
       
  3310 	rtl8168f_hw_phy_config(tp);
       
  3311 }
       
  3312 
       
  3313 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
       
  3314 {
       
  3315 	static const struct phy_reg phy_reg_init[] = {
       
  3316 		/* Channel estimation fine tune */
       
  3317 		{ 0x1f, 0x0003 },
       
  3318 		{ 0x09, 0xa20f },
       
  3319 		{ 0x1f, 0x0000 },
       
  3320 
       
  3321 		/* Modify green table for giga & fnet */
       
  3322 		{ 0x1f, 0x0005 },
       
  3323 		{ 0x05, 0x8b55 },
       
  3324 		{ 0x06, 0x0000 },
       
  3325 		{ 0x05, 0x8b5e },
       
  3326 		{ 0x06, 0x0000 },
       
  3327 		{ 0x05, 0x8b67 },
       
  3328 		{ 0x06, 0x0000 },
       
  3329 		{ 0x05, 0x8b70 },
       
  3330 		{ 0x06, 0x0000 },
       
  3331 		{ 0x1f, 0x0000 },
       
  3332 		{ 0x1f, 0x0007 },
       
  3333 		{ 0x1e, 0x0078 },
       
  3334 		{ 0x17, 0x0000 },
       
  3335 		{ 0x19, 0x00aa },
       
  3336 		{ 0x1f, 0x0000 },
       
  3337 
       
  3338 		/* Modify green table for 10M */
       
  3339 		{ 0x1f, 0x0005 },
       
  3340 		{ 0x05, 0x8b79 },
       
  3341 		{ 0x06, 0xaa00 },
       
  3342 		{ 0x1f, 0x0000 },
       
  3343 
       
  3344 		/* Disable hiimpedance detection (RTCT) */
       
  3345 		{ 0x1f, 0x0003 },
       
  3346 		{ 0x01, 0x328a },
       
  3347 		{ 0x1f, 0x0000 }
       
  3348 	};
       
  3349 
       
  3350 
       
  3351 	rtl_apply_firmware(tp);
       
  3352 
       
  3353 	rtl8168f_hw_phy_config(tp);
       
  3354 
       
  3355 	/* Improve 2-pair detection performance */
       
  3356 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3357 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3358 	rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
       
  3359 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3360 
       
  3361 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3362 
       
  3363 	/* Modify green table for giga */
       
  3364 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3365 	rtl_writephy(tp, 0x05, 0x8b54);
       
  3366 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
       
  3367 	rtl_writephy(tp, 0x05, 0x8b5d);
       
  3368 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
       
  3369 	rtl_writephy(tp, 0x05, 0x8a7c);
       
  3370 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
       
  3371 	rtl_writephy(tp, 0x05, 0x8a7f);
       
  3372 	rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
       
  3373 	rtl_writephy(tp, 0x05, 0x8a82);
       
  3374 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
       
  3375 	rtl_writephy(tp, 0x05, 0x8a85);
       
  3376 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
       
  3377 	rtl_writephy(tp, 0x05, 0x8a88);
       
  3378 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
       
  3379 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3380 
       
  3381 	/* uc same-seed solution */
       
  3382 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3383 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3384 	rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
       
  3385 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3386 
       
  3387 	/* eee setting */
       
  3388 	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
       
  3389 	rtl_writephy(tp, 0x1f, 0x0005);
       
  3390 	rtl_writephy(tp, 0x05, 0x8b85);
       
  3391 	rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
       
  3392 	rtl_writephy(tp, 0x1f, 0x0004);
       
  3393 	rtl_writephy(tp, 0x1f, 0x0007);
       
  3394 	rtl_writephy(tp, 0x1e, 0x0020);
       
  3395 	rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
       
  3396 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3397 	rtl_writephy(tp, 0x0d, 0x0007);
       
  3398 	rtl_writephy(tp, 0x0e, 0x003c);
       
  3399 	rtl_writephy(tp, 0x0d, 0x4007);
       
  3400 	rtl_writephy(tp, 0x0e, 0x0000);
       
  3401 	rtl_writephy(tp, 0x0d, 0x0000);
       
  3402 
       
  3403 	/* Green feature */
       
  3404 	rtl_writephy(tp, 0x1f, 0x0003);
       
  3405 	rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
       
  3406 	rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
       
  3407 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3408 }
       
  3409 
       
  3410 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
       
  3411 {
       
  3412 	rtl_apply_firmware(tp);
       
  3413 
       
  3414 	rtl_writephy(tp, 0x1f, 0x0a46);
       
  3415 	if (rtl_readphy(tp, 0x10) & 0x0100) {
       
  3416 		rtl_writephy(tp, 0x1f, 0x0bcc);
       
  3417 		rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
       
  3418 	} else {
       
  3419 		rtl_writephy(tp, 0x1f, 0x0bcc);
       
  3420 		rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
       
  3421 	}
       
  3422 
       
  3423 	rtl_writephy(tp, 0x1f, 0x0a46);
       
  3424 	if (rtl_readphy(tp, 0x13) & 0x0100) {
       
  3425 		rtl_writephy(tp, 0x1f, 0x0c41);
       
  3426 		rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
       
  3427 	} else {
       
  3428 		rtl_writephy(tp, 0x1f, 0x0c41);
       
  3429 		rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
       
  3430 	}
       
  3431 
       
  3432 	/* Enable PHY auto speed down */
       
  3433 	rtl_writephy(tp, 0x1f, 0x0a44);
       
  3434 	rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
       
  3435 
       
  3436 	rtl_writephy(tp, 0x1f, 0x0bcc);
       
  3437 	rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
       
  3438 	rtl_writephy(tp, 0x1f, 0x0a44);
       
  3439 	rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
       
  3440 	rtl_writephy(tp, 0x1f, 0x0a43);
       
  3441 	rtl_writephy(tp, 0x13, 0x8084);
       
  3442 	rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
       
  3443 	rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
       
  3444 
       
  3445 	/* EEE auto-fallback function */
       
  3446 	rtl_writephy(tp, 0x1f, 0x0a4b);
       
  3447 	rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
       
  3448 
       
  3449 	/* Enable UC LPF tune function */
       
  3450 	rtl_writephy(tp, 0x1f, 0x0a43);
       
  3451 	rtl_writephy(tp, 0x13, 0x8012);
       
  3452 	rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
       
  3453 
       
  3454 	rtl_writephy(tp, 0x1f, 0x0c42);
       
  3455 	rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
       
  3456 
       
  3457 	/* Improve SWR Efficiency */
       
  3458 	rtl_writephy(tp, 0x1f, 0x0bcd);
       
  3459 	rtl_writephy(tp, 0x14, 0x5065);
       
  3460 	rtl_writephy(tp, 0x14, 0xd065);
       
  3461 	rtl_writephy(tp, 0x1f, 0x0bc8);
       
  3462 	rtl_writephy(tp, 0x11, 0x5655);
       
  3463 	rtl_writephy(tp, 0x1f, 0x0bcd);
       
  3464 	rtl_writephy(tp, 0x14, 0x1065);
       
  3465 	rtl_writephy(tp, 0x14, 0x9065);
       
  3466 	rtl_writephy(tp, 0x14, 0x1065);
       
  3467 
       
  3468 	/* Check ALDPS bit, disable it if enabled */
       
  3469 	rtl_writephy(tp, 0x1f, 0x0a43);
       
  3470 	if (rtl_readphy(tp, 0x10) & 0x0004)
       
  3471 		rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
       
  3472 
       
  3473 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3474 }
       
  3475 
       
  3476 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
       
  3477 {
       
  3478 	rtl_apply_firmware(tp);
       
  3479 }
       
  3480 
       
  3481 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
       
  3482 {
       
  3483 	static const struct phy_reg phy_reg_init[] = {
       
  3484 		{ 0x1f, 0x0003 },
       
  3485 		{ 0x08, 0x441d },
       
  3486 		{ 0x01, 0x9100 },
       
  3487 		{ 0x1f, 0x0000 }
       
  3488 	};
       
  3489 
       
  3490 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3491 	rtl_patchphy(tp, 0x11, 1 << 12);
       
  3492 	rtl_patchphy(tp, 0x19, 1 << 13);
       
  3493 	rtl_patchphy(tp, 0x10, 1 << 15);
       
  3494 
       
  3495 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3496 }
       
  3497 
       
  3498 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
       
  3499 {
       
  3500 	static const struct phy_reg phy_reg_init[] = {
       
  3501 		{ 0x1f, 0x0005 },
       
  3502 		{ 0x1a, 0x0000 },
       
  3503 		{ 0x1f, 0x0000 },
       
  3504 
       
  3505 		{ 0x1f, 0x0004 },
       
  3506 		{ 0x1c, 0x0000 },
       
  3507 		{ 0x1f, 0x0000 },
       
  3508 
       
  3509 		{ 0x1f, 0x0001 },
       
  3510 		{ 0x15, 0x7701 },
       
  3511 		{ 0x1f, 0x0000 }
       
  3512 	};
       
  3513 
       
  3514 	/* Disable ALDPS before ram code */
       
  3515 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3516 	rtl_writephy(tp, 0x18, 0x0310);
       
  3517 	msleep(100);
       
  3518 
       
  3519 	rtl_apply_firmware(tp);
       
  3520 
       
  3521 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3522 }
       
  3523 
       
  3524 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
       
  3525 {
       
  3526 	/* Disable ALDPS before setting firmware */
       
  3527 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3528 	rtl_writephy(tp, 0x18, 0x0310);
       
  3529 	msleep(20);
       
  3530 
       
  3531 	rtl_apply_firmware(tp);
       
  3532 
       
  3533 	/* EEE setting */
       
  3534 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  3535 	rtl_writephy(tp, 0x1f, 0x0004);
       
  3536 	rtl_writephy(tp, 0x10, 0x401f);
       
  3537 	rtl_writephy(tp, 0x19, 0x7030);
       
  3538 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3539 }
       
  3540 
       
  3541 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
       
  3542 {
       
  3543 	static const struct phy_reg phy_reg_init[] = {
       
  3544 		{ 0x1f, 0x0004 },
       
  3545 		{ 0x10, 0xc07f },
       
  3546 		{ 0x19, 0x7030 },
       
  3547 		{ 0x1f, 0x0000 }
       
  3548 	};
       
  3549 
       
  3550 	/* Disable ALDPS before ram code */
       
  3551 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3552 	rtl_writephy(tp, 0x18, 0x0310);
       
  3553 	msleep(100);
       
  3554 
       
  3555 	rtl_apply_firmware(tp);
       
  3556 
       
  3557 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  3558 	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
       
  3559 
       
  3560 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  3561 }
       
  3562 
       
  3563 static void rtl_hw_phy_config(struct net_device *dev)
       
  3564 {
       
  3565 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3566 
       
  3567 	rtl8169_print_mac_version(tp);
       
  3568 
       
  3569 	switch (tp->mac_version) {
       
  3570 	case RTL_GIGA_MAC_VER_01:
       
  3571 		break;
       
  3572 	case RTL_GIGA_MAC_VER_02:
       
  3573 	case RTL_GIGA_MAC_VER_03:
       
  3574 		rtl8169s_hw_phy_config(tp);
       
  3575 		break;
       
  3576 	case RTL_GIGA_MAC_VER_04:
       
  3577 		rtl8169sb_hw_phy_config(tp);
       
  3578 		break;
       
  3579 	case RTL_GIGA_MAC_VER_05:
       
  3580 		rtl8169scd_hw_phy_config(tp);
       
  3581 		break;
       
  3582 	case RTL_GIGA_MAC_VER_06:
       
  3583 		rtl8169sce_hw_phy_config(tp);
       
  3584 		break;
       
  3585 	case RTL_GIGA_MAC_VER_07:
       
  3586 	case RTL_GIGA_MAC_VER_08:
       
  3587 	case RTL_GIGA_MAC_VER_09:
       
  3588 		rtl8102e_hw_phy_config(tp);
       
  3589 		break;
       
  3590 	case RTL_GIGA_MAC_VER_11:
       
  3591 		rtl8168bb_hw_phy_config(tp);
       
  3592 		break;
       
  3593 	case RTL_GIGA_MAC_VER_12:
       
  3594 		rtl8168bef_hw_phy_config(tp);
       
  3595 		break;
       
  3596 	case RTL_GIGA_MAC_VER_17:
       
  3597 		rtl8168bef_hw_phy_config(tp);
       
  3598 		break;
       
  3599 	case RTL_GIGA_MAC_VER_18:
       
  3600 		rtl8168cp_1_hw_phy_config(tp);
       
  3601 		break;
       
  3602 	case RTL_GIGA_MAC_VER_19:
       
  3603 		rtl8168c_1_hw_phy_config(tp);
       
  3604 		break;
       
  3605 	case RTL_GIGA_MAC_VER_20:
       
  3606 		rtl8168c_2_hw_phy_config(tp);
       
  3607 		break;
       
  3608 	case RTL_GIGA_MAC_VER_21:
       
  3609 		rtl8168c_3_hw_phy_config(tp);
       
  3610 		break;
       
  3611 	case RTL_GIGA_MAC_VER_22:
       
  3612 		rtl8168c_4_hw_phy_config(tp);
       
  3613 		break;
       
  3614 	case RTL_GIGA_MAC_VER_23:
       
  3615 	case RTL_GIGA_MAC_VER_24:
       
  3616 		rtl8168cp_2_hw_phy_config(tp);
       
  3617 		break;
       
  3618 	case RTL_GIGA_MAC_VER_25:
       
  3619 		rtl8168d_1_hw_phy_config(tp);
       
  3620 		break;
       
  3621 	case RTL_GIGA_MAC_VER_26:
       
  3622 		rtl8168d_2_hw_phy_config(tp);
       
  3623 		break;
       
  3624 	case RTL_GIGA_MAC_VER_27:
       
  3625 		rtl8168d_3_hw_phy_config(tp);
       
  3626 		break;
       
  3627 	case RTL_GIGA_MAC_VER_28:
       
  3628 		rtl8168d_4_hw_phy_config(tp);
       
  3629 		break;
       
  3630 	case RTL_GIGA_MAC_VER_29:
       
  3631 	case RTL_GIGA_MAC_VER_30:
       
  3632 		rtl8105e_hw_phy_config(tp);
       
  3633 		break;
       
  3634 	case RTL_GIGA_MAC_VER_31:
       
  3635 		/* None. */
       
  3636 		break;
       
  3637 	case RTL_GIGA_MAC_VER_32:
       
  3638 	case RTL_GIGA_MAC_VER_33:
       
  3639 		rtl8168e_1_hw_phy_config(tp);
       
  3640 		break;
       
  3641 	case RTL_GIGA_MAC_VER_34:
       
  3642 		rtl8168e_2_hw_phy_config(tp);
       
  3643 		break;
       
  3644 	case RTL_GIGA_MAC_VER_35:
       
  3645 		rtl8168f_1_hw_phy_config(tp);
       
  3646 		break;
       
  3647 	case RTL_GIGA_MAC_VER_36:
       
  3648 		rtl8168f_2_hw_phy_config(tp);
       
  3649 		break;
       
  3650 
       
  3651 	case RTL_GIGA_MAC_VER_37:
       
  3652 		rtl8402_hw_phy_config(tp);
       
  3653 		break;
       
  3654 
       
  3655 	case RTL_GIGA_MAC_VER_38:
       
  3656 		rtl8411_hw_phy_config(tp);
       
  3657 		break;
       
  3658 
       
  3659 	case RTL_GIGA_MAC_VER_39:
       
  3660 		rtl8106e_hw_phy_config(tp);
       
  3661 		break;
       
  3662 
       
  3663 	case RTL_GIGA_MAC_VER_40:
       
  3664 		rtl8168g_1_hw_phy_config(tp);
       
  3665 		break;
       
  3666 	case RTL_GIGA_MAC_VER_42:
       
  3667 	case RTL_GIGA_MAC_VER_43:
       
  3668 	case RTL_GIGA_MAC_VER_44:
       
  3669 		rtl8168g_2_hw_phy_config(tp);
       
  3670 		break;
       
  3671 
       
  3672 	case RTL_GIGA_MAC_VER_41:
       
  3673 	default:
       
  3674 		break;
       
  3675 	}
       
  3676 }
       
  3677 
       
  3678 static void rtl_phy_work(struct rtl8169_private *tp)
       
  3679 {
       
  3680 	struct timer_list *timer = &tp->timer;
       
  3681 	void __iomem *ioaddr = tp->mmio_addr;
       
  3682 	unsigned long timeout = RTL8169_PHY_TIMEOUT;
       
  3683 
       
  3684 	assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
       
  3685 
       
  3686 	if (tp->phy_reset_pending(tp)) {
       
  3687 		/*
       
  3688 		 * A busy loop could burn quite a few cycles on nowadays CPU.
       
  3689 		 * Let's delay the execution of the timer for a few ticks.
       
  3690 		 */
       
  3691 		timeout = HZ/10;
       
  3692 		goto out_mod_timer;
       
  3693 	}
       
  3694 
       
  3695 	if (tp->link_ok(ioaddr))
       
  3696 		return;
       
  3697 
       
  3698 	netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
       
  3699 
       
  3700 	tp->phy_reset_enable(tp);
       
  3701 
       
  3702 out_mod_timer:
       
  3703 	mod_timer(timer, jiffies + timeout);
       
  3704 }
       
  3705 
       
  3706 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
       
  3707 {
       
  3708 	if (!test_and_set_bit(flag, tp->wk.flags))
       
  3709 		schedule_work(&tp->wk.work);
       
  3710 }
       
  3711 
       
  3712 static void rtl8169_phy_timer(unsigned long __opaque)
       
  3713 {
       
  3714 	struct net_device *dev = (struct net_device *)__opaque;
       
  3715 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3716 
       
  3717 	rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
       
  3718 }
       
  3719 
       
  3720 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
       
  3721 				  void __iomem *ioaddr)
       
  3722 {
       
  3723 	iounmap(ioaddr);
       
  3724 	pci_release_regions(pdev);
       
  3725 	pci_clear_mwi(pdev);
       
  3726 	pci_disable_device(pdev);
       
  3727 	free_netdev(dev);
       
  3728 }
       
  3729 
       
  3730 DECLARE_RTL_COND(rtl_phy_reset_cond)
       
  3731 {
       
  3732 	return tp->phy_reset_pending(tp);
       
  3733 }
       
  3734 
       
  3735 static void rtl8169_phy_reset(struct net_device *dev,
       
  3736 			      struct rtl8169_private *tp)
       
  3737 {
       
  3738 	tp->phy_reset_enable(tp);
       
  3739 	rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
       
  3740 }
       
  3741 
       
  3742 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
       
  3743 {
       
  3744 	void __iomem *ioaddr = tp->mmio_addr;
       
  3745 
       
  3746 	return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
       
  3747 	    (RTL_R8(PHYstatus) & TBI_Enable);
       
  3748 }
       
  3749 
       
  3750 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
       
  3751 {
       
  3752 	void __iomem *ioaddr = tp->mmio_addr;
       
  3753 
       
  3754 	rtl_hw_phy_config(dev);
       
  3755 
       
  3756 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
       
  3757 		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
       
  3758 		RTL_W8(0x82, 0x01);
       
  3759 	}
       
  3760 
       
  3761 	pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
       
  3762 
       
  3763 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
       
  3764 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
       
  3765 
       
  3766 	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
       
  3767 		dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
       
  3768 		RTL_W8(0x82, 0x01);
       
  3769 		dprintk("Set PHY Reg 0x0bh = 0x00h\n");
       
  3770 		rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
       
  3771 	}
       
  3772 
       
  3773 	rtl8169_phy_reset(dev, tp);
       
  3774 
       
  3775 	rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
       
  3776 			  ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
       
  3777 			  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
       
  3778 			  (tp->mii.supports_gmii ?
       
  3779 			   ADVERTISED_1000baseT_Half |
       
  3780 			   ADVERTISED_1000baseT_Full : 0));
       
  3781 
       
  3782 	if (rtl_tbi_enabled(tp))
       
  3783 		netif_info(tp, link, dev, "TBI auto-negotiating\n");
       
  3784 }
       
  3785 
       
  3786 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
       
  3787 {
       
  3788 	void __iomem *ioaddr = tp->mmio_addr;
       
  3789 
       
  3790 	rtl_lock_work(tp);
       
  3791 
       
  3792 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  3793 
       
  3794 	RTL_W32(MAC4, addr[4] | addr[5] << 8);
       
  3795 	RTL_R32(MAC4);
       
  3796 
       
  3797 	RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
       
  3798 	RTL_R32(MAC0);
       
  3799 
       
  3800 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)
       
  3801 		rtl_rar_exgmac_set(tp, addr);
       
  3802 
       
  3803 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  3804 
       
  3805 	rtl_unlock_work(tp);
       
  3806 }
       
  3807 
       
  3808 static int rtl_set_mac_address(struct net_device *dev, void *p)
       
  3809 {
       
  3810 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3811 	struct sockaddr *addr = p;
       
  3812 
       
  3813 	if (!is_valid_ether_addr(addr->sa_data))
       
  3814 		return -EADDRNOTAVAIL;
       
  3815 
       
  3816 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
       
  3817 
       
  3818 	rtl_rar_set(tp, dev->dev_addr);
       
  3819 
       
  3820 	return 0;
       
  3821 }
       
  3822 
       
  3823 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
       
  3824 {
       
  3825 	struct rtl8169_private *tp = netdev_priv(dev);
       
  3826 	struct mii_ioctl_data *data = if_mii(ifr);
       
  3827 
       
  3828 	return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
       
  3829 }
       
  3830 
       
  3831 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
       
  3832 			  struct mii_ioctl_data *data, int cmd)
       
  3833 {
       
  3834 	switch (cmd) {
       
  3835 	case SIOCGMIIPHY:
       
  3836 		data->phy_id = 32; /* Internal PHY */
       
  3837 		return 0;
       
  3838 
       
  3839 	case SIOCGMIIREG:
       
  3840 		data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
       
  3841 		return 0;
       
  3842 
       
  3843 	case SIOCSMIIREG:
       
  3844 		rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
       
  3845 		return 0;
       
  3846 	}
       
  3847 	return -EOPNOTSUPP;
       
  3848 }
       
  3849 
       
  3850 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
       
  3851 {
       
  3852 	return -EOPNOTSUPP;
       
  3853 }
       
  3854 
       
  3855 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
       
  3856 {
       
  3857 	if (tp->features & RTL_FEATURE_MSI) {
       
  3858 		pci_disable_msi(pdev);
       
  3859 		tp->features &= ~RTL_FEATURE_MSI;
       
  3860 	}
       
  3861 }
       
  3862 
       
  3863 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
       
  3864 {
       
  3865 	struct mdio_ops *ops = &tp->mdio_ops;
       
  3866 
       
  3867 	switch (tp->mac_version) {
       
  3868 	case RTL_GIGA_MAC_VER_27:
       
  3869 		ops->write	= r8168dp_1_mdio_write;
       
  3870 		ops->read	= r8168dp_1_mdio_read;
       
  3871 		break;
       
  3872 	case RTL_GIGA_MAC_VER_28:
       
  3873 	case RTL_GIGA_MAC_VER_31:
       
  3874 		ops->write	= r8168dp_2_mdio_write;
       
  3875 		ops->read	= r8168dp_2_mdio_read;
       
  3876 		break;
       
  3877 	case RTL_GIGA_MAC_VER_40:
       
  3878 	case RTL_GIGA_MAC_VER_41:
       
  3879 	case RTL_GIGA_MAC_VER_42:
       
  3880 	case RTL_GIGA_MAC_VER_43:
       
  3881 	case RTL_GIGA_MAC_VER_44:
       
  3882 		ops->write	= r8168g_mdio_write;
       
  3883 		ops->read	= r8168g_mdio_read;
       
  3884 		break;
       
  3885 	default:
       
  3886 		ops->write	= r8169_mdio_write;
       
  3887 		ops->read	= r8169_mdio_read;
       
  3888 		break;
       
  3889 	}
       
  3890 }
       
  3891 
       
  3892 static void rtl_speed_down(struct rtl8169_private *tp)
       
  3893 {
       
  3894 	u32 adv;
       
  3895 	int lpa;
       
  3896 
       
  3897 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3898 	lpa = rtl_readphy(tp, MII_LPA);
       
  3899 
       
  3900 	if (lpa & (LPA_10HALF | LPA_10FULL))
       
  3901 		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
       
  3902 	else if (lpa & (LPA_100HALF | LPA_100FULL))
       
  3903 		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
       
  3904 		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
       
  3905 	else
       
  3906 		adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
       
  3907 		      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
       
  3908 		      (tp->mii.supports_gmii ?
       
  3909 		       ADVERTISED_1000baseT_Half |
       
  3910 		       ADVERTISED_1000baseT_Full : 0);
       
  3911 
       
  3912 	rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
       
  3913 			  adv);
       
  3914 }
       
  3915 
       
  3916 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
       
  3917 {
       
  3918 	void __iomem *ioaddr = tp->mmio_addr;
       
  3919 
       
  3920 	switch (tp->mac_version) {
       
  3921 	case RTL_GIGA_MAC_VER_25:
       
  3922 	case RTL_GIGA_MAC_VER_26:
       
  3923 	case RTL_GIGA_MAC_VER_29:
       
  3924 	case RTL_GIGA_MAC_VER_30:
       
  3925 	case RTL_GIGA_MAC_VER_32:
       
  3926 	case RTL_GIGA_MAC_VER_33:
       
  3927 	case RTL_GIGA_MAC_VER_34:
       
  3928 	case RTL_GIGA_MAC_VER_37:
       
  3929 	case RTL_GIGA_MAC_VER_38:
       
  3930 	case RTL_GIGA_MAC_VER_39:
       
  3931 	case RTL_GIGA_MAC_VER_40:
       
  3932 	case RTL_GIGA_MAC_VER_41:
       
  3933 	case RTL_GIGA_MAC_VER_42:
       
  3934 	case RTL_GIGA_MAC_VER_43:
       
  3935 	case RTL_GIGA_MAC_VER_44:
       
  3936 		RTL_W32(RxConfig, RTL_R32(RxConfig) |
       
  3937 			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
       
  3938 		break;
       
  3939 	default:
       
  3940 		break;
       
  3941 	}
       
  3942 }
       
  3943 
       
  3944 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
       
  3945 {
       
  3946 	if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
       
  3947 		return false;
       
  3948 
       
  3949 	rtl_speed_down(tp);
       
  3950 	rtl_wol_suspend_quirk(tp);
       
  3951 
       
  3952 	return true;
       
  3953 }
       
  3954 
       
  3955 static void r810x_phy_power_down(struct rtl8169_private *tp)
       
  3956 {
       
  3957 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3958 	rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
       
  3959 }
       
  3960 
       
  3961 static void r810x_phy_power_up(struct rtl8169_private *tp)
       
  3962 {
       
  3963 	rtl_writephy(tp, 0x1f, 0x0000);
       
  3964 	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
       
  3965 }
       
  3966 
       
  3967 static void r810x_pll_power_down(struct rtl8169_private *tp)
       
  3968 {
       
  3969 	void __iomem *ioaddr = tp->mmio_addr;
       
  3970 
       
  3971 	if (rtl_wol_pll_power_down(tp))
       
  3972 		return;
       
  3973 
       
  3974 	r810x_phy_power_down(tp);
       
  3975 
       
  3976 	switch (tp->mac_version) {
       
  3977 	case RTL_GIGA_MAC_VER_07:
       
  3978 	case RTL_GIGA_MAC_VER_08:
       
  3979 	case RTL_GIGA_MAC_VER_09:
       
  3980 	case RTL_GIGA_MAC_VER_10:
       
  3981 	case RTL_GIGA_MAC_VER_13:
       
  3982 	case RTL_GIGA_MAC_VER_16:
       
  3983 		break;
       
  3984 	default:
       
  3985 		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
       
  3986 		break;
       
  3987 	}
       
  3988 }
       
  3989 
       
  3990 static void r810x_pll_power_up(struct rtl8169_private *tp)
       
  3991 {
       
  3992 	void __iomem *ioaddr = tp->mmio_addr;
       
  3993 
       
  3994 	r810x_phy_power_up(tp);
       
  3995 
       
  3996 	switch (tp->mac_version) {
       
  3997 	case RTL_GIGA_MAC_VER_07:
       
  3998 	case RTL_GIGA_MAC_VER_08:
       
  3999 	case RTL_GIGA_MAC_VER_09:
       
  4000 	case RTL_GIGA_MAC_VER_10:
       
  4001 	case RTL_GIGA_MAC_VER_13:
       
  4002 	case RTL_GIGA_MAC_VER_16:
       
  4003 		break;
       
  4004 	default:
       
  4005 		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
       
  4006 		break;
       
  4007 	}
       
  4008 }
       
  4009 
       
  4010 static void r8168_phy_power_up(struct rtl8169_private *tp)
       
  4011 {
       
  4012 	rtl_writephy(tp, 0x1f, 0x0000);
       
  4013 	switch (tp->mac_version) {
       
  4014 	case RTL_GIGA_MAC_VER_11:
       
  4015 	case RTL_GIGA_MAC_VER_12:
       
  4016 	case RTL_GIGA_MAC_VER_17:
       
  4017 	case RTL_GIGA_MAC_VER_18:
       
  4018 	case RTL_GIGA_MAC_VER_19:
       
  4019 	case RTL_GIGA_MAC_VER_20:
       
  4020 	case RTL_GIGA_MAC_VER_21:
       
  4021 	case RTL_GIGA_MAC_VER_22:
       
  4022 	case RTL_GIGA_MAC_VER_23:
       
  4023 	case RTL_GIGA_MAC_VER_24:
       
  4024 	case RTL_GIGA_MAC_VER_25:
       
  4025 	case RTL_GIGA_MAC_VER_26:
       
  4026 	case RTL_GIGA_MAC_VER_27:
       
  4027 	case RTL_GIGA_MAC_VER_28:
       
  4028 	case RTL_GIGA_MAC_VER_31:
       
  4029 		rtl_writephy(tp, 0x0e, 0x0000);
       
  4030 		break;
       
  4031 	default:
       
  4032 		break;
       
  4033 	}
       
  4034 	rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
       
  4035 }
       
  4036 
       
  4037 static void r8168_phy_power_down(struct rtl8169_private *tp)
       
  4038 {
       
  4039 	rtl_writephy(tp, 0x1f, 0x0000);
       
  4040 	switch (tp->mac_version) {
       
  4041 	case RTL_GIGA_MAC_VER_32:
       
  4042 	case RTL_GIGA_MAC_VER_33:
       
  4043 	case RTL_GIGA_MAC_VER_40:
       
  4044 	case RTL_GIGA_MAC_VER_41:
       
  4045 		rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
       
  4046 		break;
       
  4047 
       
  4048 	case RTL_GIGA_MAC_VER_11:
       
  4049 	case RTL_GIGA_MAC_VER_12:
       
  4050 	case RTL_GIGA_MAC_VER_17:
       
  4051 	case RTL_GIGA_MAC_VER_18:
       
  4052 	case RTL_GIGA_MAC_VER_19:
       
  4053 	case RTL_GIGA_MAC_VER_20:
       
  4054 	case RTL_GIGA_MAC_VER_21:
       
  4055 	case RTL_GIGA_MAC_VER_22:
       
  4056 	case RTL_GIGA_MAC_VER_23:
       
  4057 	case RTL_GIGA_MAC_VER_24:
       
  4058 	case RTL_GIGA_MAC_VER_25:
       
  4059 	case RTL_GIGA_MAC_VER_26:
       
  4060 	case RTL_GIGA_MAC_VER_27:
       
  4061 	case RTL_GIGA_MAC_VER_28:
       
  4062 	case RTL_GIGA_MAC_VER_31:
       
  4063 		rtl_writephy(tp, 0x0e, 0x0200);
       
  4064 	default:
       
  4065 		rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
       
  4066 		break;
       
  4067 	}
       
  4068 }
       
  4069 
       
  4070 static void r8168_pll_power_down(struct rtl8169_private *tp)
       
  4071 {
       
  4072 	void __iomem *ioaddr = tp->mmio_addr;
       
  4073 
       
  4074 	if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
       
  4075 	     tp->mac_version == RTL_GIGA_MAC_VER_28 ||
       
  4076 	     tp->mac_version == RTL_GIGA_MAC_VER_31) &&
       
  4077 	    r8168dp_check_dash(tp)) {
       
  4078 		return;
       
  4079 	}
       
  4080 
       
  4081 	if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
       
  4082 	     tp->mac_version == RTL_GIGA_MAC_VER_24) &&
       
  4083 	    (RTL_R16(CPlusCmd) & ASF)) {
       
  4084 		return;
       
  4085 	}
       
  4086 
       
  4087 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
       
  4088 	    tp->mac_version == RTL_GIGA_MAC_VER_33)
       
  4089 		rtl_ephy_write(tp, 0x19, 0xff64);
       
  4090 
       
  4091 	if (rtl_wol_pll_power_down(tp))
       
  4092 		return;
       
  4093 
       
  4094 	r8168_phy_power_down(tp);
       
  4095 
       
  4096 	switch (tp->mac_version) {
       
  4097 	case RTL_GIGA_MAC_VER_25:
       
  4098 	case RTL_GIGA_MAC_VER_26:
       
  4099 	case RTL_GIGA_MAC_VER_27:
       
  4100 	case RTL_GIGA_MAC_VER_28:
       
  4101 	case RTL_GIGA_MAC_VER_31:
       
  4102 	case RTL_GIGA_MAC_VER_32:
       
  4103 	case RTL_GIGA_MAC_VER_33:
       
  4104 		RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
       
  4105 		break;
       
  4106 	case RTL_GIGA_MAC_VER_40:
       
  4107 	case RTL_GIGA_MAC_VER_41:
       
  4108 		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
       
  4109 			     0xfc000000, ERIAR_EXGMAC);
       
  4110 		break;
       
  4111 	}
       
  4112 }
       
  4113 
       
  4114 static void r8168_pll_power_up(struct rtl8169_private *tp)
       
  4115 {
       
  4116 	void __iomem *ioaddr = tp->mmio_addr;
       
  4117 
       
  4118 	switch (tp->mac_version) {
       
  4119 	case RTL_GIGA_MAC_VER_25:
       
  4120 	case RTL_GIGA_MAC_VER_26:
       
  4121 	case RTL_GIGA_MAC_VER_27:
       
  4122 	case RTL_GIGA_MAC_VER_28:
       
  4123 	case RTL_GIGA_MAC_VER_31:
       
  4124 	case RTL_GIGA_MAC_VER_32:
       
  4125 	case RTL_GIGA_MAC_VER_33:
       
  4126 		RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
       
  4127 		break;
       
  4128 	case RTL_GIGA_MAC_VER_40:
       
  4129 	case RTL_GIGA_MAC_VER_41:
       
  4130 		rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
       
  4131 			     0x00000000, ERIAR_EXGMAC);
       
  4132 		break;
       
  4133 	}
       
  4134 
       
  4135 	r8168_phy_power_up(tp);
       
  4136 }
       
  4137 
       
  4138 static void rtl_generic_op(struct rtl8169_private *tp,
       
  4139 			   void (*op)(struct rtl8169_private *))
       
  4140 {
       
  4141 	if (op)
       
  4142 		op(tp);
       
  4143 }
       
  4144 
       
  4145 static void rtl_pll_power_down(struct rtl8169_private *tp)
       
  4146 {
       
  4147 	rtl_generic_op(tp, tp->pll_power_ops.down);
       
  4148 }
       
  4149 
       
  4150 static void rtl_pll_power_up(struct rtl8169_private *tp)
       
  4151 {
       
  4152 	rtl_generic_op(tp, tp->pll_power_ops.up);
       
  4153 }
       
  4154 
       
  4155 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
       
  4156 {
       
  4157 	struct pll_power_ops *ops = &tp->pll_power_ops;
       
  4158 
       
  4159 	switch (tp->mac_version) {
       
  4160 	case RTL_GIGA_MAC_VER_07:
       
  4161 	case RTL_GIGA_MAC_VER_08:
       
  4162 	case RTL_GIGA_MAC_VER_09:
       
  4163 	case RTL_GIGA_MAC_VER_10:
       
  4164 	case RTL_GIGA_MAC_VER_16:
       
  4165 	case RTL_GIGA_MAC_VER_29:
       
  4166 	case RTL_GIGA_MAC_VER_30:
       
  4167 	case RTL_GIGA_MAC_VER_37:
       
  4168 	case RTL_GIGA_MAC_VER_39:
       
  4169 	case RTL_GIGA_MAC_VER_43:
       
  4170 		ops->down	= r810x_pll_power_down;
       
  4171 		ops->up		= r810x_pll_power_up;
       
  4172 		break;
       
  4173 
       
  4174 	case RTL_GIGA_MAC_VER_11:
       
  4175 	case RTL_GIGA_MAC_VER_12:
       
  4176 	case RTL_GIGA_MAC_VER_17:
       
  4177 	case RTL_GIGA_MAC_VER_18:
       
  4178 	case RTL_GIGA_MAC_VER_19:
       
  4179 	case RTL_GIGA_MAC_VER_20:
       
  4180 	case RTL_GIGA_MAC_VER_21:
       
  4181 	case RTL_GIGA_MAC_VER_22:
       
  4182 	case RTL_GIGA_MAC_VER_23:
       
  4183 	case RTL_GIGA_MAC_VER_24:
       
  4184 	case RTL_GIGA_MAC_VER_25:
       
  4185 	case RTL_GIGA_MAC_VER_26:
       
  4186 	case RTL_GIGA_MAC_VER_27:
       
  4187 	case RTL_GIGA_MAC_VER_28:
       
  4188 	case RTL_GIGA_MAC_VER_31:
       
  4189 	case RTL_GIGA_MAC_VER_32:
       
  4190 	case RTL_GIGA_MAC_VER_33:
       
  4191 	case RTL_GIGA_MAC_VER_34:
       
  4192 	case RTL_GIGA_MAC_VER_35:
       
  4193 	case RTL_GIGA_MAC_VER_36:
       
  4194 	case RTL_GIGA_MAC_VER_38:
       
  4195 	case RTL_GIGA_MAC_VER_40:
       
  4196 	case RTL_GIGA_MAC_VER_41:
       
  4197 	case RTL_GIGA_MAC_VER_42:
       
  4198 	case RTL_GIGA_MAC_VER_44:
       
  4199 		ops->down	= r8168_pll_power_down;
       
  4200 		ops->up		= r8168_pll_power_up;
       
  4201 		break;
       
  4202 
       
  4203 	default:
       
  4204 		ops->down	= NULL;
       
  4205 		ops->up		= NULL;
       
  4206 		break;
       
  4207 	}
       
  4208 }
       
  4209 
       
  4210 static void rtl_init_rxcfg(struct rtl8169_private *tp)
       
  4211 {
       
  4212 	void __iomem *ioaddr = tp->mmio_addr;
       
  4213 
       
  4214 	switch (tp->mac_version) {
       
  4215 	case RTL_GIGA_MAC_VER_01:
       
  4216 	case RTL_GIGA_MAC_VER_02:
       
  4217 	case RTL_GIGA_MAC_VER_03:
       
  4218 	case RTL_GIGA_MAC_VER_04:
       
  4219 	case RTL_GIGA_MAC_VER_05:
       
  4220 	case RTL_GIGA_MAC_VER_06:
       
  4221 	case RTL_GIGA_MAC_VER_10:
       
  4222 	case RTL_GIGA_MAC_VER_11:
       
  4223 	case RTL_GIGA_MAC_VER_12:
       
  4224 	case RTL_GIGA_MAC_VER_13:
       
  4225 	case RTL_GIGA_MAC_VER_14:
       
  4226 	case RTL_GIGA_MAC_VER_15:
       
  4227 	case RTL_GIGA_MAC_VER_16:
       
  4228 	case RTL_GIGA_MAC_VER_17:
       
  4229 		RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
       
  4230 		break;
       
  4231 	case RTL_GIGA_MAC_VER_18:
       
  4232 	case RTL_GIGA_MAC_VER_19:
       
  4233 	case RTL_GIGA_MAC_VER_20:
       
  4234 	case RTL_GIGA_MAC_VER_21:
       
  4235 	case RTL_GIGA_MAC_VER_22:
       
  4236 	case RTL_GIGA_MAC_VER_23:
       
  4237 	case RTL_GIGA_MAC_VER_24:
       
  4238 	case RTL_GIGA_MAC_VER_34:
       
  4239 	case RTL_GIGA_MAC_VER_35:
       
  4240 		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
       
  4241 		break;
       
  4242 	case RTL_GIGA_MAC_VER_40:
       
  4243 		RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
       
  4244 		break;
       
  4245 	case RTL_GIGA_MAC_VER_41:
       
  4246 	case RTL_GIGA_MAC_VER_42:
       
  4247 	case RTL_GIGA_MAC_VER_43:
       
  4248 	case RTL_GIGA_MAC_VER_44:
       
  4249 		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
       
  4250 		break;
       
  4251 	default:
       
  4252 		RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
       
  4253 		break;
       
  4254 	}
       
  4255 }
       
  4256 
       
  4257 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
       
  4258 {
       
  4259 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
       
  4260 }
       
  4261 
       
  4262 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4263 {
       
  4264 	void __iomem *ioaddr = tp->mmio_addr;
       
  4265 
       
  4266 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  4267 	rtl_generic_op(tp, tp->jumbo_ops.enable);
       
  4268 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  4269 }
       
  4270 
       
  4271 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4272 {
       
  4273 	void __iomem *ioaddr = tp->mmio_addr;
       
  4274 
       
  4275 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  4276 	rtl_generic_op(tp, tp->jumbo_ops.disable);
       
  4277 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  4278 }
       
  4279 
       
  4280 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4281 {
       
  4282 	void __iomem *ioaddr = tp->mmio_addr;
       
  4283 
       
  4284 	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
       
  4285 	RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
       
  4286 	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
       
  4287 }
       
  4288 
       
  4289 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4290 {
       
  4291 	void __iomem *ioaddr = tp->mmio_addr;
       
  4292 
       
  4293 	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
       
  4294 	RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
       
  4295 	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  4296 }
       
  4297 
       
  4298 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4299 {
       
  4300 	void __iomem *ioaddr = tp->mmio_addr;
       
  4301 
       
  4302 	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
       
  4303 }
       
  4304 
       
  4305 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4306 {
       
  4307 	void __iomem *ioaddr = tp->mmio_addr;
       
  4308 
       
  4309 	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
       
  4310 }
       
  4311 
       
  4312 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4313 {
       
  4314 	void __iomem *ioaddr = tp->mmio_addr;
       
  4315 
       
  4316 	RTL_W8(MaxTxPacketSize, 0x3f);
       
  4317 	RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
       
  4318 	RTL_W8(Config4, RTL_R8(Config4) | 0x01);
       
  4319 	rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
       
  4320 }
       
  4321 
       
  4322 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4323 {
       
  4324 	void __iomem *ioaddr = tp->mmio_addr;
       
  4325 
       
  4326 	RTL_W8(MaxTxPacketSize, 0x0c);
       
  4327 	RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
       
  4328 	RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
       
  4329 	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  4330 }
       
  4331 
       
  4332 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4333 {
       
  4334 	rtl_tx_performance_tweak(tp->pci_dev,
       
  4335 		(0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  4336 }
       
  4337 
       
  4338 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4339 {
       
  4340 	rtl_tx_performance_tweak(tp->pci_dev,
       
  4341 		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  4342 }
       
  4343 
       
  4344 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
       
  4345 {
       
  4346 	void __iomem *ioaddr = tp->mmio_addr;
       
  4347 
       
  4348 	r8168b_0_hw_jumbo_enable(tp);
       
  4349 
       
  4350 	RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
       
  4351 }
       
  4352 
       
  4353 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
       
  4354 {
       
  4355 	void __iomem *ioaddr = tp->mmio_addr;
       
  4356 
       
  4357 	r8168b_0_hw_jumbo_disable(tp);
       
  4358 
       
  4359 	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
       
  4360 }
       
  4361 
       
  4362 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
       
  4363 {
       
  4364 	struct jumbo_ops *ops = &tp->jumbo_ops;
       
  4365 
       
  4366 	switch (tp->mac_version) {
       
  4367 	case RTL_GIGA_MAC_VER_11:
       
  4368 		ops->disable	= r8168b_0_hw_jumbo_disable;
       
  4369 		ops->enable	= r8168b_0_hw_jumbo_enable;
       
  4370 		break;
       
  4371 	case RTL_GIGA_MAC_VER_12:
       
  4372 	case RTL_GIGA_MAC_VER_17:
       
  4373 		ops->disable	= r8168b_1_hw_jumbo_disable;
       
  4374 		ops->enable	= r8168b_1_hw_jumbo_enable;
       
  4375 		break;
       
  4376 	case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
       
  4377 	case RTL_GIGA_MAC_VER_19:
       
  4378 	case RTL_GIGA_MAC_VER_20:
       
  4379 	case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
       
  4380 	case RTL_GIGA_MAC_VER_22:
       
  4381 	case RTL_GIGA_MAC_VER_23:
       
  4382 	case RTL_GIGA_MAC_VER_24:
       
  4383 	case RTL_GIGA_MAC_VER_25:
       
  4384 	case RTL_GIGA_MAC_VER_26:
       
  4385 		ops->disable	= r8168c_hw_jumbo_disable;
       
  4386 		ops->enable	= r8168c_hw_jumbo_enable;
       
  4387 		break;
       
  4388 	case RTL_GIGA_MAC_VER_27:
       
  4389 	case RTL_GIGA_MAC_VER_28:
       
  4390 		ops->disable	= r8168dp_hw_jumbo_disable;
       
  4391 		ops->enable	= r8168dp_hw_jumbo_enable;
       
  4392 		break;
       
  4393 	case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
       
  4394 	case RTL_GIGA_MAC_VER_32:
       
  4395 	case RTL_GIGA_MAC_VER_33:
       
  4396 	case RTL_GIGA_MAC_VER_34:
       
  4397 		ops->disable	= r8168e_hw_jumbo_disable;
       
  4398 		ops->enable	= r8168e_hw_jumbo_enable;
       
  4399 		break;
       
  4400 
       
  4401 	/*
       
  4402 	 * No action needed for jumbo frames with 8169.
       
  4403 	 * No jumbo for 810x at all.
       
  4404 	 */
       
  4405 	case RTL_GIGA_MAC_VER_40:
       
  4406 	case RTL_GIGA_MAC_VER_41:
       
  4407 	case RTL_GIGA_MAC_VER_42:
       
  4408 	case RTL_GIGA_MAC_VER_43:
       
  4409 	case RTL_GIGA_MAC_VER_44:
       
  4410 	default:
       
  4411 		ops->disable	= NULL;
       
  4412 		ops->enable	= NULL;
       
  4413 		break;
       
  4414 	}
       
  4415 }
       
  4416 
       
  4417 DECLARE_RTL_COND(rtl_chipcmd_cond)
       
  4418 {
       
  4419 	void __iomem *ioaddr = tp->mmio_addr;
       
  4420 
       
  4421 	return RTL_R8(ChipCmd) & CmdReset;
       
  4422 }
       
  4423 
       
  4424 static void rtl_hw_reset(struct rtl8169_private *tp)
       
  4425 {
       
  4426 	void __iomem *ioaddr = tp->mmio_addr;
       
  4427 
       
  4428 	RTL_W8(ChipCmd, CmdReset);
       
  4429 
       
  4430 	rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
       
  4431 }
       
  4432 
       
  4433 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
       
  4434 {
       
  4435 	struct rtl_fw *rtl_fw;
       
  4436 	const char *name;
       
  4437 	int rc = -ENOMEM;
       
  4438 
       
  4439 	name = rtl_lookup_firmware_name(tp);
       
  4440 	if (!name)
       
  4441 		goto out_no_firmware;
       
  4442 
       
  4443 	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
       
  4444 	if (!rtl_fw)
       
  4445 		goto err_warn;
       
  4446 
       
  4447 	rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
       
  4448 	if (rc < 0)
       
  4449 		goto err_free;
       
  4450 
       
  4451 	rc = rtl_check_firmware(tp, rtl_fw);
       
  4452 	if (rc < 0)
       
  4453 		goto err_release_firmware;
       
  4454 
       
  4455 	tp->rtl_fw = rtl_fw;
       
  4456 out:
       
  4457 	return;
       
  4458 
       
  4459 err_release_firmware:
       
  4460 	release_firmware(rtl_fw->fw);
       
  4461 err_free:
       
  4462 	kfree(rtl_fw);
       
  4463 err_warn:
       
  4464 	netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
       
  4465 		   name, rc);
       
  4466 out_no_firmware:
       
  4467 	tp->rtl_fw = NULL;
       
  4468 	goto out;
       
  4469 }
       
  4470 
       
  4471 static void rtl_request_firmware(struct rtl8169_private *tp)
       
  4472 {
       
  4473 	if (IS_ERR(tp->rtl_fw))
       
  4474 		rtl_request_uncached_firmware(tp);
       
  4475 }
       
  4476 
       
  4477 static void rtl_rx_close(struct rtl8169_private *tp)
       
  4478 {
       
  4479 	void __iomem *ioaddr = tp->mmio_addr;
       
  4480 
       
  4481 	RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
       
  4482 }
       
  4483 
       
  4484 DECLARE_RTL_COND(rtl_npq_cond)
       
  4485 {
       
  4486 	void __iomem *ioaddr = tp->mmio_addr;
       
  4487 
       
  4488 	return RTL_R8(TxPoll) & NPQ;
       
  4489 }
       
  4490 
       
  4491 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
       
  4492 {
       
  4493 	void __iomem *ioaddr = tp->mmio_addr;
       
  4494 
       
  4495 	return RTL_R32(TxConfig) & TXCFG_EMPTY;
       
  4496 }
       
  4497 
       
  4498 static void rtl8169_hw_reset(struct rtl8169_private *tp)
       
  4499 {
       
  4500 	void __iomem *ioaddr = tp->mmio_addr;
       
  4501 
       
  4502 	/* Disable interrupts */
       
  4503 	rtl8169_irq_mask_and_ack(tp);
       
  4504 
       
  4505 	rtl_rx_close(tp);
       
  4506 
       
  4507 	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
       
  4508 	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
       
  4509 	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
       
  4510 		rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
       
  4511 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
       
  4512 	           tp->mac_version == RTL_GIGA_MAC_VER_35 ||
       
  4513 	           tp->mac_version == RTL_GIGA_MAC_VER_36 ||
       
  4514 	           tp->mac_version == RTL_GIGA_MAC_VER_37 ||
       
  4515 	           tp->mac_version == RTL_GIGA_MAC_VER_40 ||
       
  4516 	           tp->mac_version == RTL_GIGA_MAC_VER_41 ||
       
  4517 	           tp->mac_version == RTL_GIGA_MAC_VER_42 ||
       
  4518 	           tp->mac_version == RTL_GIGA_MAC_VER_43 ||
       
  4519 	           tp->mac_version == RTL_GIGA_MAC_VER_44 ||
       
  4520 	           tp->mac_version == RTL_GIGA_MAC_VER_38) {
       
  4521 		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
       
  4522 		rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
       
  4523 	} else {
       
  4524 		RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
       
  4525 		udelay(100);
       
  4526 	}
       
  4527 
       
  4528 	rtl_hw_reset(tp);
       
  4529 }
       
  4530 
       
  4531 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
       
  4532 {
       
  4533 	void __iomem *ioaddr = tp->mmio_addr;
       
  4534 
       
  4535 	/* Set DMA burst size and Interframe Gap Time */
       
  4536 	RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
       
  4537 		(InterFrameGap << TxInterFrameGapShift));
       
  4538 }
       
  4539 
       
  4540 static void rtl_hw_start(struct net_device *dev)
       
  4541 {
       
  4542 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4543 
       
  4544 	tp->hw_start(dev);
       
  4545 
       
  4546 	rtl_irq_enable_all(tp);
       
  4547 }
       
  4548 
       
  4549 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
       
  4550 					 void __iomem *ioaddr)
       
  4551 {
       
  4552 	/*
       
  4553 	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
       
  4554 	 * register to be written before TxDescAddrLow to work.
       
  4555 	 * Switching from MMIO to I/O access fixes the issue as well.
       
  4556 	 */
       
  4557 	RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
       
  4558 	RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
       
  4559 	RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
       
  4560 	RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
       
  4561 }
       
  4562 
       
  4563 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
       
  4564 {
       
  4565 	u16 cmd;
       
  4566 
       
  4567 	cmd = RTL_R16(CPlusCmd);
       
  4568 	RTL_W16(CPlusCmd, cmd);
       
  4569 	return cmd;
       
  4570 }
       
  4571 
       
  4572 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
       
  4573 {
       
  4574 	/* Low hurts. Let's disable the filtering. */
       
  4575 	RTL_W16(RxMaxSize, rx_buf_sz + 1);
       
  4576 }
       
  4577 
       
  4578 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
       
  4579 {
       
  4580 	static const struct rtl_cfg2_info {
       
  4581 		u32 mac_version;
       
  4582 		u32 clk;
       
  4583 		u32 val;
       
  4584 	} cfg2_info [] = {
       
  4585 		{ RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
       
  4586 		{ RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
       
  4587 		{ RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
       
  4588 		{ RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
       
  4589 	};
       
  4590 	const struct rtl_cfg2_info *p = cfg2_info;
       
  4591 	unsigned int i;
       
  4592 	u32 clk;
       
  4593 
       
  4594 	clk = RTL_R8(Config2) & PCI_Clock_66MHz;
       
  4595 	for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
       
  4596 		if ((p->mac_version == mac_version) && (p->clk == clk)) {
       
  4597 			RTL_W32(0x7c, p->val);
       
  4598 			break;
       
  4599 		}
       
  4600 	}
       
  4601 }
       
  4602 
       
  4603 static void rtl_set_rx_mode(struct net_device *dev)
       
  4604 {
       
  4605 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4606 	void __iomem *ioaddr = tp->mmio_addr;
       
  4607 	u32 mc_filter[2];	/* Multicast hash filter */
       
  4608 	int rx_mode;
       
  4609 	u32 tmp = 0;
       
  4610 
       
  4611 	if (dev->flags & IFF_PROMISC) {
       
  4612 		/* Unconditionally log net taps. */
       
  4613 		netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
       
  4614 		rx_mode =
       
  4615 		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
       
  4616 		    AcceptAllPhys;
       
  4617 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  4618 	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
       
  4619 		   (dev->flags & IFF_ALLMULTI)) {
       
  4620 		/* Too many to filter perfectly -- accept all multicasts. */
       
  4621 		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
       
  4622 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  4623 	} else {
       
  4624 		struct netdev_hw_addr *ha;
       
  4625 
       
  4626 		rx_mode = AcceptBroadcast | AcceptMyPhys;
       
  4627 		mc_filter[1] = mc_filter[0] = 0;
       
  4628 		netdev_for_each_mc_addr(ha, dev) {
       
  4629 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
       
  4630 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
       
  4631 			rx_mode |= AcceptMulticast;
       
  4632 		}
       
  4633 	}
       
  4634 
       
  4635 	if (dev->features & NETIF_F_RXALL)
       
  4636 		rx_mode |= (AcceptErr | AcceptRunt);
       
  4637 
       
  4638 	tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
       
  4639 
       
  4640 	if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
       
  4641 		u32 data = mc_filter[0];
       
  4642 
       
  4643 		mc_filter[0] = swab32(mc_filter[1]);
       
  4644 		mc_filter[1] = swab32(data);
       
  4645 	}
       
  4646 
       
  4647 	if (tp->mac_version == RTL_GIGA_MAC_VER_35)
       
  4648 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  4649 
       
  4650 	RTL_W32(MAR0 + 4, mc_filter[1]);
       
  4651 	RTL_W32(MAR0 + 0, mc_filter[0]);
       
  4652 
       
  4653 	RTL_W32(RxConfig, tmp);
       
  4654 }
       
  4655 
       
  4656 static void rtl_hw_start_8169(struct net_device *dev)
       
  4657 {
       
  4658 	struct rtl8169_private *tp = netdev_priv(dev);
       
  4659 	void __iomem *ioaddr = tp->mmio_addr;
       
  4660 	struct pci_dev *pdev = tp->pci_dev;
       
  4661 
       
  4662 	if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
       
  4663 		RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
       
  4664 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
       
  4665 	}
       
  4666 
       
  4667 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  4668 	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
       
  4669 	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
       
  4670 	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
       
  4671 	    tp->mac_version == RTL_GIGA_MAC_VER_04)
       
  4672 		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  4673 
       
  4674 	rtl_init_rxcfg(tp);
       
  4675 
       
  4676 	RTL_W8(EarlyTxThres, NoEarlyTx);
       
  4677 
       
  4678 	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
       
  4679 
       
  4680 	if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
       
  4681 	    tp->mac_version == RTL_GIGA_MAC_VER_02 ||
       
  4682 	    tp->mac_version == RTL_GIGA_MAC_VER_03 ||
       
  4683 	    tp->mac_version == RTL_GIGA_MAC_VER_04)
       
  4684 		rtl_set_rx_tx_config_registers(tp);
       
  4685 
       
  4686 	tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
       
  4687 
       
  4688 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
       
  4689 	    tp->mac_version == RTL_GIGA_MAC_VER_03) {
       
  4690 		dprintk("Set MAC Reg C+CR Offset 0xE0. "
       
  4691 			"Bit-3 and bit-14 MUST be 1\n");
       
  4692 		tp->cp_cmd |= (1 << 14);
       
  4693 	}
       
  4694 
       
  4695 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  4696 
       
  4697 	rtl8169_set_magic_reg(ioaddr, tp->mac_version);
       
  4698 
       
  4699 	/*
       
  4700 	 * Undocumented corner. Supposedly:
       
  4701 	 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
       
  4702 	 */
       
  4703 	RTL_W16(IntrMitigate, 0x0000);
       
  4704 
       
  4705 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  4706 
       
  4707 	if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
       
  4708 	    tp->mac_version != RTL_GIGA_MAC_VER_02 &&
       
  4709 	    tp->mac_version != RTL_GIGA_MAC_VER_03 &&
       
  4710 	    tp->mac_version != RTL_GIGA_MAC_VER_04) {
       
  4711 		RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  4712 		rtl_set_rx_tx_config_registers(tp);
       
  4713 	}
       
  4714 
       
  4715 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  4716 
       
  4717 	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
       
  4718 	RTL_R8(IntrMask);
       
  4719 
       
  4720 	RTL_W32(RxMissed, 0);
       
  4721 
       
  4722 	rtl_set_rx_mode(dev);
       
  4723 
       
  4724 	/* no early-rx interrupts */
       
  4725 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
       
  4726 }
       
  4727 
       
  4728 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
       
  4729 {
       
  4730 	if (tp->csi_ops.write)
       
  4731 		tp->csi_ops.write(tp, addr, value);
       
  4732 }
       
  4733 
       
  4734 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
       
  4735 {
       
  4736 	return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
       
  4737 }
       
  4738 
       
  4739 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
       
  4740 {
       
  4741 	u32 csi;
       
  4742 
       
  4743 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
       
  4744 	rtl_csi_write(tp, 0x070c, csi | bits);
       
  4745 }
       
  4746 
       
  4747 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
       
  4748 {
       
  4749 	rtl_csi_access_enable(tp, 0x17000000);
       
  4750 }
       
  4751 
       
  4752 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
       
  4753 {
       
  4754 	rtl_csi_access_enable(tp, 0x27000000);
       
  4755 }
       
  4756 
       
  4757 DECLARE_RTL_COND(rtl_csiar_cond)
       
  4758 {
       
  4759 	void __iomem *ioaddr = tp->mmio_addr;
       
  4760 
       
  4761 	return RTL_R32(CSIAR) & CSIAR_FLAG;
       
  4762 }
       
  4763 
       
  4764 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
       
  4765 {
       
  4766 	void __iomem *ioaddr = tp->mmio_addr;
       
  4767 
       
  4768 	RTL_W32(CSIDR, value);
       
  4769 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
       
  4770 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
  4771 
       
  4772 	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
       
  4773 }
       
  4774 
       
  4775 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
       
  4776 {
       
  4777 	void __iomem *ioaddr = tp->mmio_addr;
       
  4778 
       
  4779 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
       
  4780 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
  4781 
       
  4782 	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
       
  4783 		RTL_R32(CSIDR) : ~0;
       
  4784 }
       
  4785 
       
  4786 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
       
  4787 {
       
  4788 	void __iomem *ioaddr = tp->mmio_addr;
       
  4789 
       
  4790 	RTL_W32(CSIDR, value);
       
  4791 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
       
  4792 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
       
  4793 		CSIAR_FUNC_NIC);
       
  4794 
       
  4795 	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
       
  4796 }
       
  4797 
       
  4798 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
       
  4799 {
       
  4800 	void __iomem *ioaddr = tp->mmio_addr;
       
  4801 
       
  4802 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
       
  4803 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
  4804 
       
  4805 	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
       
  4806 		RTL_R32(CSIDR) : ~0;
       
  4807 }
       
  4808 
       
  4809 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
       
  4810 {
       
  4811 	void __iomem *ioaddr = tp->mmio_addr;
       
  4812 
       
  4813 	RTL_W32(CSIDR, value);
       
  4814 	RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
       
  4815 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
       
  4816 		CSIAR_FUNC_NIC2);
       
  4817 
       
  4818 	rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
       
  4819 }
       
  4820 
       
  4821 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
       
  4822 {
       
  4823 	void __iomem *ioaddr = tp->mmio_addr;
       
  4824 
       
  4825 	RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
       
  4826 		CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
       
  4827 
       
  4828 	return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
       
  4829 		RTL_R32(CSIDR) : ~0;
       
  4830 }
       
  4831 
       
  4832 static void rtl_init_csi_ops(struct rtl8169_private *tp)
       
  4833 {
       
  4834 	struct csi_ops *ops = &tp->csi_ops;
       
  4835 
       
  4836 	switch (tp->mac_version) {
       
  4837 	case RTL_GIGA_MAC_VER_01:
       
  4838 	case RTL_GIGA_MAC_VER_02:
       
  4839 	case RTL_GIGA_MAC_VER_03:
       
  4840 	case RTL_GIGA_MAC_VER_04:
       
  4841 	case RTL_GIGA_MAC_VER_05:
       
  4842 	case RTL_GIGA_MAC_VER_06:
       
  4843 	case RTL_GIGA_MAC_VER_10:
       
  4844 	case RTL_GIGA_MAC_VER_11:
       
  4845 	case RTL_GIGA_MAC_VER_12:
       
  4846 	case RTL_GIGA_MAC_VER_13:
       
  4847 	case RTL_GIGA_MAC_VER_14:
       
  4848 	case RTL_GIGA_MAC_VER_15:
       
  4849 	case RTL_GIGA_MAC_VER_16:
       
  4850 	case RTL_GIGA_MAC_VER_17:
       
  4851 		ops->write	= NULL;
       
  4852 		ops->read	= NULL;
       
  4853 		break;
       
  4854 
       
  4855 	case RTL_GIGA_MAC_VER_37:
       
  4856 	case RTL_GIGA_MAC_VER_38:
       
  4857 		ops->write	= r8402_csi_write;
       
  4858 		ops->read	= r8402_csi_read;
       
  4859 		break;
       
  4860 
       
  4861 	case RTL_GIGA_MAC_VER_44:
       
  4862 		ops->write	= r8411_csi_write;
       
  4863 		ops->read	= r8411_csi_read;
       
  4864 		break;
       
  4865 
       
  4866 	default:
       
  4867 		ops->write	= r8169_csi_write;
       
  4868 		ops->read	= r8169_csi_read;
       
  4869 		break;
       
  4870 	}
       
  4871 }
       
  4872 
       
  4873 struct ephy_info {
       
  4874 	unsigned int offset;
       
  4875 	u16 mask;
       
  4876 	u16 bits;
       
  4877 };
       
  4878 
       
  4879 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
       
  4880 			  int len)
       
  4881 {
       
  4882 	u16 w;
       
  4883 
       
  4884 	while (len-- > 0) {
       
  4885 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
       
  4886 		rtl_ephy_write(tp, e->offset, w);
       
  4887 		e++;
       
  4888 	}
       
  4889 }
       
  4890 
       
  4891 static void rtl_disable_clock_request(struct pci_dev *pdev)
       
  4892 {
       
  4893 	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
       
  4894 				   PCI_EXP_LNKCTL_CLKREQ_EN);
       
  4895 }
       
  4896 
       
  4897 static void rtl_enable_clock_request(struct pci_dev *pdev)
       
  4898 {
       
  4899 	pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
       
  4900 				 PCI_EXP_LNKCTL_CLKREQ_EN);
       
  4901 }
       
  4902 
       
  4903 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
       
  4904 {
       
  4905 	void __iomem *ioaddr = tp->mmio_addr;
       
  4906 	u8 data;
       
  4907 
       
  4908 	data = RTL_R8(Config3);
       
  4909 
       
  4910 	if (enable)
       
  4911 		data |= Rdy_to_L23;
       
  4912 	else
       
  4913 		data &= ~Rdy_to_L23;
       
  4914 
       
  4915 	RTL_W8(Config3, data);
       
  4916 }
       
  4917 
       
  4918 #define R8168_CPCMD_QUIRK_MASK (\
       
  4919 	EnableBist | \
       
  4920 	Mac_dbgo_oe | \
       
  4921 	Force_half_dup | \
       
  4922 	Force_rxflow_en | \
       
  4923 	Force_txflow_en | \
       
  4924 	Cxpl_dbg_sel | \
       
  4925 	ASF | \
       
  4926 	PktCntrDisable | \
       
  4927 	Mac_dbgo_sel)
       
  4928 
       
  4929 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
       
  4930 {
       
  4931 	void __iomem *ioaddr = tp->mmio_addr;
       
  4932 	struct pci_dev *pdev = tp->pci_dev;
       
  4933 
       
  4934 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  4935 
       
  4936 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  4937 
       
  4938 	if (tp->dev->mtu <= ETH_DATA_LEN) {
       
  4939 		rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
       
  4940 					 PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  4941 	}
       
  4942 }
       
  4943 
       
  4944 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
       
  4945 {
       
  4946 	void __iomem *ioaddr = tp->mmio_addr;
       
  4947 
       
  4948 	rtl_hw_start_8168bb(tp);
       
  4949 
       
  4950 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  4951 
       
  4952 	RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
       
  4953 }
       
  4954 
       
  4955 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
       
  4956 {
       
  4957 	void __iomem *ioaddr = tp->mmio_addr;
       
  4958 	struct pci_dev *pdev = tp->pci_dev;
       
  4959 
       
  4960 	RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
       
  4961 
       
  4962 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  4963 
       
  4964 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  4965 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  4966 
       
  4967 	rtl_disable_clock_request(pdev);
       
  4968 
       
  4969 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  4970 }
       
  4971 
       
  4972 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
       
  4973 {
       
  4974 	static const struct ephy_info e_info_8168cp[] = {
       
  4975 		{ 0x01, 0,	0x0001 },
       
  4976 		{ 0x02, 0x0800,	0x1000 },
       
  4977 		{ 0x03, 0,	0x0042 },
       
  4978 		{ 0x06, 0x0080,	0x0000 },
       
  4979 		{ 0x07, 0,	0x2000 }
       
  4980 	};
       
  4981 
       
  4982 	rtl_csi_access_enable_2(tp);
       
  4983 
       
  4984 	rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
       
  4985 
       
  4986 	__rtl_hw_start_8168cp(tp);
       
  4987 }
       
  4988 
       
  4989 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
       
  4990 {
       
  4991 	void __iomem *ioaddr = tp->mmio_addr;
       
  4992 	struct pci_dev *pdev = tp->pci_dev;
       
  4993 
       
  4994 	rtl_csi_access_enable_2(tp);
       
  4995 
       
  4996 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  4997 
       
  4998 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  4999 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5000 
       
  5001 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  5002 }
       
  5003 
       
  5004 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
       
  5005 {
       
  5006 	void __iomem *ioaddr = tp->mmio_addr;
       
  5007 	struct pci_dev *pdev = tp->pci_dev;
       
  5008 
       
  5009 	rtl_csi_access_enable_2(tp);
       
  5010 
       
  5011 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  5012 
       
  5013 	/* Magic. */
       
  5014 	RTL_W8(DBG_REG, 0x20);
       
  5015 
       
  5016 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5017 
       
  5018 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  5019 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5020 
       
  5021 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  5022 }
       
  5023 
       
  5024 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
       
  5025 {
       
  5026 	void __iomem *ioaddr = tp->mmio_addr;
       
  5027 	static const struct ephy_info e_info_8168c_1[] = {
       
  5028 		{ 0x02, 0x0800,	0x1000 },
       
  5029 		{ 0x03, 0,	0x0002 },
       
  5030 		{ 0x06, 0x0080,	0x0000 }
       
  5031 	};
       
  5032 
       
  5033 	rtl_csi_access_enable_2(tp);
       
  5034 
       
  5035 	RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
       
  5036 
       
  5037 	rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
       
  5038 
       
  5039 	__rtl_hw_start_8168cp(tp);
       
  5040 }
       
  5041 
       
  5042 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
       
  5043 {
       
  5044 	static const struct ephy_info e_info_8168c_2[] = {
       
  5045 		{ 0x01, 0,	0x0001 },
       
  5046 		{ 0x03, 0x0400,	0x0220 }
       
  5047 	};
       
  5048 
       
  5049 	rtl_csi_access_enable_2(tp);
       
  5050 
       
  5051 	rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
       
  5052 
       
  5053 	__rtl_hw_start_8168cp(tp);
       
  5054 }
       
  5055 
       
  5056 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
       
  5057 {
       
  5058 	rtl_hw_start_8168c_2(tp);
       
  5059 }
       
  5060 
       
  5061 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
       
  5062 {
       
  5063 	rtl_csi_access_enable_2(tp);
       
  5064 
       
  5065 	__rtl_hw_start_8168cp(tp);
       
  5066 }
       
  5067 
       
  5068 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
       
  5069 {
       
  5070 	void __iomem *ioaddr = tp->mmio_addr;
       
  5071 	struct pci_dev *pdev = tp->pci_dev;
       
  5072 
       
  5073 	rtl_csi_access_enable_2(tp);
       
  5074 
       
  5075 	rtl_disable_clock_request(pdev);
       
  5076 
       
  5077 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5078 
       
  5079 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  5080 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5081 
       
  5082 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
       
  5083 }
       
  5084 
       
  5085 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
       
  5086 {
       
  5087 	void __iomem *ioaddr = tp->mmio_addr;
       
  5088 	struct pci_dev *pdev = tp->pci_dev;
       
  5089 
       
  5090 	rtl_csi_access_enable_1(tp);
       
  5091 
       
  5092 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  5093 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5094 
       
  5095 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5096 
       
  5097 	rtl_disable_clock_request(pdev);
       
  5098 }
       
  5099 
       
  5100 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
       
  5101 {
       
  5102 	void __iomem *ioaddr = tp->mmio_addr;
       
  5103 	struct pci_dev *pdev = tp->pci_dev;
       
  5104 	static const struct ephy_info e_info_8168d_4[] = {
       
  5105 		{ 0x0b, ~0,	0x48 },
       
  5106 		{ 0x19, 0x20,	0x50 },
       
  5107 		{ 0x0c, ~0,	0x20 }
       
  5108 	};
       
  5109 	int i;
       
  5110 
       
  5111 	rtl_csi_access_enable_1(tp);
       
  5112 
       
  5113 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5114 
       
  5115 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5116 
       
  5117 	for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
       
  5118 		const struct ephy_info *e = e_info_8168d_4 + i;
       
  5119 		u16 w;
       
  5120 
       
  5121 		w = rtl_ephy_read(tp, e->offset);
       
  5122 		rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
       
  5123 	}
       
  5124 
       
  5125 	rtl_enable_clock_request(pdev);
       
  5126 }
       
  5127 
       
  5128 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
       
  5129 {
       
  5130 	void __iomem *ioaddr = tp->mmio_addr;
       
  5131 	struct pci_dev *pdev = tp->pci_dev;
       
  5132 	static const struct ephy_info e_info_8168e_1[] = {
       
  5133 		{ 0x00, 0x0200,	0x0100 },
       
  5134 		{ 0x00, 0x0000,	0x0004 },
       
  5135 		{ 0x06, 0x0002,	0x0001 },
       
  5136 		{ 0x06, 0x0000,	0x0030 },
       
  5137 		{ 0x07, 0x0000,	0x2000 },
       
  5138 		{ 0x00, 0x0000,	0x0020 },
       
  5139 		{ 0x03, 0x5800,	0x2000 },
       
  5140 		{ 0x03, 0x0000,	0x0001 },
       
  5141 		{ 0x01, 0x0800,	0x1000 },
       
  5142 		{ 0x07, 0x0000,	0x4000 },
       
  5143 		{ 0x1e, 0x0000,	0x2000 },
       
  5144 		{ 0x19, 0xffff,	0xfe6c },
       
  5145 		{ 0x0a, 0x0000,	0x0040 }
       
  5146 	};
       
  5147 
       
  5148 	rtl_csi_access_enable_2(tp);
       
  5149 
       
  5150 	rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
       
  5151 
       
  5152 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  5153 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5154 
       
  5155 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5156 
       
  5157 	rtl_disable_clock_request(pdev);
       
  5158 
       
  5159 	/* Reset tx FIFO pointer */
       
  5160 	RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
       
  5161 	RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
       
  5162 
       
  5163 	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
       
  5164 }
       
  5165 
       
  5166 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
       
  5167 {
       
  5168 	void __iomem *ioaddr = tp->mmio_addr;
       
  5169 	struct pci_dev *pdev = tp->pci_dev;
       
  5170 	static const struct ephy_info e_info_8168e_2[] = {
       
  5171 		{ 0x09, 0x0000,	0x0080 },
       
  5172 		{ 0x19, 0x0000,	0x0224 }
       
  5173 	};
       
  5174 
       
  5175 	rtl_csi_access_enable_1(tp);
       
  5176 
       
  5177 	rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
       
  5178 
       
  5179 	if (tp->dev->mtu <= ETH_DATA_LEN)
       
  5180 		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5181 
       
  5182 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5183 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5184 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
       
  5185 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
       
  5186 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
       
  5187 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
       
  5188 	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
       
  5189 	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
       
  5190 
       
  5191 	RTL_W8(MaxTxPacketSize, EarlySize);
       
  5192 
       
  5193 	rtl_disable_clock_request(pdev);
       
  5194 
       
  5195 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
       
  5196 	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
       
  5197 
       
  5198 	/* Adjust EEE LED frequency */
       
  5199 	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
       
  5200 
       
  5201 	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
       
  5202 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
       
  5203 	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
       
  5204 }
       
  5205 
       
  5206 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
       
  5207 {
       
  5208 	void __iomem *ioaddr = tp->mmio_addr;
       
  5209 	struct pci_dev *pdev = tp->pci_dev;
       
  5210 
       
  5211 	rtl_csi_access_enable_2(tp);
       
  5212 
       
  5213 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5214 
       
  5215 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5216 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5217 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
       
  5218 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
       
  5219 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
       
  5220 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
       
  5221 	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
       
  5222 	rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
       
  5223 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
       
  5224 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
       
  5225 
       
  5226 	RTL_W8(MaxTxPacketSize, EarlySize);
       
  5227 
       
  5228 	rtl_disable_clock_request(pdev);
       
  5229 
       
  5230 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
       
  5231 	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
       
  5232 	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
       
  5233 	RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
       
  5234 	RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
       
  5235 }
       
  5236 
       
  5237 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
       
  5238 {
       
  5239 	void __iomem *ioaddr = tp->mmio_addr;
       
  5240 	static const struct ephy_info e_info_8168f_1[] = {
       
  5241 		{ 0x06, 0x00c0,	0x0020 },
       
  5242 		{ 0x08, 0x0001,	0x0002 },
       
  5243 		{ 0x09, 0x0000,	0x0080 },
       
  5244 		{ 0x19, 0x0000,	0x0224 }
       
  5245 	};
       
  5246 
       
  5247 	rtl_hw_start_8168f(tp);
       
  5248 
       
  5249 	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
       
  5250 
       
  5251 	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
       
  5252 
       
  5253 	/* Adjust EEE LED frequency */
       
  5254 	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
       
  5255 }
       
  5256 
       
  5257 static void rtl_hw_start_8411(struct rtl8169_private *tp)
       
  5258 {
       
  5259 	static const struct ephy_info e_info_8168f_1[] = {
       
  5260 		{ 0x06, 0x00c0,	0x0020 },
       
  5261 		{ 0x0f, 0xffff,	0x5200 },
       
  5262 		{ 0x1e, 0x0000,	0x4000 },
       
  5263 		{ 0x19, 0x0000,	0x0224 }
       
  5264 	};
       
  5265 
       
  5266 	rtl_hw_start_8168f(tp);
       
  5267 	rtl_pcie_state_l2l3_enable(tp, false);
       
  5268 
       
  5269 	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
       
  5270 
       
  5271 	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
       
  5272 }
       
  5273 
       
  5274 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
       
  5275 {
       
  5276 	void __iomem *ioaddr = tp->mmio_addr;
       
  5277 	struct pci_dev *pdev = tp->pci_dev;
       
  5278 
       
  5279 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
       
  5280 
       
  5281 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
       
  5282 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
       
  5283 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
       
  5284 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
       
  5285 
       
  5286 	rtl_csi_access_enable_1(tp);
       
  5287 
       
  5288 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5289 
       
  5290 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
       
  5291 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
       
  5292 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
       
  5293 
       
  5294 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  5295 	RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
       
  5296 	RTL_W8(MaxTxPacketSize, EarlySize);
       
  5297 
       
  5298 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5299 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5300 
       
  5301 	/* Adjust EEE LED frequency */
       
  5302 	RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
       
  5303 
       
  5304 	rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
       
  5305 	rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
       
  5306 
       
  5307 	rtl_pcie_state_l2l3_enable(tp, false);
       
  5308 }
       
  5309 
       
  5310 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
       
  5311 {
       
  5312 	void __iomem *ioaddr = tp->mmio_addr;
       
  5313 	static const struct ephy_info e_info_8168g_2[] = {
       
  5314 		{ 0x00, 0x0000,	0x0008 },
       
  5315 		{ 0x0c, 0x3df0,	0x0200 },
       
  5316 		{ 0x19, 0xffff,	0xfc00 },
       
  5317 		{ 0x1e, 0xffff,	0x20eb }
       
  5318 	};
       
  5319 
       
  5320 	rtl_hw_start_8168g_1(tp);
       
  5321 
       
  5322 	/* disable aspm and clock request before access ephy */
       
  5323 	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
       
  5324 	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
       
  5325 	rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
       
  5326 }
       
  5327 
       
  5328 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
       
  5329 {
       
  5330 	void __iomem *ioaddr = tp->mmio_addr;
       
  5331 	static const struct ephy_info e_info_8411_2[] = {
       
  5332 		{ 0x00, 0x0000,	0x0008 },
       
  5333 		{ 0x0c, 0x3df0,	0x0200 },
       
  5334 		{ 0x0f, 0xffff,	0x5200 },
       
  5335 		{ 0x19, 0x0020,	0x0000 },
       
  5336 		{ 0x1e, 0x0000,	0x2000 }
       
  5337 	};
       
  5338 
       
  5339 	rtl_hw_start_8168g_1(tp);
       
  5340 
       
  5341 	/* disable aspm and clock request before access ephy */
       
  5342 	RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
       
  5343 	RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
       
  5344 	rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
       
  5345 }
       
  5346 
       
  5347 static void rtl_hw_start_8168(struct net_device *dev)
       
  5348 {
       
  5349 	struct rtl8169_private *tp = netdev_priv(dev);
       
  5350 	void __iomem *ioaddr = tp->mmio_addr;
       
  5351 
       
  5352 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  5353 
       
  5354 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5355 
       
  5356 	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
       
  5357 
       
  5358 	tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
       
  5359 
       
  5360 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  5361 
       
  5362 	RTL_W16(IntrMitigate, 0x5151);
       
  5363 
       
  5364 	/* Work around for RxFIFO overflow. */
       
  5365 	if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
       
  5366 		tp->event_slow |= RxFIFOOver | PCSTimeout;
       
  5367 		tp->event_slow &= ~RxOverflow;
       
  5368 	}
       
  5369 
       
  5370 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  5371 
       
  5372 	rtl_set_rx_tx_config_registers(tp);
       
  5373 
       
  5374 	RTL_R8(IntrMask);
       
  5375 
       
  5376 	switch (tp->mac_version) {
       
  5377 	case RTL_GIGA_MAC_VER_11:
       
  5378 		rtl_hw_start_8168bb(tp);
       
  5379 		break;
       
  5380 
       
  5381 	case RTL_GIGA_MAC_VER_12:
       
  5382 	case RTL_GIGA_MAC_VER_17:
       
  5383 		rtl_hw_start_8168bef(tp);
       
  5384 		break;
       
  5385 
       
  5386 	case RTL_GIGA_MAC_VER_18:
       
  5387 		rtl_hw_start_8168cp_1(tp);
       
  5388 		break;
       
  5389 
       
  5390 	case RTL_GIGA_MAC_VER_19:
       
  5391 		rtl_hw_start_8168c_1(tp);
       
  5392 		break;
       
  5393 
       
  5394 	case RTL_GIGA_MAC_VER_20:
       
  5395 		rtl_hw_start_8168c_2(tp);
       
  5396 		break;
       
  5397 
       
  5398 	case RTL_GIGA_MAC_VER_21:
       
  5399 		rtl_hw_start_8168c_3(tp);
       
  5400 		break;
       
  5401 
       
  5402 	case RTL_GIGA_MAC_VER_22:
       
  5403 		rtl_hw_start_8168c_4(tp);
       
  5404 		break;
       
  5405 
       
  5406 	case RTL_GIGA_MAC_VER_23:
       
  5407 		rtl_hw_start_8168cp_2(tp);
       
  5408 		break;
       
  5409 
       
  5410 	case RTL_GIGA_MAC_VER_24:
       
  5411 		rtl_hw_start_8168cp_3(tp);
       
  5412 		break;
       
  5413 
       
  5414 	case RTL_GIGA_MAC_VER_25:
       
  5415 	case RTL_GIGA_MAC_VER_26:
       
  5416 	case RTL_GIGA_MAC_VER_27:
       
  5417 		rtl_hw_start_8168d(tp);
       
  5418 		break;
       
  5419 
       
  5420 	case RTL_GIGA_MAC_VER_28:
       
  5421 		rtl_hw_start_8168d_4(tp);
       
  5422 		break;
       
  5423 
       
  5424 	case RTL_GIGA_MAC_VER_31:
       
  5425 		rtl_hw_start_8168dp(tp);
       
  5426 		break;
       
  5427 
       
  5428 	case RTL_GIGA_MAC_VER_32:
       
  5429 	case RTL_GIGA_MAC_VER_33:
       
  5430 		rtl_hw_start_8168e_1(tp);
       
  5431 		break;
       
  5432 	case RTL_GIGA_MAC_VER_34:
       
  5433 		rtl_hw_start_8168e_2(tp);
       
  5434 		break;
       
  5435 
       
  5436 	case RTL_GIGA_MAC_VER_35:
       
  5437 	case RTL_GIGA_MAC_VER_36:
       
  5438 		rtl_hw_start_8168f_1(tp);
       
  5439 		break;
       
  5440 
       
  5441 	case RTL_GIGA_MAC_VER_38:
       
  5442 		rtl_hw_start_8411(tp);
       
  5443 		break;
       
  5444 
       
  5445 	case RTL_GIGA_MAC_VER_40:
       
  5446 	case RTL_GIGA_MAC_VER_41:
       
  5447 		rtl_hw_start_8168g_1(tp);
       
  5448 		break;
       
  5449 	case RTL_GIGA_MAC_VER_42:
       
  5450 		rtl_hw_start_8168g_2(tp);
       
  5451 		break;
       
  5452 
       
  5453 	case RTL_GIGA_MAC_VER_44:
       
  5454 		rtl_hw_start_8411_2(tp);
       
  5455 		break;
       
  5456 
       
  5457 	default:
       
  5458 		printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
       
  5459 			dev->name, tp->mac_version);
       
  5460 		break;
       
  5461 	}
       
  5462 
       
  5463 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  5464 
       
  5465 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  5466 
       
  5467 	rtl_set_rx_mode(dev);
       
  5468 
       
  5469 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
       
  5470 }
       
  5471 
       
  5472 #define R810X_CPCMD_QUIRK_MASK (\
       
  5473 	EnableBist | \
       
  5474 	Mac_dbgo_oe | \
       
  5475 	Force_half_dup | \
       
  5476 	Force_rxflow_en | \
       
  5477 	Force_txflow_en | \
       
  5478 	Cxpl_dbg_sel | \
       
  5479 	ASF | \
       
  5480 	PktCntrDisable | \
       
  5481 	Mac_dbgo_sel)
       
  5482 
       
  5483 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
       
  5484 {
       
  5485 	void __iomem *ioaddr = tp->mmio_addr;
       
  5486 	struct pci_dev *pdev = tp->pci_dev;
       
  5487 	static const struct ephy_info e_info_8102e_1[] = {
       
  5488 		{ 0x01,	0, 0x6e65 },
       
  5489 		{ 0x02,	0, 0x091f },
       
  5490 		{ 0x03,	0, 0xc2f9 },
       
  5491 		{ 0x06,	0, 0xafb5 },
       
  5492 		{ 0x07,	0, 0x0e00 },
       
  5493 		{ 0x19,	0, 0xec80 },
       
  5494 		{ 0x01,	0, 0x2e65 },
       
  5495 		{ 0x01,	0, 0x6e65 }
       
  5496 	};
       
  5497 	u8 cfg1;
       
  5498 
       
  5499 	rtl_csi_access_enable_2(tp);
       
  5500 
       
  5501 	RTL_W8(DBG_REG, FIX_NAK_1);
       
  5502 
       
  5503 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5504 
       
  5505 	RTL_W8(Config1,
       
  5506 	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
       
  5507 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  5508 
       
  5509 	cfg1 = RTL_R8(Config1);
       
  5510 	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
       
  5511 		RTL_W8(Config1, cfg1 & ~LEDS0);
       
  5512 
       
  5513 	rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
       
  5514 }
       
  5515 
       
  5516 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
       
  5517 {
       
  5518 	void __iomem *ioaddr = tp->mmio_addr;
       
  5519 	struct pci_dev *pdev = tp->pci_dev;
       
  5520 
       
  5521 	rtl_csi_access_enable_2(tp);
       
  5522 
       
  5523 	rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5524 
       
  5525 	RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
       
  5526 	RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
       
  5527 }
       
  5528 
       
  5529 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
       
  5530 {
       
  5531 	rtl_hw_start_8102e_2(tp);
       
  5532 
       
  5533 	rtl_ephy_write(tp, 0x03, 0xc2f9);
       
  5534 }
       
  5535 
       
  5536 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
       
  5537 {
       
  5538 	void __iomem *ioaddr = tp->mmio_addr;
       
  5539 	static const struct ephy_info e_info_8105e_1[] = {
       
  5540 		{ 0x07,	0, 0x4000 },
       
  5541 		{ 0x19,	0, 0x0200 },
       
  5542 		{ 0x19,	0, 0x0020 },
       
  5543 		{ 0x1e,	0, 0x2000 },
       
  5544 		{ 0x03,	0, 0x0001 },
       
  5545 		{ 0x19,	0, 0x0100 },
       
  5546 		{ 0x19,	0, 0x0004 },
       
  5547 		{ 0x0a,	0, 0x0020 }
       
  5548 	};
       
  5549 
       
  5550 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
       
  5551 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
       
  5552 
       
  5553 	/* Disable Early Tally Counter */
       
  5554 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
       
  5555 
       
  5556 	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
       
  5557 	RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
       
  5558 
       
  5559 	rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
       
  5560 
       
  5561 	rtl_pcie_state_l2l3_enable(tp, false);
       
  5562 }
       
  5563 
       
  5564 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
       
  5565 {
       
  5566 	rtl_hw_start_8105e_1(tp);
       
  5567 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
       
  5568 }
       
  5569 
       
  5570 static void rtl_hw_start_8402(struct rtl8169_private *tp)
       
  5571 {
       
  5572 	void __iomem *ioaddr = tp->mmio_addr;
       
  5573 	static const struct ephy_info e_info_8402[] = {
       
  5574 		{ 0x19,	0xffff, 0xff64 },
       
  5575 		{ 0x1e,	0, 0x4000 }
       
  5576 	};
       
  5577 
       
  5578 	rtl_csi_access_enable_2(tp);
       
  5579 
       
  5580 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
       
  5581 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
       
  5582 
       
  5583 	RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
       
  5584 	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
       
  5585 
       
  5586 	rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
       
  5587 
       
  5588 	rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
       
  5589 
       
  5590 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
       
  5591 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
       
  5592 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
       
  5593 	rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
       
  5594 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5595 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
       
  5596 	rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
       
  5597 
       
  5598 	rtl_pcie_state_l2l3_enable(tp, false);
       
  5599 }
       
  5600 
       
  5601 static void rtl_hw_start_8106(struct rtl8169_private *tp)
       
  5602 {
       
  5603 	void __iomem *ioaddr = tp->mmio_addr;
       
  5604 
       
  5605 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
       
  5606 	RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
       
  5607 
       
  5608 	RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
       
  5609 	RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
       
  5610 	RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
       
  5611 
       
  5612 	rtl_pcie_state_l2l3_enable(tp, false);
       
  5613 }
       
  5614 
       
  5615 static void rtl_hw_start_8101(struct net_device *dev)
       
  5616 {
       
  5617 	struct rtl8169_private *tp = netdev_priv(dev);
       
  5618 	void __iomem *ioaddr = tp->mmio_addr;
       
  5619 	struct pci_dev *pdev = tp->pci_dev;
       
  5620 
       
  5621 	if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
       
  5622 		tp->event_slow &= ~RxFIFOOver;
       
  5623 
       
  5624 	if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
       
  5625 	    tp->mac_version == RTL_GIGA_MAC_VER_16)
       
  5626 		pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
       
  5627 					 PCI_EXP_DEVCTL_NOSNOOP_EN);
       
  5628 
       
  5629 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  5630 
       
  5631 	RTL_W8(MaxTxPacketSize, TxPacketMax);
       
  5632 
       
  5633 	rtl_set_rx_max_size(ioaddr, rx_buf_sz);
       
  5634 
       
  5635 	tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
       
  5636 	RTL_W16(CPlusCmd, tp->cp_cmd);
       
  5637 
       
  5638 	rtl_set_rx_tx_desc_registers(tp, ioaddr);
       
  5639 
       
  5640 	rtl_set_rx_tx_config_registers(tp);
       
  5641 
       
  5642 	switch (tp->mac_version) {
       
  5643 	case RTL_GIGA_MAC_VER_07:
       
  5644 		rtl_hw_start_8102e_1(tp);
       
  5645 		break;
       
  5646 
       
  5647 	case RTL_GIGA_MAC_VER_08:
       
  5648 		rtl_hw_start_8102e_3(tp);
       
  5649 		break;
       
  5650 
       
  5651 	case RTL_GIGA_MAC_VER_09:
       
  5652 		rtl_hw_start_8102e_2(tp);
       
  5653 		break;
       
  5654 
       
  5655 	case RTL_GIGA_MAC_VER_29:
       
  5656 		rtl_hw_start_8105e_1(tp);
       
  5657 		break;
       
  5658 	case RTL_GIGA_MAC_VER_30:
       
  5659 		rtl_hw_start_8105e_2(tp);
       
  5660 		break;
       
  5661 
       
  5662 	case RTL_GIGA_MAC_VER_37:
       
  5663 		rtl_hw_start_8402(tp);
       
  5664 		break;
       
  5665 
       
  5666 	case RTL_GIGA_MAC_VER_39:
       
  5667 		rtl_hw_start_8106(tp);
       
  5668 		break;
       
  5669 	case RTL_GIGA_MAC_VER_43:
       
  5670 		rtl_hw_start_8168g_2(tp);
       
  5671 		break;
       
  5672 	}
       
  5673 
       
  5674 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  5675 
       
  5676 	RTL_W16(IntrMitigate, 0x0000);
       
  5677 
       
  5678 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
       
  5679 
       
  5680 	rtl_set_rx_mode(dev);
       
  5681 
       
  5682 	RTL_R8(IntrMask);
       
  5683 
       
  5684 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
       
  5685 }
       
  5686 
       
  5687 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
       
  5688 {
       
  5689 	struct rtl8169_private *tp = netdev_priv(dev);
       
  5690 
       
  5691 	if (new_mtu < ETH_ZLEN ||
       
  5692 	    new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
       
  5693 		return -EINVAL;
       
  5694 
       
  5695 	if (new_mtu > ETH_DATA_LEN)
       
  5696 		rtl_hw_jumbo_enable(tp);
       
  5697 	else
       
  5698 		rtl_hw_jumbo_disable(tp);
       
  5699 
       
  5700 	dev->mtu = new_mtu;
       
  5701 	netdev_update_features(dev);
       
  5702 
       
  5703 	return 0;
       
  5704 }
       
  5705 
       
  5706 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
       
  5707 {
       
  5708 	desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
       
  5709 	desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
       
  5710 }
       
  5711 
       
  5712 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
       
  5713 				     void **data_buff, struct RxDesc *desc)
       
  5714 {
       
  5715 	dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
       
  5716 			 DMA_FROM_DEVICE);
       
  5717 
       
  5718 	kfree(*data_buff);
       
  5719 	*data_buff = NULL;
       
  5720 	rtl8169_make_unusable_by_asic(desc);
       
  5721 }
       
  5722 
       
  5723 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
       
  5724 {
       
  5725 	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
       
  5726 
       
  5727 	desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
       
  5728 }
       
  5729 
       
  5730 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
       
  5731 				       u32 rx_buf_sz)
       
  5732 {
       
  5733 	desc->addr = cpu_to_le64(mapping);
       
  5734 	wmb();
       
  5735 	rtl8169_mark_to_asic(desc, rx_buf_sz);
       
  5736 }
       
  5737 
       
  5738 static inline void *rtl8169_align(void *data)
       
  5739 {
       
  5740 	return (void *)ALIGN((long)data, 16);
       
  5741 }
       
  5742 
       
  5743 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
       
  5744 					     struct RxDesc *desc)
       
  5745 {
       
  5746 	void *data;
       
  5747 	dma_addr_t mapping;
       
  5748 	struct device *d = &tp->pci_dev->dev;
       
  5749 	struct net_device *dev = tp->dev;
       
  5750 	int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
       
  5751 
       
  5752 	data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
       
  5753 	if (!data)
       
  5754 		return NULL;
       
  5755 
       
  5756 	if (rtl8169_align(data) != data) {
       
  5757 		kfree(data);
       
  5758 		data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
       
  5759 		if (!data)
       
  5760 			return NULL;
       
  5761 	}
       
  5762 
       
  5763 	mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
       
  5764 				 DMA_FROM_DEVICE);
       
  5765 	if (unlikely(dma_mapping_error(d, mapping))) {
       
  5766 		if (net_ratelimit())
       
  5767 			netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
       
  5768 		goto err_out;
       
  5769 	}
       
  5770 
       
  5771 	rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
       
  5772 	return data;
       
  5773 
       
  5774 err_out:
       
  5775 	kfree(data);
       
  5776 	return NULL;
       
  5777 }
       
  5778 
       
  5779 static void rtl8169_rx_clear(struct rtl8169_private *tp)
       
  5780 {
       
  5781 	unsigned int i;
       
  5782 
       
  5783 	for (i = 0; i < NUM_RX_DESC; i++) {
       
  5784 		if (tp->Rx_databuff[i]) {
       
  5785 			rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
       
  5786 					    tp->RxDescArray + i);
       
  5787 		}
       
  5788 	}
       
  5789 }
       
  5790 
       
  5791 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
       
  5792 {
       
  5793 	desc->opts1 |= cpu_to_le32(RingEnd);
       
  5794 }
       
  5795 
       
  5796 static int rtl8169_rx_fill(struct rtl8169_private *tp)
       
  5797 {
       
  5798 	unsigned int i;
       
  5799 
       
  5800 	for (i = 0; i < NUM_RX_DESC; i++) {
       
  5801 		void *data;
       
  5802 
       
  5803 		if (tp->Rx_databuff[i])
       
  5804 			continue;
       
  5805 
       
  5806 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
       
  5807 		if (!data) {
       
  5808 			rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
       
  5809 			goto err_out;
       
  5810 		}
       
  5811 		tp->Rx_databuff[i] = data;
       
  5812 	}
       
  5813 
       
  5814 	rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
       
  5815 	return 0;
       
  5816 
       
  5817 err_out:
       
  5818 	rtl8169_rx_clear(tp);
       
  5819 	return -ENOMEM;
       
  5820 }
       
  5821 
       
  5822 static int rtl8169_init_ring(struct net_device *dev)
       
  5823 {
       
  5824 	struct rtl8169_private *tp = netdev_priv(dev);
       
  5825 
       
  5826 	rtl8169_init_ring_indexes(tp);
       
  5827 
       
  5828 	memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
       
  5829 	memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
       
  5830 
       
  5831 	return rtl8169_rx_fill(tp);
       
  5832 }
       
  5833 
       
  5834 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
       
  5835 				 struct TxDesc *desc)
       
  5836 {
       
  5837 	unsigned int len = tx_skb->len;
       
  5838 
       
  5839 	dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
       
  5840 
       
  5841 	desc->opts1 = 0x00;
       
  5842 	desc->opts2 = 0x00;
       
  5843 	desc->addr = 0x00;
       
  5844 	tx_skb->len = 0;
       
  5845 }
       
  5846 
       
  5847 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
       
  5848 				   unsigned int n)
       
  5849 {
       
  5850 	unsigned int i;
       
  5851 
       
  5852 	for (i = 0; i < n; i++) {
       
  5853 		unsigned int entry = (start + i) % NUM_TX_DESC;
       
  5854 		struct ring_info *tx_skb = tp->tx_skb + entry;
       
  5855 		unsigned int len = tx_skb->len;
       
  5856 
       
  5857 		if (len) {
       
  5858 			struct sk_buff *skb = tx_skb->skb;
       
  5859 
       
  5860 			rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
       
  5861 					     tp->TxDescArray + entry);
       
  5862 			if (skb) {
       
  5863 				tp->dev->stats.tx_dropped++;
       
  5864 				dev_kfree_skb_any(skb);
       
  5865 				tx_skb->skb = NULL;
       
  5866 			}
       
  5867 		}
       
  5868 	}
       
  5869 }
       
  5870 
       
  5871 static void rtl8169_tx_clear(struct rtl8169_private *tp)
       
  5872 {
       
  5873 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
       
  5874 	tp->cur_tx = tp->dirty_tx = 0;
       
  5875 }
       
  5876 
       
  5877 static void rtl_reset_work(struct rtl8169_private *tp)
       
  5878 {
       
  5879 	struct net_device *dev = tp->dev;
       
  5880 	int i;
       
  5881 
       
  5882 	napi_disable(&tp->napi);
       
  5883 	netif_stop_queue(dev);
       
  5884 	synchronize_sched();
       
  5885 
       
  5886 	rtl8169_hw_reset(tp);
       
  5887 
       
  5888 	for (i = 0; i < NUM_RX_DESC; i++)
       
  5889 		rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
       
  5890 
       
  5891 	rtl8169_tx_clear(tp);
       
  5892 	rtl8169_init_ring_indexes(tp);
       
  5893 
       
  5894 	napi_enable(&tp->napi);
       
  5895 	rtl_hw_start(dev);
       
  5896 	netif_wake_queue(dev);
       
  5897 	rtl8169_check_link_status(dev, tp, tp->mmio_addr);
       
  5898 }
       
  5899 
       
  5900 static void rtl8169_tx_timeout(struct net_device *dev)
       
  5901 {
       
  5902 	struct rtl8169_private *tp = netdev_priv(dev);
       
  5903 
       
  5904 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
       
  5905 }
       
  5906 
       
  5907 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
       
  5908 			      u32 *opts)
       
  5909 {
       
  5910 	struct skb_shared_info *info = skb_shinfo(skb);
       
  5911 	unsigned int cur_frag, entry;
       
  5912 	struct TxDesc * uninitialized_var(txd);
       
  5913 	struct device *d = &tp->pci_dev->dev;
       
  5914 
       
  5915 	entry = tp->cur_tx;
       
  5916 	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
       
  5917 		const skb_frag_t *frag = info->frags + cur_frag;
       
  5918 		dma_addr_t mapping;
       
  5919 		u32 status, len;
       
  5920 		void *addr;
       
  5921 
       
  5922 		entry = (entry + 1) % NUM_TX_DESC;
       
  5923 
       
  5924 		txd = tp->TxDescArray + entry;
       
  5925 		len = skb_frag_size(frag);
       
  5926 		addr = skb_frag_address(frag);
       
  5927 		mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
       
  5928 		if (unlikely(dma_mapping_error(d, mapping))) {
       
  5929 			if (net_ratelimit())
       
  5930 				netif_err(tp, drv, tp->dev,
       
  5931 					  "Failed to map TX fragments DMA!\n");
       
  5932 			goto err_out;
       
  5933 		}
       
  5934 
       
  5935 		/* Anti gcc 2.95.3 bugware (sic) */
       
  5936 		status = opts[0] | len |
       
  5937 			(RingEnd * !((entry + 1) % NUM_TX_DESC));
       
  5938 
       
  5939 		txd->opts1 = cpu_to_le32(status);
       
  5940 		txd->opts2 = cpu_to_le32(opts[1]);
       
  5941 		txd->addr = cpu_to_le64(mapping);
       
  5942 
       
  5943 		tp->tx_skb[entry].len = len;
       
  5944 	}
       
  5945 
       
  5946 	if (cur_frag) {
       
  5947 		tp->tx_skb[entry].skb = skb;
       
  5948 		txd->opts1 |= cpu_to_le32(LastFrag);
       
  5949 	}
       
  5950 
       
  5951 	return cur_frag;
       
  5952 
       
  5953 err_out:
       
  5954 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
       
  5955 	return -EIO;
       
  5956 }
       
  5957 
       
  5958 static bool rtl_skb_pad(struct sk_buff *skb)
       
  5959 {
       
  5960 	if (skb_padto(skb, ETH_ZLEN))
       
  5961 		return false;
       
  5962 	skb_put(skb, ETH_ZLEN - skb->len);
       
  5963 	return true;
       
  5964 }
       
  5965 
       
  5966 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
       
  5967 {
       
  5968 	return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
       
  5969 }
       
  5970 
       
  5971 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
       
  5972 				    struct sk_buff *skb, u32 *opts)
       
  5973 {
       
  5974 	const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
       
  5975 	u32 mss = skb_shinfo(skb)->gso_size;
       
  5976 	int offset = info->opts_offset;
       
  5977 
       
  5978 	if (mss) {
       
  5979 		opts[0] |= TD_LSO;
       
  5980 		opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
       
  5981 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
       
  5982 		const struct iphdr *ip = ip_hdr(skb);
       
  5983 
       
  5984 		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
       
  5985 			return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
       
  5986 
       
  5987 		if (ip->protocol == IPPROTO_TCP)
       
  5988 			opts[offset] |= info->checksum.tcp;
       
  5989 		else if (ip->protocol == IPPROTO_UDP)
       
  5990 			opts[offset] |= info->checksum.udp;
       
  5991 		else
       
  5992 			WARN_ON_ONCE(1);
       
  5993 	} else {
       
  5994 		if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
       
  5995 			return rtl_skb_pad(skb);
       
  5996 	}
       
  5997 	return true;
       
  5998 }
       
  5999 
       
  6000 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
       
  6001 				      struct net_device *dev)
       
  6002 {
       
  6003 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6004 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
       
  6005 	struct TxDesc *txd = tp->TxDescArray + entry;
       
  6006 	void __iomem *ioaddr = tp->mmio_addr;
       
  6007 	struct device *d = &tp->pci_dev->dev;
       
  6008 	dma_addr_t mapping;
       
  6009 	u32 status, len;
       
  6010 	u32 opts[2];
       
  6011 	int frags;
       
  6012 
       
  6013 	if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
       
  6014 		netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
       
  6015 		goto err_stop_0;
       
  6016 	}
       
  6017 
       
  6018 	if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
       
  6019 		goto err_stop_0;
       
  6020 
       
  6021 	opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
       
  6022 	opts[0] = DescOwn;
       
  6023 
       
  6024 	if (!rtl8169_tso_csum(tp, skb, opts))
       
  6025 		goto err_update_stats;
       
  6026 
       
  6027 	len = skb_headlen(skb);
       
  6028 	mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
       
  6029 	if (unlikely(dma_mapping_error(d, mapping))) {
       
  6030 		if (net_ratelimit())
       
  6031 			netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
       
  6032 		goto err_dma_0;
       
  6033 	}
       
  6034 
       
  6035 	tp->tx_skb[entry].len = len;
       
  6036 	txd->addr = cpu_to_le64(mapping);
       
  6037 
       
  6038 	frags = rtl8169_xmit_frags(tp, skb, opts);
       
  6039 	if (frags < 0)
       
  6040 		goto err_dma_1;
       
  6041 	else if (frags)
       
  6042 		opts[0] |= FirstFrag;
       
  6043 	else {
       
  6044 		opts[0] |= FirstFrag | LastFrag;
       
  6045 		tp->tx_skb[entry].skb = skb;
       
  6046 	}
       
  6047 
       
  6048 	txd->opts2 = cpu_to_le32(opts[1]);
       
  6049 
       
  6050 	skb_tx_timestamp(skb);
       
  6051 
       
  6052 	wmb();
       
  6053 
       
  6054 	/* Anti gcc 2.95.3 bugware (sic) */
       
  6055 	status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
       
  6056 	txd->opts1 = cpu_to_le32(status);
       
  6057 
       
  6058 	tp->cur_tx += frags + 1;
       
  6059 
       
  6060 	wmb();
       
  6061 
       
  6062 	RTL_W8(TxPoll, NPQ);
       
  6063 
       
  6064 	mmiowb();
       
  6065 
       
  6066 	if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
       
  6067 		/* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
       
  6068 		 * not miss a ring update when it notices a stopped queue.
       
  6069 		 */
       
  6070 		smp_wmb();
       
  6071 		netif_stop_queue(dev);
       
  6072 		/* Sync with rtl_tx:
       
  6073 		 * - publish queue status and cur_tx ring index (write barrier)
       
  6074 		 * - refresh dirty_tx ring index (read barrier).
       
  6075 		 * May the current thread have a pessimistic view of the ring
       
  6076 		 * status and forget to wake up queue, a racing rtl_tx thread
       
  6077 		 * can't.
       
  6078 		 */
       
  6079 		smp_mb();
       
  6080 		if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
       
  6081 			netif_wake_queue(dev);
       
  6082 	}
       
  6083 
       
  6084 	return NETDEV_TX_OK;
       
  6085 
       
  6086 err_dma_1:
       
  6087 	rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
       
  6088 err_dma_0:
       
  6089 	dev_kfree_skb_any(skb);
       
  6090 err_update_stats:
       
  6091 	dev->stats.tx_dropped++;
       
  6092 	return NETDEV_TX_OK;
       
  6093 
       
  6094 err_stop_0:
       
  6095 	netif_stop_queue(dev);
       
  6096 	dev->stats.tx_dropped++;
       
  6097 	return NETDEV_TX_BUSY;
       
  6098 }
       
  6099 
       
  6100 static void rtl8169_pcierr_interrupt(struct net_device *dev)
       
  6101 {
       
  6102 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6103 	struct pci_dev *pdev = tp->pci_dev;
       
  6104 	u16 pci_status, pci_cmd;
       
  6105 
       
  6106 	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
       
  6107 	pci_read_config_word(pdev, PCI_STATUS, &pci_status);
       
  6108 
       
  6109 	netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
       
  6110 		  pci_cmd, pci_status);
       
  6111 
       
  6112 	/*
       
  6113 	 * The recovery sequence below admits a very elaborated explanation:
       
  6114 	 * - it seems to work;
       
  6115 	 * - I did not see what else could be done;
       
  6116 	 * - it makes iop3xx happy.
       
  6117 	 *
       
  6118 	 * Feel free to adjust to your needs.
       
  6119 	 */
       
  6120 	if (pdev->broken_parity_status)
       
  6121 		pci_cmd &= ~PCI_COMMAND_PARITY;
       
  6122 	else
       
  6123 		pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
       
  6124 
       
  6125 	pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
       
  6126 
       
  6127 	pci_write_config_word(pdev, PCI_STATUS,
       
  6128 		pci_status & (PCI_STATUS_DETECTED_PARITY |
       
  6129 		PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
       
  6130 		PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
       
  6131 
       
  6132 	/* The infamous DAC f*ckup only happens at boot time */
       
  6133 	if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
       
  6134 		void __iomem *ioaddr = tp->mmio_addr;
       
  6135 
       
  6136 		netif_info(tp, intr, dev, "disabling PCI DAC\n");
       
  6137 		tp->cp_cmd &= ~PCIDAC;
       
  6138 		RTL_W16(CPlusCmd, tp->cp_cmd);
       
  6139 		dev->features &= ~NETIF_F_HIGHDMA;
       
  6140 	}
       
  6141 
       
  6142 	rtl8169_hw_reset(tp);
       
  6143 
       
  6144 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
       
  6145 }
       
  6146 
       
  6147 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
       
  6148 {
       
  6149 	unsigned int dirty_tx, tx_left;
       
  6150 
       
  6151 	dirty_tx = tp->dirty_tx;
       
  6152 	smp_rmb();
       
  6153 	tx_left = tp->cur_tx - dirty_tx;
       
  6154 
       
  6155 	while (tx_left > 0) {
       
  6156 		unsigned int entry = dirty_tx % NUM_TX_DESC;
       
  6157 		struct ring_info *tx_skb = tp->tx_skb + entry;
       
  6158 		u32 status;
       
  6159 
       
  6160 		rmb();
       
  6161 		status = le32_to_cpu(tp->TxDescArray[entry].opts1);
       
  6162 		if (status & DescOwn)
       
  6163 			break;
       
  6164 
       
  6165 		rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
       
  6166 				     tp->TxDescArray + entry);
       
  6167 		if (status & LastFrag) {
       
  6168 			u64_stats_update_begin(&tp->tx_stats.syncp);
       
  6169 			tp->tx_stats.packets++;
       
  6170 			tp->tx_stats.bytes += tx_skb->skb->len;
       
  6171 			u64_stats_update_end(&tp->tx_stats.syncp);
       
  6172 			dev_kfree_skb_any(tx_skb->skb);
       
  6173 			tx_skb->skb = NULL;
       
  6174 		}
       
  6175 		dirty_tx++;
       
  6176 		tx_left--;
       
  6177 	}
       
  6178 
       
  6179 	if (tp->dirty_tx != dirty_tx) {
       
  6180 		tp->dirty_tx = dirty_tx;
       
  6181 		/* Sync with rtl8169_start_xmit:
       
  6182 		 * - publish dirty_tx ring index (write barrier)
       
  6183 		 * - refresh cur_tx ring index and queue status (read barrier)
       
  6184 		 * May the current thread miss the stopped queue condition,
       
  6185 		 * a racing xmit thread can only have a right view of the
       
  6186 		 * ring status.
       
  6187 		 */
       
  6188 		smp_mb();
       
  6189 		if (netif_queue_stopped(dev) &&
       
  6190 		    TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
       
  6191 			netif_wake_queue(dev);
       
  6192 		}
       
  6193 		/*
       
  6194 		 * 8168 hack: TxPoll requests are lost when the Tx packets are
       
  6195 		 * too close. Let's kick an extra TxPoll request when a burst
       
  6196 		 * of start_xmit activity is detected (if it is not detected,
       
  6197 		 * it is slow enough). -- FR
       
  6198 		 */
       
  6199 		if (tp->cur_tx != dirty_tx) {
       
  6200 			void __iomem *ioaddr = tp->mmio_addr;
       
  6201 
       
  6202 			RTL_W8(TxPoll, NPQ);
       
  6203 		}
       
  6204 	}
       
  6205 }
       
  6206 
       
  6207 static inline int rtl8169_fragmented_frame(u32 status)
       
  6208 {
       
  6209 	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
       
  6210 }
       
  6211 
       
  6212 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
       
  6213 {
       
  6214 	u32 status = opts1 & RxProtoMask;
       
  6215 
       
  6216 	if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
       
  6217 	    ((status == RxProtoUDP) && !(opts1 & UDPFail)))
       
  6218 		skb->ip_summed = CHECKSUM_UNNECESSARY;
       
  6219 	else
       
  6220 		skb_checksum_none_assert(skb);
       
  6221 }
       
  6222 
       
  6223 static struct sk_buff *rtl8169_try_rx_copy(void *data,
       
  6224 					   struct rtl8169_private *tp,
       
  6225 					   int pkt_size,
       
  6226 					   dma_addr_t addr)
       
  6227 {
       
  6228 	struct sk_buff *skb;
       
  6229 	struct device *d = &tp->pci_dev->dev;
       
  6230 
       
  6231 	data = rtl8169_align(data);
       
  6232 	dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
       
  6233 	prefetch(data);
       
  6234 	skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
       
  6235 	if (skb)
       
  6236 		memcpy(skb->data, data, pkt_size);
       
  6237 	dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
       
  6238 
       
  6239 	return skb;
       
  6240 }
       
  6241 
       
  6242 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
       
  6243 {
       
  6244 	unsigned int cur_rx, rx_left;
       
  6245 	unsigned int count;
       
  6246 
       
  6247 	cur_rx = tp->cur_rx;
       
  6248 
       
  6249 	for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
       
  6250 		unsigned int entry = cur_rx % NUM_RX_DESC;
       
  6251 		struct RxDesc *desc = tp->RxDescArray + entry;
       
  6252 		u32 status;
       
  6253 
       
  6254 		rmb();
       
  6255 		status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
       
  6256 
       
  6257 		if (status & DescOwn)
       
  6258 			break;
       
  6259 		if (unlikely(status & RxRES)) {
       
  6260 			netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
       
  6261 				   status);
       
  6262 			dev->stats.rx_errors++;
       
  6263 			if (status & (RxRWT | RxRUNT))
       
  6264 				dev->stats.rx_length_errors++;
       
  6265 			if (status & RxCRC)
       
  6266 				dev->stats.rx_crc_errors++;
       
  6267 			if (status & RxFOVF) {
       
  6268 				rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
       
  6269 				dev->stats.rx_fifo_errors++;
       
  6270 			}
       
  6271 			if ((status & (RxRUNT | RxCRC)) &&
       
  6272 			    !(status & (RxRWT | RxFOVF)) &&
       
  6273 			    (dev->features & NETIF_F_RXALL))
       
  6274 				goto process_pkt;
       
  6275 		} else {
       
  6276 			struct sk_buff *skb;
       
  6277 			dma_addr_t addr;
       
  6278 			int pkt_size;
       
  6279 
       
  6280 process_pkt:
       
  6281 			addr = le64_to_cpu(desc->addr);
       
  6282 			if (likely(!(dev->features & NETIF_F_RXFCS)))
       
  6283 				pkt_size = (status & 0x00003fff) - 4;
       
  6284 			else
       
  6285 				pkt_size = status & 0x00003fff;
       
  6286 
       
  6287 			/*
       
  6288 			 * The driver does not support incoming fragmented
       
  6289 			 * frames. They are seen as a symptom of over-mtu
       
  6290 			 * sized frames.
       
  6291 			 */
       
  6292 			if (unlikely(rtl8169_fragmented_frame(status))) {
       
  6293 				dev->stats.rx_dropped++;
       
  6294 				dev->stats.rx_length_errors++;
       
  6295 				goto release_descriptor;
       
  6296 			}
       
  6297 
       
  6298 			skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
       
  6299 						  tp, pkt_size, addr);
       
  6300 			if (!skb) {
       
  6301 				dev->stats.rx_dropped++;
       
  6302 				goto release_descriptor;
       
  6303 			}
       
  6304 
       
  6305 			rtl8169_rx_csum(skb, status);
       
  6306 			skb_put(skb, pkt_size);
       
  6307 			skb->protocol = eth_type_trans(skb, dev);
       
  6308 
       
  6309 			rtl8169_rx_vlan_tag(desc, skb);
       
  6310 
       
  6311 			napi_gro_receive(&tp->napi, skb);
       
  6312 
       
  6313 			u64_stats_update_begin(&tp->rx_stats.syncp);
       
  6314 			tp->rx_stats.packets++;
       
  6315 			tp->rx_stats.bytes += pkt_size;
       
  6316 			u64_stats_update_end(&tp->rx_stats.syncp);
       
  6317 		}
       
  6318 release_descriptor:
       
  6319 		desc->opts2 = 0;
       
  6320 		wmb();
       
  6321 		rtl8169_mark_to_asic(desc, rx_buf_sz);
       
  6322 	}
       
  6323 
       
  6324 	count = cur_rx - tp->cur_rx;
       
  6325 	tp->cur_rx = cur_rx;
       
  6326 
       
  6327 	return count;
       
  6328 }
       
  6329 
       
  6330 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
       
  6331 {
       
  6332 	struct net_device *dev = dev_instance;
       
  6333 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6334 	int handled = 0;
       
  6335 	u16 status;
       
  6336 
       
  6337 	status = rtl_get_events(tp);
       
  6338 	if (status && status != 0xffff) {
       
  6339 		status &= RTL_EVENT_NAPI | tp->event_slow;
       
  6340 		if (status) {
       
  6341 			handled = 1;
       
  6342 
       
  6343 			rtl_irq_disable(tp);
       
  6344 			napi_schedule(&tp->napi);
       
  6345 		}
       
  6346 	}
       
  6347 	return IRQ_RETVAL(handled);
       
  6348 }
       
  6349 
       
  6350 /*
       
  6351  * Workqueue context.
       
  6352  */
       
  6353 static void rtl_slow_event_work(struct rtl8169_private *tp)
       
  6354 {
       
  6355 	struct net_device *dev = tp->dev;
       
  6356 	u16 status;
       
  6357 
       
  6358 	status = rtl_get_events(tp) & tp->event_slow;
       
  6359 	rtl_ack_events(tp, status);
       
  6360 
       
  6361 	if (unlikely(status & RxFIFOOver)) {
       
  6362 		switch (tp->mac_version) {
       
  6363 		/* Work around for rx fifo overflow */
       
  6364 		case RTL_GIGA_MAC_VER_11:
       
  6365 			netif_stop_queue(dev);
       
  6366 			/* XXX - Hack alert. See rtl_task(). */
       
  6367 			set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
       
  6368 		default:
       
  6369 			break;
       
  6370 		}
       
  6371 	}
       
  6372 
       
  6373 	if (unlikely(status & SYSErr))
       
  6374 		rtl8169_pcierr_interrupt(dev);
       
  6375 
       
  6376 	if (status & LinkChg)
       
  6377 		__rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
       
  6378 
       
  6379 	rtl_irq_enable_all(tp);
       
  6380 }
       
  6381 
       
  6382 static void rtl_task(struct work_struct *work)
       
  6383 {
       
  6384 	static const struct {
       
  6385 		int bitnr;
       
  6386 		void (*action)(struct rtl8169_private *);
       
  6387 	} rtl_work[] = {
       
  6388 		/* XXX - keep rtl_slow_event_work() as first element. */
       
  6389 		{ RTL_FLAG_TASK_SLOW_PENDING,	rtl_slow_event_work },
       
  6390 		{ RTL_FLAG_TASK_RESET_PENDING,	rtl_reset_work },
       
  6391 		{ RTL_FLAG_TASK_PHY_PENDING,	rtl_phy_work }
       
  6392 	};
       
  6393 	struct rtl8169_private *tp =
       
  6394 		container_of(work, struct rtl8169_private, wk.work);
       
  6395 	struct net_device *dev = tp->dev;
       
  6396 	int i;
       
  6397 
       
  6398 	rtl_lock_work(tp);
       
  6399 
       
  6400 	if (!netif_running(dev) ||
       
  6401 	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
       
  6402 		goto out_unlock;
       
  6403 
       
  6404 	for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
       
  6405 		bool pending;
       
  6406 
       
  6407 		pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
       
  6408 		if (pending)
       
  6409 			rtl_work[i].action(tp);
       
  6410 	}
       
  6411 
       
  6412 out_unlock:
       
  6413 	rtl_unlock_work(tp);
       
  6414 }
       
  6415 
       
  6416 static int rtl8169_poll(struct napi_struct *napi, int budget)
       
  6417 {
       
  6418 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
       
  6419 	struct net_device *dev = tp->dev;
       
  6420 	u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
       
  6421 	int work_done= 0;
       
  6422 	u16 status;
       
  6423 
       
  6424 	status = rtl_get_events(tp);
       
  6425 	rtl_ack_events(tp, status & ~tp->event_slow);
       
  6426 
       
  6427 	if (status & RTL_EVENT_NAPI_RX)
       
  6428 		work_done = rtl_rx(dev, tp, (u32) budget);
       
  6429 
       
  6430 	if (status & RTL_EVENT_NAPI_TX)
       
  6431 		rtl_tx(dev, tp);
       
  6432 
       
  6433 	if (status & tp->event_slow) {
       
  6434 		enable_mask &= ~tp->event_slow;
       
  6435 
       
  6436 		rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
       
  6437 	}
       
  6438 
       
  6439 	if (work_done < budget) {
       
  6440 		napi_complete(napi);
       
  6441 
       
  6442 		rtl_irq_enable(tp, enable_mask);
       
  6443 		mmiowb();
       
  6444 	}
       
  6445 
       
  6446 	return work_done;
       
  6447 }
       
  6448 
       
  6449 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
       
  6450 {
       
  6451 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6452 
       
  6453 	if (tp->mac_version > RTL_GIGA_MAC_VER_06)
       
  6454 		return;
       
  6455 
       
  6456 	dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
       
  6457 	RTL_W32(RxMissed, 0);
       
  6458 }
       
  6459 
       
  6460 static void rtl8169_down(struct net_device *dev)
       
  6461 {
       
  6462 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6463 	void __iomem *ioaddr = tp->mmio_addr;
       
  6464 
       
  6465 	del_timer_sync(&tp->timer);
       
  6466 
       
  6467 	napi_disable(&tp->napi);
       
  6468 	netif_stop_queue(dev);
       
  6469 
       
  6470 	rtl8169_hw_reset(tp);
       
  6471 	/*
       
  6472 	 * At this point device interrupts can not be enabled in any function,
       
  6473 	 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
       
  6474 	 * and napi is disabled (rtl8169_poll).
       
  6475 	 */
       
  6476 	rtl8169_rx_missed(dev, ioaddr);
       
  6477 
       
  6478 	/* Give a racing hard_start_xmit a few cycles to complete. */
       
  6479 	synchronize_sched();
       
  6480 
       
  6481 	rtl8169_tx_clear(tp);
       
  6482 
       
  6483 	rtl8169_rx_clear(tp);
       
  6484 
       
  6485 	rtl_pll_power_down(tp);
       
  6486 }
       
  6487 
       
  6488 static int rtl8169_close(struct net_device *dev)
       
  6489 {
       
  6490 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6491 	struct pci_dev *pdev = tp->pci_dev;
       
  6492 
       
  6493 	pm_runtime_get_sync(&pdev->dev);
       
  6494 
       
  6495 	/* Update counters before going down */
       
  6496 	rtl8169_update_counters(dev);
       
  6497 
       
  6498 	rtl_lock_work(tp);
       
  6499 	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
       
  6500 
       
  6501 	rtl8169_down(dev);
       
  6502 	rtl_unlock_work(tp);
       
  6503 
       
  6504 	cancel_work_sync(&tp->wk.work);
       
  6505 
       
  6506 	free_irq(pdev->irq, dev);
       
  6507 
       
  6508 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
       
  6509 			  tp->RxPhyAddr);
       
  6510 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
       
  6511 			  tp->TxPhyAddr);
       
  6512 	tp->TxDescArray = NULL;
       
  6513 	tp->RxDescArray = NULL;
       
  6514 
       
  6515 	pm_runtime_put_sync(&pdev->dev);
       
  6516 
       
  6517 	return 0;
       
  6518 }
       
  6519 
       
  6520 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  6521 static void rtl8169_netpoll(struct net_device *dev)
       
  6522 {
       
  6523 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6524 
       
  6525 	rtl8169_interrupt(tp->pci_dev->irq, dev);
       
  6526 }
       
  6527 #endif
       
  6528 
       
  6529 static int rtl_open(struct net_device *dev)
       
  6530 {
       
  6531 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6532 	void __iomem *ioaddr = tp->mmio_addr;
       
  6533 	struct pci_dev *pdev = tp->pci_dev;
       
  6534 	int retval = -ENOMEM;
       
  6535 
       
  6536 	pm_runtime_get_sync(&pdev->dev);
       
  6537 
       
  6538 	/*
       
  6539 	 * Rx and Tx descriptors needs 256 bytes alignment.
       
  6540 	 * dma_alloc_coherent provides more.
       
  6541 	 */
       
  6542 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
       
  6543 					     &tp->TxPhyAddr, GFP_KERNEL);
       
  6544 	if (!tp->TxDescArray)
       
  6545 		goto err_pm_runtime_put;
       
  6546 
       
  6547 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
       
  6548 					     &tp->RxPhyAddr, GFP_KERNEL);
       
  6549 	if (!tp->RxDescArray)
       
  6550 		goto err_free_tx_0;
       
  6551 
       
  6552 	retval = rtl8169_init_ring(dev);
       
  6553 	if (retval < 0)
       
  6554 		goto err_free_rx_1;
       
  6555 
       
  6556 	INIT_WORK(&tp->wk.work, rtl_task);
       
  6557 
       
  6558 	smp_mb();
       
  6559 
       
  6560 	rtl_request_firmware(tp);
       
  6561 
       
  6562 	retval = request_irq(pdev->irq, rtl8169_interrupt,
       
  6563 			     (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
       
  6564 			     dev->name, dev);
       
  6565 	if (retval < 0)
       
  6566 		goto err_release_fw_2;
       
  6567 
       
  6568 	rtl_lock_work(tp);
       
  6569 
       
  6570 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
       
  6571 
       
  6572 	napi_enable(&tp->napi);
       
  6573 
       
  6574 	rtl8169_init_phy(dev, tp);
       
  6575 
       
  6576 	__rtl8169_set_features(dev, dev->features);
       
  6577 
       
  6578 	rtl_pll_power_up(tp);
       
  6579 
       
  6580 	rtl_hw_start(dev);
       
  6581 
       
  6582 	netif_start_queue(dev);
       
  6583 
       
  6584 	rtl_unlock_work(tp);
       
  6585 
       
  6586 	tp->saved_wolopts = 0;
       
  6587 	pm_runtime_put_noidle(&pdev->dev);
       
  6588 
       
  6589 	rtl8169_check_link_status(dev, tp, ioaddr);
       
  6590 out:
       
  6591 	return retval;
       
  6592 
       
  6593 err_release_fw_2:
       
  6594 	rtl_release_firmware(tp);
       
  6595 	rtl8169_rx_clear(tp);
       
  6596 err_free_rx_1:
       
  6597 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
       
  6598 			  tp->RxPhyAddr);
       
  6599 	tp->RxDescArray = NULL;
       
  6600 err_free_tx_0:
       
  6601 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
       
  6602 			  tp->TxPhyAddr);
       
  6603 	tp->TxDescArray = NULL;
       
  6604 err_pm_runtime_put:
       
  6605 	pm_runtime_put_noidle(&pdev->dev);
       
  6606 	goto out;
       
  6607 }
       
  6608 
       
  6609 static struct rtnl_link_stats64 *
       
  6610 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
       
  6611 {
       
  6612 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6613 	void __iomem *ioaddr = tp->mmio_addr;
       
  6614 	unsigned int start;
       
  6615 
       
  6616 	if (netif_running(dev))
       
  6617 		rtl8169_rx_missed(dev, ioaddr);
       
  6618 
       
  6619 	do {
       
  6620 		start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
       
  6621 		stats->rx_packets = tp->rx_stats.packets;
       
  6622 		stats->rx_bytes	= tp->rx_stats.bytes;
       
  6623 	} while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
       
  6624 
       
  6625 
       
  6626 	do {
       
  6627 		start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
       
  6628 		stats->tx_packets = tp->tx_stats.packets;
       
  6629 		stats->tx_bytes	= tp->tx_stats.bytes;
       
  6630 	} while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
       
  6631 
       
  6632 	stats->rx_dropped	= dev->stats.rx_dropped;
       
  6633 	stats->tx_dropped	= dev->stats.tx_dropped;
       
  6634 	stats->rx_length_errors = dev->stats.rx_length_errors;
       
  6635 	stats->rx_errors	= dev->stats.rx_errors;
       
  6636 	stats->rx_crc_errors	= dev->stats.rx_crc_errors;
       
  6637 	stats->rx_fifo_errors	= dev->stats.rx_fifo_errors;
       
  6638 	stats->rx_missed_errors = dev->stats.rx_missed_errors;
       
  6639 
       
  6640 	return stats;
       
  6641 }
       
  6642 
       
  6643 static void rtl8169_net_suspend(struct net_device *dev)
       
  6644 {
       
  6645 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6646 
       
  6647 	if (!netif_running(dev))
       
  6648 		return;
       
  6649 
       
  6650 	netif_device_detach(dev);
       
  6651 	netif_stop_queue(dev);
       
  6652 
       
  6653 	rtl_lock_work(tp);
       
  6654 	napi_disable(&tp->napi);
       
  6655 	clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
       
  6656 	rtl_unlock_work(tp);
       
  6657 
       
  6658 	rtl_pll_power_down(tp);
       
  6659 }
       
  6660 
       
  6661 #ifdef CONFIG_PM
       
  6662 
       
  6663 static int rtl8169_suspend(struct device *device)
       
  6664 {
       
  6665 	struct pci_dev *pdev = to_pci_dev(device);
       
  6666 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6667 
       
  6668 	rtl8169_net_suspend(dev);
       
  6669 
       
  6670 	return 0;
       
  6671 }
       
  6672 
       
  6673 static void __rtl8169_resume(struct net_device *dev)
       
  6674 {
       
  6675 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6676 
       
  6677 	netif_device_attach(dev);
       
  6678 
       
  6679 	rtl_pll_power_up(tp);
       
  6680 
       
  6681 	rtl_lock_work(tp);
       
  6682 	napi_enable(&tp->napi);
       
  6683 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
       
  6684 	rtl_unlock_work(tp);
       
  6685 
       
  6686 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
       
  6687 }
       
  6688 
       
  6689 static int rtl8169_resume(struct device *device)
       
  6690 {
       
  6691 	struct pci_dev *pdev = to_pci_dev(device);
       
  6692 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6693 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6694 
       
  6695 	rtl8169_init_phy(dev, tp);
       
  6696 
       
  6697 	if (netif_running(dev))
       
  6698 		__rtl8169_resume(dev);
       
  6699 
       
  6700 	return 0;
       
  6701 }
       
  6702 
       
  6703 static int rtl8169_runtime_suspend(struct device *device)
       
  6704 {
       
  6705 	struct pci_dev *pdev = to_pci_dev(device);
       
  6706 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6707 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6708 
       
  6709 	if (!tp->TxDescArray)
       
  6710 		return 0;
       
  6711 
       
  6712 	rtl_lock_work(tp);
       
  6713 	tp->saved_wolopts = __rtl8169_get_wol(tp);
       
  6714 	__rtl8169_set_wol(tp, WAKE_ANY);
       
  6715 	rtl_unlock_work(tp);
       
  6716 
       
  6717 	rtl8169_net_suspend(dev);
       
  6718 
       
  6719 	return 0;
       
  6720 }
       
  6721 
       
  6722 static int rtl8169_runtime_resume(struct device *device)
       
  6723 {
       
  6724 	struct pci_dev *pdev = to_pci_dev(device);
       
  6725 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6726 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6727 
       
  6728 	if (!tp->TxDescArray)
       
  6729 		return 0;
       
  6730 
       
  6731 	rtl_lock_work(tp);
       
  6732 	__rtl8169_set_wol(tp, tp->saved_wolopts);
       
  6733 	tp->saved_wolopts = 0;
       
  6734 	rtl_unlock_work(tp);
       
  6735 
       
  6736 	rtl8169_init_phy(dev, tp);
       
  6737 
       
  6738 	__rtl8169_resume(dev);
       
  6739 
       
  6740 	return 0;
       
  6741 }
       
  6742 
       
  6743 static int rtl8169_runtime_idle(struct device *device)
       
  6744 {
       
  6745 	struct pci_dev *pdev = to_pci_dev(device);
       
  6746 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6747 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6748 
       
  6749 	return tp->TxDescArray ? -EBUSY : 0;
       
  6750 }
       
  6751 
       
  6752 static const struct dev_pm_ops rtl8169_pm_ops = {
       
  6753 	.suspend		= rtl8169_suspend,
       
  6754 	.resume			= rtl8169_resume,
       
  6755 	.freeze			= rtl8169_suspend,
       
  6756 	.thaw			= rtl8169_resume,
       
  6757 	.poweroff		= rtl8169_suspend,
       
  6758 	.restore		= rtl8169_resume,
       
  6759 	.runtime_suspend	= rtl8169_runtime_suspend,
       
  6760 	.runtime_resume		= rtl8169_runtime_resume,
       
  6761 	.runtime_idle		= rtl8169_runtime_idle,
       
  6762 };
       
  6763 
       
  6764 #define RTL8169_PM_OPS	(&rtl8169_pm_ops)
       
  6765 
       
  6766 #else /* !CONFIG_PM */
       
  6767 
       
  6768 #define RTL8169_PM_OPS	NULL
       
  6769 
       
  6770 #endif /* !CONFIG_PM */
       
  6771 
       
  6772 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
       
  6773 {
       
  6774 	void __iomem *ioaddr = tp->mmio_addr;
       
  6775 
       
  6776 	/* WoL fails with 8168b when the receiver is disabled. */
       
  6777 	switch (tp->mac_version) {
       
  6778 	case RTL_GIGA_MAC_VER_11:
       
  6779 	case RTL_GIGA_MAC_VER_12:
       
  6780 	case RTL_GIGA_MAC_VER_17:
       
  6781 		pci_clear_master(tp->pci_dev);
       
  6782 
       
  6783 		RTL_W8(ChipCmd, CmdRxEnb);
       
  6784 		/* PCI commit */
       
  6785 		RTL_R8(ChipCmd);
       
  6786 		break;
       
  6787 	default:
       
  6788 		break;
       
  6789 	}
       
  6790 }
       
  6791 
       
  6792 static void rtl_shutdown(struct pci_dev *pdev)
       
  6793 {
       
  6794 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6795 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6796 	struct device *d = &pdev->dev;
       
  6797 
       
  6798 	pm_runtime_get_sync(d);
       
  6799 
       
  6800 	rtl8169_net_suspend(dev);
       
  6801 
       
  6802 	/* Restore original MAC address */
       
  6803 	rtl_rar_set(tp, dev->perm_addr);
       
  6804 
       
  6805 	rtl8169_hw_reset(tp);
       
  6806 
       
  6807 	if (system_state == SYSTEM_POWER_OFF) {
       
  6808 		if (__rtl8169_get_wol(tp) & WAKE_ANY) {
       
  6809 			rtl_wol_suspend_quirk(tp);
       
  6810 			rtl_wol_shutdown_quirk(tp);
       
  6811 		}
       
  6812 
       
  6813 		pci_wake_from_d3(pdev, true);
       
  6814 		pci_set_power_state(pdev, PCI_D3hot);
       
  6815 	}
       
  6816 
       
  6817 	pm_runtime_put_noidle(d);
       
  6818 }
       
  6819 
       
  6820 static void rtl_remove_one(struct pci_dev *pdev)
       
  6821 {
       
  6822 	struct net_device *dev = pci_get_drvdata(pdev);
       
  6823 	struct rtl8169_private *tp = netdev_priv(dev);
       
  6824 
       
  6825 	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
       
  6826 	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
       
  6827 	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
       
  6828 		rtl8168_driver_stop(tp);
       
  6829 	}
       
  6830 
       
  6831 	netif_napi_del(&tp->napi);
       
  6832 
       
  6833 	unregister_netdev(dev);
       
  6834 
       
  6835 	rtl_release_firmware(tp);
       
  6836 
       
  6837 	if (pci_dev_run_wake(pdev))
       
  6838 		pm_runtime_get_noresume(&pdev->dev);
       
  6839 
       
  6840 	/* restore original MAC address */
       
  6841 	rtl_rar_set(tp, dev->perm_addr);
       
  6842 
       
  6843 	rtl_disable_msi(pdev, tp);
       
  6844 	rtl8169_release_board(pdev, dev, tp->mmio_addr);
       
  6845 }
       
  6846 
       
  6847 static const struct net_device_ops rtl_netdev_ops = {
       
  6848 	.ndo_open		= rtl_open,
       
  6849 	.ndo_stop		= rtl8169_close,
       
  6850 	.ndo_get_stats64	= rtl8169_get_stats64,
       
  6851 	.ndo_start_xmit		= rtl8169_start_xmit,
       
  6852 	.ndo_tx_timeout		= rtl8169_tx_timeout,
       
  6853 	.ndo_validate_addr	= eth_validate_addr,
       
  6854 	.ndo_change_mtu		= rtl8169_change_mtu,
       
  6855 	.ndo_fix_features	= rtl8169_fix_features,
       
  6856 	.ndo_set_features	= rtl8169_set_features,
       
  6857 	.ndo_set_mac_address	= rtl_set_mac_address,
       
  6858 	.ndo_do_ioctl		= rtl8169_ioctl,
       
  6859 	.ndo_set_rx_mode	= rtl_set_rx_mode,
       
  6860 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  6861 	.ndo_poll_controller	= rtl8169_netpoll,
       
  6862 #endif
       
  6863 
       
  6864 };
       
  6865 
       
  6866 static const struct rtl_cfg_info {
       
  6867 	void (*hw_start)(struct net_device *);
       
  6868 	unsigned int region;
       
  6869 	unsigned int align;
       
  6870 	u16 event_slow;
       
  6871 	unsigned features;
       
  6872 	u8 default_ver;
       
  6873 } rtl_cfg_infos [] = {
       
  6874 	[RTL_CFG_0] = {
       
  6875 		.hw_start	= rtl_hw_start_8169,
       
  6876 		.region		= 1,
       
  6877 		.align		= 0,
       
  6878 		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,
       
  6879 		.features	= RTL_FEATURE_GMII,
       
  6880 		.default_ver	= RTL_GIGA_MAC_VER_01,
       
  6881 	},
       
  6882 	[RTL_CFG_1] = {
       
  6883 		.hw_start	= rtl_hw_start_8168,
       
  6884 		.region		= 2,
       
  6885 		.align		= 8,
       
  6886 		.event_slow	= SYSErr | LinkChg | RxOverflow,
       
  6887 		.features	= RTL_FEATURE_GMII | RTL_FEATURE_MSI,
       
  6888 		.default_ver	= RTL_GIGA_MAC_VER_11,
       
  6889 	},
       
  6890 	[RTL_CFG_2] = {
       
  6891 		.hw_start	= rtl_hw_start_8101,
       
  6892 		.region		= 2,
       
  6893 		.align		= 8,
       
  6894 		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |
       
  6895 				  PCSTimeout,
       
  6896 		.features	= RTL_FEATURE_MSI,
       
  6897 		.default_ver	= RTL_GIGA_MAC_VER_13,
       
  6898 	}
       
  6899 };
       
  6900 
       
  6901 /* Cfg9346_Unlock assumed. */
       
  6902 static unsigned rtl_try_msi(struct rtl8169_private *tp,
       
  6903 			    const struct rtl_cfg_info *cfg)
       
  6904 {
       
  6905 	void __iomem *ioaddr = tp->mmio_addr;
       
  6906 	unsigned msi = 0;
       
  6907 	u8 cfg2;
       
  6908 
       
  6909 	cfg2 = RTL_R8(Config2) & ~MSIEnable;
       
  6910 	if (cfg->features & RTL_FEATURE_MSI) {
       
  6911 		if (pci_enable_msi(tp->pci_dev)) {
       
  6912 			netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
       
  6913 		} else {
       
  6914 			cfg2 |= MSIEnable;
       
  6915 			msi = RTL_FEATURE_MSI;
       
  6916 		}
       
  6917 	}
       
  6918 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
       
  6919 		RTL_W8(Config2, cfg2);
       
  6920 	return msi;
       
  6921 }
       
  6922 
       
  6923 DECLARE_RTL_COND(rtl_link_list_ready_cond)
       
  6924 {
       
  6925 	void __iomem *ioaddr = tp->mmio_addr;
       
  6926 
       
  6927 	return RTL_R8(MCU) & LINK_LIST_RDY;
       
  6928 }
       
  6929 
       
  6930 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
       
  6931 {
       
  6932 	void __iomem *ioaddr = tp->mmio_addr;
       
  6933 
       
  6934 	return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
       
  6935 }
       
  6936 
       
  6937 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
       
  6938 {
       
  6939 	void __iomem *ioaddr = tp->mmio_addr;
       
  6940 	u32 data;
       
  6941 
       
  6942 	tp->ocp_base = OCP_STD_PHY_BASE;
       
  6943 
       
  6944 	RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
       
  6945 
       
  6946 	if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
       
  6947 		return;
       
  6948 
       
  6949 	if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
       
  6950 		return;
       
  6951 
       
  6952 	RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
       
  6953 	msleep(1);
       
  6954 	RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
       
  6955 
       
  6956 	data = r8168_mac_ocp_read(tp, 0xe8de);
       
  6957 	data &= ~(1 << 14);
       
  6958 	r8168_mac_ocp_write(tp, 0xe8de, data);
       
  6959 
       
  6960 	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
       
  6961 		return;
       
  6962 
       
  6963 	data = r8168_mac_ocp_read(tp, 0xe8de);
       
  6964 	data |= (1 << 15);
       
  6965 	r8168_mac_ocp_write(tp, 0xe8de, data);
       
  6966 
       
  6967 	if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
       
  6968 		return;
       
  6969 }
       
  6970 
       
  6971 static void rtl_hw_initialize(struct rtl8169_private *tp)
       
  6972 {
       
  6973 	switch (tp->mac_version) {
       
  6974 	case RTL_GIGA_MAC_VER_40:
       
  6975 	case RTL_GIGA_MAC_VER_41:
       
  6976 	case RTL_GIGA_MAC_VER_42:
       
  6977 	case RTL_GIGA_MAC_VER_43:
       
  6978 	case RTL_GIGA_MAC_VER_44:
       
  6979 		rtl_hw_init_8168g(tp);
       
  6980 		break;
       
  6981 
       
  6982 	default:
       
  6983 		break;
       
  6984 	}
       
  6985 }
       
  6986 
       
  6987 static int
       
  6988 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
       
  6989 {
       
  6990 	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
       
  6991 	const unsigned int region = cfg->region;
       
  6992 	struct rtl8169_private *tp;
       
  6993 	struct mii_if_info *mii;
       
  6994 	struct net_device *dev;
       
  6995 	void __iomem *ioaddr;
       
  6996 	int chipset, i;
       
  6997 	int rc;
       
  6998 
       
  6999 	if (netif_msg_drv(&debug)) {
       
  7000 		printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
       
  7001 		       MODULENAME, RTL8169_VERSION);
       
  7002 	}
       
  7003 
       
  7004 	dev = alloc_etherdev(sizeof (*tp));
       
  7005 	if (!dev) {
       
  7006 		rc = -ENOMEM;
       
  7007 		goto out;
       
  7008 	}
       
  7009 
       
  7010 	SET_NETDEV_DEV(dev, &pdev->dev);
       
  7011 	dev->netdev_ops = &rtl_netdev_ops;
       
  7012 	tp = netdev_priv(dev);
       
  7013 	tp->dev = dev;
       
  7014 	tp->pci_dev = pdev;
       
  7015 	tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
       
  7016 
       
  7017 	mii = &tp->mii;
       
  7018 	mii->dev = dev;
       
  7019 	mii->mdio_read = rtl_mdio_read;
       
  7020 	mii->mdio_write = rtl_mdio_write;
       
  7021 	mii->phy_id_mask = 0x1f;
       
  7022 	mii->reg_num_mask = 0x1f;
       
  7023 	mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
       
  7024 
       
  7025 	/* disable ASPM completely as that cause random device stop working
       
  7026 	 * problems as well as full system hangs for some PCIe devices users */
       
  7027 	pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
       
  7028 				     PCIE_LINK_STATE_CLKPM);
       
  7029 
       
  7030 	/* enable device (incl. PCI PM wakeup and hotplug setup) */
       
  7031 	rc = pci_enable_device(pdev);
       
  7032 	if (rc < 0) {
       
  7033 		netif_err(tp, probe, dev, "enable failure\n");
       
  7034 		goto err_out_free_dev_1;
       
  7035 	}
       
  7036 
       
  7037 	if (pci_set_mwi(pdev) < 0)
       
  7038 		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
       
  7039 
       
  7040 	/* make sure PCI base addr 1 is MMIO */
       
  7041 	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
       
  7042 		netif_err(tp, probe, dev,
       
  7043 			  "region #%d not an MMIO resource, aborting\n",
       
  7044 			  region);
       
  7045 		rc = -ENODEV;
       
  7046 		goto err_out_mwi_2;
       
  7047 	}
       
  7048 
       
  7049 	/* check for weird/broken PCI region reporting */
       
  7050 	if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
       
  7051 		netif_err(tp, probe, dev,
       
  7052 			  "Invalid PCI region size(s), aborting\n");
       
  7053 		rc = -ENODEV;
       
  7054 		goto err_out_mwi_2;
       
  7055 	}
       
  7056 
       
  7057 	rc = pci_request_regions(pdev, MODULENAME);
       
  7058 	if (rc < 0) {
       
  7059 		netif_err(tp, probe, dev, "could not request regions\n");
       
  7060 		goto err_out_mwi_2;
       
  7061 	}
       
  7062 
       
  7063 	tp->cp_cmd = RxChkSum;
       
  7064 
       
  7065 	if ((sizeof(dma_addr_t) > 4) &&
       
  7066 	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
       
  7067 		tp->cp_cmd |= PCIDAC;
       
  7068 		dev->features |= NETIF_F_HIGHDMA;
       
  7069 	} else {
       
  7070 		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
       
  7071 		if (rc < 0) {
       
  7072 			netif_err(tp, probe, dev, "DMA configuration failed\n");
       
  7073 			goto err_out_free_res_3;
       
  7074 		}
       
  7075 	}
       
  7076 
       
  7077 	/* ioremap MMIO region */
       
  7078 	ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
       
  7079 	if (!ioaddr) {
       
  7080 		netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
       
  7081 		rc = -EIO;
       
  7082 		goto err_out_free_res_3;
       
  7083 	}
       
  7084 	tp->mmio_addr = ioaddr;
       
  7085 
       
  7086 	if (!pci_is_pcie(pdev))
       
  7087 		netif_info(tp, probe, dev, "not PCI Express\n");
       
  7088 
       
  7089 	/* Identify chip attached to board */
       
  7090 	rtl8169_get_mac_version(tp, dev, cfg->default_ver);
       
  7091 
       
  7092 	rtl_init_rxcfg(tp);
       
  7093 
       
  7094 	rtl_irq_disable(tp);
       
  7095 
       
  7096 	rtl_hw_initialize(tp);
       
  7097 
       
  7098 	rtl_hw_reset(tp);
       
  7099 
       
  7100 	rtl_ack_events(tp, 0xffff);
       
  7101 
       
  7102 	pci_set_master(pdev);
       
  7103 
       
  7104 	/*
       
  7105 	 * Pretend we are using VLANs; This bypasses a nasty bug where
       
  7106 	 * Interrupts stop flowing on high load on 8110SCd controllers.
       
  7107 	 */
       
  7108 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
       
  7109 		tp->cp_cmd |= RxVlan;
       
  7110 
       
  7111 	rtl_init_mdio_ops(tp);
       
  7112 	rtl_init_pll_power_ops(tp);
       
  7113 	rtl_init_jumbo_ops(tp);
       
  7114 	rtl_init_csi_ops(tp);
       
  7115 
       
  7116 	rtl8169_print_mac_version(tp);
       
  7117 
       
  7118 	chipset = tp->mac_version;
       
  7119 	tp->txd_version = rtl_chip_infos[chipset].txd_version;
       
  7120 
       
  7121 	RTL_W8(Cfg9346, Cfg9346_Unlock);
       
  7122 	RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
       
  7123 	RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
       
  7124 	if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
       
  7125 		tp->features |= RTL_FEATURE_WOL;
       
  7126 	if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
       
  7127 		tp->features |= RTL_FEATURE_WOL;
       
  7128 	tp->features |= rtl_try_msi(tp, cfg);
       
  7129 	RTL_W8(Cfg9346, Cfg9346_Lock);
       
  7130 
       
  7131 	if (rtl_tbi_enabled(tp)) {
       
  7132 		tp->set_speed = rtl8169_set_speed_tbi;
       
  7133 		tp->get_settings = rtl8169_gset_tbi;
       
  7134 		tp->phy_reset_enable = rtl8169_tbi_reset_enable;
       
  7135 		tp->phy_reset_pending = rtl8169_tbi_reset_pending;
       
  7136 		tp->link_ok = rtl8169_tbi_link_ok;
       
  7137 		tp->do_ioctl = rtl_tbi_ioctl;
       
  7138 	} else {
       
  7139 		tp->set_speed = rtl8169_set_speed_xmii;
       
  7140 		tp->get_settings = rtl8169_gset_xmii;
       
  7141 		tp->phy_reset_enable = rtl8169_xmii_reset_enable;
       
  7142 		tp->phy_reset_pending = rtl8169_xmii_reset_pending;
       
  7143 		tp->link_ok = rtl8169_xmii_link_ok;
       
  7144 		tp->do_ioctl = rtl_xmii_ioctl;
       
  7145 	}
       
  7146 
       
  7147 	mutex_init(&tp->wk.mutex);
       
  7148 	u64_stats_init(&tp->rx_stats.syncp);
       
  7149 	u64_stats_init(&tp->tx_stats.syncp);
       
  7150 
       
  7151 	/* Get MAC address */
       
  7152 	for (i = 0; i < ETH_ALEN; i++)
       
  7153 		dev->dev_addr[i] = RTL_R8(MAC0 + i);
       
  7154 
       
  7155 	dev->ethtool_ops = &rtl8169_ethtool_ops;
       
  7156 	dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
       
  7157 
       
  7158 	netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
       
  7159 
       
  7160 	/* don't enable SG, IP_CSUM and TSO by default - it might not work
       
  7161 	 * properly for all devices */
       
  7162 	dev->features |= NETIF_F_RXCSUM |
       
  7163 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
       
  7164 
       
  7165 	dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
       
  7166 		NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
       
  7167 		NETIF_F_HW_VLAN_CTAG_RX;
       
  7168 	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
       
  7169 		NETIF_F_HIGHDMA;
       
  7170 
       
  7171 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
       
  7172 		/* 8110SCd requires hardware Rx VLAN - disallow toggling */
       
  7173 		dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
       
  7174 
       
  7175 	dev->hw_features |= NETIF_F_RXALL;
       
  7176 	dev->hw_features |= NETIF_F_RXFCS;
       
  7177 
       
  7178 	tp->hw_start = cfg->hw_start;
       
  7179 	tp->event_slow = cfg->event_slow;
       
  7180 
       
  7181 	tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
       
  7182 		~(RxBOVF | RxFOVF) : ~0;
       
  7183 
       
  7184 	init_timer(&tp->timer);
       
  7185 	tp->timer.data = (unsigned long) dev;
       
  7186 	tp->timer.function = rtl8169_phy_timer;
       
  7187 
       
  7188 	tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
       
  7189 
       
  7190 	rc = register_netdev(dev);
       
  7191 	if (rc < 0)
       
  7192 		goto err_out_msi_4;
       
  7193 
       
  7194 	pci_set_drvdata(pdev, dev);
       
  7195 
       
  7196 	netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
       
  7197 		   rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
       
  7198 		   (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
       
  7199 	if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
       
  7200 		netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
       
  7201 			   "tx checksumming: %s]\n",
       
  7202 			   rtl_chip_infos[chipset].jumbo_max,
       
  7203 			   rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
       
  7204 	}
       
  7205 
       
  7206 	if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
       
  7207 	    tp->mac_version == RTL_GIGA_MAC_VER_28 ||
       
  7208 	    tp->mac_version == RTL_GIGA_MAC_VER_31) {
       
  7209 		rtl8168_driver_start(tp);
       
  7210 	}
       
  7211 
       
  7212 	device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
       
  7213 
       
  7214 	if (pci_dev_run_wake(pdev))
       
  7215 		pm_runtime_put_noidle(&pdev->dev);
       
  7216 
       
  7217 	netif_carrier_off(dev);
       
  7218 
       
  7219 out:
       
  7220 	return rc;
       
  7221 
       
  7222 err_out_msi_4:
       
  7223 	netif_napi_del(&tp->napi);
       
  7224 	rtl_disable_msi(pdev, tp);
       
  7225 	iounmap(ioaddr);
       
  7226 err_out_free_res_3:
       
  7227 	pci_release_regions(pdev);
       
  7228 err_out_mwi_2:
       
  7229 	pci_clear_mwi(pdev);
       
  7230 	pci_disable_device(pdev);
       
  7231 err_out_free_dev_1:
       
  7232 	free_netdev(dev);
       
  7233 	goto out;
       
  7234 }
       
  7235 
       
  7236 static struct pci_driver rtl8169_pci_driver = {
       
  7237 	.name		= MODULENAME,
       
  7238 	.id_table	= rtl8169_pci_tbl,
       
  7239 	.probe		= rtl_init_one,
       
  7240 	.remove		= rtl_remove_one,
       
  7241 	.shutdown	= rtl_shutdown,
       
  7242 	.driver.pm	= RTL8169_PM_OPS,
       
  7243 };
       
  7244 
       
  7245 module_pci_driver(rtl8169_pci_driver);