1 /* Intel PRO/1000 Linux driver

     2  * Copyright(c) 1999 - 2014 Intel Corporation.

     3  *

     4  * This program is free software; you can redistribute it and/or modify it

     5  * under the terms and conditions of the GNU General Public License,

     6  * version 2, as published by the Free Software Foundation.

     7  *

     8  * This program is distributed in the hope it will be useful, but WITHOUT

     9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11  * more details.

    12  *

    13  * The full GNU General Public License is included in this distribution in

    14  * the file called "COPYING".

    15  *

    16  * Contact Information:

    17  * Linux NICS <linux.nics@intel.com>

    18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20  */

    21 

    22 #include "e1000-3.16-ethercat.h"

    23 

    24 /**

    25  *  e1000e_get_bus_info_pcie - Get PCIe bus information

    26  *  @hw: pointer to the HW structure

    27  *

    28  *  Determines and stores the system bus information for a particular

    29  *  network interface.  The following bus information is determined and stored:

    30  *  bus speed, bus width, type (PCIe), and PCIe function.

    31  **/

    32 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)

    33 {

    34 	struct e1000_mac_info *mac = &hw->mac;

    35 	struct e1000_bus_info *bus = &hw->bus;

    36 	struct e1000_adapter *adapter = hw->adapter;

    37 	u16 pcie_link_status, cap_offset;

    38 

    39 	cap_offset = adapter->pdev->pcie_cap;

    40 	if (!cap_offset) {

    41 		bus->width = e1000_bus_width_unknown;

    42 	} else {

    43 		pci_read_config_word(adapter->pdev,

    44 				     cap_offset + PCIE_LINK_STATUS,

    45 				     &pcie_link_status);

    46 		bus->width = (enum e1000_bus_width)((pcie_link_status &

    47 						     PCIE_LINK_WIDTH_MASK) >>

    48 						    PCIE_LINK_WIDTH_SHIFT);

    49 	}

    50 

    51 	mac->ops.set_lan_id(hw);

    52 

    53 	return 0;

    54 }

    55 

    56 /**

    57  *  e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices

    58  *

    59  *  @hw: pointer to the HW structure

    60  *

    61  *  Determines the LAN function id by reading memory-mapped registers

    62  *  and swaps the port value if requested.

    63  **/

    64 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)

    65 {

    66 	struct e1000_bus_info *bus = &hw->bus;

    67 	u32 reg;

    68 

    69 	/* The status register reports the correct function number

    70 	 * for the device regardless of function swap state.

    71 	 */

    72 	reg = er32(STATUS);

    73 	bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

    74 }

    75 

    76 /**

    77  *  e1000_set_lan_id_single_port - Set LAN id for a single port device

    78  *  @hw: pointer to the HW structure

    79  *

    80  *  Sets the LAN function id to zero for a single port device.

    81  **/

    82 void e1000_set_lan_id_single_port(struct e1000_hw *hw)

    83 {

    84 	struct e1000_bus_info *bus = &hw->bus;

    85 

    86 	bus->func = 0;

    87 }

    88 

    89 /**

    90  *  e1000_clear_vfta_generic - Clear VLAN filter table

    91  *  @hw: pointer to the HW structure

    92  *

    93  *  Clears the register array which contains the VLAN filter table by

    94  *  setting all the values to 0.

    95  **/

    96 void e1000_clear_vfta_generic(struct e1000_hw *hw)

    97 {

    98 	u32 offset;

    99 

   100 	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {

   101 		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);

   102 		e1e_flush();

   103 	}

   104 }

   105 

   106 /**

   107  *  e1000_write_vfta_generic - Write value to VLAN filter table

   108  *  @hw: pointer to the HW structure

   109  *  @offset: register offset in VLAN filter table

   110  *  @value: register value written to VLAN filter table

   111  *

   112  *  Writes value at the given offset in the register array which stores

   113  *  the VLAN filter table.

   114  **/

   115 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)

   116 {

   117 	E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);

   118 	e1e_flush();

   119 }

   120 

   121 /**

   122  *  e1000e_init_rx_addrs - Initialize receive address's

   123  *  @hw: pointer to the HW structure

   124  *  @rar_count: receive address registers

   125  *

   126  *  Setup the receive address registers by setting the base receive address

   127  *  register to the devices MAC address and clearing all the other receive

   128  *  address registers to 0.

   129  **/

   130 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)

   131 {

   132 	u32 i;

   133 	u8 mac_addr[ETH_ALEN] = { 0 };

   134 

   135 	/* Setup the receive address */

   136 	e_dbg("Programming MAC Address into RAR[0]\n");

   137 

   138 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);

   139 

   140 	/* Zero out the other (rar_entry_count - 1) receive addresses */

   141 	e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);

   142 	for (i = 1; i < rar_count; i++)

   143 		hw->mac.ops.rar_set(hw, mac_addr, i);

   144 }

   145 

   146 /**

   147  *  e1000_check_alt_mac_addr_generic - Check for alternate MAC addr

   148  *  @hw: pointer to the HW structure

   149  *

   150  *  Checks the nvm for an alternate MAC address.  An alternate MAC address

   151  *  can be setup by pre-boot software and must be treated like a permanent

   152  *  address and must override the actual permanent MAC address. If an

   153  *  alternate MAC address is found it is programmed into RAR0, replacing

   154  *  the permanent address that was installed into RAR0 by the Si on reset.

   155  *  This function will return SUCCESS unless it encounters an error while

   156  *  reading the EEPROM.

   157  **/

   158 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)

   159 {

   160 	u32 i;

   161 	s32 ret_val;

   162 	u16 offset, nvm_alt_mac_addr_offset, nvm_data;

   163 	u8 alt_mac_addr[ETH_ALEN];

   164 

   165 	ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);

   166 	if (ret_val)

   167 		return ret_val;

   168 

   169 	/* not supported on 82573 */

   170 	if (hw->mac.type == e1000_82573)

   171 		return 0;

   172 

   173 	ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,

   174 				 &nvm_alt_mac_addr_offset);

   175 	if (ret_val) {

   176 		e_dbg("NVM Read Error\n");

   177 		return ret_val;

   178 	}

   179 

   180 	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||

   181 	    (nvm_alt_mac_addr_offset == 0x0000))

   182 		/* There is no Alternate MAC Address */

   183 		return 0;

   184 

   185 	if (hw->bus.func == E1000_FUNC_1)

   186 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;

   187 	for (i = 0; i < ETH_ALEN; i += 2) {

   188 		offset = nvm_alt_mac_addr_offset + (i >> 1);

   189 		ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);

   190 		if (ret_val) {

   191 			e_dbg("NVM Read Error\n");

   192 			return ret_val;

   193 		}

   194 

   195 		alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

   196 		alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

   197 	}

   198 

   199 	/* if multicast bit is set, the alternate address will not be used */

   200 	if (is_multicast_ether_addr(alt_mac_addr)) {

   201 		e_dbg("Ignoring Alternate Mac Address with MC bit set\n");

   202 		return 0;

   203 	}

   204 

   205 	/* We have a valid alternate MAC address, and we want to treat it the

   206 	 * same as the normal permanent MAC address stored by the HW into the

   207 	 * RAR. Do this by mapping this address into RAR0.

   208 	 */

   209 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);

   210 

   211 	return 0;

   212 }

   213 

   214 u32 e1000e_rar_get_count_generic(struct e1000_hw *hw)

   215 {

   216 	return hw->mac.rar_entry_count;

   217 }

   218 

   219 /**

   220  *  e1000e_rar_set_generic - Set receive address register

   221  *  @hw: pointer to the HW structure

   222  *  @addr: pointer to the receive address

   223  *  @index: receive address array register

   224  *

   225  *  Sets the receive address array register at index to the address passed

   226  *  in by addr.

   227  **/

   228 int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)

   229 {

   230 	u32 rar_low, rar_high;

   231 

   232 	/* HW expects these in little endian so we reverse the byte order

   233 	 * from network order (big endian) to little endian

   234 	 */

   235 	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |

   236 		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

   237 

   238 	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

   239 

   240 	/* If MAC address zero, no need to set the AV bit */

   241 	if (rar_low || rar_high)

   242 		rar_high |= E1000_RAH_AV;

   243 

   244 	/* Some bridges will combine consecutive 32-bit writes into

   245 	 * a single burst write, which will malfunction on some parts.

   246 	 * The flushes avoid this.

   247 	 */

   248 	ew32(RAL(index), rar_low);

   249 	e1e_flush();

   250 	ew32(RAH(index), rar_high);

   251 	e1e_flush();

   252 

   253 	return 0;

   254 }

   255 

   256 /**

   257  *  e1000_hash_mc_addr - Generate a multicast hash value

   258  *  @hw: pointer to the HW structure

   259  *  @mc_addr: pointer to a multicast address

   260  *

   261  *  Generates a multicast address hash value which is used to determine

   262  *  the multicast filter table array address and new table value.

   263  **/

   264 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

   265 {

   266 	u32 hash_value, hash_mask;

   267 	u8 bit_shift = 0;

   268 

   269 	/* Register count multiplied by bits per register */

   270 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;

   271 

   272 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts

   273 	 * where 0xFF would still fall within the hash mask.

   274 	 */

   275 	while (hash_mask >> bit_shift != 0xFF)

   276 		bit_shift++;

   277 

   278 	/* The portion of the address that is used for the hash table

   279 	 * is determined by the mc_filter_type setting.

   280 	 * The algorithm is such that there is a total of 8 bits of shifting.

   281 	 * The bit_shift for a mc_filter_type of 0 represents the number of

   282 	 * left-shifts where the MSB of mc_addr[5] would still fall within

   283 	 * the hash_mask.  Case 0 does this exactly.  Since there are a total

   284 	 * of 8 bits of shifting, then mc_addr[4] will shift right the

   285 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the

   286 	 * cases are a variation of this algorithm...essentially raising the

   287 	 * number of bits to shift mc_addr[5] left, while still keeping the

   288 	 * 8-bit shifting total.

   289 	 *

   290 	 * For example, given the following Destination MAC Address and an

   291 	 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),

   292 	 * we can see that the bit_shift for case 0 is 4.  These are the hash

   293 	 * values resulting from each mc_filter_type...

   294 	 * [0] [1] [2] [3] [4] [5]

   295 	 * 01  AA  00  12  34  56

   296 	 * LSB           MSB

   297 	 *

   298 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563

   299 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6

   300 	 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163

   301 	 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634

   302 	 */

   303 	switch (hw->mac.mc_filter_type) {

   304 	default:

   305 	case 0:

   306 		break;

   307 	case 1:

   308 		bit_shift += 1;

   309 		break;

   310 	case 2:

   311 		bit_shift += 2;

   312 		break;

   313 	case 3:

   314 		bit_shift += 4;

   315 		break;

   316 	}

   317 

   318 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |

   319 				   (((u16)mc_addr[5]) << bit_shift)));

   320 

   321 	return hash_value;

   322 }

   323 

   324 /**

   325  *  e1000e_update_mc_addr_list_generic - Update Multicast addresses

   326  *  @hw: pointer to the HW structure

   327  *  @mc_addr_list: array of multicast addresses to program

   328  *  @mc_addr_count: number of multicast addresses to program

   329  *

   330  *  Updates entire Multicast Table Array.

   331  *  The caller must have a packed mc_addr_list of multicast addresses.

   332  **/

   333 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,

   334 					u8 *mc_addr_list, u32 mc_addr_count)

   335 {

   336 	u32 hash_value, hash_bit, hash_reg;

   337 	int i;

   338 

   339 	/* clear mta_shadow */

   340 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));

   341 

   342 	/* update mta_shadow from mc_addr_list */

   343 	for (i = 0; (u32)i < mc_addr_count; i++) {

   344 		hash_value = e1000_hash_mc_addr(hw, mc_addr_list);

   345 

   346 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);

   347 		hash_bit = hash_value & 0x1F;

   348 

   349 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);

   350 		mc_addr_list += (ETH_ALEN);

   351 	}

   352 

   353 	/* replace the entire MTA table */

   354 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)

   355 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);

   356 	e1e_flush();

   357 }

   358 

   359 /**

   360  *  e1000e_clear_hw_cntrs_base - Clear base hardware counters

   361  *  @hw: pointer to the HW structure

   362  *

   363  *  Clears the base hardware counters by reading the counter registers.

   364  **/

   365 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)

   366 {

   367 	er32(CRCERRS);

   368 	er32(SYMERRS);

   369 	er32(MPC);

   370 	er32(SCC);

   371 	er32(ECOL);

   372 	er32(MCC);

   373 	er32(LATECOL);

   374 	er32(COLC);

   375 	er32(DC);

   376 	er32(SEC);

   377 	er32(RLEC);

   378 	er32(XONRXC);

   379 	er32(XONTXC);

   380 	er32(XOFFRXC);

   381 	er32(XOFFTXC);

   382 	er32(FCRUC);

   383 	er32(GPRC);

   384 	er32(BPRC);

   385 	er32(MPRC);

   386 	er32(GPTC);

   387 	er32(GORCL);

   388 	er32(GORCH);

   389 	er32(GOTCL);

   390 	er32(GOTCH);

   391 	er32(RNBC);

   392 	er32(RUC);

   393 	er32(RFC);

   394 	er32(ROC);

   395 	er32(RJC);

   396 	er32(TORL);

   397 	er32(TORH);

   398 	er32(TOTL);

   399 	er32(TOTH);

   400 	er32(TPR);

   401 	er32(TPT);

   402 	er32(MPTC);

   403 	er32(BPTC);

   404 }

   405 

   406 /**

   407  *  e1000e_check_for_copper_link - Check for link (Copper)

   408  *  @hw: pointer to the HW structure

   409  *

   410  *  Checks to see of the link status of the hardware has changed.  If a

   411  *  change in link status has been detected, then we read the PHY registers

   412  *  to get the current speed/duplex if link exists.

   413  **/

   414 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)

   415 {

   416 	struct e1000_mac_info *mac = &hw->mac;

   417 	s32 ret_val;

   418 	bool link;

   419 

   420 	/* We only want to go out to the PHY registers to see if Auto-Neg

   421 	 * has completed and/or if our link status has changed.  The

   422 	 * get_link_status flag is set upon receiving a Link Status

   423 	 * Change or Rx Sequence Error interrupt.

   424 	 */

   425 	if (!mac->get_link_status)

   426 		return 0;

   427 

   428 	/* First we want to see if the MII Status Register reports

   429 	 * link.  If so, then we want to get the current speed/duplex

   430 	 * of the PHY.

   431 	 */

   432 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);

   433 	if (ret_val)

   434 		return ret_val;

   435 

   436 	if (!link)

   437 		return 0;	/* No link detected */

   438 

   439 	mac->get_link_status = false;

   440 

   441 	/* Check if there was DownShift, must be checked

   442 	 * immediately after link-up

   443 	 */

   444 	e1000e_check_downshift(hw);

   445 

   446 	/* If we are forcing speed/duplex, then we simply return since

   447 	 * we have already determined whether we have link or not.

   448 	 */

   449 	if (!mac->autoneg)

   450 		return -E1000_ERR_CONFIG;

   451 

   452 	/* Auto-Neg is enabled.  Auto Speed Detection takes care

   453 	 * of MAC speed/duplex configuration.  So we only need to

   454 	 * configure Collision Distance in the MAC.

   455 	 */

   456 	mac->ops.config_collision_dist(hw);

   457 

   458 	/* Configure Flow Control now that Auto-Neg has completed.

   459 	 * First, we need to restore the desired flow control

   460 	 * settings because we may have had to re-autoneg with a

   461 	 * different link partner.

   462 	 */

   463 	ret_val = e1000e_config_fc_after_link_up(hw);

   464 	if (ret_val)

   465 		e_dbg("Error configuring flow control\n");

   466 

   467 	return ret_val;

   468 }

   469 

   470 /**

   471  *  e1000e_check_for_fiber_link - Check for link (Fiber)

   472  *  @hw: pointer to the HW structure

   473  *

   474  *  Checks for link up on the hardware.  If link is not up and we have

   475  *  a signal, then we need to force link up.

   476  **/

   477 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)

   478 {

   479 	struct e1000_mac_info *mac = &hw->mac;

   480 	u32 rxcw;

   481 	u32 ctrl;

   482 	u32 status;

   483 	s32 ret_val;

   484 

   485 	ctrl = er32(CTRL);

   486 	status = er32(STATUS);

   487 	rxcw = er32(RXCW);

   488 

   489 	/* If we don't have link (auto-negotiation failed or link partner

   490 	 * cannot auto-negotiate), the cable is plugged in (we have signal),

   491 	 * and our link partner is not trying to auto-negotiate with us (we

   492 	 * are receiving idles or data), we need to force link up. We also

   493 	 * need to give auto-negotiation time to complete, in case the cable

   494 	 * was just plugged in. The autoneg_failed flag does this.

   495 	 */

   496 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   497 	if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&

   498 	    !(rxcw & E1000_RXCW_C)) {

   499 		if (!mac->autoneg_failed) {

   500 			mac->autoneg_failed = true;

   501 			return 0;

   502 		}

   503 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");

   504 

   505 		/* Disable auto-negotiation in the TXCW register */

   506 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   507 

   508 		/* Force link-up and also force full-duplex. */

   509 		ctrl = er32(CTRL);

   510 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   511 		ew32(CTRL, ctrl);

   512 

   513 		/* Configure Flow Control after forcing link up. */

   514 		ret_val = e1000e_config_fc_after_link_up(hw);

   515 		if (ret_val) {

   516 			e_dbg("Error configuring flow control\n");

   517 			return ret_val;

   518 		}

   519 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

   520 		/* If we are forcing link and we are receiving /C/ ordered

   521 		 * sets, re-enable auto-negotiation in the TXCW register

   522 		 * and disable forced link in the Device Control register

   523 		 * in an attempt to auto-negotiate with our link partner.

   524 		 */

   525 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");

   526 		ew32(TXCW, mac->txcw);

   527 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

   528 

   529 		mac->serdes_has_link = true;

   530 	}

   531 

   532 	return 0;

   533 }

   534 

   535 /**

   536  *  e1000e_check_for_serdes_link - Check for link (Serdes)

   537  *  @hw: pointer to the HW structure

   538  *

   539  *  Checks for link up on the hardware.  If link is not up and we have

   540  *  a signal, then we need to force link up.

   541  **/

   542 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)

   543 {

   544 	struct e1000_mac_info *mac = &hw->mac;

   545 	u32 rxcw;

   546 	u32 ctrl;

   547 	u32 status;

   548 	s32 ret_val;

   549 

   550 	ctrl = er32(CTRL);

   551 	status = er32(STATUS);

   552 	rxcw = er32(RXCW);

   553 

   554 	/* If we don't have link (auto-negotiation failed or link partner

   555 	 * cannot auto-negotiate), and our link partner is not trying to

   556 	 * auto-negotiate with us (we are receiving idles or data),

   557 	 * we need to force link up. We also need to give auto-negotiation

   558 	 * time to complete.

   559 	 */

   560 	/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */

   561 	if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {

   562 		if (!mac->autoneg_failed) {

   563 			mac->autoneg_failed = true;

   564 			return 0;

   565 		}

   566 		e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");

   567 

   568 		/* Disable auto-negotiation in the TXCW register */

   569 		ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));

   570 

   571 		/* Force link-up and also force full-duplex. */

   572 		ctrl = er32(CTRL);

   573 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);

   574 		ew32(CTRL, ctrl);

   575 

   576 		/* Configure Flow Control after forcing link up. */

   577 		ret_val = e1000e_config_fc_after_link_up(hw);

   578 		if (ret_val) {

   579 			e_dbg("Error configuring flow control\n");

   580 			return ret_val;

   581 		}

   582 	} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {

   583 		/* If we are forcing link and we are receiving /C/ ordered

   584 		 * sets, re-enable auto-negotiation in the TXCW register

   585 		 * and disable forced link in the Device Control register

   586 		 * in an attempt to auto-negotiate with our link partner.

   587 		 */

   588 		e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");

   589 		ew32(TXCW, mac->txcw);

   590 		ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));

   591 

   592 		mac->serdes_has_link = true;

   593 	} else if (!(E1000_TXCW_ANE & er32(TXCW))) {

   594 		/* If we force link for non-auto-negotiation switch, check

   595 		 * link status based on MAC synchronization for internal

   596 		 * serdes media type.

   597 		 */

   598 		/* SYNCH bit and IV bit are sticky. */

   599 		usleep_range(10, 20);

   600 		rxcw = er32(RXCW);

   601 		if (rxcw & E1000_RXCW_SYNCH) {

   602 			if (!(rxcw & E1000_RXCW_IV)) {

   603 				mac->serdes_has_link = true;

   604 				e_dbg("SERDES: Link up - forced.\n");

   605 			}

   606 		} else {

   607 			mac->serdes_has_link = false;

   608 			e_dbg("SERDES: Link down - force failed.\n");

   609 		}

   610 	}

   611 

   612 	if (E1000_TXCW_ANE & er32(TXCW)) {

   613 		status = er32(STATUS);

   614 		if (status & E1000_STATUS_LU) {

   615 			/* SYNCH bit and IV bit are sticky, so reread rxcw. */

   616 			usleep_range(10, 20);

   617 			rxcw = er32(RXCW);

   618 			if (rxcw & E1000_RXCW_SYNCH) {

   619 				if (!(rxcw & E1000_RXCW_IV)) {

   620 					mac->serdes_has_link = true;

   621 					e_dbg("SERDES: Link up - autoneg completed successfully.\n");

   622 				} else {

   623 					mac->serdes_has_link = false;

   624 					e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n");

   625 				}

   626 			} else {

   627 				mac->serdes_has_link = false;

   628 				e_dbg("SERDES: Link down - no sync.\n");

   629 			}

   630 		} else {

   631 			mac->serdes_has_link = false;

   632 			e_dbg("SERDES: Link down - autoneg failed\n");

   633 		}

   634 	}

   635 

   636 	return 0;

   637 }

   638 

   639 /**

   640  *  e1000_set_default_fc_generic - Set flow control default values

   641  *  @hw: pointer to the HW structure

   642  *

   643  *  Read the EEPROM for the default values for flow control and store the

   644  *  values.

   645  **/

   646 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)

   647 {

   648 	s32 ret_val;

   649 	u16 nvm_data;

   650 

   651 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   652 	 * that determine the hardware's default PAUSE (flow control) mode,

   653 	 * a bit that determines whether the HW defaults to enabling or

   654 	 * disabling auto-negotiation, and the direction of the

   655 	 * SW defined pins. If there is no SW over-ride of the flow

   656 	 * control setting, then the variable hw->fc will

   657 	 * be initialized based on a value in the EEPROM.

   658 	 */

   659 	ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);

   660 

   661 	if (ret_val) {

   662 		e_dbg("NVM Read Error\n");

   663 		return ret_val;

   664 	}

   665 

   666 	if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))

   667 		hw->fc.requested_mode = e1000_fc_none;

   668 	else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)

   669 		hw->fc.requested_mode = e1000_fc_tx_pause;

   670 	else

   671 		hw->fc.requested_mode = e1000_fc_full;

   672 

   673 	return 0;

   674 }

   675 

   676 /**

   677  *  e1000e_setup_link_generic - Setup flow control and link settings

   678  *  @hw: pointer to the HW structure

   679  *

   680  *  Determines which flow control settings to use, then configures flow

   681  *  control.  Calls the appropriate media-specific link configuration

   682  *  function.  Assuming the adapter has a valid link partner, a valid link

   683  *  should be established.  Assumes the hardware has previously been reset

   684  *  and the transmitter and receiver are not enabled.

   685  **/

   686 s32 e1000e_setup_link_generic(struct e1000_hw *hw)

   687 {

   688 	s32 ret_val;

   689 

   690 	/* In the case of the phy reset being blocked, we already have a link.

   691 	 * We do not need to set it up again.

   692 	 */

   693 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))

   694 		return 0;

   695 

   696 	/* If requested flow control is set to default, set flow control

   697 	 * based on the EEPROM flow control settings.

   698 	 */

   699 	if (hw->fc.requested_mode == e1000_fc_default) {

   700 		ret_val = e1000_set_default_fc_generic(hw);

   701 		if (ret_val)

   702 			return ret_val;

   703 	}

   704 

   705 	/* Save off the requested flow control mode for use later.  Depending

   706 	 * on the link partner's capabilities, we may or may not use this mode.

   707 	 */

   708 	hw->fc.current_mode = hw->fc.requested_mode;

   709 

   710 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);

   711 

   712 	/* Call the necessary media_type subroutine to configure the link. */

   713 	ret_val = hw->mac.ops.setup_physical_interface(hw);

   714 	if (ret_val)

   715 		return ret_val;

   716 

   717 	/* Initialize the flow control address, type, and PAUSE timer

   718 	 * registers to their default values.  This is done even if flow

   719 	 * control is disabled, because it does not hurt anything to

   720 	 * initialize these registers.

   721 	 */

   722 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   723 	ew32(FCT, FLOW_CONTROL_TYPE);

   724 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   725 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   726 

   727 	ew32(FCTTV, hw->fc.pause_time);

   728 

   729 	return e1000e_set_fc_watermarks(hw);

   730 }

   731 

   732 /**

   733  *  e1000_commit_fc_settings_generic - Configure flow control

   734  *  @hw: pointer to the HW structure

   735  *

   736  *  Write the flow control settings to the Transmit Config Word Register (TXCW)

   737  *  base on the flow control settings in e1000_mac_info.

   738  **/

   739 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)

   740 {

   741 	struct e1000_mac_info *mac = &hw->mac;

   742 	u32 txcw;

   743 

   744 	/* Check for a software override of the flow control settings, and

   745 	 * setup the device accordingly.  If auto-negotiation is enabled, then

   746 	 * software will have to set the "PAUSE" bits to the correct value in

   747 	 * the Transmit Config Word Register (TXCW) and re-start auto-

   748 	 * negotiation.  However, if auto-negotiation is disabled, then

   749 	 * software will have to manually configure the two flow control enable

   750 	 * bits in the CTRL register.

   751 	 *

   752 	 * The possible values of the "fc" parameter are:

   753 	 *      0:  Flow control is completely disabled

   754 	 *      1:  Rx flow control is enabled (we can receive pause frames,

   755 	 *          but not send pause frames).

   756 	 *      2:  Tx flow control is enabled (we can send pause frames but we

   757 	 *          do not support receiving pause frames).

   758 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.

   759 	 */

   760 	switch (hw->fc.current_mode) {

   761 	case e1000_fc_none:

   762 		/* Flow control completely disabled by a software over-ride. */

   763 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   764 		break;

   765 	case e1000_fc_rx_pause:

   766 		/* Rx Flow control is enabled and Tx Flow control is disabled

   767 		 * by a software over-ride. Since there really isn't a way to

   768 		 * advertise that we are capable of Rx Pause ONLY, we will

   769 		 * advertise that we support both symmetric and asymmetric Rx

   770 		 * PAUSE.  Later, we will disable the adapter's ability to send

   771 		 * PAUSE frames.

   772 		 */

   773 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   774 		break;

   775 	case e1000_fc_tx_pause:

   776 		/* Tx Flow control is enabled, and Rx Flow control is disabled,

   777 		 * by a software over-ride.

   778 		 */

   779 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   780 		break;

   781 	case e1000_fc_full:

   782 		/* Flow control (both Rx and Tx) is enabled by a software

   783 		 * over-ride.

   784 		 */

   785 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   786 		break;

   787 	default:

   788 		e_dbg("Flow control param set incorrectly\n");

   789 		return -E1000_ERR_CONFIG;

   790 		break;

   791 	}

   792 

   793 	ew32(TXCW, txcw);

   794 	mac->txcw = txcw;

   795 

   796 	return 0;

   797 }

   798 

   799 /**

   800  *  e1000_poll_fiber_serdes_link_generic - Poll for link up

   801  *  @hw: pointer to the HW structure

   802  *

   803  *  Polls for link up by reading the status register, if link fails to come

   804  *  up with auto-negotiation, then the link is forced if a signal is detected.

   805  **/

   806 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)

   807 {

   808 	struct e1000_mac_info *mac = &hw->mac;

   809 	u32 i, status;

   810 	s32 ret_val;

   811 

   812 	/* If we have a signal (the cable is plugged in, or assumed true for

   813 	 * serdes media) then poll for a "Link-Up" indication in the Device

   814 	 * Status Register.  Time-out if a link isn't seen in 500 milliseconds

   815 	 * seconds (Auto-negotiation should complete in less than 500

   816 	 * milliseconds even if the other end is doing it in SW).

   817 	 */

   818 	for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {

   819 		usleep_range(10000, 20000);

   820 		status = er32(STATUS);

   821 		if (status & E1000_STATUS_LU)

   822 			break;

   823 	}

   824 	if (i == FIBER_LINK_UP_LIMIT) {

   825 		e_dbg("Never got a valid link from auto-neg!!!\n");

   826 		mac->autoneg_failed = true;

   827 		/* AutoNeg failed to achieve a link, so we'll call

   828 		 * mac->check_for_link. This routine will force the

   829 		 * link up if we detect a signal. This will allow us to

   830 		 * communicate with non-autonegotiating link partners.

   831 		 */

   832 		ret_val = mac->ops.check_for_link(hw);

   833 		if (ret_val) {

   834 			e_dbg("Error while checking for link\n");

   835 			return ret_val;

   836 		}

   837 		mac->autoneg_failed = false;

   838 	} else {

   839 		mac->autoneg_failed = false;

   840 		e_dbg("Valid Link Found\n");

   841 	}

   842 

   843 	return 0;

   844 }

   845 

   846 /**

   847  *  e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes

   848  *  @hw: pointer to the HW structure

   849  *

   850  *  Configures collision distance and flow control for fiber and serdes

   851  *  links.  Upon successful setup, poll for link.

   852  **/

   853 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)

   854 {

   855 	u32 ctrl;

   856 	s32 ret_val;

   857 

   858 	ctrl = er32(CTRL);

   859 

   860 	/* Take the link out of reset */

   861 	ctrl &= ~E1000_CTRL_LRST;

   862 

   863 	hw->mac.ops.config_collision_dist(hw);

   864 

   865 	ret_val = e1000_commit_fc_settings_generic(hw);

   866 	if (ret_val)

   867 		return ret_val;

   868 

   869 	/* Since auto-negotiation is enabled, take the link out of reset (the

   870 	 * link will be in reset, because we previously reset the chip). This

   871 	 * will restart auto-negotiation.  If auto-negotiation is successful

   872 	 * then the link-up status bit will be set and the flow control enable

   873 	 * bits (RFCE and TFCE) will be set according to their negotiated value.

   874 	 */

   875 	e_dbg("Auto-negotiation enabled\n");

   876 

   877 	ew32(CTRL, ctrl);

   878 	e1e_flush();

   879 	usleep_range(1000, 2000);

   880 

   881 	/* For these adapters, the SW definable pin 1 is set when the optics

   882 	 * detect a signal.  If we have a signal, then poll for a "Link-Up"

   883 	 * indication.

   884 	 */

   885 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||

   886 	    (er32(CTRL) & E1000_CTRL_SWDPIN1)) {

   887 		ret_val = e1000_poll_fiber_serdes_link_generic(hw);

   888 	} else {

   889 		e_dbg("No signal detected\n");

   890 	}

   891 

   892 	return ret_val;

   893 }

   894 

   895 /**

   896  *  e1000e_config_collision_dist_generic - Configure collision distance

   897  *  @hw: pointer to the HW structure

   898  *

   899  *  Configures the collision distance to the default value and is used

   900  *  during link setup.

   901  **/

   902 void e1000e_config_collision_dist_generic(struct e1000_hw *hw)

   903 {

   904 	u32 tctl;

   905 

   906 	tctl = er32(TCTL);

   907 

   908 	tctl &= ~E1000_TCTL_COLD;

   909 	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;

   910 

   911 	ew32(TCTL, tctl);

   912 	e1e_flush();

   913 }

   914 

   915 /**

   916  *  e1000e_set_fc_watermarks - Set flow control high/low watermarks

   917  *  @hw: pointer to the HW structure

   918  *

   919  *  Sets the flow control high/low threshold (watermark) registers.  If

   920  *  flow control XON frame transmission is enabled, then set XON frame

   921  *  transmission as well.

   922  **/

   923 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)

   924 {

   925 	u32 fcrtl = 0, fcrth = 0;

   926 

   927 	/* Set the flow control receive threshold registers.  Normally,

   928 	 * these registers will be set to a default threshold that may be

   929 	 * adjusted later by the driver's runtime code.  However, if the

   930 	 * ability to transmit pause frames is not enabled, then these

   931 	 * registers will be set to 0.

   932 	 */

   933 	if (hw->fc.current_mode & e1000_fc_tx_pause) {

   934 		/* We need to set up the Receive Threshold high and low water

   935 		 * marks as well as (optionally) enabling the transmission of

   936 		 * XON frames.

   937 		 */

   938 		fcrtl = hw->fc.low_water;

   939 		if (hw->fc.send_xon)

   940 			fcrtl |= E1000_FCRTL_XONE;

   941 

   942 		fcrth = hw->fc.high_water;

   943 	}

   944 	ew32(FCRTL, fcrtl);

   945 	ew32(FCRTH, fcrth);

   946 

   947 	return 0;

   948 }

   949 

   950 /**

   951  *  e1000e_force_mac_fc - Force the MAC's flow control settings

   952  *  @hw: pointer to the HW structure

   953  *

   954  *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the

   955  *  device control register to reflect the adapter settings.  TFCE and RFCE

   956  *  need to be explicitly set by software when a copper PHY is used because

   957  *  autonegotiation is managed by the PHY rather than the MAC.  Software must

   958  *  also configure these bits when link is forced on a fiber connection.

   959  **/

   960 s32 e1000e_force_mac_fc(struct e1000_hw *hw)

   961 {

   962 	u32 ctrl;

   963 

   964 	ctrl = er32(CTRL);

   965 

   966 	/* Because we didn't get link via the internal auto-negotiation

   967 	 * mechanism (we either forced link or we got link via PHY

   968 	 * auto-neg), we have to manually enable/disable transmit an

   969 	 * receive flow control.

   970 	 *

   971 	 * The "Case" statement below enables/disable flow control

   972 	 * according to the "hw->fc.current_mode" parameter.

   973 	 *

   974 	 * The possible values of the "fc" parameter are:

   975 	 *      0:  Flow control is completely disabled

   976 	 *      1:  Rx flow control is enabled (we can receive pause

   977 	 *          frames but not send pause frames).

   978 	 *      2:  Tx flow control is enabled (we can send pause frames

   979 	 *          frames but we do not receive pause frames).

   980 	 *      3:  Both Rx and Tx flow control (symmetric) is enabled.

   981 	 *  other:  No other values should be possible at this point.

   982 	 */

   983 	e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);

   984 

   985 	switch (hw->fc.current_mode) {

   986 	case e1000_fc_none:

   987 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));

   988 		break;

   989 	case e1000_fc_rx_pause:

   990 		ctrl &= (~E1000_CTRL_TFCE);

   991 		ctrl |= E1000_CTRL_RFCE;

   992 		break;

   993 	case e1000_fc_tx_pause:

   994 		ctrl &= (~E1000_CTRL_RFCE);

   995 		ctrl |= E1000_CTRL_TFCE;

   996 		break;

   997 	case e1000_fc_full:

   998 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);

   999 		break;

  1000 	default:

  1001 		e_dbg("Flow control param set incorrectly\n");

  1002 		return -E1000_ERR_CONFIG;

  1003 	}

  1004 

  1005 	ew32(CTRL, ctrl);

  1006 

  1007 	return 0;

  1008 }

  1009 

  1010 /**

  1011  *  e1000e_config_fc_after_link_up - Configures flow control after link

  1012  *  @hw: pointer to the HW structure

  1013  *

  1014  *  Checks the status of auto-negotiation after link up to ensure that the

  1015  *  speed and duplex were not forced.  If the link needed to be forced, then

  1016  *  flow control needs to be forced also.  If auto-negotiation is enabled

  1017  *  and did not fail, then we configure flow control based on our link

  1018  *  partner.

  1019  **/

  1020 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)

  1021 {

  1022 	struct e1000_mac_info *mac = &hw->mac;

  1023 	s32 ret_val = 0;

  1024 	u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;

  1025 	u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;

  1026 	u16 speed, duplex;

  1027 

  1028 	/* Check for the case where we have fiber media and auto-neg failed

  1029 	 * so we had to force link.  In this case, we need to force the

  1030 	 * configuration of the MAC to match the "fc" parameter.

  1031 	 */

  1032 	if (mac->autoneg_failed) {

  1033 		if (hw->phy.media_type == e1000_media_type_fiber ||

  1034 		    hw->phy.media_type == e1000_media_type_internal_serdes)

  1035 			ret_val = e1000e_force_mac_fc(hw);

  1036 	} else {

  1037 		if (hw->phy.media_type == e1000_media_type_copper)

  1038 			ret_val = e1000e_force_mac_fc(hw);

  1039 	}

  1040 

  1041 	if (ret_val) {

  1042 		e_dbg("Error forcing flow control settings\n");

  1043 		return ret_val;

  1044 	}

  1045 

  1046 	/* Check for the case where we have copper media and auto-neg is

  1047 	 * enabled.  In this case, we need to check and see if Auto-Neg

  1048 	 * has completed, and if so, how the PHY and link partner has

  1049 	 * flow control configured.

  1050 	 */

  1051 	if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {

  1052 		/* Read the MII Status Register and check to see if AutoNeg

  1053 		 * has completed.  We read this twice because this reg has

  1054 		 * some "sticky" (latched) bits.

  1055 		 */

  1056 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);

  1057 		if (ret_val)

  1058 			return ret_val;

  1059 		ret_val = e1e_rphy(hw, MII_BMSR, &mii_status_reg);

  1060 		if (ret_val)

  1061 			return ret_val;

  1062 

  1063 		if (!(mii_status_reg & BMSR_ANEGCOMPLETE)) {

  1064 			e_dbg("Copper PHY and Auto Neg has not completed.\n");

  1065 			return ret_val;

  1066 		}

  1067 

  1068 		/* The AutoNeg process has completed, so we now need to

  1069 		 * read both the Auto Negotiation Advertisement

  1070 		 * Register (Address 4) and the Auto_Negotiation Base

  1071 		 * Page Ability Register (Address 5) to determine how

  1072 		 * flow control was negotiated.

  1073 		 */

  1074 		ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_nway_adv_reg);

  1075 		if (ret_val)

  1076 			return ret_val;

  1077 		ret_val = e1e_rphy(hw, MII_LPA, &mii_nway_lp_ability_reg);

  1078 		if (ret_val)

  1079 			return ret_val;

  1080 

  1081 		/* Two bits in the Auto Negotiation Advertisement Register

  1082 		 * (Address 4) and two bits in the Auto Negotiation Base

  1083 		 * Page Ability Register (Address 5) determine flow control

  1084 		 * for both the PHY and the link partner.  The following

  1085 		 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,

  1086 		 * 1999, describes these PAUSE resolution bits and how flow

  1087 		 * control is determined based upon these settings.

  1088 		 * NOTE:  DC = Don't Care

  1089 		 *

  1090 		 *   LOCAL DEVICE  |   LINK PARTNER

  1091 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution

  1092 		 *-------|---------|-------|---------|--------------------

  1093 		 *   0   |    0    |  DC   |   DC    | e1000_fc_none

  1094 		 *   0   |    1    |   0   |   DC    | e1000_fc_none

  1095 		 *   0   |    1    |   1   |    0    | e1000_fc_none

  1096 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause

  1097 		 *   1   |    0    |   0   |   DC    | e1000_fc_none

  1098 		 *   1   |   DC    |   1   |   DC    | e1000_fc_full

  1099 		 *   1   |    1    |   0   |    0    | e1000_fc_none

  1100 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause

  1101 		 *

  1102 		 * Are both PAUSE bits set to 1?  If so, this implies

  1103 		 * Symmetric Flow Control is enabled at both ends.  The

  1104 		 * ASM_DIR bits are irrelevant per the spec.

  1105 		 *

  1106 		 * For Symmetric Flow Control:

  1107 		 *

  1108 		 *   LOCAL DEVICE  |   LINK PARTNER

  1109 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result

  1110 		 *-------|---------|-------|---------|--------------------

  1111 		 *   1   |   DC    |   1   |   DC    | E1000_fc_full

  1112 		 *

  1113 		 */

  1114 		if ((mii_nway_adv_reg & ADVERTISE_PAUSE_CAP) &&

  1115 		    (mii_nway_lp_ability_reg & LPA_PAUSE_CAP)) {

  1116 			/* Now we need to check if the user selected Rx ONLY

  1117 			 * of pause frames.  In this case, we had to advertise

  1118 			 * FULL flow control because we could not advertise Rx

  1119 			 * ONLY. Hence, we must now check to see if we need to

  1120 			 * turn OFF the TRANSMISSION of PAUSE frames.

  1121 			 */

  1122 			if (hw->fc.requested_mode == e1000_fc_full) {

  1123 				hw->fc.current_mode = e1000_fc_full;

  1124 				e_dbg("Flow Control = FULL.\n");

  1125 			} else {

  1126 				hw->fc.current_mode = e1000_fc_rx_pause;

  1127 				e_dbg("Flow Control = Rx PAUSE frames only.\n");

  1128 			}

  1129 		}

  1130 		/* For receiving PAUSE frames ONLY.

  1131 		 *

  1132 		 *   LOCAL DEVICE  |   LINK PARTNER

  1133 		 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result

  1134 		 *-------|---------|-------|---------|--------------------

  1135 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause

  1136 		 */