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1 /* Intel PRO/1000 Linux driver |
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2 * Copyright(c) 1999 - 2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * The full GNU General Public License is included in this distribution in |
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14 * the file called "COPYING". |
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15 * |
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16 * Contact Information: |
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17 * Linux NICS <linux.nics@intel.com> |
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18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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20 */ |
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21 |
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22 /* Linux PRO/1000 Ethernet Driver main header file */ |
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23 |
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24 #ifndef _E1000_H_ |
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25 #define _E1000_H_ |
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26 |
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27 #include <linux/bitops.h> |
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28 #include <linux/types.h> |
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29 #include <linux/timer.h> |
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30 #include <linux/workqueue.h> |
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31 #include <linux/io.h> |
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32 #include <linux/netdevice.h> |
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33 #include <linux/pci.h> |
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34 #include <linux/pci-aspm.h> |
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35 #include <linux/crc32.h> |
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36 #include <linux/if_vlan.h> |
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37 #include <linux/clocksource.h> |
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38 #include <linux/net_tstamp.h> |
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39 #include <linux/ptp_clock_kernel.h> |
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40 #include <linux/ptp_classify.h> |
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41 #include <linux/mii.h> |
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42 #include <linux/mdio.h> |
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43 #include "hw.h" |
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44 |
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45 struct e1000_info; |
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46 |
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47 #define e_dbg(format, arg...) \ |
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48 netdev_dbg(hw->adapter->netdev, format, ## arg) |
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49 #define e_err(format, arg...) \ |
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50 netdev_err(adapter->netdev, format, ## arg) |
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51 #define e_info(format, arg...) \ |
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52 netdev_info(adapter->netdev, format, ## arg) |
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53 #define e_warn(format, arg...) \ |
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54 netdev_warn(adapter->netdev, format, ## arg) |
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55 #define e_notice(format, arg...) \ |
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56 netdev_notice(adapter->netdev, format, ## arg) |
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57 |
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58 /* Interrupt modes, as used by the IntMode parameter */ |
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59 #define E1000E_INT_MODE_LEGACY 0 |
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60 #define E1000E_INT_MODE_MSI 1 |
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61 #define E1000E_INT_MODE_MSIX 2 |
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62 |
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63 /* Tx/Rx descriptor defines */ |
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64 #define E1000_DEFAULT_TXD 256 |
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65 #define E1000_MAX_TXD 4096 |
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66 #define E1000_MIN_TXD 64 |
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67 |
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68 #define E1000_DEFAULT_RXD 256 |
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69 #define E1000_MAX_RXD 4096 |
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70 #define E1000_MIN_RXD 64 |
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71 |
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72 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
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73 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ |
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74 |
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75 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ |
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76 |
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77 /* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
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78 /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
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79 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
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80 |
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81 #define AUTO_ALL_MODES 0 |
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82 #define E1000_EEPROM_APME 0x0400 |
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83 |
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84 #define E1000_MNG_VLAN_NONE (-1) |
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85 |
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86 #define DEFAULT_JUMBO 9234 |
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87 |
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88 /* Time to wait before putting the device into D3 if there's no link (in ms). */ |
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89 #define LINK_TIMEOUT 100 |
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90 |
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91 /* Count for polling __E1000_RESET condition every 10-20msec. |
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92 * Experimentation has shown the reset can take approximately 210msec. |
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93 */ |
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94 #define E1000_CHECK_RESET_COUNT 25 |
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95 |
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96 #define DEFAULT_RDTR 0 |
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97 #define DEFAULT_RADV 8 |
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98 #define BURST_RDTR 0x20 |
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99 #define BURST_RADV 0x20 |
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100 |
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101 /* in the case of WTHRESH, it appears at least the 82571/2 hardware |
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102 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when |
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103 * WTHRESH=4, so a setting of 5 gives the most efficient bus |
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104 * utilization but to avoid possible Tx stalls, set it to 1 |
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105 */ |
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106 #define E1000_TXDCTL_DMA_BURST_ENABLE \ |
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107 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ |
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108 E1000_TXDCTL_COUNT_DESC | \ |
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109 (1 << 16) | /* wthresh must be +1 more than desired */\ |
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110 (1 << 8) | /* hthresh */ \ |
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111 0x1f) /* pthresh */ |
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112 |
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113 #define E1000_RXDCTL_DMA_BURST_ENABLE \ |
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114 (0x01000000 | /* set descriptor granularity */ \ |
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115 (4 << 16) | /* set writeback threshold */ \ |
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116 (4 << 8) | /* set prefetch threshold */ \ |
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117 0x20) /* set hthresh */ |
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118 |
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119 #define E1000_TIDV_FPD (1 << 31) |
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120 #define E1000_RDTR_FPD (1 << 31) |
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121 |
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122 enum e1000_boards { |
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123 board_82571, |
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124 board_82572, |
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125 board_82573, |
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126 board_82574, |
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127 board_82583, |
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128 board_80003es2lan, |
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129 board_ich8lan, |
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130 board_ich9lan, |
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131 board_ich10lan, |
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132 board_pchlan, |
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133 board_pch2lan, |
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134 board_pch_lpt, |
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135 }; |
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136 |
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137 struct e1000_ps_page { |
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138 struct page *page; |
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139 u64 dma; /* must be u64 - written to hw */ |
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140 }; |
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141 |
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142 /* wrappers around a pointer to a socket buffer, |
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143 * so a DMA handle can be stored along with the buffer |
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144 */ |
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145 struct e1000_buffer { |
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146 dma_addr_t dma; |
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147 struct sk_buff *skb; |
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148 union { |
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149 /* Tx */ |
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150 struct { |
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151 unsigned long time_stamp; |
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152 u16 length; |
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153 u16 next_to_watch; |
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154 unsigned int segs; |
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155 unsigned int bytecount; |
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156 u16 mapped_as_page; |
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157 }; |
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158 /* Rx */ |
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159 struct { |
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160 /* arrays of page information for packet split */ |
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161 struct e1000_ps_page *ps_pages; |
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162 struct page *page; |
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163 }; |
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164 }; |
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165 }; |
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166 |
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167 struct e1000_ring { |
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168 struct e1000_adapter *adapter; /* back pointer to adapter */ |
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169 void *desc; /* pointer to ring memory */ |
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170 dma_addr_t dma; /* phys address of ring */ |
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171 unsigned int size; /* length of ring in bytes */ |
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172 unsigned int count; /* number of desc. in ring */ |
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173 |
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174 u16 next_to_use; |
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175 u16 next_to_clean; |
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176 |
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177 void __iomem *head; |
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178 void __iomem *tail; |
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179 |
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180 /* array of buffer information structs */ |
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181 struct e1000_buffer *buffer_info; |
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182 |
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183 char name[IFNAMSIZ + 5]; |
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184 u32 ims_val; |
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185 u32 itr_val; |
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186 void __iomem *itr_register; |
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187 int set_itr; |
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188 |
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189 struct sk_buff *rx_skb_top; |
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190 }; |
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191 |
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192 /* PHY register snapshot values */ |
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193 struct e1000_phy_regs { |
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194 u16 bmcr; /* basic mode control register */ |
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195 u16 bmsr; /* basic mode status register */ |
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196 u16 advertise; /* auto-negotiation advertisement */ |
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197 u16 lpa; /* link partner ability register */ |
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198 u16 expansion; /* auto-negotiation expansion reg */ |
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199 u16 ctrl1000; /* 1000BASE-T control register */ |
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200 u16 stat1000; /* 1000BASE-T status register */ |
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201 u16 estatus; /* extended status register */ |
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202 }; |
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203 |
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204 /* board specific private data structure */ |
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205 struct e1000_adapter { |
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206 struct timer_list watchdog_timer; |
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207 struct timer_list phy_info_timer; |
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208 struct timer_list blink_timer; |
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209 |
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210 struct work_struct reset_task; |
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211 struct work_struct watchdog_task; |
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212 |
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213 const struct e1000_info *ei; |
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214 |
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215 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
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216 u32 bd_number; |
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217 u32 rx_buffer_len; |
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218 u16 mng_vlan_id; |
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219 u16 link_speed; |
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220 u16 link_duplex; |
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221 u16 eeprom_vers; |
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222 |
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223 /* track device up/down/testing state */ |
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224 unsigned long state; |
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225 |
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226 /* Interrupt Throttle Rate */ |
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227 u32 itr; |
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228 u32 itr_setting; |
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229 u16 tx_itr; |
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230 u16 rx_itr; |
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231 |
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232 /* Tx - one ring per active queue */ |
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233 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp; |
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234 u32 tx_fifo_limit; |
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235 |
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236 struct napi_struct napi; |
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237 |
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238 unsigned int uncorr_errors; /* uncorrectable ECC errors */ |
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239 unsigned int corr_errors; /* correctable ECC errors */ |
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240 unsigned int restart_queue; |
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241 u32 txd_cmd; |
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242 |
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243 bool detect_tx_hung; |
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244 bool tx_hang_recheck; |
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245 u8 tx_timeout_factor; |
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246 |
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247 u32 tx_int_delay; |
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248 u32 tx_abs_int_delay; |
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249 |
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250 unsigned int total_tx_bytes; |
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251 unsigned int total_tx_packets; |
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252 unsigned int total_rx_bytes; |
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253 unsigned int total_rx_packets; |
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254 |
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255 /* Tx stats */ |
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256 u64 tpt_old; |
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257 u64 colc_old; |
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258 u32 gotc; |
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259 u64 gotc_old; |
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260 u32 tx_timeout_count; |
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261 u32 tx_fifo_head; |
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262 u32 tx_head_addr; |
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263 u32 tx_fifo_size; |
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264 u32 tx_dma_failed; |
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265 u32 tx_hwtstamp_timeouts; |
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266 |
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267 /* Rx */ |
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268 bool (*clean_rx)(struct e1000_ring *ring, int *work_done, |
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269 int work_to_do) ____cacheline_aligned_in_smp; |
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270 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count, |
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271 gfp_t gfp); |
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272 struct e1000_ring *rx_ring; |
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273 |
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274 u32 rx_int_delay; |
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275 u32 rx_abs_int_delay; |
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276 |
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277 /* Rx stats */ |
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278 u64 hw_csum_err; |
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279 u64 hw_csum_good; |
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280 u64 rx_hdr_split; |
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281 u32 gorc; |
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282 u64 gorc_old; |
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283 u32 alloc_rx_buff_failed; |
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284 u32 rx_dma_failed; |
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285 u32 rx_hwtstamp_cleared; |
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286 |
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287 unsigned int rx_ps_pages; |
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288 u16 rx_ps_bsize0; |
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289 u32 max_frame_size; |
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290 u32 min_frame_size; |
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291 |
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292 /* OS defined structs */ |
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293 struct net_device *netdev; |
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294 struct pci_dev *pdev; |
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295 |
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296 /* structs defined in e1000_hw.h */ |
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297 struct e1000_hw hw; |
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298 |
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299 spinlock_t stats64_lock; /* protects statistics counters */ |
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300 struct e1000_hw_stats stats; |
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301 struct e1000_phy_info phy_info; |
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302 struct e1000_phy_stats phy_stats; |
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303 |
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304 /* Snapshot of PHY registers */ |
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305 struct e1000_phy_regs phy_regs; |
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306 |
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307 struct e1000_ring test_tx_ring; |
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308 struct e1000_ring test_rx_ring; |
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309 u32 test_icr; |
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310 |
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311 u32 msg_enable; |
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312 unsigned int num_vectors; |
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313 struct msix_entry *msix_entries; |
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314 int int_mode; |
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315 u32 eiac_mask; |
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316 |
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317 u32 eeprom_wol; |
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318 u32 wol; |
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319 u32 pba; |
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320 u32 max_hw_frame_size; |
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321 |
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322 bool fc_autoneg; |
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323 |
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324 unsigned int flags; |
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325 unsigned int flags2; |
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326 struct work_struct downshift_task; |
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327 struct work_struct update_phy_task; |
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328 struct work_struct print_hang_task; |
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329 |
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330 int phy_hang_count; |
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331 |
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332 u16 tx_ring_count; |
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333 u16 rx_ring_count; |
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334 |
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335 struct hwtstamp_config hwtstamp_config; |
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336 struct delayed_work systim_overflow_work; |
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337 struct sk_buff *tx_hwtstamp_skb; |
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338 unsigned long tx_hwtstamp_start; |
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339 struct work_struct tx_hwtstamp_work; |
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340 spinlock_t systim_lock; /* protects SYSTIML/H regsters */ |
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341 struct cyclecounter cc; |
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342 struct timecounter tc; |
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343 struct ptp_clock *ptp_clock; |
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344 struct ptp_clock_info ptp_clock_info; |
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345 |
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346 u16 eee_advert; |
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347 }; |
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348 |
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349 struct e1000_info { |
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350 enum e1000_mac_type mac; |
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351 unsigned int flags; |
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352 unsigned int flags2; |
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353 u32 pba; |
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354 u32 max_hw_frame_size; |
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355 s32 (*get_variants)(struct e1000_adapter *); |
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356 const struct e1000_mac_operations *mac_ops; |
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357 const struct e1000_phy_operations *phy_ops; |
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358 const struct e1000_nvm_operations *nvm_ops; |
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359 }; |
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360 |
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361 s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca); |
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362 |
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363 /* The system time is maintained by a 64-bit counter comprised of the 32-bit |
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364 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore |
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365 * its resolution) is based on the contents of the TIMINCA register - it |
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366 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0). |
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367 * For the best accuracy, the incperiod should be as small as possible. The |
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368 * incvalue is scaled by a factor as large as possible (while still fitting |
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369 * in bits 23:0) so that relatively small clock corrections can be made. |
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370 * |
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371 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of |
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372 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n) |
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373 * bits to count nanoseconds leaving the rest for fractional nonseconds. |
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374 */ |
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375 #define INCVALUE_96MHz 125 |
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376 #define INCVALUE_SHIFT_96MHz 17 |
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377 #define INCPERIOD_SHIFT_96MHz 2 |
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378 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz) |
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379 |
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380 #define INCVALUE_25MHz 40 |
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381 #define INCVALUE_SHIFT_25MHz 18 |
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382 #define INCPERIOD_25MHz 1 |
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383 |
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384 /* Another drawback of scaling the incvalue by a large factor is the |
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385 * 64-bit SYSTIM register overflows more quickly. This is dealt with |
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386 * by simply reading the clock before it overflows. |
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387 * |
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388 * Clock ns bits Overflows after |
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389 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~ |
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390 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs |
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391 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours |
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392 */ |
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393 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4) |
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394 #define E1000_MAX_82574_SYSTIM_REREADS 50 |
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395 #define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL) |
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396 |
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397 /* hardware capability, feature, and workaround flags */ |
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398 #define FLAG_HAS_AMT (1 << 0) |
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399 #define FLAG_HAS_FLASH (1 << 1) |
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400 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) |
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401 #define FLAG_HAS_WOL (1 << 3) |
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402 /* reserved bit4 */ |
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403 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
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404 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) |
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405 #define FLAG_HAS_JUMBO_FRAMES (1 << 7) |
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406 #define FLAG_READ_ONLY_NVM (1 << 8) |
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407 #define FLAG_IS_ICH (1 << 9) |
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408 #define FLAG_HAS_MSIX (1 << 10) |
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409 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
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410 #define FLAG_IS_QUAD_PORT_A (1 << 12) |
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411 #define FLAG_IS_QUAD_PORT (1 << 13) |
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412 #define FLAG_HAS_HW_TIMESTAMP (1 << 14) |
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413 #define FLAG_APME_IN_WUC (1 << 15) |
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414 #define FLAG_APME_IN_CTRL3 (1 << 16) |
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415 #define FLAG_APME_CHECK_PORT_B (1 << 17) |
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416 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) |
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417 #define FLAG_NO_WAKE_UCAST (1 << 19) |
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418 #define FLAG_MNG_PT_ENABLED (1 << 20) |
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419 #define FLAG_RESET_OVERWRITES_LAA (1 << 21) |
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420 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) |
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421 #define FLAG_TARC_SET_BIT_ZERO (1 << 23) |
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422 #define FLAG_RX_NEEDS_RESTART (1 << 24) |
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423 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) |
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424 #define FLAG_SMART_POWER_DOWN (1 << 26) |
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425 #define FLAG_MSI_ENABLED (1 << 27) |
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426 /* reserved (1 << 28) */ |
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427 #define FLAG_TSO_FORCE (1 << 29) |
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428 #define FLAG_RESTART_NOW (1 << 30) |
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429 #define FLAG_MSI_TEST_FAILED (1 << 31) |
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430 |
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431 #define FLAG2_CRC_STRIPPING (1 << 0) |
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432 #define FLAG2_HAS_PHY_WAKEUP (1 << 1) |
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433 #define FLAG2_IS_DISCARDING (1 << 2) |
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434 #define FLAG2_DISABLE_ASPM_L1 (1 << 3) |
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435 #define FLAG2_HAS_PHY_STATS (1 << 4) |
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436 #define FLAG2_HAS_EEE (1 << 5) |
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437 #define FLAG2_DMA_BURST (1 << 6) |
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438 #define FLAG2_DISABLE_ASPM_L0S (1 << 7) |
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439 #define FLAG2_DISABLE_AIM (1 << 8) |
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440 #define FLAG2_CHECK_PHY_HANG (1 << 9) |
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441 #define FLAG2_NO_DISABLE_RX (1 << 10) |
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442 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11) |
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443 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12) |
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444 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13) |
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445 |
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446 #define E1000_RX_DESC_PS(R, i) \ |
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447 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
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448 #define E1000_RX_DESC_EXT(R, i) \ |
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449 (&(((union e1000_rx_desc_extended *)((R).desc))[i])) |
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450 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
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451 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
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452 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) |
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453 |
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454 enum e1000_state_t { |
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455 __E1000_TESTING, |
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456 __E1000_RESETTING, |
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457 __E1000_ACCESS_SHARED_RESOURCE, |
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458 __E1000_DOWN |
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459 }; |
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460 |
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461 enum latency_range { |
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462 lowest_latency = 0, |
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463 low_latency = 1, |
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464 bulk_latency = 2, |
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465 latency_invalid = 255 |
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466 }; |
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467 |
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468 extern char e1000e_driver_name[]; |
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469 extern const char e1000e_driver_version[]; |
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470 |
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471 void e1000e_check_options(struct e1000_adapter *adapter); |
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472 void e1000e_set_ethtool_ops(struct net_device *netdev); |
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473 |
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474 int e1000e_up(struct e1000_adapter *adapter); |
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475 void e1000e_down(struct e1000_adapter *adapter, bool reset); |
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476 void e1000e_reinit_locked(struct e1000_adapter *adapter); |
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477 void e1000e_reset(struct e1000_adapter *adapter); |
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478 void e1000e_power_up_phy(struct e1000_adapter *adapter); |
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479 int e1000e_setup_rx_resources(struct e1000_ring *ring); |
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480 int e1000e_setup_tx_resources(struct e1000_ring *ring); |
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481 void e1000e_free_rx_resources(struct e1000_ring *ring); |
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482 void e1000e_free_tx_resources(struct e1000_ring *ring); |
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483 struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev, |
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484 struct rtnl_link_stats64 *stats); |
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485 void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); |
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486 void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); |
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487 void e1000e_get_hw_control(struct e1000_adapter *adapter); |
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488 void e1000e_release_hw_control(struct e1000_adapter *adapter); |
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489 void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr); |
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490 |
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491 extern unsigned int copybreak; |
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492 |
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493 extern const struct e1000_info e1000_82571_info; |
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494 extern const struct e1000_info e1000_82572_info; |
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495 extern const struct e1000_info e1000_82573_info; |
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496 extern const struct e1000_info e1000_82574_info; |
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497 extern const struct e1000_info e1000_82583_info; |
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498 extern const struct e1000_info e1000_ich8_info; |
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499 extern const struct e1000_info e1000_ich9_info; |
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500 extern const struct e1000_info e1000_ich10_info; |
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501 extern const struct e1000_info e1000_pch_info; |
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502 extern const struct e1000_info e1000_pch2_info; |
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503 extern const struct e1000_info e1000_pch_lpt_info; |
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504 extern const struct e1000_info e1000_es2_info; |
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505 |
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506 void e1000e_ptp_init(struct e1000_adapter *adapter); |
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507 void e1000e_ptp_remove(struct e1000_adapter *adapter); |
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508 |
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509 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
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510 { |
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511 return hw->phy.ops.reset(hw); |
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512 } |
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513 |
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514 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) |
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515 { |
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516 return hw->phy.ops.read_reg(hw, offset, data); |
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517 } |
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518 |
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519 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
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520 { |
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521 return hw->phy.ops.read_reg_locked(hw, offset, data); |
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522 } |
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523 |
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524 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) |
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525 { |
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526 return hw->phy.ops.write_reg(hw, offset, data); |
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527 } |
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528 |
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529 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data) |
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530 { |
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531 return hw->phy.ops.write_reg_locked(hw, offset, data); |
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532 } |
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533 |
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534 void e1000e_reload_nvm_generic(struct e1000_hw *hw); |
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535 |
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536 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw) |
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537 { |
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538 if (hw->mac.ops.read_mac_addr) |
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539 return hw->mac.ops.read_mac_addr(hw); |
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540 |
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541 return e1000_read_mac_addr_generic(hw); |
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542 } |
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543 |
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544 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) |
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545 { |
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546 return hw->nvm.ops.validate(hw); |
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547 } |
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548 |
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549 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) |
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550 { |
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551 return hw->nvm.ops.update(hw); |
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552 } |
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553 |
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554 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
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555 u16 *data) |
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556 { |
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557 return hw->nvm.ops.read(hw, offset, words, data); |
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558 } |
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559 |
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560 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, |
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561 u16 *data) |
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562 { |
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563 return hw->nvm.ops.write(hw, offset, words, data); |
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564 } |
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565 |
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566 static inline s32 e1000_get_phy_info(struct e1000_hw *hw) |
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567 { |
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568 return hw->phy.ops.get_info(hw); |
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569 } |
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570 |
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571 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) |
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572 { |
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573 return readl(hw->hw_addr + reg); |
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574 } |
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575 |
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576 #define er32(reg) __er32(hw, E1000_##reg) |
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577 |
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578 s32 __ew32_prepare(struct e1000_hw *hw); |
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579 void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); |
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580 |
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581 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
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582 |
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583 #define e1e_flush() er32(STATUS) |
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584 |
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585 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ |
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586 (__ew32((a), (reg + ((offset) << 2)), (value))) |
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587 |
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588 #define E1000_READ_REG_ARRAY(a, reg, offset) \ |
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589 (readl((a)->hw_addr + reg + ((offset) << 2))) |
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590 |
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591 #endif /* _E1000_H_ */ |