1 /* Intel PRO/1000 Linux driver

     2  * Copyright(c) 1999 - 2014 Intel Corporation.

     3  *

     4  * This program is free software; you can redistribute it and/or modify it

     5  * under the terms and conditions of the GNU General Public License,

     6  * version 2, as published by the Free Software Foundation.

     7  *

     8  * This program is distributed in the hope it will be useful, but WITHOUT

     9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    11  * more details.

    12  *

    13  * The full GNU General Public License is included in this distribution in

    14  * the file called "COPYING".

    15  *

    16  * Contact Information:

    17  * Linux NICS <linux.nics@intel.com>

    18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    20  */

    21 

    22 /* 82571EB Gigabit Ethernet Controller

    23  * 82571EB Gigabit Ethernet Controller (Copper)

    24  * 82571EB Gigabit Ethernet Controller (Fiber)

    25  * 82571EB Dual Port Gigabit Mezzanine Adapter

    26  * 82571EB Quad Port Gigabit Mezzanine Adapter

    27  * 82571PT Gigabit PT Quad Port Server ExpressModule

    28  * 82572EI Gigabit Ethernet Controller (Copper)

    29  * 82572EI Gigabit Ethernet Controller (Fiber)

    30  * 82572EI Gigabit Ethernet Controller

    31  * 82573V Gigabit Ethernet Controller (Copper)

    32  * 82573E Gigabit Ethernet Controller (Copper)

    33  * 82573L Gigabit Ethernet Controller

    34  * 82574L Gigabit Network Connection

    35  * 82583V Gigabit Network Connection

    36  */

    37 

    38 #include "e1000-3.16-ethercat.h"

    39 

    40 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

    41 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

    42 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);

    43 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

    44 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

    45 				      u16 words, u16 *data);

    46 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);

    47 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);

    48 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);

    49 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);

    50 static s32 e1000_led_on_82574(struct e1000_hw *hw);

    51 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);

    52 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);

    53 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);

    54 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);

    55 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);

    56 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);

    57 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);

    58 

    59 /**

    60  *  e1000_init_phy_params_82571 - Init PHY func ptrs.

    61  *  @hw: pointer to the HW structure

    62  **/

    63 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)

    64 {

    65 	struct e1000_phy_info *phy = &hw->phy;

    66 	s32 ret_val __attribute__ ((unused));

    67 

    68 	if (hw->phy.media_type != e1000_media_type_copper) {

    69 		phy->type = e1000_phy_none;

    70 		return 0;

    71 	}

    72 

    73 	phy->addr = 1;

    74 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    75 	phy->reset_delay_us = 100;

    76 

    77 	phy->ops.power_up = e1000_power_up_phy_copper;

    78 	phy->ops.power_down = e1000_power_down_phy_copper_82571;

    79 

    80 	switch (hw->mac.type) {

    81 	case e1000_82571:

    82 	case e1000_82572:

    83 		phy->type = e1000_phy_igp_2;

    84 		break;

    85 	case e1000_82573:

    86 		phy->type = e1000_phy_m88;

    87 		break;

    88 	case e1000_82574:

    89 	case e1000_82583:

    90 		phy->type = e1000_phy_bm;

    91 		phy->ops.acquire = e1000_get_hw_semaphore_82574;

    92 		phy->ops.release = e1000_put_hw_semaphore_82574;

    93 		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;

    94 		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;

    95 		break;

    96 	default:

    97 		return -E1000_ERR_PHY;

    98 		break;

    99 	}

   100 

   101 	/* This can only be done after all function pointers are setup. */

   102 	ret_val = e1000_get_phy_id_82571(hw);

   103 	if (ret_val) {

   104 		e_dbg("Error getting PHY ID\n");

   105 		return ret_val;

   106 	}

   107 

   108 	/* Verify phy id */

   109 	switch (hw->mac.type) {

   110 	case e1000_82571:

   111 	case e1000_82572:

   112 		if (phy->id != IGP01E1000_I_PHY_ID)

   113 			ret_val = -E1000_ERR_PHY;

   114 		break;

   115 	case e1000_82573:

   116 		if (phy->id != M88E1111_I_PHY_ID)

   117 			ret_val = -E1000_ERR_PHY;

   118 		break;

   119 	case e1000_82574:

   120 	case e1000_82583:

   121 		if (phy->id != BME1000_E_PHY_ID_R2)

   122 			ret_val = -E1000_ERR_PHY;

   123 		break;

   124 	default:

   125 		ret_val = -E1000_ERR_PHY;

   126 		break;

   127 	}

   128 

   129 	if (ret_val)

   130 		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);

   131 

   132 	return ret_val;

   133 }

   134 

   135 /**

   136  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.

   137  *  @hw: pointer to the HW structure

   138  **/

   139 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)

   140 {

   141 	struct e1000_nvm_info *nvm = &hw->nvm;

   142 	u32 eecd = er32(EECD);

   143 	u16 size;

   144 

   145 	nvm->opcode_bits = 8;

   146 	nvm->delay_usec = 1;

   147 	switch (nvm->override) {

   148 	case e1000_nvm_override_spi_large:

   149 		nvm->page_size = 32;

   150 		nvm->address_bits = 16;

   151 		break;

   152 	case e1000_nvm_override_spi_small:

   153 		nvm->page_size = 8;

   154 		nvm->address_bits = 8;

   155 		break;

   156 	default:

   157 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   158 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   159 		break;

   160 	}

   161 

   162 	switch (hw->mac.type) {

   163 	case e1000_82573:

   164 	case e1000_82574:

   165 	case e1000_82583:

   166 		if (((eecd >> 15) & 0x3) == 0x3) {

   167 			nvm->type = e1000_nvm_flash_hw;

   168 			nvm->word_size = 2048;

   169 			/* Autonomous Flash update bit must be cleared due

   170 			 * to Flash update issue.

   171 			 */

   172 			eecd &= ~E1000_EECD_AUPDEN;

   173 			ew32(EECD, eecd);

   174 			break;

   175 		}

   176 		/* Fall Through */

   177 	default:

   178 		nvm->type = e1000_nvm_eeprom_spi;

   179 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   180 			     E1000_EECD_SIZE_EX_SHIFT);

   181 		/* Added to a constant, "size" becomes the left-shift value

   182 		 * for setting word_size.

   183 		 */

   184 		size += NVM_WORD_SIZE_BASE_SHIFT;

   185 

   186 		/* EEPROM access above 16k is unsupported */

   187 		if (size > 14)

   188 			size = 14;

   189 		nvm->word_size = 1 << size;

   190 		break;

   191 	}

   192 

   193 	/* Function Pointers */

   194 	switch (hw->mac.type) {

   195 	case e1000_82574:

   196 	case e1000_82583:

   197 		nvm->ops.acquire = e1000_get_hw_semaphore_82574;

   198 		nvm->ops.release = e1000_put_hw_semaphore_82574;

   199 		break;

   200 	default:

   201 		break;

   202 	}

   203 

   204 	return 0;

   205 }

   206 

   207 /**

   208  *  e1000_init_mac_params_82571 - Init MAC func ptrs.

   209  *  @hw: pointer to the HW structure

   210  **/

   211 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)

   212 {

   213 	struct e1000_mac_info *mac = &hw->mac;

   214 	u32 swsm = 0;

   215 	u32 swsm2 = 0;

   216 	bool force_clear_smbi = false;

   217 

   218 	/* Set media type and media-dependent function pointers */

   219 	switch (hw->adapter->pdev->device) {

   220 	case E1000_DEV_ID_82571EB_FIBER:

   221 	case E1000_DEV_ID_82572EI_FIBER:

   222 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   223 		hw->phy.media_type = e1000_media_type_fiber;

   224 		mac->ops.setup_physical_interface =

   225 		    e1000_setup_fiber_serdes_link_82571;

   226 		mac->ops.check_for_link = e1000e_check_for_fiber_link;

   227 		mac->ops.get_link_up_info =

   228 		    e1000e_get_speed_and_duplex_fiber_serdes;

   229 		break;

   230 	case E1000_DEV_ID_82571EB_SERDES:

   231 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   232 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   233 	case E1000_DEV_ID_82572EI_SERDES:

   234 		hw->phy.media_type = e1000_media_type_internal_serdes;

   235 		mac->ops.setup_physical_interface =

   236 		    e1000_setup_fiber_serdes_link_82571;

   237 		mac->ops.check_for_link = e1000_check_for_serdes_link_82571;

   238 		mac->ops.get_link_up_info =

   239 		    e1000e_get_speed_and_duplex_fiber_serdes;

   240 		break;

   241 	default:

   242 		hw->phy.media_type = e1000_media_type_copper;

   243 		mac->ops.setup_physical_interface =

   244 		    e1000_setup_copper_link_82571;

   245 		mac->ops.check_for_link = e1000e_check_for_copper_link;

   246 		mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;

   247 		break;

   248 	}

   249 

   250 	/* Set mta register count */

   251 	mac->mta_reg_count = 128;

   252 	/* Set rar entry count */

   253 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   254 	/* Adaptive IFS supported */

   255 	mac->adaptive_ifs = true;

   256 

   257 	/* MAC-specific function pointers */

   258 	switch (hw->mac.type) {

   259 	case e1000_82573:

   260 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   261 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   262 		mac->ops.led_on = e1000e_led_on_generic;

   263 		mac->ops.blink_led = e1000e_blink_led_generic;

   264 

   265 		/* FWSM register */

   266 		mac->has_fwsm = true;

   267 		/* ARC supported; valid only if manageability features are

   268 		 * enabled.

   269 		 */

   270 		mac->arc_subsystem_valid = !!(er32(FWSM) &

   271 					      E1000_FWSM_MODE_MASK);

   272 		break;

   273 	case e1000_82574:

   274 	case e1000_82583:

   275 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   276 		mac->ops.check_mng_mode = e1000_check_mng_mode_82574;

   277 		mac->ops.led_on = e1000_led_on_82574;

   278 		break;

   279 	default:

   280 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   281 		mac->ops.led_on = e1000e_led_on_generic;

   282 		mac->ops.blink_led = e1000e_blink_led_generic;

   283 

   284 		/* FWSM register */

   285 		mac->has_fwsm = true;

   286 		break;

   287 	}

   288 

   289 	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before

   290 	 * first NVM or PHY access. This should be done for single-port

   291 	 * devices, and for one port only on dual-port devices so that

   292 	 * for those devices we can still use the SMBI lock to synchronize

   293 	 * inter-port accesses to the PHY & NVM.

   294 	 */

   295 	switch (hw->mac.type) {

   296 	case e1000_82571:

   297 	case e1000_82572:

   298 		swsm2 = er32(SWSM2);

   299 

   300 		if (!(swsm2 & E1000_SWSM2_LOCK)) {

   301 			/* Only do this for the first interface on this card */

   302 			ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);

   303 			force_clear_smbi = true;

   304 		} else {

   305 			force_clear_smbi = false;

   306 		}

   307 		break;

   308 	default:

   309 		force_clear_smbi = true;

   310 		break;

   311 	}

   312 

   313 	if (force_clear_smbi) {

   314 		/* Make sure SWSM.SMBI is clear */

   315 		swsm = er32(SWSM);

   316 		if (swsm & E1000_SWSM_SMBI) {

   317 			/* This bit should not be set on a first interface, and

   318 			 * indicates that the bootagent or EFI code has

   319 			 * improperly left this bit enabled

   320 			 */

   321 			e_dbg("Please update your 82571 Bootagent\n");

   322 		}

   323 		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

   324 	}

   325 

   326 	/* Initialize device specific counter of SMBI acquisition timeouts. */

   327 	hw->dev_spec.e82571.smb_counter = 0;

   328 

   329 	return 0;

   330 }

   331 

   332 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)

   333 {

   334 	struct e1000_hw *hw = &adapter->hw;

   335 	static int global_quad_port_a;	/* global port a indication */

   336 	struct pci_dev *pdev = adapter->pdev;

   337 	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;

   338 	s32 rc;

   339 

   340 	rc = e1000_init_mac_params_82571(hw);

   341 	if (rc)

   342 		return rc;

   343 

   344 	rc = e1000_init_nvm_params_82571(hw);

   345 	if (rc)

   346 		return rc;

   347 

   348 	rc = e1000_init_phy_params_82571(hw);

   349 	if (rc)

   350 		return rc;

   351 

   352 	/* tag quad port adapters first, it's used below */

   353 	switch (pdev->device) {

   354 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   355 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   356 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:

   357 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   358 		adapter->flags |= FLAG_IS_QUAD_PORT;

   359 		/* mark the first port */

   360 		if (global_quad_port_a == 0)

   361 			adapter->flags |= FLAG_IS_QUAD_PORT_A;

   362 		/* Reset for multiple quad port adapters */

   363 		global_quad_port_a++;

   364 		if (global_quad_port_a == 4)

   365 			global_quad_port_a = 0;

   366 		break;

   367 	default:

   368 		break;

   369 	}

   370 

   371 	switch (adapter->hw.mac.type) {

   372 	case e1000_82571:

   373 		/* these dual ports don't have WoL on port B at all */

   374 		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||

   375 		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||

   376 		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&

   377 		    (is_port_b))

   378 			adapter->flags &= ~FLAG_HAS_WOL;

   379 		/* quad ports only support WoL on port A */

   380 		if (adapter->flags & FLAG_IS_QUAD_PORT &&

   381 		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))

   382 			adapter->flags &= ~FLAG_HAS_WOL;

   383 		/* Does not support WoL on any port */

   384 		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)

   385 			adapter->flags &= ~FLAG_HAS_WOL;

   386 		break;

   387 	case e1000_82573:

   388 		if (pdev->device == E1000_DEV_ID_82573L) {

   389 			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;

   390 			adapter->max_hw_frame_size = DEFAULT_JUMBO;

   391 		}

   392 		break;

   393 	default:

   394 		break;

   395 	}

   396 

   397 	return 0;

   398 }

   399 

   400 /**

   401  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision

   402  *  @hw: pointer to the HW structure

   403  *

   404  *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   405  *  revision in the hardware structure.

   406  **/

   407 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)

   408 {

   409 	struct e1000_phy_info *phy = &hw->phy;

   410 	s32 ret_val;

   411 	u16 phy_id = 0;

   412 

   413 	switch (hw->mac.type) {

   414 	case e1000_82571:

   415 	case e1000_82572:

   416 		/* The 82571 firmware may still be configuring the PHY.

   417 		 * In this case, we cannot access the PHY until the

   418 		 * configuration is done.  So we explicitly set the

   419 		 * PHY ID.

   420 		 */

   421 		phy->id = IGP01E1000_I_PHY_ID;

   422 		break;

   423 	case e1000_82573:

   424 		return e1000e_get_phy_id(hw);

   425 		break;

   426 	case e1000_82574:

   427 	case e1000_82583:

   428 		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);

   429 		if (ret_val)

   430 			return ret_val;

   431 

   432 		phy->id = (u32)(phy_id << 16);

   433 		usleep_range(20, 40);

   434 		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);

   435 		if (ret_val)

   436 			return ret_val;

   437 

   438 		phy->id |= (u32)(phy_id);

   439 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   440 		break;

   441 	default:

   442 		return -E1000_ERR_PHY;

   443 		break;

   444 	}

   445 

   446 	return 0;

   447 }

   448 

   449 /**

   450  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore

   451  *  @hw: pointer to the HW structure

   452  *

   453  *  Acquire the HW semaphore to access the PHY or NVM

   454  **/

   455 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)

   456 {

   457 	u32 swsm;

   458 	s32 sw_timeout = hw->nvm.word_size + 1;

   459 	s32 fw_timeout = hw->nvm.word_size + 1;

   460 	s32 i = 0;

   461 

   462 	/* If we have timedout 3 times on trying to acquire

   463 	 * the inter-port SMBI semaphore, there is old code

   464 	 * operating on the other port, and it is not

   465 	 * releasing SMBI. Modify the number of times that

   466 	 * we try for the semaphore to interwork with this

   467 	 * older code.

   468 	 */

   469 	if (hw->dev_spec.e82571.smb_counter > 2)

   470 		sw_timeout = 1;

   471 

   472 	/* Get the SW semaphore */

   473 	while (i < sw_timeout) {

   474 		swsm = er32(SWSM);

   475 		if (!(swsm & E1000_SWSM_SMBI))

   476 			break;

   477 

   478 		usleep_range(50, 100);

   479 		i++;

   480 	}

   481 

   482 	if (i == sw_timeout) {

   483 		e_dbg("Driver can't access device - SMBI bit is set.\n");

   484 		hw->dev_spec.e82571.smb_counter++;

   485 	}

   486 	/* Get the FW semaphore. */

   487 	for (i = 0; i < fw_timeout; i++) {

   488 		swsm = er32(SWSM);

   489 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

   490 

   491 		/* Semaphore acquired if bit latched */

   492 		if (er32(SWSM) & E1000_SWSM_SWESMBI)

   493 			break;

   494 

   495 		usleep_range(50, 100);

   496 	}

   497 

   498 	if (i == fw_timeout) {

   499 		/* Release semaphores */

   500 		e1000_put_hw_semaphore_82571(hw);

   501 		e_dbg("Driver can't access the NVM\n");

   502 		return -E1000_ERR_NVM;

   503 	}

   504 

   505 	return 0;

   506 }

   507 

   508 /**

   509  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore

   510  *  @hw: pointer to the HW structure

   511  *

   512  *  Release hardware semaphore used to access the PHY or NVM

   513  **/

   514 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)

   515 {

   516 	u32 swsm;

   517 

   518 	swsm = er32(SWSM);

   519 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

   520 	ew32(SWSM, swsm);

   521 }

   522 

   523 /**

   524  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore

   525  *  @hw: pointer to the HW structure

   526  *

   527  *  Acquire the HW semaphore during reset.

   528  *

   529  **/

   530 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)

   531 {

   532 	u32 extcnf_ctrl;

   533 	s32 i = 0;

   534 

   535 	extcnf_ctrl = er32(EXTCNF_CTRL);

   536 	do {

   537 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   538 		ew32(EXTCNF_CTRL, extcnf_ctrl);

   539 		extcnf_ctrl = er32(EXTCNF_CTRL);

   540 

   541 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   542 			break;

   543 

   544 		usleep_range(2000, 4000);

   545 		i++;

   546 	} while (i < MDIO_OWNERSHIP_TIMEOUT);

   547 

   548 	if (i == MDIO_OWNERSHIP_TIMEOUT) {

   549 		/* Release semaphores */

   550 		e1000_put_hw_semaphore_82573(hw);

   551 		e_dbg("Driver can't access the PHY\n");

   552 		return -E1000_ERR_PHY;

   553 	}

   554 

   555 	return 0;

   556 }

   557 

   558 /**

   559  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore

   560  *  @hw: pointer to the HW structure

   561  *

   562  *  Release hardware semaphore used during reset.

   563  *

   564  **/

   565 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)

   566 {

   567 	u32 extcnf_ctrl;

   568 

   569 	extcnf_ctrl = er32(EXTCNF_CTRL);

   570 	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   571 	ew32(EXTCNF_CTRL, extcnf_ctrl);

   572 }

   573 

   574 static DEFINE_MUTEX(swflag_mutex);

   575 

   576 /**

   577  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore

   578  *  @hw: pointer to the HW structure

   579  *

   580  *  Acquire the HW semaphore to access the PHY or NVM.

   581  *

   582  **/

   583 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)

   584 {

   585 	s32 ret_val;

   586 

   587 	mutex_lock(&swflag_mutex);

   588 	ret_val = e1000_get_hw_semaphore_82573(hw);

   589 	if (ret_val)

   590 		mutex_unlock(&swflag_mutex);

   591 	return ret_val;

   592 }

   593 

   594 /**

   595  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore

   596  *  @hw: pointer to the HW structure

   597  *

   598  *  Release hardware semaphore used to access the PHY or NVM

   599  *

   600  **/

   601 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)

   602 {

   603 	e1000_put_hw_semaphore_82573(hw);

   604 	mutex_unlock(&swflag_mutex);

   605 }

   606 

   607 /**

   608  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state

   609  *  @hw: pointer to the HW structure

   610  *  @active: true to enable LPLU, false to disable

   611  *

   612  *  Sets the LPLU D0 state according to the active flag.

   613  *  LPLU will not be activated unless the

   614  *  device autonegotiation advertisement meets standards of

   615  *  either 10 or 10/100 or 10/100/1000 at all duplexes.

   616  *  This is a function pointer entry point only called by

   617  *  PHY setup routines.

   618  **/

   619 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)

   620 {

   621 	u32 data = er32(POEMB);

   622 

   623 	if (active)

   624 		data |= E1000_PHY_CTRL_D0A_LPLU;

   625 	else

   626 		data &= ~E1000_PHY_CTRL_D0A_LPLU;

   627 

   628 	ew32(POEMB, data);

   629 	return 0;

   630 }

   631 

   632 /**

   633  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3

   634  *  @hw: pointer to the HW structure

   635  *  @active: boolean used to enable/disable lplu

   636  *

   637  *  The low power link up (lplu) state is set to the power management level D3

   638  *  when active is true, else clear lplu for D3. LPLU

   639  *  is used during Dx states where the power conservation is most important.

   640  *  During driver activity, SmartSpeed should be enabled so performance is

   641  *  maintained.

   642  **/

   643 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)

   644 {

   645 	u32 data = er32(POEMB);

   646 

   647 	if (!active) {

   648 		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;

   649 	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

   650 		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||

   651 		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {

   652 		data |= E1000_PHY_CTRL_NOND0A_LPLU;

   653 	}

   654 

   655 	ew32(POEMB, data);

   656 	return 0;

   657 }

   658 

   659 /**

   660  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM

   661  *  @hw: pointer to the HW structure

   662  *

   663  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.

   664  *  Then for non-82573 hardware, set the EEPROM access request bit and wait

   665  *  for EEPROM access grant bit.  If the access grant bit is not set, release

   666  *  hardware semaphore.

   667  **/

   668 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)

   669 {

   670 	s32 ret_val;

   671 

   672 	ret_val = e1000_get_hw_semaphore_82571(hw);

   673 	if (ret_val)

   674 		return ret_val;

   675 

   676 	switch (hw->mac.type) {

   677 	case e1000_82573:

   678 		break;

   679 	default:

   680 		ret_val = e1000e_acquire_nvm(hw);

   681 		break;

   682 	}

   683 

   684 	if (ret_val)

   685 		e1000_put_hw_semaphore_82571(hw);

   686 

   687 	return ret_val;

   688 }

   689 

   690 /**

   691  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM

   692  *  @hw: pointer to the HW structure

   693  *

   694  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.

   695  **/

   696 static void e1000_release_nvm_82571(struct e1000_hw *hw)

   697 {

   698 	e1000e_release_nvm(hw);

   699 	e1000_put_hw_semaphore_82571(hw);

   700 }

   701 

   702 /**

   703  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface

   704  *  @hw: pointer to the HW structure

   705  *  @offset: offset within the EEPROM to be written to

   706  *  @words: number of words to write

   707  *  @data: 16 bit word(s) to be written to the EEPROM

   708  *

   709  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.

   710  *

   711  *  If e1000e_update_nvm_checksum is not called after this function, the

   712  *  EEPROM will most likely contain an invalid checksum.

   713  **/

   714 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,

   715 				 u16 *data)

   716 {

   717 	s32 ret_val;

   718 

   719 	switch (hw->mac.type) {

   720 	case e1000_82573:

   721 	case e1000_82574:

   722 	case e1000_82583:

   723 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);

   724 		break;

   725 	case e1000_82571:

   726 	case e1000_82572:

   727 		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);

   728 		break;

   729 	default:

   730 		ret_val = -E1000_ERR_NVM;

   731 		break;

   732 	}

   733 

   734 	return ret_val;

   735 }

   736 

   737 /**

   738  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum

   739  *  @hw: pointer to the HW structure

   740  *

   741  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM

   742  *  up to the checksum.  Then calculates the EEPROM checksum and writes the

   743  *  value to the EEPROM.

   744  **/

   745 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)

   746 {

   747 	u32 eecd;

   748 	s32 ret_val;

   749 	u16 i;

   750 

   751 	ret_val = e1000e_update_nvm_checksum_generic(hw);

   752 	if (ret_val)

   753 		return ret_val;

   754 

   755 	/* If our nvm is an EEPROM, then we're done

   756 	 * otherwise, commit the checksum to the flash NVM.

   757 	 */

   758 	if (hw->nvm.type != e1000_nvm_flash_hw)

   759 		return 0;

   760 

   761 	/* Check for pending operations. */

   762 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   763 		usleep_range(1000, 2000);

   764 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   765 			break;

   766 	}

   767 

   768 	if (i == E1000_FLASH_UPDATES)

   769 		return -E1000_ERR_NVM;

   770 

   771 	/* Reset the firmware if using STM opcode. */

   772 	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

   773 		/* The enabling of and the actual reset must be done

   774 		 * in two write cycles.

   775 		 */

   776 		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

   777 		e1e_flush();

   778 		ew32(HICR, E1000_HICR_FW_RESET);

   779 	}

   780 

   781 	/* Commit the write to flash */

   782 	eecd = er32(EECD) | E1000_EECD_FLUPD;

   783 	ew32(EECD, eecd);

   784 

   785 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   786 		usleep_range(1000, 2000);

   787 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   788 			break;

   789 	}

   790 

   791 	if (i == E1000_FLASH_UPDATES)

   792 		return -E1000_ERR_NVM;

   793 

   794 	return 0;

   795 }

   796 

   797 /**

   798  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum

   799  *  @hw: pointer to the HW structure

   800  *

   801  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM

   802  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.

   803  **/

   804 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)

   805 {

   806 	if (hw->nvm.type == e1000_nvm_flash_hw)

   807 		e1000_fix_nvm_checksum_82571(hw);

   808 

   809 	return e1000e_validate_nvm_checksum_generic(hw);

   810 }

   811 

   812 /**

   813  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon

   814  *  @hw: pointer to the HW structure

   815  *  @offset: offset within the EEPROM to be written to

   816  *  @words: number of words to write

   817  *  @data: 16 bit word(s) to be written to the EEPROM

   818  *

   819  *  After checking for invalid values, poll the EEPROM to ensure the previous

   820  *  command has completed before trying to write the next word.  After write

   821  *  poll for completion.

   822  *

   823  *  If e1000e_update_nvm_checksum is not called after this function, the

   824  *  EEPROM will most likely contain an invalid checksum.

   825  **/

   826 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

   827 				      u16 words, u16 *data)

   828 {

   829 	struct e1000_nvm_info *nvm = &hw->nvm;

   830 	u32 i, eewr = 0;

   831 	s32 ret_val = 0;

   832 

   833 	/* A check for invalid values:  offset too large, too many words,

   834 	 * and not enough words.

   835 	 */

   836 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

   837 	    (words == 0)) {

   838 		e_dbg("nvm parameter(s) out of bounds\n");

   839 		return -E1000_ERR_NVM;

   840 	}

   841 

   842 	for (i = 0; i < words; i++) {

   843 		eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |

   844 			((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |

   845 			E1000_NVM_RW_REG_START);

   846 

   847 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   848 		if (ret_val)

   849 			break;

   850 

   851 		ew32(EEWR, eewr);

   852 

   853 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   854 		if (ret_val)

   855 			break;

   856 	}

   857 

   858 	return ret_val;

   859 }

   860 

   861 /**

   862  *  e1000_get_cfg_done_82571 - Poll for configuration done

   863  *  @hw: pointer to the HW structure

   864  *

   865  *  Reads the management control register for the config done bit to be set.

   866  **/

   867 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)

   868 {

   869 	s32 timeout = PHY_CFG_TIMEOUT;

   870 

   871 	while (timeout) {

   872 		if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)

   873 			break;

   874 		usleep_range(1000, 2000);

   875 		timeout--;

   876 	}

   877 	if (!timeout) {

   878 		e_dbg("MNG configuration cycle has not completed.\n");

   879 		return -E1000_ERR_RESET;

   880 	}

   881 

   882 	return 0;

   883 }

   884 

   885 /**

   886  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state

   887  *  @hw: pointer to the HW structure

   888  *  @active: true to enable LPLU, false to disable

   889  *

   890  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU

   891  *  this function also disables smart speed and vice versa.  LPLU will not be

   892  *  activated unless the device autonegotiation advertisement meets standards

   893  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function

   894  *  pointer entry point only called by PHY setup routines.

   895  **/

   896 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)

   897 {

   898 	struct e1000_phy_info *phy = &hw->phy;

   899 	s32 ret_val;

   900 	u16 data;

   901 

   902 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);

   903 	if (ret_val)

   904 		return ret_val;

   905 

   906 	if (active) {

   907 		data |= IGP02E1000_PM_D0_LPLU;

   908 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   909 		if (ret_val)

   910 			return ret_val;

   911 

   912 		/* When LPLU is enabled, we should disable SmartSpeed */

   913 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);

   914 		if (ret_val)

   915 			return ret_val;

   916 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   917 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);

   918 		if (ret_val)

   919 			return ret_val;

   920 	} else {

   921 		data &= ~IGP02E1000_PM_D0_LPLU;

   922 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   923 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used

   924 		 * during Dx states where the power conservation is most

   925 		 * important.  During driver activity we should enable

   926 		 * SmartSpeed, so performance is maintained.

   927 		 */

   928 		if (phy->smart_speed == e1000_smart_speed_on) {

   929 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   930 					   &data);

   931 			if (ret_val)

   932 				return ret_val;

   933 

   934 			data |= IGP01E1000_PSCFR_SMART_SPEED;

   935 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   936 					   data);

   937 			if (ret_val)

   938 				return ret_val;

   939 		} else if (phy->smart_speed == e1000_smart_speed_off) {

   940 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   941 					   &data);

   942 			if (ret_val)

   943 				return ret_val;

   944 

   945 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   946 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   947 					   data);

   948 			if (ret_val)

   949 				return ret_val;

   950 		}

   951 	}

   952 

   953 	return 0;

   954 }

   955 

   956 /**

   957  *  e1000_reset_hw_82571 - Reset hardware

   958  *  @hw: pointer to the HW structure

   959  *

   960  *  This resets the hardware into a known state.

   961  **/

   962 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

   963 {

   964 	u32 ctrl, ctrl_ext, eecd, tctl;

   965 	s32 ret_val;

   966 

   967 	/* Prevent the PCI-E bus from sticking if there is no TLP connection

   968 	 * on the last TLP read/write transaction when MAC is reset.

   969 	 */

   970 	ret_val = e1000e_disable_pcie_master(hw);

   971 	if (ret_val)

   972 		e_dbg("PCI-E Master disable polling has failed.\n");

   973 

   974 	e_dbg("Masking off all interrupts\n");

   975 	ew32(IMC, 0xffffffff);

   976 

   977 	ew32(RCTL, 0);

   978 	tctl = er32(TCTL);

   979 	tctl &= ~E1000_TCTL_EN;

   980 	ew32(TCTL, tctl);

   981 	e1e_flush();

   982 

   983 	usleep_range(10000, 20000);

   984 

   985 	/* Must acquire the MDIO ownership before MAC reset.

   986 	 * Ownership defaults to firmware after a reset.

   987 	 */

   988 	switch (hw->mac.type) {

   989 	case e1000_82573:

   990 		ret_val = e1000_get_hw_semaphore_82573(hw);

   991 		break;

   992 	case e1000_82574:

   993 	case e1000_82583:

   994 		ret_val = e1000_get_hw_semaphore_82574(hw);

   995 		break;

   996 	default:

   997 		break;

   998 	}

   999 

  1000 	ctrl = er32(CTRL);

  1001 

  1002 	e_dbg("Issuing a global reset to MAC\n");

  1003 	ew32(CTRL, ctrl | E1000_CTRL_RST);

  1004 

  1005 	/* Must release MDIO ownership and mutex after MAC reset. */

  1006 	switch (hw->mac.type) {

  1007 	case e1000_82573:

  1008 		/* Release mutex only if the hw semaphore is acquired */

  1009 		if (!ret_val)

  1010 			e1000_put_hw_semaphore_82573(hw);

  1011 		break;

  1012 	case e1000_82574:

  1013 	case e1000_82583:

  1014 		/* Release mutex only if the hw semaphore is acquired */

  1015 		if (!ret_val)

  1016 			e1000_put_hw_semaphore_82574(hw);

  1017 		break;

  1018 	default:

  1019 		break;

  1020 	}

  1021 

  1022 	if (hw->nvm.type == e1000_nvm_flash_hw) {

  1023 		usleep_range(10, 20);

  1024 		ctrl_ext = er32(CTRL_EXT);

  1025 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

  1026 		ew32(CTRL_EXT, ctrl_ext);

  1027 		e1e_flush();

  1028 	}

  1029 

  1030 	ret_val = e1000e_get_auto_rd_done(hw);

  1031 	if (ret_val)

  1032 		/* We don't want to continue accessing MAC registers. */

  1033 		return ret_val;

  1034 

  1035 	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.

  1036 	 * Need to wait for Phy configuration completion before accessing

  1037 	 * NVM and Phy.

  1038 	 */

  1039 

  1040 	switch (hw->mac.type) {

  1041 	case e1000_82571:

  1042 	case e1000_82572:

  1043 		/* REQ and GNT bits need to be cleared when using AUTO_RD

  1044 		 * to access the EEPROM.

  1045 		 */

  1046 		eecd = er32(EECD);

  1047 		eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);

  1048 		ew32(EECD, eecd);

  1049 		break;

  1050 	case e1000_82573:

  1051 	case e1000_82574:

  1052 	case e1000_82583:

  1053 		msleep(25);

  1054 		break;

  1055 	default:

  1056 		break;

  1057 	}

  1058 

  1059 	/* Clear any pending interrupt events. */

  1060 	ew32(IMC, 0xffffffff);

  1061 	er32(ICR);

  1062 

  1063 	if (hw->mac.type == e1000_82571) {

  1064 		/* Install any alternate MAC address into RAR0 */

  1065 		ret_val = e1000_check_alt_mac_addr_generic(hw);

  1066 		if (ret_val)

  1067 			return ret_val;

  1068 

  1069 		e1000e_set_laa_state_82571(hw, true);

  1070 	}

  1071 

  1072 	/* Reinitialize the 82571 serdes link state machine */

  1073 	if (hw->phy.media_type == e1000_media_type_internal_serdes)

  1074 		hw->mac.serdes_link_state = e1000_serdes_link_down;

  1075 

  1076 	return 0;

  1077 }

  1078 

  1079 /**

  1080  *  e1000_init_hw_82571 - Initialize hardware

  1081  *  @hw: pointer to the HW structure

  1082  *

  1083  *  This inits the hardware readying it for operation.

  1084  **/

  1085 static s32 e1000_init_hw_82571(struct e1000_hw *hw)

  1086 {

  1087 	struct e1000_mac_info *mac = &hw->mac;

  1088 	u32 reg_data;

  1089 	s32 ret_val;

  1090 	u16 i, rar_count = mac->rar_entry_count;

  1091 

  1092 	e1000_initialize_hw_bits_82571(hw);

  1093 

  1094 	/* Initialize identification LED */

  1095 	ret_val = mac->ops.id_led_init(hw);

  1096 	/* An error is not fatal and we should not stop init due to this */

  1097 	if (ret_val)

  1098 		e_dbg("Error initializing identification LED\n");

  1099 

  1100 	/* Disabling VLAN filtering */

  1101 	e_dbg("Initializing the IEEE VLAN\n");

  1102 	mac->ops.clear_vfta(hw);

  1103 

  1104 	/* Setup the receive address.

  1105 	 * If, however, a locally administered address was assigned to the

  1106 	 * 82571, we must reserve a RAR for it to work around an issue where

  1107 	 * resetting one port will reload the MAC on the other port.

  1108 	 */

  1109 	if (e1000e_get_laa_state_82571(hw))

  1110 		rar_count--;

  1111 	e1000e_init_rx_addrs(hw, rar_count);

  1112 

  1113 	/* Zero out the Multicast HASH table */

  1114 	e_dbg("Zeroing the MTA\n");

  1115 	for (i = 0; i < mac->mta_reg_count; i++)

  1116 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

  1117 

  1118 	/* Setup link and flow control */

  1119 	ret_val = mac->ops.setup_link(hw);

  1120 

  1121 	/* Set the transmit descriptor write-back policy */

  1122 	reg_data = er32(TXDCTL(0));

  1123 	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

  1124 		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);

  1125 	ew32(TXDCTL(0), reg_data);

  1126 

  1127 	/* ...for both queues. */

  1128 	switch (mac->type) {

  1129 	case e1000_82573:

  1130 		e1000e_enable_tx_pkt_filtering(hw);

  1131 		/* fall through */

  1132 	case e1000_82574:

  1133 	case e1000_82583:

  1134 		reg_data = er32(GCR);

  1135 		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

  1136 		ew32(GCR, reg_data);