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1 /* Intel PRO/1000 Linux driver |
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2 * Copyright(c) 1999 - 2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * The full GNU General Public License is included in this distribution in |
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14 * the file called "COPYING". |
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15 * |
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16 * Contact Information: |
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17 * Linux NICS <linux.nics@intel.com> |
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18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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20 */ |
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21 |
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22 #ifndef _E1000E_80003ES2LAN_H_ |
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23 #define _E1000E_80003ES2LAN_H_ |
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24 |
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25 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 |
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26 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 |
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27 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 |
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28 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
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29 |
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30 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 |
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31 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 |
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32 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 |
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33 |
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34 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 |
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35 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 |
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36 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
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37 |
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38 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C |
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39 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 |
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40 |
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41 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ |
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42 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 |
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43 |
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44 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 |
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45 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 |
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46 |
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47 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ |
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48 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ |
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49 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 |
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50 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ |
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51 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ |
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52 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ |
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53 |
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54 /* PHY Specific Control Register 2 (Page 0, Register 26) */ |
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55 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ |
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56 |
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57 /* MAC Specific Control Register (Page 2, Register 21) */ |
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58 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ |
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59 #define GG82563_MSCR_TX_CLK_MASK 0x0007 |
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60 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 |
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61 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 |
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62 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 |
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63 |
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64 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ |
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65 |
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66 /* DSP Distance Register (Page 5, Register 26) |
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67 * 0 = <50M |
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68 * 1 = 50-80M |
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69 * 2 = 80-100M |
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70 * 3 = 110-140M |
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71 * 4 = >140M |
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72 */ |
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73 #define GG82563_DSPD_CABLE_LENGTH 0x0007 |
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74 |
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75 /* Kumeran Mode Control Register (Page 193, Register 16) */ |
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76 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 |
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77 |
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78 /* Max number of times Kumeran read/write should be validated */ |
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79 #define GG82563_MAX_KMRN_RETRY 0x5 |
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80 |
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81 /* Power Management Control Register (Page 193, Register 20) */ |
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82 /* 1=Enable SERDES Electrical Idle */ |
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83 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 |
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84 |
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85 /* In-Band Control Register (Page 194, Register 18) */ |
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86 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ |
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87 |
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88 #endif |