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1 /* Intel PRO/1000 Linux driver |
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2 * Copyright(c) 1999 - 2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * The full GNU General Public License is included in this distribution in |
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14 * the file called "COPYING". |
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15 * |
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16 * Contact Information: |
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17 * Linux NICS <linux.nics@intel.com> |
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18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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20 */ |
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21 |
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22 /* 80003ES2LAN Gigabit Ethernet Controller (Copper) |
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23 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) |
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24 */ |
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25 |
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26 #include "e1000.h" |
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27 |
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28 /* A table for the GG82563 cable length where the range is defined |
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29 * with a lower bound at "index" and the upper bound at |
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30 * "index + 5". |
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31 */ |
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32 static const u16 e1000_gg82563_cable_length_table[] = { |
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33 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF |
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34 }; |
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35 |
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36 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ |
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37 ARRAY_SIZE(e1000_gg82563_cable_length_table) |
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38 |
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39 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); |
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40 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); |
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41 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); |
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42 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); |
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43 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); |
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44 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); |
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45 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); |
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46 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
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47 u16 *data); |
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48 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
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49 u16 data); |
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50 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); |
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51 |
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52 /** |
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53 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. |
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54 * @hw: pointer to the HW structure |
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55 **/ |
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56 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) |
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57 { |
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58 struct e1000_phy_info *phy = &hw->phy; |
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59 s32 ret_val; |
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60 |
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61 if (hw->phy.media_type != e1000_media_type_copper) { |
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62 phy->type = e1000_phy_none; |
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63 return 0; |
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64 } else { |
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65 phy->ops.power_up = e1000_power_up_phy_copper; |
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66 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; |
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67 } |
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68 |
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69 phy->addr = 1; |
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70 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
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71 phy->reset_delay_us = 100; |
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72 phy->type = e1000_phy_gg82563; |
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73 |
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74 /* This can only be done after all function pointers are setup. */ |
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75 ret_val = e1000e_get_phy_id(hw); |
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76 |
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77 /* Verify phy id */ |
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78 if (phy->id != GG82563_E_PHY_ID) |
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79 return -E1000_ERR_PHY; |
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80 |
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81 return ret_val; |
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82 } |
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83 |
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84 /** |
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85 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. |
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86 * @hw: pointer to the HW structure |
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87 **/ |
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88 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) |
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89 { |
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90 struct e1000_nvm_info *nvm = &hw->nvm; |
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91 u32 eecd = er32(EECD); |
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92 u16 size; |
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93 |
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94 nvm->opcode_bits = 8; |
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95 nvm->delay_usec = 1; |
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96 switch (nvm->override) { |
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97 case e1000_nvm_override_spi_large: |
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98 nvm->page_size = 32; |
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99 nvm->address_bits = 16; |
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100 break; |
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101 case e1000_nvm_override_spi_small: |
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102 nvm->page_size = 8; |
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103 nvm->address_bits = 8; |
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104 break; |
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105 default: |
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106 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; |
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107 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; |
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108 break; |
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109 } |
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110 |
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111 nvm->type = e1000_nvm_eeprom_spi; |
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112 |
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113 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
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114 E1000_EECD_SIZE_EX_SHIFT); |
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115 |
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116 /* Added to a constant, "size" becomes the left-shift value |
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117 * for setting word_size. |
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118 */ |
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119 size += NVM_WORD_SIZE_BASE_SHIFT; |
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120 |
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121 /* EEPROM access above 16k is unsupported */ |
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122 if (size > 14) |
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123 size = 14; |
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124 nvm->word_size = 1 << size; |
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125 |
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126 return 0; |
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127 } |
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128 |
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129 /** |
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130 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. |
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131 * @hw: pointer to the HW structure |
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132 **/ |
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133 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) |
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134 { |
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135 struct e1000_mac_info *mac = &hw->mac; |
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136 |
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137 /* Set media type and media-dependent function pointers */ |
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138 switch (hw->adapter->pdev->device) { |
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139 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
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140 hw->phy.media_type = e1000_media_type_internal_serdes; |
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141 mac->ops.check_for_link = e1000e_check_for_serdes_link; |
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142 mac->ops.setup_physical_interface = |
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143 e1000e_setup_fiber_serdes_link; |
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144 break; |
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145 default: |
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146 hw->phy.media_type = e1000_media_type_copper; |
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147 mac->ops.check_for_link = e1000e_check_for_copper_link; |
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148 mac->ops.setup_physical_interface = |
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149 e1000_setup_copper_link_80003es2lan; |
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150 break; |
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151 } |
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152 |
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153 /* Set mta register count */ |
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154 mac->mta_reg_count = 128; |
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155 /* Set rar entry count */ |
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156 mac->rar_entry_count = E1000_RAR_ENTRIES; |
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157 /* FWSM register */ |
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158 mac->has_fwsm = true; |
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159 /* ARC supported; valid only if manageability features are enabled. */ |
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160 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK); |
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161 /* Adaptive IFS not supported */ |
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162 mac->adaptive_ifs = false; |
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163 |
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164 /* set lan id for port to determine which phy lock to use */ |
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165 hw->mac.ops.set_lan_id(hw); |
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166 |
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167 return 0; |
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168 } |
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169 |
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170 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
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171 { |
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172 struct e1000_hw *hw = &adapter->hw; |
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173 s32 rc; |
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174 |
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175 rc = e1000_init_mac_params_80003es2lan(hw); |
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176 if (rc) |
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177 return rc; |
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178 |
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179 rc = e1000_init_nvm_params_80003es2lan(hw); |
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180 if (rc) |
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181 return rc; |
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182 |
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183 rc = e1000_init_phy_params_80003es2lan(hw); |
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184 if (rc) |
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185 return rc; |
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186 |
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187 return 0; |
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188 } |
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189 |
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190 /** |
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191 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY |
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192 * @hw: pointer to the HW structure |
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193 * |
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194 * A wrapper to acquire access rights to the correct PHY. |
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195 **/ |
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196 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) |
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197 { |
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198 u16 mask; |
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199 |
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200 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
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201 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
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202 } |
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203 |
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204 /** |
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205 * e1000_release_phy_80003es2lan - Release rights to access PHY |
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206 * @hw: pointer to the HW structure |
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207 * |
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208 * A wrapper to release access rights to the correct PHY. |
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209 **/ |
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210 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) |
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211 { |
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212 u16 mask; |
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213 |
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214 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
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215 e1000_release_swfw_sync_80003es2lan(hw, mask); |
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216 } |
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217 |
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218 /** |
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219 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register |
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220 * @hw: pointer to the HW structure |
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221 * |
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222 * Acquire the semaphore to access the Kumeran interface. |
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223 * |
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224 **/ |
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225 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) |
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226 { |
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227 u16 mask; |
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228 |
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229 mask = E1000_SWFW_CSR_SM; |
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230 |
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231 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
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232 } |
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233 |
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234 /** |
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235 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register |
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236 * @hw: pointer to the HW structure |
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237 * |
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238 * Release the semaphore used to access the Kumeran interface |
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239 **/ |
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240 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) |
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241 { |
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242 u16 mask; |
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243 |
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244 mask = E1000_SWFW_CSR_SM; |
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245 |
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246 e1000_release_swfw_sync_80003es2lan(hw, mask); |
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247 } |
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248 |
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249 /** |
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250 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM |
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251 * @hw: pointer to the HW structure |
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252 * |
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253 * Acquire the semaphore to access the EEPROM. |
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254 **/ |
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255 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) |
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256 { |
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257 s32 ret_val; |
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258 |
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259 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); |
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260 if (ret_val) |
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261 return ret_val; |
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262 |
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263 ret_val = e1000e_acquire_nvm(hw); |
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264 |
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265 if (ret_val) |
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266 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); |
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267 |
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268 return ret_val; |
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269 } |
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270 |
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271 /** |
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272 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM |
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273 * @hw: pointer to the HW structure |
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274 * |
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275 * Release the semaphore used to access the EEPROM. |
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276 **/ |
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277 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) |
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278 { |
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279 e1000e_release_nvm(hw); |
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280 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); |
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281 } |
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282 |
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283 /** |
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284 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore |
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285 * @hw: pointer to the HW structure |
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286 * @mask: specifies which semaphore to acquire |
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287 * |
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288 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask |
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289 * will also specify which port we're acquiring the lock for. |
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290 **/ |
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291 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) |
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292 { |
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293 u32 swfw_sync; |
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294 u32 swmask = mask; |
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295 u32 fwmask = mask << 16; |
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296 s32 i = 0; |
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297 s32 timeout = 50; |
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298 |
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299 while (i < timeout) { |
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300 if (e1000e_get_hw_semaphore(hw)) |
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301 return -E1000_ERR_SWFW_SYNC; |
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302 |
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303 swfw_sync = er32(SW_FW_SYNC); |
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304 if (!(swfw_sync & (fwmask | swmask))) |
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305 break; |
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306 |
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307 /* Firmware currently using resource (fwmask) |
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308 * or other software thread using resource (swmask) |
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309 */ |
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310 e1000e_put_hw_semaphore(hw); |
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311 mdelay(5); |
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312 i++; |
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313 } |
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314 |
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315 if (i == timeout) { |
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316 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
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317 return -E1000_ERR_SWFW_SYNC; |
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318 } |
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319 |
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320 swfw_sync |= swmask; |
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321 ew32(SW_FW_SYNC, swfw_sync); |
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322 |
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323 e1000e_put_hw_semaphore(hw); |
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324 |
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325 return 0; |
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326 } |
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327 |
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328 /** |
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329 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore |
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330 * @hw: pointer to the HW structure |
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331 * @mask: specifies which semaphore to acquire |
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332 * |
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333 * Release the SW/FW semaphore used to access the PHY or NVM. The mask |
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334 * will also specify which port we're releasing the lock for. |
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335 **/ |
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336 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) |
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337 { |
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338 u32 swfw_sync; |
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339 |
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340 while (e1000e_get_hw_semaphore(hw) != 0) |
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341 ; /* Empty */ |
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342 |
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343 swfw_sync = er32(SW_FW_SYNC); |
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344 swfw_sync &= ~mask; |
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345 ew32(SW_FW_SYNC, swfw_sync); |
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346 |
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347 e1000e_put_hw_semaphore(hw); |
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348 } |
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349 |
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350 /** |
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351 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register |
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352 * @hw: pointer to the HW structure |
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353 * @offset: offset of the register to read |
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354 * @data: pointer to the data returned from the operation |
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355 * |
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356 * Read the GG82563 PHY register. |
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357 **/ |
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358 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, |
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359 u32 offset, u16 *data) |
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360 { |
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361 s32 ret_val; |
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362 u32 page_select; |
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363 u16 temp; |
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364 |
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365 ret_val = e1000_acquire_phy_80003es2lan(hw); |
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366 if (ret_val) |
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367 return ret_val; |
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368 |
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369 /* Select Configuration Page */ |
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370 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
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371 page_select = GG82563_PHY_PAGE_SELECT; |
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372 } else { |
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373 /* Use Alternative Page Select register to access |
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374 * registers 30 and 31 |
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375 */ |
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376 page_select = GG82563_PHY_PAGE_SELECT_ALT; |
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377 } |
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378 |
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379 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); |
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380 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
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381 if (ret_val) { |
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382 e1000_release_phy_80003es2lan(hw); |
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383 return ret_val; |
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384 } |
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385 |
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386 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { |
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387 /* The "ready" bit in the MDIC register may be incorrectly set |
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388 * before the device has completed the "Page Select" MDI |
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389 * transaction. So we wait 200us after each MDI command... |
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390 */ |
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391 usleep_range(200, 400); |
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392 |
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393 /* ...and verify the command was successful. */ |
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394 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
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395 |
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396 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
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397 e1000_release_phy_80003es2lan(hw); |
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398 return -E1000_ERR_PHY; |
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399 } |
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400 |
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401 usleep_range(200, 400); |
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402 |
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403 ret_val = e1000e_read_phy_reg_mdic(hw, |
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404 MAX_PHY_REG_ADDRESS & offset, |
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405 data); |
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406 |
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407 usleep_range(200, 400); |
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408 } else { |
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409 ret_val = e1000e_read_phy_reg_mdic(hw, |
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410 MAX_PHY_REG_ADDRESS & offset, |
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411 data); |
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412 } |
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413 |
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414 e1000_release_phy_80003es2lan(hw); |
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415 |
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416 return ret_val; |
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417 } |
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418 |
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419 /** |
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420 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register |
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421 * @hw: pointer to the HW structure |
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422 * @offset: offset of the register to read |
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423 * @data: value to write to the register |
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424 * |
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425 * Write to the GG82563 PHY register. |
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426 **/ |
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427 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, |
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428 u32 offset, u16 data) |
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429 { |
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430 s32 ret_val; |
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431 u32 page_select; |
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432 u16 temp; |
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433 |
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434 ret_val = e1000_acquire_phy_80003es2lan(hw); |
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435 if (ret_val) |
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436 return ret_val; |
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437 |
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438 /* Select Configuration Page */ |
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439 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
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440 page_select = GG82563_PHY_PAGE_SELECT; |
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441 } else { |
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442 /* Use Alternative Page Select register to access |
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443 * registers 30 and 31 |
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444 */ |
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445 page_select = GG82563_PHY_PAGE_SELECT_ALT; |
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446 } |
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447 |
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448 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); |
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449 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
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450 if (ret_val) { |
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451 e1000_release_phy_80003es2lan(hw); |
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452 return ret_val; |
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453 } |
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454 |
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455 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { |
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456 /* The "ready" bit in the MDIC register may be incorrectly set |
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457 * before the device has completed the "Page Select" MDI |
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458 * transaction. So we wait 200us after each MDI command... |
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459 */ |
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460 usleep_range(200, 400); |
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461 |
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462 /* ...and verify the command was successful. */ |
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463 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
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464 |
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465 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
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466 e1000_release_phy_80003es2lan(hw); |
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467 return -E1000_ERR_PHY; |
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468 } |
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469 |
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470 usleep_range(200, 400); |
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471 |
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472 ret_val = e1000e_write_phy_reg_mdic(hw, |
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473 MAX_PHY_REG_ADDRESS & |
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474 offset, data); |
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475 |
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476 usleep_range(200, 400); |
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477 } else { |
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478 ret_val = e1000e_write_phy_reg_mdic(hw, |
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479 MAX_PHY_REG_ADDRESS & |
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480 offset, data); |
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481 } |
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482 |
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483 e1000_release_phy_80003es2lan(hw); |
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484 |
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485 return ret_val; |
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486 } |
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487 |
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488 /** |
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489 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM |
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490 * @hw: pointer to the HW structure |
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491 * @offset: offset of the register to read |
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492 * @words: number of words to write |
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493 * @data: buffer of data to write to the NVM |
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494 * |
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495 * Write "words" of data to the ESB2 NVM. |
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496 **/ |
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497 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, |
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498 u16 words, u16 *data) |
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499 { |
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500 return e1000e_write_nvm_spi(hw, offset, words, data); |
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501 } |
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502 |
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503 /** |
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504 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete |
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505 * @hw: pointer to the HW structure |
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506 * |
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507 * Wait a specific amount of time for manageability processes to complete. |
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508 * This is a function pointer entry point called by the phy module. |
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509 **/ |
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510 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) |
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511 { |
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512 s32 timeout = PHY_CFG_TIMEOUT; |
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513 u32 mask = E1000_NVM_CFG_DONE_PORT_0; |
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514 |
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515 if (hw->bus.func == 1) |
|
516 mask = E1000_NVM_CFG_DONE_PORT_1; |
|
517 |
|
518 while (timeout) { |
|
519 if (er32(EEMNGCTL) & mask) |
|
520 break; |
|
521 usleep_range(1000, 2000); |
|
522 timeout--; |
|
523 } |
|
524 if (!timeout) { |
|
525 e_dbg("MNG configuration cycle has not completed.\n"); |
|
526 return -E1000_ERR_RESET; |
|
527 } |
|
528 |
|
529 return 0; |
|
530 } |
|
531 |
|
532 /** |
|
533 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex |
|
534 * @hw: pointer to the HW structure |
|
535 * |
|
536 * Force the speed and duplex settings onto the PHY. This is a |
|
537 * function pointer entry point called by the phy module. |
|
538 **/ |
|
539 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) |
|
540 { |
|
541 s32 ret_val; |
|
542 u16 phy_data; |
|
543 bool link; |
|
544 |
|
545 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
546 * forced whenever speed and duplex are forced. |
|
547 */ |
|
548 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
549 if (ret_val) |
|
550 return ret_val; |
|
551 |
|
552 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; |
|
553 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); |
|
554 if (ret_val) |
|
555 return ret_val; |
|
556 |
|
557 e_dbg("GG82563 PSCR: %X\n", phy_data); |
|
558 |
|
559 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
|
560 if (ret_val) |
|
561 return ret_val; |
|
562 |
|
563 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
564 |
|
565 /* Reset the phy to commit changes. */ |
|
566 phy_data |= BMCR_RESET; |
|
567 |
|
568 ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
|
569 if (ret_val) |
|
570 return ret_val; |
|
571 |
|
572 udelay(1); |
|
573 |
|
574 if (hw->phy.autoneg_wait_to_complete) { |
|
575 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n"); |
|
576 |
|
577 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
578 100000, &link); |
|
579 if (ret_val) |
|
580 return ret_val; |
|
581 |
|
582 if (!link) { |
|
583 /* We didn't get link. |
|
584 * Reset the DSP and cross our fingers. |
|
585 */ |
|
586 ret_val = e1000e_phy_reset_dsp(hw); |
|
587 if (ret_val) |
|
588 return ret_val; |
|
589 } |
|
590 |
|
591 /* Try once more */ |
|
592 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
593 100000, &link); |
|
594 if (ret_val) |
|
595 return ret_val; |
|
596 } |
|
597 |
|
598 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); |
|
599 if (ret_val) |
|
600 return ret_val; |
|
601 |
|
602 /* Resetting the phy means we need to verify the TX_CLK corresponds |
|
603 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
|
604 */ |
|
605 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; |
|
606 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) |
|
607 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; |
|
608 else |
|
609 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; |
|
610 |
|
611 /* In addition, we must re-enable CRS on Tx for both half and full |
|
612 * duplex. |
|
613 */ |
|
614 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
615 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); |
|
616 |
|
617 return ret_val; |
|
618 } |
|
619 |
|
620 /** |
|
621 * e1000_get_cable_length_80003es2lan - Set approximate cable length |
|
622 * @hw: pointer to the HW structure |
|
623 * |
|
624 * Find the approximate cable length as measured by the GG82563 PHY. |
|
625 * This is a function pointer entry point called by the phy module. |
|
626 **/ |
|
627 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) |
|
628 { |
|
629 struct e1000_phy_info *phy = &hw->phy; |
|
630 s32 ret_val; |
|
631 u16 phy_data, index; |
|
632 |
|
633 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); |
|
634 if (ret_val) |
|
635 return ret_val; |
|
636 |
|
637 index = phy_data & GG82563_DSPD_CABLE_LENGTH; |
|
638 |
|
639 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) |
|
640 return -E1000_ERR_PHY; |
|
641 |
|
642 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; |
|
643 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; |
|
644 |
|
645 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
646 |
|
647 return 0; |
|
648 } |
|
649 |
|
650 /** |
|
651 * e1000_get_link_up_info_80003es2lan - Report speed and duplex |
|
652 * @hw: pointer to the HW structure |
|
653 * @speed: pointer to speed buffer |
|
654 * @duplex: pointer to duplex buffer |
|
655 * |
|
656 * Retrieve the current speed and duplex configuration. |
|
657 **/ |
|
658 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, |
|
659 u16 *duplex) |
|
660 { |
|
661 s32 ret_val; |
|
662 |
|
663 if (hw->phy.media_type == e1000_media_type_copper) { |
|
664 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); |
|
665 hw->phy.ops.cfg_on_link_up(hw); |
|
666 } else { |
|
667 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, |
|
668 speed, |
|
669 duplex); |
|
670 } |
|
671 |
|
672 return ret_val; |
|
673 } |
|
674 |
|
675 /** |
|
676 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller |
|
677 * @hw: pointer to the HW structure |
|
678 * |
|
679 * Perform a global reset to the ESB2 controller. |
|
680 **/ |
|
681 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) |
|
682 { |
|
683 u32 ctrl; |
|
684 s32 ret_val; |
|
685 u16 kum_reg_data; |
|
686 |
|
687 /* Prevent the PCI-E bus from sticking if there is no TLP connection |
|
688 * on the last TLP read/write transaction when MAC is reset. |
|
689 */ |
|
690 ret_val = e1000e_disable_pcie_master(hw); |
|
691 if (ret_val) |
|
692 e_dbg("PCI-E Master disable polling has failed.\n"); |
|
693 |
|
694 e_dbg("Masking off all interrupts\n"); |
|
695 ew32(IMC, 0xffffffff); |
|
696 |
|
697 ew32(RCTL, 0); |
|
698 ew32(TCTL, E1000_TCTL_PSP); |
|
699 e1e_flush(); |
|
700 |
|
701 usleep_range(10000, 20000); |
|
702 |
|
703 ctrl = er32(CTRL); |
|
704 |
|
705 ret_val = e1000_acquire_phy_80003es2lan(hw); |
|
706 if (ret_val) |
|
707 return ret_val; |
|
708 |
|
709 e_dbg("Issuing a global reset to MAC\n"); |
|
710 ew32(CTRL, ctrl | E1000_CTRL_RST); |
|
711 e1000_release_phy_80003es2lan(hw); |
|
712 |
|
713 /* Disable IBIST slave mode (far-end loopback) */ |
|
714 ret_val = |
|
715 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
716 &kum_reg_data); |
|
717 if (ret_val) |
|
718 return ret_val; |
|
719 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; |
|
720 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
721 kum_reg_data); |
|
722 |
|
723 ret_val = e1000e_get_auto_rd_done(hw); |
|
724 if (ret_val) |
|
725 /* We don't want to continue accessing MAC registers. */ |
|
726 return ret_val; |
|
727 |
|
728 /* Clear any pending interrupt events. */ |
|
729 ew32(IMC, 0xffffffff); |
|
730 er32(ICR); |
|
731 |
|
732 return e1000_check_alt_mac_addr_generic(hw); |
|
733 } |
|
734 |
|
735 /** |
|
736 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller |
|
737 * @hw: pointer to the HW structure |
|
738 * |
|
739 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. |
|
740 **/ |
|
741 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) |
|
742 { |
|
743 struct e1000_mac_info *mac = &hw->mac; |
|
744 u32 reg_data; |
|
745 s32 ret_val; |
|
746 u16 kum_reg_data; |
|
747 u16 i; |
|
748 |
|
749 e1000_initialize_hw_bits_80003es2lan(hw); |
|
750 |
|
751 /* Initialize identification LED */ |
|
752 ret_val = mac->ops.id_led_init(hw); |
|
753 /* An error is not fatal and we should not stop init due to this */ |
|
754 if (ret_val) |
|
755 e_dbg("Error initializing identification LED\n"); |
|
756 |
|
757 /* Disabling VLAN filtering */ |
|
758 e_dbg("Initializing the IEEE VLAN\n"); |
|
759 mac->ops.clear_vfta(hw); |
|
760 |
|
761 /* Setup the receive address. */ |
|
762 e1000e_init_rx_addrs(hw, mac->rar_entry_count); |
|
763 |
|
764 /* Zero out the Multicast HASH table */ |
|
765 e_dbg("Zeroing the MTA\n"); |
|
766 for (i = 0; i < mac->mta_reg_count; i++) |
|
767 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
|
768 |
|
769 /* Setup link and flow control */ |
|
770 ret_val = mac->ops.setup_link(hw); |
|
771 if (ret_val) |
|
772 return ret_val; |
|
773 |
|
774 /* Disable IBIST slave mode (far-end loopback) */ |
|
775 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
776 &kum_reg_data); |
|
777 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; |
|
778 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
|
779 kum_reg_data); |
|
780 |
|
781 /* Set the transmit descriptor write-back policy */ |
|
782 reg_data = er32(TXDCTL(0)); |
|
783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
784 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); |
|
785 ew32(TXDCTL(0), reg_data); |
|
786 |
|
787 /* ...for both queues. */ |
|
788 reg_data = er32(TXDCTL(1)); |
|
789 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
790 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); |
|
791 ew32(TXDCTL(1), reg_data); |
|
792 |
|
793 /* Enable retransmit on late collisions */ |
|
794 reg_data = er32(TCTL); |
|
795 reg_data |= E1000_TCTL_RTLC; |
|
796 ew32(TCTL, reg_data); |
|
797 |
|
798 /* Configure Gigabit Carry Extend Padding */ |
|
799 reg_data = er32(TCTL_EXT); |
|
800 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
|
801 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; |
|
802 ew32(TCTL_EXT, reg_data); |
|
803 |
|
804 /* Configure Transmit Inter-Packet Gap */ |
|
805 reg_data = er32(TIPG); |
|
806 reg_data &= ~E1000_TIPG_IPGT_MASK; |
|
807 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; |
|
808 ew32(TIPG, reg_data); |
|
809 |
|
810 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); |
|
811 reg_data &= ~0x00100000; |
|
812 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); |
|
813 |
|
814 /* default to true to enable the MDIC W/A */ |
|
815 hw->dev_spec.e80003es2lan.mdic_wa_enable = true; |
|
816 |
|
817 ret_val = |
|
818 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> |
|
819 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); |
|
820 if (!ret_val) { |
|
821 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == |
|
822 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) |
|
823 hw->dev_spec.e80003es2lan.mdic_wa_enable = false; |
|
824 } |
|
825 |
|
826 /* Clear all of the statistics registers (clear on read). It is |
|
827 * important that we do this after we have tried to establish link |
|
828 * because the symbol error count will increment wildly if there |
|
829 * is no link. |
|
830 */ |
|
831 e1000_clear_hw_cntrs_80003es2lan(hw); |
|
832 |
|
833 return ret_val; |
|
834 } |
|
835 |
|
836 /** |
|
837 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 |
|
838 * @hw: pointer to the HW structure |
|
839 * |
|
840 * Initializes required hardware-dependent bits needed for normal operation. |
|
841 **/ |
|
842 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) |
|
843 { |
|
844 u32 reg; |
|
845 |
|
846 /* Transmit Descriptor Control 0 */ |
|
847 reg = er32(TXDCTL(0)); |
|
848 reg |= (1 << 22); |
|
849 ew32(TXDCTL(0), reg); |
|
850 |
|
851 /* Transmit Descriptor Control 1 */ |
|
852 reg = er32(TXDCTL(1)); |
|
853 reg |= (1 << 22); |
|
854 ew32(TXDCTL(1), reg); |
|
855 |
|
856 /* Transmit Arbitration Control 0 */ |
|
857 reg = er32(TARC(0)); |
|
858 reg &= ~(0xF << 27); /* 30:27 */ |
|
859 if (hw->phy.media_type != e1000_media_type_copper) |
|
860 reg &= ~(1 << 20); |
|
861 ew32(TARC(0), reg); |
|
862 |
|
863 /* Transmit Arbitration Control 1 */ |
|
864 reg = er32(TARC(1)); |
|
865 if (er32(TCTL) & E1000_TCTL_MULR) |
|
866 reg &= ~(1 << 28); |
|
867 else |
|
868 reg |= (1 << 28); |
|
869 ew32(TARC(1), reg); |
|
870 |
|
871 /* Disable IPv6 extension header parsing because some malformed |
|
872 * IPv6 headers can hang the Rx. |
|
873 */ |
|
874 reg = er32(RFCTL); |
|
875 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); |
|
876 ew32(RFCTL, reg); |
|
877 } |
|
878 |
|
879 /** |
|
880 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link |
|
881 * @hw: pointer to the HW structure |
|
882 * |
|
883 * Setup some GG82563 PHY registers for obtaining link |
|
884 **/ |
|
885 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) |
|
886 { |
|
887 struct e1000_phy_info *phy = &hw->phy; |
|
888 s32 ret_val; |
|
889 u32 reg; |
|
890 u16 data; |
|
891 |
|
892 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
|
893 if (ret_val) |
|
894 return ret_val; |
|
895 |
|
896 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
|
897 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ |
|
898 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; |
|
899 |
|
900 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
|
901 if (ret_val) |
|
902 return ret_val; |
|
903 |
|
904 /* Options: |
|
905 * MDI/MDI-X = 0 (default) |
|
906 * 0 - Auto for all speeds |
|
907 * 1 - MDI mode |
|
908 * 2 - MDI-X mode |
|
909 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
910 */ |
|
911 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); |
|
912 if (ret_val) |
|
913 return ret_val; |
|
914 |
|
915 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; |
|
916 |
|
917 switch (phy->mdix) { |
|
918 case 1: |
|
919 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; |
|
920 break; |
|
921 case 2: |
|
922 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; |
|
923 break; |
|
924 case 0: |
|
925 default: |
|
926 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; |
|
927 break; |
|
928 } |
|
929 |
|
930 /* Options: |
|
931 * disable_polarity_correction = 0 (default) |
|
932 * Automatic Correction for Reversed Cable Polarity |
|
933 * 0 - Disabled |
|
934 * 1 - Enabled |
|
935 */ |
|
936 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
937 if (phy->disable_polarity_correction) |
|
938 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
|
939 |
|
940 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); |
|
941 if (ret_val) |
|
942 return ret_val; |
|
943 |
|
944 /* SW Reset the PHY so all changes take effect */ |
|
945 ret_val = hw->phy.ops.commit(hw); |
|
946 if (ret_val) { |
|
947 e_dbg("Error Resetting the PHY\n"); |
|
948 return ret_val; |
|
949 } |
|
950 |
|
951 /* Bypass Rx and Tx FIFO's */ |
|
952 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; |
|
953 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
|
954 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
|
955 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); |
|
956 if (ret_val) |
|
957 return ret_val; |
|
958 |
|
959 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; |
|
960 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); |
|
961 if (ret_val) |
|
962 return ret_val; |
|
963 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; |
|
964 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); |
|
965 if (ret_val) |
|
966 return ret_val; |
|
967 |
|
968 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
|
969 if (ret_val) |
|
970 return ret_val; |
|
971 |
|
972 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; |
|
973 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); |
|
974 if (ret_val) |
|
975 return ret_val; |
|
976 |
|
977 reg = er32(CTRL_EXT); |
|
978 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; |
|
979 ew32(CTRL_EXT, reg); |
|
980 |
|
981 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); |
|
982 if (ret_val) |
|
983 return ret_val; |
|
984 |
|
985 /* Do not init these registers when the HW is in IAMT mode, since the |
|
986 * firmware will have already initialized them. We only initialize |
|
987 * them if the HW is not in IAMT mode. |
|
988 */ |
|
989 if (!hw->mac.ops.check_mng_mode(hw)) { |
|
990 /* Enable Electrical Idle on the PHY */ |
|
991 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; |
|
992 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); |
|
993 if (ret_val) |
|
994 return ret_val; |
|
995 |
|
996 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
|
997 if (ret_val) |
|
998 return ret_val; |
|
999 |
|
1000 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1001 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); |
|
1002 if (ret_val) |
|
1003 return ret_val; |
|
1004 } |
|
1005 |
|
1006 /* Workaround: Disable padding in Kumeran interface in the MAC |
|
1007 * and in the PHY to avoid CRC errors. |
|
1008 */ |
|
1009 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); |
|
1010 if (ret_val) |
|
1011 return ret_val; |
|
1012 |
|
1013 data |= GG82563_ICR_DIS_PADDING; |
|
1014 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); |
|
1015 if (ret_val) |
|
1016 return ret_val; |
|
1017 |
|
1018 return 0; |
|
1019 } |
|
1020 |
|
1021 /** |
|
1022 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 |
|
1023 * @hw: pointer to the HW structure |
|
1024 * |
|
1025 * Essentially a wrapper for setting up all things "copper" related. |
|
1026 * This is a function pointer entry point called by the mac module. |
|
1027 **/ |
|
1028 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) |
|
1029 { |
|
1030 u32 ctrl; |
|
1031 s32 ret_val; |
|
1032 u16 reg_data; |
|
1033 |
|
1034 ctrl = er32(CTRL); |
|
1035 ctrl |= E1000_CTRL_SLU; |
|
1036 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1037 ew32(CTRL, ctrl); |
|
1038 |
|
1039 /* Set the mac to wait the maximum time between each |
|
1040 * iteration and increase the max iterations when |
|
1041 * polling the phy; this fixes erroneous timeouts at 10Mbps. |
|
1042 */ |
|
1043 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
|
1044 0xFFFF); |
|
1045 if (ret_val) |
|
1046 return ret_val; |
|
1047 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
|
1048 ®_data); |
|
1049 if (ret_val) |
|
1050 return ret_val; |
|
1051 reg_data |= 0x3F; |
|
1052 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
|
1053 reg_data); |
|
1054 if (ret_val) |
|
1055 return ret_val; |
|
1056 ret_val = |
|
1057 e1000_read_kmrn_reg_80003es2lan(hw, |
|
1058 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
|
1059 ®_data); |
|
1060 if (ret_val) |
|
1061 return ret_val; |
|
1062 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; |
|
1063 ret_val = |
|
1064 e1000_write_kmrn_reg_80003es2lan(hw, |
|
1065 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
|
1066 reg_data); |
|
1067 if (ret_val) |
|
1068 return ret_val; |
|
1069 |
|
1070 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); |
|
1071 if (ret_val) |
|
1072 return ret_val; |
|
1073 |
|
1074 return e1000e_setup_copper_link(hw); |
|
1075 } |
|
1076 |
|
1077 /** |
|
1078 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up |
|
1079 * @hw: pointer to the HW structure |
|
1080 * @duplex: current duplex setting |
|
1081 * |
|
1082 * Configure the KMRN interface by applying last minute quirks for |
|
1083 * 10/100 operation. |
|
1084 **/ |
|
1085 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) |
|
1086 { |
|
1087 s32 ret_val = 0; |
|
1088 u16 speed; |
|
1089 u16 duplex; |
|
1090 |
|
1091 if (hw->phy.media_type == e1000_media_type_copper) { |
|
1092 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, |
|
1093 &duplex); |
|
1094 if (ret_val) |
|
1095 return ret_val; |
|
1096 |
|
1097 if (speed == SPEED_1000) |
|
1098 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); |
|
1099 else |
|
1100 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); |
|
1101 } |
|
1102 |
|
1103 return ret_val; |
|
1104 } |
|
1105 |
|
1106 /** |
|
1107 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation |
|
1108 * @hw: pointer to the HW structure |
|
1109 * @duplex: current duplex setting |
|
1110 * |
|
1111 * Configure the KMRN interface by applying last minute quirks for |
|
1112 * 10/100 operation. |
|
1113 **/ |
|
1114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) |
|
1115 { |
|
1116 s32 ret_val; |
|
1117 u32 tipg; |
|
1118 u32 i = 0; |
|
1119 u16 reg_data, reg_data2; |
|
1120 |
|
1121 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; |
|
1122 ret_val = |
|
1123 e1000_write_kmrn_reg_80003es2lan(hw, |
|
1124 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
|
1125 reg_data); |
|
1126 if (ret_val) |
|
1127 return ret_val; |
|
1128 |
|
1129 /* Configure Transmit Inter-Packet Gap */ |
|
1130 tipg = er32(TIPG); |
|
1131 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
1132 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; |
|
1133 ew32(TIPG, tipg); |
|
1134 |
|
1135 do { |
|
1136 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
1137 if (ret_val) |
|
1138 return ret_val; |
|
1139 |
|
1140 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); |
|
1141 if (ret_val) |
|
1142 return ret_val; |
|
1143 i++; |
|
1144 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); |
|
1145 |
|
1146 if (duplex == HALF_DUPLEX) |
|
1147 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1148 else |
|
1149 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1150 |
|
1151 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
1152 } |
|
1153 |
|
1154 /** |
|
1155 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation |
|
1156 * @hw: pointer to the HW structure |
|
1157 * |
|
1158 * Configure the KMRN interface by applying last minute quirks for |
|
1159 * gigabit operation. |
|
1160 **/ |
|
1161 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) |
|
1162 { |
|
1163 s32 ret_val; |
|
1164 u16 reg_data, reg_data2; |
|
1165 u32 tipg; |
|
1166 u32 i = 0; |
|
1167 |
|
1168 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; |
|
1169 ret_val = |
|
1170 e1000_write_kmrn_reg_80003es2lan(hw, |
|
1171 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
|
1172 reg_data); |
|
1173 if (ret_val) |
|
1174 return ret_val; |
|
1175 |
|
1176 /* Configure Transmit Inter-Packet Gap */ |
|
1177 tipg = er32(TIPG); |
|
1178 tipg &= ~E1000_TIPG_IPGT_MASK; |
|
1179 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; |
|
1180 ew32(TIPG, tipg); |
|
1181 |
|
1182 do { |
|
1183 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
|
1184 if (ret_val) |
|
1185 return ret_val; |
|
1186 |
|
1187 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); |
|
1188 if (ret_val) |
|
1189 return ret_val; |
|
1190 i++; |
|
1191 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); |
|
1192 |
|
1193 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
|
1194 |
|
1195 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
|
1196 } |
|
1197 |
|
1198 /** |
|
1199 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register |
|
1200 * @hw: pointer to the HW structure |
|
1201 * @offset: register offset to be read |
|
1202 * @data: pointer to the read data |
|
1203 * |
|
1204 * Acquire semaphore, then read the PHY register at offset |
|
1205 * using the kumeran interface. The information retrieved is stored in data. |
|
1206 * Release the semaphore before exiting. |
|
1207 **/ |
|
1208 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
|
1209 u16 *data) |
|
1210 { |
|
1211 u32 kmrnctrlsta; |
|
1212 s32 ret_val; |
|
1213 |
|
1214 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); |
|
1215 if (ret_val) |
|
1216 return ret_val; |
|
1217 |
|
1218 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
1219 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
|
1220 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
1221 e1e_flush(); |
|
1222 |
|
1223 udelay(2); |
|
1224 |
|
1225 kmrnctrlsta = er32(KMRNCTRLSTA); |
|
1226 *data = (u16)kmrnctrlsta; |
|
1227 |
|
1228 e1000_release_mac_csr_80003es2lan(hw); |
|
1229 |
|
1230 return ret_val; |
|
1231 } |
|
1232 |
|
1233 /** |
|
1234 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register |
|
1235 * @hw: pointer to the HW structure |
|
1236 * @offset: register offset to write to |
|
1237 * @data: data to write at register offset |
|
1238 * |
|
1239 * Acquire semaphore, then write the data to PHY register |
|
1240 * at the offset using the kumeran interface. Release semaphore |
|
1241 * before exiting. |
|
1242 **/ |
|
1243 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
|
1244 u16 data) |
|
1245 { |
|
1246 u32 kmrnctrlsta; |
|
1247 s32 ret_val; |
|
1248 |
|
1249 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); |
|
1250 if (ret_val) |
|
1251 return ret_val; |
|
1252 |
|
1253 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
1254 E1000_KMRNCTRLSTA_OFFSET) | data; |
|
1255 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
1256 e1e_flush(); |
|
1257 |
|
1258 udelay(2); |
|
1259 |
|
1260 e1000_release_mac_csr_80003es2lan(hw); |
|
1261 |
|
1262 return ret_val; |
|
1263 } |
|
1264 |
|
1265 /** |
|
1266 * e1000_read_mac_addr_80003es2lan - Read device MAC address |
|
1267 * @hw: pointer to the HW structure |
|
1268 **/ |
|
1269 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) |
|
1270 { |
|
1271 s32 ret_val; |
|
1272 |
|
1273 /* If there's an alternate MAC address place it in RAR0 |
|
1274 * so that it will override the Si installed default perm |
|
1275 * address. |
|
1276 */ |
|
1277 ret_val = e1000_check_alt_mac_addr_generic(hw); |
|
1278 if (ret_val) |
|
1279 return ret_val; |
|
1280 |
|
1281 return e1000_read_mac_addr_generic(hw); |
|
1282 } |
|
1283 |
|
1284 /** |
|
1285 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down |
|
1286 * @hw: pointer to the HW structure |
|
1287 * |
|
1288 * In the case of a PHY power down to save power, or to turn off link during a |
|
1289 * driver unload, or wake on lan is not enabled, remove the link. |
|
1290 **/ |
|
1291 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) |
|
1292 { |
|
1293 /* If the management interface is not enabled, then power down */ |
|
1294 if (!(hw->mac.ops.check_mng_mode(hw) || |
|
1295 hw->phy.ops.check_reset_block(hw))) |
|
1296 e1000_power_down_phy_copper(hw); |
|
1297 } |
|
1298 |
|
1299 /** |
|
1300 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters |
|
1301 * @hw: pointer to the HW structure |
|
1302 * |
|
1303 * Clears the hardware counters by reading the counter registers. |
|
1304 **/ |
|
1305 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) |
|
1306 { |
|
1307 e1000e_clear_hw_cntrs_base(hw); |
|
1308 |
|
1309 er32(PRC64); |
|
1310 er32(PRC127); |
|
1311 er32(PRC255); |
|
1312 er32(PRC511); |
|
1313 er32(PRC1023); |
|
1314 er32(PRC1522); |
|
1315 er32(PTC64); |
|
1316 er32(PTC127); |
|
1317 er32(PTC255); |
|
1318 er32(PTC511); |
|
1319 er32(PTC1023); |
|
1320 er32(PTC1522); |
|
1321 |
|
1322 er32(ALGNERRC); |
|
1323 er32(RXERRC); |
|
1324 er32(TNCRS); |
|
1325 er32(CEXTERR); |
|
1326 er32(TSCTC); |
|
1327 er32(TSCTFC); |
|
1328 |
|
1329 er32(MGTPRC); |
|
1330 er32(MGTPDC); |
|
1331 er32(MGTPTC); |
|
1332 |
|
1333 er32(IAC); |
|
1334 er32(ICRXOC); |
|
1335 |
|
1336 er32(ICRXPTC); |
|
1337 er32(ICRXATC); |
|
1338 er32(ICTXPTC); |
|
1339 er32(ICTXATC); |
|
1340 er32(ICTXQEC); |
|
1341 er32(ICTXQMTC); |
|
1342 er32(ICRXDMTC); |
|
1343 } |
|
1344 |
|
1345 static const struct e1000_mac_operations es2_mac_ops = { |
|
1346 .read_mac_addr = e1000_read_mac_addr_80003es2lan, |
|
1347 .id_led_init = e1000e_id_led_init_generic, |
|
1348 .blink_led = e1000e_blink_led_generic, |
|
1349 .check_mng_mode = e1000e_check_mng_mode_generic, |
|
1350 /* check_for_link dependent on media type */ |
|
1351 .cleanup_led = e1000e_cleanup_led_generic, |
|
1352 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, |
|
1353 .get_bus_info = e1000e_get_bus_info_pcie, |
|
1354 .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
|
1355 .get_link_up_info = e1000_get_link_up_info_80003es2lan, |
|
1356 .led_on = e1000e_led_on_generic, |
|
1357 .led_off = e1000e_led_off_generic, |
|
1358 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
|
1359 .write_vfta = e1000_write_vfta_generic, |
|
1360 .clear_vfta = e1000_clear_vfta_generic, |
|
1361 .reset_hw = e1000_reset_hw_80003es2lan, |
|
1362 .init_hw = e1000_init_hw_80003es2lan, |
|
1363 .setup_link = e1000e_setup_link_generic, |
|
1364 /* setup_physical_interface dependent on media type */ |
|
1365 .setup_led = e1000e_setup_led_generic, |
|
1366 .config_collision_dist = e1000e_config_collision_dist_generic, |
|
1367 .rar_set = e1000e_rar_set_generic, |
|
1368 .rar_get_count = e1000e_rar_get_count_generic, |
|
1369 }; |
|
1370 |
|
1371 static const struct e1000_phy_operations es2_phy_ops = { |
|
1372 .acquire = e1000_acquire_phy_80003es2lan, |
|
1373 .check_polarity = e1000_check_polarity_m88, |
|
1374 .check_reset_block = e1000e_check_reset_block_generic, |
|
1375 .commit = e1000e_phy_sw_reset, |
|
1376 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, |
|
1377 .get_cfg_done = e1000_get_cfg_done_80003es2lan, |
|
1378 .get_cable_length = e1000_get_cable_length_80003es2lan, |
|
1379 .get_info = e1000e_get_phy_info_m88, |
|
1380 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, |
|
1381 .release = e1000_release_phy_80003es2lan, |
|
1382 .reset = e1000e_phy_hw_reset_generic, |
|
1383 .set_d0_lplu_state = NULL, |
|
1384 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1385 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, |
|
1386 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, |
|
1387 }; |
|
1388 |
|
1389 static const struct e1000_nvm_operations es2_nvm_ops = { |
|
1390 .acquire = e1000_acquire_nvm_80003es2lan, |
|
1391 .read = e1000e_read_nvm_eerd, |
|
1392 .release = e1000_release_nvm_80003es2lan, |
|
1393 .reload = e1000e_reload_nvm_generic, |
|
1394 .update = e1000e_update_nvm_checksum_generic, |
|
1395 .valid_led_default = e1000e_valid_led_default, |
|
1396 .validate = e1000e_validate_nvm_checksum_generic, |
|
1397 .write = e1000_write_nvm_80003es2lan, |
|
1398 }; |
|
1399 |
|
1400 const struct e1000_info e1000_es2_info = { |
|
1401 .mac = e1000_80003es2lan, |
|
1402 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1403 | FLAG_HAS_JUMBO_FRAMES |
|
1404 | FLAG_HAS_WOL |
|
1405 | FLAG_APME_IN_CTRL3 |
|
1406 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
1407 | FLAG_RX_NEEDS_RESTART /* errata */ |
|
1408 | FLAG_TARC_SET_BIT_ZERO /* errata */ |
|
1409 | FLAG_APME_CHECK_PORT_B |
|
1410 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */ |
|
1411 .flags2 = FLAG2_DMA_BURST, |
|
1412 .pba = 38, |
|
1413 .max_hw_frame_size = DEFAULT_JUMBO, |
|
1414 .get_variants = e1000_get_variants_80003es2lan, |
|
1415 .mac_ops = &es2_mac_ops, |
|
1416 .phy_ops = &es2_phy_ops, |
|
1417 .nvm_ops = &es2_nvm_ops, |
|
1418 }; |