1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2014  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *  vim: noexpandtab

    29  *

    30  *****************************************************************************/

    31 

    32 /**

    33    \file

    34    EtherCAT driver for RTL8139-compatible NICs.

    35 */

    36 

    37 /*****************************************************************************/

    38 

    39 /*

    40   Former documentation:

    41 

    42 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    43 

    44 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    45 	Copyright 2000-2002 Jeff Garzik

    46 

    47 	Much code comes from Donald Becker's rtl8139.c driver,

    48 	versions 1.13 and older.  This driver was originally based

    49 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    50 

    51 	-----<snip>-----

    52 

    53         	Written 1997-2001 by Donald Becker.

    54 		This software may be used and distributed according to the

    55 		terms of the GNU General Public License (GPL), incorporated

    56 		herein by reference.  Drivers based on or derived from this

    57 		code fall under the GPL and must retain the authorship,

    58 		copyright and license notice.  This file is not a complete

    59 		program and may only be used when the entire operating

    60 		system is licensed under the GPL.

    61 

    62 		This driver is for boards based on the RTL8129 and RTL8139

    63 		PCI ethernet chips.

    64 

    65 		The author may be reached as becker@scyld.com, or C/O Scyld

    66 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    67 		MD 21403

    68 

    69 		Support and updates available at

    70 		http://www.scyld.com/network/rtl8139.html

    71 

    72 		Twister-tuning table provided by Kinston

    73 		<shangh@realtek.com.tw>.

    74 

    75 	-----<snip>-----

    76 

    77 	This software may be used and distributed according to the terms

    78 	of the GNU General Public License, incorporated herein by reference.

    79 

    80 	Contributors:

    81 

    82 		Donald Becker - he wrote the original driver, kudos to him!

    83 		(but please don't e-mail him for support, this isn't his driver)

    84 

    85 		Tigran Aivazian - bug fixes, skbuff free cleanup

    86 

    87 		Martin Mares - suggestions for PCI cleanup

    88 

    89 		David S. Miller - PCI DMA and softnet updates

    90 

    91 		Ernst Gill - fixes ported from BSD driver

    92 

    93 		Daniel Kobras - identified specific locations of

    94 			posted MMIO write bugginess

    95 

    96 		Gerard Sharp - bug fix, testing and feedback

    97 

    98 		David Ford - Rx ring wrap fix

    99 

   100 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   101 		to find and fix a crucial bug on older chipsets.

   102 

   103 		Donald Becker/Chris Butterworth/Marcus Westergren -

   104 		Noticed various Rx packet size-related buglets.

   105 

   106 		Santiago Garcia Mantinan - testing and feedback

   107 

   108 		Jens David - 2.2.x kernel backports

   109 

   110 		Martin Dennett - incredibly helpful insight on undocumented

   111 		features of the 8139 chips

   112 

   113 		Jean-Jacques Michel - bug fix

   114 

   115 		Tobias Ringström - Rx interrupt status checking suggestion

   116 

   117 		Andrew Morton - Clear blocked signals, avoid

   118 		buffer overrun setting current->comm.

   119 

   120 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   121 

   122 		Robert Kuebel - Save kernel thread from dying on any signal.

   123 

   124 	Submitting bug reports:

   125 

   126 		"rtl8139-diag -mmmaaavvveefN" output

   127 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   128 

   129 */

   130 

   131 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

   132 

   133 #define DRV_NAME	"ec_8139too"

   134 #define DRV_VERSION	"0.9.28"

   135 

   136 

   137 #include <linux/module.h>

   138 #include <linux/kernel.h>

   139 #include <linux/compiler.h>

   140 #include <linux/pci.h>

   141 #include <linux/init.h>

   142 #include <linux/interrupt.h>

   143 #include <linux/netdevice.h>

   144 #include <linux/etherdevice.h>

   145 #include <linux/rtnetlink.h>

   146 #include <linux/delay.h>

   147 #include <linux/ethtool.h>

   148 #include <linux/mii.h>

   149 #include <linux/completion.h>

   150 #include <linux/crc32.h>

   151 #include <linux/io.h>

   152 #include <linux/uaccess.h>

   153 #include <linux/gfp.h>

   154 #include <asm/irq.h>

   155 

   156 #include "../globals.h"

   157 #include "ecdev.h"

   158 

   159 #define RTL8139_DRIVER_NAME DRV_NAME \

   160 	" EtherCAT-capable Fast Ethernet driver " \

   161 	DRV_VERSION ", master " EC_MASTER_VERSION

   162 

   163 #define PFX DRV_NAME ": "

   164 

   165 /* Default Message level */

   166 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   167                                  NETIF_MSG_PROBE  | \

   168                                  NETIF_MSG_LINK)

   169 

   170 

   171 /* define to 1, 2 or 3 to enable copious debugging info */

   172 #define RTL8139_DEBUG 0

   173 

   174 /* define to 1 to disable lightweight runtime debugging checks */

   175 #undef RTL8139_NDEBUG

   176 

   177 

   178 #ifdef RTL8139_NDEBUG

   179 #  define assert(expr) do {} while (0)

   180 #else

   181 #  define assert(expr) \

   182         if (unlikely(!(expr))) {				\

   183 		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   184 		       #expr, __FILE__, __func__, __LINE__);	\

   185         }

   186 #endif

   187 

   188 

   189 /* A few user-configurable values. */

   190 /* media options */

   191 #define MAX_UNITS 8

   192 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   193 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   194 

   195 /* Whether to use MMIO or PIO. Default to MMIO. */

   196 #ifdef CONFIG_8139TOO_PIO

   197 static bool use_io = true;

   198 #else

   199 static bool use_io = false;

   200 #endif

   201 

   202 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   203    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   204 static int multicast_filter_limit = 32;

   205 

   206 /* bitmapped message enable number */

   207 static int debug = -1;

   208 

   209 /*

   210  * Receive ring size

   211  * Warning: 64K ring has hardware issues and may lock up.

   212  */

   213 #if defined(CONFIG_SH_DREAMCAST)

   214 #define RX_BUF_IDX 0	/* 8K ring */

   215 #else

   216 #define RX_BUF_IDX	2	/* 32K ring */

   217 #endif

   218 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   219 #define RX_BUF_PAD	16

   220 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   221 

   222 #if RX_BUF_LEN == 65536

   223 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   224 #else

   225 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   226 #endif

   227 

   228 /* Number of Tx descriptor registers. */

   229 #define NUM_TX_DESC	4

   230 

   231 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   232 #define MAX_ETH_FRAME_SIZE	1536

   233 

   234 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   235 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   236 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   237 

   238 /* PCI Tuning Parameters

   239    Threshold is bytes transferred to chip before transmission starts. */

   240 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   241 

   242 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   243 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   244 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   245 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   246 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   247 

   248 /* Operational parameters that usually are not changed. */

   249 /* Time in jiffies before concluding the transmitter is hung. */

   250 #define TX_TIMEOUT  (6*HZ)

   251 

   252 

   253 enum {

   254 	HAS_MII_XCVR = 0x010000,

   255 	HAS_CHIP_XCVR = 0x020000,

   256 	HAS_LNK_CHNG = 0x040000,

   257 };

   258 

   259 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   260 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   261 #define RTL_MIN_IO_SIZE 0x80

   262 #define RTL8139B_IO_SIZE 256

   263 

   264 #define RTL8129_CAPS	HAS_MII_XCVR

   265 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   266 

   267 typedef enum {

   268 	RTL8139 = 0,

   269 	RTL8129,

   270 } board_t;

   271 

   272 

   273 /* indexed by board_t, above */

   274 static const struct {

   275 	const char *name;

   276 	u32 hw_flags;

   277 } board_info[] = {

   278 	{ "RealTek RTL8139", RTL8139_CAPS },

   279 	{ "RealTek RTL8129", RTL8129_CAPS },

   280 };

   281 

   282 

   283 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   284 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 

   304 #ifdef CONFIG_SH_SECUREEDGE5410

   305 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   306 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307 #endif

   308 #ifdef CONFIG_8139TOO_8129

   309 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   310 #endif

   311 

   312 	/* some crazy cards report invalid vendor ids like

   313 	 * 0x0001 here.  The other ids are valid and constant,

   314 	 * so we simply don't match on the main vendor id.

   315 	 */

   316 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   317 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   318 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   319 

   320 	{0,}

   321 };

   322 

   323 /* prevent driver from being loaded automatically */

   324 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   325 

   326 static struct {

   327 	const char str[ETH_GSTRING_LEN];

   328 } ethtool_stats_keys[] = {

   329 	{ "early_rx" },

   330 	{ "tx_buf_mapped" },

   331 	{ "tx_timeouts" },

   332 	{ "rx_lost_in_ring" },

   333 };

   334 

   335 /* The rest of these values should never change. */

   336 

   337 /* Symbolic offsets to registers. */

   338 enum RTL8139_registers {

   339 	MAC0		= 0,	 /* Ethernet hardware address. */

   340 	MAR0		= 8,	 /* Multicast filter. */

   341 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   342 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   343 	RxBuf		= 0x30,

   344 	ChipCmd		= 0x37,

   345 	RxBufPtr	= 0x38,

   346 	RxBufAddr	= 0x3A,

   347 	IntrMask	= 0x3C,

   348 	IntrStatus	= 0x3E,

   349 	TxConfig	= 0x40,

   350 	RxConfig	= 0x44,

   351 	Timer		= 0x48,	 /* A general-purpose counter. */

   352 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   353 	Cfg9346		= 0x50,

   354 	Config0		= 0x51,

   355 	Config1		= 0x52,

   356 	TimerInt	= 0x54,

   357 	MediaStatus	= 0x58,

   358 	Config3		= 0x59,

   359 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   360 	HltClk		= 0x5B,

   361 	MultiIntr	= 0x5C,

   362 	TxSummary	= 0x60,

   363 	BasicModeCtrl	= 0x62,

   364 	BasicModeStatus	= 0x64,

   365 	NWayAdvert	= 0x66,

   366 	NWayLPAR	= 0x68,

   367 	NWayExpansion	= 0x6A,

   368 	/* Undocumented registers, but required for proper operation. */

   369 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   370 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   371 	PARA78		= 0x78,

   372 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   373 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   374 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   375 };

   376 

   377 enum ClearBitMasks {

   378 	MultiIntrClear	= 0xF000,

   379 	ChipCmdClear	= 0xE2,

   380 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   381 };

   382 

   383 enum ChipCmdBits {

   384 	CmdReset	= 0x10,

   385 	CmdRxEnb	= 0x08,

   386 	CmdTxEnb	= 0x04,

   387 	RxBufEmpty	= 0x01,

   388 };

   389 

   390 /* Interrupt register bits, using my own meaningful names. */

   391 enum IntrStatusBits {

   392 	PCIErr		= 0x8000,

   393 	PCSTimeout	= 0x4000,

   394 	RxFIFOOver	= 0x40,

   395 	RxUnderrun	= 0x20,

   396 	RxOverflow	= 0x10,

   397 	TxErr		= 0x08,

   398 	TxOK		= 0x04,

   399 	RxErr		= 0x02,

   400 	RxOK		= 0x01,

   401 

   402 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   403 };

   404 

   405 enum TxStatusBits {

   406 	TxHostOwns	= 0x2000,

   407 	TxUnderrun	= 0x4000,

   408 	TxStatOK	= 0x8000,

   409 	TxOutOfWindow	= 0x20000000,

   410 	TxAborted	= 0x40000000,

   411 	TxCarrierLost	= 0x80000000,

   412 };

   413 enum RxStatusBits {

   414 	RxMulticast	= 0x8000,

   415 	RxPhysical	= 0x4000,

   416 	RxBroadcast	= 0x2000,

   417 	RxBadSymbol	= 0x0020,

   418 	RxRunt		= 0x0010,

   419 	RxTooLong	= 0x0008,

   420 	RxCRCErr	= 0x0004,

   421 	RxBadAlign	= 0x0002,

   422 	RxStatusOK	= 0x0001,

   423 };

   424 

   425 /* Bits in RxConfig. */

   426 enum rx_mode_bits {

   427 	AcceptErr	= 0x20,

   428 	AcceptRunt	= 0x10,

   429 	AcceptBroadcast	= 0x08,

   430 	AcceptMulticast	= 0x04,

   431 	AcceptMyPhys	= 0x02,

   432 	AcceptAllPhys	= 0x01,

   433 };

   434 

   435 /* Bits in TxConfig. */

   436 enum tx_config_bits {

   437         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   438         TxIFGShift	= 24,

   439         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   440         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   441         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   442         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   443 

   444 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   445 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   446 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   447 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   448 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   449 

   450 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   451 };

   452 

   453 /* Bits in Config1 */

   454 enum Config1Bits {

   455 	Cfg1_PM_Enable	= 0x01,

   456 	Cfg1_VPD_Enable	= 0x02,

   457 	Cfg1_PIO	= 0x04,

   458 	Cfg1_MMIO	= 0x08,

   459 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   460 	Cfg1_Driver_Load = 0x20,

   461 	Cfg1_LED0	= 0x40,

   462 	Cfg1_LED1	= 0x80,

   463 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   464 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   465 };

   466 

   467 /* Bits in Config3 */

   468 enum Config3Bits {

   469 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   470 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   471 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   472 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   473 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   474 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   475 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   476 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   477 };

   478 

   479 /* Bits in Config4 */

   480 enum Config4Bits {

   481 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   482 };

   483 

   484 /* Bits in Config5 */

   485 enum Config5Bits {

   486 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   487 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   488 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   489 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   490 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   491 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   492 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   493 };

   494 

   495 enum RxConfigBits {

   496 	/* rx fifo threshold */

   497 	RxCfgFIFOShift	= 13,

   498 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   499 

   500 	/* Max DMA burst */

   501 	RxCfgDMAShift	= 8,

   502 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   503 

   504 	/* rx ring buffer length */

   505 	RxCfgRcv8K	= 0,

   506 	RxCfgRcv16K	= (1 << 11),

   507 	RxCfgRcv32K	= (1 << 12),

   508 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   509 

   510 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   511 	RxNoWrap	= (1 << 7),

   512 };

   513 

   514 /* Twister tuning parameters from RealTek.

   515    Completely undocumented, but required to tune bad links on some boards. */

   516 enum CSCRBits {

   517 	CSCR_LinkOKBit		= 0x0400,

   518 	CSCR_LinkChangeBit	= 0x0800,

   519 	CSCR_LinkStatusBits	= 0x0f000,

   520 	CSCR_LinkDownOffCmd	= 0x003c0,

   521 	CSCR_LinkDownCmd	= 0x0f3c0,

   522 };

   523 

   524 enum Cfg9346Bits {

   525 	Cfg9346_Lock	= 0x00,

   526 	Cfg9346_Unlock	= 0xC0,

   527 };

   528 

   529 typedef enum {

   530 	CH_8139	= 0,

   531 	CH_8139_K,

   532 	CH_8139A,

   533 	CH_8139A_G,

   534 	CH_8139B,

   535 	CH_8130,

   536 	CH_8139C,

   537 	CH_8100,

   538 	CH_8100B_8139D,

   539 	CH_8101,

   540 } chip_t;

   541 

   542 enum chip_flags {

   543 	HasHltClk	= (1 << 0),

   544 	HasLWake	= (1 << 1),

   545 };

   546 

   547 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   548 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   549 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   550 

   551 /* directly indexed by chip_t, above */

   552 static const struct {

   553 	const char *name;

   554 	u32 version; /* from RTL8139C/RTL8139D docs */

   555 	u32 flags;

   556 } rtl_chip_info[] = {

   557 	{ "RTL-8139",

   558 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   559 	  HasHltClk,

   560 	},

   561 

   562 	{ "RTL-8139 rev K",

   563 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   564 	  HasHltClk,

   565 	},

   566 

   567 	{ "RTL-8139A",

   568 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   569 	  HasHltClk, /* XXX undocumented? */

   570 	},

   571 

   572 	{ "RTL-8139A rev G",

   573 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   574 	  HasHltClk, /* XXX undocumented? */

   575 	},

   576 

   577 	{ "RTL-8139B",

   578 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   579 	  HasLWake,

   580 	},

   581 

   582 	{ "RTL-8130",

   583 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   584 	  HasLWake,

   585 	},

   586 

   587 	{ "RTL-8139C",

   588 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   589 	  HasLWake,

   590 	},

   591 

   592 	{ "RTL-8100",

   593 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   594  	  HasLWake,

   595  	},

   596 

   597 	{ "RTL-8100B/8139D",

   598 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   599 	  HasHltClk /* XXX undocumented? */

   600 	| HasLWake,

   601 	},

   602 

   603 	{ "RTL-8101",

   604 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   605 	  HasLWake,

   606 	},

   607 };

   608 

   609 struct rtl_extra_stats {

   610 	unsigned long early_rx;

   611 	unsigned long tx_buf_mapped;

   612 	unsigned long tx_timeouts;

   613 	unsigned long rx_lost_in_ring;

   614 };

   615 

   616 struct rtl8139_stats {

   617 	u64	packets;

   618 	u64	bytes;

   619 	struct u64_stats_sync	syncp;

   620 };

   621 

   622 struct rtl8139_private {

   623 	void __iomem		*mmio_addr;

   624 	int			drv_flags;

   625 	struct pci_dev		*pci_dev;

   626 	u32			msg_enable;

   627 	struct napi_struct	napi;

   628 	struct net_device	*dev;

   629 

   630 	unsigned char		*rx_ring;

   631 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   632 	struct rtl8139_stats	rx_stats;

   633 	dma_addr_t		rx_ring_dma;

   634 

   635 	unsigned int		tx_flag;

   636 	unsigned long		cur_tx;

   637 	unsigned long		dirty_tx;

   638 	struct rtl8139_stats	tx_stats;

   639 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   640 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   641 	dma_addr_t		tx_bufs_dma;

   642 

   643 	signed char		phys[4];	/* MII device addresses. */

   644 

   645 				/* Twister tune state. */

   646 	char			twistie, twist_row, twist_col;

   647 

   648 	unsigned int		watchdog_fired : 1;

   649 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   650 	unsigned int		have_thread : 1;

   651 

   652 	spinlock_t		lock;

   653 	spinlock_t		rx_lock;

   654 

   655 	chip_t			chipset;

   656 	u32			rx_config;

   657 	struct rtl_extra_stats	xstats;

   658 

   659 	struct delayed_work	thread;

   660 

   661 	struct mii_if_info	mii;

   662 	unsigned int		regs_len;

   663 	unsigned long		fifo_copy_timeout;

   664 

   665 	ec_device_t *ecdev;

   666 };

   667 

   668 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   669 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   670 MODULE_LICENSE("GPL");

   671 MODULE_VERSION(EC_MASTER_VERSION);

   672 

   673 module_param(use_io, bool, 0);

   674 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   675 module_param(multicast_filter_limit, int, 0);

   676 module_param_array(media, int, NULL, 0);

   677 module_param_array(full_duplex, int, NULL, 0);

   678 module_param(debug, int, 0);

   679 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   680 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   681 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   682 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   683 

   684 void ec_poll(struct net_device *);

   685 

   686 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   687 static int rtl8139_open (struct net_device *dev);

   688 static int mdio_read (struct net_device *dev, int phy_id, int location);

   689 static void mdio_write (struct net_device *dev, int phy_id, int location,

   690 			int val);

   691 static void rtl8139_start_thread(struct rtl8139_private *tp);

   692 static void rtl8139_tx_timeout (struct net_device *dev);

   693 static void rtl8139_init_ring (struct net_device *dev);

   694 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,

   695 				       struct net_device *dev);

   696 #ifdef CONFIG_NET_POLL_CONTROLLER

   697 static void rtl8139_poll_controller(struct net_device *dev);

   698 #endif

   699 static int rtl8139_set_mac_address(struct net_device *dev, void *p);

   700 static int rtl8139_poll(struct napi_struct *napi, int budget);

   701 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   702 static int rtl8139_close (struct net_device *dev);

   703 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   704 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,

   705 						    struct rtnl_link_stats64

   706 						    *stats);

   707 static void rtl8139_set_rx_mode (struct net_device *dev);

   708 static void __set_rx_mode (struct net_device *dev);

   709 static void rtl8139_hw_start (struct net_device *dev);

   710 static void rtl8139_thread (struct work_struct *work);

   711 static void rtl8139_tx_timeout_task(struct work_struct *work);

   712 static const struct ethtool_ops rtl8139_ethtool_ops;

   713 

   714 /* write MMIO register, with flush */

   715 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   716 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   717 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   718 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   719 

   720 /* write MMIO register */

   721 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   722 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   723 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   724 

   725 /* read MMIO register */

   726 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   727 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   728 #define RTL_R32(reg)		ioread32 (ioaddr + (reg))

   729 

   730 

   731 static const u16 rtl8139_intr_mask =

   732 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   733 	TxErr | TxOK | RxErr | RxOK;

   734 

   735 static const u16 rtl8139_norx_intr_mask =

   736 	PCIErr | PCSTimeout | RxUnderrun |

   737 	TxErr | TxOK | RxErr ;

   738 

   739 #if RX_BUF_IDX == 0

   740 static const unsigned int rtl8139_rx_config =

   741 	RxCfgRcv8K | RxNoWrap |

   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   743 	(RX_DMA_BURST << RxCfgDMAShift);

   744 #elif RX_BUF_IDX == 1

   745 static const unsigned int rtl8139_rx_config =

   746 	RxCfgRcv16K | RxNoWrap |

   747 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   748 	(RX_DMA_BURST << RxCfgDMAShift);

   749 #elif RX_BUF_IDX == 2

   750 static const unsigned int rtl8139_rx_config =

   751 	RxCfgRcv32K | RxNoWrap |

   752 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   753 	(RX_DMA_BURST << RxCfgDMAShift);

   754 #elif RX_BUF_IDX == 3

   755 static const unsigned int rtl8139_rx_config =

   756 	RxCfgRcv64K |

   757 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   758 	(RX_DMA_BURST << RxCfgDMAShift);

   759 #else

   760 #error "Invalid configuration for 8139_RXBUF_IDX"

   761 #endif

   762 

   763 static const unsigned int rtl8139_tx_config =

   764 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   765 

   766 static void __rtl8139_cleanup_dev (struct net_device *dev)

   767 {

   768 	struct rtl8139_private *tp = netdev_priv(dev);

   769 	struct pci_dev *pdev;

   770 

   771 	assert (dev != NULL);

   772 	assert (tp->pci_dev != NULL);

   773 	pdev = tp->pci_dev;

   774 

   775 	if (tp->mmio_addr)

   776 		pci_iounmap (pdev, tp->mmio_addr);

   777 

   778 	/* it's ok to call this even if we have no regions to free */

   779 	pci_release_regions (pdev);

   780 

   781 	free_netdev(dev);

   782 }

   783 

   784 

   785 static void rtl8139_chip_reset (void __iomem *ioaddr)

   786 {

   787 	int i;

   788 

   789 	/* Soft reset the chip. */

   790 	RTL_W8 (ChipCmd, CmdReset);

   791 

   792 	/* Check that the chip has finished the reset. */

   793 	for (i = 1000; i > 0; i--) {

   794 		barrier();

   795 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   796 			break;

   797 		udelay (10);

   798 	}

   799 }

   800 

   801 

   802 static struct net_device *rtl8139_init_board(struct pci_dev *pdev)

   803 {

   804 	struct device *d = &pdev->dev;

   805 	void __iomem *ioaddr;

   806 	struct net_device *dev;

   807 	struct rtl8139_private *tp;

   808 	u8 tmp8;

   809 	int rc, disable_dev_on_err = 0;

   810 	unsigned int i, bar;

   811 	unsigned long io_len;

   812 	u32 version;

   813 	static const struct {

   814 		unsigned long mask;

   815 		char *type;

   816 	} res[] = {

   817 		{ IORESOURCE_IO,  "PIO" },

   818 		{ IORESOURCE_MEM, "MMIO" }

   819 	};

   820 

   821 	assert (pdev != NULL);

   822 

   823 	/* dev and priv zeroed in alloc_etherdev */

   824 	dev = alloc_etherdev (sizeof (*tp));

   825 	if (dev == NULL)

   826 		return ERR_PTR(-ENOMEM);

   827 

   828 	SET_NETDEV_DEV(dev, &pdev->dev);

   829 

   830 	tp = netdev_priv(dev);

   831 	tp->pci_dev = pdev;

   832 

   833 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   834 	rc = pci_enable_device (pdev);

   835 	if (rc)

   836 		goto err_out;

   837 

   838 	rc = pci_request_regions (pdev, DRV_NAME);

   839 	if (rc)

   840 		goto err_out;

   841 	disable_dev_on_err = 1;

   842 

   843 	pci_set_master (pdev);

   844 

   845 	u64_stats_init(&tp->rx_stats.syncp);

   846 	u64_stats_init(&tp->tx_stats.syncp);

   847 

   848 retry:

   849 	/* PIO bar register comes first. */

   850 	bar = !use_io;

   851 

   852 	io_len = pci_resource_len(pdev, bar);

   853 

   854 	dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);

   855 

   856 	if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {

   857 		dev_err(d, "region #%d not a %s resource, aborting\n", bar,

   858 			res[bar].type);

   859 		rc = -ENODEV;

   860 		goto err_out;

   861 	}

   862 	if (io_len < RTL_MIN_IO_SIZE) {

   863 		dev_err(d, "Invalid PCI %s region size(s), aborting\n",

   864 			res[bar].type);

   865 		rc = -ENODEV;

   866 		goto err_out;

   867 	}

   868 

   869 	ioaddr = pci_iomap(pdev, bar, 0);

   870 	if (!ioaddr) {

   871 		dev_err(d, "cannot map %s\n", res[bar].type);

   872 		if (!use_io) {

   873 			use_io = true;

   874 			goto retry;

   875 		}

   876 		rc = -ENODEV;

   877 		goto err_out;

   878 	}

   879 	tp->regs_len = io_len;

   880 	tp->mmio_addr = ioaddr;

   881 

   882 	/* Bring old chips out of low-power mode. */

   883 	RTL_W8 (HltClk, 'R');

   884 

   885 	/* check for missing/broken hardware */

   886 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   887 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   888 		rc = -EIO;

   889 		goto err_out;

   890 	}

   891 

   892 	/* identify chip attached to board */

   893 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   894 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   895 		if (version == rtl_chip_info[i].version) {

   896 			tp->chipset = i;

   897 			goto match;

   898 		}

   899 

   900 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   901 	i = 0;

   902 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");

   903 	dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));

   904 	tp->chipset = 0;

   905 

   906 match:

   907 	pr_debug("chipset id (%d) == index %d, '%s'\n",

   908 		 version, i, rtl_chip_info[i].name);

   909 

   910 	if (tp->chipset >= CH_8139B) {

   911 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   912 		pr_debug("PCI PM wakeup\n");

   913 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   914 		    (tmp8 & LWAKE))

   915 			new_tmp8 &= ~LWAKE;

   916 		new_tmp8 |= Cfg1_PM_Enable;

   917 		if (new_tmp8 != tmp8) {

   918 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   919 			RTL_W8 (Config1, tmp8);

   920 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   921 		}

   922 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   923 			tmp8 = RTL_R8 (Config4);

   924 			if (tmp8 & LWPTN) {

   925 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   926 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   927 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   928 			}

   929 		}

   930 	} else {

   931 		pr_debug("Old chip wakeup\n");

   932 		tmp8 = RTL_R8 (Config1);

   933 		tmp8 &= ~(SLEEP | PWRDN);

   934 		RTL_W8 (Config1, tmp8);

   935 	}

   936 

   937 	rtl8139_chip_reset (ioaddr);

   938 

   939 	return dev;

   940 

   941 err_out:

   942 	__rtl8139_cleanup_dev (dev);

   943 	if (disable_dev_on_err)

   944 		pci_disable_device (pdev);

   945 	return ERR_PTR(rc);

   946 }

   947 

   948 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)

   949 {

   950 	struct rtl8139_private *tp = netdev_priv(dev);

   951 	unsigned long flags;

   952 	netdev_features_t changed = features ^ dev->features;

   953 	void __iomem *ioaddr = tp->mmio_addr;

   954 

   955 	if (!(changed & (NETIF_F_RXALL)))

   956 		return 0;

   957 

   958 	spin_lock_irqsave(&tp->lock, flags);

   959 

   960 	if (changed & NETIF_F_RXALL) {

   961 		int rx_mode = tp->rx_config;

   962 		if (features & NETIF_F_RXALL)

   963 			rx_mode |= (AcceptErr | AcceptRunt);

   964 		else

   965 			rx_mode &= ~(AcceptErr | AcceptRunt);

   966 		tp->rx_config = rtl8139_rx_config | rx_mode;

   967 		RTL_W32_F(RxConfig, tp->rx_config);

   968 	}

   969 

   970 	spin_unlock_irqrestore(&tp->lock, flags);

   971 

   972 	return 0;

   973 }

   974 

   975 static const struct net_device_ops rtl8139_netdev_ops = {

   976 	.ndo_open		= rtl8139_open,

   977 	.ndo_stop		= rtl8139_close,

   978 	.ndo_get_stats64	= rtl8139_get_stats64,

   979 	.ndo_change_mtu		= eth_change_mtu,

   980 	.ndo_validate_addr	= eth_validate_addr,

   981 	.ndo_set_mac_address 	= rtl8139_set_mac_address,

   982 	.ndo_start_xmit		= rtl8139_start_xmit,

   983 	.ndo_set_rx_mode	= rtl8139_set_rx_mode,

   984 	.ndo_do_ioctl		= netdev_ioctl,

   985 	.ndo_tx_timeout		= rtl8139_tx_timeout,

   986 #ifdef CONFIG_NET_POLL_CONTROLLER

   987 	.ndo_poll_controller	= rtl8139_poll_controller,

   988 #endif

   989 	.ndo_set_features	= rtl8139_set_features,

   990 };

   991 

   992 static int rtl8139_init_one(struct pci_dev *pdev,

   993 			    const struct pci_device_id *ent)

   994 {

   995 	struct net_device *dev = NULL;

   996 	struct rtl8139_private *tp;

   997 	int i, addr_len, option;

   998 	void __iomem *ioaddr;

   999 	static int board_idx = -1;

  1000 

  1001 	assert (pdev != NULL);

  1002 	assert (ent != NULL);

  1003 

  1004 	board_idx++;

  1005 

  1006 	/* when we're built into the kernel, the driver version message

  1007 	 * is only printed if at least one 8139 board has been found

  1008 	 */

  1009 #ifndef MODULE

  1010 	{

  1011 		static int printed_version;

  1012 		if (!printed_version++)

  1013 			pr_info(RTL8139_DRIVER_NAME "\n");

  1014 	}

  1015 #endif

  1016 

  1017 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1018 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1019 		dev_info(&pdev->dev,

  1020 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1021 		       	   pdev->vendor, pdev->device, pdev->revision);

  1022 		return -ENODEV;

  1023 	}

  1024 

  1025 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1026 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1027 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1028 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1029 		pr_info("OQO Model 2 detected. Forcing PIO\n");

  1030 		use_io = 1;

  1031 	}

  1032 

  1033 	dev = rtl8139_init_board (pdev);

  1034 	if (IS_ERR(dev))

  1035 		return PTR_ERR(dev);

  1036 

  1037 	assert (dev != NULL);

  1038 	tp = netdev_priv(dev);

  1039 	tp->dev = dev;

  1040 

  1041 	ioaddr = tp->mmio_addr;

  1042 	assert (ioaddr != NULL);

  1043 

  1044 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1045 	for (i = 0; i < 3; i++)

  1046 		((__le16 *) (dev->dev_addr))[i] =

  1047 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1048 

  1049 	/* The Rtl8139-specific entries in the device structure. */

  1050 	dev->netdev_ops = &rtl8139_netdev_ops;

  1051 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1052 	dev->watchdog_timeo = TX_TIMEOUT;

  1053 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1054 

  1055 	/* note: the hardware is not capable of sg/csum/highdma, however

  1056 	 * through the use of skb_copy_and_csum_dev we enable these

  1057 	 * features

  1058 	 */

  1059 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1060 	dev->vlan_features = dev->features;

  1061 

  1062 	dev->hw_features |= NETIF_F_RXALL;

  1063 	dev->hw_features |= NETIF_F_RXFCS;

  1064 

  1065 	/* tp zeroed and aligned in alloc_etherdev */

  1066 	tp = netdev_priv(dev);

  1067 

  1068 	/* note: tp->chipset set in rtl8139_init_board */

  1069 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1070 	tp->mmio_addr = ioaddr;

  1071 	tp->msg_enable =

  1072 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1073 	spin_lock_init (&tp->lock);

  1074 	spin_lock_init (&tp->rx_lock);

  1075 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1076 	tp->mii.dev = dev;

  1077 	tp->mii.mdio_read = mdio_read;

  1078 	tp->mii.mdio_write = mdio_write;

  1079 	tp->mii.phy_id_mask = 0x3f;

  1080 	tp->mii.reg_num_mask = 0x1f;

  1081 

  1082 	/* dev is fully set up and ready to use now */

  1083 

  1084 	// offer device to EtherCAT master module

  1085 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1086 

  1087 	if (!tp->ecdev) {

  1088 		pr_debug("about to register device named %s (%p)...\n",

  1089 				dev->name, dev);

  1090 		i = register_netdev (dev);

  1091 		if (i) goto err_out;

  1092 	}

  1093 

  1094 	pci_set_drvdata (pdev, dev);

  1095 

  1096 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",

  1097 		dev->name,

  1098 		board_info[ent->driver_data].name,

  1099 		dev->base_addr,

  1100 		dev->dev_addr,

  1101 		dev->irq);

  1102 

  1103 	pr_debug("%s:  Identified 8139 chip type '%s'\n",

  1104 		dev->name, rtl_chip_info[tp->chipset].name);

  1105 

  1106 	/* Find the connected MII xcvrs.

  1107 	   Doing this in open() would allow detecting external xcvrs later, but

  1108 	   takes too much time. */

  1109 #ifdef CONFIG_8139TOO_8129

  1110 	if (tp->drv_flags & HAS_MII_XCVR) {

  1111 		int phy, phy_idx = 0;

  1112 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1113 			int mii_status = mdio_read(dev, phy, 1);

  1114 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1115 				u16 advertising = mdio_read(dev, phy, 4);

  1116 				tp->phys[phy_idx++] = phy;

  1117 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",

  1118 					   dev->name, phy, mii_status, advertising);

  1119 			}

  1120 		}

  1121 		if (phy_idx == 0) {

  1122 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",

  1123 				   dev->name);

  1124 			tp->phys[0] = 32;

  1125 		}

  1126 	} else

  1127 #endif

  1128 		tp->phys[0] = 32;

  1129 	tp->mii.phy_id = tp->phys[0];

  1130 

  1131 	/* The lower four bits are the media type. */

  1132 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1133 	if (option > 0) {

  1134 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1135 		tp->default_port = option & 0xFF;

  1136 		if (tp->default_port)