1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define DRV_NAME	"ec_8139too"

   130 #define DRV_VERSION	"0.9.28"

   131 

   132 

   133 #include <linux/module.h>

   134 #include <linux/kernel.h>

   135 #include <linux/compiler.h>

   136 #include <linux/pci.h>

   137 #include <linux/init.h>

   138 #include <linux/netdevice.h>

   139 #include <linux/etherdevice.h>

   140 #include <linux/rtnetlink.h>

   141 #include <linux/delay.h>

   142 #include <linux/ethtool.h>

   143 #include <linux/mii.h>

   144 #include <linux/completion.h>

   145 #include <linux/crc32.h>

   146 #include <linux/io.h>

   147 #include <linux/uaccess.h>

   148 #include <asm/irq.h>

   149 

   150 #include "../globals.h"

   151 #include "ecdev.h"

   152 

   153 #define RTL8139_DRIVER_NAME DRV_NAME \

   154                             " EtherCAT-capable Fast Ethernet driver " \

   155                             DRV_VERSION ", master " EC_MASTER_VERSION

   156 

   157 #define PFX DRV_NAME ": "

   158 

   159 /* Default Message level */

   160 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   161                                  NETIF_MSG_PROBE  | \

   162                                  NETIF_MSG_LINK)

   163 

   164 

   165 /* define to 1, 2 or 3 to enable copious debugging info */

   166 #define RTL8139_DEBUG 0

   167 

   168 /* define to 1 to disable lightweight runtime debugging checks */

   169 #undef RTL8139_NDEBUG

   170 

   171 

   172 #ifdef RTL8139_NDEBUG

   173 #  define assert(expr) do {} while (0)

   174 #else

   175 #  define assert(expr) \

   176         if(unlikely(!(expr))) {				        \

   177         pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   178 	#expr, __FILE__, __func__, __LINE__);			\

   179         }

   180 #endif

   181 

   182 

   183 /* A few user-configurable values. */

   184 /* media options */

   185 #define MAX_UNITS 8

   186 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   187 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   188 

   189 /* Whether to use MMIO or PIO. Default to MMIO. */

   190 #ifdef CONFIG_8139TOO_PIO

   191 static int use_io = 1;

   192 #else

   193 static int use_io = 0;

   194 #endif

   195 

   196 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   197    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   198 static int multicast_filter_limit = 32;

   199 

   200 /* bitmapped message enable number */

   201 static int debug = -1;

   202 

   203 /*

   204  * Receive ring size

   205  * Warning: 64K ring has hardware issues and may lock up.

   206  */

   207 #if defined(CONFIG_SH_DREAMCAST)

   208 #define RX_BUF_IDX 0	/* 8K ring */

   209 #else

   210 #define RX_BUF_IDX	2	/* 32K ring */

   211 #endif

   212 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   213 #define RX_BUF_PAD	16

   214 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   215 

   216 #if RX_BUF_LEN == 65536

   217 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   218 #else

   219 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   220 #endif

   221 

   222 /* Number of Tx descriptor registers. */

   223 #define NUM_TX_DESC	4

   224 

   225 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   226 #define MAX_ETH_FRAME_SIZE	1536

   227 

   228 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   229 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   230 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   231 

   232 /* PCI Tuning Parameters

   233    Threshold is bytes transferred to chip before transmission starts. */

   234 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   235 

   236 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   237 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   238 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   239 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   240 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   241 

   242 /* Operational parameters that usually are not changed. */

   243 /* Time in jiffies before concluding the transmitter is hung. */

   244 #define TX_TIMEOUT  (6*HZ)

   245 

   246 

   247 enum {

   248 	HAS_MII_XCVR = 0x010000,

   249 	HAS_CHIP_XCVR = 0x020000,

   250 	HAS_LNK_CHNG = 0x040000,

   251 };

   252 

   253 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   254 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   255 #define RTL_MIN_IO_SIZE 0x80

   256 #define RTL8139B_IO_SIZE 256

   257 

   258 #define RTL8129_CAPS	HAS_MII_XCVR

   259 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   260 

   261 typedef enum {

   262 	RTL8139 = 0,

   263 	RTL8129,

   264 } board_t;

   265 

   266 

   267 /* indexed by board_t, above */

   268 static const struct {

   269 	const char *name;

   270 	u32 hw_flags;

   271 } board_info[] __devinitdata = {

   272 	{ "RealTek RTL8139", RTL8139_CAPS },

   273 	{ "RealTek RTL8129", RTL8129_CAPS },

   274 };

   275 

   276 

   277 static struct pci_device_id rtl8139_pci_tbl[] = {

   278 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   279 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   280 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   281 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   282 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 

   298 #ifdef CONFIG_SH_SECUREEDGE5410

   299 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   300 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 #endif

   302 #ifdef CONFIG_8139TOO_8129

   303 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   304 #endif

   305 

   306 	/* some crazy cards report invalid vendor ids like

   307 	 * 0x0001 here.  The other ids are valid and constant,

   308 	 * so we simply don't match on the main vendor id.

   309 	 */

   310 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   311 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   312 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   313 

   314 	{0,}

   315 };

   316 

   317 /* prevent driver from being loaded automatically */

   318 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   319 

   320 static struct {

   321 	const char str[ETH_GSTRING_LEN];

   322 } ethtool_stats_keys[] = {

   323 	{ "early_rx" },

   324 	{ "tx_buf_mapped" },

   325 	{ "tx_timeouts" },

   326 	{ "rx_lost_in_ring" },

   327 };

   328 

   329 /* The rest of these values should never change. */

   330 

   331 /* Symbolic offsets to registers. */

   332 enum RTL8139_registers {

   333 	MAC0		= 0,	 /* Ethernet hardware address. */

   334 	MAR0		= 8,	 /* Multicast filter. */

   335 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   336 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   337 	RxBuf		= 0x30,

   338 	ChipCmd		= 0x37,

   339 	RxBufPtr	= 0x38,

   340 	RxBufAddr	= 0x3A,

   341 	IntrMask	= 0x3C,

   342 	IntrStatus	= 0x3E,

   343 	TxConfig	= 0x40,

   344 	RxConfig	= 0x44,

   345 	Timer		= 0x48,	 /* A general-purpose counter. */

   346 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   347 	Cfg9346		= 0x50,

   348 	Config0		= 0x51,

   349 	Config1		= 0x52,

   350 	TimerInt	= 0x54,

   351 	MediaStatus	= 0x58,

   352 	Config3		= 0x59,

   353 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   354 	HltClk		= 0x5B,

   355 	MultiIntr	= 0x5C,

   356 	TxSummary	= 0x60,

   357 	BasicModeCtrl	= 0x62,

   358 	BasicModeStatus	= 0x64,

   359 	NWayAdvert	= 0x66,

   360 	NWayLPAR	= 0x68,

   361 	NWayExpansion	= 0x6A,

   362 	/* Undocumented registers, but required for proper operation. */

   363 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   364 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   365 	PARA78		= 0x78,

   366 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   367 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   368 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   369 };

   370 

   371 enum ClearBitMasks {

   372 	MultiIntrClear	= 0xF000,

   373 	ChipCmdClear	= 0xE2,

   374 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   375 };

   376 

   377 enum ChipCmdBits {

   378 	CmdReset	= 0x10,

   379 	CmdRxEnb	= 0x08,

   380 	CmdTxEnb	= 0x04,

   381 	RxBufEmpty	= 0x01,

   382 };

   383 

   384 /* Interrupt register bits, using my own meaningful names. */

   385 enum IntrStatusBits {

   386 	PCIErr		= 0x8000,

   387 	PCSTimeout	= 0x4000,

   388 	RxFIFOOver	= 0x40,

   389 	RxUnderrun	= 0x20,

   390 	RxOverflow	= 0x10,

   391 	TxErr		= 0x08,

   392 	TxOK		= 0x04,

   393 	RxErr		= 0x02,

   394 	RxOK		= 0x01,

   395 

   396 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   397 };

   398 

   399 enum TxStatusBits {

   400 	TxHostOwns	= 0x2000,

   401 	TxUnderrun	= 0x4000,

   402 	TxStatOK	= 0x8000,

   403 	TxOutOfWindow	= 0x20000000,

   404 	TxAborted	= 0x40000000,

   405 	TxCarrierLost	= 0x80000000,

   406 };

   407 enum RxStatusBits {

   408 	RxMulticast	= 0x8000,

   409 	RxPhysical	= 0x4000,

   410 	RxBroadcast	= 0x2000,

   411 	RxBadSymbol	= 0x0020,

   412 	RxRunt		= 0x0010,

   413 	RxTooLong	= 0x0008,

   414 	RxCRCErr	= 0x0004,

   415 	RxBadAlign	= 0x0002,

   416 	RxStatusOK	= 0x0001,

   417 };

   418 

   419 /* Bits in RxConfig. */

   420 enum rx_mode_bits {

   421 	AcceptErr	= 0x20,

   422 	AcceptRunt	= 0x10,

   423 	AcceptBroadcast	= 0x08,

   424 	AcceptMulticast	= 0x04,

   425 	AcceptMyPhys	= 0x02,

   426 	AcceptAllPhys	= 0x01,

   427 };

   428 

   429 /* Bits in TxConfig. */

   430 enum tx_config_bits {

   431         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   432         TxIFGShift	= 24,

   433         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   434         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   435         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   436         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   437 

   438 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   439 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   440 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   441 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   442 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   443 

   444 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   445 };

   446 

   447 /* Bits in Config1 */

   448 enum Config1Bits {

   449 	Cfg1_PM_Enable	= 0x01,

   450 	Cfg1_VPD_Enable	= 0x02,

   451 	Cfg1_PIO	= 0x04,

   452 	Cfg1_MMIO	= 0x08,

   453 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   454 	Cfg1_Driver_Load = 0x20,

   455 	Cfg1_LED0	= 0x40,

   456 	Cfg1_LED1	= 0x80,

   457 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   458 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   459 };

   460 

   461 /* Bits in Config3 */

   462 enum Config3Bits {

   463 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   464 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   465 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   466 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   467 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   468 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   469 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   470 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   471 };

   472 

   473 /* Bits in Config4 */

   474 enum Config4Bits {

   475 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   476 };

   477 

   478 /* Bits in Config5 */

   479 enum Config5Bits {

   480 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   481 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   482 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   483 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   484 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   485 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   486 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   487 };

   488 

   489 enum RxConfigBits {

   490 	/* rx fifo threshold */

   491 	RxCfgFIFOShift	= 13,

   492 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   493 

   494 	/* Max DMA burst */

   495 	RxCfgDMAShift	= 8,

   496 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   497 

   498 	/* rx ring buffer length */

   499 	RxCfgRcv8K	= 0,

   500 	RxCfgRcv16K	= (1 << 11),

   501 	RxCfgRcv32K	= (1 << 12),

   502 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   503 

   504 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   505 	RxNoWrap	= (1 << 7),

   506 };

   507 

   508 /* Twister tuning parameters from RealTek.

   509    Completely undocumented, but required to tune bad links on some boards. */

   510 enum CSCRBits {

   511 	CSCR_LinkOKBit		= 0x0400,

   512 	CSCR_LinkChangeBit	= 0x0800,

   513 	CSCR_LinkStatusBits	= 0x0f000,

   514 	CSCR_LinkDownOffCmd	= 0x003c0,

   515 	CSCR_LinkDownCmd	= 0x0f3c0,

   516 };

   517 

   518 enum Cfg9346Bits {

   519 	Cfg9346_Lock	= 0x00,

   520 	Cfg9346_Unlock	= 0xC0,

   521 };

   522 

   523 typedef enum {

   524 	CH_8139	= 0,

   525 	CH_8139_K,

   526 	CH_8139A,

   527 	CH_8139A_G,

   528 	CH_8139B,

   529 	CH_8130,

   530 	CH_8139C,

   531 	CH_8100,

   532 	CH_8100B_8139D,

   533 	CH_8101,

   534 } chip_t;

   535 

   536 enum chip_flags {

   537 	HasHltClk	= (1 << 0),

   538 	HasLWake	= (1 << 1),

   539 };

   540 

   541 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   542 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   543 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   544 

   545 /* directly indexed by chip_t, above */

   546 static const struct {

   547 	const char *name;

   548 	u32 version; /* from RTL8139C/RTL8139D docs */

   549 	u32 flags;

   550 } rtl_chip_info[] = {

   551 	{ "RTL-8139",

   552 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   553 	  HasHltClk,

   554 	},

   555 

   556 	{ "RTL-8139 rev K",

   557 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   558 	  HasHltClk,

   559 	},

   560 

   561 	{ "RTL-8139A",

   562 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   563 	  HasHltClk, /* XXX undocumented? */

   564 	},

   565 

   566 	{ "RTL-8139A rev G",

   567 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   568 	  HasHltClk, /* XXX undocumented? */

   569 	},

   570 

   571 	{ "RTL-8139B",

   572 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   573 	  HasLWake,

   574 	},

   575 

   576 	{ "RTL-8130",

   577 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   578 	  HasLWake,

   579 	},

   580 

   581 	{ "RTL-8139C",

   582 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   583 	  HasLWake,

   584 	},

   585 

   586 	{ "RTL-8100",

   587 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   588  	  HasLWake,

   589  	},

   590 

   591 	{ "RTL-8100B/8139D",

   592 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   593 	  HasHltClk /* XXX undocumented? */

   594 	| HasLWake,

   595 	},

   596 

   597 	{ "RTL-8101",

   598 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   599 	  HasLWake,

   600 	},

   601 };

   602 

   603 struct rtl_extra_stats {

   604 	unsigned long early_rx;

   605 	unsigned long tx_buf_mapped;

   606 	unsigned long tx_timeouts;

   607 	unsigned long rx_lost_in_ring;

   608 };

   609 

   610 struct rtl8139_private {

   611 	void __iomem		*mmio_addr;

   612 	int			drv_flags;

   613 	struct pci_dev		*pci_dev;

   614 	u32			msg_enable;

   615 	struct napi_struct	napi;

   616 	struct net_device	*dev;

   617 

   618 	unsigned char		*rx_ring;

   619 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   620 	dma_addr_t		rx_ring_dma;

   621 

   622 	unsigned int		tx_flag;

   623 	unsigned long		cur_tx;

   624 	unsigned long		dirty_tx;

   625 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   626 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   627 	dma_addr_t		tx_bufs_dma;

   628 

   629 	signed char		phys[4];	/* MII device addresses. */

   630 

   631 				/* Twister tune state. */

   632 	char			twistie, twist_row, twist_col;

   633 

   634 	unsigned int		watchdog_fired : 1;

   635 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   636 	unsigned int		have_thread : 1;

   637 

   638 	spinlock_t		lock;

   639 	spinlock_t		rx_lock;

   640 

   641 	chip_t			chipset;

   642 	u32			rx_config;

   643 	struct rtl_extra_stats	xstats;

   644 

   645 	struct delayed_work	thread;

   646 

   647 	struct mii_if_info	mii;

   648 	unsigned int		regs_len;

   649 	unsigned long		fifo_copy_timeout;

   650     

   651 	ec_device_t *ecdev;

   652 };

   653 

   654 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   655 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   656 MODULE_LICENSE("GPL");

   657 MODULE_VERSION(EC_MASTER_VERSION);

   658 

   659 module_param(use_io, int, 0);

   660 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   661 module_param(multicast_filter_limit, int, 0);

   662 module_param_array(media, int, NULL, 0);

   663 module_param_array(full_duplex, int, NULL, 0);

   664 module_param(debug, int, 0);

   665 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   666 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   667 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   668 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   669 

   670 void ec_poll(struct net_device *);

   671 

   672 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   673 static int rtl8139_open (struct net_device *dev);

   674 static int mdio_read (struct net_device *dev, int phy_id, int location);

   675 static void mdio_write (struct net_device *dev, int phy_id, int location,

   676 			int val);

   677 static void rtl8139_start_thread(struct rtl8139_private *tp);

   678 static void rtl8139_tx_timeout (struct net_device *dev);

   679 static void rtl8139_init_ring (struct net_device *dev);

   680 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,

   681 				       struct net_device *dev);

   682 #ifdef CONFIG_NET_POLL_CONTROLLER

   683 static void rtl8139_poll_controller(struct net_device *dev);

   684 #endif

   685 static int rtl8139_set_mac_address(struct net_device *dev, void *p);

   686 static int rtl8139_poll(struct napi_struct *napi, int budget);

   687 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   688 static int rtl8139_close (struct net_device *dev);

   689 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   690 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   691 static void rtl8139_set_rx_mode (struct net_device *dev);

   692 static void __set_rx_mode (struct net_device *dev);

   693 static void rtl8139_hw_start (struct net_device *dev);

   694 static void rtl8139_thread (struct work_struct *work);

   695 static void rtl8139_tx_timeout_task(struct work_struct *work);

   696 static const struct ethtool_ops rtl8139_ethtool_ops;

   697 

   698 /* write MMIO register, with flush */

   699 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   700 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   701 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   702 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   703 

   704 /* write MMIO register */

   705 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   706 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   707 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   708 

   709 /* read MMIO register */

   710 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   711 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   712 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   713 

   714 

   715 static const u16 rtl8139_intr_mask =

   716 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   717 	TxErr | TxOK | RxErr | RxOK;

   718 

   719 static const u16 rtl8139_norx_intr_mask =

   720 	PCIErr | PCSTimeout | RxUnderrun |

   721 	TxErr | TxOK | RxErr ;

   722 

   723 #if RX_BUF_IDX == 0

   724 static const unsigned int rtl8139_rx_config =

   725 	RxCfgRcv8K | RxNoWrap |

   726 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   727 	(RX_DMA_BURST << RxCfgDMAShift);

   728 #elif RX_BUF_IDX == 1

   729 static const unsigned int rtl8139_rx_config =

   730 	RxCfgRcv16K | RxNoWrap |

   731 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   732 	(RX_DMA_BURST << RxCfgDMAShift);

   733 #elif RX_BUF_IDX == 2

   734 static const unsigned int rtl8139_rx_config =

   735 	RxCfgRcv32K | RxNoWrap |

   736 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   737 	(RX_DMA_BURST << RxCfgDMAShift);

   738 #elif RX_BUF_IDX == 3

   739 static const unsigned int rtl8139_rx_config =

   740 	RxCfgRcv64K |

   741 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   742 	(RX_DMA_BURST << RxCfgDMAShift);

   743 #else

   744 #error "Invalid configuration for 8139_RXBUF_IDX"

   745 #endif

   746 

   747 static const unsigned int rtl8139_tx_config =

   748 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   749 

   750 static void __rtl8139_cleanup_dev (struct net_device *dev)

   751 {

   752 	struct rtl8139_private *tp = netdev_priv(dev);

   753 	struct pci_dev *pdev;

   754 

   755 	assert (dev != NULL);

   756 	assert (tp->pci_dev != NULL);

   757 	pdev = tp->pci_dev;

   758 

   759 	if (tp->mmio_addr)

   760 		pci_iounmap (pdev, tp->mmio_addr);

   761 

   762 	/* it's ok to call this even if we have no regions to free */

   763 	pci_release_regions (pdev);

   764 

   765 	free_netdev(dev);

   766 	pci_set_drvdata (pdev, NULL);

   767 }

   768 

   769 

   770 static void rtl8139_chip_reset (void __iomem *ioaddr)

   771 {

   772 	int i;

   773 

   774 	/* Soft reset the chip. */

   775 	RTL_W8 (ChipCmd, CmdReset);

   776 

   777 	/* Check that the chip has finished the reset. */

   778 	for (i = 1000; i > 0; i--) {

   779 		barrier();

   780 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   781 			break;

   782 		udelay (10);

   783 	}

   784 }

   785 

   786 

   787 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)

   788 {

   789 	void __iomem *ioaddr;

   790 	struct net_device *dev;

   791 	struct rtl8139_private *tp;

   792 	u8 tmp8;

   793 	int rc, disable_dev_on_err = 0;

   794 	unsigned int i;

   795 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   796 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   797 	u32 version;

   798 

   799 	assert (pdev != NULL);

   800 

   801 	/* dev and priv zeroed in alloc_etherdev */

   802 	dev = alloc_etherdev (sizeof (*tp));

   803 	if (dev == NULL) {

   804 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   805 		return ERR_PTR(-ENOMEM);

   806 	}

   807 	SET_NETDEV_DEV(dev, &pdev->dev);

   808 

   809 	tp = netdev_priv(dev);

   810 	tp->pci_dev = pdev;

   811 

   812 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   813 	rc = pci_enable_device (pdev);

   814 	if (rc)

   815 		goto err_out;

   816 

   817 	pio_start = pci_resource_start (pdev, 0);

   818 	pio_end = pci_resource_end (pdev, 0);

   819 	pio_flags = pci_resource_flags (pdev, 0);

   820 	pio_len = pci_resource_len (pdev, 0);

   821 

   822 	mmio_start = pci_resource_start (pdev, 1);

   823 	mmio_end = pci_resource_end (pdev, 1);

   824 	mmio_flags = pci_resource_flags (pdev, 1);

   825 	mmio_len = pci_resource_len (pdev, 1);

   826 

   827 	/* set this immediately, we need to know before

   828 	 * we talk to the chip directly */

   829 	pr_debug("PIO region size == 0x%02lX\n", pio_len);

   830 	pr_debug("MMIO region size == 0x%02lX\n", mmio_len);

   831 

   832 retry:

   833 	if (use_io) {

   834 		/* make sure PCI base addr 0 is PIO */

   835 		if (!(pio_flags & IORESOURCE_IO)) {

   836 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   837 			rc = -ENODEV;

   838 			goto err_out;

   839 		}

   840 		/* check for weird/broken PCI region reporting */

   841 		if (pio_len < RTL_MIN_IO_SIZE) {

   842 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   843 			rc = -ENODEV;

   844 			goto err_out;

   845 		}

   846 	} else {

   847 		/* make sure PCI base addr 1 is MMIO */

   848 		if (!(mmio_flags & IORESOURCE_MEM)) {

   849 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   850 			rc = -ENODEV;

   851 			goto err_out;

   852 		}

   853 		if (mmio_len < RTL_MIN_IO_SIZE) {

   854 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   855 			rc = -ENODEV;

   856 			goto err_out;

   857 		}

   858 	}

   859 

   860 	rc = pci_request_regions (pdev, DRV_NAME);

   861 	if (rc)

   862 		goto err_out;

   863 	disable_dev_on_err = 1;

   864 

   865 	/* enable PCI bus-mastering */

   866 	pci_set_master (pdev);

   867 

   868 	if (use_io) {

   869 		ioaddr = pci_iomap(pdev, 0, 0);

   870 		if (!ioaddr) {

   871 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   872 			rc = -EIO;

   873 			goto err_out;

   874 		}

   875 		dev->base_addr = pio_start;

   876 		tp->regs_len = pio_len;

   877 	} else {

   878 		/* ioremap MMIO region */

   879 		ioaddr = pci_iomap(pdev, 1, 0);

   880 		if (ioaddr == NULL) {

   881 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   882 			pci_release_regions(pdev);

   883 			use_io = 1;

   884 			goto retry;

   885 		}

   886 		dev->base_addr = (long) ioaddr;

   887 		tp->regs_len = mmio_len;

   888 	}

   889 	tp->mmio_addr = ioaddr;

   890 

   891 	/* Bring old chips out of low-power mode. */

   892 	RTL_W8 (HltClk, 'R');

   893 

   894 	/* check for missing/broken hardware */

   895 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   896 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   897 		rc = -EIO;

   898 		goto err_out;

   899 	}

   900 

   901 	/* identify chip attached to board */

   902 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   903 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   904 		if (version == rtl_chip_info[i].version) {

   905 			tp->chipset = i;

   906 			goto match;

   907 		}

   908 

   909 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   910 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");

   911 	dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   912 	tp->chipset = 0;

   913 

   914 match:

   915 	pr_debug("chipset id (%d) == index %d, '%s'\n",

   916 		 version, i, rtl_chip_info[i].name);

   917 

   918 	if (tp->chipset >= CH_8139B) {

   919 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   920 		pr_debug("PCI PM wakeup\n");

   921 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   922 		    (tmp8 & LWAKE))

   923 			new_tmp8 &= ~LWAKE;

   924 		new_tmp8 |= Cfg1_PM_Enable;

   925 		if (new_tmp8 != tmp8) {

   926 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   927 			RTL_W8 (Config1, tmp8);

   928 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   929 		}

   930 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   931 			tmp8 = RTL_R8 (Config4);

   932 			if (tmp8 & LWPTN) {

   933 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   934 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   935 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   936 			}

   937 		}

   938 	} else {

   939 		pr_debug("Old chip wakeup\n");

   940 		tmp8 = RTL_R8 (Config1);

   941 		tmp8 &= ~(SLEEP | PWRDN);

   942 		RTL_W8 (Config1, tmp8);

   943 	}

   944 

   945 	rtl8139_chip_reset (ioaddr);

   946 

   947 	return dev;

   948 

   949 err_out:

   950 	__rtl8139_cleanup_dev (dev);

   951 	if (disable_dev_on_err)

   952 		pci_disable_device (pdev);

   953 	return ERR_PTR(rc);

   954 }

   955 

   956 static const struct net_device_ops rtl8139_netdev_ops = {

   957 	.ndo_open		= rtl8139_open,

   958 	.ndo_stop		= rtl8139_close,

   959 	.ndo_get_stats		= rtl8139_get_stats,

   960 	.ndo_change_mtu		= eth_change_mtu,

   961 	.ndo_validate_addr	= eth_validate_addr,

   962 	.ndo_set_mac_address 	= rtl8139_set_mac_address,

   963 	.ndo_start_xmit		= rtl8139_start_xmit,

   964 	.ndo_set_multicast_list	= rtl8139_set_rx_mode,

   965 	.ndo_do_ioctl		= netdev_ioctl,

   966 	.ndo_tx_timeout		= rtl8139_tx_timeout,

   967 #ifdef CONFIG_NET_POLL_CONTROLLER

   968 	.ndo_poll_controller	= rtl8139_poll_controller,

   969 #endif

   970 };

   971 

   972 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   973 				       const struct pci_device_id *ent)

   974 {

   975 	struct net_device *dev = NULL;

   976 	struct rtl8139_private *tp;

   977 	int i, addr_len, option;

   978 	void __iomem *ioaddr;

   979 	static int board_idx = -1;

   980 

   981 	assert (pdev != NULL);

   982 	assert (ent != NULL);

   983 

   984 	board_idx++;

   985 

   986 	/* when we're built into the kernel, the driver version message

   987 	 * is only printed if at least one 8139 board has been found

   988 	 */

   989 #ifndef MODULE

   990 	{

   991 		static int printed_version;

   992 		if (!printed_version++)

   993 			pr_info(RTL8139_DRIVER_NAME "\n");

   994 	}

   995 #endif

   996 

   997 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

   998 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

   999 		dev_info(&pdev->dev,

  1000 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1001 		       	   pdev->vendor, pdev->device, pdev->revision);

  1002 		return -ENODEV;

  1003 	}

  1004 

  1005 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1006 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1007 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1008 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1009 		pr_info("8139too: OQO Model 2 detected. Forcing PIO\n");

  1010 		use_io = 1;

  1011 	}

  1012 

  1013 	dev = rtl8139_init_board (pdev);

  1014 	if (IS_ERR(dev))

  1015 		return PTR_ERR(dev);

  1016 

  1017 	assert (dev != NULL);

  1018 	tp = netdev_priv(dev);

  1019 	tp->dev = dev;

  1020 

  1021 	ioaddr = tp->mmio_addr;

  1022 	assert (ioaddr != NULL);

  1023 

  1024 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1025 	for (i = 0; i < 3; i++)

  1026 		((__le16 *) (dev->dev_addr))[i] =

  1027 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1028 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1029 

  1030 	/* The Rtl8139-specific entries in the device structure. */

  1031 	dev->netdev_ops = &rtl8139_netdev_ops;

  1032 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1033 	dev->watchdog_timeo = TX_TIMEOUT;

  1034 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1035 

  1036 	/* note: the hardware is not capable of sg/csum/highdma, however

  1037 	 * through the use of skb_copy_and_csum_dev we enable these

  1038 	 * features

  1039 	 */

  1040 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1041 

  1042 	dev->irq = pdev->irq;

  1043 

  1044 	/* tp zeroed and aligned in alloc_etherdev */

  1045 	tp = netdev_priv(dev);

  1046 

  1047 	/* note: tp->chipset set in rtl8139_init_board */

  1048 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1049 	tp->mmio_addr = ioaddr;

  1050 	tp->msg_enable =

  1051 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1052 	spin_lock_init (&tp->lock);

  1053 	spin_lock_init (&tp->rx_lock);

  1054 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1055 	tp->mii.dev = dev;

  1056 	tp->mii.mdio_read = mdio_read;

  1057 	tp->mii.mdio_write = mdio_write;

  1058 	tp->mii.phy_id_mask = 0x3f;

  1059 	tp->mii.reg_num_mask = 0x1f;

  1060 

  1061 	/* dev is fully set up and ready to use now */

  1062 	// offer device to EtherCAT master module

  1063 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1064 

  1065 	if (!tp->ecdev) {

  1066 		pr_debug("about to register device named %s (%p)...\n", dev->name, dev);

  1067 		i = register_netdev (dev);

  1068 		if (i) goto err_out;

  1069 	}

  1070 

  1071 	pci_set_drvdata (pdev, dev);

  1072 

  1073 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",

  1074 		dev->name,

  1075 		board_info[ent->driver_data].name,

  1076 		dev->base_addr,

  1077 		dev->dev_addr,

  1078 		dev->irq);

  1079 

  1080 	pr_debug("%s:  Identified 8139 chip type '%s'\n",

  1081 		dev->name, rtl_chip_info[tp->chipset].name);

  1082 

  1083 	/* Find the connected MII xcvrs.

  1084 	   Doing this in open() would allow detecting external xcvrs later, but

  1085 	   takes too much time. */

  1086 #ifdef CONFIG_8139TOO_8129

  1087 	if (tp->drv_flags & HAS_MII_XCVR) {

  1088 		int phy, phy_idx = 0;

  1089 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1090 			int mii_status = mdio_read(dev, phy, 1);

  1091 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1092 				u16 advertising = mdio_read(dev, phy, 4);

  1093 				tp->phys[phy_idx++] = phy;

  1094 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",

  1095 					   dev->name, phy, mii_status, advertising);

  1096 			}

  1097 		}

  1098 		if (phy_idx == 0) {

  1099 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",

  1100 				   dev->name);

  1101 			tp->phys[0] = 32;

  1102 		}

  1103 	} else

  1104 #endif

  1105 		tp->phys[0] = 32;

  1106 	tp->mii.phy_id = tp->phys[0];

  1107 

  1108 	/* The lower four bits are the media type. */

  1109 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1110 	if (option > 0) {

  1111 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1112 		tp->default_port = option & 0xFF;

  1113 		if (tp->default_port)

  1114 			tp->mii.force_media = 1;

  1115 	}

  1116 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1117 		tp->mii.full_duplex = full_duplex[board_idx];

  1118 	if (tp->mii.full_duplex) {

  1119 		pr_info("%s: Media type forced to Full Duplex.\n", dev->name);

  1120 		/* Changing the MII-advertised media because might prevent

  1121 		   re-connection. */

  1122 		tp->mii.force_media = 1;

  1123 	}

  1124 	if (tp->default_port) {

  1125 		pr_info("  Forcing %dMbps %s-duplex operation.\n",

  1126 			   (option & 0x20 ? 100 : 10),

  1127 			   (option & 0x10 ? "full" : "half"));

  1128 		mdio_write(dev, tp->phys[0], 0,

  1129 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */

  1130 				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */

  1131 	}

  1132 

  1133 	/* Put the chip into low-power mode. */

  1134 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)

  1135 		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */

  1136