1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2007-2008  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *  ---

    29  *

    30  *  vim: noexpandtab

    31  *

    32  *****************************************************************************/

    33 

    34 /**

    35    \file

    36    EtherCAT driver for e100-compatible NICs.

    37 */

    38 

    39 /* Former documentation: */

    40 

    41 /*******************************************************************************

    42 

    43   Intel PRO/100 Linux driver

    44   Copyright(c) 1999 - 2006 Intel Corporation.

    45 

    46   This program is free software; you can redistribute it and/or modify it

    47   under the terms and conditions of the GNU General Public License,

    48   version 2, as published by the Free Software Foundation.

    49 

    50   This program is distributed in the hope it will be useful, but WITHOUT

    51   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    52   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    53   more details.

    54 

    55   You should have received a copy of the GNU General Public License along with

    56   this program; if not, write to the Free Software Foundation, Inc.,

    57   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    58 

    59   The full GNU General Public License is included in this distribution in

    60   the file called "COPYING".

    61 

    62   Contact Information:

    63   Linux NICS <linux.nics@intel.com>

    64   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    65   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    66 

    67 *******************************************************************************/

    68 

    69 /*

    70  *	e100.c: Intel(R) PRO/100 ethernet driver

    71  *

    72  *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    73  *	original e100 driver, but better described as a munging of

    74  *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    75  *

    76  *	References:

    77  *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    78  *		Open Source Software Developers Manual,

    79  *		http://sourceforge.net/projects/e1000

    80  *

    81  *

    82  *	                      Theory of Operation

    83  *

    84  *	I.   General

    85  *

    86  *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    87  *	controller family, which includes the 82557, 82558, 82559, 82550,

    88  *	82551, and 82562 devices.  82558 and greater controllers

    89  *	integrate the Intel 82555 PHY.  The controllers are used in

    90  *	server and client network interface cards, as well as in

    91  *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    92  *	configurations.  8255x supports a 32-bit linear addressing

    93  *	mode and operates at 33Mhz PCI clock rate.

    94  *

    95  *	II.  Driver Operation

    96  *

    97  *	Memory-mapped mode is used exclusively to access the device's

    98  *	shared-memory structure, the Control/Status Registers (CSR). All

    99  *	setup, configuration, and control of the device, including queuing

   100  *	of Tx, Rx, and configuration commands is through the CSR.

   101  *	cmd_lock serializes accesses to the CSR command register.  cb_lock

   102  *	protects the shared Command Block List (CBL).

   103  *

   104  *	8255x is highly MII-compliant and all access to the PHY go

   105  *	through the Management Data Interface (MDI).  Consequently, the

   106  *	driver leverages the mii.c library shared with other MII-compliant

   107  *	devices.

   108  *

   109  *	Big- and Little-Endian byte order as well as 32- and 64-bit

   110  *	archs are supported.  Weak-ordered memory and non-cache-coherent

   111  *	archs are supported.

   112  *

   113  *	III. Transmit

   114  *

   115  *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

   116  *	together in a fixed-size ring (CBL) thus forming the flexible mode

   117  *	memory structure.  A TCB marked with the suspend-bit indicates

   118  *	the end of the ring.  The last TCB processed suspends the

   119  *	controller, and the controller can be restarted by issue a CU

   120  *	resume command to continue from the suspend point, or a CU start

   121  *	command to start at a given position in the ring.

   122  *

   123  *	Non-Tx commands (config, multicast setup, etc) are linked

   124  *	into the CBL ring along with Tx commands.  The common structure

   125  *	used for both Tx and non-Tx commands is the Command Block (CB).

   126  *

   127  *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

   128  *	is the next CB to check for completion; cb_to_send is the first

   129  *	CB to start on in case of a previous failure to resume.  CB clean

   130  *	up happens in interrupt context in response to a CU interrupt.

   131  *	cbs_avail keeps track of number of free CB resources available.

   132  *

   133  * 	Hardware padding of short packets to minimum packet size is

   134  * 	enabled.  82557 pads with 7Eh, while the later controllers pad

   135  * 	with 00h.

   136  *

   137  *	IV.  Receive

   138  *

   139  *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   140  *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   141  *	memory structure.  Rx skbs are allocated to contain both the RFD

   142  *	and the data buffer, but the RFD is pulled off before the skb is

   143  *	indicated.  The data buffer is aligned such that encapsulated

   144  *	protocol headers are u32-aligned.  Since the RFD is part of the

   145  *	mapped shared memory, and completion status is contained within

   146  *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   147  *	view from software and hardware.

   148  *

   149  *	In order to keep updates to the RFD link field from colliding with

   150  *	hardware writes to mark packets complete, we use the feature that

   151  *	hardware will not write to a size 0 descriptor and mark the previous

   152  *	packet as end-of-list (EL).   After updating the link, we remove EL

   153  *	and only then restore the size such that hardware may use the

   154  *	previous-to-end RFD.

   155  *

   156  *	Under typical operation, the  receive unit (RU) is start once,

   157  *	and the controller happily fills RFDs as frames arrive.  If

   158  *	replacement RFDs cannot be allocated, or the RU goes non-active,

   159  *	the RU must be restarted.  Frame arrival generates an interrupt,

   160  *	and Rx indication and re-allocation happen in the same context,

   161  *	therefore no locking is required.  A software-generated interrupt

   162  *	is generated from the watchdog to recover from a failed allocation

   163  *	scenario where all Rx resources have been indicated and none re-

   164  *	placed.

   165  *

   166  *	V.   Miscellaneous

   167  *

   168  * 	VLAN offloading of tagging, stripping and filtering is not

   169  * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   170  * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   171  * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   172  * 	not supported (hardware limitation).

   173  *

   174  * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   175  *

   176  * 	Thanks to JC (jchapman@katalix.com) for helping with

   177  * 	testing/troubleshooting the development driver.

   178  *

   179  * 	TODO:

   180  * 	o several entry points race with dev->close

   181  * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   182  *

   183  *	FIXES:

   184  * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   185  *	- Stratus87247: protect MDI control register manipulations

   186  */

   187 

   188 #include <linux/module.h>

   189 #include <linux/moduleparam.h>

   190 #include <linux/kernel.h>

   191 #include <linux/types.h>

   192 #include <linux/slab.h>

   193 #include <linux/delay.h>

   194 #include <linux/init.h>

   195 #include <linux/pci.h>

   196 #include <linux/dma-mapping.h>

   197 #include <linux/netdevice.h>

   198 #include <linux/etherdevice.h>

   199 #include <linux/mii.h>

   200 #include <linux/if_vlan.h>

   201 #include <linux/skbuff.h>

   202 #include <linux/ethtool.h>

   203 #include <linux/string.h>

   204 #include <asm/unaligned.h>

   205 

   206 // EtherCAT includes

   207 #include "../globals.h"

   208 #include "ecdev.h"

   209 

   210 #define DRV_NAME		"ec_e100"

   211 

   212 #define DRV_EXT			"-NAPI"

   213 #define DRV_VERSION		"3.5.23-k6"DRV_EXT

   214 #define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

   215 #define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"

   216 #define PFX			DRV_NAME ": "

   217 

   218 #define E100_WATCHDOG_PERIOD	(2 * HZ)

   219 #define E100_NAPI_WEIGHT	16

   220 

   221 MODULE_DESCRIPTION(DRV_DESCRIPTION);

   222 MODULE_AUTHOR(DRV_COPYRIGHT);

   223 MODULE_LICENSE("GPL");

   224 MODULE_VERSION(DRV_VERSION);

   225 

   226 MODULE_DESCRIPTION(DRV_DESCRIPTION);

   227 MODULE_AUTHOR("Mario Witkowski <mario.witkowski@w4systems.de>");

   228 MODULE_LICENSE("GPL");

   229 MODULE_VERSION(DRV_VERSION ", master " EC_MASTER_VERSION);

   230 

   231 void e100_ec_poll(struct net_device *);

   232 

   233 static int debug = 3;

   234 static int eeprom_bad_csum_allow = 0;

   235 static int use_io = 0;

   236 module_param(debug, int, 0);

   237 module_param(eeprom_bad_csum_allow, int, 0);

   238 module_param(use_io, int, 0);

   239 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   240 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   241 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");

   242 #define DPRINTK(nlevel, klevel, fmt, args...) \

   243 	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   244 	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   245 		__func__ , ## args))

   246 

   247 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   248 	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   249 	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   250 static struct pci_device_id e100_id_table[] = {

   251 	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   252 	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   253 	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   254 	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   255 	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   256 	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   257 	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   258 	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   259 	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   260 	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   261 	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   262 	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   263 	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   264 	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   265 	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   266 	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   267 	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   268 	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   269 	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   270 	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   271 	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   272 	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   273 	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   274 	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   275 	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   276 	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   277 	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   278 	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   279 	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   280 	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   281 	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   282 	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   283 	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   284 	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   285 	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   286 	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   287 	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   288 	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   289 	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   290 	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   291 	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   292 	{ 0, }

   293 };

   294 

   295 // prevent from being loaded automatically

   296 //MODULE_DEVICE_TABLE(pci, e100_id_table);

   297 

   298 enum mac {

   299 	mac_82557_D100_A  = 0,

   300 	mac_82557_D100_B  = 1,

   301 	mac_82557_D100_C  = 2,

   302 	mac_82558_D101_A4 = 4,

   303 	mac_82558_D101_B0 = 5,

   304 	mac_82559_D101M   = 8,

   305 	mac_82559_D101S   = 9,

   306 	mac_82550_D102    = 12,

   307 	mac_82550_D102_C  = 13,

   308 	mac_82551_E       = 14,

   309 	mac_82551_F       = 15,

   310 	mac_82551_10      = 16,

   311 	mac_unknown       = 0xFF,

   312 };

   313 

   314 enum phy {

   315 	phy_100a     = 0x000003E0,

   316 	phy_100c     = 0x035002A8,

   317 	phy_82555_tx = 0x015002A8,

   318 	phy_nsc_tx   = 0x5C002000,

   319 	phy_82562_et = 0x033002A8,

   320 	phy_82562_em = 0x032002A8,

   321 	phy_82562_ek = 0x031002A8,

   322 	phy_82562_eh = 0x017002A8,

   323 	phy_unknown  = 0xFFFFFFFF,

   324 };

   325 

   326 /* CSR (Control/Status Registers) */

   327 struct csr {

   328 	struct {

   329 		u8 status;

   330 		u8 stat_ack;

   331 		u8 cmd_lo;

   332 		u8 cmd_hi;

   333 		u32 gen_ptr;

   334 	} scb;

   335 	u32 port;

   336 	u16 flash_ctrl;

   337 	u8 eeprom_ctrl_lo;

   338 	u8 eeprom_ctrl_hi;

   339 	u32 mdi_ctrl;

   340 	u32 rx_dma_count;

   341 };

   342 

   343 enum scb_status {

   344 	rus_no_res       = 0x08,

   345 	rus_ready        = 0x10,

   346 	rus_mask         = 0x3C,

   347 };

   348 

   349 enum ru_state  {

   350 	RU_SUSPENDED = 0,

   351 	RU_RUNNING	 = 1,

   352 	RU_UNINITIALIZED = -1,

   353 };

   354 

   355 enum scb_stat_ack {

   356 	stat_ack_not_ours    = 0x00,

   357 	stat_ack_sw_gen      = 0x04,

   358 	stat_ack_rnr         = 0x10,

   359 	stat_ack_cu_idle     = 0x20,

   360 	stat_ack_frame_rx    = 0x40,

   361 	stat_ack_cu_cmd_done = 0x80,

   362 	stat_ack_not_present = 0xFF,

   363 	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   364 	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   365 };

   366 

   367 enum scb_cmd_hi {

   368 	irq_mask_none = 0x00,

   369 	irq_mask_all  = 0x01,

   370 	irq_sw_gen    = 0x02,

   371 };

   372 

   373 enum scb_cmd_lo {

   374 	cuc_nop        = 0x00,

   375 	ruc_start      = 0x01,

   376 	ruc_load_base  = 0x06,

   377 	cuc_start      = 0x10,

   378 	cuc_resume     = 0x20,

   379 	cuc_dump_addr  = 0x40,

   380 	cuc_dump_stats = 0x50,

   381 	cuc_load_base  = 0x60,

   382 	cuc_dump_reset = 0x70,

   383 };

   384 

   385 enum cuc_dump {

   386 	cuc_dump_complete       = 0x0000A005,

   387 	cuc_dump_reset_complete = 0x0000A007,

   388 };

   389 

   390 enum port {

   391 	software_reset  = 0x0000,

   392 	selftest        = 0x0001,

   393 	selective_reset = 0x0002,

   394 };

   395 

   396 enum eeprom_ctrl_lo {

   397 	eesk = 0x01,

   398 	eecs = 0x02,

   399 	eedi = 0x04,

   400 	eedo = 0x08,

   401 };

   402 

   403 enum mdi_ctrl {

   404 	mdi_write = 0x04000000,

   405 	mdi_read  = 0x08000000,

   406 	mdi_ready = 0x10000000,

   407 };

   408 

   409 enum eeprom_op {

   410 	op_write = 0x05,

   411 	op_read  = 0x06,

   412 	op_ewds  = 0x10,

   413 	op_ewen  = 0x13,

   414 };

   415 

   416 enum eeprom_offsets {

   417 	eeprom_cnfg_mdix  = 0x03,

   418 	eeprom_id         = 0x0A,

   419 	eeprom_config_asf = 0x0D,

   420 	eeprom_smbus_addr = 0x90,

   421 };

   422 

   423 enum eeprom_cnfg_mdix {

   424 	eeprom_mdix_enabled = 0x0080,

   425 };

   426 

   427 enum eeprom_id {

   428 	eeprom_id_wol = 0x0020,

   429 };

   430 

   431 enum eeprom_config_asf {

   432 	eeprom_asf = 0x8000,

   433 	eeprom_gcl = 0x4000,

   434 };

   435 

   436 enum cb_status {

   437 	cb_complete = 0x8000,

   438 	cb_ok       = 0x2000,

   439 };

   440 

   441 enum cb_command {

   442 	cb_nop    = 0x0000,

   443 	cb_iaaddr = 0x0001,

   444 	cb_config = 0x0002,

   445 	cb_multi  = 0x0003,

   446 	cb_tx     = 0x0004,

   447 	cb_ucode  = 0x0005,

   448 	cb_dump   = 0x0006,

   449 	cb_tx_sf  = 0x0008,

   450 	cb_cid    = 0x1f00,

   451 	cb_i      = 0x2000,

   452 	cb_s      = 0x4000,

   453 	cb_el     = 0x8000,

   454 };

   455 

   456 struct rfd {

   457 	__le16 status;

   458 	__le16 command;

   459 	__le32 link;

   460 	__le32 rbd;

   461 	__le16 actual_size;

   462 	__le16 size;

   463 };

   464 

   465 struct rx {

   466 	struct rx *next, *prev;

   467 	struct sk_buff *skb;

   468 	dma_addr_t dma_addr;

   469 };

   470 

   471 #if defined(__BIG_ENDIAN_BITFIELD)

   472 #define X(a,b)	b,a

   473 #else

   474 #define X(a,b)	a,b

   475 #endif

   476 struct config {

   477 /*0*/	u8 X(byte_count:6, pad0:2);

   478 /*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   479 /*2*/	u8 adaptive_ifs;

   480 /*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   481 	   term_write_cache_line:1), pad3:4);

   482 /*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   483 /*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   484 /*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   485 	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   486 	   rx_discard_overruns:1), rx_save_bad_frames:1);

   487 /*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   488 	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   489 	   tx_dynamic_tbd:1);

   490 /*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   491 /*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   492 	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   493 /*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   494 	   loopback:2);

   495 /*11*/	u8 X(linear_priority:3, pad11:5);

   496 /*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   497 /*13*/	u8 ip_addr_lo;

   498 /*14*/	u8 ip_addr_hi;

   499 /*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   500 	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   501 	   pad15_2:1), crs_or_cdt:1);

   502 /*16*/	u8 fc_delay_lo;

   503 /*17*/	u8 fc_delay_hi;

   504 /*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   505 	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   506 /*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   507 	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   508 	   full_duplex_force:1), full_duplex_pin:1);

   509 /*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   510 /*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   511 /*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   512 	u8 pad_d102[9];

   513 };

   514 

   515 #define E100_MAX_MULTICAST_ADDRS	64

   516 struct multi {

   517 	__le16 count;

   518 	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   519 };

   520 

   521 /* Important: keep total struct u32-aligned */

   522 #define UCODE_SIZE			134

   523 struct cb {

   524 	__le16 status;

   525 	__le16 command;

   526 	__le32 link;

   527 	union {

   528 		u8 iaaddr[ETH_ALEN];

   529 		__le32 ucode[UCODE_SIZE];

   530 		struct config config;

   531 		struct multi multi;

   532 		struct {

   533 			u32 tbd_array;

   534 			u16 tcb_byte_count;

   535 			u8 threshold;

   536 			u8 tbd_count;

   537 			struct {

   538 				__le32 buf_addr;

   539 				__le16 size;

   540 				u16 eol;

   541 			} tbd;

   542 		} tcb;

   543 		__le32 dump_buffer_addr;

   544 	} u;

   545 	struct cb *next, *prev;

   546 	dma_addr_t dma_addr;

   547 	struct sk_buff *skb;

   548 };

   549 

   550 enum loopback {

   551 	lb_none = 0, lb_mac = 1, lb_phy = 3,

   552 };

   553 

   554 struct stats {

   555 	__le32 tx_good_frames, tx_max_collisions, tx_late_collisions,

   556 		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,

   557 		tx_multiple_collisions, tx_total_collisions;

   558 	__le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,

   559 		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,

   560 		rx_short_frame_errors;

   561 	__le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;

   562 	__le16 xmt_tco_frames, rcv_tco_frames;

   563 	__le32 complete;

   564 };

   565 

   566 struct mem {

   567 	struct {

   568 		u32 signature;

   569 		u32 result;

   570 	} selftest;

   571 	struct stats stats;

   572 	u8 dump_buf[596];

   573 };

   574 

   575 struct param_range {

   576 	u32 min;

   577 	u32 max;

   578 	u32 count;

   579 };

   580 

   581 struct params {

   582 	struct param_range rfds;

   583 	struct param_range cbs;

   584 };

   585 

   586 struct nic {

   587 	/* Begin: frequently used values: keep adjacent for cache effect */

   588 	u32 msg_enable				____cacheline_aligned;

   589 	struct net_device *netdev;

   590 	struct pci_dev *pdev;

   591 

   592 	struct rx *rxs				____cacheline_aligned;

   593 	struct rx *rx_to_use;

   594 	struct rx *rx_to_clean;

   595 	struct rfd blank_rfd;

   596 	enum ru_state ru_running;

   597 

   598 	spinlock_t cb_lock			____cacheline_aligned;

   599 	spinlock_t cmd_lock;

   600 	struct csr __iomem *csr;

   601 	enum scb_cmd_lo cuc_cmd;

   602 	unsigned int cbs_avail;

   603 	struct napi_struct napi;

   604 	struct cb *cbs;

   605 	struct cb *cb_to_use;

   606 	struct cb *cb_to_send;

   607 	struct cb *cb_to_clean;

   608 	__le16 tx_command;

   609 	/* End: frequently used values: keep adjacent for cache effect */

   610 

   611 	enum {

   612 		ich                = (1 << 0),

   613 		promiscuous        = (1 << 1),

   614 		multicast_all      = (1 << 2),

   615 		wol_magic          = (1 << 3),

   616 		ich_10h_workaround = (1 << 4),

   617 	} flags					____cacheline_aligned;

   618 

   619 	enum mac mac;

   620 	enum phy phy;

   621 	struct params params;

   622 	struct timer_list watchdog;

   623 	struct timer_list blink_timer;

   624 	struct mii_if_info mii;

   625 	struct work_struct tx_timeout_task;

   626 	enum loopback loopback;

   627 

   628 	struct mem *mem;

   629 	dma_addr_t dma_addr;

   630 

   631 	dma_addr_t cbs_dma_addr;

   632 	u8 adaptive_ifs;

   633 	u8 tx_threshold;

   634 	u32 tx_frames;

   635 	u32 tx_collisions;

   636 	u32 tx_deferred;

   637 	u32 tx_single_collisions;

   638 	u32 tx_multiple_collisions;

   639 	u32 tx_fc_pause;

   640 	u32 tx_tco_frames;

   641 

   642 	u32 rx_fc_pause;

   643 	u32 rx_fc_unsupported;

   644 	u32 rx_tco_frames;

   645 	u32 rx_over_length_errors;

   646 

   647 	u16 leds;

   648 	u16 eeprom_wc;

   649 	__le16 eeprom[256];

   650 	spinlock_t mdio_lock;

   651 

   652 	ec_device_t *ecdev;

   653 	unsigned long ec_watchdog_jiffies;

   654 };

   655 

   656 static inline void e100_write_flush(struct nic *nic)

   657 {

   658 	/* Flush previous PCI writes through intermediate bridges

   659 	 * by doing a benign read */

   660 	(void)ioread8(&nic->csr->scb.status);

   661 }

   662 

   663 static void e100_enable_irq(struct nic *nic)

   664 {

   665 	unsigned long flags;

   666 

   667 	if (nic->ecdev)

   668 		return;

   669 

   670 	spin_lock_irqsave(&nic->cmd_lock, flags);

   671 	iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);

   672 	e100_write_flush(nic);

   673 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   674 }

   675 

   676 static void e100_disable_irq(struct nic *nic)

   677 {

   678 	unsigned long flags = 0;

   679 

   680 	if (!nic->ecdev)

   681 		spin_lock_irqsave(&nic->cmd_lock, flags);

   682 	iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);

   683 	e100_write_flush(nic);

   684 	if (!nic->ecdev)

   685 		spin_unlock_irqrestore(&nic->cmd_lock, flags);

   686 }

   687 

   688 static void e100_hw_reset(struct nic *nic)

   689 {

   690 	/* Put CU and RU into idle with a selective reset to get

   691 	 * device off of PCI bus */

   692 	iowrite32(selective_reset, &nic->csr->port);

   693 	e100_write_flush(nic); udelay(20);

   694 

   695 	/* Now fully reset device */

   696 	iowrite32(software_reset, &nic->csr->port);

   697 	e100_write_flush(nic); udelay(20);

   698 

   699 	/* Mask off our interrupt line - it's unmasked after reset */

   700 	e100_disable_irq(nic);

   701 }

   702 

   703 static int e100_self_test(struct nic *nic)

   704 {

   705 	u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);

   706 

   707 	/* Passing the self-test is a pretty good indication

   708 	 * that the device can DMA to/from host memory */

   709 

   710 	nic->mem->selftest.signature = 0;

   711 	nic->mem->selftest.result = 0xFFFFFFFF;

   712 

   713 	iowrite32(selftest | dma_addr, &nic->csr->port);

   714 	e100_write_flush(nic);

   715 	/* Wait 10 msec for self-test to complete */

   716 	msleep(10);

   717 

   718 	/* Interrupts are enabled after self-test */

   719 	e100_disable_irq(nic);

   720 

   721 	/* Check results of self-test */

   722 	if(nic->mem->selftest.result != 0) {

   723 		DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",

   724 			nic->mem->selftest.result);

   725 		return -ETIMEDOUT;

   726 	}

   727 	if(nic->mem->selftest.signature == 0) {

   728 		DPRINTK(HW, ERR, "Self-test failed: timed out\n");

   729 		return -ETIMEDOUT;

   730 	}

   731 

   732 	return 0;

   733 }

   734 

   735 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)

   736 {

   737 	u32 cmd_addr_data[3];

   738 	u8 ctrl;

   739 	int i, j;

   740 

   741 	/* Three cmds: write/erase enable, write data, write/erase disable */

   742 	cmd_addr_data[0] = op_ewen << (addr_len - 2);

   743 	cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |

   744 		le16_to_cpu(data);

   745 	cmd_addr_data[2] = op_ewds << (addr_len - 2);

   746 

   747 	/* Bit-bang cmds to write word to eeprom */

   748 	for(j = 0; j < 3; j++) {

   749 

   750 		/* Chip select */

   751 		iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   752 		e100_write_flush(nic); udelay(4);

   753 

   754 		for(i = 31; i >= 0; i--) {

   755 			ctrl = (cmd_addr_data[j] & (1 << i)) ?

   756 				eecs | eedi : eecs;

   757 			iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);

   758 			e100_write_flush(nic); udelay(4);

   759 

   760 			iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   761 			e100_write_flush(nic); udelay(4);

   762 		}

   763 		/* Wait 10 msec for cmd to complete */

   764 		msleep(10);

   765 

   766 		/* Chip deselect */

   767 		iowrite8(0, &nic->csr->eeprom_ctrl_lo);

   768 		e100_write_flush(nic); udelay(4);

   769 	}

   770 };

   771 

   772 /* General technique stolen from the eepro100 driver - very clever */

   773 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)

   774 {

   775 	u32 cmd_addr_data;

   776 	u16 data = 0;

   777 	u8 ctrl;

   778 	int i;

   779 

   780 	cmd_addr_data = ((op_read << *addr_len) | addr) << 16;

   781 

   782 	/* Chip select */

   783 	iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   784 	e100_write_flush(nic); udelay(4);

   785 

   786 	/* Bit-bang to read word from eeprom */

   787 	for(i = 31; i >= 0; i--) {

   788 		ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;

   789 		iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);

   790 		e100_write_flush(nic); udelay(4);

   791 

   792 		iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   793 		e100_write_flush(nic); udelay(4);

   794 

   795 		/* Eeprom drives a dummy zero to EEDO after receiving

   796 		 * complete address.  Use this to adjust addr_len. */

   797 		ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);

   798 		if(!(ctrl & eedo) && i > 16) {

   799 			*addr_len -= (i - 16);

   800 			i = 17;

   801 		}

   802 

   803 		data = (data << 1) | (ctrl & eedo ? 1 : 0);

   804 	}

   805 

   806 	/* Chip deselect */

   807 	iowrite8(0, &nic->csr->eeprom_ctrl_lo);

   808 	e100_write_flush(nic); udelay(4);

   809 

   810 	return cpu_to_le16(data);

   811 };

   812 

   813 /* Load entire EEPROM image into driver cache and validate checksum */

   814 static int e100_eeprom_load(struct nic *nic)

   815 {

   816 	u16 addr, addr_len = 8, checksum = 0;

   817 

   818 	/* Try reading with an 8-bit addr len to discover actual addr len */

   819 	e100_eeprom_read(nic, &addr_len, 0);

   820 	nic->eeprom_wc = 1 << addr_len;

   821 

   822 	for(addr = 0; addr < nic->eeprom_wc; addr++) {

   823 		nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);

   824 		if(addr < nic->eeprom_wc - 1)

   825 			checksum += le16_to_cpu(nic->eeprom[addr]);

   826 	}

   827 

   828 	/* The checksum, stored in the last word, is calculated such that

   829 	 * the sum of words should be 0xBABA */

   830 	if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {

   831 		DPRINTK(PROBE, ERR, "EEPROM corrupted\n");

   832 		if (!eeprom_bad_csum_allow)

   833 			return -EAGAIN;

   834 	}

   835 

   836 	return 0;

   837 }

   838 

   839 /* Save (portion of) driver EEPROM cache to device and update checksum */

   840 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)

   841 {

   842 	u16 addr, addr_len = 8, checksum = 0;

   843 

   844 	/* Try reading with an 8-bit addr len to discover actual addr len */

   845 	e100_eeprom_read(nic, &addr_len, 0);

   846 	nic->eeprom_wc = 1 << addr_len;

   847 

   848 	if(start + count >= nic->eeprom_wc)

   849 		return -EINVAL;

   850 

   851 	for(addr = start; addr < start + count; addr++)

   852 		e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);

   853 

   854 	/* The checksum, stored in the last word, is calculated such that

   855 	 * the sum of words should be 0xBABA */

   856 	for(addr = 0; addr < nic->eeprom_wc - 1; addr++)

   857 		checksum += le16_to_cpu(nic->eeprom[addr]);

   858 	nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);

   859 	e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,

   860 		nic->eeprom[nic->eeprom_wc - 1]);

   861 

   862 	return 0;

   863 }

   864 

   865 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */

   866 #define E100_WAIT_SCB_FAST 20       /* delay like the old code */

   867 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)

   868 {

   869 	unsigned long flags = 0;

   870 	unsigned int i;

   871 	int err = 0;

   872 

   873 	if (!nic->ecdev)

   874 		spin_lock_irqsave(&nic->cmd_lock, flags);

   875 

   876 	/* Previous command is accepted when SCB clears */

   877 	for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {

   878 		if(likely(!ioread8(&nic->csr->scb.cmd_lo)))

   879 			break;

   880 		cpu_relax();

   881 		if(unlikely(i > E100_WAIT_SCB_FAST))

   882 			udelay(5);

   883 	}

   884 	if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {

   885 		err = -EAGAIN;

   886 		goto err_unlock;

   887 	}

   888 

   889 	if(unlikely(cmd != cuc_resume))

   890 		iowrite32(dma_addr, &nic->csr->scb.gen_ptr);

   891 	iowrite8(cmd, &nic->csr->scb.cmd_lo);

   892 

   893 err_unlock:

   894 	if (!nic->ecdev)

   895 		spin_unlock_irqrestore(&nic->cmd_lock, flags);

   896 

   897 	return err;

   898 }

   899 

   900 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,

   901 	void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))

   902 {

   903 	struct cb *cb;

   904 	unsigned long flags = 0;

   905 	int err = 0;

   906 

   907 	if (!nic->ecdev)

   908 		spin_lock_irqsave(&nic->cb_lock, flags);

   909 

   910 	if(unlikely(!nic->cbs_avail)) {

   911 		err = -ENOMEM;

   912 		goto err_unlock;

   913 	}

   914 

   915 	cb = nic->cb_to_use;

   916 	nic->cb_to_use = cb->next;

   917 	nic->cbs_avail--;

   918 	cb->skb = skb;

   919 

   920 	if(unlikely(!nic->cbs_avail))

   921 		err = -ENOSPC;

   922 

   923 	cb_prepare(nic, cb, skb);

   924 

   925 	/* Order is important otherwise we'll be in a race with h/w:

   926 	 * set S-bit in current first, then clear S-bit in previous. */

   927 	cb->command |= cpu_to_le16(cb_s);

   928 	wmb();

   929 	cb->prev->command &= cpu_to_le16(~cb_s);

   930 

   931 	while(nic->cb_to_send != nic->cb_to_use) {

   932 		if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,

   933 			nic->cb_to_send->dma_addr))) {

   934 			/* Ok, here's where things get sticky.  It's

   935 			 * possible that we can't schedule the command

   936 			 * because the controller is too busy, so

   937 			 * let's just queue the command and try again

   938 			 * when another command is scheduled. */

   939 			if(err == -ENOSPC) {

   940 				//request a reset

   941 				schedule_work(&nic->tx_timeout_task);

   942 			}

   943 			break;

   944 		} else {

   945 			nic->cuc_cmd = cuc_resume;

   946 			nic->cb_to_send = nic->cb_to_send->next;

   947 		}

   948 	}

   949 

   950 err_unlock:

   951 	if (!nic->ecdev)

   952 		spin_unlock_irqrestore(&nic->cb_lock, flags);

   953 

   954 	return err;

   955 }

   956 

   957 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)

   958 {

   959 	u32 data_out = 0;

   960 	unsigned int i;

   961 	unsigned long flags = 0;

   962 

   963 

   964 	/*

   965 	 * Stratus87247: we shouldn't be writing the MDI control

   966 	 * register until the Ready bit shows True.  Also, since

   967 	 * manipulation of the MDI control registers is a multi-step

   968 	 * procedure it should be done under lock.

   969 	 */

   970 	if (!nic->ecdev)

   971 		spin_lock_irqsave(&nic->mdio_lock, flags);

   972 	for (i = 100; i; --i) {

   973 		if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)

   974 			break;

   975 		udelay(20);

   976 	}

   977 	if (unlikely(!i)) {

   978 		printk("e100.mdio_ctrl(%s) won't go Ready\n",

   979 			nic->netdev->name );

   980 		if (!nic->ecdev)

   981 			spin_unlock_irqrestore(&nic->mdio_lock, flags);

   982 		return 0;		/* No way to indicate timeout error */

   983 	}

   984 	iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

   985 

   986 	for (i = 0; i < 100; i++) {

   987 		udelay(20);

   988 		if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)

   989 			break;

   990 	}

   991 	if (!nic->ecdev)

   992 		spin_unlock_irqrestore(&nic->mdio_lock, flags);

   993 	DPRINTK(HW, DEBUG,

   994 		"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",

   995 		dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);

   996 	return (u16)data_out;

   997 }

   998 

   999 static int mdio_read(struct net_device *netdev, int addr, int reg)

  1000 {

  1001 	return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);

  1002 }

  1003 

  1004 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)

  1005 {

  1006 	mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);

  1007 }

  1008 

  1009 static void e100_get_defaults(struct nic *nic)

  1010 {

  1011 	struct param_range rfds = { .min = 16, .max = 256, .count = 256 };

  1012 	struct param_range cbs  = { .min = 64, .max = 256, .count = 128 };

  1013 

  1014 	/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */

  1015 	nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;

  1016 	if(nic->mac == mac_unknown)

  1017 		nic->mac = mac_82557_D100_A;

  1018 

  1019 	nic->params.rfds = rfds;

  1020 	nic->params.cbs = cbs;

  1021 

  1022 	/* Quadwords to DMA into FIFO before starting frame transmit */

  1023 	nic->tx_threshold = 0xE0;

  1024 

  1025 	/* no interrupt for every tx completion, delay = 256us if not 557 */

  1026 	nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |

  1027 		((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));

  1028 

  1029 	/* Template for a freshly allocated RFD */

  1030 	nic->blank_rfd.command = 0;

  1031 	nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);

  1032 	nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);

  1033 

  1034 	/* MII setup */

  1035 	nic->mii.phy_id_mask = 0x1F;

  1036 	nic->mii.reg_num_mask = 0x1F;

  1037 	nic->mii.dev = nic->netdev;

  1038 	nic->mii.mdio_read = mdio_read;

  1039 	nic->mii.mdio_write = mdio_write;

  1040 }

  1041 

  1042 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)

  1043 {

  1044 	struct config *config = &cb->u.config;

  1045 	u8 *c = (u8 *)config;

  1046 

  1047 	cb->command = cpu_to_le16(cb_config);

  1048 

  1049 	memset(config, 0, sizeof(struct config));

  1050 

  1051 	config->byte_count = 0x16;		/* bytes in this struct */

  1052 	config->rx_fifo_limit = 0x8;		/* bytes in FIFO before DMA */

  1053 	config->direct_rx_dma = 0x1;		/* reserved */

  1054 	config->standard_tcb = 0x1;		/* 1=standard, 0=extended */

  1055 	config->standard_stat_counter = 0x1;	/* 1=standard, 0=extended */

  1056 	config->rx_discard_short_frames = 0x1;	/* 1=discard, 0=pass */

  1057 	config->tx_underrun_retry = 0x3;	/* # of underrun retries */

  1058 	config->mii_mode = 0x1;			/* 1=MII mode, 0=503 mode */

  1059 	config->pad10 = 0x6;

  1060 	config->no_source_addr_insertion = 0x1;	/* 1=no, 0=yes */

  1061 	config->preamble_length = 0x2;		/* 0=1, 1=3, 2=7, 3=15 bytes */

  1062 	config->ifs = 0x6;			/* x16 = inter frame spacing */

  1063 	config->ip_addr_hi = 0xF2;		/* ARP IP filter - not used */

  1064 	config->pad15_1 = 0x1;

  1065 	config->pad15_2 = 0x1;

  1066 	config->crs_or_cdt = 0x0;		/* 0=CRS only, 1=CRS or CDT */

  1067 	config->fc_delay_hi = 0x40;		/* time delay for fc frame */

  1068 	config->tx_padding = 0x1;		/* 1=pad short frames */

  1069 	config->fc_priority_threshold = 0x7;	/* 7=priority fc disabled */

  1070 	config->pad18 = 0x1;

  1071 	config->full_duplex_pin = 0x1;		/* 1=examine FDX# pin */

  1072 	config->pad20_1 = 0x1F;

  1073 	config->fc_priority_location = 0x1;	/* 1=byte#31, 0=byte#19 */

  1074 	config->pad21_1 = 0x5;

  1075 

  1076 	config->adaptive_ifs = nic->adaptive_ifs;

  1077 	config->loopback = nic->loopback;

  1078 

  1079 	if(nic->mii.force_media && nic->mii.full_duplex)

  1080 		config->full_duplex_force = 0x1;	/* 1=force, 0=auto */

  1081 

  1082 	if(nic->flags & promiscuous || nic->loopback) {

  1083 		config->rx_save_bad_frames = 0x1;	/* 1=save, 0=discard */

  1084 		config->rx_discard_short_frames = 0x0;	/* 1=discard, 0=save */

  1085 		config->promiscuous_mode = 0x1;		/* 1=on, 0=off */

  1086 	}

  1087 

  1088 	if(nic->flags & multicast_all)

  1089 		config->multicast_all = 0x1;		/* 1=accept, 0=no */

  1090 

  1091 	/* disable WoL when up */

  1092 	if (nic->ecdev ||

  1093 			(netif_running(nic->netdev) || !(nic->flags & wol_magic)))

  1094 		config->magic_packet_disable = 0x1;	/* 1=off, 0=on */

  1095 

  1096 	if(nic->mac >= mac_82558_D101_A4) {

  1097 		config->fc_disable = 0x1;	/* 1=Tx fc off, 0=Tx fc on */

  1098 		config->mwi_enable = 0x1;	/* 1=enable, 0=disable */

  1099 		config->standard_tcb = 0x0;	/* 1=standard, 0=extended */

  1100 		config->rx_long_ok = 0x1;	/* 1=VLANs ok, 0=standard */

  1101 		if (nic->mac >= mac_82559_D101M) {

  1102 			config->tno_intr = 0x1;		/* TCO stats enable */

  1103 			/* Enable TCO in extended config */

  1104 			if (nic->mac >= mac_82551_10) {

  1105 				config->byte_count = 0x20; /* extended bytes */

  1106 				config->rx_d102_mode = 0x1; /* GMRC for TCO */

  1107 			}

  1108 		} else {

  1109 			config->standard_stat_counter = 0x0;

  1110 		}

  1111 	}

  1112 

  1113 	DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1114 		c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);

  1115 	DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1116 		c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);

  1117 	DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1118 		c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);

  1119 }

  1120 

  1121 /********************************************************/

  1122 /*  Micro code for 8086:1229 Rev 8                      */

  1123 /********************************************************/

  1124 

  1125 /*  Parameter values for the D101M B-step  */

  1126 #define D101M_CPUSAVER_TIMER_DWORD		78

  1127 #define D101M_CPUSAVER_BUNDLE_DWORD		65

  1128 #define D101M_CPUSAVER_MIN_SIZE_DWORD		126

  1129 

  1130 #define D101M_B_RCVBUNDLE_UCODE \

  1131 {\

  1132 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \

  1133 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \

  1134 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \

  1135 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \

  1136 0x00380438, 0x00000000, 0x00140000, 0x00380555, \