1 /******************************************************************************

     2  *

     3  *  drv_8139too.c

     4  *

     5  *  EtherCAT-Treiber für RTL8139-kompatible Netzwerkkarten.

     6  *

     7  *  Autoren: Wilhelm Hagemeister, Florian Pose

     8  *

     9  *  $Date$

    10  *  $Author$

    11  *

    12  *  (C) Copyright IgH 2005

    13  *  Ingenieurgemeinschaft IgH

    14  *  Heinz-Bäcker Str. 34

    15  *  D-45356 Essen

    16  *  Tel.: +49 201/61 99 31

    17  *  Fax.: +49 201/61 98 36

    18  *  E-mail: sp@igh-essen.com

    19  *

    20  ******************************************************************************/

    21 

    22 /*

    23 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    24 

    25 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    26 	Copyright 2000-2002 Jeff Garzik

    27 

    28 	Much code comes from Donald Becker's rtl8139.c driver,

    29 	versions 1.13 and older.  This driver was originally based

    30 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    31 

    32 	-----<snip>-----

    33 

    34         	Written 1997-2001 by Donald Becker.

    35 		This software may be used and distributed according to the

    36 		terms of the GNU General Public License (GPL), incorporated

    37 		herein by reference.  Drivers based on or derived from this

    38 		code fall under the GPL and must retain the authorship,

    39 		copyright and license notice.  This file is not a complete

    40 		program and may only be used when the entire operating

    41 		system is licensed under the GPL.

    42 

    43 		This driver is for boards based on the RTL8129 and RTL8139

    44 		PCI ethernet chips.

    45 

    46 		The author may be reached as becker@scyld.com, or C/O Scyld

    47 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    48 		MD 21403

    49 

    50 		Support and updates available at

    51 		http://www.scyld.com/network/rtl8139.html

    52 

    53 		Twister-tuning table provided by Kinston

    54 		<shangh@realtek.com.tw>.

    55 

    56 	-----<snip>-----

    57 

    58 	This software may be used and distributed according to the terms

    59 	of the GNU General Public License, incorporated herein by reference.

    60 

    61 	Contributors:

    62 

    63 		Donald Becker - he wrote the original driver, kudos to him!

    64 		(but please don't e-mail him for support, this isn't his driver)

    65 

    66 		Tigran Aivazian - bug fixes, skbuff free cleanup

    67 

    68 		Martin Mares - suggestions for PCI cleanup

    69 

    70 		David S. Miller - PCI DMA and softnet updates

    71 

    72 		Ernst Gill - fixes ported from BSD driver

    73 

    74 		Daniel Kobras - identified specific locations of

    75 			posted MMIO write bugginess

    76 

    77 		Gerard Sharp - bug fix, testing and feedback

    78 

    79 		David Ford - Rx ring wrap fix

    80 

    81 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    82 		to find and fix a crucial bug on older chipsets.

    83 

    84 		Donald Becker/Chris Butterworth/Marcus Westergren -

    85 		Noticed various Rx packet size-related buglets.

    86 

    87 		Santiago Garcia Mantinan - testing and feedback

    88 

    89 		Jens David - 2.2.x kernel backports

    90 

    91 		Martin Dennett - incredibly helpful insight on undocumented

    92 		features of the 8139 chips

    93 

    94 		Jean-Jacques Michel - bug fix

    95 

    96 		Tobias Ringström - Rx interrupt status checking suggestion

    97 

    98 		Andrew Morton - Clear blocked signals, avoid

    99 		buffer overrun setting current->comm.

   100 

   101 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   102 

   103 		Robert Kuebel - Save kernel thread from dying on any signal.

   104 

   105 	Submitting bug reports:

   106 

   107 		"rtl8139-diag -mmmaaavvveefN" output

   108 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   109 

   110 */

   111 

   112 #define DRV_NAME	"8139too_ecat"

   113 #define DRV_VERSION	"0.9.27"

   114 

   115 

   116 #include <linux/config.h>

   117 #include <linux/module.h>

   118 #include <linux/kernel.h>

   119 #include <linux/compiler.h>

   120 #include <linux/pci.h>

   121 #include <linux/init.h>

   122 #include <linux/ioport.h>

   123 #include <linux/netdevice.h>

   124 #include <linux/etherdevice.h>

   125 #include <linux/rtnetlink.h>

   126 #include <linux/delay.h>

   127 #include <linux/ethtool.h>

   128 #include <linux/mii.h>

   129 #include <linux/completion.h>

   130 #include <linux/crc32.h>

   131 #include <asm/io.h>

   132 #include <asm/uaccess.h>

   133 #include <asm/irq.h>

   134 

   135 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   136 

   137 #include "ec_device.h"

   138 #include "ec_master.h"

   139 #include "ec_module.h"

   140 

   141 #define LITERAL(X) #X

   142 #define STRINGIFY(X) LITERAL(X)

   143 

   144 #define COMPILE_INFO "Revision " STRINGIFY(EC_REV) \

   145                      ", compiled by " STRINGIFY(EC_USER) \

   146                      " at " STRINGIFY(EC_DATE)

   147 

   148 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   149 

   150 #define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION

   151 #define PFX DRV_NAME ": "

   152 

   153 /* Default Message level */

   154 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   155                                  NETIF_MSG_PROBE  | \

   156                                  NETIF_MSG_LINK)

   157 

   158 

   159 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   160 #ifdef CONFIG_8139TOO_PIO

   161 #define USE_IO_OPS 1

   162 #endif

   163 

   164 /* define to 1, 2 or 3 to enable copious debugging info */

   165 #define RTL8139_DEBUG 0

   166 

   167 /* define to 1 to disable lightweight runtime debugging checks */

   168 #undef RTL8139_NDEBUG

   169 

   170 

   171 #if RTL8139_DEBUG

   172 /* note: prints function name for you */

   173 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   174 #else

   175 #  define DPRINTK(fmt, args...)

   176 #endif

   177 

   178 #ifdef RTL8139_NDEBUG

   179 #  define assert(expr) do {} while (0)

   180 #else

   181 #  define assert(expr) \

   182         if(unlikely(!(expr))) {				        \

   183         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   184         #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   185         }

   186 #endif

   187 

   188 

   189 /* A few user-configurable values. */

   190 /* media options */

   191 #define MAX_UNITS 8

   192 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   193 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   194 

   195 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   196    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   197 static int multicast_filter_limit = 32;

   198 

   199 /* bitmapped message enable number */

   200 static int debug = -1;

   201 

   202 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   203 

   204 // Uncomment for debugging

   205 //#define ECAT_DEBUG

   206 

   207 // Device index for EtherCAT device selection

   208 static int ec_device_index = -1;

   209 static int ec_device_master_index = 0;

   210 

   211 static EtherCAT_device_t rtl_ecat_dev;

   212 int rtl_ecat_dev_registered = 0;

   213 

   214 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   215 

   216 /*

   217  * Receive ring size 

   218  * Warning: 64K ring has hardware issues and may lock up.

   219  */

   220 #if defined(CONFIG_SH_DREAMCAST)

   221 #define RX_BUF_IDX	1	/* 16K ring */

   222 #else

   223 #define RX_BUF_IDX	2	/* 32K ring */

   224 #endif

   225 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   226 #define RX_BUF_PAD	16

   227 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   228 

   229 #if RX_BUF_LEN == 65536

   230 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   231 #else

   232 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   233 #endif

   234 

   235 /* Number of Tx descriptor registers. */

   236 #define NUM_TX_DESC	4

   237 

   238 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   239 #define MAX_ETH_FRAME_SIZE	1536

   240 

   241 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   242 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   243 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   244 

   245 /* PCI Tuning Parameters

   246    Threshold is bytes transferred to chip before transmission starts. */

   247 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   248 

   249 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   250 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   251 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   252 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   253 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   254 

   255 /* Operational parameters that usually are not changed. */

   256 /* Time in jiffies before concluding the transmitter is hung. */

   257 #define TX_TIMEOUT  (6*HZ)

   258 

   259 

   260 enum {

   261 	HAS_MII_XCVR = 0x010000,

   262 	HAS_CHIP_XCVR = 0x020000,

   263 	HAS_LNK_CHNG = 0x040000,

   264 };

   265 

   266 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   267 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   268 #define RTL_MIN_IO_SIZE 0x80

   269 #define RTL8139B_IO_SIZE 256

   270 

   271 #define RTL8129_CAPS	HAS_MII_XCVR

   272 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   273 

   274 typedef enum {

   275 	RTL8139 = 0,

   276 	RTL8129,

   277 } board_t;

   278 

   279 

   280 /* indexed by board_t, above */

   281 static struct {

   282 	const char *name;

   283 	u32 hw_flags;

   284 } board_info[] __devinitdata = {

   285 	{ "RealTek RTL8139", RTL8139_CAPS },

   286 	{ "RealTek RTL8129", RTL8129_CAPS },

   287 };

   288 

   289 

   290 static struct pci_device_id rtl8139_pci_tbl[] = {

   291 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   308 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   309 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 

   310 

   311 #ifdef CONFIG_SH_SECUREEDGE5410

   312 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   313 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   314 #endif

   315 #ifdef CONFIG_8139TOO_8129

   316 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   317 #endif

   318 

   319 	/* some crazy cards report invalid vendor ids like

   320 	 * 0x0001 here.  The other ids are valid and constant,

   321 	 * so we simply don't match on the main vendor id.

   322 	 */

   323 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   324 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   325 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   326 

   327 	{0,}

   328 };

   329 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   330 

   331 static struct {

   332 	const char str[ETH_GSTRING_LEN];

   333 } ethtool_stats_keys[] = {

   334 	{ "early_rx" },

   335 	{ "tx_buf_mapped" },

   336 	{ "tx_timeouts" },

   337 	{ "rx_lost_in_ring" },

   338 };

   339 

   340 /* The rest of these values should never change. */

   341 

   342 /* Symbolic offsets to registers. */

   343 enum RTL8139_registers {

   344 	MAC0 = 0,		/* Ethernet hardware address. */

   345 	MAR0 = 8,		/* Multicast filter. */

   346 	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   347 	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   348 	RxBuf = 0x30,

   349 	ChipCmd = 0x37,

   350 	RxBufPtr = 0x38,

   351 	RxBufAddr = 0x3A,

   352 	IntrMask = 0x3C,

   353 	IntrStatus = 0x3E,

   354 	TxConfig = 0x40,

   355 	RxConfig = 0x44,

   356 	Timer = 0x48,		/* A general-purpose counter. */

   357 	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   358 	Cfg9346 = 0x50,

   359 	Config0 = 0x51,

   360 	Config1 = 0x52,

   361 	FlashReg = 0x54,

   362 	MediaStatus = 0x58,

   363 	Config3 = 0x59,

   364 	Config4 = 0x5A,		/* absent on RTL-8139A */

   365 	HltClk = 0x5B,

   366 	MultiIntr = 0x5C,

   367 	TxSummary = 0x60,

   368 	BasicModeCtrl = 0x62,

   369 	BasicModeStatus = 0x64,

   370 	NWayAdvert = 0x66,

   371 	NWayLPAR = 0x68,

   372 	NWayExpansion = 0x6A,

   373 	/* Undocumented registers, but required for proper operation. */

   374 	FIFOTMS = 0x70,		/* FIFO Control and test. */

   375 	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   376 	PARA78 = 0x78,

   377 	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   378 	Config5 = 0xD8,		/* absent on RTL-8139A */

   379 };

   380 

   381 enum ClearBitMasks {

   382 	MultiIntrClear = 0xF000,

   383 	ChipCmdClear = 0xE2,

   384 	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   385 };

   386 

   387 enum ChipCmdBits {

   388 	CmdReset = 0x10,

   389 	CmdRxEnb = 0x08,

   390 	CmdTxEnb = 0x04,

   391 	RxBufEmpty = 0x01,

   392 };

   393 

   394 /* Interrupt register bits, using my own meaningful names. */

   395 enum IntrStatusBits {

   396 	PCIErr = 0x8000,

   397 	PCSTimeout = 0x4000,

   398 	RxFIFOOver = 0x40,

   399 	RxUnderrun = 0x20,

   400 	RxOverflow = 0x10,

   401 	TxErr = 0x08,

   402 	TxOK = 0x04,

   403 	RxErr = 0x02,

   404 	RxOK = 0x01,

   405 

   406 	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   407 };

   408 

   409 enum TxStatusBits {

   410 	TxHostOwns = 0x2000,

   411 	TxUnderrun = 0x4000,

   412 	TxStatOK = 0x8000,

   413 	TxOutOfWindow = 0x20000000,

   414 	TxAborted = 0x40000000,

   415 	TxCarrierLost = 0x80000000,

   416 };

   417 enum RxStatusBits {

   418 	RxMulticast = 0x8000,

   419 	RxPhysical = 0x4000,

   420 	RxBroadcast = 0x2000,

   421 	RxBadSymbol = 0x0020,

   422 	RxRunt = 0x0010,

   423 	RxTooLong = 0x0008,

   424 	RxCRCErr = 0x0004,

   425 	RxBadAlign = 0x0002,

   426 	RxStatusOK = 0x0001,

   427 };

   428 

   429 /* Bits in RxConfig. */

   430 enum rx_mode_bits {

   431 	AcceptErr = 0x20,

   432 	AcceptRunt = 0x10,

   433 	AcceptBroadcast = 0x08,

   434 	AcceptMulticast = 0x04,

   435 	AcceptMyPhys = 0x02,

   436 	AcceptAllPhys = 0x01,

   437 };

   438 

   439 /* Bits in TxConfig. */

   440 enum tx_config_bits {

   441 

   442         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   443         TxIFGShift = 24,

   444         TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   445         TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   446         TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   447         TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   448 

   449 	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   450 	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   451 	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   452 	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   453 	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   454 

   455 	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   456 };

   457 

   458 /* Bits in Config1 */

   459 enum Config1Bits {

   460 	Cfg1_PM_Enable = 0x01,

   461 	Cfg1_VPD_Enable = 0x02,

   462 	Cfg1_PIO = 0x04,

   463 	Cfg1_MMIO = 0x08,

   464 	LWAKE = 0x10,		/* not on 8139, 8139A */

   465 	Cfg1_Driver_Load = 0x20,

   466 	Cfg1_LED0 = 0x40,

   467 	Cfg1_LED1 = 0x80,

   468 	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   469 	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   470 };

   471 

   472 /* Bits in Config3 */

   473 enum Config3Bits {

   474 	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   475 	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   476 	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   477 	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   478 	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   479 	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   480 	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   481 	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   482 };

   483 

   484 /* Bits in Config4 */

   485 enum Config4Bits {

   486 	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   487 };

   488 

   489 /* Bits in Config5 */

   490 enum Config5Bits {

   491 	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   492 	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   493 	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   494 	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   495 	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   496 	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   497 	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   498 };

   499 

   500 enum RxConfigBits {

   501 	/* rx fifo threshold */

   502 	RxCfgFIFOShift = 13,

   503 	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   504 

   505 	/* Max DMA burst */

   506 	RxCfgDMAShift = 8,

   507 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   508 

   509 	/* rx ring buffer length */

   510 	RxCfgRcv8K = 0,

   511 	RxCfgRcv16K = (1 << 11),

   512 	RxCfgRcv32K = (1 << 12),

   513 	RxCfgRcv64K = (1 << 11) | (1 << 12),

   514 

   515 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   516 	RxNoWrap = (1 << 7),

   517 };

   518 

   519 /* Twister tuning parameters from RealTek.

   520    Completely undocumented, but required to tune bad links on some boards. */

   521 enum CSCRBits {

   522 	CSCR_LinkOKBit = 0x0400,

   523 	CSCR_LinkChangeBit = 0x0800,

   524 	CSCR_LinkStatusBits = 0x0f000,

   525 	CSCR_LinkDownOffCmd = 0x003c0,

   526 	CSCR_LinkDownCmd = 0x0f3c0,

   527 };

   528 

   529 enum Cfg9346Bits {

   530 	Cfg9346_Lock = 0x00,

   531 	Cfg9346_Unlock = 0xC0,

   532 };

   533 

   534 typedef enum {

   535 	CH_8139 = 0,

   536 	CH_8139_K,

   537 	CH_8139A,

   538 	CH_8139A_G,

   539 	CH_8139B,

   540 	CH_8130,

   541 	CH_8139C,

   542 	CH_8100,

   543 	CH_8100B_8139D,

   544 	CH_8101,

   545 } chip_t;

   546 

   547 enum chip_flags {

   548 	HasHltClk = (1 << 0),

   549 	HasLWake = (1 << 1),

   550 };

   551 

   552 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   553 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   554 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   555 

   556 /* directly indexed by chip_t, above */

   557 const static struct {

   558 	const char *name;

   559 	u32 version; /* from RTL8139C/RTL8139D docs */

   560 	u32 flags;

   561 } rtl_chip_info[] = {

   562 	{ "RTL-8139",

   563 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   564 	  HasHltClk,

   565 	},

   566 

   567 	{ "RTL-8139 rev K",

   568 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   569 	  HasHltClk,

   570 	},

   571 

   572 	{ "RTL-8139A",

   573 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   574 	  HasHltClk, /* XXX undocumented? */

   575 	},

   576 

   577 	{ "RTL-8139A rev G",

   578 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   579 	  HasHltClk, /* XXX undocumented? */

   580 	},

   581 

   582 	{ "RTL-8139B",

   583 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   584 	  HasLWake,

   585 	},

   586 

   587 	{ "RTL-8130",

   588 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   589 	  HasLWake,

   590 	},

   591 

   592 	{ "RTL-8139C",

   593 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   594 	  HasLWake,

   595 	},

   596 

   597 	{ "RTL-8100",

   598 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   599  	  HasLWake,

   600  	},

   601 

   602 	{ "RTL-8100B/8139D",

   603 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   604 	  HasLWake,

   605 	},

   606 

   607 	{ "RTL-8101",

   608 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   609 	  HasLWake,

   610 	},

   611 };

   612 

   613 struct rtl_extra_stats {

   614 	unsigned long early_rx;

   615 	unsigned long tx_buf_mapped;

   616 	unsigned long tx_timeouts;

   617 	unsigned long rx_lost_in_ring;

   618 };

   619 

   620 struct rtl8139_private {

   621 	void __iomem *mmio_addr;

   622 	int drv_flags;

   623 	struct pci_dev *pci_dev;

   624 	u32 msg_enable;

   625 	struct net_device_stats stats;

   626 	unsigned char *rx_ring;

   627 	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */

   628 	unsigned int tx_flag;

   629 	unsigned long cur_tx;

   630 	unsigned long dirty_tx;

   631 	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   632 	unsigned char *tx_bufs;	/* Tx bounce buffer region. */

   633 	dma_addr_t rx_ring_dma;

   634 	dma_addr_t tx_bufs_dma;

   635 	signed char phys[4];		/* MII device addresses. */

   636 	char twistie, twist_row, twist_col;	/* Twister tune state. */

   637 	unsigned int default_port:4;	/* Last dev->if_port value. */

   638 	spinlock_t lock;

   639 	spinlock_t rx_lock;

   640 	chip_t chipset;

   641 	pid_t thr_pid;

   642 	wait_queue_head_t thr_wait;

   643 	struct completion thr_exited;

   644 	u32 rx_config;

   645 	struct rtl_extra_stats xstats;

   646 	int time_to_die;

   647 	struct mii_if_info mii;

   648 	unsigned int regs_len;

   649 	unsigned long fifo_copy_timeout;

   650 };

   651 

   652 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   653 

   654 MODULE_AUTHOR ("Wilhelm Hagemeister <hm@igh-essen.com>, Florian Pose <fp@igh-essen.com>");

   655 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver with EtherCAT functionality");

   656 MODULE_LICENSE("GPL");

   657 MODULE_VERSION(COMPILE_INFO);

   658 

   659 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   660 

   661 module_param(multicast_filter_limit, int, 0);

   662 module_param_array(media, int, NULL, 0);

   663 module_param_array(full_duplex, int, NULL, 0);

   664 module_param(debug, int, 0);

   665 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   666 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   667 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   668 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   669 

   670 /* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

   671 

   672 module_param(ec_device_index, int, -1);

   673 module_param(ec_device_master_index, int, 0);

   674 MODULE_PARM_DESC(ec_device_index, "Index of the device reserved for EtherCAT.");

   675 MODULE_PARM_DESC(ec_device_master_index, "Index of the EtherCAT master to register the device.");

   676 

   677 /* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

   678 

   679 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   680 static int rtl8139_open (struct net_device *dev);

   681 static int mdio_read (struct net_device *dev, int phy_id, int location);

   682 static void mdio_write (struct net_device *dev, int phy_id, int location,

   683 			int val);

   684 static void rtl8139_start_thread(struct net_device *dev);

   685 static void rtl8139_tx_timeout (struct net_device *dev);

   686 static void rtl8139_init_ring (struct net_device *dev);

   687 static int rtl8139_start_xmit (struct sk_buff *skb,

   688 			       struct net_device *dev);

   689 int rtl8139_poll(struct net_device *dev, int *budget);

   690 #ifdef CONFIG_NET_POLL_CONTROLLER

   691 static void rtl8139_poll_controller(struct net_device *dev);

   692 #endif

   693 irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,

   694                                struct pt_regs *regs);

   695 static int rtl8139_close (struct net_device *dev);

   696 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   697 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   698 static void rtl8139_set_rx_mode (struct net_device *dev);

   699 static void __set_rx_mode (struct net_device *dev);

   700 static void rtl8139_hw_start (struct net_device *dev);

   701 static struct ethtool_ops rtl8139_ethtool_ops;

   702 

   703 /* write MMIO register, with flush */

   704 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   705 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   706 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   707 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   708 

   709 

   710 #define MMIO_FLUSH_AUDIT_COMPLETE 1

   711 #if MMIO_FLUSH_AUDIT_COMPLETE

   712 

   713 /* write MMIO register */

   714 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   715 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   716 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   717 

   718 #else

   719 

   720 /* write MMIO register, then flush */

   721 #define RTL_W8		RTL_W8_F

   722 #define RTL_W16		RTL_W16_F

   723 #define RTL_W32		RTL_W32_F

   724 

   725 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */

   726 

   727 /* read MMIO register */

   728 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   729 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   730 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   731 

   732 

   733 static const u16 rtl8139_intr_mask =

   734 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   735 	TxErr | TxOK | RxErr | RxOK;

   736 

   737 static const u16 rtl8139_norx_intr_mask =

   738 	PCIErr | PCSTimeout | RxUnderrun |

   739 	TxErr | TxOK | RxErr ;

   740 

   741 #if RX_BUF_IDX == 0

   742 static const unsigned int rtl8139_rx_config =

   743 	RxCfgRcv8K | RxNoWrap |

   744 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   745 	(RX_DMA_BURST << RxCfgDMAShift);

   746 #elif RX_BUF_IDX == 1

   747 static const unsigned int rtl8139_rx_config =

   748 	RxCfgRcv16K | RxNoWrap |

   749 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   750 	(RX_DMA_BURST << RxCfgDMAShift);

   751 #elif RX_BUF_IDX == 2

   752 static const unsigned int rtl8139_rx_config =

   753 	RxCfgRcv32K | RxNoWrap |

   754 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   755 	(RX_DMA_BURST << RxCfgDMAShift);

   756 #elif RX_BUF_IDX == 3

   757 static const unsigned int rtl8139_rx_config =

   758 	RxCfgRcv64K |

   759 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   760 	(RX_DMA_BURST << RxCfgDMAShift);

   761 #else

   762 #error "Invalid configuration for 8139_RXBUF_IDX"

   763 #endif

   764 

   765 static const unsigned int rtl8139_tx_config =

   766 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   767 

   768 static void __rtl8139_cleanup_dev (struct net_device *dev)

   769 {

   770 	struct rtl8139_private *tp = netdev_priv(dev);

   771 	struct pci_dev *pdev;

   772 

   773 	assert (dev != NULL);

   774 	assert (tp->pci_dev != NULL);

   775 	pdev = tp->pci_dev;

   776 

   777 #ifdef USE_IO_OPS

   778 	if (tp->mmio_addr)

   779 		ioport_unmap (tp->mmio_addr);

   780 #else

   781 	if (tp->mmio_addr)

   782 		pci_iounmap (pdev, tp->mmio_addr);

   783 #endif /* USE_IO_OPS */

   784 

   785 	/* it's ok to call this even if we have no regions to free */

   786 	pci_release_regions (pdev);

   787 

   788 	free_netdev(dev);

   789 	pci_set_drvdata (pdev, NULL);

   790 }

   791 

   792 

   793 static void rtl8139_chip_reset (void __iomem *ioaddr)

   794 {

   795 	int i;

   796 

   797 	/* Soft reset the chip. */

   798 	RTL_W8 (ChipCmd, CmdReset);

   799 

   800 	/* Check that the chip has finished the reset. */

   801 	for (i = 1000; i > 0; i--) {

   802 		barrier();

   803 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   804 		    break;

   805 		udelay (10);

   806 	}

   807 }

   808 

   809 

   810 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   811 					 struct net_device **dev_out)

   812 {

   813 	void __iomem *ioaddr;

   814 	struct net_device *dev;

   815 	struct rtl8139_private *tp;

   816 	u8 tmp8;

   817 	int rc, disable_dev_on_err = 0;

   818 	unsigned int i;

   819 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   820 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   821 	u32 version;

   822 

   823 	assert (pdev != NULL);

   824 

   825 	*dev_out = NULL;

   826 

   827 	/* dev and priv zeroed in alloc_etherdev */

   828 	dev = alloc_etherdev (sizeof (*tp));

   829 	if (dev == NULL) {

   830 		printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));

   831 		return -ENOMEM;

   832 	}

   833 	SET_MODULE_OWNER(dev);

   834 	SET_NETDEV_DEV(dev, &pdev->dev);

   835 

   836 	tp = netdev_priv(dev);

   837 	tp->pci_dev = pdev;

   838 

   839 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   840 	rc = pci_enable_device (pdev);

   841 	if (rc)

   842 		goto err_out;

   843 

   844 	pio_start = pci_resource_start (pdev, 0);

   845 	pio_end = pci_resource_end (pdev, 0);

   846 	pio_flags = pci_resource_flags (pdev, 0);

   847 	pio_len = pci_resource_len (pdev, 0);

   848 

   849 	mmio_start = pci_resource_start (pdev, 1);

   850 	mmio_end = pci_resource_end (pdev, 1);

   851 	mmio_flags = pci_resource_flags (pdev, 1);

   852 	mmio_len = pci_resource_len (pdev, 1);

   853 

   854 	/* set this immediately, we need to know before

   855 	 * we talk to the chip directly */

   856 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   857 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   858 

   859 #ifdef USE_IO_OPS

   860 	/* make sure PCI base addr 0 is PIO */

   861 	if (!(pio_flags & IORESOURCE_IO)) {

   862 		printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));

   863 		rc = -ENODEV;

   864 		goto err_out;

   865 	}

   866 	/* check for weird/broken PCI region reporting */

   867 	if (pio_len < RTL_MIN_IO_SIZE) {

   868 		printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));

   869 		rc = -ENODEV;

   870 		goto err_out;

   871 	}

   872 #else

   873 	/* make sure PCI base addr 1 is MMIO */

   874 	if (!(mmio_flags & IORESOURCE_MEM)) {

   875 		printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));

   876 		rc = -ENODEV;

   877 		goto err_out;

   878 	}

   879 	if (mmio_len < RTL_MIN_IO_SIZE) {

   880 		printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));

   881 		rc = -ENODEV;

   882 		goto err_out;

   883 	}

   884 #endif

   885 

   886 	rc = pci_request_regions (pdev, "8139too");

   887 	if (rc)

   888 		goto err_out;

   889 	disable_dev_on_err = 1;

   890 

   891 	/* enable PCI bus-mastering */

   892 	pci_set_master (pdev);

   893 

   894 #ifdef USE_IO_OPS

   895 	ioaddr = ioport_map(pio_start, pio_len);

   896 	if (!ioaddr) {

   897 		printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));

   898 		rc = -EIO;

   899 		goto err_out;

   900 	}

   901 	dev->base_addr = pio_start;

   902 	tp->mmio_addr = ioaddr;

   903 	tp->regs_len = pio_len;

   904 #else

   905 	/* ioremap MMIO region */

   906 	ioaddr = pci_iomap(pdev, 1, 0);

   907 	if (ioaddr == NULL) {

   908 		printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));

   909 		rc = -EIO;

   910 		goto err_out;

   911 	}

   912 	dev->base_addr = (long) ioaddr;

   913 	tp->mmio_addr = ioaddr;

   914 	tp->regs_len = mmio_len;

   915 #endif /* USE_IO_OPS */

   916 

   917 	/* Bring old chips out of low-power mode. */

   918 	RTL_W8 (HltClk, 'R');

   919 

   920 	/* check for missing/broken hardware */

   921 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   922 		printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",

   923 			pci_name(pdev));

   924 		rc = -EIO;

   925 		goto err_out;

   926 	}

   927 

   928 	/* identify chip attached to board */

   929 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   930 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   931 		if (version == rtl_chip_info[i].version) {

   932 			tp->chipset = i;

   933 			goto match;

   934 		}

   935 

   936 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   937 	printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",

   938 		pci_name(pdev));

   939         printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));

   940 	tp->chipset = 0;

   941 

   942 match:

   943 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   944 		 version, i, rtl_chip_info[i].name);

   945 

   946 	if (tp->chipset >= CH_8139B) {

   947 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   948 		DPRINTK("PCI PM wakeup\n");

   949 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   950 		    (tmp8 & LWAKE))

   951 			new_tmp8 &= ~LWAKE;

   952 		new_tmp8 |= Cfg1_PM_Enable;

   953 		if (new_tmp8 != tmp8) {

   954 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   955 			RTL_W8 (Config1, tmp8);

   956 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   957 		}

   958 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   959 			tmp8 = RTL_R8 (Config4);

   960 			if (tmp8 & LWPTN) {

   961 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   962 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   963 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   964 			}

   965 		}

   966 	} else {

   967 		DPRINTK("Old chip wakeup\n");

   968 		tmp8 = RTL_R8 (Config1);

   969 		tmp8 &= ~(SLEEP | PWRDN);

   970 		RTL_W8 (Config1, tmp8);

   971 	}

   972 

   973 	rtl8139_chip_reset (ioaddr);

   974 

   975 	*dev_out = dev;

   976 	return 0;

   977 

   978 err_out:

   979 	__rtl8139_cleanup_dev (dev);

   980 	if (disable_dev_on_err)

   981 		pci_disable_device (pdev);

   982 	return rc;

   983 }

   984 

   985 

   986 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   987 				       const struct pci_device_id *ent)

   988 {

   989 	struct net_device *dev = NULL;

   990 	struct rtl8139_private *tp;

   991 	int i, addr_len, option;

   992 	void __iomem *ioaddr;

   993 	static int board_idx = -1;

   994 	u8 pci_rev;

   995 

   996 	assert (pdev != NULL);

   997 	assert (ent != NULL);

   998 

   999 	board_idx++;

  1000 

  1001 	/* when we're built into the kernel, the driver version message

  1002 	 * is only printed if at least one 8139 board has been found

  1003 	 */

  1004 #ifndef MODULE

  1005 	{

  1006 		static int printed_version;

  1007 		if (!printed_version++)

  1008 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

  1009 	}

  1010 #endif

  1011 

  1012 	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);

  1013 

  1014 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1015 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {

  1016 		printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

  1017 		       pci_name(pdev), pdev->vendor, pdev->device, pci_rev);

  1018 		printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");

  1019 	}

  1020 

  1021 	i = rtl8139_init_board (pdev, &dev);

  1022 	if (i < 0)

  1023 		return i;

  1024 

  1025 	assert (dev != NULL);

  1026 	tp = netdev_priv(dev);

  1027 

  1028 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1029 

  1030 	if (board_idx == ec_device_index)

  1031         {

  1032                 printk("EtherCAT registering board %d.\n", board_idx);

  1033 

  1034                 if (EtherCAT_device_assign(&rtl_ecat_dev, dev) < 0)

  1035                   goto err_out;

  1036 

  1037                 strcpy(dev->name,"ecat0"); //device name überschreiben

  1038 	}

  1039 

  1040 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1041 

  1042 	ioaddr = tp->mmio_addr;

  1043 	assert (ioaddr != NULL);

  1044 

  1045 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1046 	for (i = 0; i < 3; i++)

  1047 		((u16 *) (dev->dev_addr))[i] =

  1048 		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));

  1049 

  1050 	/* The Rtl8139-specific entries in the device structure. */

  1051 	dev->open = rtl8139_open;

  1052 	dev->hard_start_xmit = rtl8139_start_xmit;

  1053 	dev->poll = rtl8139_poll;

  1054 	dev->weight = 64;

  1055 	dev->stop = rtl8139_close;

  1056 	dev->get_stats = rtl8139_get_stats;

  1057 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1058 	dev->do_ioctl = netdev_ioctl;

  1059 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1060 	dev->tx_timeout = rtl8139_tx_timeout;

  1061 	dev->watchdog_timeo = TX_TIMEOUT;

  1062 #ifdef CONFIG_NET_POLL_CONTROLLER

  1063 	dev->poll_controller = rtl8139_poll_controller;

  1064 #endif

  1065 

  1066 	/* note: the hardware is not capable of sg/csum/highdma, however

  1067 	 * through the use of skb_copy_and_csum_dev we enable these

  1068 	 * features

  1069 	 */

  1070 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1071 

  1072 	dev->irq = pdev->irq;

  1073 

  1074 	/* tp zeroed and aligned in alloc_etherdev */

  1075 	tp = netdev_priv(dev);

  1076 

  1077 	/* note: tp->chipset set in rtl8139_init_board */

  1078 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1079 	tp->mmio_addr = ioaddr;

  1080 	tp->msg_enable =

  1081 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1082 	spin_lock_init (&tp->lock);

  1083 	spin_lock_init (&tp->rx_lock);

  1084 

  1085 	init_waitqueue_head (&tp->thr_wait);

  1086 	init_completion (&tp->thr_exited);

  1087 	tp->mii.dev = dev;

  1088 	tp->mii.mdio_read = mdio_read;

  1089 	tp->mii.mdio_write = mdio_write;

  1090 	tp->mii.phy_id_mask = 0x3f;

  1091 	tp->mii.reg_num_mask = 0x1f;

  1092 

  1093 	/* dev is fully set up and ready to use now */

  1094 

  1095 	/* EtherCAT >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>*/

  1096 

  1097 	/* EtherCAT-Karten nicht beim Stack anmelden. */

  1098         if (dev != rtl_ecat_dev.dev)

  1099 	{

  1100                 DPRINTK("About to register device named %s (%p)...\n", dev->name, dev);

  1101                 i = register_netdev (dev);

  1102                 if (i) goto err_out;

  1103 	}

  1104 

  1105 	/* EtherCAT <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<*/

  1106 

  1107 	pci_set_drvdata (pdev, dev);

  1108 

  1109 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1110 		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "

  1111 		"IRQ %d\n",

  1112 		dev->name,

  1113 		board_info[ent->driver_data].name,

  1114 		dev->base_addr,

  1115 		dev->dev_addr[0], dev->dev_addr[1],

  1116 		dev->dev_addr[2], dev->dev_addr[3],

  1117 		dev->dev_addr[4], dev->dev_addr[5],

  1118 		dev->irq);

  1119 

  1120 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1121 		dev->name, rtl_chip_info[tp->chipset].name);

  1122 

  1123 	/* Find the connected MII xcvrs.

  1124 	   Doing this in open() would allow detecting external xcvrs later, but

  1125 	   takes too much time. */

  1126 #ifdef CONFIG_8139TOO_8129

  1127 	if (tp->drv_flags & HAS_MII_XCVR) {

  1128 		int phy, phy_idx = 0;

  1129 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1130 			int mii_status = mdio_read(dev, phy, 1);

  1131 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1132 				u16 advertising = mdio_read(dev, phy, 4);

  1133 				tp->phys[phy_idx++] = phy;

  1134 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1135 					   "advertising %4.4x.\n",

  1136 					   dev->name, phy, mii_status, advertising);