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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2009 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 /* |
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30 * 82571EB Gigabit Ethernet Controller |
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31 * 82571EB Gigabit Ethernet Controller (Copper) |
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32 * 82571EB Gigabit Ethernet Controller (Fiber) |
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33 * 82571EB Dual Port Gigabit Mezzanine Adapter |
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34 * 82571EB Quad Port Gigabit Mezzanine Adapter |
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35 * 82571PT Gigabit PT Quad Port Server ExpressModule |
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36 * 82572EI Gigabit Ethernet Controller (Copper) |
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37 * 82572EI Gigabit Ethernet Controller (Fiber) |
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38 * 82572EI Gigabit Ethernet Controller |
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39 * 82573V Gigabit Ethernet Controller (Copper) |
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40 * 82573E Gigabit Ethernet Controller (Copper) |
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41 * 82573L Gigabit Ethernet Controller |
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42 * 82574L Gigabit Network Connection |
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43 * 82583V Gigabit Network Connection |
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44 */ |
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45 |
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46 #include "e1000.h" |
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47 |
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48 #define ID_LED_RESERVED_F746 0xF746 |
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49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ |
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50 (ID_LED_OFF1_ON2 << 8) | \ |
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51 (ID_LED_DEF1_DEF2 << 4) | \ |
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52 (ID_LED_DEF1_DEF2)) |
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53 |
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54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 |
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55 |
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56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
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57 |
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58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
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59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); |
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60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); |
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61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
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62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
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63 u16 words, u16 *data); |
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64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); |
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65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); |
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66 static s32 e1000_setup_link_82571(struct e1000_hw *hw); |
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67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); |
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68 static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
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69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
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70 static s32 e1000_led_on_82574(struct e1000_hw *hw); |
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71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
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72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
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73 |
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74 /** |
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75 * e1000_init_phy_params_82571 - Init PHY func ptrs. |
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76 * @hw: pointer to the HW structure |
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77 **/ |
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78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) |
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79 { |
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80 struct e1000_phy_info *phy = &hw->phy; |
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81 s32 ret_val; |
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82 |
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83 if (hw->phy.media_type != e1000_media_type_copper) { |
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84 phy->type = e1000_phy_none; |
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85 return 0; |
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86 } |
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87 |
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88 phy->addr = 1; |
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89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
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90 phy->reset_delay_us = 100; |
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91 |
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92 phy->ops.power_up = e1000_power_up_phy_copper; |
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93 phy->ops.power_down = e1000_power_down_phy_copper_82571; |
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94 |
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95 switch (hw->mac.type) { |
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96 case e1000_82571: |
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97 case e1000_82572: |
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98 phy->type = e1000_phy_igp_2; |
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99 break; |
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100 case e1000_82573: |
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101 phy->type = e1000_phy_m88; |
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102 break; |
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103 case e1000_82574: |
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104 case e1000_82583: |
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105 phy->type = e1000_phy_bm; |
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106 break; |
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107 default: |
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108 return -E1000_ERR_PHY; |
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109 break; |
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110 } |
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111 |
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112 /* This can only be done after all function pointers are setup. */ |
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113 ret_val = e1000_get_phy_id_82571(hw); |
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114 |
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115 /* Verify phy id */ |
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116 switch (hw->mac.type) { |
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117 case e1000_82571: |
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118 case e1000_82572: |
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119 if (phy->id != IGP01E1000_I_PHY_ID) |
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120 return -E1000_ERR_PHY; |
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121 break; |
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122 case e1000_82573: |
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123 if (phy->id != M88E1111_I_PHY_ID) |
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124 return -E1000_ERR_PHY; |
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125 break; |
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126 case e1000_82574: |
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127 case e1000_82583: |
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128 if (phy->id != BME1000_E_PHY_ID_R2) |
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129 return -E1000_ERR_PHY; |
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130 break; |
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131 default: |
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132 return -E1000_ERR_PHY; |
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133 break; |
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134 } |
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135 |
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136 return 0; |
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137 } |
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138 |
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139 /** |
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140 * e1000_init_nvm_params_82571 - Init NVM func ptrs. |
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141 * @hw: pointer to the HW structure |
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142 **/ |
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143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) |
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144 { |
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145 struct e1000_nvm_info *nvm = &hw->nvm; |
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146 u32 eecd = er32(EECD); |
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147 u16 size; |
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148 |
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149 nvm->opcode_bits = 8; |
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150 nvm->delay_usec = 1; |
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151 switch (nvm->override) { |
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152 case e1000_nvm_override_spi_large: |
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153 nvm->page_size = 32; |
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154 nvm->address_bits = 16; |
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155 break; |
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156 case e1000_nvm_override_spi_small: |
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157 nvm->page_size = 8; |
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158 nvm->address_bits = 8; |
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159 break; |
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160 default: |
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161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; |
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162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; |
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163 break; |
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164 } |
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165 |
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166 switch (hw->mac.type) { |
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167 case e1000_82573: |
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168 case e1000_82574: |
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169 case e1000_82583: |
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170 if (((eecd >> 15) & 0x3) == 0x3) { |
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171 nvm->type = e1000_nvm_flash_hw; |
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172 nvm->word_size = 2048; |
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173 /* |
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174 * Autonomous Flash update bit must be cleared due |
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175 * to Flash update issue. |
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176 */ |
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177 eecd &= ~E1000_EECD_AUPDEN; |
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178 ew32(EECD, eecd); |
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179 break; |
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180 } |
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181 /* Fall Through */ |
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182 default: |
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183 nvm->type = e1000_nvm_eeprom_spi; |
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184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
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185 E1000_EECD_SIZE_EX_SHIFT); |
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186 /* |
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187 * Added to a constant, "size" becomes the left-shift value |
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188 * for setting word_size. |
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189 */ |
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190 size += NVM_WORD_SIZE_BASE_SHIFT; |
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191 |
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192 /* EEPROM access above 16k is unsupported */ |
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193 if (size > 14) |
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194 size = 14; |
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195 nvm->word_size = 1 << size; |
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196 break; |
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197 } |
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198 |
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199 return 0; |
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200 } |
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201 |
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202 /** |
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203 * e1000_init_mac_params_82571 - Init MAC func ptrs. |
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204 * @hw: pointer to the HW structure |
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205 **/ |
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206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) |
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207 { |
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208 struct e1000_hw *hw = &adapter->hw; |
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209 struct e1000_mac_info *mac = &hw->mac; |
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210 struct e1000_mac_operations *func = &mac->ops; |
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211 u32 swsm = 0; |
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212 u32 swsm2 = 0; |
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213 bool force_clear_smbi = false; |
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214 |
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215 /* Set media type */ |
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216 switch (adapter->pdev->device) { |
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217 case E1000_DEV_ID_82571EB_FIBER: |
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218 case E1000_DEV_ID_82572EI_FIBER: |
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219 case E1000_DEV_ID_82571EB_QUAD_FIBER: |
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220 hw->phy.media_type = e1000_media_type_fiber; |
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221 break; |
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222 case E1000_DEV_ID_82571EB_SERDES: |
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223 case E1000_DEV_ID_82572EI_SERDES: |
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224 case E1000_DEV_ID_82571EB_SERDES_DUAL: |
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225 case E1000_DEV_ID_82571EB_SERDES_QUAD: |
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226 hw->phy.media_type = e1000_media_type_internal_serdes; |
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227 break; |
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228 default: |
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229 hw->phy.media_type = e1000_media_type_copper; |
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230 break; |
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231 } |
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232 |
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233 /* Set mta register count */ |
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234 mac->mta_reg_count = 128; |
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235 /* Set rar entry count */ |
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236 mac->rar_entry_count = E1000_RAR_ENTRIES; |
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237 /* Set if manageability features are enabled. */ |
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238 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
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239 ? true : false; |
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240 /* Adaptive IFS supported */ |
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241 mac->adaptive_ifs = true; |
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242 |
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243 /* check for link */ |
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244 switch (hw->phy.media_type) { |
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245 case e1000_media_type_copper: |
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246 func->setup_physical_interface = e1000_setup_copper_link_82571; |
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247 func->check_for_link = e1000e_check_for_copper_link; |
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248 func->get_link_up_info = e1000e_get_speed_and_duplex_copper; |
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249 break; |
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250 case e1000_media_type_fiber: |
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251 func->setup_physical_interface = |
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252 e1000_setup_fiber_serdes_link_82571; |
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253 func->check_for_link = e1000e_check_for_fiber_link; |
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254 func->get_link_up_info = |
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255 e1000e_get_speed_and_duplex_fiber_serdes; |
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256 break; |
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257 case e1000_media_type_internal_serdes: |
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258 func->setup_physical_interface = |
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259 e1000_setup_fiber_serdes_link_82571; |
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260 func->check_for_link = e1000_check_for_serdes_link_82571; |
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261 func->get_link_up_info = |
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262 e1000e_get_speed_and_duplex_fiber_serdes; |
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263 break; |
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264 default: |
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265 return -E1000_ERR_CONFIG; |
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266 break; |
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267 } |
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268 |
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269 switch (hw->mac.type) { |
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270 case e1000_82573: |
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271 func->set_lan_id = e1000_set_lan_id_single_port; |
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272 func->check_mng_mode = e1000e_check_mng_mode_generic; |
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273 func->led_on = e1000e_led_on_generic; |
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274 break; |
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275 case e1000_82574: |
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276 case e1000_82583: |
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277 func->set_lan_id = e1000_set_lan_id_single_port; |
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278 func->check_mng_mode = e1000_check_mng_mode_82574; |
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279 func->led_on = e1000_led_on_82574; |
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280 break; |
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281 default: |
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282 func->check_mng_mode = e1000e_check_mng_mode_generic; |
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283 func->led_on = e1000e_led_on_generic; |
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284 break; |
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285 } |
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286 |
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287 /* |
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288 * Ensure that the inter-port SWSM.SMBI lock bit is clear before |
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289 * first NVM or PHY acess. This should be done for single-port |
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290 * devices, and for one port only on dual-port devices so that |
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291 * for those devices we can still use the SMBI lock to synchronize |
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292 * inter-port accesses to the PHY & NVM. |
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293 */ |
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294 switch (hw->mac.type) { |
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295 case e1000_82571: |
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296 case e1000_82572: |
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297 swsm2 = er32(SWSM2); |
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298 |
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299 if (!(swsm2 & E1000_SWSM2_LOCK)) { |
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300 /* Only do this for the first interface on this card */ |
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301 ew32(SWSM2, |
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302 swsm2 | E1000_SWSM2_LOCK); |
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303 force_clear_smbi = true; |
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304 } else |
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305 force_clear_smbi = false; |
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306 break; |
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307 default: |
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308 force_clear_smbi = true; |
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309 break; |
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310 } |
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311 |
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312 if (force_clear_smbi) { |
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313 /* Make sure SWSM.SMBI is clear */ |
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314 swsm = er32(SWSM); |
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315 if (swsm & E1000_SWSM_SMBI) { |
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316 /* This bit should not be set on a first interface, and |
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317 * indicates that the bootagent or EFI code has |
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318 * improperly left this bit enabled |
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319 */ |
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320 e_dbg("Please update your 82571 Bootagent\n"); |
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321 } |
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322 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); |
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323 } |
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324 |
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325 /* |
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326 * Initialze device specific counter of SMBI acquisition |
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327 * timeouts. |
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328 */ |
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329 hw->dev_spec.e82571.smb_counter = 0; |
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330 |
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331 return 0; |
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332 } |
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333 |
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334 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
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335 { |
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336 struct e1000_hw *hw = &adapter->hw; |
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337 static int global_quad_port_a; /* global port a indication */ |
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338 struct pci_dev *pdev = adapter->pdev; |
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339 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
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340 s32 rc; |
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341 |
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342 rc = e1000_init_mac_params_82571(adapter); |
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343 if (rc) |
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344 return rc; |
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345 |
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346 rc = e1000_init_nvm_params_82571(hw); |
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347 if (rc) |
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348 return rc; |
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349 |
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350 rc = e1000_init_phy_params_82571(hw); |
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351 if (rc) |
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352 return rc; |
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353 |
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354 /* tag quad port adapters first, it's used below */ |
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355 switch (pdev->device) { |
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356 case E1000_DEV_ID_82571EB_QUAD_COPPER: |
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357 case E1000_DEV_ID_82571EB_QUAD_FIBER: |
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358 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: |
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359 case E1000_DEV_ID_82571PT_QUAD_COPPER: |
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360 adapter->flags |= FLAG_IS_QUAD_PORT; |
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361 /* mark the first port */ |
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362 if (global_quad_port_a == 0) |
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363 adapter->flags |= FLAG_IS_QUAD_PORT_A; |
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364 /* Reset for multiple quad port adapters */ |
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365 global_quad_port_a++; |
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366 if (global_quad_port_a == 4) |
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367 global_quad_port_a = 0; |
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368 break; |
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369 default: |
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370 break; |
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371 } |
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372 |
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373 switch (adapter->hw.mac.type) { |
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374 case e1000_82571: |
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375 /* these dual ports don't have WoL on port B at all */ |
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376 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || |
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377 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || |
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378 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && |
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379 (is_port_b)) |
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380 adapter->flags &= ~FLAG_HAS_WOL; |
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381 /* quad ports only support WoL on port A */ |
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382 if (adapter->flags & FLAG_IS_QUAD_PORT && |
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383 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
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384 adapter->flags &= ~FLAG_HAS_WOL; |
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385 /* Does not support WoL on any port */ |
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386 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) |
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387 adapter->flags &= ~FLAG_HAS_WOL; |
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388 break; |
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389 case e1000_82573: |
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390 case e1000_82574: |
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391 case e1000_82583: |
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392 /* Disable ASPM L0s due to hardware errata */ |
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393 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); |
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394 |
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395 if (pdev->device == E1000_DEV_ID_82573L) { |
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396 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
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397 adapter->max_hw_frame_size = DEFAULT_JUMBO; |
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398 } |
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399 break; |
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400 default: |
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401 break; |
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402 } |
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403 |
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404 return 0; |
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405 } |
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406 |
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407 /** |
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408 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision |
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409 * @hw: pointer to the HW structure |
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410 * |
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411 * Reads the PHY registers and stores the PHY ID and possibly the PHY |
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412 * revision in the hardware structure. |
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413 **/ |
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414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) |
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415 { |
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416 struct e1000_phy_info *phy = &hw->phy; |
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417 s32 ret_val; |
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418 u16 phy_id = 0; |
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419 |
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420 switch (hw->mac.type) { |
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421 case e1000_82571: |
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422 case e1000_82572: |
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423 /* |
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424 * The 82571 firmware may still be configuring the PHY. |
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425 * In this case, we cannot access the PHY until the |
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426 * configuration is done. So we explicitly set the |
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427 * PHY ID. |
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428 */ |
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429 phy->id = IGP01E1000_I_PHY_ID; |
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430 break; |
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431 case e1000_82573: |
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432 return e1000e_get_phy_id(hw); |
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433 break; |
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434 case e1000_82574: |
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435 case e1000_82583: |
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436 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
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437 if (ret_val) |
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438 return ret_val; |
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439 |
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440 phy->id = (u32)(phy_id << 16); |
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441 udelay(20); |
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442 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); |
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443 if (ret_val) |
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444 return ret_val; |
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445 |
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446 phy->id |= (u32)(phy_id); |
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447 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
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448 break; |
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449 default: |
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450 return -E1000_ERR_PHY; |
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451 break; |
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452 } |
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453 |
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454 return 0; |
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455 } |
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456 |
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457 /** |
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458 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore |
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459 * @hw: pointer to the HW structure |
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460 * |
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461 * Acquire the HW semaphore to access the PHY or NVM |
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462 **/ |
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463 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) |
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464 { |
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465 u32 swsm; |
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466 s32 sw_timeout = hw->nvm.word_size + 1; |
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467 s32 fw_timeout = hw->nvm.word_size + 1; |
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468 s32 i = 0; |
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469 |
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470 /* |
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471 * If we have timedout 3 times on trying to acquire |
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472 * the inter-port SMBI semaphore, there is old code |
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473 * operating on the other port, and it is not |
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474 * releasing SMBI. Modify the number of times that |
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475 * we try for the semaphore to interwork with this |
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476 * older code. |
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477 */ |
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478 if (hw->dev_spec.e82571.smb_counter > 2) |
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479 sw_timeout = 1; |
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480 |
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481 /* Get the SW semaphore */ |
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482 while (i < sw_timeout) { |
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483 swsm = er32(SWSM); |
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484 if (!(swsm & E1000_SWSM_SMBI)) |
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485 break; |
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486 |
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487 udelay(50); |
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488 i++; |
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489 } |
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490 |
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491 if (i == sw_timeout) { |
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492 e_dbg("Driver can't access device - SMBI bit is set.\n"); |
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493 hw->dev_spec.e82571.smb_counter++; |
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494 } |
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495 /* Get the FW semaphore. */ |
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496 for (i = 0; i < fw_timeout; i++) { |
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497 swsm = er32(SWSM); |
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498 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
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499 |
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500 /* Semaphore acquired if bit latched */ |
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501 if (er32(SWSM) & E1000_SWSM_SWESMBI) |
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502 break; |
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503 |
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504 udelay(50); |
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505 } |
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506 |
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507 if (i == fw_timeout) { |
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508 /* Release semaphores */ |
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509 e1000_put_hw_semaphore_82571(hw); |
|
510 e_dbg("Driver can't access the NVM\n"); |
|
511 return -E1000_ERR_NVM; |
|
512 } |
|
513 |
|
514 return 0; |
|
515 } |
|
516 |
|
517 /** |
|
518 * e1000_put_hw_semaphore_82571 - Release hardware semaphore |
|
519 * @hw: pointer to the HW structure |
|
520 * |
|
521 * Release hardware semaphore used to access the PHY or NVM |
|
522 **/ |
|
523 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) |
|
524 { |
|
525 u32 swsm; |
|
526 |
|
527 swsm = er32(SWSM); |
|
528 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
529 ew32(SWSM, swsm); |
|
530 } |
|
531 |
|
532 /** |
|
533 * e1000_acquire_nvm_82571 - Request for access to the EEPROM |
|
534 * @hw: pointer to the HW structure |
|
535 * |
|
536 * To gain access to the EEPROM, first we must obtain a hardware semaphore. |
|
537 * Then for non-82573 hardware, set the EEPROM access request bit and wait |
|
538 * for EEPROM access grant bit. If the access grant bit is not set, release |
|
539 * hardware semaphore. |
|
540 **/ |
|
541 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) |
|
542 { |
|
543 s32 ret_val; |
|
544 |
|
545 ret_val = e1000_get_hw_semaphore_82571(hw); |
|
546 if (ret_val) |
|
547 return ret_val; |
|
548 |
|
549 switch (hw->mac.type) { |
|
550 case e1000_82573: |
|
551 case e1000_82574: |
|
552 case e1000_82583: |
|
553 break; |
|
554 default: |
|
555 ret_val = e1000e_acquire_nvm(hw); |
|
556 break; |
|
557 } |
|
558 |
|
559 if (ret_val) |
|
560 e1000_put_hw_semaphore_82571(hw); |
|
561 |
|
562 return ret_val; |
|
563 } |
|
564 |
|
565 /** |
|
566 * e1000_release_nvm_82571 - Release exclusive access to EEPROM |
|
567 * @hw: pointer to the HW structure |
|
568 * |
|
569 * Stop any current commands to the EEPROM and clear the EEPROM request bit. |
|
570 **/ |
|
571 static void e1000_release_nvm_82571(struct e1000_hw *hw) |
|
572 { |
|
573 e1000e_release_nvm(hw); |
|
574 e1000_put_hw_semaphore_82571(hw); |
|
575 } |
|
576 |
|
577 /** |
|
578 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface |
|
579 * @hw: pointer to the HW structure |
|
580 * @offset: offset within the EEPROM to be written to |
|
581 * @words: number of words to write |
|
582 * @data: 16 bit word(s) to be written to the EEPROM |
|
583 * |
|
584 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. |
|
585 * |
|
586 * If e1000e_update_nvm_checksum is not called after this function, the |
|
587 * EEPROM will most likely contain an invalid checksum. |
|
588 **/ |
|
589 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, |
|
590 u16 *data) |
|
591 { |
|
592 s32 ret_val; |
|
593 |
|
594 switch (hw->mac.type) { |
|
595 case e1000_82573: |
|
596 case e1000_82574: |
|
597 case e1000_82583: |
|
598 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
|
599 break; |
|
600 case e1000_82571: |
|
601 case e1000_82572: |
|
602 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); |
|
603 break; |
|
604 default: |
|
605 ret_val = -E1000_ERR_NVM; |
|
606 break; |
|
607 } |
|
608 |
|
609 return ret_val; |
|
610 } |
|
611 |
|
612 /** |
|
613 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum |
|
614 * @hw: pointer to the HW structure |
|
615 * |
|
616 * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
617 * up to the checksum. Then calculates the EEPROM checksum and writes the |
|
618 * value to the EEPROM. |
|
619 **/ |
|
620 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) |
|
621 { |
|
622 u32 eecd; |
|
623 s32 ret_val; |
|
624 u16 i; |
|
625 |
|
626 ret_val = e1000e_update_nvm_checksum_generic(hw); |
|
627 if (ret_val) |
|
628 return ret_val; |
|
629 |
|
630 /* |
|
631 * If our nvm is an EEPROM, then we're done |
|
632 * otherwise, commit the checksum to the flash NVM. |
|
633 */ |
|
634 if (hw->nvm.type != e1000_nvm_flash_hw) |
|
635 return ret_val; |
|
636 |
|
637 /* Check for pending operations. */ |
|
638 for (i = 0; i < E1000_FLASH_UPDATES; i++) { |
|
639 msleep(1); |
|
640 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
|
641 break; |
|
642 } |
|
643 |
|
644 if (i == E1000_FLASH_UPDATES) |
|
645 return -E1000_ERR_NVM; |
|
646 |
|
647 /* Reset the firmware if using STM opcode. */ |
|
648 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { |
|
649 /* |
|
650 * The enabling of and the actual reset must be done |
|
651 * in two write cycles. |
|
652 */ |
|
653 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); |
|
654 e1e_flush(); |
|
655 ew32(HICR, E1000_HICR_FW_RESET); |
|
656 } |
|
657 |
|
658 /* Commit the write to flash */ |
|
659 eecd = er32(EECD) | E1000_EECD_FLUPD; |
|
660 ew32(EECD, eecd); |
|
661 |
|
662 for (i = 0; i < E1000_FLASH_UPDATES; i++) { |
|
663 msleep(1); |
|
664 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
|
665 break; |
|
666 } |
|
667 |
|
668 if (i == E1000_FLASH_UPDATES) |
|
669 return -E1000_ERR_NVM; |
|
670 |
|
671 return 0; |
|
672 } |
|
673 |
|
674 /** |
|
675 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum |
|
676 * @hw: pointer to the HW structure |
|
677 * |
|
678 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
|
679 * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
|
680 **/ |
|
681 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) |
|
682 { |
|
683 if (hw->nvm.type == e1000_nvm_flash_hw) |
|
684 e1000_fix_nvm_checksum_82571(hw); |
|
685 |
|
686 return e1000e_validate_nvm_checksum_generic(hw); |
|
687 } |
|
688 |
|
689 /** |
|
690 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon |
|
691 * @hw: pointer to the HW structure |
|
692 * @offset: offset within the EEPROM to be written to |
|
693 * @words: number of words to write |
|
694 * @data: 16 bit word(s) to be written to the EEPROM |
|
695 * |
|
696 * After checking for invalid values, poll the EEPROM to ensure the previous |
|
697 * command has completed before trying to write the next word. After write |
|
698 * poll for completion. |
|
699 * |
|
700 * If e1000e_update_nvm_checksum is not called after this function, the |
|
701 * EEPROM will most likely contain an invalid checksum. |
|
702 **/ |
|
703 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
|
704 u16 words, u16 *data) |
|
705 { |
|
706 struct e1000_nvm_info *nvm = &hw->nvm; |
|
707 u32 i, eewr = 0; |
|
708 s32 ret_val = 0; |
|
709 |
|
710 /* |
|
711 * A check for invalid values: offset too large, too many words, |
|
712 * and not enough words. |
|
713 */ |
|
714 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
|
715 (words == 0)) { |
|
716 e_dbg("nvm parameter(s) out of bounds\n"); |
|
717 return -E1000_ERR_NVM; |
|
718 } |
|
719 |
|
720 for (i = 0; i < words; i++) { |
|
721 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | |
|
722 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | |
|
723 E1000_NVM_RW_REG_START; |
|
724 |
|
725 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); |
|
726 if (ret_val) |
|
727 break; |
|
728 |
|
729 ew32(EEWR, eewr); |
|
730 |
|
731 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); |
|
732 if (ret_val) |
|
733 break; |
|
734 } |
|
735 |
|
736 return ret_val; |
|
737 } |
|
738 |
|
739 /** |
|
740 * e1000_get_cfg_done_82571 - Poll for configuration done |
|
741 * @hw: pointer to the HW structure |
|
742 * |
|
743 * Reads the management control register for the config done bit to be set. |
|
744 **/ |
|
745 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) |
|
746 { |
|
747 s32 timeout = PHY_CFG_TIMEOUT; |
|
748 |
|
749 while (timeout) { |
|
750 if (er32(EEMNGCTL) & |
|
751 E1000_NVM_CFG_DONE_PORT_0) |
|
752 break; |
|
753 msleep(1); |
|
754 timeout--; |
|
755 } |
|
756 if (!timeout) { |
|
757 e_dbg("MNG configuration cycle has not completed.\n"); |
|
758 return -E1000_ERR_RESET; |
|
759 } |
|
760 |
|
761 return 0; |
|
762 } |
|
763 |
|
764 /** |
|
765 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state |
|
766 * @hw: pointer to the HW structure |
|
767 * @active: true to enable LPLU, false to disable |
|
768 * |
|
769 * Sets the LPLU D0 state according to the active flag. When activating LPLU |
|
770 * this function also disables smart speed and vice versa. LPLU will not be |
|
771 * activated unless the device autonegotiation advertisement meets standards |
|
772 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function |
|
773 * pointer entry point only called by PHY setup routines. |
|
774 **/ |
|
775 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) |
|
776 { |
|
777 struct e1000_phy_info *phy = &hw->phy; |
|
778 s32 ret_val; |
|
779 u16 data; |
|
780 |
|
781 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
|
782 if (ret_val) |
|
783 return ret_val; |
|
784 |
|
785 if (active) { |
|
786 data |= IGP02E1000_PM_D0_LPLU; |
|
787 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
788 if (ret_val) |
|
789 return ret_val; |
|
790 |
|
791 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
792 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
793 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
794 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
795 if (ret_val) |
|
796 return ret_val; |
|
797 } else { |
|
798 data &= ~IGP02E1000_PM_D0_LPLU; |
|
799 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
800 /* |
|
801 * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
802 * during Dx states where the power conservation is most |
|
803 * important. During driver activity we should enable |
|
804 * SmartSpeed, so performance is maintained. |
|
805 */ |
|
806 if (phy->smart_speed == e1000_smart_speed_on) { |
|
807 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
808 &data); |
|
809 if (ret_val) |
|
810 return ret_val; |
|
811 |
|
812 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
813 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
814 data); |
|
815 if (ret_val) |
|
816 return ret_val; |
|
817 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
818 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
819 &data); |
|
820 if (ret_val) |
|
821 return ret_val; |
|
822 |
|
823 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
824 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
825 data); |
|
826 if (ret_val) |
|
827 return ret_val; |
|
828 } |
|
829 } |
|
830 |
|
831 return 0; |
|
832 } |
|
833 |
|
834 /** |
|
835 * e1000_reset_hw_82571 - Reset hardware |
|
836 * @hw: pointer to the HW structure |
|
837 * |
|
838 * This resets the hardware into a known state. |
|
839 **/ |
|
840 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) |
|
841 { |
|
842 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; |
|
843 s32 ret_val; |
|
844 u16 i = 0; |
|
845 |
|
846 /* |
|
847 * Prevent the PCI-E bus from sticking if there is no TLP connection |
|
848 * on the last TLP read/write transaction when MAC is reset. |
|
849 */ |
|
850 ret_val = e1000e_disable_pcie_master(hw); |
|
851 if (ret_val) |
|
852 e_dbg("PCI-E Master disable polling has failed.\n"); |
|
853 |
|
854 e_dbg("Masking off all interrupts\n"); |
|
855 ew32(IMC, 0xffffffff); |
|
856 |
|
857 ew32(RCTL, 0); |
|
858 ew32(TCTL, E1000_TCTL_PSP); |
|
859 e1e_flush(); |
|
860 |
|
861 msleep(10); |
|
862 |
|
863 /* |
|
864 * Must acquire the MDIO ownership before MAC reset. |
|
865 * Ownership defaults to firmware after a reset. |
|
866 */ |
|
867 switch (hw->mac.type) { |
|
868 case e1000_82573: |
|
869 case e1000_82574: |
|
870 case e1000_82583: |
|
871 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
872 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
873 |
|
874 do { |
|
875 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
876 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
877 |
|
878 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
|
879 break; |
|
880 |
|
881 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
882 |
|
883 msleep(2); |
|
884 i++; |
|
885 } while (i < MDIO_OWNERSHIP_TIMEOUT); |
|
886 break; |
|
887 default: |
|
888 break; |
|
889 } |
|
890 |
|
891 ctrl = er32(CTRL); |
|
892 |
|
893 e_dbg("Issuing a global reset to MAC\n"); |
|
894 ew32(CTRL, ctrl | E1000_CTRL_RST); |
|
895 |
|
896 if (hw->nvm.type == e1000_nvm_flash_hw) { |
|
897 udelay(10); |
|
898 ctrl_ext = er32(CTRL_EXT); |
|
899 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
900 ew32(CTRL_EXT, ctrl_ext); |
|
901 e1e_flush(); |
|
902 } |
|
903 |
|
904 ret_val = e1000e_get_auto_rd_done(hw); |
|
905 if (ret_val) |
|
906 /* We don't want to continue accessing MAC registers. */ |
|
907 return ret_val; |
|
908 |
|
909 /* |
|
910 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. |
|
911 * Need to wait for Phy configuration completion before accessing |
|
912 * NVM and Phy. |
|
913 */ |
|
914 |
|
915 switch (hw->mac.type) { |
|
916 case e1000_82573: |
|
917 case e1000_82574: |
|
918 case e1000_82583: |
|
919 msleep(25); |
|
920 break; |
|
921 default: |
|
922 break; |
|
923 } |
|
924 |
|
925 /* Clear any pending interrupt events. */ |
|
926 ew32(IMC, 0xffffffff); |
|
927 icr = er32(ICR); |
|
928 |
|
929 /* Install any alternate MAC address into RAR0 */ |
|
930 ret_val = e1000_check_alt_mac_addr_generic(hw); |
|
931 if (ret_val) |
|
932 return ret_val; |
|
933 |
|
934 e1000e_set_laa_state_82571(hw, true); |
|
935 |
|
936 /* Reinitialize the 82571 serdes link state machine */ |
|
937 if (hw->phy.media_type == e1000_media_type_internal_serdes) |
|
938 hw->mac.serdes_link_state = e1000_serdes_link_down; |
|
939 |
|
940 return 0; |
|
941 } |
|
942 |
|
943 /** |
|
944 * e1000_init_hw_82571 - Initialize hardware |
|
945 * @hw: pointer to the HW structure |
|
946 * |
|
947 * This inits the hardware readying it for operation. |
|
948 **/ |
|
949 static s32 e1000_init_hw_82571(struct e1000_hw *hw) |
|
950 { |
|
951 struct e1000_mac_info *mac = &hw->mac; |
|
952 u32 reg_data; |
|
953 s32 ret_val; |
|
954 u16 i, rar_count = mac->rar_entry_count; |
|
955 |
|
956 e1000_initialize_hw_bits_82571(hw); |
|
957 |
|
958 /* Initialize identification LED */ |
|
959 ret_val = e1000e_id_led_init(hw); |
|
960 if (ret_val) |
|
961 e_dbg("Error initializing identification LED\n"); |
|
962 /* This is not fatal and we should not stop init due to this */ |
|
963 |
|
964 /* Disabling VLAN filtering */ |
|
965 e_dbg("Initializing the IEEE VLAN\n"); |
|
966 mac->ops.clear_vfta(hw); |
|
967 |
|
968 /* Setup the receive address. */ |
|
969 /* |
|
970 * If, however, a locally administered address was assigned to the |
|
971 * 82571, we must reserve a RAR for it to work around an issue where |
|
972 * resetting one port will reload the MAC on the other port. |
|
973 */ |
|
974 if (e1000e_get_laa_state_82571(hw)) |
|
975 rar_count--; |
|
976 e1000e_init_rx_addrs(hw, rar_count); |
|
977 |
|
978 /* Zero out the Multicast HASH table */ |
|
979 e_dbg("Zeroing the MTA\n"); |
|
980 for (i = 0; i < mac->mta_reg_count; i++) |
|
981 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
|
982 |
|
983 /* Setup link and flow control */ |
|
984 ret_val = e1000_setup_link_82571(hw); |
|
985 |
|
986 /* Set the transmit descriptor write-back policy */ |
|
987 reg_data = er32(TXDCTL(0)); |
|
988 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
989 E1000_TXDCTL_FULL_TX_DESC_WB | |
|
990 E1000_TXDCTL_COUNT_DESC; |
|
991 ew32(TXDCTL(0), reg_data); |
|
992 |
|
993 /* ...for both queues. */ |
|
994 switch (mac->type) { |
|
995 case e1000_82573: |
|
996 case e1000_82574: |
|
997 case e1000_82583: |
|
998 e1000e_enable_tx_pkt_filtering(hw); |
|
999 reg_data = er32(GCR); |
|
1000 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
|
1001 ew32(GCR, reg_data); |
|
1002 break; |
|
1003 default: |
|
1004 reg_data = er32(TXDCTL(1)); |
|
1005 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
1006 E1000_TXDCTL_FULL_TX_DESC_WB | |
|
1007 E1000_TXDCTL_COUNT_DESC; |
|
1008 ew32(TXDCTL(1), reg_data); |
|
1009 break; |
|
1010 } |
|
1011 |
|
1012 /* |
|
1013 * Clear all of the statistics registers (clear on read). It is |
|
1014 * important that we do this after we have tried to establish link |
|
1015 * because the symbol error count will increment wildly if there |
|
1016 * is no link. |
|
1017 */ |
|
1018 e1000_clear_hw_cntrs_82571(hw); |
|
1019 |
|
1020 return ret_val; |
|
1021 } |
|
1022 |
|
1023 /** |
|
1024 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits |
|
1025 * @hw: pointer to the HW structure |
|
1026 * |
|
1027 * Initializes required hardware-dependent bits needed for normal operation. |
|
1028 **/ |
|
1029 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) |
|
1030 { |
|
1031 u32 reg; |
|
1032 |
|
1033 /* Transmit Descriptor Control 0 */ |
|
1034 reg = er32(TXDCTL(0)); |
|
1035 reg |= (1 << 22); |
|
1036 ew32(TXDCTL(0), reg); |
|
1037 |
|
1038 /* Transmit Descriptor Control 1 */ |
|
1039 reg = er32(TXDCTL(1)); |
|
1040 reg |= (1 << 22); |
|
1041 ew32(TXDCTL(1), reg); |
|
1042 |
|
1043 /* Transmit Arbitration Control 0 */ |
|
1044 reg = er32(TARC(0)); |
|
1045 reg &= ~(0xF << 27); /* 30:27 */ |
|
1046 switch (hw->mac.type) { |
|
1047 case e1000_82571: |
|
1048 case e1000_82572: |
|
1049 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); |
|
1050 break; |
|
1051 default: |
|
1052 break; |
|
1053 } |
|
1054 ew32(TARC(0), reg); |
|
1055 |
|
1056 /* Transmit Arbitration Control 1 */ |
|
1057 reg = er32(TARC(1)); |
|
1058 switch (hw->mac.type) { |
|
1059 case e1000_82571: |
|
1060 case e1000_82572: |
|
1061 reg &= ~((1 << 29) | (1 << 30)); |
|
1062 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); |
|
1063 if (er32(TCTL) & E1000_TCTL_MULR) |
|
1064 reg &= ~(1 << 28); |
|
1065 else |
|
1066 reg |= (1 << 28); |
|
1067 ew32(TARC(1), reg); |
|
1068 break; |
|
1069 default: |
|
1070 break; |
|
1071 } |
|
1072 |
|
1073 /* Device Control */ |
|
1074 switch (hw->mac.type) { |
|
1075 case e1000_82573: |
|
1076 case e1000_82574: |
|
1077 case e1000_82583: |
|
1078 reg = er32(CTRL); |
|
1079 reg &= ~(1 << 29); |
|
1080 ew32(CTRL, reg); |
|
1081 break; |
|
1082 default: |
|
1083 break; |
|
1084 } |
|
1085 |
|
1086 /* Extended Device Control */ |
|
1087 switch (hw->mac.type) { |
|
1088 case e1000_82573: |
|
1089 case e1000_82574: |
|
1090 case e1000_82583: |
|
1091 reg = er32(CTRL_EXT); |
|
1092 reg &= ~(1 << 23); |
|
1093 reg |= (1 << 22); |
|
1094 ew32(CTRL_EXT, reg); |
|
1095 break; |
|
1096 default: |
|
1097 break; |
|
1098 } |
|
1099 |
|
1100 if (hw->mac.type == e1000_82571) { |
|
1101 reg = er32(PBA_ECC); |
|
1102 reg |= E1000_PBA_ECC_CORR_EN; |
|
1103 ew32(PBA_ECC, reg); |
|
1104 } |
|
1105 /* |
|
1106 * Workaround for hardware errata. |
|
1107 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 |
|
1108 */ |
|
1109 |
|
1110 if ((hw->mac.type == e1000_82571) || |
|
1111 (hw->mac.type == e1000_82572)) { |
|
1112 reg = er32(CTRL_EXT); |
|
1113 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; |
|
1114 ew32(CTRL_EXT, reg); |
|
1115 } |
|
1116 |
|
1117 |
|
1118 /* PCI-Ex Control Registers */ |
|
1119 switch (hw->mac.type) { |
|
1120 case e1000_82574: |
|
1121 case e1000_82583: |
|
1122 reg = er32(GCR); |
|
1123 reg |= (1 << 22); |
|
1124 ew32(GCR, reg); |
|
1125 |
|
1126 /* |
|
1127 * Workaround for hardware errata. |
|
1128 * apply workaround for hardware errata documented in errata |
|
1129 * docs Fixes issue where some error prone or unreliable PCIe |
|
1130 * completions are occurring, particularly with ASPM enabled. |
|
1131 * Without fix, issue can cause tx timeouts. |
|
1132 */ |
|
1133 reg = er32(GCR2); |
|
1134 reg |= 1; |
|
1135 ew32(GCR2, reg); |
|
1136 break; |
|
1137 default: |
|
1138 break; |
|
1139 } |
|
1140 |
|
1141 return; |
|
1142 } |
|
1143 |
|
1144 /** |
|
1145 * e1000_clear_vfta_82571 - Clear VLAN filter table |
|
1146 * @hw: pointer to the HW structure |
|
1147 * |
|
1148 * Clears the register array which contains the VLAN filter table by |
|
1149 * setting all the values to 0. |
|
1150 **/ |
|
1151 static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
|
1152 { |
|
1153 u32 offset; |
|
1154 u32 vfta_value = 0; |
|
1155 u32 vfta_offset = 0; |
|
1156 u32 vfta_bit_in_reg = 0; |
|
1157 |
|
1158 switch (hw->mac.type) { |
|
1159 case e1000_82573: |
|
1160 case e1000_82574: |
|
1161 case e1000_82583: |
|
1162 if (hw->mng_cookie.vlan_id != 0) { |
|
1163 /* |
|
1164 * The VFTA is a 4096b bit-field, each identifying |
|
1165 * a single VLAN ID. The following operations |
|
1166 * determine which 32b entry (i.e. offset) into the |
|
1167 * array we want to set the VLAN ID (i.e. bit) of |
|
1168 * the manageability unit. |
|
1169 */ |
|
1170 vfta_offset = (hw->mng_cookie.vlan_id >> |
|
1171 E1000_VFTA_ENTRY_SHIFT) & |
|
1172 E1000_VFTA_ENTRY_MASK; |
|
1173 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
|
1174 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
|
1175 } |
|
1176 break; |
|
1177 default: |
|
1178 break; |
|
1179 } |
|
1180 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
1181 /* |
|
1182 * If the offset we want to clear is the same offset of the |
|
1183 * manageability VLAN ID, then clear all bits except that of |
|
1184 * the manageability unit. |
|
1185 */ |
|
1186 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
1187 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); |
|
1188 e1e_flush(); |
|
1189 } |
|
1190 } |
|
1191 |
|
1192 /** |
|
1193 * e1000_check_mng_mode_82574 - Check manageability is enabled |
|
1194 * @hw: pointer to the HW structure |
|
1195 * |
|
1196 * Reads the NVM Initialization Control Word 2 and returns true |
|
1197 * (>0) if any manageability is enabled, else false (0). |
|
1198 **/ |
|
1199 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) |
|
1200 { |
|
1201 u16 data; |
|
1202 |
|
1203 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); |
|
1204 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; |
|
1205 } |
|
1206 |
|
1207 /** |
|
1208 * e1000_led_on_82574 - Turn LED on |
|
1209 * @hw: pointer to the HW structure |
|
1210 * |
|
1211 * Turn LED on. |
|
1212 **/ |
|
1213 static s32 e1000_led_on_82574(struct e1000_hw *hw) |
|
1214 { |
|
1215 u32 ctrl; |
|
1216 u32 i; |
|
1217 |
|
1218 ctrl = hw->mac.ledctl_mode2; |
|
1219 if (!(E1000_STATUS_LU & er32(STATUS))) { |
|
1220 /* |
|
1221 * If no link, then turn LED on by setting the invert bit |
|
1222 * for each LED that's "on" (0x0E) in ledctl_mode2. |
|
1223 */ |
|
1224 for (i = 0; i < 4; i++) |
|
1225 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
1226 E1000_LEDCTL_MODE_LED_ON) |
|
1227 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); |
|
1228 } |
|
1229 ew32(LEDCTL, ctrl); |
|
1230 |
|
1231 return 0; |
|
1232 } |
|
1233 |
|
1234 /** |
|
1235 * e1000_setup_link_82571 - Setup flow control and link settings |
|
1236 * @hw: pointer to the HW structure |
|
1237 * |
|
1238 * Determines which flow control settings to use, then configures flow |
|
1239 * control. Calls the appropriate media-specific link configuration |
|
1240 * function. Assuming the adapter has a valid link partner, a valid link |
|
1241 * should be established. Assumes the hardware has previously been reset |
|
1242 * and the transmitter and receiver are not enabled. |
|
1243 **/ |
|
1244 static s32 e1000_setup_link_82571(struct e1000_hw *hw) |
|
1245 { |
|
1246 /* |
|
1247 * 82573 does not have a word in the NVM to determine |
|
1248 * the default flow control setting, so we explicitly |
|
1249 * set it to full. |
|
1250 */ |
|
1251 switch (hw->mac.type) { |
|
1252 case e1000_82573: |
|
1253 case e1000_82574: |
|
1254 case e1000_82583: |
|
1255 if (hw->fc.requested_mode == e1000_fc_default) |
|
1256 hw->fc.requested_mode = e1000_fc_full; |
|
1257 break; |
|
1258 default: |
|
1259 break; |
|
1260 } |
|
1261 |
|
1262 return e1000e_setup_link(hw); |
|
1263 } |
|
1264 |
|
1265 /** |
|
1266 * e1000_setup_copper_link_82571 - Configure copper link settings |
|
1267 * @hw: pointer to the HW structure |
|
1268 * |
|
1269 * Configures the link for auto-neg or forced speed and duplex. Then we check |
|
1270 * for link, once link is established calls to configure collision distance |
|
1271 * and flow control are called. |
|
1272 **/ |
|
1273 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) |
|
1274 { |
|
1275 u32 ctrl; |
|
1276 s32 ret_val; |
|
1277 |
|
1278 ctrl = er32(CTRL); |
|
1279 ctrl |= E1000_CTRL_SLU; |
|
1280 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1281 ew32(CTRL, ctrl); |
|
1282 |
|
1283 switch (hw->phy.type) { |
|
1284 case e1000_phy_m88: |
|
1285 case e1000_phy_bm: |
|
1286 ret_val = e1000e_copper_link_setup_m88(hw); |
|
1287 break; |
|
1288 case e1000_phy_igp_2: |
|
1289 ret_val = e1000e_copper_link_setup_igp(hw); |
|
1290 break; |
|
1291 default: |
|
1292 return -E1000_ERR_PHY; |
|
1293 break; |
|
1294 } |
|
1295 |
|
1296 if (ret_val) |
|
1297 return ret_val; |
|
1298 |
|
1299 ret_val = e1000e_setup_copper_link(hw); |
|
1300 |
|
1301 return ret_val; |
|
1302 } |
|
1303 |
|
1304 /** |
|
1305 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes |
|
1306 * @hw: pointer to the HW structure |
|
1307 * |
|
1308 * Configures collision distance and flow control for fiber and serdes links. |
|
1309 * Upon successful setup, poll for link. |
|
1310 **/ |
|
1311 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) |
|
1312 { |
|
1313 switch (hw->mac.type) { |
|
1314 case e1000_82571: |
|
1315 case e1000_82572: |
|
1316 /* |
|
1317 * If SerDes loopback mode is entered, there is no form |
|
1318 * of reset to take the adapter out of that mode. So we |
|
1319 * have to explicitly take the adapter out of loopback |
|
1320 * mode. This prevents drivers from twiddling their thumbs |
|
1321 * if another tool failed to take it out of loopback mode. |
|
1322 */ |
|
1323 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
|
1324 break; |
|
1325 default: |
|
1326 break; |
|
1327 } |
|
1328 |
|
1329 return e1000e_setup_fiber_serdes_link(hw); |
|
1330 } |
|
1331 |
|
1332 /** |
|
1333 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) |
|
1334 * @hw: pointer to the HW structure |
|
1335 * |
|
1336 * Reports the link state as up or down. |
|
1337 * |
|
1338 * If autonegotiation is supported by the link partner, the link state is |
|
1339 * determined by the result of autonegotiation. This is the most likely case. |
|
1340 * If autonegotiation is not supported by the link partner, and the link |
|
1341 * has a valid signal, force the link up. |
|
1342 * |
|
1343 * The link state is represented internally here by 4 states: |
|
1344 * |
|
1345 * 1) down |
|
1346 * 2) autoneg_progress |
|
1347 * 3) autoneg_complete (the link successfully autonegotiated) |
|
1348 * 4) forced_up (the link has been forced up, it did not autonegotiate) |
|
1349 * |
|
1350 **/ |
|
1351 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
|
1352 { |
|
1353 struct e1000_mac_info *mac = &hw->mac; |
|
1354 u32 rxcw; |
|
1355 u32 ctrl; |
|
1356 u32 status; |
|
1357 s32 ret_val = 0; |
|
1358 |
|
1359 ctrl = er32(CTRL); |
|
1360 status = er32(STATUS); |
|
1361 rxcw = er32(RXCW); |
|
1362 |
|
1363 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { |
|
1364 |
|
1365 /* Receiver is synchronized with no invalid bits. */ |
|
1366 switch (mac->serdes_link_state) { |
|
1367 case e1000_serdes_link_autoneg_complete: |
|
1368 if (!(status & E1000_STATUS_LU)) { |
|
1369 /* |
|
1370 * We have lost link, retry autoneg before |
|
1371 * reporting link failure |
|
1372 */ |
|
1373 mac->serdes_link_state = |
|
1374 e1000_serdes_link_autoneg_progress; |
|
1375 mac->serdes_has_link = false; |
|
1376 e_dbg("AN_UP -> AN_PROG\n"); |
|
1377 } |
|
1378 break; |
|
1379 |
|
1380 case e1000_serdes_link_forced_up: |
|
1381 /* |
|
1382 * If we are receiving /C/ ordered sets, re-enable |
|
1383 * auto-negotiation in the TXCW register and disable |
|
1384 * forced link in the Device Control register in an |
|
1385 * attempt to auto-negotiate with our link partner. |
|
1386 */ |
|
1387 if (rxcw & E1000_RXCW_C) { |
|
1388 /* Enable autoneg, and unforce link up */ |
|
1389 ew32(TXCW, mac->txcw); |
|
1390 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
1391 mac->serdes_link_state = |
|
1392 e1000_serdes_link_autoneg_progress; |
|
1393 mac->serdes_has_link = false; |
|
1394 e_dbg("FORCED_UP -> AN_PROG\n"); |
|
1395 } |
|
1396 break; |
|
1397 |
|
1398 case e1000_serdes_link_autoneg_progress: |
|
1399 if (rxcw & E1000_RXCW_C) { |
|
1400 /* |
|
1401 * We received /C/ ordered sets, meaning the |
|
1402 * link partner has autonegotiated, and we can |
|
1403 * trust the Link Up (LU) status bit. |
|
1404 */ |
|
1405 if (status & E1000_STATUS_LU) { |
|
1406 mac->serdes_link_state = |
|
1407 e1000_serdes_link_autoneg_complete; |
|
1408 e_dbg("AN_PROG -> AN_UP\n"); |
|
1409 mac->serdes_has_link = true; |
|
1410 } else { |
|
1411 /* Autoneg completed, but failed. */ |
|
1412 mac->serdes_link_state = |
|
1413 e1000_serdes_link_down; |
|
1414 e_dbg("AN_PROG -> DOWN\n"); |
|
1415 } |
|
1416 } else { |
|
1417 /* |
|
1418 * The link partner did not autoneg. |
|
1419 * Force link up and full duplex, and change |
|
1420 * state to forced. |
|
1421 */ |
|
1422 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
|
1423 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
1424 ew32(CTRL, ctrl); |
|
1425 |
|
1426 /* Configure Flow Control after link up. */ |
|
1427 ret_val = e1000e_config_fc_after_link_up(hw); |
|
1428 if (ret_val) { |
|
1429 e_dbg("Error config flow control\n"); |
|
1430 break; |
|
1431 } |
|
1432 mac->serdes_link_state = |
|
1433 e1000_serdes_link_forced_up; |
|
1434 mac->serdes_has_link = true; |
|
1435 e_dbg("AN_PROG -> FORCED_UP\n"); |
|
1436 } |
|
1437 break; |
|
1438 |
|
1439 case e1000_serdes_link_down: |
|
1440 default: |
|
1441 /* |
|
1442 * The link was down but the receiver has now gained |
|
1443 * valid sync, so lets see if we can bring the link |
|
1444 * up. |
|
1445 */ |
|
1446 ew32(TXCW, mac->txcw); |
|
1447 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
1448 mac->serdes_link_state = |
|
1449 e1000_serdes_link_autoneg_progress; |
|
1450 e_dbg("DOWN -> AN_PROG\n"); |
|
1451 break; |
|
1452 } |
|
1453 } else { |
|
1454 if (!(rxcw & E1000_RXCW_SYNCH)) { |
|
1455 mac->serdes_has_link = false; |
|
1456 mac->serdes_link_state = e1000_serdes_link_down; |
|
1457 e_dbg("ANYSTATE -> DOWN\n"); |
|
1458 } else { |
|
1459 /* |
|
1460 * We have sync, and can tolerate one invalid (IV) |
|
1461 * codeword before declaring link down, so reread |
|
1462 * to look again. |
|
1463 */ |
|
1464 udelay(10); |
|
1465 rxcw = er32(RXCW); |
|
1466 if (rxcw & E1000_RXCW_IV) { |
|
1467 mac->serdes_link_state = e1000_serdes_link_down; |
|
1468 mac->serdes_has_link = false; |
|
1469 e_dbg("ANYSTATE -> DOWN\n"); |
|
1470 } |
|
1471 } |
|
1472 } |
|
1473 |
|
1474 return ret_val; |
|
1475 } |
|
1476 |
|
1477 /** |
|
1478 * e1000_valid_led_default_82571 - Verify a valid default LED config |
|
1479 * @hw: pointer to the HW structure |
|
1480 * @data: pointer to the NVM (EEPROM) |
|
1481 * |
|
1482 * Read the EEPROM for the current default LED configuration. If the |
|
1483 * LED configuration is not valid, set to a valid LED configuration. |
|
1484 **/ |
|
1485 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) |
|
1486 { |
|
1487 s32 ret_val; |
|
1488 |
|
1489 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
1490 if (ret_val) { |
|
1491 e_dbg("NVM Read Error\n"); |
|
1492 return ret_val; |
|
1493 } |
|
1494 |
|
1495 switch (hw->mac.type) { |
|
1496 case e1000_82573: |
|
1497 case e1000_82574: |
|
1498 case e1000_82583: |
|
1499 if (*data == ID_LED_RESERVED_F746) |
|
1500 *data = ID_LED_DEFAULT_82573; |
|
1501 break; |
|
1502 default: |
|
1503 if (*data == ID_LED_RESERVED_0000 || |
|
1504 *data == ID_LED_RESERVED_FFFF) |
|
1505 *data = ID_LED_DEFAULT; |
|
1506 break; |
|
1507 } |
|
1508 |
|
1509 return 0; |
|
1510 } |
|
1511 |
|
1512 /** |
|
1513 * e1000e_get_laa_state_82571 - Get locally administered address state |
|
1514 * @hw: pointer to the HW structure |
|
1515 * |
|
1516 * Retrieve and return the current locally administered address state. |
|
1517 **/ |
|
1518 bool e1000e_get_laa_state_82571(struct e1000_hw *hw) |
|
1519 { |
|
1520 if (hw->mac.type != e1000_82571) |
|
1521 return false; |
|
1522 |
|
1523 return hw->dev_spec.e82571.laa_is_present; |
|
1524 } |
|
1525 |
|
1526 /** |
|
1527 * e1000e_set_laa_state_82571 - Set locally administered address state |
|
1528 * @hw: pointer to the HW structure |
|
1529 * @state: enable/disable locally administered address |
|
1530 * |
|
1531 * Enable/Disable the current locally administered address state. |
|
1532 **/ |
|
1533 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) |
|
1534 { |
|
1535 if (hw->mac.type != e1000_82571) |
|
1536 return; |
|
1537 |
|
1538 hw->dev_spec.e82571.laa_is_present = state; |
|
1539 |
|
1540 /* If workaround is activated... */ |
|
1541 if (state) |
|
1542 /* |
|
1543 * Hold a copy of the LAA in RAR[14] This is done so that |
|
1544 * between the time RAR[0] gets clobbered and the time it |
|
1545 * gets fixed, the actual LAA is in one of the RARs and no |
|
1546 * incoming packets directed to this port are dropped. |
|
1547 * Eventually the LAA will be in RAR[0] and RAR[14]. |
|
1548 */ |
|
1549 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); |
|
1550 } |
|
1551 |
|
1552 /** |
|
1553 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum |
|
1554 * @hw: pointer to the HW structure |
|
1555 * |
|
1556 * Verifies that the EEPROM has completed the update. After updating the |
|
1557 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If |
|
1558 * the checksum fix is not implemented, we need to set the bit and update |
|
1559 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, |
|
1560 * we need to return bad checksum. |
|
1561 **/ |
|
1562 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) |
|
1563 { |
|
1564 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1565 s32 ret_val; |
|
1566 u16 data; |
|
1567 |
|
1568 if (nvm->type != e1000_nvm_flash_hw) |
|
1569 return 0; |
|
1570 |
|
1571 /* |
|
1572 * Check bit 4 of word 10h. If it is 0, firmware is done updating |
|
1573 * 10h-12h. Checksum may need to be fixed. |
|
1574 */ |
|
1575 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); |
|
1576 if (ret_val) |
|
1577 return ret_val; |
|
1578 |
|
1579 if (!(data & 0x10)) { |
|
1580 /* |
|
1581 * Read 0x23 and check bit 15. This bit is a 1 |
|
1582 * when the checksum has already been fixed. If |
|
1583 * the checksum is still wrong and this bit is a |
|
1584 * 1, we need to return bad checksum. Otherwise, |
|
1585 * we need to set this bit to a 1 and update the |
|
1586 * checksum. |
|
1587 */ |
|
1588 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); |
|
1589 if (ret_val) |
|
1590 return ret_val; |
|
1591 |
|
1592 if (!(data & 0x8000)) { |
|
1593 data |= 0x8000; |
|
1594 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); |
|
1595 if (ret_val) |
|
1596 return ret_val; |
|
1597 ret_val = e1000e_update_nvm_checksum(hw); |
|
1598 } |
|
1599 } |
|
1600 |
|
1601 return 0; |
|
1602 } |
|
1603 |
|
1604 /** |
|
1605 * e1000_read_mac_addr_82571 - Read device MAC address |
|
1606 * @hw: pointer to the HW structure |
|
1607 **/ |
|
1608 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) |
|
1609 { |
|
1610 s32 ret_val = 0; |
|
1611 |
|
1612 /* |
|
1613 * If there's an alternate MAC address place it in RAR0 |
|
1614 * so that it will override the Si installed default perm |
|
1615 * address. |
|
1616 */ |
|
1617 ret_val = e1000_check_alt_mac_addr_generic(hw); |
|
1618 if (ret_val) |
|
1619 goto out; |
|
1620 |
|
1621 ret_val = e1000_read_mac_addr_generic(hw); |
|
1622 |
|
1623 out: |
|
1624 return ret_val; |
|
1625 } |
|
1626 |
|
1627 /** |
|
1628 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down |
|
1629 * @hw: pointer to the HW structure |
|
1630 * |
|
1631 * In the case of a PHY power down to save power, or to turn off link during a |
|
1632 * driver unload, or wake on lan is not enabled, remove the link. |
|
1633 **/ |
|
1634 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) |
|
1635 { |
|
1636 struct e1000_phy_info *phy = &hw->phy; |
|
1637 struct e1000_mac_info *mac = &hw->mac; |
|
1638 |
|
1639 if (!(phy->ops.check_reset_block)) |
|
1640 return; |
|
1641 |
|
1642 /* If the management interface is not enabled, then power down */ |
|
1643 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) |
|
1644 e1000_power_down_phy_copper(hw); |
|
1645 |
|
1646 return; |
|
1647 } |
|
1648 |
|
1649 /** |
|
1650 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters |
|
1651 * @hw: pointer to the HW structure |
|
1652 * |
|
1653 * Clears the hardware counters by reading the counter registers. |
|
1654 **/ |
|
1655 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) |
|
1656 { |
|
1657 e1000e_clear_hw_cntrs_base(hw); |
|
1658 |
|
1659 er32(PRC64); |
|
1660 er32(PRC127); |
|
1661 er32(PRC255); |
|
1662 er32(PRC511); |
|
1663 er32(PRC1023); |
|
1664 er32(PRC1522); |
|
1665 er32(PTC64); |
|
1666 er32(PTC127); |
|
1667 er32(PTC255); |
|
1668 er32(PTC511); |
|
1669 er32(PTC1023); |
|
1670 er32(PTC1522); |
|
1671 |
|
1672 er32(ALGNERRC); |
|
1673 er32(RXERRC); |
|
1674 er32(TNCRS); |
|
1675 er32(CEXTERR); |
|
1676 er32(TSCTC); |
|
1677 er32(TSCTFC); |
|
1678 |
|
1679 er32(MGTPRC); |
|
1680 er32(MGTPDC); |
|
1681 er32(MGTPTC); |
|
1682 |
|
1683 er32(IAC); |
|
1684 er32(ICRXOC); |
|
1685 |
|
1686 er32(ICRXPTC); |
|
1687 er32(ICRXATC); |
|
1688 er32(ICTXPTC); |
|
1689 er32(ICTXATC); |
|
1690 er32(ICTXQEC); |
|
1691 er32(ICTXQMTC); |
|
1692 er32(ICRXDMTC); |
|
1693 } |
|
1694 |
|
1695 static struct e1000_mac_operations e82571_mac_ops = { |
|
1696 /* .check_mng_mode: mac type dependent */ |
|
1697 /* .check_for_link: media type dependent */ |
|
1698 .id_led_init = e1000e_id_led_init, |
|
1699 .cleanup_led = e1000e_cleanup_led_generic, |
|
1700 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, |
|
1701 .get_bus_info = e1000e_get_bus_info_pcie, |
|
1702 .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
|
1703 /* .get_link_up_info: media type dependent */ |
|
1704 /* .led_on: mac type dependent */ |
|
1705 .led_off = e1000e_led_off_generic, |
|
1706 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
|
1707 .write_vfta = e1000_write_vfta_generic, |
|
1708 .clear_vfta = e1000_clear_vfta_82571, |
|
1709 .reset_hw = e1000_reset_hw_82571, |
|
1710 .init_hw = e1000_init_hw_82571, |
|
1711 .setup_link = e1000_setup_link_82571, |
|
1712 /* .setup_physical_interface: media type dependent */ |
|
1713 .setup_led = e1000e_setup_led_generic, |
|
1714 .read_mac_addr = e1000_read_mac_addr_82571, |
|
1715 }; |
|
1716 |
|
1717 static struct e1000_phy_operations e82_phy_ops_igp = { |
|
1718 .acquire = e1000_get_hw_semaphore_82571, |
|
1719 .check_polarity = e1000_check_polarity_igp, |
|
1720 .check_reset_block = e1000e_check_reset_block_generic, |
|
1721 .commit = NULL, |
|
1722 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
|
1723 .get_cfg_done = e1000_get_cfg_done_82571, |
|
1724 .get_cable_length = e1000e_get_cable_length_igp_2, |
|
1725 .get_info = e1000e_get_phy_info_igp, |
|
1726 .read_reg = e1000e_read_phy_reg_igp, |
|
1727 .release = e1000_put_hw_semaphore_82571, |
|
1728 .reset = e1000e_phy_hw_reset_generic, |
|
1729 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1730 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1731 .write_reg = e1000e_write_phy_reg_igp, |
|
1732 .cfg_on_link_up = NULL, |
|
1733 }; |
|
1734 |
|
1735 static struct e1000_phy_operations e82_phy_ops_m88 = { |
|
1736 .acquire = e1000_get_hw_semaphore_82571, |
|
1737 .check_polarity = e1000_check_polarity_m88, |
|
1738 .check_reset_block = e1000e_check_reset_block_generic, |
|
1739 .commit = e1000e_phy_sw_reset, |
|
1740 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
|
1741 .get_cfg_done = e1000e_get_cfg_done, |
|
1742 .get_cable_length = e1000e_get_cable_length_m88, |
|
1743 .get_info = e1000e_get_phy_info_m88, |
|
1744 .read_reg = e1000e_read_phy_reg_m88, |
|
1745 .release = e1000_put_hw_semaphore_82571, |
|
1746 .reset = e1000e_phy_hw_reset_generic, |
|
1747 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1748 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1749 .write_reg = e1000e_write_phy_reg_m88, |
|
1750 .cfg_on_link_up = NULL, |
|
1751 }; |
|
1752 |
|
1753 static struct e1000_phy_operations e82_phy_ops_bm = { |
|
1754 .acquire = e1000_get_hw_semaphore_82571, |
|
1755 .check_polarity = e1000_check_polarity_m88, |
|
1756 .check_reset_block = e1000e_check_reset_block_generic, |
|
1757 .commit = e1000e_phy_sw_reset, |
|
1758 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
|
1759 .get_cfg_done = e1000e_get_cfg_done, |
|
1760 .get_cable_length = e1000e_get_cable_length_m88, |
|
1761 .get_info = e1000e_get_phy_info_m88, |
|
1762 .read_reg = e1000e_read_phy_reg_bm2, |
|
1763 .release = e1000_put_hw_semaphore_82571, |
|
1764 .reset = e1000e_phy_hw_reset_generic, |
|
1765 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1766 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1767 .write_reg = e1000e_write_phy_reg_bm2, |
|
1768 .cfg_on_link_up = NULL, |
|
1769 }; |
|
1770 |
|
1771 static struct e1000_nvm_operations e82571_nvm_ops = { |
|
1772 .acquire = e1000_acquire_nvm_82571, |
|
1773 .read = e1000e_read_nvm_eerd, |
|
1774 .release = e1000_release_nvm_82571, |
|
1775 .update = e1000_update_nvm_checksum_82571, |
|
1776 .valid_led_default = e1000_valid_led_default_82571, |
|
1777 .validate = e1000_validate_nvm_checksum_82571, |
|
1778 .write = e1000_write_nvm_82571, |
|
1779 }; |
|
1780 |
|
1781 struct e1000_info e1000_82571_info = { |
|
1782 .mac = e1000_82571, |
|
1783 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1784 | FLAG_HAS_JUMBO_FRAMES |
|
1785 | FLAG_HAS_WOL |
|
1786 | FLAG_APME_IN_CTRL3 |
|
1787 | FLAG_RX_CSUM_ENABLED |
|
1788 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
1789 | FLAG_HAS_SMART_POWER_DOWN |
|
1790 | FLAG_RESET_OVERWRITES_LAA /* errata */ |
|
1791 | FLAG_TARC_SPEED_MODE_BIT /* errata */ |
|
1792 | FLAG_APME_CHECK_PORT_B, |
|
1793 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */ |
|
1794 .pba = 38, |
|
1795 .max_hw_frame_size = DEFAULT_JUMBO, |
|
1796 .get_variants = e1000_get_variants_82571, |
|
1797 .mac_ops = &e82571_mac_ops, |
|
1798 .phy_ops = &e82_phy_ops_igp, |
|
1799 .nvm_ops = &e82571_nvm_ops, |
|
1800 }; |
|
1801 |
|
1802 struct e1000_info e1000_82572_info = { |
|
1803 .mac = e1000_82572, |
|
1804 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1805 | FLAG_HAS_JUMBO_FRAMES |
|
1806 | FLAG_HAS_WOL |
|
1807 | FLAG_APME_IN_CTRL3 |
|
1808 | FLAG_RX_CSUM_ENABLED |
|
1809 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
1810 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
|
1811 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */ |
|
1812 .pba = 38, |
|
1813 .max_hw_frame_size = DEFAULT_JUMBO, |
|
1814 .get_variants = e1000_get_variants_82571, |
|
1815 .mac_ops = &e82571_mac_ops, |
|
1816 .phy_ops = &e82_phy_ops_igp, |
|
1817 .nvm_ops = &e82571_nvm_ops, |
|
1818 }; |
|
1819 |
|
1820 struct e1000_info e1000_82573_info = { |
|
1821 .mac = e1000_82573, |
|
1822 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1823 | FLAG_HAS_WOL |
|
1824 | FLAG_APME_IN_CTRL3 |
|
1825 | FLAG_RX_CSUM_ENABLED |
|
1826 | FLAG_HAS_SMART_POWER_DOWN |
|
1827 | FLAG_HAS_AMT |
|
1828 | FLAG_HAS_SWSM_ON_LOAD, |
|
1829 .pba = 20, |
|
1830 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
|
1831 .get_variants = e1000_get_variants_82571, |
|
1832 .mac_ops = &e82571_mac_ops, |
|
1833 .phy_ops = &e82_phy_ops_m88, |
|
1834 .nvm_ops = &e82571_nvm_ops, |
|
1835 }; |
|
1836 |
|
1837 struct e1000_info e1000_82574_info = { |
|
1838 .mac = e1000_82574, |
|
1839 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1840 | FLAG_HAS_MSIX |
|
1841 | FLAG_HAS_JUMBO_FRAMES |
|
1842 | FLAG_HAS_WOL |
|
1843 | FLAG_APME_IN_CTRL3 |
|
1844 | FLAG_RX_CSUM_ENABLED |
|
1845 | FLAG_HAS_SMART_POWER_DOWN |
|
1846 | FLAG_HAS_AMT |
|
1847 | FLAG_HAS_CTRLEXT_ON_LOAD, |
|
1848 .pba = 20, |
|
1849 .max_hw_frame_size = DEFAULT_JUMBO, |
|
1850 .get_variants = e1000_get_variants_82571, |
|
1851 .mac_ops = &e82571_mac_ops, |
|
1852 .phy_ops = &e82_phy_ops_bm, |
|
1853 .nvm_ops = &e82571_nvm_ops, |
|
1854 }; |
|
1855 |
|
1856 struct e1000_info e1000_82583_info = { |
|
1857 .mac = e1000_82583, |
|
1858 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
1859 | FLAG_HAS_WOL |
|
1860 | FLAG_APME_IN_CTRL3 |
|
1861 | FLAG_RX_CSUM_ENABLED |
|
1862 | FLAG_HAS_SMART_POWER_DOWN |
|
1863 | FLAG_HAS_AMT |
|
1864 | FLAG_HAS_CTRLEXT_ON_LOAD, |
|
1865 .pba = 20, |
|
1866 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
|
1867 .get_variants = e1000_get_variants_82571, |
|
1868 .mac_ops = &e82571_mac_ops, |
|
1869 .phy_ops = &e82_phy_ops_bm, |
|
1870 .nvm_ops = &e82571_nvm_ops, |
|
1871 }; |
|
1872 |