1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2009 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /*

    30  * 82571EB Gigabit Ethernet Controller

    31  * 82571EB Gigabit Ethernet Controller (Copper)

    32  * 82571EB Gigabit Ethernet Controller (Fiber)

    33  * 82571EB Dual Port Gigabit Mezzanine Adapter

    34  * 82571EB Quad Port Gigabit Mezzanine Adapter

    35  * 82571PT Gigabit PT Quad Port Server ExpressModule

    36  * 82572EI Gigabit Ethernet Controller (Copper)

    37  * 82572EI Gigabit Ethernet Controller (Fiber)

    38  * 82572EI Gigabit Ethernet Controller

    39  * 82573V Gigabit Ethernet Controller (Copper)

    40  * 82573E Gigabit Ethernet Controller (Copper)

    41  * 82573L Gigabit Ethernet Controller

    42  * 82574L Gigabit Network Connection

    43  * 82583V Gigabit Network Connection

    44  */

    45 

    46 #include "e1000-2.6.34-ethercat.h"

    47 

    48 #define ID_LED_RESERVED_F746 0xF746

    49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \

    50 			      (ID_LED_OFF1_ON2  <<  8) | \

    51 			      (ID_LED_DEF1_DEF2 <<  4) | \

    52 			      (ID_LED_DEF1_DEF2))

    53 

    54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000

    55 

    56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */

    57 

    58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);

    61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

    62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

    63 				      u16 words, u16 *data);

    64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);

    65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);

    66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);

    67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);

    68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);

    69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);

    70 static s32 e1000_led_on_82574(struct e1000_hw *hw);

    71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);

    72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);

    73 

    74 /**

    75  *  e1000_init_phy_params_82571 - Init PHY func ptrs.

    76  *  @hw: pointer to the HW structure

    77  **/

    78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)

    79 {

    80 	struct e1000_phy_info *phy = &hw->phy;

    81 	s32 ret_val;

    82 

    83 	if (hw->phy.media_type != e1000_media_type_copper) {

    84 		phy->type = e1000_phy_none;

    85 		return 0;

    86 	}

    87 

    88 	phy->addr			 = 1;

    89 	phy->autoneg_mask		 = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    90 	phy->reset_delay_us		 = 100;

    91 

    92 	phy->ops.power_up		 = e1000_power_up_phy_copper;

    93 	phy->ops.power_down		 = e1000_power_down_phy_copper_82571;

    94 

    95 	switch (hw->mac.type) {

    96 	case e1000_82571:

    97 	case e1000_82572:

    98 		phy->type		 = e1000_phy_igp_2;

    99 		break;

   100 	case e1000_82573:

   101 		phy->type		 = e1000_phy_m88;

   102 		break;

   103 	case e1000_82574:

   104 	case e1000_82583:

   105 		phy->type		 = e1000_phy_bm;

   106 		break;

   107 	default:

   108 		return -E1000_ERR_PHY;

   109 		break;

   110 	}

   111 

   112 	/* This can only be done after all function pointers are setup. */

   113 	ret_val = e1000_get_phy_id_82571(hw);

   114 

   115 	/* Verify phy id */

   116 	switch (hw->mac.type) {

   117 	case e1000_82571:

   118 	case e1000_82572:

   119 		if (phy->id != IGP01E1000_I_PHY_ID)

   120 			return -E1000_ERR_PHY;

   121 		break;

   122 	case e1000_82573:

   123 		if (phy->id != M88E1111_I_PHY_ID)

   124 			return -E1000_ERR_PHY;

   125 		break;

   126 	case e1000_82574:

   127 	case e1000_82583:

   128 		if (phy->id != BME1000_E_PHY_ID_R2)

   129 			return -E1000_ERR_PHY;

   130 		break;

   131 	default:

   132 		return -E1000_ERR_PHY;

   133 		break;

   134 	}

   135 

   136 	return 0;

   137 }

   138 

   139 /**

   140  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.

   141  *  @hw: pointer to the HW structure

   142  **/

   143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)

   144 {

   145 	struct e1000_nvm_info *nvm = &hw->nvm;

   146 	u32 eecd = er32(EECD);

   147 	u16 size;

   148 

   149 	nvm->opcode_bits = 8;

   150 	nvm->delay_usec = 1;

   151 	switch (nvm->override) {

   152 	case e1000_nvm_override_spi_large:

   153 		nvm->page_size = 32;

   154 		nvm->address_bits = 16;

   155 		break;

   156 	case e1000_nvm_override_spi_small:

   157 		nvm->page_size = 8;

   158 		nvm->address_bits = 8;

   159 		break;

   160 	default:

   161 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   162 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   163 		break;

   164 	}

   165 

   166 	switch (hw->mac.type) {

   167 	case e1000_82573:

   168 	case e1000_82574:

   169 	case e1000_82583:

   170 		if (((eecd >> 15) & 0x3) == 0x3) {

   171 			nvm->type = e1000_nvm_flash_hw;

   172 			nvm->word_size = 2048;

   173 			/*

   174 			 * Autonomous Flash update bit must be cleared due

   175 			 * to Flash update issue.

   176 			 */

   177 			eecd &= ~E1000_EECD_AUPDEN;

   178 			ew32(EECD, eecd);

   179 			break;

   180 		}

   181 		/* Fall Through */

   182 	default:

   183 		nvm->type = e1000_nvm_eeprom_spi;

   184 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   185 				  E1000_EECD_SIZE_EX_SHIFT);

   186 		/*

   187 		 * Added to a constant, "size" becomes the left-shift value

   188 		 * for setting word_size.

   189 		 */

   190 		size += NVM_WORD_SIZE_BASE_SHIFT;

   191 

   192 		/* EEPROM access above 16k is unsupported */

   193 		if (size > 14)

   194 			size = 14;

   195 		nvm->word_size	= 1 << size;

   196 		break;

   197 	}

   198 

   199 	return 0;

   200 }

   201 

   202 /**

   203  *  e1000_init_mac_params_82571 - Init MAC func ptrs.

   204  *  @hw: pointer to the HW structure

   205  **/

   206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)

   207 {

   208 	struct e1000_hw *hw = &adapter->hw;

   209 	struct e1000_mac_info *mac = &hw->mac;

   210 	struct e1000_mac_operations *func = &mac->ops;

   211 	u32 swsm = 0;

   212 	u32 swsm2 = 0;

   213 	bool force_clear_smbi = false;

   214 

   215 	/* Set media type */

   216 	switch (adapter->pdev->device) {

   217 	case E1000_DEV_ID_82571EB_FIBER:

   218 	case E1000_DEV_ID_82572EI_FIBER:

   219 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   220 		hw->phy.media_type = e1000_media_type_fiber;

   221 		break;

   222 	case E1000_DEV_ID_82571EB_SERDES:

   223 	case E1000_DEV_ID_82572EI_SERDES:

   224 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   225 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   226 		hw->phy.media_type = e1000_media_type_internal_serdes;

   227 		break;

   228 	default:

   229 		hw->phy.media_type = e1000_media_type_copper;

   230 		break;

   231 	}

   232 

   233 	/* Set mta register count */

   234 	mac->mta_reg_count = 128;

   235 	/* Set rar entry count */

   236 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   237 	/* Set if manageability features are enabled. */

   238 	mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)

   239 	                ? true : false;

   240 	/* Adaptive IFS supported */

   241 	mac->adaptive_ifs = true;

   242 

   243 	/* check for link */

   244 	switch (hw->phy.media_type) {

   245 	case e1000_media_type_copper:

   246 		func->setup_physical_interface = e1000_setup_copper_link_82571;

   247 		func->check_for_link = e1000e_check_for_copper_link;

   248 		func->get_link_up_info = e1000e_get_speed_and_duplex_copper;

   249 		break;

   250 	case e1000_media_type_fiber:

   251 		func->setup_physical_interface =

   252 			e1000_setup_fiber_serdes_link_82571;

   253 		func->check_for_link = e1000e_check_for_fiber_link;

   254 		func->get_link_up_info =

   255 			e1000e_get_speed_and_duplex_fiber_serdes;

   256 		break;

   257 	case e1000_media_type_internal_serdes:

   258 		func->setup_physical_interface =

   259 			e1000_setup_fiber_serdes_link_82571;

   260 		func->check_for_link = e1000_check_for_serdes_link_82571;

   261 		func->get_link_up_info =

   262 			e1000e_get_speed_and_duplex_fiber_serdes;

   263 		break;

   264 	default:

   265 		return -E1000_ERR_CONFIG;

   266 		break;

   267 	}

   268 

   269 	switch (hw->mac.type) {

   270 	case e1000_82573:

   271 		func->set_lan_id = e1000_set_lan_id_single_port;

   272 		func->check_mng_mode = e1000e_check_mng_mode_generic;

   273 		func->led_on = e1000e_led_on_generic;

   274 		break;

   275 	case e1000_82574:

   276 	case e1000_82583:

   277 		func->set_lan_id = e1000_set_lan_id_single_port;

   278 		func->check_mng_mode = e1000_check_mng_mode_82574;

   279 		func->led_on = e1000_led_on_82574;

   280 		break;

   281 	default:

   282 		func->check_mng_mode = e1000e_check_mng_mode_generic;

   283 		func->led_on = e1000e_led_on_generic;

   284 		break;

   285 	}

   286 

   287 	/*

   288 	 * Ensure that the inter-port SWSM.SMBI lock bit is clear before

   289 	 * first NVM or PHY acess. This should be done for single-port

   290 	 * devices, and for one port only on dual-port devices so that

   291 	 * for those devices we can still use the SMBI lock to synchronize

   292 	 * inter-port accesses to the PHY & NVM.

   293 	 */

   294 	switch (hw->mac.type) {

   295 	case e1000_82571:

   296 	case e1000_82572:

   297 		swsm2 = er32(SWSM2);

   298 

   299 		if (!(swsm2 & E1000_SWSM2_LOCK)) {

   300 			/* Only do this for the first interface on this card */

   301 			ew32(SWSM2,

   302 			    swsm2 | E1000_SWSM2_LOCK);

   303 			force_clear_smbi = true;

   304 		} else

   305 			force_clear_smbi = false;

   306 		break;

   307 	default:

   308 		force_clear_smbi = true;

   309 		break;

   310 	}

   311 

   312 	if (force_clear_smbi) {

   313 		/* Make sure SWSM.SMBI is clear */

   314 		swsm = er32(SWSM);

   315 		if (swsm & E1000_SWSM_SMBI) {

   316 			/* This bit should not be set on a first interface, and

   317 			 * indicates that the bootagent or EFI code has

   318 			 * improperly left this bit enabled

   319 			 */

   320 			e_dbg("Please update your 82571 Bootagent\n");

   321 		}

   322 		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

   323 	}

   324 

   325 	/*

   326 	 * Initialze device specific counter of SMBI acquisition

   327 	 * timeouts.

   328 	 */

   329 	 hw->dev_spec.e82571.smb_counter = 0;

   330 

   331 	return 0;

   332 }

   333 

   334 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)

   335 {

   336 	struct e1000_hw *hw = &adapter->hw;

   337 	static int global_quad_port_a; /* global port a indication */

   338 	struct pci_dev *pdev = adapter->pdev;

   339 	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;

   340 	s32 rc;

   341 

   342 	rc = e1000_init_mac_params_82571(adapter);

   343 	if (rc)

   344 		return rc;

   345 

   346 	rc = e1000_init_nvm_params_82571(hw);

   347 	if (rc)

   348 		return rc;

   349 

   350 	rc = e1000_init_phy_params_82571(hw);

   351 	if (rc)

   352 		return rc;

   353 

   354 	/* tag quad port adapters first, it's used below */

   355 	switch (pdev->device) {

   356 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   357 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   358 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:

   359 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   360 		adapter->flags |= FLAG_IS_QUAD_PORT;

   361 		/* mark the first port */

   362 		if (global_quad_port_a == 0)

   363 			adapter->flags |= FLAG_IS_QUAD_PORT_A;

   364 		/* Reset for multiple quad port adapters */

   365 		global_quad_port_a++;

   366 		if (global_quad_port_a == 4)

   367 			global_quad_port_a = 0;

   368 		break;

   369 	default:

   370 		break;

   371 	}

   372 

   373 	switch (adapter->hw.mac.type) {

   374 	case e1000_82571:

   375 		/* these dual ports don't have WoL on port B at all */

   376 		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||

   377 		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||

   378 		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&

   379 		    (is_port_b))

   380 			adapter->flags &= ~FLAG_HAS_WOL;

   381 		/* quad ports only support WoL on port A */

   382 		if (adapter->flags & FLAG_IS_QUAD_PORT &&

   383 		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))

   384 			adapter->flags &= ~FLAG_HAS_WOL;

   385 		/* Does not support WoL on any port */

   386 		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)

   387 			adapter->flags &= ~FLAG_HAS_WOL;

   388 		break;

   389 	case e1000_82573:

   390 	case e1000_82574:

   391 	case e1000_82583:

   392 		/* Disable ASPM L0s due to hardware errata */

   393 		e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S);

   394 

   395 		if (pdev->device == E1000_DEV_ID_82573L) {

   396 			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;

   397 			adapter->max_hw_frame_size = DEFAULT_JUMBO;

   398 		}

   399 		break;

   400 	default:

   401 		break;

   402 	}

   403 

   404 	return 0;

   405 }

   406 

   407 /**

   408  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision

   409  *  @hw: pointer to the HW structure

   410  *

   411  *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   412  *  revision in the hardware structure.

   413  **/

   414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)

   415 {

   416 	struct e1000_phy_info *phy = &hw->phy;

   417 	s32 ret_val;

   418 	u16 phy_id = 0;

   419 

   420 	switch (hw->mac.type) {

   421 	case e1000_82571:

   422 	case e1000_82572:

   423 		/*

   424 		 * The 82571 firmware may still be configuring the PHY.

   425 		 * In this case, we cannot access the PHY until the

   426 		 * configuration is done.  So we explicitly set the

   427 		 * PHY ID.

   428 		 */

   429 		phy->id = IGP01E1000_I_PHY_ID;

   430 		break;

   431 	case e1000_82573:

   432 		return e1000e_get_phy_id(hw);

   433 		break;

   434 	case e1000_82574:

   435 	case e1000_82583:

   436 		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);

   437 		if (ret_val)

   438 			return ret_val;

   439 

   440 		phy->id = (u32)(phy_id << 16);

   441 		udelay(20);

   442 		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);

   443 		if (ret_val)

   444 			return ret_val;

   445 

   446 		phy->id |= (u32)(phy_id);

   447 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   448 		break;

   449 	default:

   450 		return -E1000_ERR_PHY;

   451 		break;

   452 	}

   453 

   454 	return 0;

   455 }

   456 

   457 /**

   458  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore

   459  *  @hw: pointer to the HW structure

   460  *

   461  *  Acquire the HW semaphore to access the PHY or NVM

   462  **/

   463 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)

   464 {

   465 	u32 swsm;

   466 	s32 sw_timeout = hw->nvm.word_size + 1;

   467 	s32 fw_timeout = hw->nvm.word_size + 1;

   468 	s32 i = 0;

   469 

   470 	/*

   471 	 * If we have timedout 3 times on trying to acquire

   472 	 * the inter-port SMBI semaphore, there is old code

   473 	 * operating on the other port, and it is not

   474 	 * releasing SMBI. Modify the number of times that

   475 	 * we try for the semaphore to interwork with this

   476 	 * older code.

   477 	 */

   478 	if (hw->dev_spec.e82571.smb_counter > 2)

   479 		sw_timeout = 1;

   480 

   481 	/* Get the SW semaphore */

   482 	while (i < sw_timeout) {

   483 		swsm = er32(SWSM);

   484 		if (!(swsm & E1000_SWSM_SMBI))

   485 			break;

   486 

   487 		udelay(50);

   488 		i++;

   489 	}

   490 

   491 	if (i == sw_timeout) {

   492 		e_dbg("Driver can't access device - SMBI bit is set.\n");

   493 		hw->dev_spec.e82571.smb_counter++;

   494 	}

   495 	/* Get the FW semaphore. */

   496 	for (i = 0; i < fw_timeout; i++) {

   497 		swsm = er32(SWSM);

   498 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

   499 

   500 		/* Semaphore acquired if bit latched */

   501 		if (er32(SWSM) & E1000_SWSM_SWESMBI)

   502 			break;

   503 

   504 		udelay(50);

   505 	}

   506 

   507 	if (i == fw_timeout) {

   508 		/* Release semaphores */

   509 		e1000_put_hw_semaphore_82571(hw);

   510 		e_dbg("Driver can't access the NVM\n");

   511 		return -E1000_ERR_NVM;

   512 	}

   513 

   514 	return 0;

   515 }

   516 

   517 /**

   518  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore

   519  *  @hw: pointer to the HW structure

   520  *

   521  *  Release hardware semaphore used to access the PHY or NVM

   522  **/

   523 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)

   524 {

   525 	u32 swsm;

   526 

   527 	swsm = er32(SWSM);

   528 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

   529 	ew32(SWSM, swsm);

   530 }

   531 

   532 /**

   533  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM

   534  *  @hw: pointer to the HW structure

   535  *

   536  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.

   537  *  Then for non-82573 hardware, set the EEPROM access request bit and wait

   538  *  for EEPROM access grant bit.  If the access grant bit is not set, release

   539  *  hardware semaphore.

   540  **/

   541 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)

   542 {

   543 	s32 ret_val;

   544 

   545 	ret_val = e1000_get_hw_semaphore_82571(hw);

   546 	if (ret_val)

   547 		return ret_val;

   548 

   549 	switch (hw->mac.type) {

   550 	case e1000_82573:

   551 	case e1000_82574:

   552 	case e1000_82583:

   553 		break;

   554 	default:

   555 		ret_val = e1000e_acquire_nvm(hw);

   556 		break;

   557 	}

   558 

   559 	if (ret_val)

   560 		e1000_put_hw_semaphore_82571(hw);

   561 

   562 	return ret_val;

   563 }

   564 

   565 /**

   566  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM

   567  *  @hw: pointer to the HW structure

   568  *

   569  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.

   570  **/

   571 static void e1000_release_nvm_82571(struct e1000_hw *hw)

   572 {

   573 	e1000e_release_nvm(hw);

   574 	e1000_put_hw_semaphore_82571(hw);

   575 }

   576 

   577 /**

   578  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface

   579  *  @hw: pointer to the HW structure

   580  *  @offset: offset within the EEPROM to be written to

   581  *  @words: number of words to write

   582  *  @data: 16 bit word(s) to be written to the EEPROM

   583  *

   584  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.

   585  *

   586  *  If e1000e_update_nvm_checksum is not called after this function, the

   587  *  EEPROM will most likely contain an invalid checksum.

   588  **/

   589 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,

   590 				 u16 *data)

   591 {

   592 	s32 ret_val;

   593 

   594 	switch (hw->mac.type) {

   595 	case e1000_82573:

   596 	case e1000_82574:

   597 	case e1000_82583:

   598 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);

   599 		break;

   600 	case e1000_82571:

   601 	case e1000_82572:

   602 		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);

   603 		break;

   604 	default:

   605 		ret_val = -E1000_ERR_NVM;

   606 		break;

   607 	}

   608 

   609 	return ret_val;

   610 }

   611 

   612 /**

   613  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum

   614  *  @hw: pointer to the HW structure

   615  *

   616  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM

   617  *  up to the checksum.  Then calculates the EEPROM checksum and writes the

   618  *  value to the EEPROM.

   619  **/

   620 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)

   621 {

   622 	u32 eecd;

   623 	s32 ret_val;

   624 	u16 i;

   625 

   626 	ret_val = e1000e_update_nvm_checksum_generic(hw);

   627 	if (ret_val)

   628 		return ret_val;

   629 

   630 	/*

   631 	 * If our nvm is an EEPROM, then we're done

   632 	 * otherwise, commit the checksum to the flash NVM.

   633 	 */

   634 	if (hw->nvm.type != e1000_nvm_flash_hw)

   635 		return ret_val;

   636 

   637 	/* Check for pending operations. */

   638 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   639 		msleep(1);

   640 		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)

   641 			break;

   642 	}

   643 

   644 	if (i == E1000_FLASH_UPDATES)

   645 		return -E1000_ERR_NVM;

   646 

   647 	/* Reset the firmware if using STM opcode. */

   648 	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

   649 		/*

   650 		 * The enabling of and the actual reset must be done

   651 		 * in two write cycles.

   652 		 */

   653 		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

   654 		e1e_flush();

   655 		ew32(HICR, E1000_HICR_FW_RESET);

   656 	}

   657 

   658 	/* Commit the write to flash */

   659 	eecd = er32(EECD) | E1000_EECD_FLUPD;

   660 	ew32(EECD, eecd);

   661 

   662 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   663 		msleep(1);

   664 		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)

   665 			break;

   666 	}

   667 

   668 	if (i == E1000_FLASH_UPDATES)

   669 		return -E1000_ERR_NVM;

   670 

   671 	return 0;

   672 }

   673 

   674 /**

   675  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum

   676  *  @hw: pointer to the HW structure

   677  *

   678  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM

   679  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.

   680  **/

   681 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)

   682 {

   683 	if (hw->nvm.type == e1000_nvm_flash_hw)

   684 		e1000_fix_nvm_checksum_82571(hw);

   685 

   686 	return e1000e_validate_nvm_checksum_generic(hw);

   687 }

   688 

   689 /**

   690  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon

   691  *  @hw: pointer to the HW structure

   692  *  @offset: offset within the EEPROM to be written to

   693  *  @words: number of words to write

   694  *  @data: 16 bit word(s) to be written to the EEPROM

   695  *

   696  *  After checking for invalid values, poll the EEPROM to ensure the previous

   697  *  command has completed before trying to write the next word.  After write

   698  *  poll for completion.

   699  *

   700  *  If e1000e_update_nvm_checksum is not called after this function, the

   701  *  EEPROM will most likely contain an invalid checksum.

   702  **/

   703 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

   704 				      u16 words, u16 *data)

   705 {

   706 	struct e1000_nvm_info *nvm = &hw->nvm;

   707 	u32 i, eewr = 0;

   708 	s32 ret_val = 0;

   709 

   710 	/*

   711 	 * A check for invalid values:  offset too large, too many words,

   712 	 * and not enough words.

   713 	 */

   714 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

   715 	    (words == 0)) {

   716 		e_dbg("nvm parameter(s) out of bounds\n");

   717 		return -E1000_ERR_NVM;

   718 	}

   719 

   720 	for (i = 0; i < words; i++) {

   721 		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |

   722 		       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |

   723 		       E1000_NVM_RW_REG_START;

   724 

   725 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   726 		if (ret_val)

   727 			break;

   728 

   729 		ew32(EEWR, eewr);

   730 

   731 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   732 		if (ret_val)

   733 			break;

   734 	}

   735 

   736 	return ret_val;

   737 }

   738 

   739 /**

   740  *  e1000_get_cfg_done_82571 - Poll for configuration done

   741  *  @hw: pointer to the HW structure

   742  *

   743  *  Reads the management control register for the config done bit to be set.

   744  **/

   745 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)

   746 {

   747 	s32 timeout = PHY_CFG_TIMEOUT;

   748 

   749 	while (timeout) {

   750 		if (er32(EEMNGCTL) &

   751 		    E1000_NVM_CFG_DONE_PORT_0)

   752 			break;

   753 		msleep(1);

   754 		timeout--;

   755 	}

   756 	if (!timeout) {

   757 		e_dbg("MNG configuration cycle has not completed.\n");

   758 		return -E1000_ERR_RESET;

   759 	}

   760 

   761 	return 0;

   762 }

   763 

   764 /**

   765  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state

   766  *  @hw: pointer to the HW structure

   767  *  @active: true to enable LPLU, false to disable

   768  *

   769  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU

   770  *  this function also disables smart speed and vice versa.  LPLU will not be

   771  *  activated unless the device autonegotiation advertisement meets standards

   772  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function

   773  *  pointer entry point only called by PHY setup routines.

   774  **/

   775 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)

   776 {

   777 	struct e1000_phy_info *phy = &hw->phy;

   778 	s32 ret_val;

   779 	u16 data;

   780 

   781 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);

   782 	if (ret_val)

   783 		return ret_val;

   784 

   785 	if (active) {

   786 		data |= IGP02E1000_PM_D0_LPLU;

   787 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   788 		if (ret_val)

   789 			return ret_val;

   790 

   791 		/* When LPLU is enabled, we should disable SmartSpeed */

   792 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);

   793 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   794 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);

   795 		if (ret_val)

   796 			return ret_val;

   797 	} else {

   798 		data &= ~IGP02E1000_PM_D0_LPLU;

   799 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   800 		/*

   801 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used

   802 		 * during Dx states where the power conservation is most

   803 		 * important.  During driver activity we should enable

   804 		 * SmartSpeed, so performance is maintained.

   805 		 */

   806 		if (phy->smart_speed == e1000_smart_speed_on) {

   807 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   808 					   &data);

   809 			if (ret_val)

   810 				return ret_val;

   811 

   812 			data |= IGP01E1000_PSCFR_SMART_SPEED;

   813 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   814 					   data);

   815 			if (ret_val)

   816 				return ret_val;

   817 		} else if (phy->smart_speed == e1000_smart_speed_off) {

   818 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   819 					   &data);

   820 			if (ret_val)

   821 				return ret_val;

   822 

   823 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   824 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   825 					   data);

   826 			if (ret_val)

   827 				return ret_val;

   828 		}

   829 	}

   830 

   831 	return 0;

   832 }

   833 

   834 /**

   835  *  e1000_reset_hw_82571 - Reset hardware

   836  *  @hw: pointer to the HW structure

   837  *

   838  *  This resets the hardware into a known state.

   839  **/

   840 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

   841 {

   842 	u32 ctrl, extcnf_ctrl, ctrl_ext, icr;

   843 	s32 ret_val;

   844 	u16 i = 0;

   845 

   846 	/*

   847 	 * Prevent the PCI-E bus from sticking if there is no TLP connection

   848 	 * on the last TLP read/write transaction when MAC is reset.

   849 	 */

   850 	ret_val = e1000e_disable_pcie_master(hw);

   851 	if (ret_val)

   852 		e_dbg("PCI-E Master disable polling has failed.\n");

   853 

   854 	e_dbg("Masking off all interrupts\n");

   855 	ew32(IMC, 0xffffffff);

   856 

   857 	ew32(RCTL, 0);

   858 	ew32(TCTL, E1000_TCTL_PSP);

   859 	e1e_flush();

   860 

   861 	msleep(10);

   862 

   863 	/*

   864 	 * Must acquire the MDIO ownership before MAC reset.

   865 	 * Ownership defaults to firmware after a reset.

   866 	 */

   867 	switch (hw->mac.type) {

   868 	case e1000_82573:

   869 	case e1000_82574:

   870 	case e1000_82583:

   871 		extcnf_ctrl = er32(EXTCNF_CTRL);

   872 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   873 

   874 		do {

   875 			ew32(EXTCNF_CTRL, extcnf_ctrl);

   876 			extcnf_ctrl = er32(EXTCNF_CTRL);

   877 

   878 			if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   879 				break;

   880 

   881 			extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   882 

   883 			msleep(2);

   884 			i++;

   885 		} while (i < MDIO_OWNERSHIP_TIMEOUT);

   886 		break;

   887 	default:

   888 		break;

   889 	}

   890 

   891 	ctrl = er32(CTRL);

   892 

   893 	e_dbg("Issuing a global reset to MAC\n");

   894 	ew32(CTRL, ctrl | E1000_CTRL_RST);

   895 

   896 	if (hw->nvm.type == e1000_nvm_flash_hw) {

   897 		udelay(10);

   898 		ctrl_ext = er32(CTRL_EXT);

   899 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   900 		ew32(CTRL_EXT, ctrl_ext);

   901 		e1e_flush();

   902 	}

   903 

   904 	ret_val = e1000e_get_auto_rd_done(hw);

   905 	if (ret_val)

   906 		/* We don't want to continue accessing MAC registers. */

   907 		return ret_val;

   908 

   909 	/*

   910 	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.

   911 	 * Need to wait for Phy configuration completion before accessing

   912 	 * NVM and Phy.

   913 	 */

   914 

   915 	switch (hw->mac.type) {

   916 	case e1000_82573:

   917 	case e1000_82574:

   918 	case e1000_82583:

   919 		msleep(25);

   920 		break;

   921 	default:

   922 		break;

   923 	}

   924 

   925 	/* Clear any pending interrupt events. */

   926 	ew32(IMC, 0xffffffff);

   927 	icr = er32(ICR);

   928 

   929 	/* Install any alternate MAC address into RAR0 */

   930 	ret_val = e1000_check_alt_mac_addr_generic(hw);

   931 	if (ret_val)

   932 		return ret_val;

   933 

   934 	e1000e_set_laa_state_82571(hw, true);

   935 

   936 	/* Reinitialize the 82571 serdes link state machine */

   937 	if (hw->phy.media_type == e1000_media_type_internal_serdes)

   938 		hw->mac.serdes_link_state = e1000_serdes_link_down;

   939 

   940 	return 0;

   941 }

   942 

   943 /**

   944  *  e1000_init_hw_82571 - Initialize hardware

   945  *  @hw: pointer to the HW structure

   946  *

   947  *  This inits the hardware readying it for operation.

   948  **/

   949 static s32 e1000_init_hw_82571(struct e1000_hw *hw)

   950 {

   951 	struct e1000_mac_info *mac = &hw->mac;

   952 	u32 reg_data;

   953 	s32 ret_val;

   954 	u16 i, rar_count = mac->rar_entry_count;

   955 

   956 	e1000_initialize_hw_bits_82571(hw);

   957 

   958 	/* Initialize identification LED */

   959 	ret_val = e1000e_id_led_init(hw);

   960 	if (ret_val)

   961 		e_dbg("Error initializing identification LED\n");

   962 		/* This is not fatal and we should not stop init due to this */

   963 

   964 	/* Disabling VLAN filtering */

   965 	e_dbg("Initializing the IEEE VLAN\n");

   966 	mac->ops.clear_vfta(hw);

   967 

   968 	/* Setup the receive address. */

   969 	/*

   970 	 * If, however, a locally administered address was assigned to the

   971 	 * 82571, we must reserve a RAR for it to work around an issue where

   972 	 * resetting one port will reload the MAC on the other port.

   973 	 */

   974 	if (e1000e_get_laa_state_82571(hw))

   975 		rar_count--;

   976 	e1000e_init_rx_addrs(hw, rar_count);

   977 

   978 	/* Zero out the Multicast HASH table */

   979 	e_dbg("Zeroing the MTA\n");

   980 	for (i = 0; i < mac->mta_reg_count; i++)

   981 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

   982 

   983 	/* Setup link and flow control */

   984 	ret_val = e1000_setup_link_82571(hw);

   985 

   986 	/* Set the transmit descriptor write-back policy */

   987 	reg_data = er32(TXDCTL(0));

   988 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

   989 		   E1000_TXDCTL_FULL_TX_DESC_WB |

   990 		   E1000_TXDCTL_COUNT_DESC;

   991 	ew32(TXDCTL(0), reg_data);

   992 

   993 	/* ...for both queues. */

   994 	switch (mac->type) {

   995 	case e1000_82573:

   996 	case e1000_82574:

   997 	case e1000_82583:

   998 		e1000e_enable_tx_pkt_filtering(hw);

   999 		reg_data = er32(GCR);

  1000 		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;

  1001 		ew32(GCR, reg_data);

  1002 		break;

  1003 	default:

  1004 		reg_data = er32(TXDCTL(1));

  1005 		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |

  1006 			   E1000_TXDCTL_FULL_TX_DESC_WB |

  1007 			   E1000_TXDCTL_COUNT_DESC;

  1008 		ew32(TXDCTL(1), reg_data);

  1009 		break;

  1010 	}

  1011 

  1012 	/*

  1013 	 * Clear all of the statistics registers (clear on read).  It is

  1014 	 * important that we do this after we have tried to establish link

  1015 	 * because the symbol error count will increment wildly if there

  1016 	 * is no link.

  1017 	 */

  1018 	e1000_clear_hw_cntrs_82571(hw);

  1019 

  1020 	return ret_val;

  1021 }

  1022 

  1023 /**

  1024  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits

  1025  *  @hw: pointer to the HW structure

  1026  *

  1027  *  Initializes required hardware-dependent bits needed for normal operation.

  1028  **/

  1029 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)

  1030 {

  1031 	u32 reg;

  1032 

  1033 	/* Transmit Descriptor Control 0 */

  1034 	reg = er32(TXDCTL(0));

  1035 	reg |= (1 << 22);

  1036 	ew32(TXDCTL(0), reg);

  1037 

  1038 	/* Transmit Descriptor Control 1 */

  1039 	reg = er32(TXDCTL(1));

  1040 	reg |= (1 << 22);

  1041 	ew32(TXDCTL(1), reg);

  1042 

  1043 	/* Transmit Arbitration Control 0 */

  1044 	reg = er32(TARC(0));

  1045 	reg &= ~(0xF << 27); /* 30:27 */

  1046 	switch (hw->mac.type) {

  1047 	case e1000_82571:

  1048 	case e1000_82572:

  1049 		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);

  1050 		break;

  1051 	default:

  1052 		break;

  1053 	}

  1054 	ew32(TARC(0), reg);

  1055 

  1056 	/* Transmit Arbitration Control 1 */

  1057 	reg = er32(TARC(1));

  1058 	switch (hw->mac.type) {

  1059 	case e1000_82571:

  1060 	case e1000_82572:

  1061 		reg &= ~((1 << 29) | (1 << 30));

  1062 		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);

  1063 		if (er32(TCTL) & E1000_TCTL_MULR)

  1064 			reg &= ~(1 << 28);

  1065 		else

  1066 			reg |= (1 << 28);

  1067 		ew32(TARC(1), reg);

  1068 		break;

  1069 	default:

  1070 		break;

  1071 	}

  1072 

  1073 	/* Device Control */

  1074 	switch (hw->mac.type) {

  1075 	case e1000_82573:

  1076 	case e1000_82574:

  1077 	case e1000_82583:

  1078 		reg = er32(CTRL);

  1079 		reg &= ~(1 << 29);

  1080 		ew32(CTRL, reg);

  1081 		break;

  1082 	default:

  1083 		break;

  1084 	}

  1085 

  1086 	/* Extended Device Control */

  1087 	switch (hw->mac.type) {

  1088 	case e1000_82573:

  1089 	case e1000_82574:

  1090 	case e1000_82583:

  1091 		reg = er32(CTRL_EXT);

  1092 		reg &= ~(1 << 23);

  1093 		reg |= (1 << 22);

  1094 		ew32(CTRL_EXT, reg);

  1095 		break;

  1096 	default:

  1097 		break;

  1098 	}

  1099 

  1100 	if (hw->mac.type == e1000_82571) {

  1101 		reg = er32(PBA_ECC);

  1102 		reg |= E1000_PBA_ECC_CORR_EN;

  1103 		ew32(PBA_ECC, reg);

  1104 	}

  1105 	/*

  1106 	 * Workaround for hardware errata.

  1107 	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572

  1108 	 */

  1109 

  1110         if ((hw->mac.type == e1000_82571) ||

  1111            (hw->mac.type == e1000_82572)) {

  1112                 reg = er32(CTRL_EXT);

  1113                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;

  1114                 ew32(CTRL_EXT, reg);

  1115         }

  1116 

  1117 

  1118 	/* PCI-Ex Control Registers */

  1119 	switch (hw->mac.type) {

  1120 	case e1000_82574:

  1121 	case e1000_82583:

  1122 		reg = er32(GCR);

  1123 		reg |= (1 << 22);

  1124 		ew32(GCR, reg);

  1125 

  1126 		/*

  1127 		 * Workaround for hardware errata.

  1128 		 * apply workaround for hardware errata documented in errata

  1129 		 * docs Fixes issue where some error prone or unreliable PCIe

  1130 		 * completions are occurring, particularly with ASPM enabled.

  1131 		 * Without fix, issue can cause tx timeouts.

  1132 		 */

  1133 		reg = er32(GCR2);

  1134 		reg |= 1;

  1135 		ew32(GCR2, reg);

  1136 		break;