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1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 |
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2 * |
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3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> |
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4 * |
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5 * This program is free software; you can redistribute it and/or modify |
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6 * it under the terms of the GNU General Public License as published by |
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7 * the Free Software Foundation; either version 2 of the License, or |
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8 * (at your option) any later version. |
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9 * |
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10 * This program is distributed in the hope that it will be useful, |
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 * GNU General Public License for more details. |
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14 * |
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15 * You should have received a copy of the GNU General Public License along with |
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16 * this program; if not, see <http://www.gnu.org/licenses/>. |
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17 */ |
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18 #include <linux/module.h> |
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19 #include <linux/device.h> |
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20 #include <linux/pci.h> |
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21 #include <linux/ptp_classify.h> |
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22 |
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23 #include "igb-3.18-ethercat.h" |
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24 |
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25 #define INCVALUE_MASK 0x7fffffff |
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26 #define ISGN 0x80000000 |
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27 |
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28 /* The 82580 timesync updates the system timer every 8ns by 8ns, |
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29 * and this update value cannot be reprogrammed. |
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30 * |
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31 * Neither the 82576 nor the 82580 offer registers wide enough to hold |
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32 * nanoseconds time values for very long. For the 82580, SYSTIM always |
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33 * counts nanoseconds, but the upper 24 bits are not availible. The |
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34 * frequency is adjusted by changing the 32 bit fractional nanoseconds |
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35 * register, TIMINCA. |
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36 * |
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37 * For the 82576, the SYSTIM register time unit is affect by the |
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38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this |
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39 * field are needed to provide the nominal 16 nanosecond period, |
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40 * leaving 19 bits for fractional nanoseconds. |
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41 * |
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42 * We scale the NIC clock cycle by a large factor so that relatively |
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43 * small clock corrections can be added or subtracted at each clock |
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44 * tick. The drawbacks of a large factor are a) that the clock |
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45 * register overflows more quickly (not such a big deal) and b) that |
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46 * the increment per tick has to fit into 24 bits. As a result we |
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47 * need to use a shift of 19 so we can fit a value of 16 into the |
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48 * TIMINCA register. |
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49 * |
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50 * |
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51 * SYSTIMH SYSTIML |
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52 * +--------------+ +---+---+------+ |
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53 * 82576 | 32 | | 8 | 5 | 19 | |
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54 * +--------------+ +---+---+------+ |
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55 * \________ 45 bits _______/ fract |
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56 * |
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57 * +----------+---+ +--------------+ |
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58 * 82580 | 24 | 8 | | 32 | |
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59 * +----------+---+ +--------------+ |
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60 * reserved \______ 40 bits _____/ |
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61 * |
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62 * |
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63 * The 45 bit 82576 SYSTIM overflows every |
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64 * 2^45 * 10^-9 / 3600 = 9.77 hours. |
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65 * |
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66 * The 40 bit 82580 SYSTIM overflows every |
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67 * 2^40 * 10^-9 / 60 = 18.3 minutes. |
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68 */ |
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69 |
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70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) |
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71 #define IGB_PTP_TX_TIMEOUT (HZ * 15) |
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72 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) |
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73 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) |
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74 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) |
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75 #define IGB_NBITS_82580 40 |
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76 |
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77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); |
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78 |
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79 /* SYSTIM read access for the 82576 */ |
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80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) |
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81 { |
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82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
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83 struct e1000_hw *hw = &igb->hw; |
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84 u64 val; |
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85 u32 lo, hi; |
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86 |
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87 lo = rd32(E1000_SYSTIML); |
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88 hi = rd32(E1000_SYSTIMH); |
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89 |
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90 val = ((u64) hi) << 32; |
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91 val |= lo; |
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92 |
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93 return val; |
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94 } |
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95 |
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96 /* SYSTIM read access for the 82580 */ |
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97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) |
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98 { |
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99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); |
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100 struct e1000_hw *hw = &igb->hw; |
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101 u32 lo, hi; |
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102 u64 val; |
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103 |
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104 /* The timestamp latches on lowest register read. For the 82580 |
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105 * the lowest register is SYSTIMR instead of SYSTIML. However we only |
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106 * need to provide nanosecond resolution, so we just ignore it. |
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107 */ |
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108 rd32(E1000_SYSTIMR); |
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109 lo = rd32(E1000_SYSTIML); |
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110 hi = rd32(E1000_SYSTIMH); |
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111 |
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112 val = ((u64) hi) << 32; |
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113 val |= lo; |
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114 |
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115 return val; |
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116 } |
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117 |
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118 /* SYSTIM read access for I210/I211 */ |
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119 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) |
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120 { |
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121 struct e1000_hw *hw = &adapter->hw; |
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122 u32 sec, nsec; |
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123 |
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124 /* The timestamp latches on lowest register read. For I210/I211, the |
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125 * lowest register is SYSTIMR. Since we only need to provide nanosecond |
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126 * resolution, we can ignore it. |
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127 */ |
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128 rd32(E1000_SYSTIMR); |
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129 nsec = rd32(E1000_SYSTIML); |
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130 sec = rd32(E1000_SYSTIMH); |
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131 |
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132 ts->tv_sec = sec; |
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133 ts->tv_nsec = nsec; |
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134 } |
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135 |
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136 static void igb_ptp_write_i210(struct igb_adapter *adapter, |
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137 const struct timespec *ts) |
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138 { |
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139 struct e1000_hw *hw = &adapter->hw; |
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140 |
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141 /* Writing the SYSTIMR register is not necessary as it only provides |
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142 * sub-nanosecond resolution. |
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143 */ |
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144 wr32(E1000_SYSTIML, ts->tv_nsec); |
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145 wr32(E1000_SYSTIMH, ts->tv_sec); |
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146 } |
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147 |
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148 /** |
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149 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp |
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150 * @adapter: board private structure |
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151 * @hwtstamps: timestamp structure to update |
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152 * @systim: unsigned 64bit system time value. |
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153 * |
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154 * We need to convert the system time value stored in the RX/TXSTMP registers |
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155 * into a hwtstamp which can be used by the upper level timestamping functions. |
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156 * |
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157 * The 'tmreg_lock' spinlock is used to protect the consistency of the |
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158 * system time value. This is needed because reading the 64 bit time |
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159 * value involves reading two (or three) 32 bit registers. The first |
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160 * read latches the value. Ditto for writing. |
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161 * |
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162 * In addition, here have extended the system time with an overflow |
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163 * counter in software. |
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164 **/ |
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165 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, |
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166 struct skb_shared_hwtstamps *hwtstamps, |
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167 u64 systim) |
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168 { |
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169 unsigned long flags; |
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170 u64 ns; |
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171 |
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172 switch (adapter->hw.mac.type) { |
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173 case e1000_82576: |
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174 case e1000_82580: |
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175 case e1000_i354: |
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176 case e1000_i350: |
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177 spin_lock_irqsave(&adapter->tmreg_lock, flags); |
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178 |
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179 ns = timecounter_cyc2time(&adapter->tc, systim); |
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180 |
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181 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); |
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182 |
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183 memset(hwtstamps, 0, sizeof(*hwtstamps)); |
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184 hwtstamps->hwtstamp = ns_to_ktime(ns); |
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185 break; |
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186 case e1000_i210: |
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187 case e1000_i211: |
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188 memset(hwtstamps, 0, sizeof(*hwtstamps)); |
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189 /* Upper 32 bits contain s, lower 32 bits contain ns. */ |
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190 hwtstamps->hwtstamp = ktime_set(systim >> 32, |
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191 systim & 0xFFFFFFFF); |
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192 break; |
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193 default: |
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194 break; |
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195 } |
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196 } |
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197 |
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198 /* PTP clock operations */ |
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199 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) |
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200 { |
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201 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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202 ptp_caps); |
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203 struct e1000_hw *hw = &igb->hw; |
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204 int neg_adj = 0; |
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205 u64 rate; |
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206 u32 incvalue; |
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207 |
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208 if (ppb < 0) { |
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209 neg_adj = 1; |
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210 ppb = -ppb; |
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211 } |
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212 rate = ppb; |
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213 rate <<= 14; |
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214 rate = div_u64(rate, 1953125); |
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215 |
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216 incvalue = 16 << IGB_82576_TSYNC_SHIFT; |
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217 |
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218 if (neg_adj) |
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219 incvalue -= rate; |
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220 else |
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221 incvalue += rate; |
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222 |
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223 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); |
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224 |
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225 return 0; |
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226 } |
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227 |
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228 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) |
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229 { |
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230 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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231 ptp_caps); |
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232 struct e1000_hw *hw = &igb->hw; |
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233 int neg_adj = 0; |
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234 u64 rate; |
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235 u32 inca; |
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236 |
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237 if (ppb < 0) { |
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238 neg_adj = 1; |
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239 ppb = -ppb; |
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240 } |
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241 rate = ppb; |
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242 rate <<= 26; |
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243 rate = div_u64(rate, 1953125); |
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244 |
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245 inca = rate & INCVALUE_MASK; |
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246 if (neg_adj) |
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247 inca |= ISGN; |
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248 |
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249 wr32(E1000_TIMINCA, inca); |
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250 |
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251 return 0; |
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252 } |
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253 |
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254 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) |
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255 { |
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256 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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257 ptp_caps); |
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258 unsigned long flags; |
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259 s64 now; |
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260 |
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261 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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262 |
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263 now = timecounter_read(&igb->tc); |
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264 now += delta; |
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265 timecounter_init(&igb->tc, &igb->cc, now); |
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266 |
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267 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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268 |
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269 return 0; |
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270 } |
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271 |
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272 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) |
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273 { |
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274 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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275 ptp_caps); |
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276 unsigned long flags; |
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277 struct timespec now, then = ns_to_timespec(delta); |
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278 |
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279 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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280 |
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281 igb_ptp_read_i210(igb, &now); |
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282 now = timespec_add(now, then); |
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283 igb_ptp_write_i210(igb, (const struct timespec *)&now); |
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284 |
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285 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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286 |
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287 return 0; |
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288 } |
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289 |
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290 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, |
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291 struct timespec *ts) |
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292 { |
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293 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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294 ptp_caps); |
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295 unsigned long flags; |
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296 u64 ns; |
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297 u32 remainder; |
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298 |
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299 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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300 |
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301 ns = timecounter_read(&igb->tc); |
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302 |
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303 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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304 |
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305 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); |
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306 ts->tv_nsec = remainder; |
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307 |
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308 return 0; |
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309 } |
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310 |
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311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, |
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312 struct timespec *ts) |
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313 { |
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314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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315 ptp_caps); |
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316 unsigned long flags; |
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317 |
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318 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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319 |
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320 igb_ptp_read_i210(igb, ts); |
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321 |
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322 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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323 |
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324 return 0; |
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325 } |
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326 |
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327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, |
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328 const struct timespec *ts) |
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329 { |
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330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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331 ptp_caps); |
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332 unsigned long flags; |
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333 u64 ns; |
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334 |
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335 ns = ts->tv_sec * 1000000000ULL; |
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336 ns += ts->tv_nsec; |
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337 |
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338 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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339 |
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340 timecounter_init(&igb->tc, &igb->cc, ns); |
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341 |
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342 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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343 |
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344 return 0; |
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345 } |
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346 |
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347 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, |
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348 const struct timespec *ts) |
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349 { |
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350 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, |
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351 ptp_caps); |
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352 unsigned long flags; |
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353 |
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354 spin_lock_irqsave(&igb->tmreg_lock, flags); |
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355 |
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356 igb_ptp_write_i210(igb, ts); |
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357 |
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358 spin_unlock_irqrestore(&igb->tmreg_lock, flags); |
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359 |
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360 return 0; |
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361 } |
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362 |
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363 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp, |
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364 struct ptp_clock_request *rq, int on) |
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365 { |
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366 return -EOPNOTSUPP; |
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367 } |
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368 |
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369 /** |
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370 * igb_ptp_tx_work |
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371 * @work: pointer to work struct |
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372 * |
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373 * This work function polls the TSYNCTXCTL valid bit to determine when a |
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374 * timestamp has been taken for the current stored skb. |
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375 **/ |
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376 static void igb_ptp_tx_work(struct work_struct *work) |
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377 { |
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378 struct igb_adapter *adapter = container_of(work, struct igb_adapter, |
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379 ptp_tx_work); |
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380 struct e1000_hw *hw = &adapter->hw; |
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381 u32 tsynctxctl; |
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382 |
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383 if (!adapter->ptp_tx_skb) |
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384 return; |
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385 |
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386 if (time_is_before_jiffies(adapter->ptp_tx_start + |
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387 IGB_PTP_TX_TIMEOUT)) { |
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388 dev_kfree_skb_any(adapter->ptp_tx_skb); |
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389 adapter->ptp_tx_skb = NULL; |
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390 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
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391 adapter->tx_hwtstamp_timeouts++; |
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392 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n"); |
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393 return; |
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394 } |
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395 |
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396 tsynctxctl = rd32(E1000_TSYNCTXCTL); |
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397 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) |
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398 igb_ptp_tx_hwtstamp(adapter); |
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399 else |
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400 /* reschedule to check later */ |
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401 schedule_work(&adapter->ptp_tx_work); |
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402 } |
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403 |
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404 static void igb_ptp_overflow_check(struct work_struct *work) |
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405 { |
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406 struct igb_adapter *igb = |
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407 container_of(work, struct igb_adapter, ptp_overflow_work.work); |
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408 struct timespec ts; |
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409 |
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410 igb->ptp_caps.gettime(&igb->ptp_caps, &ts); |
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411 |
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412 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); |
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413 |
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414 schedule_delayed_work(&igb->ptp_overflow_work, |
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415 IGB_SYSTIM_OVERFLOW_PERIOD); |
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416 } |
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417 |
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418 /** |
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419 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched |
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420 * @adapter: private network adapter structure |
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421 * |
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422 * This watchdog task is scheduled to detect error case where hardware has |
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423 * dropped an Rx packet that was timestamped when the ring is full. The |
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424 * particular error is rare but leaves the device in a state unable to timestamp |
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425 * any future packets. |
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426 **/ |
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427 void igb_ptp_rx_hang(struct igb_adapter *adapter) |
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428 { |
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429 struct e1000_hw *hw = &adapter->hw; |
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430 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); |
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431 unsigned long rx_event; |
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432 |
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433 if (hw->mac.type != e1000_82576) |
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434 return; |
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435 |
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436 /* If we don't have a valid timestamp in the registers, just update the |
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437 * timeout counter and exit |
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438 */ |
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439 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { |
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440 adapter->last_rx_ptp_check = jiffies; |
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441 return; |
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442 } |
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443 |
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444 /* Determine the most recent watchdog or rx_timestamp event */ |
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445 rx_event = adapter->last_rx_ptp_check; |
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446 if (time_after(adapter->last_rx_timestamp, rx_event)) |
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447 rx_event = adapter->last_rx_timestamp; |
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448 |
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449 /* Only need to read the high RXSTMP register to clear the lock */ |
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450 if (time_is_before_jiffies(rx_event + 5 * HZ)) { |
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451 rd32(E1000_RXSTMPH); |
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452 adapter->last_rx_ptp_check = jiffies; |
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453 adapter->rx_hwtstamp_cleared++; |
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454 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n"); |
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455 } |
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456 } |
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457 |
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458 /** |
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459 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp |
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460 * @adapter: Board private structure. |
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461 * |
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462 * If we were asked to do hardware stamping and such a time stamp is |
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463 * available, then it must have been for this skb here because we only |
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464 * allow only one such packet into the queue. |
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465 **/ |
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466 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) |
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467 { |
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468 struct e1000_hw *hw = &adapter->hw; |
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469 struct skb_shared_hwtstamps shhwtstamps; |
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470 u64 regval; |
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471 |
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472 regval = rd32(E1000_TXSTMPL); |
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473 regval |= (u64)rd32(E1000_TXSTMPH) << 32; |
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474 |
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475 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); |
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476 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); |
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477 dev_kfree_skb_any(adapter->ptp_tx_skb); |
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478 adapter->ptp_tx_skb = NULL; |
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479 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
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480 } |
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481 |
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482 /** |
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483 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp |
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484 * @q_vector: Pointer to interrupt specific structure |
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485 * @va: Pointer to address containing Rx buffer |
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486 * @skb: Buffer containing timestamp and packet |
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487 * |
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488 * This function is meant to retrieve a timestamp from the first buffer of an |
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489 * incoming frame. The value is stored in little endian format starting on |
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490 * byte 8. |
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491 **/ |
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492 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, |
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493 unsigned char *va, |
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494 struct sk_buff *skb) |
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495 { |
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496 __le64 *regval = (__le64 *)va; |
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497 |
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498 /* The timestamp is recorded in little endian format. |
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499 * DWORD: 0 1 2 3 |
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500 * Field: Reserved Reserved SYSTIML SYSTIMH |
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501 */ |
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502 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), |
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503 le64_to_cpu(regval[1])); |
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504 } |
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505 |
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506 /** |
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507 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register |
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508 * @q_vector: Pointer to interrupt specific structure |
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509 * @skb: Buffer containing timestamp and packet |
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510 * |
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511 * This function is meant to retrieve a timestamp from the internal registers |
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512 * of the adapter and store it in the skb. |
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513 **/ |
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514 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, |
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515 struct sk_buff *skb) |
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516 { |
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517 struct igb_adapter *adapter = q_vector->adapter; |
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518 struct e1000_hw *hw = &adapter->hw; |
|
519 u64 regval; |
|
520 |
|
521 /* If this bit is set, then the RX registers contain the time stamp. No |
|
522 * other packet will be time stamped until we read these registers, so |
|
523 * read the registers to make them available again. Because only one |
|
524 * packet can be time stamped at a time, we know that the register |
|
525 * values must belong to this one here and therefore we don't need to |
|
526 * compare any of the additional attributes stored for it. |
|
527 * |
|
528 * If nothing went wrong, then it should have a shared tx_flags that we |
|
529 * can turn into a skb_shared_hwtstamps. |
|
530 */ |
|
531 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) |
|
532 return; |
|
533 |
|
534 regval = rd32(E1000_RXSTMPL); |
|
535 regval |= (u64)rd32(E1000_RXSTMPH) << 32; |
|
536 |
|
537 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); |
|
538 |
|
539 /* Update the last_rx_timestamp timer in order to enable watchdog check |
|
540 * for error case of latched timestamp on a dropped packet. |
|
541 */ |
|
542 adapter->last_rx_timestamp = jiffies; |
|
543 } |
|
544 |
|
545 /** |
|
546 * igb_ptp_get_ts_config - get hardware time stamping config |
|
547 * @netdev: |
|
548 * @ifreq: |
|
549 * |
|
550 * Get the hwtstamp_config settings to return to the user. Rather than attempt |
|
551 * to deconstruct the settings from the registers, just return a shadow copy |
|
552 * of the last known settings. |
|
553 **/ |
|
554 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr) |
|
555 { |
|
556 struct igb_adapter *adapter = netdev_priv(netdev); |
|
557 struct hwtstamp_config *config = &adapter->tstamp_config; |
|
558 |
|
559 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? |
|
560 -EFAULT : 0; |
|
561 } |
|
562 |
|
563 /** |
|
564 * igb_ptp_set_timestamp_mode - setup hardware for timestamping |
|
565 * @adapter: networking device structure |
|
566 * @config: hwtstamp configuration |
|
567 * |
|
568 * Outgoing time stamping can be enabled and disabled. Play nice and |
|
569 * disable it when requested, although it shouldn't case any overhead |
|
570 * when no packet needs it. At most one packet in the queue may be |
|
571 * marked for time stamping, otherwise it would be impossible to tell |
|
572 * for sure to which packet the hardware time stamp belongs. |
|
573 * |
|
574 * Incoming time stamping has to be configured via the hardware |
|
575 * filters. Not all combinations are supported, in particular event |
|
576 * type has to be specified. Matching the kind of event packet is |
|
577 * not supported, with the exception of "all V2 events regardless of |
|
578 * level 2 or 4". |
|
579 */ |
|
580 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter, |
|
581 struct hwtstamp_config *config) |
|
582 { |
|
583 struct e1000_hw *hw = &adapter->hw; |
|
584 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
|
585 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; |
|
586 u32 tsync_rx_cfg = 0; |
|
587 bool is_l4 = false; |
|
588 bool is_l2 = false; |
|
589 u32 regval; |
|
590 |
|
591 /* reserved for future extensions */ |
|
592 if (config->flags) |
|
593 return -EINVAL; |
|
594 |
|
595 switch (config->tx_type) { |
|
596 case HWTSTAMP_TX_OFF: |
|
597 tsync_tx_ctl = 0; |
|
598 case HWTSTAMP_TX_ON: |
|
599 break; |
|
600 default: |
|
601 return -ERANGE; |
|
602 } |
|
603 |
|
604 switch (config->rx_filter) { |
|
605 case HWTSTAMP_FILTER_NONE: |
|
606 tsync_rx_ctl = 0; |
|
607 break; |
|
608 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
|
609 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
|
610 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; |
|
611 is_l4 = true; |
|
612 break; |
|
613 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
|
614 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
|
615 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; |
|
616 is_l4 = true; |
|
617 break; |
|
618 case HWTSTAMP_FILTER_PTP_V2_EVENT: |
|
619 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
|
620 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
|
621 case HWTSTAMP_FILTER_PTP_V2_SYNC: |
|
622 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: |
|
623 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
|
624 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
|
625 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: |
|
626 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
|
627 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
|
628 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
|
629 is_l2 = true; |
|
630 is_l4 = true; |
|
631 break; |
|
632 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
|
633 case HWTSTAMP_FILTER_ALL: |
|
634 /* 82576 cannot timestamp all packets, which it needs to do to |
|
635 * support both V1 Sync and Delay_Req messages |
|
636 */ |
|
637 if (hw->mac.type != e1000_82576) { |
|
638 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
|
639 config->rx_filter = HWTSTAMP_FILTER_ALL; |
|
640 break; |
|
641 } |
|
642 /* fall through */ |
|
643 default: |
|
644 config->rx_filter = HWTSTAMP_FILTER_NONE; |
|
645 return -ERANGE; |
|
646 } |
|
647 |
|
648 if (hw->mac.type == e1000_82575) { |
|
649 if (tsync_rx_ctl | tsync_tx_ctl) |
|
650 return -EINVAL; |
|
651 return 0; |
|
652 } |
|
653 |
|
654 /* Per-packet timestamping only works if all packets are |
|
655 * timestamped, so enable timestamping in all packets as |
|
656 * long as one Rx filter was configured. |
|
657 */ |
|
658 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { |
|
659 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; |
|
660 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
|
661 config->rx_filter = HWTSTAMP_FILTER_ALL; |
|
662 is_l2 = true; |
|
663 is_l4 = true; |
|
664 |
|
665 if ((hw->mac.type == e1000_i210) || |
|
666 (hw->mac.type == e1000_i211)) { |
|
667 regval = rd32(E1000_RXPBS); |
|
668 regval |= E1000_RXPBS_CFG_TS_EN; |
|
669 wr32(E1000_RXPBS, regval); |
|
670 } |
|
671 } |
|
672 |
|
673 /* enable/disable TX */ |
|
674 regval = rd32(E1000_TSYNCTXCTL); |
|
675 regval &= ~E1000_TSYNCTXCTL_ENABLED; |
|
676 regval |= tsync_tx_ctl; |
|
677 wr32(E1000_TSYNCTXCTL, regval); |
|
678 |
|
679 /* enable/disable RX */ |
|
680 regval = rd32(E1000_TSYNCRXCTL); |
|
681 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); |
|
682 regval |= tsync_rx_ctl; |
|
683 wr32(E1000_TSYNCRXCTL, regval); |
|
684 |
|
685 /* define which PTP packets are time stamped */ |
|
686 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); |
|
687 |
|
688 /* define ethertype filter for timestamped packets */ |
|
689 if (is_l2) |
|
690 wr32(E1000_ETQF(3), |
|
691 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ |
|
692 E1000_ETQF_1588 | /* enable timestamping */ |
|
693 ETH_P_1588)); /* 1588 eth protocol type */ |
|
694 else |
|
695 wr32(E1000_ETQF(3), 0); |
|
696 |
|
697 /* L4 Queue Filter[3]: filter by destination port and protocol */ |
|
698 if (is_l4) { |
|
699 u32 ftqf = (IPPROTO_UDP /* UDP */ |
|
700 | E1000_FTQF_VF_BP /* VF not compared */ |
|
701 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ |
|
702 | E1000_FTQF_MASK); /* mask all inputs */ |
|
703 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ |
|
704 |
|
705 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); |
|
706 wr32(E1000_IMIREXT(3), |
|
707 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); |
|
708 if (hw->mac.type == e1000_82576) { |
|
709 /* enable source port check */ |
|
710 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); |
|
711 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; |
|
712 } |
|
713 wr32(E1000_FTQF(3), ftqf); |
|
714 } else { |
|
715 wr32(E1000_FTQF(3), E1000_FTQF_MASK); |
|
716 } |
|
717 wrfl(); |
|
718 |
|
719 /* clear TX/RX time stamp registers, just to be sure */ |
|
720 regval = rd32(E1000_TXSTMPL); |
|
721 regval = rd32(E1000_TXSTMPH); |
|
722 regval = rd32(E1000_RXSTMPL); |
|
723 regval = rd32(E1000_RXSTMPH); |
|
724 |
|
725 return 0; |
|
726 } |
|
727 |
|
728 /** |
|
729 * igb_ptp_set_ts_config - set hardware time stamping config |
|
730 * @netdev: |
|
731 * @ifreq: |
|
732 * |
|
733 **/ |
|
734 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr) |
|
735 { |
|
736 struct igb_adapter *adapter = netdev_priv(netdev); |
|
737 struct hwtstamp_config config; |
|
738 int err; |
|
739 |
|
740 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) |
|
741 return -EFAULT; |
|
742 |
|
743 err = igb_ptp_set_timestamp_mode(adapter, &config); |
|
744 if (err) |
|
745 return err; |
|
746 |
|
747 /* save these settings for future reference */ |
|
748 memcpy(&adapter->tstamp_config, &config, |
|
749 sizeof(adapter->tstamp_config)); |
|
750 |
|
751 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
|
752 -EFAULT : 0; |
|
753 } |
|
754 |
|
755 void igb_ptp_init(struct igb_adapter *adapter) |
|
756 { |
|
757 struct e1000_hw *hw = &adapter->hw; |
|
758 struct net_device *netdev = adapter->netdev; |
|
759 |
|
760 switch (hw->mac.type) { |
|
761 case e1000_82576: |
|
762 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
|
763 adapter->ptp_caps.owner = THIS_MODULE; |
|
764 adapter->ptp_caps.max_adj = 999999881; |
|
765 adapter->ptp_caps.n_ext_ts = 0; |
|
766 adapter->ptp_caps.pps = 0; |
|
767 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; |
|
768 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
|
769 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; |
|
770 adapter->ptp_caps.settime = igb_ptp_settime_82576; |
|
771 adapter->ptp_caps.enable = igb_ptp_feature_enable; |
|
772 adapter->cc.read = igb_ptp_read_82576; |
|
773 adapter->cc.mask = CLOCKSOURCE_MASK(64); |
|
774 adapter->cc.mult = 1; |
|
775 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; |
|
776 /* Dial the nominal frequency. */ |
|
777 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); |
|
778 break; |
|
779 case e1000_82580: |
|
780 case e1000_i354: |
|
781 case e1000_i350: |
|
782 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
|
783 adapter->ptp_caps.owner = THIS_MODULE; |
|
784 adapter->ptp_caps.max_adj = 62499999; |
|
785 adapter->ptp_caps.n_ext_ts = 0; |
|
786 adapter->ptp_caps.pps = 0; |
|
787 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
|
788 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; |
|
789 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; |
|
790 adapter->ptp_caps.settime = igb_ptp_settime_82576; |
|
791 adapter->ptp_caps.enable = igb_ptp_feature_enable; |
|
792 adapter->cc.read = igb_ptp_read_82580; |
|
793 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); |
|
794 adapter->cc.mult = 1; |
|
795 adapter->cc.shift = 0; |
|
796 /* Enable the timer functions by clearing bit 31. */ |
|
797 wr32(E1000_TSAUXC, 0x0); |
|
798 break; |
|
799 case e1000_i210: |
|
800 case e1000_i211: |
|
801 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); |
|
802 adapter->ptp_caps.owner = THIS_MODULE; |
|
803 adapter->ptp_caps.max_adj = 62499999; |
|
804 adapter->ptp_caps.n_ext_ts = 0; |
|
805 adapter->ptp_caps.pps = 0; |
|
806 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; |
|
807 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; |
|
808 adapter->ptp_caps.gettime = igb_ptp_gettime_i210; |
|
809 adapter->ptp_caps.settime = igb_ptp_settime_i210; |
|
810 adapter->ptp_caps.enable = igb_ptp_feature_enable; |
|
811 /* Enable the timer functions by clearing bit 31. */ |
|
812 wr32(E1000_TSAUXC, 0x0); |
|
813 break; |
|
814 default: |
|
815 adapter->ptp_clock = NULL; |
|
816 return; |
|
817 } |
|
818 |
|
819 wrfl(); |
|
820 |
|
821 spin_lock_init(&adapter->tmreg_lock); |
|
822 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); |
|
823 |
|
824 /* Initialize the clock and overflow work for devices that need it. */ |
|
825 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { |
|
826 struct timespec ts = ktime_to_timespec(ktime_get_real()); |
|
827 |
|
828 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); |
|
829 } else { |
|
830 timecounter_init(&adapter->tc, &adapter->cc, |
|
831 ktime_to_ns(ktime_get_real())); |
|
832 |
|
833 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, |
|
834 igb_ptp_overflow_check); |
|
835 |
|
836 schedule_delayed_work(&adapter->ptp_overflow_work, |
|
837 IGB_SYSTIM_OVERFLOW_PERIOD); |
|
838 } |
|
839 |
|
840 /* Initialize the time sync interrupts for devices that support it. */ |
|
841 if (hw->mac.type >= e1000_82580) { |
|
842 wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
|
843 wr32(E1000_IMS, E1000_IMS_TS); |
|
844 } |
|
845 |
|
846 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; |
|
847 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; |
|
848 |
|
849 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, |
|
850 &adapter->pdev->dev); |
|
851 if (IS_ERR(adapter->ptp_clock)) { |
|
852 adapter->ptp_clock = NULL; |
|
853 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); |
|
854 } else { |
|
855 dev_info(&adapter->pdev->dev, "added PHC on %s\n", |
|
856 adapter->netdev->name); |
|
857 adapter->flags |= IGB_FLAG_PTP; |
|
858 } |
|
859 } |
|
860 |
|
861 /** |
|
862 * igb_ptp_stop - Disable PTP device and stop the overflow check. |
|
863 * @adapter: Board private structure. |
|
864 * |
|
865 * This function stops the PTP support and cancels the delayed work. |
|
866 **/ |
|
867 void igb_ptp_stop(struct igb_adapter *adapter) |
|
868 { |
|
869 switch (adapter->hw.mac.type) { |
|
870 case e1000_82576: |
|
871 case e1000_82580: |
|
872 case e1000_i354: |
|
873 case e1000_i350: |
|
874 cancel_delayed_work_sync(&adapter->ptp_overflow_work); |
|
875 break; |
|
876 case e1000_i210: |
|
877 case e1000_i211: |
|
878 /* No delayed work to cancel. */ |
|
879 break; |
|
880 default: |
|
881 return; |
|
882 } |
|
883 |
|
884 cancel_work_sync(&adapter->ptp_tx_work); |
|
885 if (adapter->ptp_tx_skb) { |
|
886 dev_kfree_skb_any(adapter->ptp_tx_skb); |
|
887 adapter->ptp_tx_skb = NULL; |
|
888 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state); |
|
889 } |
|
890 |
|
891 if (adapter->ptp_clock) { |
|
892 ptp_clock_unregister(adapter->ptp_clock); |
|
893 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", |
|
894 adapter->netdev->name); |
|
895 adapter->flags &= ~IGB_FLAG_PTP; |
|
896 } |
|
897 } |
|
898 |
|
899 /** |
|
900 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. |
|
901 * @adapter: Board private structure. |
|
902 * |
|
903 * This function handles the reset work required to re-enable the PTP device. |
|
904 **/ |
|
905 void igb_ptp_reset(struct igb_adapter *adapter) |
|
906 { |
|
907 struct e1000_hw *hw = &adapter->hw; |
|
908 |
|
909 if (!(adapter->flags & IGB_FLAG_PTP)) |
|
910 return; |
|
911 |
|
912 /* reset the tstamp_config */ |
|
913 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); |
|
914 |
|
915 switch (adapter->hw.mac.type) { |
|
916 case e1000_82576: |
|
917 /* Dial the nominal frequency. */ |
|
918 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); |
|
919 break; |
|
920 case e1000_82580: |
|
921 case e1000_i354: |
|
922 case e1000_i350: |
|
923 case e1000_i210: |
|
924 case e1000_i211: |
|
925 /* Enable the timer functions and interrupts. */ |
|
926 wr32(E1000_TSAUXC, 0x0); |
|
927 wr32(E1000_TSIM, TSYNC_INTERRUPTS); |
|
928 wr32(E1000_IMS, E1000_IMS_TS); |
|
929 break; |
|
930 default: |
|
931 /* No work to do. */ |
|
932 return; |
|
933 } |
|
934 |
|
935 /* Re-initialize the timer. */ |
|
936 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { |
|
937 struct timespec ts = ktime_to_timespec(ktime_get_real()); |
|
938 |
|
939 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); |
|
940 } else { |
|
941 timecounter_init(&adapter->tc, &adapter->cc, |
|
942 ktime_to_ns(ktime_get_real())); |
|
943 } |
|
944 } |