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1 /* Intel(R) Gigabit Ethernet Linux driver |
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2 * Copyright(c) 2007-2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * You should have received a copy of the GNU General Public License along with |
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14 * this program; if not, see <http://www.gnu.org/licenses/>. |
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15 * |
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16 * The full GNU General Public License is included in this distribution in |
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17 * the file called "COPYING". |
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18 * |
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19 * Contact Information: |
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20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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22 */ |
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23 |
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24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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25 |
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26 #include <linux/module.h> |
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27 #include <linux/types.h> |
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28 #include <linux/init.h> |
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29 #include <linux/bitops.h> |
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30 #include <linux/vmalloc.h> |
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31 #include <linux/pagemap.h> |
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32 #include <linux/netdevice.h> |
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33 #include <linux/ipv6.h> |
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34 #include <linux/slab.h> |
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35 #include <net/checksum.h> |
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36 #include <net/ip6_checksum.h> |
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37 #include <linux/net_tstamp.h> |
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38 #include <linux/mii.h> |
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39 #include <linux/ethtool.h> |
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40 #include <linux/if.h> |
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41 #include <linux/if_vlan.h> |
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42 #include <linux/pci.h> |
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43 #include <linux/pci-aspm.h> |
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44 #include <linux/delay.h> |
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45 #include <linux/interrupt.h> |
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46 #include <linux/ip.h> |
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47 #include <linux/tcp.h> |
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48 #include <linux/sctp.h> |
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49 #include <linux/if_ether.h> |
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50 #include <linux/aer.h> |
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51 #include <linux/prefetch.h> |
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52 #include <linux/pm_runtime.h> |
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53 #ifdef CONFIG_IGB_DCA |
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54 #include <linux/dca.h> |
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55 #endif |
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56 #include <linux/i2c.h> |
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57 #include "igb.h" |
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58 |
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59 #define MAJ 5 |
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60 #define MIN 2 |
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61 #define BUILD 15 |
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62 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
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63 __stringify(BUILD) "-k" |
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64 char igb_driver_name[] = "igb"; |
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65 char igb_driver_version[] = DRV_VERSION; |
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66 static const char igb_driver_string[] = |
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67 "Intel(R) Gigabit Ethernet Network Driver"; |
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68 static const char igb_copyright[] = |
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69 "Copyright (c) 2007-2014 Intel Corporation."; |
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70 |
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71 static const struct e1000_info *igb_info_tbl[] = { |
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72 [board_82575] = &e1000_82575_info, |
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73 }; |
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74 |
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75 static const struct pci_device_id igb_pci_tbl[] = { |
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76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, |
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77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, |
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78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, |
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79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, |
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80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, |
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81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, |
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82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, |
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83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, |
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84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, |
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85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, |
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86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
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87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, |
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88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, |
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89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, |
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90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
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91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, |
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92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
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93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
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94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, |
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95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, |
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96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
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97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, |
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98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
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99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, |
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100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
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101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
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102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
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103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
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104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, |
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105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
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106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
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107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
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108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
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109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, |
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110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, |
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111 /* required last entry */ |
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112 {0, } |
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113 }; |
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114 |
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115 MODULE_DEVICE_TABLE(pci, igb_pci_tbl); |
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116 |
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117 static int igb_setup_all_tx_resources(struct igb_adapter *); |
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118 static int igb_setup_all_rx_resources(struct igb_adapter *); |
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119 static void igb_free_all_tx_resources(struct igb_adapter *); |
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120 static void igb_free_all_rx_resources(struct igb_adapter *); |
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121 static void igb_setup_mrqc(struct igb_adapter *); |
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122 static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
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123 static void igb_remove(struct pci_dev *pdev); |
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124 static int igb_sw_init(struct igb_adapter *); |
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125 static int igb_open(struct net_device *); |
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126 static int igb_close(struct net_device *); |
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127 static void igb_configure(struct igb_adapter *); |
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128 static void igb_configure_tx(struct igb_adapter *); |
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129 static void igb_configure_rx(struct igb_adapter *); |
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130 static void igb_clean_all_tx_rings(struct igb_adapter *); |
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131 static void igb_clean_all_rx_rings(struct igb_adapter *); |
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132 static void igb_clean_tx_ring(struct igb_ring *); |
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133 static void igb_clean_rx_ring(struct igb_ring *); |
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134 static void igb_set_rx_mode(struct net_device *); |
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135 static void igb_update_phy_info(unsigned long); |
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136 static void igb_watchdog(unsigned long); |
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137 static void igb_watchdog_task(struct work_struct *); |
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138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
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139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
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140 struct rtnl_link_stats64 *stats); |
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141 static int igb_change_mtu(struct net_device *, int); |
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142 static int igb_set_mac(struct net_device *, void *); |
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143 static void igb_set_uta(struct igb_adapter *adapter); |
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144 static irqreturn_t igb_intr(int irq, void *); |
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145 static irqreturn_t igb_intr_msi(int irq, void *); |
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146 static irqreturn_t igb_msix_other(int irq, void *); |
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147 static irqreturn_t igb_msix_ring(int irq, void *); |
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148 #ifdef CONFIG_IGB_DCA |
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149 static void igb_update_dca(struct igb_q_vector *); |
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150 static void igb_setup_dca(struct igb_adapter *); |
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151 #endif /* CONFIG_IGB_DCA */ |
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152 static int igb_poll(struct napi_struct *, int); |
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153 static bool igb_clean_tx_irq(struct igb_q_vector *); |
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154 static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
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155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
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156 static void igb_tx_timeout(struct net_device *); |
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157 static void igb_reset_task(struct work_struct *); |
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158 static void igb_vlan_mode(struct net_device *netdev, |
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159 netdev_features_t features); |
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160 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); |
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161 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); |
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162 static void igb_restore_vlan(struct igb_adapter *); |
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163 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
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164 static void igb_ping_all_vfs(struct igb_adapter *); |
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165 static void igb_msg_task(struct igb_adapter *); |
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166 static void igb_vmm_control(struct igb_adapter *); |
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167 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
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168 static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
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169 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
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170 static int igb_ndo_set_vf_vlan(struct net_device *netdev, |
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171 int vf, u16 vlan, u8 qos); |
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172 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int); |
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173 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
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174 bool setting); |
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175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, |
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176 struct ifla_vf_info *ivi); |
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177 static void igb_check_vf_rate_limit(struct igb_adapter *); |
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178 |
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179 #ifdef CONFIG_PCI_IOV |
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180 static int igb_vf_configure(struct igb_adapter *adapter, int vf); |
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181 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); |
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182 #endif |
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183 |
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184 #ifdef CONFIG_PM |
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185 #ifdef CONFIG_PM_SLEEP |
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186 static int igb_suspend(struct device *); |
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187 #endif |
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188 static int igb_resume(struct device *); |
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189 #ifdef CONFIG_PM_RUNTIME |
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190 static int igb_runtime_suspend(struct device *dev); |
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191 static int igb_runtime_resume(struct device *dev); |
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192 static int igb_runtime_idle(struct device *dev); |
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193 #endif |
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194 static const struct dev_pm_ops igb_pm_ops = { |
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195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) |
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196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, |
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197 igb_runtime_idle) |
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198 }; |
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199 #endif |
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200 static void igb_shutdown(struct pci_dev *); |
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201 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); |
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202 #ifdef CONFIG_IGB_DCA |
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203 static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
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204 static struct notifier_block dca_notifier = { |
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205 .notifier_call = igb_notify_dca, |
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206 .next = NULL, |
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207 .priority = 0 |
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208 }; |
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209 #endif |
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210 #ifdef CONFIG_NET_POLL_CONTROLLER |
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211 /* for netdump / net console */ |
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212 static void igb_netpoll(struct net_device *); |
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213 #endif |
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214 #ifdef CONFIG_PCI_IOV |
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215 static unsigned int max_vfs; |
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216 module_param(max_vfs, uint, 0); |
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217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); |
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218 #endif /* CONFIG_PCI_IOV */ |
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219 |
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220 static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
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221 pci_channel_state_t); |
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222 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); |
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223 static void igb_io_resume(struct pci_dev *); |
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224 |
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225 static const struct pci_error_handlers igb_err_handler = { |
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226 .error_detected = igb_io_error_detected, |
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227 .slot_reset = igb_io_slot_reset, |
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228 .resume = igb_io_resume, |
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229 }; |
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230 |
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231 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); |
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232 |
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233 static struct pci_driver igb_driver = { |
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234 .name = igb_driver_name, |
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235 .id_table = igb_pci_tbl, |
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236 .probe = igb_probe, |
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237 .remove = igb_remove, |
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238 #ifdef CONFIG_PM |
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239 .driver.pm = &igb_pm_ops, |
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240 #endif |
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241 .shutdown = igb_shutdown, |
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242 .sriov_configure = igb_pci_sriov_configure, |
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243 .err_handler = &igb_err_handler |
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244 }; |
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245 |
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246 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); |
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247 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); |
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248 MODULE_LICENSE("GPL"); |
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249 MODULE_VERSION(DRV_VERSION); |
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250 |
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251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
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252 static int debug = -1; |
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253 module_param(debug, int, 0); |
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254 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
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255 |
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256 struct igb_reg_info { |
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257 u32 ofs; |
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258 char *name; |
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259 }; |
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260 |
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261 static const struct igb_reg_info igb_reg_info_tbl[] = { |
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262 |
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263 /* General Registers */ |
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264 {E1000_CTRL, "CTRL"}, |
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265 {E1000_STATUS, "STATUS"}, |
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266 {E1000_CTRL_EXT, "CTRL_EXT"}, |
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267 |
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268 /* Interrupt Registers */ |
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269 {E1000_ICR, "ICR"}, |
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270 |
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271 /* RX Registers */ |
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272 {E1000_RCTL, "RCTL"}, |
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273 {E1000_RDLEN(0), "RDLEN"}, |
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274 {E1000_RDH(0), "RDH"}, |
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275 {E1000_RDT(0), "RDT"}, |
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276 {E1000_RXDCTL(0), "RXDCTL"}, |
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277 {E1000_RDBAL(0), "RDBAL"}, |
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278 {E1000_RDBAH(0), "RDBAH"}, |
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279 |
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280 /* TX Registers */ |
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281 {E1000_TCTL, "TCTL"}, |
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282 {E1000_TDBAL(0), "TDBAL"}, |
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283 {E1000_TDBAH(0), "TDBAH"}, |
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284 {E1000_TDLEN(0), "TDLEN"}, |
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285 {E1000_TDH(0), "TDH"}, |
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286 {E1000_TDT(0), "TDT"}, |
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287 {E1000_TXDCTL(0), "TXDCTL"}, |
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288 {E1000_TDFH, "TDFH"}, |
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289 {E1000_TDFT, "TDFT"}, |
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290 {E1000_TDFHS, "TDFHS"}, |
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291 {E1000_TDFPC, "TDFPC"}, |
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292 |
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293 /* List Terminator */ |
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294 {} |
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295 }; |
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296 |
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297 /* igb_regdump - register printout routine */ |
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298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) |
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299 { |
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300 int n = 0; |
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301 char rname[16]; |
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302 u32 regs[8]; |
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303 |
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304 switch (reginfo->ofs) { |
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305 case E1000_RDLEN(0): |
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306 for (n = 0; n < 4; n++) |
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307 regs[n] = rd32(E1000_RDLEN(n)); |
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308 break; |
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309 case E1000_RDH(0): |
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310 for (n = 0; n < 4; n++) |
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311 regs[n] = rd32(E1000_RDH(n)); |
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312 break; |
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313 case E1000_RDT(0): |
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314 for (n = 0; n < 4; n++) |
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315 regs[n] = rd32(E1000_RDT(n)); |
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316 break; |
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317 case E1000_RXDCTL(0): |
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318 for (n = 0; n < 4; n++) |
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319 regs[n] = rd32(E1000_RXDCTL(n)); |
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320 break; |
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321 case E1000_RDBAL(0): |
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322 for (n = 0; n < 4; n++) |
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323 regs[n] = rd32(E1000_RDBAL(n)); |
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324 break; |
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325 case E1000_RDBAH(0): |
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326 for (n = 0; n < 4; n++) |
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327 regs[n] = rd32(E1000_RDBAH(n)); |
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328 break; |
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329 case E1000_TDBAL(0): |
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330 for (n = 0; n < 4; n++) |
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331 regs[n] = rd32(E1000_RDBAL(n)); |
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332 break; |
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333 case E1000_TDBAH(0): |
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334 for (n = 0; n < 4; n++) |
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335 regs[n] = rd32(E1000_TDBAH(n)); |
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336 break; |
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337 case E1000_TDLEN(0): |
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338 for (n = 0; n < 4; n++) |
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339 regs[n] = rd32(E1000_TDLEN(n)); |
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340 break; |
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341 case E1000_TDH(0): |
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342 for (n = 0; n < 4; n++) |
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343 regs[n] = rd32(E1000_TDH(n)); |
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344 break; |
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345 case E1000_TDT(0): |
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346 for (n = 0; n < 4; n++) |
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347 regs[n] = rd32(E1000_TDT(n)); |
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348 break; |
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349 case E1000_TXDCTL(0): |
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350 for (n = 0; n < 4; n++) |
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351 regs[n] = rd32(E1000_TXDCTL(n)); |
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352 break; |
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353 default: |
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354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); |
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355 return; |
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356 } |
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357 |
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358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); |
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359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], |
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360 regs[2], regs[3]); |
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361 } |
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362 |
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363 /* igb_dump - Print registers, Tx-rings and Rx-rings */ |
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364 static void igb_dump(struct igb_adapter *adapter) |
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365 { |
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366 struct net_device *netdev = adapter->netdev; |
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367 struct e1000_hw *hw = &adapter->hw; |
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368 struct igb_reg_info *reginfo; |
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369 struct igb_ring *tx_ring; |
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370 union e1000_adv_tx_desc *tx_desc; |
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371 struct my_u0 { u64 a; u64 b; } *u0; |
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372 struct igb_ring *rx_ring; |
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373 union e1000_adv_rx_desc *rx_desc; |
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374 u32 staterr; |
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375 u16 i, n; |
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376 |
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377 if (!netif_msg_hw(adapter)) |
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378 return; |
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379 |
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380 /* Print netdevice Info */ |
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381 if (netdev) { |
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382 dev_info(&adapter->pdev->dev, "Net device Info\n"); |
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383 pr_info("Device Name state trans_start last_rx\n"); |
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384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, |
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385 netdev->state, netdev->trans_start, netdev->last_rx); |
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386 } |
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387 |
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388 /* Print Registers */ |
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389 dev_info(&adapter->pdev->dev, "Register Dump\n"); |
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390 pr_info(" Register Name Value\n"); |
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391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; |
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392 reginfo->name; reginfo++) { |
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393 igb_regdump(hw, reginfo); |
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394 } |
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395 |
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396 /* Print TX Ring Summary */ |
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397 if (!netdev || !netif_running(netdev)) |
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398 goto exit; |
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399 |
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400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); |
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401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
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402 for (n = 0; n < adapter->num_tx_queues; n++) { |
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403 struct igb_tx_buffer *buffer_info; |
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404 tx_ring = adapter->tx_ring[n]; |
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405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
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406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
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407 n, tx_ring->next_to_use, tx_ring->next_to_clean, |
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408 (u64)dma_unmap_addr(buffer_info, dma), |
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409 dma_unmap_len(buffer_info, len), |
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410 buffer_info->next_to_watch, |
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411 (u64)buffer_info->time_stamp); |
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412 } |
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413 |
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414 /* Print TX Rings */ |
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415 if (!netif_msg_tx_done(adapter)) |
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416 goto rx_ring_summary; |
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417 |
|
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); |
|
419 |
|
420 /* Transmit Descriptor Formats |
|
421 * |
|
422 * Advanced Transmit Descriptor |
|
423 * +--------------------------------------------------------------+ |
|
424 * 0 | Buffer Address [63:0] | |
|
425 * +--------------------------------------------------------------+ |
|
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | |
|
427 * +--------------------------------------------------------------+ |
|
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0 |
|
429 */ |
|
430 |
|
431 for (n = 0; n < adapter->num_tx_queues; n++) { |
|
432 tx_ring = adapter->tx_ring[n]; |
|
433 pr_info("------------------------------------\n"); |
|
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); |
|
435 pr_info("------------------------------------\n"); |
|
436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); |
|
437 |
|
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { |
|
439 const char *next_desc; |
|
440 struct igb_tx_buffer *buffer_info; |
|
441 tx_desc = IGB_TX_DESC(tx_ring, i); |
|
442 buffer_info = &tx_ring->tx_buffer_info[i]; |
|
443 u0 = (struct my_u0 *)tx_desc; |
|
444 if (i == tx_ring->next_to_use && |
|
445 i == tx_ring->next_to_clean) |
|
446 next_desc = " NTC/U"; |
|
447 else if (i == tx_ring->next_to_use) |
|
448 next_desc = " NTU"; |
|
449 else if (i == tx_ring->next_to_clean) |
|
450 next_desc = " NTC"; |
|
451 else |
|
452 next_desc = ""; |
|
453 |
|
454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", |
|
455 i, le64_to_cpu(u0->a), |
|
456 le64_to_cpu(u0->b), |
|
457 (u64)dma_unmap_addr(buffer_info, dma), |
|
458 dma_unmap_len(buffer_info, len), |
|
459 buffer_info->next_to_watch, |
|
460 (u64)buffer_info->time_stamp, |
|
461 buffer_info->skb, next_desc); |
|
462 |
|
463 if (netif_msg_pktdata(adapter) && buffer_info->skb) |
|
464 print_hex_dump(KERN_INFO, "", |
|
465 DUMP_PREFIX_ADDRESS, |
|
466 16, 1, buffer_info->skb->data, |
|
467 dma_unmap_len(buffer_info, len), |
|
468 true); |
|
469 } |
|
470 } |
|
471 |
|
472 /* Print RX Rings Summary */ |
|
473 rx_ring_summary: |
|
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); |
|
475 pr_info("Queue [NTU] [NTC]\n"); |
|
476 for (n = 0; n < adapter->num_rx_queues; n++) { |
|
477 rx_ring = adapter->rx_ring[n]; |
|
478 pr_info(" %5d %5X %5X\n", |
|
479 n, rx_ring->next_to_use, rx_ring->next_to_clean); |
|
480 } |
|
481 |
|
482 /* Print RX Rings */ |
|
483 if (!netif_msg_rx_status(adapter)) |
|
484 goto exit; |
|
485 |
|
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); |
|
487 |
|
488 /* Advanced Receive Descriptor (Read) Format |
|
489 * 63 1 0 |
|
490 * +-----------------------------------------------------+ |
|
491 * 0 | Packet Buffer Address [63:1] |A0/NSE| |
|
492 * +----------------------------------------------+------+ |
|
493 * 8 | Header Buffer Address [63:1] | DD | |
|
494 * +-----------------------------------------------------+ |
|
495 * |
|
496 * |
|
497 * Advanced Receive Descriptor (Write-Back) Format |
|
498 * |
|
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0 |
|
500 * +------------------------------------------------------+ |
|
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | |
|
502 * | Checksum Ident | | | | Type | Type | |
|
503 * +------------------------------------------------------+ |
|
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status | |
|
505 * +------------------------------------------------------+ |
|
506 * 63 48 47 32 31 20 19 0 |
|
507 */ |
|
508 |
|
509 for (n = 0; n < adapter->num_rx_queues; n++) { |
|
510 rx_ring = adapter->rx_ring[n]; |
|
511 pr_info("------------------------------------\n"); |
|
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); |
|
513 pr_info("------------------------------------\n"); |
|
514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); |
|
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); |
|
516 |
|
517 for (i = 0; i < rx_ring->count; i++) { |
|
518 const char *next_desc; |
|
519 struct igb_rx_buffer *buffer_info; |
|
520 buffer_info = &rx_ring->rx_buffer_info[i]; |
|
521 rx_desc = IGB_RX_DESC(rx_ring, i); |
|
522 u0 = (struct my_u0 *)rx_desc; |
|
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
|
524 |
|
525 if (i == rx_ring->next_to_use) |
|
526 next_desc = " NTU"; |
|
527 else if (i == rx_ring->next_to_clean) |
|
528 next_desc = " NTC"; |
|
529 else |
|
530 next_desc = ""; |
|
531 |
|
532 if (staterr & E1000_RXD_STAT_DD) { |
|
533 /* Descriptor Done */ |
|
534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", |
|
535 "RWB", i, |
|
536 le64_to_cpu(u0->a), |
|
537 le64_to_cpu(u0->b), |
|
538 next_desc); |
|
539 } else { |
|
540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", |
|
541 "R ", i, |
|
542 le64_to_cpu(u0->a), |
|
543 le64_to_cpu(u0->b), |
|
544 (u64)buffer_info->dma, |
|
545 next_desc); |
|
546 |
|
547 if (netif_msg_pktdata(adapter) && |
|
548 buffer_info->dma && buffer_info->page) { |
|
549 print_hex_dump(KERN_INFO, "", |
|
550 DUMP_PREFIX_ADDRESS, |
|
551 16, 1, |
|
552 page_address(buffer_info->page) + |
|
553 buffer_info->page_offset, |
|
554 IGB_RX_BUFSZ, true); |
|
555 } |
|
556 } |
|
557 } |
|
558 } |
|
559 |
|
560 exit: |
|
561 return; |
|
562 } |
|
563 |
|
564 /** |
|
565 * igb_get_i2c_data - Reads the I2C SDA data bit |
|
566 * @hw: pointer to hardware structure |
|
567 * @i2cctl: Current value of I2CCTL register |
|
568 * |
|
569 * Returns the I2C data bit value |
|
570 **/ |
|
571 static int igb_get_i2c_data(void *data) |
|
572 { |
|
573 struct igb_adapter *adapter = (struct igb_adapter *)data; |
|
574 struct e1000_hw *hw = &adapter->hw; |
|
575 s32 i2cctl = rd32(E1000_I2CPARAMS); |
|
576 |
|
577 return !!(i2cctl & E1000_I2C_DATA_IN); |
|
578 } |
|
579 |
|
580 /** |
|
581 * igb_set_i2c_data - Sets the I2C data bit |
|
582 * @data: pointer to hardware structure |
|
583 * @state: I2C data value (0 or 1) to set |
|
584 * |
|
585 * Sets the I2C data bit |
|
586 **/ |
|
587 static void igb_set_i2c_data(void *data, int state) |
|
588 { |
|
589 struct igb_adapter *adapter = (struct igb_adapter *)data; |
|
590 struct e1000_hw *hw = &adapter->hw; |
|
591 s32 i2cctl = rd32(E1000_I2CPARAMS); |
|
592 |
|
593 if (state) |
|
594 i2cctl |= E1000_I2C_DATA_OUT; |
|
595 else |
|
596 i2cctl &= ~E1000_I2C_DATA_OUT; |
|
597 |
|
598 i2cctl &= ~E1000_I2C_DATA_OE_N; |
|
599 i2cctl |= E1000_I2C_CLK_OE_N; |
|
600 wr32(E1000_I2CPARAMS, i2cctl); |
|
601 wrfl(); |
|
602 |
|
603 } |
|
604 |
|
605 /** |
|
606 * igb_set_i2c_clk - Sets the I2C SCL clock |
|
607 * @data: pointer to hardware structure |
|
608 * @state: state to set clock |
|
609 * |
|
610 * Sets the I2C clock line to state |
|
611 **/ |
|
612 static void igb_set_i2c_clk(void *data, int state) |
|
613 { |
|
614 struct igb_adapter *adapter = (struct igb_adapter *)data; |
|
615 struct e1000_hw *hw = &adapter->hw; |
|
616 s32 i2cctl = rd32(E1000_I2CPARAMS); |
|
617 |
|
618 if (state) { |
|
619 i2cctl |= E1000_I2C_CLK_OUT; |
|
620 i2cctl &= ~E1000_I2C_CLK_OE_N; |
|
621 } else { |
|
622 i2cctl &= ~E1000_I2C_CLK_OUT; |
|
623 i2cctl &= ~E1000_I2C_CLK_OE_N; |
|
624 } |
|
625 wr32(E1000_I2CPARAMS, i2cctl); |
|
626 wrfl(); |
|
627 } |
|
628 |
|
629 /** |
|
630 * igb_get_i2c_clk - Gets the I2C SCL clock state |
|
631 * @data: pointer to hardware structure |
|
632 * |
|
633 * Gets the I2C clock state |
|
634 **/ |
|
635 static int igb_get_i2c_clk(void *data) |
|
636 { |
|
637 struct igb_adapter *adapter = (struct igb_adapter *)data; |
|
638 struct e1000_hw *hw = &adapter->hw; |
|
639 s32 i2cctl = rd32(E1000_I2CPARAMS); |
|
640 |
|
641 return !!(i2cctl & E1000_I2C_CLK_IN); |
|
642 } |
|
643 |
|
644 static const struct i2c_algo_bit_data igb_i2c_algo = { |
|
645 .setsda = igb_set_i2c_data, |
|
646 .setscl = igb_set_i2c_clk, |
|
647 .getsda = igb_get_i2c_data, |
|
648 .getscl = igb_get_i2c_clk, |
|
649 .udelay = 5, |
|
650 .timeout = 20, |
|
651 }; |
|
652 |
|
653 /** |
|
654 * igb_get_hw_dev - return device |
|
655 * @hw: pointer to hardware structure |
|
656 * |
|
657 * used by hardware layer to print debugging information |
|
658 **/ |
|
659 struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
|
660 { |
|
661 struct igb_adapter *adapter = hw->back; |
|
662 return adapter->netdev; |
|
663 } |
|
664 |
|
665 /** |
|
666 * igb_init_module - Driver Registration Routine |
|
667 * |
|
668 * igb_init_module is the first routine called when the driver is |
|
669 * loaded. All it does is register with the PCI subsystem. |
|
670 **/ |
|
671 static int __init igb_init_module(void) |
|
672 { |
|
673 int ret; |
|
674 |
|
675 pr_info("%s - version %s\n", |
|
676 igb_driver_string, igb_driver_version); |
|
677 pr_info("%s\n", igb_copyright); |
|
678 |
|
679 #ifdef CONFIG_IGB_DCA |
|
680 dca_register_notify(&dca_notifier); |
|
681 #endif |
|
682 ret = pci_register_driver(&igb_driver); |
|
683 return ret; |
|
684 } |
|
685 |
|
686 module_init(igb_init_module); |
|
687 |
|
688 /** |
|
689 * igb_exit_module - Driver Exit Cleanup Routine |
|
690 * |
|
691 * igb_exit_module is called just before the driver is removed |
|
692 * from memory. |
|
693 **/ |
|
694 static void __exit igb_exit_module(void) |
|
695 { |
|
696 #ifdef CONFIG_IGB_DCA |
|
697 dca_unregister_notify(&dca_notifier); |
|
698 #endif |
|
699 pci_unregister_driver(&igb_driver); |
|
700 } |
|
701 |
|
702 module_exit(igb_exit_module); |
|
703 |
|
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
|
705 /** |
|
706 * igb_cache_ring_register - Descriptor ring to register mapping |
|
707 * @adapter: board private structure to initialize |
|
708 * |
|
709 * Once we know the feature-set enabled for the device, we'll cache |
|
710 * the register offset the descriptor ring is assigned to. |
|
711 **/ |
|
712 static void igb_cache_ring_register(struct igb_adapter *adapter) |
|
713 { |
|
714 int i = 0, j = 0; |
|
715 u32 rbase_offset = adapter->vfs_allocated_count; |
|
716 |
|
717 switch (adapter->hw.mac.type) { |
|
718 case e1000_82576: |
|
719 /* The queues are allocated for virtualization such that VF 0 |
|
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. |
|
721 * In order to avoid collision we start at the first free queue |
|
722 * and continue consuming queues in the same sequence |
|
723 */ |
|
724 if (adapter->vfs_allocated_count) { |
|
725 for (; i < adapter->rss_queues; i++) |
|
726 adapter->rx_ring[i]->reg_idx = rbase_offset + |
|
727 Q_IDX_82576(i); |
|
728 } |
|
729 /* Fall through */ |
|
730 case e1000_82575: |
|
731 case e1000_82580: |
|
732 case e1000_i350: |
|
733 case e1000_i354: |
|
734 case e1000_i210: |
|
735 case e1000_i211: |
|
736 /* Fall through */ |
|
737 default: |
|
738 for (; i < adapter->num_rx_queues; i++) |
|
739 adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
|
740 for (; j < adapter->num_tx_queues; j++) |
|
741 adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
|
742 break; |
|
743 } |
|
744 } |
|
745 |
|
746 u32 igb_rd32(struct e1000_hw *hw, u32 reg) |
|
747 { |
|
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); |
|
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); |
|
750 u32 value = 0; |
|
751 |
|
752 if (E1000_REMOVED(hw_addr)) |
|
753 return ~value; |
|
754 |
|
755 value = readl(&hw_addr[reg]); |
|
756 |
|
757 /* reads should not return all F's */ |
|
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) { |
|
759 struct net_device *netdev = igb->netdev; |
|
760 hw->hw_addr = NULL; |
|
761 netif_device_detach(netdev); |
|
762 netdev_err(netdev, "PCIe link lost, device now detached\n"); |
|
763 } |
|
764 |
|
765 return value; |
|
766 } |
|
767 |
|
768 /** |
|
769 * igb_write_ivar - configure ivar for given MSI-X vector |
|
770 * @hw: pointer to the HW structure |
|
771 * @msix_vector: vector number we are allocating to a given ring |
|
772 * @index: row index of IVAR register to write within IVAR table |
|
773 * @offset: column offset of in IVAR, should be multiple of 8 |
|
774 * |
|
775 * This function is intended to handle the writing of the IVAR register |
|
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns, |
|
777 * each containing an cause allocation for an Rx and Tx ring, and a |
|
778 * variable number of rows depending on the number of queues supported. |
|
779 **/ |
|
780 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, |
|
781 int index, int offset) |
|
782 { |
|
783 u32 ivar = array_rd32(E1000_IVAR0, index); |
|
784 |
|
785 /* clear any bits that are currently set */ |
|
786 ivar &= ~((u32)0xFF << offset); |
|
787 |
|
788 /* write vector and valid bit */ |
|
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; |
|
790 |
|
791 array_wr32(E1000_IVAR0, index, ivar); |
|
792 } |
|
793 |
|
794 #define IGB_N0_QUEUE -1 |
|
795 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
|
796 { |
|
797 struct igb_adapter *adapter = q_vector->adapter; |
|
798 struct e1000_hw *hw = &adapter->hw; |
|
799 int rx_queue = IGB_N0_QUEUE; |
|
800 int tx_queue = IGB_N0_QUEUE; |
|
801 u32 msixbm = 0; |
|
802 |
|
803 if (q_vector->rx.ring) |
|
804 rx_queue = q_vector->rx.ring->reg_idx; |
|
805 if (q_vector->tx.ring) |
|
806 tx_queue = q_vector->tx.ring->reg_idx; |
|
807 |
|
808 switch (hw->mac.type) { |
|
809 case e1000_82575: |
|
810 /* The 82575 assigns vectors using a bitmask, which matches the |
|
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one |
|
812 * or more queues to a vector, we write the appropriate bits |
|
813 * into the MSIXBM register for that vector. |
|
814 */ |
|
815 if (rx_queue > IGB_N0_QUEUE) |
|
816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
|
817 if (tx_queue > IGB_N0_QUEUE) |
|
818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
|
819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) |
|
820 msixbm |= E1000_EIMS_OTHER; |
|
821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
|
822 q_vector->eims_value = msixbm; |
|
823 break; |
|
824 case e1000_82576: |
|
825 /* 82576 uses a table that essentially consists of 2 columns |
|
826 * with 8 rows. The ordering is column-major so we use the |
|
827 * lower 3 bits as the row index, and the 4th bit as the |
|
828 * column offset. |
|
829 */ |
|
830 if (rx_queue > IGB_N0_QUEUE) |
|
831 igb_write_ivar(hw, msix_vector, |
|
832 rx_queue & 0x7, |
|
833 (rx_queue & 0x8) << 1); |
|
834 if (tx_queue > IGB_N0_QUEUE) |
|
835 igb_write_ivar(hw, msix_vector, |
|
836 tx_queue & 0x7, |
|
837 ((tx_queue & 0x8) << 1) + 8); |
|
838 q_vector->eims_value = 1 << msix_vector; |
|
839 break; |
|
840 case e1000_82580: |
|
841 case e1000_i350: |
|
842 case e1000_i354: |
|
843 case e1000_i210: |
|
844 case e1000_i211: |
|
845 /* On 82580 and newer adapters the scheme is similar to 82576 |
|
846 * however instead of ordering column-major we have things |
|
847 * ordered row-major. So we traverse the table by using |
|
848 * bit 0 as the column offset, and the remaining bits as the |
|
849 * row index. |
|
850 */ |
|
851 if (rx_queue > IGB_N0_QUEUE) |
|
852 igb_write_ivar(hw, msix_vector, |
|
853 rx_queue >> 1, |
|
854 (rx_queue & 0x1) << 4); |
|
855 if (tx_queue > IGB_N0_QUEUE) |
|
856 igb_write_ivar(hw, msix_vector, |
|
857 tx_queue >> 1, |
|
858 ((tx_queue & 0x1) << 4) + 8); |
|
859 q_vector->eims_value = 1 << msix_vector; |
|
860 break; |
|
861 default: |
|
862 BUG(); |
|
863 break; |
|
864 } |
|
865 |
|
866 /* add q_vector eims value to global eims_enable_mask */ |
|
867 adapter->eims_enable_mask |= q_vector->eims_value; |
|
868 |
|
869 /* configure q_vector to set itr on first interrupt */ |
|
870 q_vector->set_itr = 1; |
|
871 } |
|
872 |
|
873 /** |
|
874 * igb_configure_msix - Configure MSI-X hardware |
|
875 * @adapter: board private structure to initialize |
|
876 * |
|
877 * igb_configure_msix sets up the hardware to properly |
|
878 * generate MSI-X interrupts. |
|
879 **/ |
|
880 static void igb_configure_msix(struct igb_adapter *adapter) |
|
881 { |
|
882 u32 tmp; |
|
883 int i, vector = 0; |
|
884 struct e1000_hw *hw = &adapter->hw; |
|
885 |
|
886 adapter->eims_enable_mask = 0; |
|
887 |
|
888 /* set vector for other causes, i.e. link changes */ |
|
889 switch (hw->mac.type) { |
|
890 case e1000_82575: |
|
891 tmp = rd32(E1000_CTRL_EXT); |
|
892 /* enable MSI-X PBA support*/ |
|
893 tmp |= E1000_CTRL_EXT_PBA_CLR; |
|
894 |
|
895 /* Auto-Mask interrupts upon ICR read. */ |
|
896 tmp |= E1000_CTRL_EXT_EIAME; |
|
897 tmp |= E1000_CTRL_EXT_IRCA; |
|
898 |
|
899 wr32(E1000_CTRL_EXT, tmp); |
|
900 |
|
901 /* enable msix_other interrupt */ |
|
902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); |
|
903 adapter->eims_other = E1000_EIMS_OTHER; |
|
904 |
|
905 break; |
|
906 |
|
907 case e1000_82576: |
|
908 case e1000_82580: |
|
909 case e1000_i350: |
|
910 case e1000_i354: |
|
911 case e1000_i210: |
|
912 case e1000_i211: |
|
913 /* Turn on MSI-X capability first, or our settings |
|
914 * won't stick. And it will take days to debug. |
|
915 */ |
|
916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | |
|
917 E1000_GPIE_PBA | E1000_GPIE_EIAME | |
|
918 E1000_GPIE_NSICR); |
|
919 |
|
920 /* enable msix_other interrupt */ |
|
921 adapter->eims_other = 1 << vector; |
|
922 tmp = (vector++ | E1000_IVAR_VALID) << 8; |
|
923 |
|
924 wr32(E1000_IVAR_MISC, tmp); |
|
925 break; |
|
926 default: |
|
927 /* do nothing, since nothing else supports MSI-X */ |
|
928 break; |
|
929 } /* switch (hw->mac.type) */ |
|
930 |
|
931 adapter->eims_enable_mask |= adapter->eims_other; |
|
932 |
|
933 for (i = 0; i < adapter->num_q_vectors; i++) |
|
934 igb_assign_vector(adapter->q_vector[i], vector++); |
|
935 |
|
936 wrfl(); |
|
937 } |
|
938 |
|
939 /** |
|
940 * igb_request_msix - Initialize MSI-X interrupts |
|
941 * @adapter: board private structure to initialize |
|
942 * |
|
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the |
|
944 * kernel. |
|
945 **/ |
|
946 static int igb_request_msix(struct igb_adapter *adapter) |
|
947 { |
|
948 struct net_device *netdev = adapter->netdev; |
|
949 struct e1000_hw *hw = &adapter->hw; |
|
950 int i, err = 0, vector = 0, free_vector = 0; |
|
951 |
|
952 err = request_irq(adapter->msix_entries[vector].vector, |
|
953 igb_msix_other, 0, netdev->name, adapter); |
|
954 if (err) |
|
955 goto err_out; |
|
956 |
|
957 for (i = 0; i < adapter->num_q_vectors; i++) { |
|
958 struct igb_q_vector *q_vector = adapter->q_vector[i]; |
|
959 |
|
960 vector++; |
|
961 |
|
962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); |
|
963 |
|
964 if (q_vector->rx.ring && q_vector->tx.ring) |
|
965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
|
966 q_vector->rx.ring->queue_index); |
|
967 else if (q_vector->tx.ring) |
|
968 sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
|
969 q_vector->tx.ring->queue_index); |
|
970 else if (q_vector->rx.ring) |
|
971 sprintf(q_vector->name, "%s-rx-%u", netdev->name, |
|
972 q_vector->rx.ring->queue_index); |
|
973 else |
|
974 sprintf(q_vector->name, "%s-unused", netdev->name); |
|
975 |
|
976 err = request_irq(adapter->msix_entries[vector].vector, |
|
977 igb_msix_ring, 0, q_vector->name, |
|
978 q_vector); |
|
979 if (err) |
|
980 goto err_free; |
|
981 } |
|
982 |
|
983 igb_configure_msix(adapter); |
|
984 return 0; |
|
985 |
|
986 err_free: |
|
987 /* free already assigned IRQs */ |
|
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter); |
|
989 |
|
990 vector--; |
|
991 for (i = 0; i < vector; i++) { |
|
992 free_irq(adapter->msix_entries[free_vector++].vector, |
|
993 adapter->q_vector[i]); |
|
994 } |
|
995 err_out: |
|
996 return err; |
|
997 } |
|
998 |
|
999 /** |
|
1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector |
|
1001 * @adapter: board private structure to initialize |
|
1002 * @v_idx: Index of vector to be freed |
|
1003 * |
|
1004 * This function frees the memory allocated to the q_vector. |
|
1005 **/ |
|
1006 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) |
|
1007 { |
|
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
|
1009 |
|
1010 adapter->q_vector[v_idx] = NULL; |
|
1011 |
|
1012 /* igb_get_stats64() might access the rings on this vector, |
|
1013 * we must wait a grace period before freeing it. |
|
1014 */ |
|
1015 if (q_vector) |
|
1016 kfree_rcu(q_vector, rcu); |
|
1017 } |
|
1018 |
|
1019 /** |
|
1020 * igb_reset_q_vector - Reset config for interrupt vector |
|
1021 * @adapter: board private structure to initialize |
|
1022 * @v_idx: Index of vector to be reset |
|
1023 * |
|
1024 * If NAPI is enabled it will delete any references to the |
|
1025 * NAPI struct. This is preparation for igb_free_q_vector. |
|
1026 **/ |
|
1027 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) |
|
1028 { |
|
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
|
1030 |
|
1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet |
|
1032 * allocated. So, q_vector is NULL so we should stop here. |
|
1033 */ |
|
1034 if (!q_vector) |
|
1035 return; |
|
1036 |
|
1037 if (q_vector->tx.ring) |
|
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; |
|
1039 |
|
1040 if (q_vector->rx.ring) |
|
1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; |
|
1042 |
|
1043 netif_napi_del(&q_vector->napi); |
|
1044 |
|
1045 } |
|
1046 |
|
1047 static void igb_reset_interrupt_capability(struct igb_adapter *adapter) |
|
1048 { |
|
1049 int v_idx = adapter->num_q_vectors; |
|
1050 |
|
1051 if (adapter->flags & IGB_FLAG_HAS_MSIX) |
|
1052 pci_disable_msix(adapter->pdev); |
|
1053 else if (adapter->flags & IGB_FLAG_HAS_MSI) |
|
1054 pci_disable_msi(adapter->pdev); |
|
1055 |
|
1056 while (v_idx--) |
|
1057 igb_reset_q_vector(adapter, v_idx); |
|
1058 } |
|
1059 |
|
1060 /** |
|
1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors |
|
1062 * @adapter: board private structure to initialize |
|
1063 * |
|
1064 * This function frees the memory allocated to the q_vectors. In addition if |
|
1065 * NAPI is enabled it will delete any references to the NAPI struct prior |
|
1066 * to freeing the q_vector. |
|
1067 **/ |
|
1068 static void igb_free_q_vectors(struct igb_adapter *adapter) |
|
1069 { |
|
1070 int v_idx = adapter->num_q_vectors; |
|
1071 |
|
1072 adapter->num_tx_queues = 0; |
|
1073 adapter->num_rx_queues = 0; |
|
1074 adapter->num_q_vectors = 0; |
|
1075 |
|
1076 while (v_idx--) { |
|
1077 igb_reset_q_vector(adapter, v_idx); |
|
1078 igb_free_q_vector(adapter, v_idx); |
|
1079 } |
|
1080 } |
|
1081 |
|
1082 /** |
|
1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts |
|
1084 * @adapter: board private structure to initialize |
|
1085 * |
|
1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and |
|
1087 * MSI-X interrupts allocated. |
|
1088 */ |
|
1089 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) |
|
1090 { |
|
1091 igb_free_q_vectors(adapter); |
|
1092 igb_reset_interrupt_capability(adapter); |
|
1093 } |
|
1094 |
|
1095 /** |
|
1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported |
|
1097 * @adapter: board private structure to initialize |
|
1098 * @msix: boolean value of MSIX capability |
|
1099 * |
|
1100 * Attempt to configure interrupts using the best available |
|
1101 * capabilities of the hardware and kernel. |
|
1102 **/ |
|
1103 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) |
|
1104 { |
|
1105 int err; |
|
1106 int numvecs, i; |
|
1107 |
|
1108 if (!msix) |
|
1109 goto msi_only; |
|
1110 adapter->flags |= IGB_FLAG_HAS_MSIX; |
|
1111 |
|
1112 /* Number of supported queues. */ |
|
1113 adapter->num_rx_queues = adapter->rss_queues; |
|
1114 if (adapter->vfs_allocated_count) |
|
1115 adapter->num_tx_queues = 1; |
|
1116 else |
|
1117 adapter->num_tx_queues = adapter->rss_queues; |
|
1118 |
|
1119 /* start with one vector for every Rx queue */ |
|
1120 numvecs = adapter->num_rx_queues; |
|
1121 |
|
1122 /* if Tx handler is separate add 1 for every Tx queue */ |
|
1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
|
1124 numvecs += adapter->num_tx_queues; |
|
1125 |
|
1126 /* store the number of vectors reserved for queues */ |
|
1127 adapter->num_q_vectors = numvecs; |
|
1128 |
|
1129 /* add 1 vector for link status interrupts */ |
|
1130 numvecs++; |
|
1131 for (i = 0; i < numvecs; i++) |
|
1132 adapter->msix_entries[i].entry = i; |
|
1133 |
|
1134 err = pci_enable_msix_range(adapter->pdev, |
|
1135 adapter->msix_entries, |
|
1136 numvecs, |
|
1137 numvecs); |
|
1138 if (err > 0) |
|
1139 return; |
|
1140 |
|
1141 igb_reset_interrupt_capability(adapter); |
|
1142 |
|
1143 /* If we can't do MSI-X, try MSI */ |
|
1144 msi_only: |
|
1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX; |
|
1146 #ifdef CONFIG_PCI_IOV |
|
1147 /* disable SR-IOV for non MSI-X configurations */ |
|
1148 if (adapter->vf_data) { |
|
1149 struct e1000_hw *hw = &adapter->hw; |
|
1150 /* disable iov and allow time for transactions to clear */ |
|
1151 pci_disable_sriov(adapter->pdev); |
|
1152 msleep(500); |
|
1153 |
|
1154 kfree(adapter->vf_data); |
|
1155 adapter->vf_data = NULL; |
|
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); |
|
1157 wrfl(); |
|
1158 msleep(100); |
|
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); |
|
1160 } |
|
1161 #endif |
|
1162 adapter->vfs_allocated_count = 0; |
|
1163 adapter->rss_queues = 1; |
|
1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
|
1165 adapter->num_rx_queues = 1; |
|
1166 adapter->num_tx_queues = 1; |
|
1167 adapter->num_q_vectors = 1; |
|
1168 if (!pci_enable_msi(adapter->pdev)) |
|
1169 adapter->flags |= IGB_FLAG_HAS_MSI; |
|
1170 } |
|
1171 |
|
1172 static void igb_add_ring(struct igb_ring *ring, |
|
1173 struct igb_ring_container *head) |
|
1174 { |
|
1175 head->ring = ring; |
|
1176 head->count++; |
|
1177 } |
|
1178 |
|
1179 /** |
|
1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector |
|
1181 * @adapter: board private structure to initialize |
|
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving |
|
1183 * @v_idx: index of vector in adapter struct |
|
1184 * @txr_count: total number of Tx rings to allocate |
|
1185 * @txr_idx: index of first Tx ring to allocate |
|
1186 * @rxr_count: total number of Rx rings to allocate |
|
1187 * @rxr_idx: index of first Rx ring to allocate |
|
1188 * |
|
1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. |
|
1190 **/ |
|
1191 static int igb_alloc_q_vector(struct igb_adapter *adapter, |
|
1192 int v_count, int v_idx, |
|
1193 int txr_count, int txr_idx, |
|
1194 int rxr_count, int rxr_idx) |
|
1195 { |
|
1196 struct igb_q_vector *q_vector; |
|
1197 struct igb_ring *ring; |
|
1198 int ring_count, size; |
|
1199 |
|
1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ |
|
1201 if (txr_count > 1 || rxr_count > 1) |
|
1202 return -ENOMEM; |
|
1203 |
|
1204 ring_count = txr_count + rxr_count; |
|
1205 size = sizeof(struct igb_q_vector) + |
|
1206 (sizeof(struct igb_ring) * ring_count); |
|
1207 |
|
1208 /* allocate q_vector and rings */ |
|
1209 q_vector = adapter->q_vector[v_idx]; |
|
1210 if (!q_vector) |
|
1211 q_vector = kzalloc(size, GFP_KERNEL); |
|
1212 if (!q_vector) |
|
1213 return -ENOMEM; |
|
1214 |
|
1215 /* initialize NAPI */ |
|
1216 netif_napi_add(adapter->netdev, &q_vector->napi, |
|
1217 igb_poll, 64); |
|
1218 |
|
1219 /* tie q_vector and adapter together */ |
|
1220 adapter->q_vector[v_idx] = q_vector; |
|
1221 q_vector->adapter = adapter; |
|
1222 |
|
1223 /* initialize work limits */ |
|
1224 q_vector->tx.work_limit = adapter->tx_work_limit; |
|
1225 |
|
1226 /* initialize ITR configuration */ |
|
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); |
|
1228 q_vector->itr_val = IGB_START_ITR; |
|
1229 |
|
1230 /* initialize pointer to rings */ |
|
1231 ring = q_vector->ring; |
|
1232 |
|
1233 /* intialize ITR */ |
|
1234 if (rxr_count) { |
|
1235 /* rx or rx/tx vector */ |
|
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) |
|
1237 q_vector->itr_val = adapter->rx_itr_setting; |
|
1238 } else { |
|
1239 /* tx only vector */ |
|
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) |
|
1241 q_vector->itr_val = adapter->tx_itr_setting; |
|
1242 } |
|
1243 |
|
1244 if (txr_count) { |
|
1245 /* assign generic ring traits */ |
|
1246 ring->dev = &adapter->pdev->dev; |
|
1247 ring->netdev = adapter->netdev; |
|
1248 |
|
1249 /* configure backlink on ring */ |
|
1250 ring->q_vector = q_vector; |
|
1251 |
|
1252 /* update q_vector Tx values */ |
|
1253 igb_add_ring(ring, &q_vector->tx); |
|
1254 |
|
1255 /* For 82575, context index must be unique per ring. */ |
|
1256 if (adapter->hw.mac.type == e1000_82575) |
|
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); |
|
1258 |
|
1259 /* apply Tx specific ring traits */ |
|
1260 ring->count = adapter->tx_ring_count; |
|
1261 ring->queue_index = txr_idx; |
|
1262 |
|
1263 u64_stats_init(&ring->tx_syncp); |
|
1264 u64_stats_init(&ring->tx_syncp2); |
|
1265 |
|
1266 /* assign ring to adapter */ |
|
1267 adapter->tx_ring[txr_idx] = ring; |
|
1268 |
|
1269 /* push pointer to next ring */ |
|
1270 ring++; |
|
1271 } |
|
1272 |
|
1273 if (rxr_count) { |
|
1274 /* assign generic ring traits */ |
|
1275 ring->dev = &adapter->pdev->dev; |
|
1276 ring->netdev = adapter->netdev; |
|
1277 |
|
1278 /* configure backlink on ring */ |
|
1279 ring->q_vector = q_vector; |
|
1280 |
|
1281 /* update q_vector Rx values */ |
|
1282 igb_add_ring(ring, &q_vector->rx); |
|
1283 |
|
1284 /* set flag indicating ring supports SCTP checksum offload */ |
|
1285 if (adapter->hw.mac.type >= e1000_82576) |
|
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); |
|
1287 |
|
1288 /* On i350, i354, i210, and i211, loopback VLAN packets |
|
1289 * have the tag byte-swapped. |
|
1290 */ |
|
1291 if (adapter->hw.mac.type >= e1000_i350) |
|
1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); |
|
1293 |
|
1294 /* apply Rx specific ring traits */ |
|
1295 ring->count = adapter->rx_ring_count; |
|
1296 ring->queue_index = rxr_idx; |
|
1297 |
|
1298 u64_stats_init(&ring->rx_syncp); |
|
1299 |
|
1300 /* assign ring to adapter */ |
|
1301 adapter->rx_ring[rxr_idx] = ring; |
|
1302 } |
|
1303 |
|
1304 return 0; |
|
1305 } |
|
1306 |
|
1307 |
|
1308 /** |
|
1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors |
|
1310 * @adapter: board private structure to initialize |
|
1311 * |
|
1312 * We allocate one q_vector per queue interrupt. If allocation fails we |
|
1313 * return -ENOMEM. |
|
1314 **/ |
|
1315 static int igb_alloc_q_vectors(struct igb_adapter *adapter) |
|
1316 { |
|
1317 int q_vectors = adapter->num_q_vectors; |
|
1318 int rxr_remaining = adapter->num_rx_queues; |
|
1319 int txr_remaining = adapter->num_tx_queues; |
|
1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0; |
|
1321 int err; |
|
1322 |
|
1323 if (q_vectors >= (rxr_remaining + txr_remaining)) { |
|
1324 for (; rxr_remaining; v_idx++) { |
|
1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, |
|
1326 0, 0, 1, rxr_idx); |
|
1327 |
|
1328 if (err) |
|
1329 goto err_out; |
|
1330 |
|
1331 /* update counts and index */ |
|
1332 rxr_remaining--; |
|
1333 rxr_idx++; |
|
1334 } |
|
1335 } |
|
1336 |
|
1337 for (; v_idx < q_vectors; v_idx++) { |
|
1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); |
|
1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); |
|
1340 |
|
1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, |
|
1342 tqpv, txr_idx, rqpv, rxr_idx); |
|
1343 |
|
1344 if (err) |
|
1345 goto err_out; |
|
1346 |
|
1347 /* update counts and index */ |
|
1348 rxr_remaining -= rqpv; |
|
1349 txr_remaining -= tqpv; |
|
1350 rxr_idx++; |
|
1351 txr_idx++; |
|
1352 } |
|
1353 |
|
1354 return 0; |
|
1355 |
|
1356 err_out: |
|
1357 adapter->num_tx_queues = 0; |
|
1358 adapter->num_rx_queues = 0; |
|
1359 adapter->num_q_vectors = 0; |
|
1360 |
|
1361 while (v_idx--) |
|
1362 igb_free_q_vector(adapter, v_idx); |
|
1363 |
|
1364 return -ENOMEM; |
|
1365 } |
|
1366 |
|
1367 /** |
|
1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors |
|
1369 * @adapter: board private structure to initialize |
|
1370 * @msix: boolean value of MSIX capability |
|
1371 * |
|
1372 * This function initializes the interrupts and allocates all of the queues. |
|
1373 **/ |
|
1374 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) |
|
1375 { |
|
1376 struct pci_dev *pdev = adapter->pdev; |
|
1377 int err; |
|
1378 |
|
1379 igb_set_interrupt_capability(adapter, msix); |
|
1380 |
|
1381 err = igb_alloc_q_vectors(adapter); |
|
1382 if (err) { |
|
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); |
|
1384 goto err_alloc_q_vectors; |
|
1385 } |
|
1386 |
|
1387 igb_cache_ring_register(adapter); |
|
1388 |
|
1389 return 0; |
|
1390 |
|
1391 err_alloc_q_vectors: |
|
1392 igb_reset_interrupt_capability(adapter); |
|
1393 return err; |
|
1394 } |
|
1395 |
|
1396 /** |
|
1397 * igb_request_irq - initialize interrupts |
|
1398 * @adapter: board private structure to initialize |
|
1399 * |
|
1400 * Attempts to configure interrupts using the best available |
|
1401 * capabilities of the hardware and kernel. |
|
1402 **/ |
|
1403 static int igb_request_irq(struct igb_adapter *adapter) |
|
1404 { |
|
1405 struct net_device *netdev = adapter->netdev; |
|
1406 struct pci_dev *pdev = adapter->pdev; |
|
1407 int err = 0; |
|
1408 |
|
1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
1410 err = igb_request_msix(adapter); |
|
1411 if (!err) |
|
1412 goto request_done; |
|
1413 /* fall back to MSI */ |
|
1414 igb_free_all_tx_resources(adapter); |
|
1415 igb_free_all_rx_resources(adapter); |
|
1416 |
|
1417 igb_clear_interrupt_scheme(adapter); |
|
1418 err = igb_init_interrupt_scheme(adapter, false); |
|
1419 if (err) |
|
1420 goto request_done; |
|
1421 |
|
1422 igb_setup_all_tx_resources(adapter); |
|
1423 igb_setup_all_rx_resources(adapter); |
|
1424 igb_configure(adapter); |
|
1425 } |
|
1426 |
|
1427 igb_assign_vector(adapter->q_vector[0], 0); |
|
1428 |
|
1429 if (adapter->flags & IGB_FLAG_HAS_MSI) { |
|
1430 err = request_irq(pdev->irq, igb_intr_msi, 0, |
|
1431 netdev->name, adapter); |
|
1432 if (!err) |
|
1433 goto request_done; |
|
1434 |
|
1435 /* fall back to legacy interrupts */ |
|
1436 igb_reset_interrupt_capability(adapter); |
|
1437 adapter->flags &= ~IGB_FLAG_HAS_MSI; |
|
1438 } |
|
1439 |
|
1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, |
|
1441 netdev->name, adapter); |
|
1442 |
|
1443 if (err) |
|
1444 dev_err(&pdev->dev, "Error %d getting interrupt\n", |
|
1445 err); |
|
1446 |
|
1447 request_done: |
|
1448 return err; |
|
1449 } |
|
1450 |
|
1451 static void igb_free_irq(struct igb_adapter *adapter) |
|
1452 { |
|
1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
1454 int vector = 0, i; |
|
1455 |
|
1456 free_irq(adapter->msix_entries[vector++].vector, adapter); |
|
1457 |
|
1458 for (i = 0; i < adapter->num_q_vectors; i++) |
|
1459 free_irq(adapter->msix_entries[vector++].vector, |
|
1460 adapter->q_vector[i]); |
|
1461 } else { |
|
1462 free_irq(adapter->pdev->irq, adapter); |
|
1463 } |
|
1464 } |
|
1465 |
|
1466 /** |
|
1467 * igb_irq_disable - Mask off interrupt generation on the NIC |
|
1468 * @adapter: board private structure |
|
1469 **/ |
|
1470 static void igb_irq_disable(struct igb_adapter *adapter) |
|
1471 { |
|
1472 struct e1000_hw *hw = &adapter->hw; |
|
1473 |
|
1474 /* we need to be careful when disabling interrupts. The VFs are also |
|
1475 * mapped into these registers and so clearing the bits can cause |
|
1476 * issues on the VF drivers so we only need to clear what we set |
|
1477 */ |
|
1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
1479 u32 regval = rd32(E1000_EIAM); |
|
1480 |
|
1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); |
|
1482 wr32(E1000_EIMC, adapter->eims_enable_mask); |
|
1483 regval = rd32(E1000_EIAC); |
|
1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); |
|
1485 } |
|
1486 |
|
1487 wr32(E1000_IAM, 0); |
|
1488 wr32(E1000_IMC, ~0); |
|
1489 wrfl(); |
|
1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
1491 int i; |
|
1492 |
|
1493 for (i = 0; i < adapter->num_q_vectors; i++) |
|
1494 synchronize_irq(adapter->msix_entries[i].vector); |
|
1495 } else { |
|
1496 synchronize_irq(adapter->pdev->irq); |
|
1497 } |
|
1498 } |
|
1499 |
|
1500 /** |
|
1501 * igb_irq_enable - Enable default interrupt generation settings |
|
1502 * @adapter: board private structure |
|
1503 **/ |
|
1504 static void igb_irq_enable(struct igb_adapter *adapter) |
|
1505 { |
|
1506 struct e1000_hw *hw = &adapter->hw; |
|
1507 |
|
1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; |
|
1510 u32 regval = rd32(E1000_EIAC); |
|
1511 |
|
1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); |
|
1513 regval = rd32(E1000_EIAM); |
|
1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); |
|
1515 wr32(E1000_EIMS, adapter->eims_enable_mask); |
|
1516 if (adapter->vfs_allocated_count) { |
|
1517 wr32(E1000_MBVFIMR, 0xFF); |
|
1518 ims |= E1000_IMS_VMMB; |
|
1519 } |
|
1520 wr32(E1000_IMS, ims); |
|
1521 } else { |
|
1522 wr32(E1000_IMS, IMS_ENABLE_MASK | |
|
1523 E1000_IMS_DRSTA); |
|
1524 wr32(E1000_IAM, IMS_ENABLE_MASK | |
|
1525 E1000_IMS_DRSTA); |
|
1526 } |
|
1527 } |
|
1528 |
|
1529 static void igb_update_mng_vlan(struct igb_adapter *adapter) |
|
1530 { |
|
1531 struct e1000_hw *hw = &adapter->hw; |
|
1532 u16 vid = adapter->hw.mng_cookie.vlan_id; |
|
1533 u16 old_vid = adapter->mng_vlan_id; |
|
1534 |
|
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { |
|
1536 /* add VID to filter table */ |
|
1537 igb_vfta_set(hw, vid, true); |
|
1538 adapter->mng_vlan_id = vid; |
|
1539 } else { |
|
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; |
|
1541 } |
|
1542 |
|
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && |
|
1544 (vid != old_vid) && |
|
1545 !test_bit(old_vid, adapter->active_vlans)) { |
|
1546 /* remove VID from filter table */ |
|
1547 igb_vfta_set(hw, old_vid, false); |
|
1548 } |
|
1549 } |
|
1550 |
|
1551 /** |
|
1552 * igb_release_hw_control - release control of the h/w to f/w |
|
1553 * @adapter: address of board private structure |
|
1554 * |
|
1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. |
|
1556 * For ASF and Pass Through versions of f/w this means that the |
|
1557 * driver is no longer loaded. |
|
1558 **/ |
|
1559 static void igb_release_hw_control(struct igb_adapter *adapter) |
|
1560 { |
|
1561 struct e1000_hw *hw = &adapter->hw; |
|
1562 u32 ctrl_ext; |
|
1563 |
|
1564 /* Let firmware take over control of h/w */ |
|
1565 ctrl_ext = rd32(E1000_CTRL_EXT); |
|
1566 wr32(E1000_CTRL_EXT, |
|
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); |
|
1568 } |
|
1569 |
|
1570 /** |
|
1571 * igb_get_hw_control - get control of the h/w from f/w |
|
1572 * @adapter: address of board private structure |
|
1573 * |
|
1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. |
|
1575 * For ASF and Pass Through versions of f/w this means that |
|
1576 * the driver is loaded. |
|
1577 **/ |
|
1578 static void igb_get_hw_control(struct igb_adapter *adapter) |
|
1579 { |
|
1580 struct e1000_hw *hw = &adapter->hw; |
|
1581 u32 ctrl_ext; |
|
1582 |
|
1583 /* Let firmware know the driver has taken over */ |
|
1584 ctrl_ext = rd32(E1000_CTRL_EXT); |
|
1585 wr32(E1000_CTRL_EXT, |
|
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); |
|
1587 } |
|
1588 |
|
1589 /** |
|
1590 * igb_configure - configure the hardware for RX and TX |
|
1591 * @adapter: private board structure |
|
1592 **/ |
|
1593 static void igb_configure(struct igb_adapter *adapter) |
|
1594 { |
|
1595 struct net_device *netdev = adapter->netdev; |
|
1596 int i; |
|
1597 |
|
1598 igb_get_hw_control(adapter); |
|
1599 igb_set_rx_mode(netdev); |
|
1600 |
|
1601 igb_restore_vlan(adapter); |
|
1602 |
|
1603 igb_setup_tctl(adapter); |
|
1604 igb_setup_mrqc(adapter); |
|
1605 igb_setup_rctl(adapter); |
|
1606 |
|
1607 igb_configure_tx(adapter); |
|
1608 igb_configure_rx(adapter); |
|
1609 |
|
1610 igb_rx_fifo_flush_82575(&adapter->hw); |
|
1611 |
|
1612 /* call igb_desc_unused which always leaves |
|
1613 * at least 1 descriptor unused to make sure |
|
1614 * next_to_use != next_to_clean |
|
1615 */ |
|
1616 for (i = 0; i < adapter->num_rx_queues; i++) { |
|
1617 struct igb_ring *ring = adapter->rx_ring[i]; |
|
1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
|
1619 } |
|
1620 } |
|
1621 |
|
1622 /** |
|
1623 * igb_power_up_link - Power up the phy/serdes link |
|
1624 * @adapter: address of board private structure |
|
1625 **/ |
|
1626 void igb_power_up_link(struct igb_adapter *adapter) |
|
1627 { |
|
1628 igb_reset_phy(&adapter->hw); |
|
1629 |
|
1630 if (adapter->hw.phy.media_type == e1000_media_type_copper) |
|
1631 igb_power_up_phy_copper(&adapter->hw); |
|
1632 else |
|
1633 igb_power_up_serdes_link_82575(&adapter->hw); |
|
1634 |
|
1635 igb_setup_link(&adapter->hw); |
|
1636 } |
|
1637 |
|
1638 /** |
|
1639 * igb_power_down_link - Power down the phy/serdes link |
|
1640 * @adapter: address of board private structure |
|
1641 */ |
|
1642 static void igb_power_down_link(struct igb_adapter *adapter) |
|
1643 { |
|
1644 if (adapter->hw.phy.media_type == e1000_media_type_copper) |
|
1645 igb_power_down_phy_copper_82575(&adapter->hw); |
|
1646 else |
|
1647 igb_shutdown_serdes_link_82575(&adapter->hw); |
|
1648 } |
|
1649 |
|
1650 /** |
|
1651 * Detect and switch function for Media Auto Sense |
|
1652 * @adapter: address of the board private structure |
|
1653 **/ |
|
1654 static void igb_check_swap_media(struct igb_adapter *adapter) |
|
1655 { |
|
1656 struct e1000_hw *hw = &adapter->hw; |
|
1657 u32 ctrl_ext, connsw; |
|
1658 bool swap_now = false; |
|
1659 |
|
1660 ctrl_ext = rd32(E1000_CTRL_EXT); |
|
1661 connsw = rd32(E1000_CONNSW); |
|
1662 |
|
1663 /* need to live swap if current media is copper and we have fiber/serdes |
|
1664 * to go to. |
|
1665 */ |
|
1666 |
|
1667 if ((hw->phy.media_type == e1000_media_type_copper) && |
|
1668 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { |
|
1669 swap_now = true; |
|
1670 } else if (!(connsw & E1000_CONNSW_SERDESD)) { |
|
1671 /* copper signal takes time to appear */ |
|
1672 if (adapter->copper_tries < 4) { |
|
1673 adapter->copper_tries++; |
|
1674 connsw |= E1000_CONNSW_AUTOSENSE_CONF; |
|
1675 wr32(E1000_CONNSW, connsw); |
|
1676 return; |
|
1677 } else { |
|
1678 adapter->copper_tries = 0; |
|
1679 if ((connsw & E1000_CONNSW_PHYSD) && |
|
1680 (!(connsw & E1000_CONNSW_PHY_PDN))) { |
|
1681 swap_now = true; |
|
1682 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; |
|
1683 wr32(E1000_CONNSW, connsw); |
|
1684 } |
|
1685 } |
|
1686 } |
|
1687 |
|
1688 if (!swap_now) |
|
1689 return; |
|
1690 |
|
1691 switch (hw->phy.media_type) { |
|
1692 case e1000_media_type_copper: |
|
1693 netdev_info(adapter->netdev, |
|
1694 "MAS: changing media to fiber/serdes\n"); |
|
1695 ctrl_ext |= |
|
1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; |
|
1697 adapter->flags |= IGB_FLAG_MEDIA_RESET; |
|
1698 adapter->copper_tries = 0; |
|
1699 break; |
|
1700 case e1000_media_type_internal_serdes: |
|
1701 case e1000_media_type_fiber: |
|
1702 netdev_info(adapter->netdev, |
|
1703 "MAS: changing media to copper\n"); |
|
1704 ctrl_ext &= |
|
1705 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; |
|
1706 adapter->flags |= IGB_FLAG_MEDIA_RESET; |
|
1707 break; |
|
1708 default: |
|
1709 /* shouldn't get here during regular operation */ |
|
1710 netdev_err(adapter->netdev, |
|
1711 "AMS: Invalid media type found, returning\n"); |
|
1712 break; |
|
1713 } |
|
1714 wr32(E1000_CTRL_EXT, ctrl_ext); |
|
1715 } |
|
1716 |
|
1717 /** |
|
1718 * igb_up - Open the interface and prepare it to handle traffic |
|
1719 * @adapter: board private structure |
|
1720 **/ |
|
1721 int igb_up(struct igb_adapter *adapter) |
|
1722 { |
|
1723 struct e1000_hw *hw = &adapter->hw; |
|
1724 int i; |
|
1725 |
|
1726 /* hardware has been reset, we need to reload some things */ |
|
1727 igb_configure(adapter); |
|
1728 |
|
1729 clear_bit(__IGB_DOWN, &adapter->state); |
|
1730 |
|
1731 for (i = 0; i < adapter->num_q_vectors; i++) |
|
1732 napi_enable(&(adapter->q_vector[i]->napi)); |
|
1733 |
|
1734 if (adapter->flags & IGB_FLAG_HAS_MSIX) |
|
1735 igb_configure_msix(adapter); |
|
1736 else |
|
1737 igb_assign_vector(adapter->q_vector[0], 0); |
|
1738 |
|
1739 /* Clear any pending interrupts. */ |
|
1740 rd32(E1000_ICR); |
|
1741 igb_irq_enable(adapter); |
|
1742 |
|
1743 /* notify VFs that reset has been completed */ |
|
1744 if (adapter->vfs_allocated_count) { |
|
1745 u32 reg_data = rd32(E1000_CTRL_EXT); |
|
1746 |
|
1747 reg_data |= E1000_CTRL_EXT_PFRSTD; |
|
1748 wr32(E1000_CTRL_EXT, reg_data); |
|
1749 } |
|
1750 |
|
1751 netif_tx_start_all_queues(adapter->netdev); |
|
1752 |
|
1753 /* start the watchdog. */ |
|
1754 hw->mac.get_link_status = 1; |
|
1755 schedule_work(&adapter->watchdog_task); |
|
1756 |
|
1757 if ((adapter->flags & IGB_FLAG_EEE) && |
|
1758 (!hw->dev_spec._82575.eee_disable)) |
|
1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; |
|
1760 |
|
1761 return 0; |
|
1762 } |
|
1763 |
|
1764 void igb_down(struct igb_adapter *adapter) |
|
1765 { |
|
1766 struct net_device *netdev = adapter->netdev; |
|
1767 struct e1000_hw *hw = &adapter->hw; |
|
1768 u32 tctl, rctl; |
|
1769 int i; |
|
1770 |
|
1771 /* signal that we're down so the interrupt handler does not |
|
1772 * reschedule our watchdog timer |
|
1773 */ |
|
1774 set_bit(__IGB_DOWN, &adapter->state); |
|
1775 |
|
1776 /* disable receives in the hardware */ |
|
1777 rctl = rd32(E1000_RCTL); |
|
1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); |
|
1779 /* flush and sleep below */ |
|
1780 |
|
1781 netif_tx_stop_all_queues(netdev); |
|
1782 |
|
1783 /* disable transmits in the hardware */ |
|
1784 tctl = rd32(E1000_TCTL); |
|
1785 tctl &= ~E1000_TCTL_EN; |
|
1786 wr32(E1000_TCTL, tctl); |
|
1787 /* flush both disables and wait for them to finish */ |
|
1788 wrfl(); |
|
1789 usleep_range(10000, 11000); |
|
1790 |
|
1791 igb_irq_disable(adapter); |
|
1792 |
|
1793 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; |
|
1794 |
|
1795 for (i = 0; i < adapter->num_q_vectors; i++) { |
|
1796 if (adapter->q_vector[i]) { |
|
1797 napi_synchronize(&adapter->q_vector[i]->napi); |
|
1798 napi_disable(&adapter->q_vector[i]->napi); |
|
1799 } |
|
1800 } |
|
1801 |
|
1802 |
|
1803 del_timer_sync(&adapter->watchdog_timer); |
|
1804 del_timer_sync(&adapter->phy_info_timer); |
|
1805 |
|
1806 netif_carrier_off(netdev); |
|
1807 |
|
1808 /* record the stats before reset*/ |
|
1809 spin_lock(&adapter->stats64_lock); |
|
1810 igb_update_stats(adapter, &adapter->stats64); |
|
1811 spin_unlock(&adapter->stats64_lock); |
|
1812 |
|
1813 adapter->link_speed = 0; |
|
1814 adapter->link_duplex = 0; |
|
1815 |
|
1816 if (!pci_channel_offline(adapter->pdev)) |
|
1817 igb_reset(adapter); |
|
1818 igb_clean_all_tx_rings(adapter); |
|
1819 igb_clean_all_rx_rings(adapter); |
|
1820 #ifdef CONFIG_IGB_DCA |
|
1821 |
|
1822 /* since we reset the hardware DCA settings were cleared */ |
|
1823 igb_setup_dca(adapter); |
|
1824 #endif |
|
1825 } |
|
1826 |
|
1827 void igb_reinit_locked(struct igb_adapter *adapter) |
|
1828 { |
|
1829 WARN_ON(in_interrupt()); |
|
1830 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
|
1831 usleep_range(1000, 2000); |
|
1832 igb_down(adapter); |
|
1833 igb_up(adapter); |
|
1834 clear_bit(__IGB_RESETTING, &adapter->state); |
|
1835 } |
|
1836 |
|
1837 /** igb_enable_mas - Media Autosense re-enable after swap |
|
1838 * |
|
1839 * @adapter: adapter struct |
|
1840 **/ |
|
1841 static s32 igb_enable_mas(struct igb_adapter *adapter) |
|
1842 { |
|
1843 struct e1000_hw *hw = &adapter->hw; |
|
1844 u32 connsw; |
|
1845 s32 ret_val = 0; |
|
1846 |
|
1847 connsw = rd32(E1000_CONNSW); |
|
1848 if (!(hw->phy.media_type == e1000_media_type_copper)) |
|
1849 return ret_val; |
|
1850 |
|
1851 /* configure for SerDes media detect */ |
|
1852 if (!(connsw & E1000_CONNSW_SERDESD)) { |
|
1853 connsw |= E1000_CONNSW_ENRGSRC; |
|
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN; |
|
1855 wr32(E1000_CONNSW, connsw); |
|
1856 wrfl(); |
|
1857 } else if (connsw & E1000_CONNSW_SERDESD) { |
|
1858 /* already SerDes, no need to enable anything */ |
|
1859 return ret_val; |
|
1860 } else { |
|
1861 netdev_info(adapter->netdev, |
|
1862 "MAS: Unable to configure feature, disabling..\n"); |
|
1863 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; |
|
1864 } |
|
1865 return ret_val; |
|
1866 } |
|
1867 |
|
1868 void igb_reset(struct igb_adapter *adapter) |
|
1869 { |
|
1870 struct pci_dev *pdev = adapter->pdev; |
|
1871 struct e1000_hw *hw = &adapter->hw; |
|
1872 struct e1000_mac_info *mac = &hw->mac; |
|
1873 struct e1000_fc_info *fc = &hw->fc; |
|
1874 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; |
|
1875 |
|
1876 /* Repartition Pba for greater than 9k mtu |
|
1877 * To take effect CTRL.RST is required. |
|
1878 */ |
|
1879 switch (mac->type) { |
|
1880 case e1000_i350: |
|
1881 case e1000_i354: |
|
1882 case e1000_82580: |
|
1883 pba = rd32(E1000_RXPBS); |
|
1884 pba = igb_rxpbs_adjust_82580(pba); |
|
1885 break; |
|
1886 case e1000_82576: |
|
1887 pba = rd32(E1000_RXPBS); |
|
1888 pba &= E1000_RXPBS_SIZE_MASK_82576; |
|
1889 break; |
|
1890 case e1000_82575: |
|
1891 case e1000_i210: |
|
1892 case e1000_i211: |
|
1893 default: |
|
1894 pba = E1000_PBA_34K; |
|
1895 break; |
|
1896 } |
|
1897 |
|
1898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
|
1899 (mac->type < e1000_82576)) { |
|
1900 /* adjust PBA for jumbo frames */ |
|
1901 wr32(E1000_PBA, pba); |
|
1902 |
|
1903 /* To maintain wire speed transmits, the Tx FIFO should be |
|
1904 * large enough to accommodate two full transmit packets, |
|
1905 * rounded up to the next 1KB and expressed in KB. Likewise, |
|
1906 * the Rx FIFO should be large enough to accommodate at least |
|
1907 * one full receive packet and is similarly rounded up and |
|
1908 * expressed in KB. |
|
1909 */ |
|
1910 pba = rd32(E1000_PBA); |
|
1911 /* upper 16 bits has Tx packet buffer allocation size in KB */ |
|
1912 tx_space = pba >> 16; |
|
1913 /* lower 16 bits has Rx packet buffer allocation size in KB */ |
|
1914 pba &= 0xffff; |
|
1915 /* the Tx fifo also stores 16 bytes of information about the Tx |
|
1916 * but don't include ethernet FCS because hardware appends it |
|
1917 */ |
|
1918 min_tx_space = (adapter->max_frame_size + |
|
1919 sizeof(union e1000_adv_tx_desc) - |
|
1920 ETH_FCS_LEN) * 2; |
|
1921 min_tx_space = ALIGN(min_tx_space, 1024); |
|
1922 min_tx_space >>= 10; |
|
1923 /* software strips receive CRC, so leave room for it */ |
|
1924 min_rx_space = adapter->max_frame_size; |
|
1925 min_rx_space = ALIGN(min_rx_space, 1024); |
|
1926 min_rx_space >>= 10; |
|
1927 |
|
1928 /* If current Tx allocation is less than the min Tx FIFO size, |
|
1929 * and the min Tx FIFO size is less than the current Rx FIFO |
|
1930 * allocation, take space away from current Rx allocation |
|
1931 */ |
|
1932 if (tx_space < min_tx_space && |
|
1933 ((min_tx_space - tx_space) < pba)) { |
|
1934 pba = pba - (min_tx_space - tx_space); |
|
1935 |
|
1936 /* if short on Rx space, Rx wins and must trump Tx |
|
1937 * adjustment |
|
1938 */ |
|
1939 if (pba < min_rx_space) |
|
1940 pba = min_rx_space; |
|
1941 } |
|
1942 wr32(E1000_PBA, pba); |
|
1943 } |
|
1944 |
|
1945 /* flow control settings */ |
|
1946 /* The high water mark must be low enough to fit one full frame |
|
1947 * (or the size used for early receive) above it in the Rx FIFO. |
|
1948 * Set it to the lower of: |
|
1949 * - 90% of the Rx FIFO size, or |
|
1950 * - the full Rx FIFO size minus one full frame |
|
1951 */ |
|
1952 hwm = min(((pba << 10) * 9 / 10), |
|
1953 ((pba << 10) - 2 * adapter->max_frame_size)); |
|
1954 |
|
1955 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ |
|
1956 fc->low_water = fc->high_water - 16; |
|
1957 fc->pause_time = 0xFFFF; |
|
1958 fc->send_xon = 1; |
|
1959 fc->current_mode = fc->requested_mode; |
|
1960 |
|
1961 /* disable receive for all VFs and wait one second */ |
|
1962 if (adapter->vfs_allocated_count) { |
|
1963 int i; |
|
1964 |
|
1965 for (i = 0 ; i < adapter->vfs_allocated_count; i++) |
|
1966 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
|
1967 |
|
1968 /* ping all the active vfs to let them know we are going down */ |
|
1969 igb_ping_all_vfs(adapter); |
|
1970 |
|
1971 /* disable transmits and receives */ |
|
1972 wr32(E1000_VFRE, 0); |
|
1973 wr32(E1000_VFTE, 0); |
|
1974 } |
|
1975 |
|
1976 /* Allow time for pending master requests to run */ |
|
1977 hw->mac.ops.reset_hw(hw); |
|
1978 wr32(E1000_WUC, 0); |
|
1979 |
|
1980 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { |
|
1981 /* need to resetup here after media swap */ |
|
1982 adapter->ei.get_invariants(hw); |
|
1983 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; |
|
1984 } |
|
1985 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { |
|
1986 if (igb_enable_mas(adapter)) |
|
1987 dev_err(&pdev->dev, |
|
1988 "Error enabling Media Auto Sense\n"); |
|
1989 } |
|
1990 if (hw->mac.ops.init_hw(hw)) |
|
1991 dev_err(&pdev->dev, "Hardware Error\n"); |
|
1992 |
|
1993 /* Flow control settings reset on hardware reset, so guarantee flow |
|
1994 * control is off when forcing speed. |
|
1995 */ |
|
1996 if (!hw->mac.autoneg) |
|
1997 igb_force_mac_fc(hw); |
|
1998 |
|
1999 igb_init_dmac(adapter, pba); |
|
2000 #ifdef CONFIG_IGB_HWMON |
|
2001 /* Re-initialize the thermal sensor on i350 devices. */ |
|
2002 if (!test_bit(__IGB_DOWN, &adapter->state)) { |
|
2003 if (mac->type == e1000_i350 && hw->bus.func == 0) { |
|
2004 /* If present, re-initialize the external thermal sensor |
|
2005 * interface. |
|
2006 */ |
|
2007 if (adapter->ets) |
|
2008 mac->ops.init_thermal_sensor_thresh(hw); |
|
2009 } |
|
2010 } |
|
2011 #endif |
|
2012 /* Re-establish EEE setting */ |
|
2013 if (hw->phy.media_type == e1000_media_type_copper) { |
|
2014 switch (mac->type) { |
|
2015 case e1000_i350: |
|
2016 case e1000_i210: |
|
2017 case e1000_i211: |
|
2018 igb_set_eee_i350(hw, true, true); |
|
2019 break; |
|
2020 case e1000_i354: |
|
2021 igb_set_eee_i354(hw, true, true); |
|
2022 break; |
|
2023 default: |
|
2024 break; |
|
2025 } |
|
2026 } |
|
2027 if (!netif_running(adapter->netdev)) |
|
2028 igb_power_down_link(adapter); |
|
2029 |
|
2030 igb_update_mng_vlan(adapter); |
|
2031 |
|
2032 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ |
|
2033 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); |
|
2034 |
|
2035 /* Re-enable PTP, where applicable. */ |
|
2036 igb_ptp_reset(adapter); |
|
2037 |
|
2038 igb_get_phy_info(hw); |
|
2039 } |
|
2040 |
|
2041 static netdev_features_t igb_fix_features(struct net_device *netdev, |
|
2042 netdev_features_t features) |
|
2043 { |
|
2044 /* Since there is no support for separate Rx/Tx vlan accel |
|
2045 * enable/disable make sure Tx flag is always in same state as Rx. |
|
2046 */ |
|
2047 if (features & NETIF_F_HW_VLAN_CTAG_RX) |
|
2048 features |= NETIF_F_HW_VLAN_CTAG_TX; |
|
2049 else |
|
2050 features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
|
2051 |
|
2052 return features; |
|
2053 } |
|
2054 |
|
2055 static int igb_set_features(struct net_device *netdev, |
|
2056 netdev_features_t features) |
|
2057 { |
|
2058 netdev_features_t changed = netdev->features ^ features; |
|
2059 struct igb_adapter *adapter = netdev_priv(netdev); |
|
2060 |
|
2061 if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
|
2062 igb_vlan_mode(netdev, features); |
|
2063 |
|
2064 if (!(changed & NETIF_F_RXALL)) |
|
2065 return 0; |
|
2066 |
|
2067 netdev->features = features; |
|
2068 |
|
2069 if (netif_running(netdev)) |
|
2070 igb_reinit_locked(adapter); |
|
2071 else |
|
2072 igb_reset(adapter); |
|
2073 |
|
2074 return 0; |
|
2075 } |
|
2076 |
|
2077 static const struct net_device_ops igb_netdev_ops = { |
|
2078 .ndo_open = igb_open, |
|
2079 .ndo_stop = igb_close, |
|
2080 .ndo_start_xmit = igb_xmit_frame, |
|
2081 .ndo_get_stats64 = igb_get_stats64, |
|
2082 .ndo_set_rx_mode = igb_set_rx_mode, |
|
2083 .ndo_set_mac_address = igb_set_mac, |
|
2084 .ndo_change_mtu = igb_change_mtu, |
|
2085 .ndo_do_ioctl = igb_ioctl, |
|
2086 .ndo_tx_timeout = igb_tx_timeout, |
|
2087 .ndo_validate_addr = eth_validate_addr, |
|
2088 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
|
2089 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, |
|
2090 .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
|
2091 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, |
|
2092 .ndo_set_vf_rate = igb_ndo_set_vf_bw, |
|
2093 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, |
|
2094 .ndo_get_vf_config = igb_ndo_get_vf_config, |
|
2095 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2096 .ndo_poll_controller = igb_netpoll, |
|
2097 #endif |
|
2098 .ndo_fix_features = igb_fix_features, |
|
2099 .ndo_set_features = igb_set_features, |
|
2100 }; |
|
2101 |
|
2102 /** |
|
2103 * igb_set_fw_version - Configure version string for ethtool |
|
2104 * @adapter: adapter struct |
|
2105 **/ |
|
2106 void igb_set_fw_version(struct igb_adapter *adapter) |
|
2107 { |
|
2108 struct e1000_hw *hw = &adapter->hw; |
|
2109 struct e1000_fw_version fw; |
|
2110 |
|
2111 igb_get_fw_version(hw, &fw); |
|
2112 |
|
2113 switch (hw->mac.type) { |
|
2114 case e1000_i210: |
|
2115 case e1000_i211: |
|
2116 if (!(igb_get_flash_presence_i210(hw))) { |
|
2117 snprintf(adapter->fw_version, |
|
2118 sizeof(adapter->fw_version), |
|
2119 "%2d.%2d-%d", |
|
2120 fw.invm_major, fw.invm_minor, |
|
2121 fw.invm_img_type); |
|
2122 break; |
|
2123 } |
|
2124 /* fall through */ |
|
2125 default: |
|
2126 /* if option is rom valid, display its version too */ |
|
2127 if (fw.or_valid) { |
|
2128 snprintf(adapter->fw_version, |
|
2129 sizeof(adapter->fw_version), |
|
2130 "%d.%d, 0x%08x, %d.%d.%d", |
|
2131 fw.eep_major, fw.eep_minor, fw.etrack_id, |
|
2132 fw.or_major, fw.or_build, fw.or_patch); |
|
2133 /* no option rom */ |
|
2134 } else if (fw.etrack_id != 0X0000) { |
|
2135 snprintf(adapter->fw_version, |
|
2136 sizeof(adapter->fw_version), |
|
2137 "%d.%d, 0x%08x", |
|
2138 fw.eep_major, fw.eep_minor, fw.etrack_id); |
|
2139 } else { |
|
2140 snprintf(adapter->fw_version, |
|
2141 sizeof(adapter->fw_version), |
|
2142 "%d.%d.%d", |
|
2143 fw.eep_major, fw.eep_minor, fw.eep_build); |
|
2144 } |
|
2145 break; |
|
2146 } |
|
2147 } |
|
2148 |
|
2149 /** |
|
2150 * igb_init_mas - init Media Autosense feature if enabled in the NVM |
|
2151 * |
|
2152 * @adapter: adapter struct |
|
2153 **/ |
|
2154 static void igb_init_mas(struct igb_adapter *adapter) |
|
2155 { |
|
2156 struct e1000_hw *hw = &adapter->hw; |
|
2157 u16 eeprom_data; |
|
2158 |
|
2159 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); |
|
2160 switch (hw->bus.func) { |
|
2161 case E1000_FUNC_0: |
|
2162 if (eeprom_data & IGB_MAS_ENABLE_0) { |
|
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE; |
|
2164 netdev_info(adapter->netdev, |
|
2165 "MAS: Enabling Media Autosense for port %d\n", |
|
2166 hw->bus.func); |
|
2167 } |
|
2168 break; |
|
2169 case E1000_FUNC_1: |
|
2170 if (eeprom_data & IGB_MAS_ENABLE_1) { |
|
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE; |
|
2172 netdev_info(adapter->netdev, |
|
2173 "MAS: Enabling Media Autosense for port %d\n", |
|
2174 hw->bus.func); |
|
2175 } |
|
2176 break; |
|
2177 case E1000_FUNC_2: |
|
2178 if (eeprom_data & IGB_MAS_ENABLE_2) { |
|
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE; |
|
2180 netdev_info(adapter->netdev, |
|
2181 "MAS: Enabling Media Autosense for port %d\n", |
|
2182 hw->bus.func); |
|
2183 } |
|
2184 break; |
|
2185 case E1000_FUNC_3: |
|
2186 if (eeprom_data & IGB_MAS_ENABLE_3) { |
|
2187 adapter->flags |= IGB_FLAG_MAS_ENABLE; |
|
2188 netdev_info(adapter->netdev, |
|
2189 "MAS: Enabling Media Autosense for port %d\n", |
|
2190 hw->bus.func); |
|
2191 } |
|
2192 break; |
|
2193 default: |
|
2194 /* Shouldn't get here */ |
|
2195 netdev_err(adapter->netdev, |
|
2196 "MAS: Invalid port configuration, returning\n"); |
|
2197 break; |
|
2198 } |
|
2199 } |
|
2200 |
|
2201 /** |
|
2202 * igb_init_i2c - Init I2C interface |
|
2203 * @adapter: pointer to adapter structure |
|
2204 **/ |
|
2205 static s32 igb_init_i2c(struct igb_adapter *adapter) |
|
2206 { |
|
2207 s32 status = 0; |
|
2208 |
|
2209 /* I2C interface supported on i350 devices */ |
|
2210 if (adapter->hw.mac.type != e1000_i350) |
|
2211 return 0; |
|
2212 |
|
2213 /* Initialize the i2c bus which is controlled by the registers. |
|
2214 * This bus will use the i2c_algo_bit structue that implements |
|
2215 * the protocol through toggling of the 4 bits in the register. |
|
2216 */ |
|
2217 adapter->i2c_adap.owner = THIS_MODULE; |
|
2218 adapter->i2c_algo = igb_i2c_algo; |
|
2219 adapter->i2c_algo.data = adapter; |
|
2220 adapter->i2c_adap.algo_data = &adapter->i2c_algo; |
|
2221 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; |
|
2222 strlcpy(adapter->i2c_adap.name, "igb BB", |
|
2223 sizeof(adapter->i2c_adap.name)); |
|
2224 status = i2c_bit_add_bus(&adapter->i2c_adap); |
|
2225 return status; |
|
2226 } |
|
2227 |
|
2228 /** |
|
2229 * igb_probe - Device Initialization Routine |
|
2230 * @pdev: PCI device information struct |
|
2231 * @ent: entry in igb_pci_tbl |
|
2232 * |
|
2233 * Returns 0 on success, negative on failure |
|
2234 * |
|
2235 * igb_probe initializes an adapter identified by a pci_dev structure. |
|
2236 * The OS initialization, configuring of the adapter private structure, |
|
2237 * and a hardware reset occur. |
|
2238 **/ |
|
2239 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
2240 { |
|
2241 struct net_device *netdev; |
|
2242 struct igb_adapter *adapter; |
|
2243 struct e1000_hw *hw; |
|
2244 u16 eeprom_data = 0; |
|
2245 s32 ret_val; |
|
2246 static int global_quad_port_a; /* global quad port a indication */ |
|
2247 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
|
2248 int err, pci_using_dac; |
|
2249 u8 part_str[E1000_PBANUM_LENGTH]; |
|
2250 |
|
2251 /* Catch broken hardware that put the wrong VF device ID in |
|
2252 * the PCIe SR-IOV capability. |
|
2253 */ |
|
2254 if (pdev->is_virtfn) { |
|
2255 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", |
|
2256 pci_name(pdev), pdev->vendor, pdev->device); |
|
2257 return -EINVAL; |
|
2258 } |
|
2259 |
|
2260 err = pci_enable_device_mem(pdev); |
|
2261 if (err) |
|
2262 return err; |
|
2263 |
|
2264 pci_using_dac = 0; |
|
2265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
|
2266 if (!err) { |
|
2267 pci_using_dac = 1; |
|
2268 } else { |
|
2269 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
|
2270 if (err) { |
|
2271 dev_err(&pdev->dev, |
|
2272 "No usable DMA configuration, aborting\n"); |
|
2273 goto err_dma; |
|
2274 } |
|
2275 } |
|
2276 |
|
2277 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
|
2278 IORESOURCE_MEM), |
|
2279 igb_driver_name); |
|
2280 if (err) |
|
2281 goto err_pci_reg; |
|
2282 |
|
2283 pci_enable_pcie_error_reporting(pdev); |
|
2284 |
|
2285 pci_set_master(pdev); |
|
2286 pci_save_state(pdev); |
|
2287 |
|
2288 err = -ENOMEM; |
|
2289 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
|
2290 IGB_MAX_TX_QUEUES); |
|
2291 if (!netdev) |
|
2292 goto err_alloc_etherdev; |
|
2293 |
|
2294 SET_NETDEV_DEV(netdev, &pdev->dev); |
|
2295 |
|
2296 pci_set_drvdata(pdev, netdev); |
|
2297 adapter = netdev_priv(netdev); |
|
2298 adapter->netdev = netdev; |
|
2299 adapter->pdev = pdev; |
|
2300 hw = &adapter->hw; |
|
2301 hw->back = adapter; |
|
2302 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
|
2303 |
|
2304 err = -EIO; |
|
2305 hw->hw_addr = pci_iomap(pdev, 0, 0); |
|
2306 if (!hw->hw_addr) |
|
2307 goto err_ioremap; |
|
2308 |
|
2309 netdev->netdev_ops = &igb_netdev_ops; |
|
2310 igb_set_ethtool_ops(netdev); |
|
2311 netdev->watchdog_timeo = 5 * HZ; |
|
2312 |
|
2313 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
|
2314 |
|
2315 netdev->mem_start = pci_resource_start(pdev, 0); |
|
2316 netdev->mem_end = pci_resource_end(pdev, 0); |
|
2317 |
|
2318 /* PCI config space info */ |
|
2319 hw->vendor_id = pdev->vendor; |
|
2320 hw->device_id = pdev->device; |
|
2321 hw->revision_id = pdev->revision; |
|
2322 hw->subsystem_vendor_id = pdev->subsystem_vendor; |
|
2323 hw->subsystem_device_id = pdev->subsystem_device; |
|
2324 |
|
2325 /* Copy the default MAC, PHY and NVM function pointers */ |
|
2326 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); |
|
2327 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); |
|
2328 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); |
|
2329 /* Initialize skew-specific constants */ |
|
2330 err = ei->get_invariants(hw); |
|
2331 if (err) |
|
2332 goto err_sw_init; |
|
2333 |
|
2334 /* setup the private structure */ |
|
2335 err = igb_sw_init(adapter); |
|
2336 if (err) |
|
2337 goto err_sw_init; |
|
2338 |
|
2339 igb_get_bus_info_pcie(hw); |
|
2340 |
|
2341 hw->phy.autoneg_wait_to_complete = false; |
|
2342 |
|
2343 /* Copper options */ |
|
2344 if (hw->phy.media_type == e1000_media_type_copper) { |
|
2345 hw->phy.mdix = AUTO_ALL_MODES; |
|
2346 hw->phy.disable_polarity_correction = false; |
|
2347 hw->phy.ms_type = e1000_ms_hw_default; |
|
2348 } |
|
2349 |
|
2350 if (igb_check_reset_block(hw)) |
|
2351 dev_info(&pdev->dev, |
|
2352 "PHY reset is blocked due to SOL/IDER session.\n"); |
|
2353 |
|
2354 /* features is initialized to 0 in allocation, it might have bits |
|
2355 * set by igb_sw_init so we should use an or instead of an |
|
2356 * assignment. |
|
2357 */ |
|
2358 netdev->features |= NETIF_F_SG | |
|
2359 NETIF_F_IP_CSUM | |
|
2360 NETIF_F_IPV6_CSUM | |
|
2361 NETIF_F_TSO | |
|
2362 NETIF_F_TSO6 | |
|
2363 NETIF_F_RXHASH | |
|
2364 NETIF_F_RXCSUM | |
|
2365 NETIF_F_HW_VLAN_CTAG_RX | |
|
2366 NETIF_F_HW_VLAN_CTAG_TX; |
|
2367 |
|
2368 /* copy netdev features into list of user selectable features */ |
|
2369 netdev->hw_features |= netdev->features; |
|
2370 netdev->hw_features |= NETIF_F_RXALL; |
|
2371 |
|
2372 /* set this bit last since it cannot be part of hw_features */ |
|
2373 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
|
2374 |
|
2375 netdev->vlan_features |= NETIF_F_TSO | |
|
2376 NETIF_F_TSO6 | |
|
2377 NETIF_F_IP_CSUM | |
|
2378 NETIF_F_IPV6_CSUM | |
|
2379 NETIF_F_SG; |
|
2380 |
|
2381 netdev->priv_flags |= IFF_SUPP_NOFCS; |
|
2382 |
|
2383 if (pci_using_dac) { |
|
2384 netdev->features |= NETIF_F_HIGHDMA; |
|
2385 netdev->vlan_features |= NETIF_F_HIGHDMA; |
|
2386 } |
|
2387 |
|
2388 if (hw->mac.type >= e1000_82576) { |
|
2389 netdev->hw_features |= NETIF_F_SCTP_CSUM; |
|
2390 netdev->features |= NETIF_F_SCTP_CSUM; |
|
2391 } |
|
2392 |
|
2393 netdev->priv_flags |= IFF_UNICAST_FLT; |
|
2394 |
|
2395 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
|
2396 |
|
2397 /* before reading the NVM, reset the controller to put the device in a |
|
2398 * known good starting state |
|
2399 */ |
|
2400 hw->mac.ops.reset_hw(hw); |
|
2401 |
|
2402 /* make sure the NVM is good , i211/i210 parts can have special NVM |
|
2403 * that doesn't contain a checksum |
|
2404 */ |
|
2405 switch (hw->mac.type) { |
|
2406 case e1000_i210: |
|
2407 case e1000_i211: |
|
2408 if (igb_get_flash_presence_i210(hw)) { |
|
2409 if (hw->nvm.ops.validate(hw) < 0) { |
|
2410 dev_err(&pdev->dev, |
|
2411 "The NVM Checksum Is Not Valid\n"); |
|
2412 err = -EIO; |
|
2413 goto err_eeprom; |
|
2414 } |
|
2415 } |
|
2416 break; |
|
2417 default: |
|
2418 if (hw->nvm.ops.validate(hw) < 0) { |
|
2419 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); |
|
2420 err = -EIO; |
|
2421 goto err_eeprom; |
|
2422 } |
|
2423 break; |
|
2424 } |
|
2425 |
|
2426 /* copy the MAC address out of the NVM */ |
|
2427 if (hw->mac.ops.read_mac_addr(hw)) |
|
2428 dev_err(&pdev->dev, "NVM Read Error\n"); |
|
2429 |
|
2430 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); |
|
2431 |
|
2432 if (!is_valid_ether_addr(netdev->dev_addr)) { |
|
2433 dev_err(&pdev->dev, "Invalid MAC Address\n"); |
|
2434 err = -EIO; |
|
2435 goto err_eeprom; |
|
2436 } |
|
2437 |
|
2438 /* get firmware version for ethtool -i */ |
|
2439 igb_set_fw_version(adapter); |
|
2440 |
|
2441 /* configure RXPBSIZE and TXPBSIZE */ |
|
2442 if (hw->mac.type == e1000_i210) { |
|
2443 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); |
|
2444 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); |
|
2445 } |
|
2446 |
|
2447 setup_timer(&adapter->watchdog_timer, igb_watchdog, |
|
2448 (unsigned long) adapter); |
|
2449 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
|
2450 (unsigned long) adapter); |
|
2451 |
|
2452 INIT_WORK(&adapter->reset_task, igb_reset_task); |
|
2453 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); |
|
2454 |
|
2455 /* Initialize link properties that are user-changeable */ |
|
2456 adapter->fc_autoneg = true; |
|
2457 hw->mac.autoneg = true; |
|
2458 hw->phy.autoneg_advertised = 0x2f; |
|
2459 |
|
2460 hw->fc.requested_mode = e1000_fc_default; |
|
2461 hw->fc.current_mode = e1000_fc_default; |
|
2462 |
|
2463 igb_validate_mdi_setting(hw); |
|
2464 |
|
2465 /* By default, support wake on port A */ |
|
2466 if (hw->bus.func == 0) |
|
2467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
|
2468 |
|
2469 /* Check the NVM for wake support on non-port A ports */ |
|
2470 if (hw->mac.type >= e1000_82580) |
|
2471 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
|
2472 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, |
|
2473 &eeprom_data); |
|
2474 else if (hw->bus.func == 1) |
|
2475 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); |
|
2476 |
|
2477 if (eeprom_data & IGB_EEPROM_APME) |
|
2478 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
|
2479 |
|
2480 /* now that we have the eeprom settings, apply the special cases where |
|
2481 * the eeprom may be wrong or the board simply won't support wake on |
|
2482 * lan on a particular port |
|
2483 */ |
|
2484 switch (pdev->device) { |
|
2485 case E1000_DEV_ID_82575GB_QUAD_COPPER: |
|
2486 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
|
2487 break; |
|
2488 case E1000_DEV_ID_82575EB_FIBER_SERDES: |
|
2489 case E1000_DEV_ID_82576_FIBER: |
|
2490 case E1000_DEV_ID_82576_SERDES: |
|
2491 /* Wake events only supported on port A for dual fiber |
|
2492 * regardless of eeprom setting |
|
2493 */ |
|
2494 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) |
|
2495 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
|
2496 break; |
|
2497 case E1000_DEV_ID_82576_QUAD_COPPER: |
|
2498 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
|
2499 /* if quad port adapter, disable WoL on all but port A */ |
|
2500 if (global_quad_port_a != 0) |
|
2501 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
|
2502 else |
|
2503 adapter->flags |= IGB_FLAG_QUAD_PORT_A; |
|
2504 /* Reset for multiple quad port adapters */ |
|
2505 if (++global_quad_port_a == 4) |
|
2506 global_quad_port_a = 0; |
|
2507 break; |
|
2508 default: |
|
2509 /* If the device can't wake, don't set software support */ |
|
2510 if (!device_can_wakeup(&adapter->pdev->dev)) |
|
2511 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
|
2512 } |
|
2513 |
|
2514 /* initialize the wol settings based on the eeprom settings */ |
|
2515 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) |
|
2516 adapter->wol |= E1000_WUFC_MAG; |
|
2517 |
|
2518 /* Some vendors want WoL disabled by default, but still supported */ |
|
2519 if ((hw->mac.type == e1000_i350) && |
|
2520 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
|
2521 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
|
2522 adapter->wol = 0; |
|
2523 } |
|
2524 |
|
2525 device_set_wakeup_enable(&adapter->pdev->dev, |
|
2526 adapter->flags & IGB_FLAG_WOL_SUPPORTED); |
|
2527 |
|
2528 /* reset the hardware with the new settings */ |
|
2529 igb_reset(adapter); |
|
2530 |
|
2531 /* Init the I2C interface */ |
|
2532 err = igb_init_i2c(adapter); |
|
2533 if (err) { |
|
2534 dev_err(&pdev->dev, "failed to init i2c interface\n"); |
|
2535 goto err_eeprom; |
|
2536 } |
|
2537 |
|
2538 /* let the f/w know that the h/w is now under the control of the |
|
2539 * driver. |
|
2540 */ |
|
2541 igb_get_hw_control(adapter); |
|
2542 |
|
2543 strcpy(netdev->name, "eth%d"); |
|
2544 err = register_netdev(netdev); |
|
2545 if (err) |
|
2546 goto err_register; |
|
2547 |
|
2548 /* carrier off reporting is important to ethtool even BEFORE open */ |
|
2549 netif_carrier_off(netdev); |
|
2550 |
|
2551 #ifdef CONFIG_IGB_DCA |
|
2552 if (dca_add_requester(&pdev->dev) == 0) { |
|
2553 adapter->flags |= IGB_FLAG_DCA_ENABLED; |
|
2554 dev_info(&pdev->dev, "DCA enabled\n"); |
|
2555 igb_setup_dca(adapter); |
|
2556 } |
|
2557 |
|
2558 #endif |
|
2559 #ifdef CONFIG_IGB_HWMON |
|
2560 /* Initialize the thermal sensor on i350 devices. */ |
|
2561 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { |
|
2562 u16 ets_word; |
|
2563 |
|
2564 /* Read the NVM to determine if this i350 device supports an |
|
2565 * external thermal sensor. |
|
2566 */ |
|
2567 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); |
|
2568 if (ets_word != 0x0000 && ets_word != 0xFFFF) |
|
2569 adapter->ets = true; |
|
2570 else |
|
2571 adapter->ets = false; |
|
2572 if (igb_sysfs_init(adapter)) |
|
2573 dev_err(&pdev->dev, |
|
2574 "failed to allocate sysfs resources\n"); |
|
2575 } else { |
|
2576 adapter->ets = false; |
|
2577 } |
|
2578 #endif |
|
2579 /* Check if Media Autosense is enabled */ |
|
2580 adapter->ei = *ei; |
|
2581 if (hw->dev_spec._82575.mas_capable) |
|
2582 igb_init_mas(adapter); |
|
2583 |
|
2584 /* do hw tstamp init after resetting */ |
|
2585 igb_ptp_init(adapter); |
|
2586 |
|
2587 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
|
2588 /* print bus type/speed/width info, not applicable to i354 */ |
|
2589 if (hw->mac.type != e1000_i354) { |
|
2590 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
|
2591 netdev->name, |
|
2592 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
|
2593 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : |
|
2594 "unknown"), |
|
2595 ((hw->bus.width == e1000_bus_width_pcie_x4) ? |
|
2596 "Width x4" : |
|
2597 (hw->bus.width == e1000_bus_width_pcie_x2) ? |
|
2598 "Width x2" : |
|
2599 (hw->bus.width == e1000_bus_width_pcie_x1) ? |
|
2600 "Width x1" : "unknown"), netdev->dev_addr); |
|
2601 } |
|
2602 |
|
2603 if ((hw->mac.type >= e1000_i210 || |
|
2604 igb_get_flash_presence_i210(hw))) { |
|
2605 ret_val = igb_read_part_string(hw, part_str, |
|
2606 E1000_PBANUM_LENGTH); |
|
2607 } else { |
|
2608 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; |
|
2609 } |
|
2610 |
|
2611 if (ret_val) |
|
2612 strcpy(part_str, "Unknown"); |
|
2613 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); |
|
2614 dev_info(&pdev->dev, |
|
2615 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", |
|
2616 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : |
|
2617 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
|
2618 adapter->num_rx_queues, adapter->num_tx_queues); |
|
2619 if (hw->phy.media_type == e1000_media_type_copper) { |
|
2620 switch (hw->mac.type) { |
|
2621 case e1000_i350: |
|
2622 case e1000_i210: |
|
2623 case e1000_i211: |
|
2624 /* Enable EEE for internal copper PHY devices */ |
|
2625 err = igb_set_eee_i350(hw, true, true); |
|
2626 if ((!err) && |
|
2627 (!hw->dev_spec._82575.eee_disable)) { |
|
2628 adapter->eee_advert = |
|
2629 MDIO_EEE_100TX | MDIO_EEE_1000T; |
|
2630 adapter->flags |= IGB_FLAG_EEE; |
|
2631 } |
|
2632 break; |
|
2633 case e1000_i354: |
|
2634 if ((rd32(E1000_CTRL_EXT) & |
|
2635 E1000_CTRL_EXT_LINK_MODE_SGMII)) { |
|
2636 err = igb_set_eee_i354(hw, true, true); |
|
2637 if ((!err) && |
|
2638 (!hw->dev_spec._82575.eee_disable)) { |
|
2639 adapter->eee_advert = |
|
2640 MDIO_EEE_100TX | MDIO_EEE_1000T; |
|
2641 adapter->flags |= IGB_FLAG_EEE; |
|
2642 } |
|
2643 } |
|
2644 break; |
|
2645 default: |
|
2646 break; |
|
2647 } |
|
2648 } |
|
2649 pm_runtime_put_noidle(&pdev->dev); |
|
2650 return 0; |
|
2651 |
|
2652 err_register: |
|
2653 igb_release_hw_control(adapter); |
|
2654 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); |
|
2655 err_eeprom: |
|
2656 if (!igb_check_reset_block(hw)) |
|
2657 igb_reset_phy(hw); |
|
2658 |
|
2659 if (hw->flash_address) |
|
2660 iounmap(hw->flash_address); |
|
2661 err_sw_init: |
|
2662 igb_clear_interrupt_scheme(adapter); |
|
2663 pci_iounmap(pdev, hw->hw_addr); |
|
2664 err_ioremap: |
|
2665 free_netdev(netdev); |
|
2666 err_alloc_etherdev: |
|
2667 pci_release_selected_regions(pdev, |
|
2668 pci_select_bars(pdev, IORESOURCE_MEM)); |
|
2669 err_pci_reg: |
|
2670 err_dma: |
|
2671 pci_disable_device(pdev); |
|
2672 return err; |
|
2673 } |
|
2674 |
|
2675 #ifdef CONFIG_PCI_IOV |
|
2676 static int igb_disable_sriov(struct pci_dev *pdev) |
|
2677 { |
|
2678 struct net_device *netdev = pci_get_drvdata(pdev); |
|
2679 struct igb_adapter *adapter = netdev_priv(netdev); |
|
2680 struct e1000_hw *hw = &adapter->hw; |
|
2681 |
|
2682 /* reclaim resources allocated to VFs */ |
|
2683 if (adapter->vf_data) { |
|
2684 /* disable iov and allow time for transactions to clear */ |
|
2685 if (pci_vfs_assigned(pdev)) { |
|
2686 dev_warn(&pdev->dev, |
|
2687 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); |
|
2688 return -EPERM; |
|
2689 } else { |
|
2690 pci_disable_sriov(pdev); |
|
2691 msleep(500); |
|
2692 } |
|
2693 |
|
2694 kfree(adapter->vf_data); |
|
2695 adapter->vf_data = NULL; |
|
2696 adapter->vfs_allocated_count = 0; |
|
2697 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); |
|
2698 wrfl(); |
|
2699 msleep(100); |
|
2700 dev_info(&pdev->dev, "IOV Disabled\n"); |
|
2701 |
|
2702 /* Re-enable DMA Coalescing flag since IOV is turned off */ |
|
2703 adapter->flags |= IGB_FLAG_DMAC; |
|
2704 } |
|
2705 |
|
2706 return 0; |
|
2707 } |
|
2708 |
|
2709 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) |
|
2710 { |
|
2711 struct net_device *netdev = pci_get_drvdata(pdev); |
|
2712 struct igb_adapter *adapter = netdev_priv(netdev); |
|
2713 int old_vfs = pci_num_vf(pdev); |
|
2714 int err = 0; |
|
2715 int i; |
|
2716 |
|
2717 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { |
|
2718 err = -EPERM; |
|
2719 goto out; |
|
2720 } |
|
2721 if (!num_vfs) |
|
2722 goto out; |
|
2723 |
|
2724 if (old_vfs) { |
|
2725 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", |
|
2726 old_vfs, max_vfs); |
|
2727 adapter->vfs_allocated_count = old_vfs; |
|
2728 } else |
|
2729 adapter->vfs_allocated_count = num_vfs; |
|
2730 |
|
2731 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, |
|
2732 sizeof(struct vf_data_storage), GFP_KERNEL); |
|
2733 |
|
2734 /* if allocation failed then we do not support SR-IOV */ |
|
2735 if (!adapter->vf_data) { |
|
2736 adapter->vfs_allocated_count = 0; |
|
2737 dev_err(&pdev->dev, |
|
2738 "Unable to allocate memory for VF Data Storage\n"); |
|
2739 err = -ENOMEM; |
|
2740 goto out; |
|
2741 } |
|
2742 |
|
2743 /* only call pci_enable_sriov() if no VFs are allocated already */ |
|
2744 if (!old_vfs) { |
|
2745 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); |
|
2746 if (err) |
|
2747 goto err_out; |
|
2748 } |
|
2749 dev_info(&pdev->dev, "%d VFs allocated\n", |
|
2750 adapter->vfs_allocated_count); |
|
2751 for (i = 0; i < adapter->vfs_allocated_count; i++) |
|
2752 igb_vf_configure(adapter, i); |
|
2753 |
|
2754 /* DMA Coalescing is not supported in IOV mode. */ |
|
2755 adapter->flags &= ~IGB_FLAG_DMAC; |
|
2756 goto out; |
|
2757 |
|
2758 err_out: |
|
2759 kfree(adapter->vf_data); |
|
2760 adapter->vf_data = NULL; |
|
2761 adapter->vfs_allocated_count = 0; |
|
2762 out: |
|
2763 return err; |
|
2764 } |
|
2765 |
|
2766 #endif |
|
2767 /** |
|
2768 * igb_remove_i2c - Cleanup I2C interface |
|
2769 * @adapter: pointer to adapter structure |
|
2770 **/ |
|
2771 static void igb_remove_i2c(struct igb_adapter *adapter) |
|
2772 { |
|
2773 /* free the adapter bus structure */ |
|
2774 i2c_del_adapter(&adapter->i2c_adap); |
|
2775 } |
|
2776 |
|
2777 /** |
|
2778 * igb_remove - Device Removal Routine |
|
2779 * @pdev: PCI device information struct |
|
2780 * |
|
2781 * igb_remove is called by the PCI subsystem to alert the driver |
|
2782 * that it should release a PCI device. The could be caused by a |
|
2783 * Hot-Plug event, or because the driver is going to be removed from |
|
2784 * memory. |
|
2785 **/ |
|
2786 static void igb_remove(struct pci_dev *pdev) |
|
2787 { |
|
2788 struct net_device *netdev = pci_get_drvdata(pdev); |
|
2789 struct igb_adapter *adapter = netdev_priv(netdev); |
|
2790 struct e1000_hw *hw = &adapter->hw; |
|
2791 |
|
2792 pm_runtime_get_noresume(&pdev->dev); |
|
2793 #ifdef CONFIG_IGB_HWMON |
|
2794 igb_sysfs_exit(adapter); |
|
2795 #endif |
|
2796 igb_remove_i2c(adapter); |
|
2797 igb_ptp_stop(adapter); |
|
2798 /* The watchdog timer may be rescheduled, so explicitly |
|
2799 * disable watchdog from being rescheduled. |
|
2800 */ |
|
2801 set_bit(__IGB_DOWN, &adapter->state); |
|
2802 del_timer_sync(&adapter->watchdog_timer); |
|
2803 del_timer_sync(&adapter->phy_info_timer); |
|
2804 |
|
2805 cancel_work_sync(&adapter->reset_task); |
|
2806 cancel_work_sync(&adapter->watchdog_task); |
|
2807 |
|
2808 #ifdef CONFIG_IGB_DCA |
|
2809 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
|
2810 dev_info(&pdev->dev, "DCA disabled\n"); |
|
2811 dca_remove_requester(&pdev->dev); |
|
2812 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
|
2813 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
|
2814 } |
|
2815 #endif |
|
2816 |
|
2817 /* Release control of h/w to f/w. If f/w is AMT enabled, this |
|
2818 * would have already happened in close and is redundant. |
|
2819 */ |
|
2820 igb_release_hw_control(adapter); |
|
2821 |
|
2822 unregister_netdev(netdev); |
|
2823 |
|
2824 igb_clear_interrupt_scheme(adapter); |
|
2825 |
|
2826 #ifdef CONFIG_PCI_IOV |
|
2827 igb_disable_sriov(pdev); |
|
2828 #endif |
|
2829 |
|
2830 pci_iounmap(pdev, hw->hw_addr); |
|
2831 if (hw->flash_address) |
|
2832 iounmap(hw->flash_address); |
|
2833 pci_release_selected_regions(pdev, |
|
2834 pci_select_bars(pdev, IORESOURCE_MEM)); |
|
2835 |
|
2836 kfree(adapter->shadow_vfta); |
|
2837 free_netdev(netdev); |
|
2838 |
|
2839 pci_disable_pcie_error_reporting(pdev); |
|
2840 |
|
2841 pci_disable_device(pdev); |
|
2842 } |
|
2843 |
|
2844 /** |
|
2845 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space |
|
2846 * @adapter: board private structure to initialize |
|
2847 * |
|
2848 * This function initializes the vf specific data storage and then attempts to |
|
2849 * allocate the VFs. The reason for ordering it this way is because it is much |
|
2850 * mor expensive time wise to disable SR-IOV than it is to allocate and free |
|
2851 * the memory for the VFs. |
|
2852 **/ |
|
2853 static void igb_probe_vfs(struct igb_adapter *adapter) |
|
2854 { |
|
2855 #ifdef CONFIG_PCI_IOV |
|
2856 struct pci_dev *pdev = adapter->pdev; |
|
2857 struct e1000_hw *hw = &adapter->hw; |
|
2858 |
|
2859 /* Virtualization features not supported on i210 family. */ |
|
2860 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) |
|
2861 return; |
|
2862 |
|
2863 pci_sriov_set_totalvfs(pdev, 7); |
|
2864 igb_pci_enable_sriov(pdev, max_vfs); |
|
2865 |
|
2866 #endif /* CONFIG_PCI_IOV */ |
|
2867 } |
|
2868 |
|
2869 static void igb_init_queue_configuration(struct igb_adapter *adapter) |
|
2870 { |
|
2871 struct e1000_hw *hw = &adapter->hw; |
|
2872 u32 max_rss_queues; |
|
2873 |
|
2874 /* Determine the maximum number of RSS queues supported. */ |
|
2875 switch (hw->mac.type) { |
|
2876 case e1000_i211: |
|
2877 max_rss_queues = IGB_MAX_RX_QUEUES_I211; |
|
2878 break; |
|
2879 case e1000_82575: |
|
2880 case e1000_i210: |
|
2881 max_rss_queues = IGB_MAX_RX_QUEUES_82575; |
|
2882 break; |
|
2883 case e1000_i350: |
|
2884 /* I350 cannot do RSS and SR-IOV at the same time */ |
|
2885 if (!!adapter->vfs_allocated_count) { |
|
2886 max_rss_queues = 1; |
|
2887 break; |
|
2888 } |
|
2889 /* fall through */ |
|
2890 case e1000_82576: |
|
2891 if (!!adapter->vfs_allocated_count) { |
|
2892 max_rss_queues = 2; |
|
2893 break; |
|
2894 } |
|
2895 /* fall through */ |
|
2896 case e1000_82580: |
|
2897 case e1000_i354: |
|
2898 default: |
|
2899 max_rss_queues = IGB_MAX_RX_QUEUES; |
|
2900 break; |
|
2901 } |
|
2902 |
|
2903 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); |
|
2904 |
|
2905 /* Determine if we need to pair queues. */ |
|
2906 switch (hw->mac.type) { |
|
2907 case e1000_82575: |
|
2908 case e1000_i211: |
|
2909 /* Device supports enough interrupts without queue pairing. */ |
|
2910 break; |
|
2911 case e1000_82576: |
|
2912 /* If VFs are going to be allocated with RSS queues then we |
|
2913 * should pair the queues in order to conserve interrupts due |
|
2914 * to limited supply. |
|
2915 */ |
|
2916 if ((adapter->rss_queues > 1) && |
|
2917 (adapter->vfs_allocated_count > 6)) |
|
2918 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
|
2919 /* fall through */ |
|
2920 case e1000_82580: |
|
2921 case e1000_i350: |
|
2922 case e1000_i354: |
|
2923 case e1000_i210: |
|
2924 default: |
|
2925 /* If rss_queues > half of max_rss_queues, pair the queues in |
|
2926 * order to conserve interrupts due to limited supply. |
|
2927 */ |
|
2928 if (adapter->rss_queues > (max_rss_queues / 2)) |
|
2929 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
|
2930 break; |
|
2931 } |
|
2932 } |
|
2933 |
|
2934 /** |
|
2935 * igb_sw_init - Initialize general software structures (struct igb_adapter) |
|
2936 * @adapter: board private structure to initialize |
|
2937 * |
|
2938 * igb_sw_init initializes the Adapter private data structure. |
|
2939 * Fields are initialized based on PCI device information and |
|
2940 * OS network device settings (MTU size). |
|
2941 **/ |
|
2942 static int igb_sw_init(struct igb_adapter *adapter) |
|
2943 { |
|
2944 struct e1000_hw *hw = &adapter->hw; |
|
2945 struct net_device *netdev = adapter->netdev; |
|
2946 struct pci_dev *pdev = adapter->pdev; |
|
2947 |
|
2948 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); |
|
2949 |
|
2950 /* set default ring sizes */ |
|
2951 adapter->tx_ring_count = IGB_DEFAULT_TXD; |
|
2952 adapter->rx_ring_count = IGB_DEFAULT_RXD; |
|
2953 |
|
2954 /* set default ITR values */ |
|
2955 adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
|
2956 adapter->tx_itr_setting = IGB_DEFAULT_ITR; |
|
2957 |
|
2958 /* set default work limits */ |
|
2959 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; |
|
2960 |
|
2961 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + |
|
2962 VLAN_HLEN; |
|
2963 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
|
2964 |
|
2965 spin_lock_init(&adapter->stats64_lock); |
|
2966 #ifdef CONFIG_PCI_IOV |
|
2967 switch (hw->mac.type) { |
|
2968 case e1000_82576: |
|
2969 case e1000_i350: |
|
2970 if (max_vfs > 7) { |
|
2971 dev_warn(&pdev->dev, |
|
2972 "Maximum of 7 VFs per PF, using max\n"); |
|
2973 max_vfs = adapter->vfs_allocated_count = 7; |
|
2974 } else |
|
2975 adapter->vfs_allocated_count = max_vfs; |
|
2976 if (adapter->vfs_allocated_count) |
|
2977 dev_warn(&pdev->dev, |
|
2978 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); |
|
2979 break; |
|
2980 default: |
|
2981 break; |
|
2982 } |
|
2983 #endif /* CONFIG_PCI_IOV */ |
|
2984 |
|
2985 igb_init_queue_configuration(adapter); |
|
2986 |
|
2987 /* Setup and initialize a copy of the hw vlan table array */ |
|
2988 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), |
|
2989 GFP_ATOMIC); |
|
2990 |
|
2991 /* This call may decrease the number of queues */ |
|
2992 if (igb_init_interrupt_scheme(adapter, true)) { |
|
2993 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
|
2994 return -ENOMEM; |
|
2995 } |
|
2996 |
|
2997 igb_probe_vfs(adapter); |
|
2998 |
|
2999 /* Explicitly disable IRQ since the NIC can be in any state. */ |
|
3000 igb_irq_disable(adapter); |
|
3001 |
|
3002 if (hw->mac.type >= e1000_i350) |
|
3003 adapter->flags &= ~IGB_FLAG_DMAC; |
|
3004 |
|
3005 set_bit(__IGB_DOWN, &adapter->state); |
|
3006 return 0; |
|
3007 } |
|
3008 |
|
3009 /** |
|
3010 * igb_open - Called when a network interface is made active |
|
3011 * @netdev: network interface device structure |
|
3012 * |
|
3013 * Returns 0 on success, negative value on failure |
|
3014 * |
|
3015 * The open entry point is called when a network interface is made |
|
3016 * active by the system (IFF_UP). At this point all resources needed |
|
3017 * for transmit and receive operations are allocated, the interrupt |
|
3018 * handler is registered with the OS, the watchdog timer is started, |
|
3019 * and the stack is notified that the interface is ready. |
|
3020 **/ |
|
3021 static int __igb_open(struct net_device *netdev, bool resuming) |
|
3022 { |
|
3023 struct igb_adapter *adapter = netdev_priv(netdev); |
|
3024 struct e1000_hw *hw = &adapter->hw; |
|
3025 struct pci_dev *pdev = adapter->pdev; |
|
3026 int err; |
|
3027 int i; |
|
3028 |
|
3029 /* disallow open during test */ |
|
3030 if (test_bit(__IGB_TESTING, &adapter->state)) { |
|
3031 WARN_ON(resuming); |
|
3032 return -EBUSY; |
|
3033 } |
|
3034 |
|
3035 if (!resuming) |
|
3036 pm_runtime_get_sync(&pdev->dev); |
|
3037 |
|
3038 netif_carrier_off(netdev); |
|
3039 |
|
3040 /* allocate transmit descriptors */ |
|
3041 err = igb_setup_all_tx_resources(adapter); |
|
3042 if (err) |
|
3043 goto err_setup_tx; |
|
3044 |
|
3045 /* allocate receive descriptors */ |
|
3046 err = igb_setup_all_rx_resources(adapter); |
|
3047 if (err) |
|
3048 goto err_setup_rx; |
|
3049 |
|
3050 igb_power_up_link(adapter); |
|
3051 |
|
3052 /* before we allocate an interrupt, we must be ready to handle it. |
|
3053 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt |
|
3054 * as soon as we call pci_request_irq, so we have to setup our |
|
3055 * clean_rx handler before we do so. |
|
3056 */ |
|
3057 igb_configure(adapter); |
|
3058 |
|
3059 err = igb_request_irq(adapter); |
|
3060 if (err) |
|
3061 goto err_req_irq; |
|
3062 |
|
3063 /* Notify the stack of the actual queue counts. */ |
|
3064 err = netif_set_real_num_tx_queues(adapter->netdev, |
|
3065 adapter->num_tx_queues); |
|
3066 if (err) |
|
3067 goto err_set_queues; |
|
3068 |
|
3069 err = netif_set_real_num_rx_queues(adapter->netdev, |
|
3070 adapter->num_rx_queues); |
|
3071 if (err) |
|
3072 goto err_set_queues; |
|
3073 |
|
3074 /* From here on the code is the same as igb_up() */ |
|
3075 clear_bit(__IGB_DOWN, &adapter->state); |
|
3076 |
|
3077 for (i = 0; i < adapter->num_q_vectors; i++) |
|
3078 napi_enable(&(adapter->q_vector[i]->napi)); |
|
3079 |
|
3080 /* Clear any pending interrupts. */ |
|
3081 rd32(E1000_ICR); |
|
3082 |
|
3083 igb_irq_enable(adapter); |
|
3084 |
|
3085 /* notify VFs that reset has been completed */ |
|
3086 if (adapter->vfs_allocated_count) { |
|
3087 u32 reg_data = rd32(E1000_CTRL_EXT); |
|
3088 |
|
3089 reg_data |= E1000_CTRL_EXT_PFRSTD; |
|
3090 wr32(E1000_CTRL_EXT, reg_data); |
|
3091 } |
|
3092 |
|
3093 netif_tx_start_all_queues(netdev); |
|
3094 |
|
3095 if (!resuming) |
|
3096 pm_runtime_put(&pdev->dev); |
|
3097 |
|
3098 /* start the watchdog. */ |
|
3099 hw->mac.get_link_status = 1; |
|
3100 schedule_work(&adapter->watchdog_task); |
|
3101 |
|
3102 return 0; |
|
3103 |
|
3104 err_set_queues: |
|
3105 igb_free_irq(adapter); |
|
3106 err_req_irq: |
|
3107 igb_release_hw_control(adapter); |
|
3108 igb_power_down_link(adapter); |
|
3109 igb_free_all_rx_resources(adapter); |
|
3110 err_setup_rx: |
|
3111 igb_free_all_tx_resources(adapter); |
|
3112 err_setup_tx: |
|
3113 igb_reset(adapter); |
|
3114 if (!resuming) |
|
3115 pm_runtime_put(&pdev->dev); |
|
3116 |
|
3117 return err; |
|
3118 } |
|
3119 |
|
3120 static int igb_open(struct net_device *netdev) |
|
3121 { |
|
3122 return __igb_open(netdev, false); |
|
3123 } |
|
3124 |
|
3125 /** |
|
3126 * igb_close - Disables a network interface |
|
3127 * @netdev: network interface device structure |
|
3128 * |
|
3129 * Returns 0, this is not allowed to fail |
|
3130 * |
|
3131 * The close entry point is called when an interface is de-activated |
|
3132 * by the OS. The hardware is still under the driver's control, but |
|
3133 * needs to be disabled. A global MAC reset is issued to stop the |
|
3134 * hardware, and all transmit and receive resources are freed. |
|
3135 **/ |
|
3136 static int __igb_close(struct net_device *netdev, bool suspending) |
|
3137 { |
|
3138 struct igb_adapter *adapter = netdev_priv(netdev); |
|
3139 struct pci_dev *pdev = adapter->pdev; |
|
3140 |
|
3141 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); |
|
3142 |
|
3143 if (!suspending) |
|
3144 pm_runtime_get_sync(&pdev->dev); |
|
3145 |
|
3146 igb_down(adapter); |
|
3147 igb_free_irq(adapter); |
|
3148 |
|
3149 igb_free_all_tx_resources(adapter); |
|
3150 igb_free_all_rx_resources(adapter); |
|
3151 |
|
3152 if (!suspending) |
|
3153 pm_runtime_put_sync(&pdev->dev); |
|
3154 return 0; |
|
3155 } |
|
3156 |
|
3157 static int igb_close(struct net_device *netdev) |
|
3158 { |
|
3159 return __igb_close(netdev, false); |
|
3160 } |
|
3161 |
|
3162 /** |
|
3163 * igb_setup_tx_resources - allocate Tx resources (Descriptors) |
|
3164 * @tx_ring: tx descriptor ring (for a specific queue) to setup |
|
3165 * |
|
3166 * Return 0 on success, negative on failure |
|
3167 **/ |
|
3168 int igb_setup_tx_resources(struct igb_ring *tx_ring) |
|
3169 { |
|
3170 struct device *dev = tx_ring->dev; |
|
3171 int size; |
|
3172 |
|
3173 size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
|
3174 |
|
3175 tx_ring->tx_buffer_info = vzalloc(size); |
|
3176 if (!tx_ring->tx_buffer_info) |
|
3177 goto err; |
|
3178 |
|
3179 /* round up to nearest 4K */ |
|
3180 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
|
3181 tx_ring->size = ALIGN(tx_ring->size, 4096); |
|
3182 |
|
3183 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
|
3184 &tx_ring->dma, GFP_KERNEL); |
|
3185 if (!tx_ring->desc) |
|
3186 goto err; |
|
3187 |
|
3188 tx_ring->next_to_use = 0; |
|
3189 tx_ring->next_to_clean = 0; |
|
3190 |
|
3191 return 0; |
|
3192 |
|
3193 err: |
|
3194 vfree(tx_ring->tx_buffer_info); |
|
3195 tx_ring->tx_buffer_info = NULL; |
|
3196 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
|
3197 return -ENOMEM; |
|
3198 } |
|
3199 |
|
3200 /** |
|
3201 * igb_setup_all_tx_resources - wrapper to allocate Tx resources |
|
3202 * (Descriptors) for all queues |
|
3203 * @adapter: board private structure |
|
3204 * |
|
3205 * Return 0 on success, negative on failure |
|
3206 **/ |
|
3207 static int igb_setup_all_tx_resources(struct igb_adapter *adapter) |
|
3208 { |
|
3209 struct pci_dev *pdev = adapter->pdev; |
|
3210 int i, err = 0; |
|
3211 |
|
3212 for (i = 0; i < adapter->num_tx_queues; i++) { |
|
3213 err = igb_setup_tx_resources(adapter->tx_ring[i]); |
|
3214 if (err) { |
|
3215 dev_err(&pdev->dev, |
|
3216 "Allocation for Tx Queue %u failed\n", i); |
|
3217 for (i--; i >= 0; i--) |
|
3218 igb_free_tx_resources(adapter->tx_ring[i]); |
|
3219 break; |
|
3220 } |
|
3221 } |
|
3222 |
|
3223 return err; |
|
3224 } |
|
3225 |
|
3226 /** |
|
3227 * igb_setup_tctl - configure the transmit control registers |
|
3228 * @adapter: Board private structure |
|
3229 **/ |
|
3230 void igb_setup_tctl(struct igb_adapter *adapter) |
|
3231 { |
|
3232 struct e1000_hw *hw = &adapter->hw; |
|
3233 u32 tctl; |
|
3234 |
|
3235 /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
|
3236 wr32(E1000_TXDCTL(0), 0); |
|
3237 |
|
3238 /* Program the Transmit Control Register */ |
|
3239 tctl = rd32(E1000_TCTL); |
|
3240 tctl &= ~E1000_TCTL_CT; |
|
3241 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | |
|
3242 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); |
|
3243 |
|
3244 igb_config_collision_dist(hw); |
|
3245 |
|
3246 /* Enable transmits */ |
|
3247 tctl |= E1000_TCTL_EN; |
|
3248 |
|
3249 wr32(E1000_TCTL, tctl); |
|
3250 } |
|
3251 |
|
3252 /** |
|
3253 * igb_configure_tx_ring - Configure transmit ring after Reset |
|
3254 * @adapter: board private structure |
|
3255 * @ring: tx ring to configure |
|
3256 * |
|
3257 * Configure a transmit ring after a reset. |
|
3258 **/ |
|
3259 void igb_configure_tx_ring(struct igb_adapter *adapter, |
|
3260 struct igb_ring *ring) |
|
3261 { |
|
3262 struct e1000_hw *hw = &adapter->hw; |
|
3263 u32 txdctl = 0; |
|
3264 u64 tdba = ring->dma; |
|
3265 int reg_idx = ring->reg_idx; |
|
3266 |
|
3267 /* disable the queue */ |
|
3268 wr32(E1000_TXDCTL(reg_idx), 0); |
|
3269 wrfl(); |
|
3270 mdelay(10); |
|
3271 |
|
3272 wr32(E1000_TDLEN(reg_idx), |
|
3273 ring->count * sizeof(union e1000_adv_tx_desc)); |
|
3274 wr32(E1000_TDBAL(reg_idx), |
|
3275 tdba & 0x00000000ffffffffULL); |
|
3276 wr32(E1000_TDBAH(reg_idx), tdba >> 32); |
|
3277 |
|
3278 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
|
3279 wr32(E1000_TDH(reg_idx), 0); |
|
3280 writel(0, ring->tail); |
|
3281 |
|
3282 txdctl |= IGB_TX_PTHRESH; |
|
3283 txdctl |= IGB_TX_HTHRESH << 8; |
|
3284 txdctl |= IGB_TX_WTHRESH << 16; |
|
3285 |
|
3286 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; |
|
3287 wr32(E1000_TXDCTL(reg_idx), txdctl); |
|
3288 } |
|
3289 |
|
3290 /** |
|
3291 * igb_configure_tx - Configure transmit Unit after Reset |
|
3292 * @adapter: board private structure |
|
3293 * |
|
3294 * Configure the Tx unit of the MAC after a reset. |
|
3295 **/ |
|
3296 static void igb_configure_tx(struct igb_adapter *adapter) |
|
3297 { |
|
3298 int i; |
|
3299 |
|
3300 for (i = 0; i < adapter->num_tx_queues; i++) |
|
3301 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
|
3302 } |
|
3303 |
|
3304 /** |
|
3305 * igb_setup_rx_resources - allocate Rx resources (Descriptors) |
|
3306 * @rx_ring: Rx descriptor ring (for a specific queue) to setup |
|
3307 * |
|
3308 * Returns 0 on success, negative on failure |
|
3309 **/ |
|
3310 int igb_setup_rx_resources(struct igb_ring *rx_ring) |
|
3311 { |
|
3312 struct device *dev = rx_ring->dev; |
|
3313 int size; |
|
3314 |
|
3315 size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
|
3316 |
|
3317 rx_ring->rx_buffer_info = vzalloc(size); |
|
3318 if (!rx_ring->rx_buffer_info) |
|
3319 goto err; |
|
3320 |
|
3321 /* Round up to nearest 4K */ |
|
3322 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); |
|
3323 rx_ring->size = ALIGN(rx_ring->size, 4096); |
|
3324 |
|
3325 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
|
3326 &rx_ring->dma, GFP_KERNEL); |
|
3327 if (!rx_ring->desc) |
|
3328 goto err; |
|
3329 |
|
3330 rx_ring->next_to_alloc = 0; |
|
3331 rx_ring->next_to_clean = 0; |
|
3332 rx_ring->next_to_use = 0; |
|
3333 |
|
3334 return 0; |
|
3335 |
|
3336 err: |
|
3337 vfree(rx_ring->rx_buffer_info); |
|
3338 rx_ring->rx_buffer_info = NULL; |
|
3339 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); |
|
3340 return -ENOMEM; |
|
3341 } |
|
3342 |
|
3343 /** |
|
3344 * igb_setup_all_rx_resources - wrapper to allocate Rx resources |
|
3345 * (Descriptors) for all queues |
|
3346 * @adapter: board private structure |
|
3347 * |
|
3348 * Return 0 on success, negative on failure |
|
3349 **/ |
|
3350 static int igb_setup_all_rx_resources(struct igb_adapter *adapter) |
|
3351 { |
|
3352 struct pci_dev *pdev = adapter->pdev; |
|
3353 int i, err = 0; |
|
3354 |
|
3355 for (i = 0; i < adapter->num_rx_queues; i++) { |
|
3356 err = igb_setup_rx_resources(adapter->rx_ring[i]); |
|
3357 if (err) { |
|
3358 dev_err(&pdev->dev, |
|
3359 "Allocation for Rx Queue %u failed\n", i); |
|
3360 for (i--; i >= 0; i--) |
|
3361 igb_free_rx_resources(adapter->rx_ring[i]); |
|
3362 break; |
|
3363 } |
|
3364 } |
|
3365 |
|
3366 return err; |
|
3367 } |
|
3368 |
|
3369 /** |
|
3370 * igb_setup_mrqc - configure the multiple receive queue control registers |
|
3371 * @adapter: Board private structure |
|
3372 **/ |
|
3373 static void igb_setup_mrqc(struct igb_adapter *adapter) |
|
3374 { |
|
3375 struct e1000_hw *hw = &adapter->hw; |
|
3376 u32 mrqc, rxcsum; |
|
3377 u32 j, num_rx_queues; |
|
3378 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, |
|
3379 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, |
|
3380 0xA32DCB77, 0x0CF23080, 0x3BB7426A, |
|
3381 0xFA01ACBE }; |
|
3382 |
|
3383 /* Fill out hash function seeds */ |
|
3384 for (j = 0; j < 10; j++) |
|
3385 wr32(E1000_RSSRK(j), rsskey[j]); |
|
3386 |
|
3387 num_rx_queues = adapter->rss_queues; |
|
3388 |
|
3389 switch (hw->mac.type) { |
|
3390 case e1000_82576: |
|
3391 /* 82576 supports 2 RSS queues for SR-IOV */ |
|
3392 if (adapter->vfs_allocated_count) |
|
3393 num_rx_queues = 2; |
|
3394 break; |
|
3395 default: |
|
3396 break; |
|
3397 } |
|
3398 |
|
3399 if (adapter->rss_indir_tbl_init != num_rx_queues) { |
|
3400 for (j = 0; j < IGB_RETA_SIZE; j++) |
|
3401 adapter->rss_indir_tbl[j] = |
|
3402 (j * num_rx_queues) / IGB_RETA_SIZE; |
|
3403 adapter->rss_indir_tbl_init = num_rx_queues; |
|
3404 } |
|
3405 igb_write_rss_indir_tbl(adapter); |
|
3406 |
|
3407 /* Disable raw packet checksumming so that RSS hash is placed in |
|
3408 * descriptor on writeback. No need to enable TCP/UDP/IP checksum |
|
3409 * offloads as they are enabled by default |
|
3410 */ |
|
3411 rxcsum = rd32(E1000_RXCSUM); |
|
3412 rxcsum |= E1000_RXCSUM_PCSD; |
|
3413 |
|
3414 if (adapter->hw.mac.type >= e1000_82576) |
|
3415 /* Enable Receive Checksum Offload for SCTP */ |
|
3416 rxcsum |= E1000_RXCSUM_CRCOFL; |
|
3417 |
|
3418 /* Don't need to set TUOFL or IPOFL, they default to 1 */ |
|
3419 wr32(E1000_RXCSUM, rxcsum); |
|
3420 |
|
3421 /* Generate RSS hash based on packet types, TCP/UDP |
|
3422 * port numbers and/or IPv4/v6 src and dst addresses |
|
3423 */ |
|
3424 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | |
|
3425 E1000_MRQC_RSS_FIELD_IPV4_TCP | |
|
3426 E1000_MRQC_RSS_FIELD_IPV6 | |
|
3427 E1000_MRQC_RSS_FIELD_IPV6_TCP | |
|
3428 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; |
|
3429 |
|
3430 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) |
|
3431 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; |
|
3432 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) |
|
3433 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; |
|
3434 |
|
3435 /* If VMDq is enabled then we set the appropriate mode for that, else |
|
3436 * we default to RSS so that an RSS hash is calculated per packet even |
|
3437 * if we are only using one queue |
|
3438 */ |
|
3439 if (adapter->vfs_allocated_count) { |
|
3440 if (hw->mac.type > e1000_82575) { |
|
3441 /* Set the default pool for the PF's first queue */ |
|
3442 u32 vtctl = rd32(E1000_VT_CTL); |
|
3443 |
|
3444 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | |
|
3445 E1000_VT_CTL_DISABLE_DEF_POOL); |
|
3446 vtctl |= adapter->vfs_allocated_count << |
|
3447 E1000_VT_CTL_DEFAULT_POOL_SHIFT; |
|
3448 wr32(E1000_VT_CTL, vtctl); |
|
3449 } |
|
3450 if (adapter->rss_queues > 1) |
|
3451 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
|
3452 else |
|
3453 mrqc |= E1000_MRQC_ENABLE_VMDQ; |
|
3454 } else { |
|
3455 if (hw->mac.type != e1000_i211) |
|
3456 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; |
|
3457 } |
|
3458 igb_vmm_control(adapter); |
|
3459 |
|
3460 wr32(E1000_MRQC, mrqc); |
|
3461 } |
|
3462 |
|
3463 /** |
|
3464 * igb_setup_rctl - configure the receive control registers |
|
3465 * @adapter: Board private structure |
|
3466 **/ |
|
3467 void igb_setup_rctl(struct igb_adapter *adapter) |
|
3468 { |
|
3469 struct e1000_hw *hw = &adapter->hw; |
|
3470 u32 rctl; |
|
3471 |
|
3472 rctl = rd32(E1000_RCTL); |
|
3473 |
|
3474 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); |
|
3475 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
|
3476 |
|
3477 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
|
3478 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
|
3479 |
|
3480 /* enable stripping of CRC. It's unlikely this will break BMC |
|
3481 * redirection as it did with e1000. Newer features require |
|
3482 * that the HW strips the CRC. |
|
3483 */ |
|
3484 rctl |= E1000_RCTL_SECRC; |
|
3485 |
|
3486 /* disable store bad packets and clear size bits. */ |
|
3487 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
|
3488 |
|
3489 /* enable LPE to prevent packets larger than max_frame_size */ |
|
3490 rctl |= E1000_RCTL_LPE; |
|
3491 |
|
3492 /* disable queue 0 to prevent tail write w/o re-config */ |
|
3493 wr32(E1000_RXDCTL(0), 0); |
|
3494 |
|
3495 /* Attention!!! For SR-IOV PF driver operations you must enable |
|
3496 * queue drop for all VF and PF queues to prevent head of line blocking |
|
3497 * if an un-trusted VF does not provide descriptors to hardware. |
|
3498 */ |
|
3499 if (adapter->vfs_allocated_count) { |
|
3500 /* set all queue drop enable bits */ |
|
3501 wr32(E1000_QDE, ALL_QUEUES); |
|
3502 } |
|
3503 |
|
3504 /* This is useful for sniffing bad packets. */ |
|
3505 if (adapter->netdev->features & NETIF_F_RXALL) { |
|
3506 /* UPE and MPE will be handled by normal PROMISC logic |
|
3507 * in e1000e_set_rx_mode |
|
3508 */ |
|
3509 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ |
|
3510 E1000_RCTL_BAM | /* RX All Bcast Pkts */ |
|
3511 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ |
|
3512 |
|
3513 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ |
|
3514 E1000_RCTL_DPF | /* Allow filtered pause */ |
|
3515 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ |
|
3516 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, |
|
3517 * and that breaks VLANs. |
|
3518 */ |
|
3519 } |
|
3520 |
|
3521 wr32(E1000_RCTL, rctl); |
|
3522 } |
|
3523 |
|
3524 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
|
3525 int vfn) |
|
3526 { |
|
3527 struct e1000_hw *hw = &adapter->hw; |
|
3528 u32 vmolr; |
|
3529 |
|
3530 /* if it isn't the PF check to see if VFs are enabled and |
|
3531 * increase the size to support vlan tags |
|
3532 */ |
|
3533 if (vfn < adapter->vfs_allocated_count && |
|
3534 adapter->vf_data[vfn].vlans_enabled) |
|
3535 size += VLAN_TAG_SIZE; |
|
3536 |
|
3537 vmolr = rd32(E1000_VMOLR(vfn)); |
|
3538 vmolr &= ~E1000_VMOLR_RLPML_MASK; |
|
3539 vmolr |= size | E1000_VMOLR_LPE; |
|
3540 wr32(E1000_VMOLR(vfn), vmolr); |
|
3541 |
|
3542 return 0; |
|
3543 } |
|
3544 |
|
3545 /** |
|
3546 * igb_rlpml_set - set maximum receive packet size |
|
3547 * @adapter: board private structure |
|
3548 * |
|
3549 * Configure maximum receivable packet size. |
|
3550 **/ |
|
3551 static void igb_rlpml_set(struct igb_adapter *adapter) |
|
3552 { |
|
3553 u32 max_frame_size = adapter->max_frame_size; |
|
3554 struct e1000_hw *hw = &adapter->hw; |
|
3555 u16 pf_id = adapter->vfs_allocated_count; |
|
3556 |
|
3557 if (pf_id) { |
|
3558 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); |
|
3559 /* If we're in VMDQ or SR-IOV mode, then set global RLPML |
|
3560 * to our max jumbo frame size, in case we need to enable |
|
3561 * jumbo frames on one of the rings later. |
|
3562 * This will not pass over-length frames into the default |
|
3563 * queue because it's gated by the VMOLR.RLPML. |
|
3564 */ |
|
3565 max_frame_size = MAX_JUMBO_FRAME_SIZE; |
|
3566 } |
|
3567 |
|
3568 wr32(E1000_RLPML, max_frame_size); |
|
3569 } |
|
3570 |
|
3571 static inline void igb_set_vmolr(struct igb_adapter *adapter, |
|
3572 int vfn, bool aupe) |
|
3573 { |
|
3574 struct e1000_hw *hw = &adapter->hw; |
|
3575 u32 vmolr; |
|
3576 |
|
3577 /* This register exists only on 82576 and newer so if we are older then |
|
3578 * we should exit and do nothing |
|
3579 */ |
|
3580 if (hw->mac.type < e1000_82576) |
|
3581 return; |
|
3582 |
|
3583 vmolr = rd32(E1000_VMOLR(vfn)); |
|
3584 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
|
3585 if (hw->mac.type == e1000_i350) { |
|
3586 u32 dvmolr; |
|
3587 |
|
3588 dvmolr = rd32(E1000_DVMOLR(vfn)); |
|
3589 dvmolr |= E1000_DVMOLR_STRVLAN; |
|
3590 wr32(E1000_DVMOLR(vfn), dvmolr); |
|
3591 } |
|
3592 if (aupe) |
|
3593 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ |
|
3594 else |
|
3595 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ |
|
3596 |
|
3597 /* clear all bits that might not be set */ |
|
3598 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); |
|
3599 |
|
3600 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
|
3601 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
|
3602 /* for VMDq only allow the VFs and pool 0 to accept broadcast and |
|
3603 * multicast packets |
|
3604 */ |
|
3605 if (vfn <= adapter->vfs_allocated_count) |
|
3606 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ |
|
3607 |
|
3608 wr32(E1000_VMOLR(vfn), vmolr); |
|
3609 } |
|
3610 |
|
3611 /** |
|
3612 * igb_configure_rx_ring - Configure a receive ring after Reset |
|
3613 * @adapter: board private structure |
|
3614 * @ring: receive ring to be configured |
|
3615 * |
|
3616 * Configure the Rx unit of the MAC after a reset. |
|
3617 **/ |
|
3618 void igb_configure_rx_ring(struct igb_adapter *adapter, |
|
3619 struct igb_ring *ring) |
|
3620 { |
|
3621 struct e1000_hw *hw = &adapter->hw; |
|
3622 u64 rdba = ring->dma; |
|
3623 int reg_idx = ring->reg_idx; |
|
3624 u32 srrctl = 0, rxdctl = 0; |
|
3625 |
|
3626 /* disable the queue */ |
|
3627 wr32(E1000_RXDCTL(reg_idx), 0); |
|
3628 |
|
3629 /* Set DMA base address registers */ |
|
3630 wr32(E1000_RDBAL(reg_idx), |
|
3631 rdba & 0x00000000ffffffffULL); |
|
3632 wr32(E1000_RDBAH(reg_idx), rdba >> 32); |
|
3633 wr32(E1000_RDLEN(reg_idx), |
|
3634 ring->count * sizeof(union e1000_adv_rx_desc)); |
|
3635 |
|
3636 /* initialize head and tail */ |
|
3637 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
|
3638 wr32(E1000_RDH(reg_idx), 0); |
|
3639 writel(0, ring->tail); |
|
3640 |
|
3641 /* set descriptor configuration */ |
|
3642 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
|
3643 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
|
3644 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; |
|
3645 if (hw->mac.type >= e1000_82580) |
|
3646 srrctl |= E1000_SRRCTL_TIMESTAMP; |
|
3647 /* Only set Drop Enable if we are supporting multiple queues */ |
|
3648 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) |
|
3649 srrctl |= E1000_SRRCTL_DROP_EN; |
|
3650 |
|
3651 wr32(E1000_SRRCTL(reg_idx), srrctl); |
|
3652 |
|
3653 /* set filtering for VMDQ pools */ |
|
3654 igb_set_vmolr(adapter, reg_idx & 0x7, true); |
|
3655 |
|
3656 rxdctl |= IGB_RX_PTHRESH; |
|
3657 rxdctl |= IGB_RX_HTHRESH << 8; |
|
3658 rxdctl |= IGB_RX_WTHRESH << 16; |
|
3659 |
|
3660 /* enable receive descriptor fetching */ |
|
3661 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; |
|
3662 wr32(E1000_RXDCTL(reg_idx), rxdctl); |
|
3663 } |
|
3664 |
|
3665 /** |
|
3666 * igb_configure_rx - Configure receive Unit after Reset |
|
3667 * @adapter: board private structure |
|
3668 * |
|
3669 * Configure the Rx unit of the MAC after a reset. |
|
3670 **/ |
|
3671 static void igb_configure_rx(struct igb_adapter *adapter) |
|
3672 { |
|
3673 int i; |
|
3674 |
|
3675 /* set UTA to appropriate mode */ |
|
3676 igb_set_uta(adapter); |
|
3677 |
|
3678 /* set the correct pool for the PF default MAC address in entry 0 */ |
|
3679 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, |
|
3680 adapter->vfs_allocated_count); |
|
3681 |
|
3682 /* Setup the HW Rx Head and Tail Descriptor Pointers and |
|
3683 * the Base and Length of the Rx Descriptor Ring |
|
3684 */ |
|
3685 for (i = 0; i < adapter->num_rx_queues; i++) |
|
3686 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
|
3687 } |
|
3688 |
|
3689 /** |
|
3690 * igb_free_tx_resources - Free Tx Resources per Queue |
|
3691 * @tx_ring: Tx descriptor ring for a specific queue |
|
3692 * |
|
3693 * Free all transmit software resources |
|
3694 **/ |
|
3695 void igb_free_tx_resources(struct igb_ring *tx_ring) |
|
3696 { |
|
3697 igb_clean_tx_ring(tx_ring); |
|
3698 |
|
3699 vfree(tx_ring->tx_buffer_info); |
|
3700 tx_ring->tx_buffer_info = NULL; |
|
3701 |
|
3702 /* if not set, then don't free */ |
|
3703 if (!tx_ring->desc) |
|
3704 return; |
|
3705 |
|
3706 dma_free_coherent(tx_ring->dev, tx_ring->size, |
|
3707 tx_ring->desc, tx_ring->dma); |
|
3708 |
|
3709 tx_ring->desc = NULL; |
|
3710 } |
|
3711 |
|
3712 /** |
|
3713 * igb_free_all_tx_resources - Free Tx Resources for All Queues |
|
3714 * @adapter: board private structure |
|
3715 * |
|
3716 * Free all transmit software resources |
|
3717 **/ |
|
3718 static void igb_free_all_tx_resources(struct igb_adapter *adapter) |
|
3719 { |
|
3720 int i; |
|
3721 |
|
3722 for (i = 0; i < adapter->num_tx_queues; i++) |
|
3723 if (adapter->tx_ring[i]) |
|
3724 igb_free_tx_resources(adapter->tx_ring[i]); |
|
3725 } |
|
3726 |
|
3727 void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
|
3728 struct igb_tx_buffer *tx_buffer) |
|
3729 { |
|
3730 if (tx_buffer->skb) { |
|
3731 dev_kfree_skb_any(tx_buffer->skb); |
|
3732 if (dma_unmap_len(tx_buffer, len)) |
|
3733 dma_unmap_single(ring->dev, |
|
3734 dma_unmap_addr(tx_buffer, dma), |
|
3735 dma_unmap_len(tx_buffer, len), |
|
3736 DMA_TO_DEVICE); |
|
3737 } else if (dma_unmap_len(tx_buffer, len)) { |
|
3738 dma_unmap_page(ring->dev, |
|
3739 dma_unmap_addr(tx_buffer, dma), |
|
3740 dma_unmap_len(tx_buffer, len), |
|
3741 DMA_TO_DEVICE); |
|
3742 } |
|
3743 tx_buffer->next_to_watch = NULL; |
|
3744 tx_buffer->skb = NULL; |
|
3745 dma_unmap_len_set(tx_buffer, len, 0); |
|
3746 /* buffer_info must be completely set up in the transmit path */ |
|
3747 } |
|
3748 |
|
3749 /** |
|
3750 * igb_clean_tx_ring - Free Tx Buffers |
|
3751 * @tx_ring: ring to be cleaned |
|
3752 **/ |
|
3753 static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
|
3754 { |
|
3755 struct igb_tx_buffer *buffer_info; |
|
3756 unsigned long size; |
|
3757 u16 i; |
|
3758 |
|
3759 if (!tx_ring->tx_buffer_info) |
|
3760 return; |
|
3761 /* Free all the Tx ring sk_buffs */ |
|
3762 |
|
3763 for (i = 0; i < tx_ring->count; i++) { |
|
3764 buffer_info = &tx_ring->tx_buffer_info[i]; |
|
3765 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
|
3766 } |
|
3767 |
|
3768 netdev_tx_reset_queue(txring_txq(tx_ring)); |
|
3769 |
|
3770 size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
|
3771 memset(tx_ring->tx_buffer_info, 0, size); |
|
3772 |
|
3773 /* Zero out the descriptor ring */ |
|
3774 memset(tx_ring->desc, 0, tx_ring->size); |
|
3775 |
|
3776 tx_ring->next_to_use = 0; |
|
3777 tx_ring->next_to_clean = 0; |
|
3778 } |
|
3779 |
|
3780 /** |
|
3781 * igb_clean_all_tx_rings - Free Tx Buffers for all queues |
|
3782 * @adapter: board private structure |
|
3783 **/ |
|
3784 static void igb_clean_all_tx_rings(struct igb_adapter *adapter) |
|
3785 { |
|
3786 int i; |
|
3787 |
|
3788 for (i = 0; i < adapter->num_tx_queues; i++) |
|
3789 if (adapter->tx_ring[i]) |
|
3790 igb_clean_tx_ring(adapter->tx_ring[i]); |
|
3791 } |
|
3792 |
|
3793 /** |
|
3794 * igb_free_rx_resources - Free Rx Resources |
|
3795 * @rx_ring: ring to clean the resources from |
|
3796 * |
|
3797 * Free all receive software resources |
|
3798 **/ |
|
3799 void igb_free_rx_resources(struct igb_ring *rx_ring) |
|
3800 { |
|
3801 igb_clean_rx_ring(rx_ring); |
|
3802 |
|
3803 vfree(rx_ring->rx_buffer_info); |
|
3804 rx_ring->rx_buffer_info = NULL; |
|
3805 |
|
3806 /* if not set, then don't free */ |
|
3807 if (!rx_ring->desc) |
|
3808 return; |
|
3809 |
|
3810 dma_free_coherent(rx_ring->dev, rx_ring->size, |
|
3811 rx_ring->desc, rx_ring->dma); |
|
3812 |
|
3813 rx_ring->desc = NULL; |
|
3814 } |
|
3815 |
|
3816 /** |
|
3817 * igb_free_all_rx_resources - Free Rx Resources for All Queues |
|
3818 * @adapter: board private structure |
|
3819 * |
|
3820 * Free all receive software resources |
|
3821 **/ |
|
3822 static void igb_free_all_rx_resources(struct igb_adapter *adapter) |
|
3823 { |
|
3824 int i; |
|
3825 |
|
3826 for (i = 0; i < adapter->num_rx_queues; i++) |
|
3827 if (adapter->rx_ring[i]) |
|
3828 igb_free_rx_resources(adapter->rx_ring[i]); |
|
3829 } |
|
3830 |
|
3831 /** |
|
3832 * igb_clean_rx_ring - Free Rx Buffers per Queue |
|
3833 * @rx_ring: ring to free buffers from |
|
3834 **/ |
|
3835 static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
|
3836 { |
|
3837 unsigned long size; |
|
3838 u16 i; |
|
3839 |
|
3840 if (rx_ring->skb) |
|
3841 dev_kfree_skb(rx_ring->skb); |
|
3842 rx_ring->skb = NULL; |
|
3843 |
|
3844 if (!rx_ring->rx_buffer_info) |
|
3845 return; |
|
3846 |
|
3847 /* Free all the Rx ring sk_buffs */ |
|
3848 for (i = 0; i < rx_ring->count; i++) { |
|
3849 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
|
3850 |
|
3851 if (!buffer_info->page) |
|
3852 continue; |
|
3853 |
|
3854 dma_unmap_page(rx_ring->dev, |
|
3855 buffer_info->dma, |
|
3856 PAGE_SIZE, |
|
3857 DMA_FROM_DEVICE); |
|
3858 __free_page(buffer_info->page); |
|
3859 |
|
3860 buffer_info->page = NULL; |
|
3861 } |
|
3862 |
|
3863 size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
|
3864 memset(rx_ring->rx_buffer_info, 0, size); |
|
3865 |
|
3866 /* Zero out the descriptor ring */ |
|
3867 memset(rx_ring->desc, 0, rx_ring->size); |
|
3868 |
|
3869 rx_ring->next_to_alloc = 0; |
|
3870 rx_ring->next_to_clean = 0; |
|
3871 rx_ring->next_to_use = 0; |
|
3872 } |
|
3873 |
|
3874 /** |
|
3875 * igb_clean_all_rx_rings - Free Rx Buffers for all queues |
|
3876 * @adapter: board private structure |
|
3877 **/ |
|
3878 static void igb_clean_all_rx_rings(struct igb_adapter *adapter) |
|
3879 { |
|
3880 int i; |
|
3881 |
|
3882 for (i = 0; i < adapter->num_rx_queues; i++) |
|
3883 if (adapter->rx_ring[i]) |
|
3884 igb_clean_rx_ring(adapter->rx_ring[i]); |
|
3885 } |
|
3886 |
|
3887 /** |
|
3888 * igb_set_mac - Change the Ethernet Address of the NIC |
|
3889 * @netdev: network interface device structure |
|
3890 * @p: pointer to an address structure |
|
3891 * |
|
3892 * Returns 0 on success, negative on failure |
|
3893 **/ |
|
3894 static int igb_set_mac(struct net_device *netdev, void *p) |
|
3895 { |
|
3896 struct igb_adapter *adapter = netdev_priv(netdev); |
|
3897 struct e1000_hw *hw = &adapter->hw; |
|
3898 struct sockaddr *addr = p; |
|
3899 |
|
3900 if (!is_valid_ether_addr(addr->sa_data)) |
|
3901 return -EADDRNOTAVAIL; |
|
3902 |
|
3903 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
|
3904 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
|
3905 |
|
3906 /* set the correct pool for the new PF MAC address in entry 0 */ |
|
3907 igb_rar_set_qsel(adapter, hw->mac.addr, 0, |
|
3908 adapter->vfs_allocated_count); |
|
3909 |
|
3910 return 0; |
|
3911 } |
|
3912 |
|
3913 /** |
|
3914 * igb_write_mc_addr_list - write multicast addresses to MTA |
|
3915 * @netdev: network interface device structure |
|
3916 * |
|
3917 * Writes multicast address list to the MTA hash table. |
|
3918 * Returns: -ENOMEM on failure |
|
3919 * 0 on no addresses written |
|
3920 * X on writing X addresses to MTA |
|
3921 **/ |
|
3922 static int igb_write_mc_addr_list(struct net_device *netdev) |
|
3923 { |
|
3924 struct igb_adapter *adapter = netdev_priv(netdev); |
|
3925 struct e1000_hw *hw = &adapter->hw; |
|
3926 struct netdev_hw_addr *ha; |
|
3927 u8 *mta_list; |
|
3928 int i; |
|
3929 |
|
3930 if (netdev_mc_empty(netdev)) { |
|
3931 /* nothing to program, so clear mc list */ |
|
3932 igb_update_mc_addr_list(hw, NULL, 0); |
|
3933 igb_restore_vf_multicasts(adapter); |
|
3934 return 0; |
|
3935 } |
|
3936 |
|
3937 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
|
3938 if (!mta_list) |
|
3939 return -ENOMEM; |
|
3940 |
|
3941 /* The shared function expects a packed array of only addresses. */ |
|
3942 i = 0; |
|
3943 netdev_for_each_mc_addr(ha, netdev) |
|
3944 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); |
|
3945 |
|
3946 igb_update_mc_addr_list(hw, mta_list, i); |
|
3947 kfree(mta_list); |
|
3948 |
|
3949 return netdev_mc_count(netdev); |
|
3950 } |
|
3951 |
|
3952 /** |
|
3953 * igb_write_uc_addr_list - write unicast addresses to RAR table |
|
3954 * @netdev: network interface device structure |
|
3955 * |
|
3956 * Writes unicast address list to the RAR table. |
|
3957 * Returns: -ENOMEM on failure/insufficient address space |
|
3958 * 0 on no addresses written |
|
3959 * X on writing X addresses to the RAR table |
|
3960 **/ |
|
3961 static int igb_write_uc_addr_list(struct net_device *netdev) |
|
3962 { |
|
3963 struct igb_adapter *adapter = netdev_priv(netdev); |
|
3964 struct e1000_hw *hw = &adapter->hw; |
|
3965 unsigned int vfn = adapter->vfs_allocated_count; |
|
3966 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); |
|
3967 int count = 0; |
|
3968 |
|
3969 /* return ENOMEM indicating insufficient memory for addresses */ |
|
3970 if (netdev_uc_count(netdev) > rar_entries) |
|
3971 return -ENOMEM; |
|
3972 |
|
3973 if (!netdev_uc_empty(netdev) && rar_entries) { |
|
3974 struct netdev_hw_addr *ha; |
|
3975 |
|
3976 netdev_for_each_uc_addr(ha, netdev) { |
|
3977 if (!rar_entries) |
|
3978 break; |
|
3979 igb_rar_set_qsel(adapter, ha->addr, |
|
3980 rar_entries--, |
|
3981 vfn); |
|
3982 count++; |
|
3983 } |
|
3984 } |
|
3985 /* write the addresses in reverse order to avoid write combining */ |
|
3986 for (; rar_entries > 0 ; rar_entries--) { |
|
3987 wr32(E1000_RAH(rar_entries), 0); |
|
3988 wr32(E1000_RAL(rar_entries), 0); |
|
3989 } |
|
3990 wrfl(); |
|
3991 |
|
3992 return count; |
|
3993 } |
|
3994 |
|
3995 /** |
|
3996 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set |
|
3997 * @netdev: network interface device structure |
|
3998 * |
|
3999 * The set_rx_mode entry point is called whenever the unicast or multicast |
|
4000 * address lists or the network interface flags are updated. This routine is |
|
4001 * responsible for configuring the hardware for proper unicast, multicast, |
|
4002 * promiscuous mode, and all-multi behavior. |
|
4003 **/ |
|
4004 static void igb_set_rx_mode(struct net_device *netdev) |
|
4005 { |
|
4006 struct igb_adapter *adapter = netdev_priv(netdev); |
|
4007 struct e1000_hw *hw = &adapter->hw; |
|
4008 unsigned int vfn = adapter->vfs_allocated_count; |
|
4009 u32 rctl, vmolr = 0; |
|
4010 int count; |
|
4011 |
|
4012 /* Check for Promiscuous and All Multicast modes */ |
|
4013 rctl = rd32(E1000_RCTL); |
|
4014 |
|
4015 /* clear the effected bits */ |
|
4016 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); |
|
4017 |
|
4018 if (netdev->flags & IFF_PROMISC) { |
|
4019 /* retain VLAN HW filtering if in VT mode */ |
|
4020 if (adapter->vfs_allocated_count) |
|
4021 rctl |= E1000_RCTL_VFE; |
|
4022 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
|
4023 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); |
|
4024 } else { |
|
4025 if (netdev->flags & IFF_ALLMULTI) { |
|
4026 rctl |= E1000_RCTL_MPE; |
|
4027 vmolr |= E1000_VMOLR_MPME; |
|
4028 } else { |
|
4029 /* Write addresses to the MTA, if the attempt fails |
|
4030 * then we should just turn on promiscuous mode so |
|
4031 * that we can at least receive multicast traffic |
|
4032 */ |
|
4033 count = igb_write_mc_addr_list(netdev); |
|
4034 if (count < 0) { |
|
4035 rctl |= E1000_RCTL_MPE; |
|
4036 vmolr |= E1000_VMOLR_MPME; |
|
4037 } else if (count) { |
|
4038 vmolr |= E1000_VMOLR_ROMPE; |
|
4039 } |
|
4040 } |
|
4041 /* Write addresses to available RAR registers, if there is not |
|
4042 * sufficient space to store all the addresses then enable |
|
4043 * unicast promiscuous mode |
|
4044 */ |
|
4045 count = igb_write_uc_addr_list(netdev); |
|
4046 if (count < 0) { |
|
4047 rctl |= E1000_RCTL_UPE; |
|
4048 vmolr |= E1000_VMOLR_ROPE; |
|
4049 } |
|
4050 rctl |= E1000_RCTL_VFE; |
|
4051 } |
|
4052 wr32(E1000_RCTL, rctl); |
|
4053 |
|
4054 /* In order to support SR-IOV and eventually VMDq it is necessary to set |
|
4055 * the VMOLR to enable the appropriate modes. Without this workaround |
|
4056 * we will have issues with VLAN tag stripping not being done for frames |
|
4057 * that are only arriving because we are the default pool |
|
4058 */ |
|
4059 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) |
|
4060 return; |
|
4061 |
|
4062 vmolr |= rd32(E1000_VMOLR(vfn)) & |
|
4063 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); |
|
4064 wr32(E1000_VMOLR(vfn), vmolr); |
|
4065 igb_restore_vf_multicasts(adapter); |
|
4066 } |
|
4067 |
|
4068 static void igb_check_wvbr(struct igb_adapter *adapter) |
|
4069 { |
|
4070 struct e1000_hw *hw = &adapter->hw; |
|
4071 u32 wvbr = 0; |
|
4072 |
|
4073 switch (hw->mac.type) { |
|
4074 case e1000_82576: |
|
4075 case e1000_i350: |
|
4076 wvbr = rd32(E1000_WVBR); |
|
4077 if (!wvbr) |
|
4078 return; |
|
4079 break; |
|
4080 default: |
|
4081 break; |
|
4082 } |
|
4083 |
|
4084 adapter->wvbr |= wvbr; |
|
4085 } |
|
4086 |
|
4087 #define IGB_STAGGERED_QUEUE_OFFSET 8 |
|
4088 |
|
4089 static void igb_spoof_check(struct igb_adapter *adapter) |
|
4090 { |
|
4091 int j; |
|
4092 |
|
4093 if (!adapter->wvbr) |
|
4094 return; |
|
4095 |
|
4096 for (j = 0; j < adapter->vfs_allocated_count; j++) { |
|
4097 if (adapter->wvbr & (1 << j) || |
|
4098 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { |
|
4099 dev_warn(&adapter->pdev->dev, |
|
4100 "Spoof event(s) detected on VF %d\n", j); |
|
4101 adapter->wvbr &= |
|
4102 ~((1 << j) | |
|
4103 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); |
|
4104 } |
|
4105 } |
|
4106 } |
|
4107 |
|
4108 /* Need to wait a few seconds after link up to get diagnostic information from |
|
4109 * the phy |
|
4110 */ |
|
4111 static void igb_update_phy_info(unsigned long data) |
|
4112 { |
|
4113 struct igb_adapter *adapter = (struct igb_adapter *) data; |
|
4114 igb_get_phy_info(&adapter->hw); |
|
4115 } |
|
4116 |
|
4117 /** |
|
4118 * igb_has_link - check shared code for link and determine up/down |
|
4119 * @adapter: pointer to driver private info |
|
4120 **/ |
|
4121 bool igb_has_link(struct igb_adapter *adapter) |
|
4122 { |
|
4123 struct e1000_hw *hw = &adapter->hw; |
|
4124 bool link_active = false; |
|
4125 |
|
4126 /* get_link_status is set on LSC (link status) interrupt or |
|
4127 * rx sequence error interrupt. get_link_status will stay |
|
4128 * false until the e1000_check_for_link establishes link |
|
4129 * for copper adapters ONLY |
|
4130 */ |
|
4131 switch (hw->phy.media_type) { |
|
4132 case e1000_media_type_copper: |
|
4133 if (!hw->mac.get_link_status) |
|
4134 return true; |
|
4135 case e1000_media_type_internal_serdes: |
|
4136 hw->mac.ops.check_for_link(hw); |
|
4137 link_active = !hw->mac.get_link_status; |
|
4138 break; |
|
4139 default: |
|
4140 case e1000_media_type_unknown: |
|
4141 break; |
|
4142 } |
|
4143 |
|
4144 if (((hw->mac.type == e1000_i210) || |
|
4145 (hw->mac.type == e1000_i211)) && |
|
4146 (hw->phy.id == I210_I_PHY_ID)) { |
|
4147 if (!netif_carrier_ok(adapter->netdev)) { |
|
4148 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; |
|
4149 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { |
|
4150 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; |
|
4151 adapter->link_check_timeout = jiffies; |
|
4152 } |
|
4153 } |
|
4154 |
|
4155 return link_active; |
|
4156 } |
|
4157 |
|
4158 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
|
4159 { |
|
4160 bool ret = false; |
|
4161 u32 ctrl_ext, thstat; |
|
4162 |
|
4163 /* check for thermal sensor event on i350 copper only */ |
|
4164 if (hw->mac.type == e1000_i350) { |
|
4165 thstat = rd32(E1000_THSTAT); |
|
4166 ctrl_ext = rd32(E1000_CTRL_EXT); |
|
4167 |
|
4168 if ((hw->phy.media_type == e1000_media_type_copper) && |
|
4169 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) |
|
4170 ret = !!(thstat & event); |
|
4171 } |
|
4172 |
|
4173 return ret; |
|
4174 } |
|
4175 |
|
4176 /** |
|
4177 * igb_check_lvmmc - check for malformed packets received |
|
4178 * and indicated in LVMMC register |
|
4179 * @adapter: pointer to adapter |
|
4180 **/ |
|
4181 static void igb_check_lvmmc(struct igb_adapter *adapter) |
|
4182 { |
|
4183 struct e1000_hw *hw = &adapter->hw; |
|
4184 u32 lvmmc; |
|
4185 |
|
4186 lvmmc = rd32(E1000_LVMMC); |
|
4187 if (lvmmc) { |
|
4188 if (unlikely(net_ratelimit())) { |
|
4189 netdev_warn(adapter->netdev, |
|
4190 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n", |
|
4191 lvmmc); |
|
4192 } |
|
4193 } |
|
4194 } |
|
4195 |
|
4196 /** |
|
4197 * igb_watchdog - Timer Call-back |
|
4198 * @data: pointer to adapter cast into an unsigned long |
|
4199 **/ |
|
4200 static void igb_watchdog(unsigned long data) |
|
4201 { |
|
4202 struct igb_adapter *adapter = (struct igb_adapter *)data; |
|
4203 /* Do the rest outside of interrupt context */ |
|
4204 schedule_work(&adapter->watchdog_task); |
|
4205 } |
|
4206 |
|
4207 static void igb_watchdog_task(struct work_struct *work) |
|
4208 { |
|
4209 struct igb_adapter *adapter = container_of(work, |
|
4210 struct igb_adapter, |
|
4211 watchdog_task); |
|
4212 struct e1000_hw *hw = &adapter->hw; |
|
4213 struct e1000_phy_info *phy = &hw->phy; |
|
4214 struct net_device *netdev = adapter->netdev; |
|
4215 u32 link; |
|
4216 int i; |
|
4217 u32 connsw; |
|
4218 |
|
4219 link = igb_has_link(adapter); |
|
4220 |
|
4221 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { |
|
4222 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) |
|
4223 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; |
|
4224 else |
|
4225 link = false; |
|
4226 } |
|
4227 |
|
4228 /* Force link down if we have fiber to swap to */ |
|
4229 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { |
|
4230 if (hw->phy.media_type == e1000_media_type_copper) { |
|
4231 connsw = rd32(E1000_CONNSW); |
|
4232 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) |
|
4233 link = 0; |
|
4234 } |
|
4235 } |
|
4236 if (link) { |
|
4237 /* Perform a reset if the media type changed. */ |
|
4238 if (hw->dev_spec._82575.media_changed) { |
|
4239 hw->dev_spec._82575.media_changed = false; |
|
4240 adapter->flags |= IGB_FLAG_MEDIA_RESET; |
|
4241 igb_reset(adapter); |
|
4242 } |
|
4243 /* Cancel scheduled suspend requests. */ |
|
4244 pm_runtime_resume(netdev->dev.parent); |
|
4245 |
|
4246 if (!netif_carrier_ok(netdev)) { |
|
4247 u32 ctrl; |
|
4248 |
|
4249 hw->mac.ops.get_speed_and_duplex(hw, |
|
4250 &adapter->link_speed, |
|
4251 &adapter->link_duplex); |
|
4252 |
|
4253 ctrl = rd32(E1000_CTRL); |
|
4254 /* Links status message must follow this format */ |
|
4255 netdev_info(netdev, |
|
4256 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", |
|
4257 netdev->name, |
|
4258 adapter->link_speed, |
|
4259 adapter->link_duplex == FULL_DUPLEX ? |
|
4260 "Full" : "Half", |
|
4261 (ctrl & E1000_CTRL_TFCE) && |
|
4262 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : |
|
4263 (ctrl & E1000_CTRL_RFCE) ? "RX" : |
|
4264 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); |
|
4265 |
|
4266 /* disable EEE if enabled */ |
|
4267 if ((adapter->flags & IGB_FLAG_EEE) && |
|
4268 (adapter->link_duplex == HALF_DUPLEX)) { |
|
4269 dev_info(&adapter->pdev->dev, |
|
4270 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); |
|
4271 adapter->hw.dev_spec._82575.eee_disable = true; |
|
4272 adapter->flags &= ~IGB_FLAG_EEE; |
|
4273 } |
|
4274 |
|
4275 /* check if SmartSpeed worked */ |
|
4276 igb_check_downshift(hw); |
|
4277 if (phy->speed_downgraded) |
|
4278 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); |
|
4279 |
|
4280 /* check for thermal sensor event */ |
|
4281 if (igb_thermal_sensor_event(hw, |
|
4282 E1000_THSTAT_LINK_THROTTLE)) |
|
4283 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); |
|
4284 |
|
4285 /* adjust timeout factor according to speed/duplex */ |
|
4286 adapter->tx_timeout_factor = 1; |
|
4287 switch (adapter->link_speed) { |
|
4288 case SPEED_10: |
|
4289 adapter->tx_timeout_factor = 14; |
|
4290 break; |
|
4291 case SPEED_100: |
|
4292 /* maybe add some timeout factor ? */ |
|
4293 break; |
|
4294 } |
|
4295 |
|
4296 netif_carrier_on(netdev); |
|
4297 |
|
4298 igb_ping_all_vfs(adapter); |
|
4299 igb_check_vf_rate_limit(adapter); |
|
4300 |
|
4301 /* link state has changed, schedule phy info update */ |
|
4302 if (!test_bit(__IGB_DOWN, &adapter->state)) |
|
4303 mod_timer(&adapter->phy_info_timer, |
|
4304 round_jiffies(jiffies + 2 * HZ)); |
|
4305 } |
|
4306 } else { |
|
4307 if (netif_carrier_ok(netdev)) { |
|
4308 adapter->link_speed = 0; |
|
4309 adapter->link_duplex = 0; |
|
4310 |
|
4311 /* check for thermal sensor event */ |
|
4312 if (igb_thermal_sensor_event(hw, |
|
4313 E1000_THSTAT_PWR_DOWN)) { |
|
4314 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); |
|
4315 } |
|
4316 |
|
4317 /* Links status message must follow this format */ |
|
4318 netdev_info(netdev, "igb: %s NIC Link is Down\n", |
|
4319 netdev->name); |
|
4320 netif_carrier_off(netdev); |
|
4321 |
|
4322 igb_ping_all_vfs(adapter); |
|
4323 |
|
4324 /* link state has changed, schedule phy info update */ |
|
4325 if (!test_bit(__IGB_DOWN, &adapter->state)) |
|
4326 mod_timer(&adapter->phy_info_timer, |
|
4327 round_jiffies(jiffies + 2 * HZ)); |
|
4328 |
|
4329 /* link is down, time to check for alternate media */ |
|
4330 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { |
|
4331 igb_check_swap_media(adapter); |
|
4332 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { |
|
4333 schedule_work(&adapter->reset_task); |
|
4334 /* return immediately */ |
|
4335 return; |
|
4336 } |
|
4337 } |
|
4338 pm_schedule_suspend(netdev->dev.parent, |
|
4339 MSEC_PER_SEC * 5); |
|
4340 |
|
4341 /* also check for alternate media here */ |
|
4342 } else if (!netif_carrier_ok(netdev) && |
|
4343 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { |
|
4344 igb_check_swap_media(adapter); |
|
4345 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { |
|
4346 schedule_work(&adapter->reset_task); |
|
4347 /* return immediately */ |
|
4348 return; |
|
4349 } |
|
4350 } |
|
4351 } |
|
4352 |
|
4353 spin_lock(&adapter->stats64_lock); |
|
4354 igb_update_stats(adapter, &adapter->stats64); |
|
4355 spin_unlock(&adapter->stats64_lock); |
|
4356 |
|
4357 for (i = 0; i < adapter->num_tx_queues; i++) { |
|
4358 struct igb_ring *tx_ring = adapter->tx_ring[i]; |
|
4359 if (!netif_carrier_ok(netdev)) { |
|
4360 /* We've lost link, so the controller stops DMA, |
|
4361 * but we've got queued Tx work that's never going |
|
4362 * to get done, so reset controller to flush Tx. |
|
4363 * (Do the reset outside of interrupt context). |
|
4364 */ |
|
4365 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
|
4366 adapter->tx_timeout_count++; |
|
4367 schedule_work(&adapter->reset_task); |
|
4368 /* return immediately since reset is imminent */ |
|
4369 return; |
|
4370 } |
|
4371 } |
|
4372 |
|
4373 /* Force detection of hung controller every watchdog period */ |
|
4374 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
|
4375 } |
|
4376 |
|
4377 /* Cause software interrupt to ensure Rx ring is cleaned */ |
|
4378 if (adapter->flags & IGB_FLAG_HAS_MSIX) { |
|
4379 u32 eics = 0; |
|
4380 |
|
4381 for (i = 0; i < adapter->num_q_vectors; i++) |
|
4382 eics |= adapter->q_vector[i]->eims_value; |
|
4383 wr32(E1000_EICS, eics); |
|
4384 } else { |
|
4385 wr32(E1000_ICS, E1000_ICS_RXDMT0); |
|
4386 } |
|
4387 |
|
4388 igb_spoof_check(adapter); |
|
4389 igb_ptp_rx_hang(adapter); |
|
4390 |
|
4391 /* Check LVMMC register on i350/i354 only */ |
|
4392 if ((adapter->hw.mac.type == e1000_i350) || |
|
4393 (adapter->hw.mac.type == e1000_i354)) |
|
4394 igb_check_lvmmc(adapter); |
|
4395 |
|
4396 /* Reset the timer */ |
|
4397 if (!test_bit(__IGB_DOWN, &adapter->state)) { |
|
4398 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) |
|
4399 mod_timer(&adapter->watchdog_timer, |
|
4400 round_jiffies(jiffies + HZ)); |
|
4401 else |
|
4402 mod_timer(&adapter->watchdog_timer, |
|
4403 round_jiffies(jiffies + 2 * HZ)); |
|
4404 } |
|
4405 } |
|
4406 |
|
4407 enum latency_range { |
|
4408 lowest_latency = 0, |
|
4409 low_latency = 1, |
|
4410 bulk_latency = 2, |
|
4411 latency_invalid = 255 |
|
4412 }; |
|
4413 |
|
4414 /** |
|
4415 * igb_update_ring_itr - update the dynamic ITR value based on packet size |
|
4416 * @q_vector: pointer to q_vector |
|
4417 * |
|
4418 * Stores a new ITR value based on strictly on packet size. This |
|
4419 * algorithm is less sophisticated than that used in igb_update_itr, |
|
4420 * due to the difficulty of synchronizing statistics across multiple |
|
4421 * receive rings. The divisors and thresholds used by this function |
|
4422 * were determined based on theoretical maximum wire speed and testing |
|
4423 * data, in order to minimize response time while increasing bulk |
|
4424 * throughput. |
|
4425 * This functionality is controlled by ethtool's coalescing settings. |
|
4426 * NOTE: This function is called only when operating in a multiqueue |
|
4427 * receive environment. |
|
4428 **/ |
|
4429 static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
|
4430 { |
|
4431 int new_val = q_vector->itr_val; |
|
4432 int avg_wire_size = 0; |
|
4433 struct igb_adapter *adapter = q_vector->adapter; |
|
4434 unsigned int packets; |
|
4435 |
|
4436 /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
|
4437 * ints/sec - ITR timer value of 120 ticks. |
|
4438 */ |
|
4439 if (adapter->link_speed != SPEED_1000) { |
|
4440 new_val = IGB_4K_ITR; |
|
4441 goto set_itr_val; |
|
4442 } |
|
4443 |
|
4444 packets = q_vector->rx.total_packets; |
|
4445 if (packets) |
|
4446 avg_wire_size = q_vector->rx.total_bytes / packets; |
|
4447 |
|
4448 packets = q_vector->tx.total_packets; |
|
4449 if (packets) |
|
4450 avg_wire_size = max_t(u32, avg_wire_size, |
|
4451 q_vector->tx.total_bytes / packets); |
|
4452 |
|
4453 /* if avg_wire_size isn't set no work was done */ |
|
4454 if (!avg_wire_size) |
|
4455 goto clear_counts; |
|
4456 |
|
4457 /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
|
4458 avg_wire_size += 24; |
|
4459 |
|
4460 /* Don't starve jumbo frames */ |
|
4461 avg_wire_size = min(avg_wire_size, 3000); |
|
4462 |
|
4463 /* Give a little boost to mid-size frames */ |
|
4464 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) |
|
4465 new_val = avg_wire_size / 3; |
|
4466 else |
|
4467 new_val = avg_wire_size / 2; |
|
4468 |
|
4469 /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
|
4470 if (new_val < IGB_20K_ITR && |
|
4471 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || |
|
4472 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) |
|
4473 new_val = IGB_20K_ITR; |
|
4474 |
|
4475 set_itr_val: |
|
4476 if (new_val != q_vector->itr_val) { |
|
4477 q_vector->itr_val = new_val; |
|
4478 q_vector->set_itr = 1; |
|
4479 } |
|
4480 clear_counts: |
|
4481 q_vector->rx.total_bytes = 0; |
|
4482 q_vector->rx.total_packets = 0; |
|
4483 q_vector->tx.total_bytes = 0; |
|
4484 q_vector->tx.total_packets = 0; |
|
4485 } |
|
4486 |
|
4487 /** |
|
4488 * igb_update_itr - update the dynamic ITR value based on statistics |
|
4489 * @q_vector: pointer to q_vector |
|
4490 * @ring_container: ring info to update the itr for |
|
4491 * |
|
4492 * Stores a new ITR value based on packets and byte |
|
4493 * counts during the last interrupt. The advantage of per interrupt |
|
4494 * computation is faster updates and more accurate ITR for the current |
|
4495 * traffic pattern. Constants in this function were computed |
|
4496 * based on theoretical maximum wire speed and thresholds were set based |
|
4497 * on testing data as well as attempting to minimize response time |
|
4498 * while increasing bulk throughput. |
|
4499 * This functionality is controlled by ethtool's coalescing settings. |
|
4500 * NOTE: These calculations are only valid when operating in a single- |
|
4501 * queue environment. |
|
4502 **/ |
|
4503 static void igb_update_itr(struct igb_q_vector *q_vector, |
|
4504 struct igb_ring_container *ring_container) |
|
4505 { |
|
4506 unsigned int packets = ring_container->total_packets; |
|
4507 unsigned int bytes = ring_container->total_bytes; |
|
4508 u8 itrval = ring_container->itr; |
|
4509 |
|
4510 /* no packets, exit with status unchanged */ |
|
4511 if (packets == 0) |
|
4512 return; |
|
4513 |
|
4514 switch (itrval) { |
|
4515 case lowest_latency: |
|
4516 /* handle TSO and jumbo frames */ |
|
4517 if (bytes/packets > 8000) |
|
4518 itrval = bulk_latency; |
|
4519 else if ((packets < 5) && (bytes > 512)) |
|
4520 itrval = low_latency; |
|
4521 break; |
|
4522 case low_latency: /* 50 usec aka 20000 ints/s */ |
|
4523 if (bytes > 10000) { |
|
4524 /* this if handles the TSO accounting */ |
|
4525 if (bytes/packets > 8000) |
|
4526 itrval = bulk_latency; |
|
4527 else if ((packets < 10) || ((bytes/packets) > 1200)) |
|
4528 itrval = bulk_latency; |
|
4529 else if ((packets > 35)) |
|
4530 itrval = lowest_latency; |
|
4531 } else if (bytes/packets > 2000) { |
|
4532 itrval = bulk_latency; |
|
4533 } else if (packets <= 2 && bytes < 512) { |
|
4534 itrval = lowest_latency; |
|
4535 } |
|
4536 break; |
|
4537 case bulk_latency: /* 250 usec aka 4000 ints/s */ |
|
4538 if (bytes > 25000) { |
|
4539 if (packets > 35) |
|
4540 itrval = low_latency; |
|
4541 } else if (bytes < 1500) { |
|
4542 itrval = low_latency; |
|
4543 } |
|
4544 break; |
|
4545 } |
|
4546 |
|
4547 /* clear work counters since we have the values we need */ |
|
4548 ring_container->total_bytes = 0; |
|
4549 ring_container->total_packets = 0; |
|
4550 |
|
4551 /* write updated itr to ring container */ |
|
4552 ring_container->itr = itrval; |
|
4553 } |
|
4554 |
|
4555 static void igb_set_itr(struct igb_q_vector *q_vector) |
|
4556 { |
|
4557 struct igb_adapter *adapter = q_vector->adapter; |
|
4558 u32 new_itr = q_vector->itr_val; |
|
4559 u8 current_itr = 0; |
|
4560 |
|
4561 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ |
|
4562 if (adapter->link_speed != SPEED_1000) { |
|
4563 current_itr = 0; |
|
4564 new_itr = IGB_4K_ITR; |
|
4565 goto set_itr_now; |
|
4566 } |
|
4567 |
|
4568 igb_update_itr(q_vector, &q_vector->tx); |
|
4569 igb_update_itr(q_vector, &q_vector->rx); |
|
4570 |
|
4571 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
|
4572 |
|
4573 /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
|
4574 if (current_itr == lowest_latency && |
|
4575 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || |
|
4576 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) |
|
4577 current_itr = low_latency; |
|
4578 |
|
4579 switch (current_itr) { |
|
4580 /* counts and packets in update_itr are dependent on these numbers */ |
|
4581 case lowest_latency: |
|
4582 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ |
|
4583 break; |
|
4584 case low_latency: |
|
4585 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ |
|
4586 break; |
|
4587 case bulk_latency: |
|
4588 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ |
|
4589 break; |
|
4590 default: |
|
4591 break; |
|
4592 } |
|
4593 |
|
4594 set_itr_now: |
|
4595 if (new_itr != q_vector->itr_val) { |
|
4596 /* this attempts to bias the interrupt rate towards Bulk |
|
4597 * by adding intermediate steps when interrupt rate is |
|
4598 * increasing |
|
4599 */ |
|
4600 new_itr = new_itr > q_vector->itr_val ? |
|
4601 max((new_itr * q_vector->itr_val) / |
|
4602 (new_itr + (q_vector->itr_val >> 2)), |
|
4603 new_itr) : new_itr; |
|
4604 /* Don't write the value here; it resets the adapter's |
|
4605 * internal timer, and causes us to delay far longer than |
|
4606 * we should between interrupts. Instead, we write the ITR |
|
4607 * value at the beginning of the next interrupt so the timing |
|
4608 * ends up being correct. |
|
4609 */ |
|
4610 q_vector->itr_val = new_itr; |
|
4611 q_vector->set_itr = 1; |
|
4612 } |
|
4613 } |
|
4614 |
|
4615 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
|
4616 u32 type_tucmd, u32 mss_l4len_idx) |
|
4617 { |
|
4618 struct e1000_adv_tx_context_desc *context_desc; |
|
4619 u16 i = tx_ring->next_to_use; |
|
4620 |
|
4621 context_desc = IGB_TX_CTXTDESC(tx_ring, i); |
|
4622 |
|
4623 i++; |
|
4624 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; |
|
4625 |
|
4626 /* set bits to identify this as an advanced context descriptor */ |
|
4627 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; |
|
4628 |
|
4629 /* For 82575, context index must be unique per ring. */ |
|
4630 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
|
4631 mss_l4len_idx |= tx_ring->reg_idx << 4; |
|
4632 |
|
4633 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
|
4634 context_desc->seqnum_seed = 0; |
|
4635 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); |
|
4636 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
|
4637 } |
|
4638 |
|
4639 static int igb_tso(struct igb_ring *tx_ring, |
|
4640 struct igb_tx_buffer *first, |
|
4641 u8 *hdr_len) |
|
4642 { |
|
4643 struct sk_buff *skb = first->skb; |
|
4644 u32 vlan_macip_lens, type_tucmd; |
|
4645 u32 mss_l4len_idx, l4len; |
|
4646 int err; |
|
4647 |
|
4648 if (skb->ip_summed != CHECKSUM_PARTIAL) |
|
4649 return 0; |
|
4650 |
|
4651 if (!skb_is_gso(skb)) |
|
4652 return 0; |
|
4653 |
|
4654 err = skb_cow_head(skb, 0); |
|
4655 if (err < 0) |
|
4656 return err; |
|
4657 |
|
4658 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
|
4659 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; |
|
4660 |
|
4661 if (first->protocol == htons(ETH_P_IP)) { |
|
4662 struct iphdr *iph = ip_hdr(skb); |
|
4663 iph->tot_len = 0; |
|
4664 iph->check = 0; |
|
4665 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, |
|
4666 iph->daddr, 0, |
|
4667 IPPROTO_TCP, |
|
4668 0); |
|
4669 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
|
4670 first->tx_flags |= IGB_TX_FLAGS_TSO | |
|
4671 IGB_TX_FLAGS_CSUM | |
|
4672 IGB_TX_FLAGS_IPV4; |
|
4673 } else if (skb_is_gso_v6(skb)) { |
|
4674 ipv6_hdr(skb)->payload_len = 0; |
|
4675 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, |
|
4676 &ipv6_hdr(skb)->daddr, |
|
4677 0, IPPROTO_TCP, 0); |
|
4678 first->tx_flags |= IGB_TX_FLAGS_TSO | |
|
4679 IGB_TX_FLAGS_CSUM; |
|
4680 } |
|
4681 |
|
4682 /* compute header lengths */ |
|
4683 l4len = tcp_hdrlen(skb); |
|
4684 *hdr_len = skb_transport_offset(skb) + l4len; |
|
4685 |
|
4686 /* update gso size and bytecount with header size */ |
|
4687 first->gso_segs = skb_shinfo(skb)->gso_segs; |
|
4688 first->bytecount += (first->gso_segs - 1) * *hdr_len; |
|
4689 |
|
4690 /* MSS L4LEN IDX */ |
|
4691 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
|
4692 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; |
|
4693 |
|
4694 /* VLAN MACLEN IPLEN */ |
|
4695 vlan_macip_lens = skb_network_header_len(skb); |
|
4696 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
|
4697 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
|
4698 |
|
4699 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
|
4700 |
|
4701 return 1; |
|
4702 } |
|
4703 |
|
4704 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
|
4705 { |
|
4706 struct sk_buff *skb = first->skb; |
|
4707 u32 vlan_macip_lens = 0; |
|
4708 u32 mss_l4len_idx = 0; |
|
4709 u32 type_tucmd = 0; |
|
4710 |
|
4711 if (skb->ip_summed != CHECKSUM_PARTIAL) { |
|
4712 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
|
4713 return; |
|
4714 } else { |
|
4715 u8 l4_hdr = 0; |
|
4716 |
|
4717 switch (first->protocol) { |
|
4718 case htons(ETH_P_IP): |
|
4719 vlan_macip_lens |= skb_network_header_len(skb); |
|
4720 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
|
4721 l4_hdr = ip_hdr(skb)->protocol; |
|
4722 break; |
|
4723 case htons(ETH_P_IPV6): |
|
4724 vlan_macip_lens |= skb_network_header_len(skb); |
|
4725 l4_hdr = ipv6_hdr(skb)->nexthdr; |
|
4726 break; |
|
4727 default: |
|
4728 if (unlikely(net_ratelimit())) { |
|
4729 dev_warn(tx_ring->dev, |
|
4730 "partial checksum but proto=%x!\n", |
|
4731 first->protocol); |
|
4732 } |
|
4733 break; |
|
4734 } |
|
4735 |
|
4736 switch (l4_hdr) { |
|
4737 case IPPROTO_TCP: |
|
4738 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; |
|
4739 mss_l4len_idx = tcp_hdrlen(skb) << |
|
4740 E1000_ADVTXD_L4LEN_SHIFT; |
|
4741 break; |
|
4742 case IPPROTO_SCTP: |
|
4743 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; |
|
4744 mss_l4len_idx = sizeof(struct sctphdr) << |
|
4745 E1000_ADVTXD_L4LEN_SHIFT; |
|
4746 break; |
|
4747 case IPPROTO_UDP: |
|
4748 mss_l4len_idx = sizeof(struct udphdr) << |
|
4749 E1000_ADVTXD_L4LEN_SHIFT; |
|
4750 break; |
|
4751 default: |
|
4752 if (unlikely(net_ratelimit())) { |
|
4753 dev_warn(tx_ring->dev, |
|
4754 "partial checksum but l4 proto=%x!\n", |
|
4755 l4_hdr); |
|
4756 } |
|
4757 break; |
|
4758 } |
|
4759 |
|
4760 /* update TX checksum flag */ |
|
4761 first->tx_flags |= IGB_TX_FLAGS_CSUM; |
|
4762 } |
|
4763 |
|
4764 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
|
4765 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
|
4766 |
|
4767 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
|
4768 } |
|
4769 |
|
4770 #define IGB_SET_FLAG(_input, _flag, _result) \ |
|
4771 ((_flag <= _result) ? \ |
|
4772 ((u32)(_input & _flag) * (_result / _flag)) : \ |
|
4773 ((u32)(_input & _flag) / (_flag / _result))) |
|
4774 |
|
4775 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) |
|
4776 { |
|
4777 /* set type for advanced descriptor with frame checksum insertion */ |
|
4778 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | |
|
4779 E1000_ADVTXD_DCMD_DEXT | |
|
4780 E1000_ADVTXD_DCMD_IFCS; |
|
4781 |
|
4782 /* set HW vlan bit if vlan is present */ |
|
4783 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, |
|
4784 (E1000_ADVTXD_DCMD_VLE)); |
|
4785 |
|
4786 /* set segmentation bits for TSO */ |
|
4787 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, |
|
4788 (E1000_ADVTXD_DCMD_TSE)); |
|
4789 |
|
4790 /* set timestamp bit if present */ |
|
4791 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, |
|
4792 (E1000_ADVTXD_MAC_TSTAMP)); |
|
4793 |
|
4794 /* insert frame checksum */ |
|
4795 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); |
|
4796 |
|
4797 return cmd_type; |
|
4798 } |
|
4799 |
|
4800 static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
|
4801 union e1000_adv_tx_desc *tx_desc, |
|
4802 u32 tx_flags, unsigned int paylen) |
|
4803 { |
|
4804 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; |
|
4805 |
|
4806 /* 82575 requires a unique index per ring */ |
|
4807 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
|
4808 olinfo_status |= tx_ring->reg_idx << 4; |
|
4809 |
|
4810 /* insert L4 checksum */ |
|
4811 olinfo_status |= IGB_SET_FLAG(tx_flags, |
|
4812 IGB_TX_FLAGS_CSUM, |
|
4813 (E1000_TXD_POPTS_TXSM << 8)); |
|
4814 |
|
4815 /* insert IPv4 checksum */ |
|
4816 olinfo_status |= IGB_SET_FLAG(tx_flags, |
|
4817 IGB_TX_FLAGS_IPV4, |
|
4818 (E1000_TXD_POPTS_IXSM << 8)); |
|
4819 |
|
4820 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
|
4821 } |
|
4822 |
|
4823 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
|
4824 { |
|
4825 struct net_device *netdev = tx_ring->netdev; |
|
4826 |
|
4827 netif_stop_subqueue(netdev, tx_ring->queue_index); |
|
4828 |
|
4829 /* Herbert's original patch had: |
|
4830 * smp_mb__after_netif_stop_queue(); |
|
4831 * but since that doesn't exist yet, just open code it. |
|
4832 */ |
|
4833 smp_mb(); |
|
4834 |
|
4835 /* We need to check again in a case another CPU has just |
|
4836 * made room available. |
|
4837 */ |
|
4838 if (igb_desc_unused(tx_ring) < size) |
|
4839 return -EBUSY; |
|
4840 |
|
4841 /* A reprieve! */ |
|
4842 netif_wake_subqueue(netdev, tx_ring->queue_index); |
|
4843 |
|
4844 u64_stats_update_begin(&tx_ring->tx_syncp2); |
|
4845 tx_ring->tx_stats.restart_queue2++; |
|
4846 u64_stats_update_end(&tx_ring->tx_syncp2); |
|
4847 |
|
4848 return 0; |
|
4849 } |
|
4850 |
|
4851 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
|
4852 { |
|
4853 if (igb_desc_unused(tx_ring) >= size) |
|
4854 return 0; |
|
4855 return __igb_maybe_stop_tx(tx_ring, size); |
|
4856 } |
|
4857 |
|
4858 static void igb_tx_map(struct igb_ring *tx_ring, |
|
4859 struct igb_tx_buffer *first, |
|
4860 const u8 hdr_len) |
|
4861 { |
|
4862 struct sk_buff *skb = first->skb; |
|
4863 struct igb_tx_buffer *tx_buffer; |
|
4864 union e1000_adv_tx_desc *tx_desc; |
|
4865 struct skb_frag_struct *frag; |
|
4866 dma_addr_t dma; |
|
4867 unsigned int data_len, size; |
|
4868 u32 tx_flags = first->tx_flags; |
|
4869 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); |
|
4870 u16 i = tx_ring->next_to_use; |
|
4871 |
|
4872 tx_desc = IGB_TX_DESC(tx_ring, i); |
|
4873 |
|
4874 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); |
|
4875 |
|
4876 size = skb_headlen(skb); |
|
4877 data_len = skb->data_len; |
|
4878 |
|
4879 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
|
4880 |
|
4881 tx_buffer = first; |
|
4882 |
|
4883 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { |
|
4884 if (dma_mapping_error(tx_ring->dev, dma)) |
|
4885 goto dma_error; |
|
4886 |
|
4887 /* record length, and DMA address */ |
|
4888 dma_unmap_len_set(tx_buffer, len, size); |
|
4889 dma_unmap_addr_set(tx_buffer, dma, dma); |
|
4890 |
|
4891 tx_desc->read.buffer_addr = cpu_to_le64(dma); |
|
4892 |
|
4893 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { |
|
4894 tx_desc->read.cmd_type_len = |
|
4895 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); |
|
4896 |
|
4897 i++; |
|
4898 tx_desc++; |
|
4899 if (i == tx_ring->count) { |
|
4900 tx_desc = IGB_TX_DESC(tx_ring, 0); |
|
4901 i = 0; |
|
4902 } |
|
4903 tx_desc->read.olinfo_status = 0; |
|
4904 |
|
4905 dma += IGB_MAX_DATA_PER_TXD; |
|
4906 size -= IGB_MAX_DATA_PER_TXD; |
|
4907 |
|
4908 tx_desc->read.buffer_addr = cpu_to_le64(dma); |
|
4909 } |
|
4910 |
|
4911 if (likely(!data_len)) |
|
4912 break; |
|
4913 |
|
4914 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
|
4915 |
|
4916 i++; |
|
4917 tx_desc++; |
|
4918 if (i == tx_ring->count) { |
|
4919 tx_desc = IGB_TX_DESC(tx_ring, 0); |
|
4920 i = 0; |
|
4921 } |
|
4922 tx_desc->read.olinfo_status = 0; |
|
4923 |
|
4924 size = skb_frag_size(frag); |
|
4925 data_len -= size; |
|
4926 |
|
4927 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, |
|
4928 size, DMA_TO_DEVICE); |
|
4929 |
|
4930 tx_buffer = &tx_ring->tx_buffer_info[i]; |
|
4931 } |
|
4932 |
|
4933 /* write last descriptor with RS and EOP bits */ |
|
4934 cmd_type |= size | IGB_TXD_DCMD; |
|
4935 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); |
|
4936 |
|
4937 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
|
4938 |
|
4939 /* set the timestamp */ |
|
4940 first->time_stamp = jiffies; |
|
4941 |
|
4942 /* Force memory writes to complete before letting h/w know there |
|
4943 * are new descriptors to fetch. (Only applicable for weak-ordered |
|
4944 * memory model archs, such as IA-64). |
|
4945 * |
|
4946 * We also need this memory barrier to make certain all of the |
|
4947 * status bits have been updated before next_to_watch is written. |
|
4948 */ |
|
4949 wmb(); |
|
4950 |
|
4951 /* set next_to_watch value indicating a packet is present */ |
|
4952 first->next_to_watch = tx_desc; |
|
4953 |
|
4954 i++; |
|
4955 if (i == tx_ring->count) |
|
4956 i = 0; |
|
4957 |
|
4958 tx_ring->next_to_use = i; |
|
4959 |
|
4960 /* Make sure there is space in the ring for the next send. */ |
|
4961 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); |
|
4962 |
|
4963 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { |
|
4964 writel(i, tx_ring->tail); |
|
4965 |
|
4966 /* we need this if more than one processor can write to our tail |
|
4967 * at a time, it synchronizes IO on IA64/Altix systems |
|
4968 */ |
|
4969 mmiowb(); |
|
4970 } |
|
4971 return; |
|
4972 |
|
4973 dma_error: |
|
4974 dev_err(tx_ring->dev, "TX DMA map failed\n"); |
|
4975 |
|
4976 /* clear dma mappings for failed tx_buffer_info map */ |
|
4977 for (;;) { |
|
4978 tx_buffer = &tx_ring->tx_buffer_info[i]; |
|
4979 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); |
|
4980 if (tx_buffer == first) |
|
4981 break; |
|
4982 if (i == 0) |
|
4983 i = tx_ring->count; |
|
4984 i--; |
|
4985 } |
|
4986 |
|
4987 tx_ring->next_to_use = i; |
|
4988 } |
|
4989 |
|
4990 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
|
4991 struct igb_ring *tx_ring) |
|
4992 { |
|
4993 struct igb_tx_buffer *first; |
|
4994 int tso; |
|
4995 u32 tx_flags = 0; |
|
4996 u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
|
4997 __be16 protocol = vlan_get_protocol(skb); |
|
4998 u8 hdr_len = 0; |
|
4999 |
|
5000 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, |
|
5001 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, |
|
5002 * + 2 desc gap to keep tail from touching head, |
|
5003 * + 1 desc for context descriptor, |
|
5004 * otherwise try next time |
|
5005 */ |
|
5006 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { |
|
5007 unsigned short f; |
|
5008 |
|
5009 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
|
5010 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
|
5011 } else { |
|
5012 count += skb_shinfo(skb)->nr_frags; |
|
5013 } |
|
5014 |
|
5015 if (igb_maybe_stop_tx(tx_ring, count + 3)) { |
|
5016 /* this is a hard error */ |
|
5017 return NETDEV_TX_BUSY; |
|
5018 } |
|
5019 |
|
5020 /* record the location of the first descriptor for this packet */ |
|
5021 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; |
|
5022 first->skb = skb; |
|
5023 first->bytecount = skb->len; |
|
5024 first->gso_segs = 1; |
|
5025 |
|
5026 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
|
5027 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
|
5028 |
|
5029 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, |
|
5030 &adapter->state)) { |
|
5031 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
|
5032 tx_flags |= IGB_TX_FLAGS_TSTAMP; |
|
5033 |
|
5034 adapter->ptp_tx_skb = skb_get(skb); |
|
5035 adapter->ptp_tx_start = jiffies; |
|
5036 if (adapter->hw.mac.type == e1000_82576) |
|
5037 schedule_work(&adapter->ptp_tx_work); |
|
5038 } |
|
5039 } |
|
5040 |
|
5041 skb_tx_timestamp(skb); |
|
5042 |
|
5043 if (vlan_tx_tag_present(skb)) { |
|
5044 tx_flags |= IGB_TX_FLAGS_VLAN; |
|
5045 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); |
|
5046 } |
|
5047 |
|
5048 /* record initial flags and protocol */ |
|
5049 first->tx_flags = tx_flags; |
|
5050 first->protocol = protocol; |
|
5051 |
|
5052 tso = igb_tso(tx_ring, first, &hdr_len); |
|
5053 if (tso < 0) |
|
5054 goto out_drop; |
|
5055 else if (!tso) |
|
5056 igb_tx_csum(tx_ring, first); |
|
5057 |
|
5058 igb_tx_map(tx_ring, first, hdr_len); |
|
5059 |
|
5060 return NETDEV_TX_OK; |
|
5061 |
|
5062 out_drop: |
|
5063 igb_unmap_and_free_tx_resource(tx_ring, first); |
|
5064 |
|
5065 return NETDEV_TX_OK; |
|
5066 } |
|
5067 |
|
5068 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
|
5069 struct sk_buff *skb) |
|
5070 { |
|
5071 unsigned int r_idx = skb->queue_mapping; |
|
5072 |
|
5073 if (r_idx >= adapter->num_tx_queues) |
|
5074 r_idx = r_idx % adapter->num_tx_queues; |
|
5075 |
|
5076 return adapter->tx_ring[r_idx]; |
|
5077 } |
|
5078 |
|
5079 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
|
5080 struct net_device *netdev) |
|
5081 { |
|
5082 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5083 |
|
5084 if (test_bit(__IGB_DOWN, &adapter->state)) { |
|
5085 dev_kfree_skb_any(skb); |
|
5086 return NETDEV_TX_OK; |
|
5087 } |
|
5088 |
|
5089 if (skb->len <= 0) { |
|
5090 dev_kfree_skb_any(skb); |
|
5091 return NETDEV_TX_OK; |
|
5092 } |
|
5093 |
|
5094 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb |
|
5095 * in order to meet this minimum size requirement. |
|
5096 */ |
|
5097 if (unlikely(skb->len < 17)) { |
|
5098 if (skb_pad(skb, 17 - skb->len)) |
|
5099 return NETDEV_TX_OK; |
|
5100 skb->len = 17; |
|
5101 skb_set_tail_pointer(skb, 17); |
|
5102 } |
|
5103 |
|
5104 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
|
5105 } |
|
5106 |
|
5107 /** |
|
5108 * igb_tx_timeout - Respond to a Tx Hang |
|
5109 * @netdev: network interface device structure |
|
5110 **/ |
|
5111 static void igb_tx_timeout(struct net_device *netdev) |
|
5112 { |
|
5113 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5114 struct e1000_hw *hw = &adapter->hw; |
|
5115 |
|
5116 /* Do the reset outside of interrupt context */ |
|
5117 adapter->tx_timeout_count++; |
|
5118 |
|
5119 if (hw->mac.type >= e1000_82580) |
|
5120 hw->dev_spec._82575.global_device_reset = true; |
|
5121 |
|
5122 schedule_work(&adapter->reset_task); |
|
5123 wr32(E1000_EICS, |
|
5124 (adapter->eims_enable_mask & ~adapter->eims_other)); |
|
5125 } |
|
5126 |
|
5127 static void igb_reset_task(struct work_struct *work) |
|
5128 { |
|
5129 struct igb_adapter *adapter; |
|
5130 adapter = container_of(work, struct igb_adapter, reset_task); |
|
5131 |
|
5132 igb_dump(adapter); |
|
5133 netdev_err(adapter->netdev, "Reset adapter\n"); |
|
5134 igb_reinit_locked(adapter); |
|
5135 } |
|
5136 |
|
5137 /** |
|
5138 * igb_get_stats64 - Get System Network Statistics |
|
5139 * @netdev: network interface device structure |
|
5140 * @stats: rtnl_link_stats64 pointer |
|
5141 **/ |
|
5142 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
|
5143 struct rtnl_link_stats64 *stats) |
|
5144 { |
|
5145 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5146 |
|
5147 spin_lock(&adapter->stats64_lock); |
|
5148 igb_update_stats(adapter, &adapter->stats64); |
|
5149 memcpy(stats, &adapter->stats64, sizeof(*stats)); |
|
5150 spin_unlock(&adapter->stats64_lock); |
|
5151 |
|
5152 return stats; |
|
5153 } |
|
5154 |
|
5155 /** |
|
5156 * igb_change_mtu - Change the Maximum Transfer Unit |
|
5157 * @netdev: network interface device structure |
|
5158 * @new_mtu: new value for maximum frame size |
|
5159 * |
|
5160 * Returns 0 on success, negative on failure |
|
5161 **/ |
|
5162 static int igb_change_mtu(struct net_device *netdev, int new_mtu) |
|
5163 { |
|
5164 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5165 struct pci_dev *pdev = adapter->pdev; |
|
5166 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
|
5167 |
|
5168 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
|
5169 dev_err(&pdev->dev, "Invalid MTU setting\n"); |
|
5170 return -EINVAL; |
|
5171 } |
|
5172 |
|
5173 #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
|
5174 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
|
5175 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
|
5176 return -EINVAL; |
|
5177 } |
|
5178 |
|
5179 /* adjust max frame to be at least the size of a standard frame */ |
|
5180 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) |
|
5181 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; |
|
5182 |
|
5183 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
|
5184 usleep_range(1000, 2000); |
|
5185 |
|
5186 /* igb_down has a dependency on max_frame_size */ |
|
5187 adapter->max_frame_size = max_frame; |
|
5188 |
|
5189 if (netif_running(netdev)) |
|
5190 igb_down(adapter); |
|
5191 |
|
5192 dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
|
5193 netdev->mtu, new_mtu); |
|
5194 netdev->mtu = new_mtu; |
|
5195 |
|
5196 if (netif_running(netdev)) |
|
5197 igb_up(adapter); |
|
5198 else |
|
5199 igb_reset(adapter); |
|
5200 |
|
5201 clear_bit(__IGB_RESETTING, &adapter->state); |
|
5202 |
|
5203 return 0; |
|
5204 } |
|
5205 |
|
5206 /** |
|
5207 * igb_update_stats - Update the board statistics counters |
|
5208 * @adapter: board private structure |
|
5209 **/ |
|
5210 void igb_update_stats(struct igb_adapter *adapter, |
|
5211 struct rtnl_link_stats64 *net_stats) |
|
5212 { |
|
5213 struct e1000_hw *hw = &adapter->hw; |
|
5214 struct pci_dev *pdev = adapter->pdev; |
|
5215 u32 reg, mpc; |
|
5216 int i; |
|
5217 u64 bytes, packets; |
|
5218 unsigned int start; |
|
5219 u64 _bytes, _packets; |
|
5220 |
|
5221 /* Prevent stats update while adapter is being reset, or if the pci |
|
5222 * connection is down. |
|
5223 */ |
|
5224 if (adapter->link_speed == 0) |
|
5225 return; |
|
5226 if (pci_channel_offline(pdev)) |
|
5227 return; |
|
5228 |
|
5229 bytes = 0; |
|
5230 packets = 0; |
|
5231 |
|
5232 rcu_read_lock(); |
|
5233 for (i = 0; i < adapter->num_rx_queues; i++) { |
|
5234 struct igb_ring *ring = adapter->rx_ring[i]; |
|
5235 u32 rqdpc = rd32(E1000_RQDPC(i)); |
|
5236 if (hw->mac.type >= e1000_i210) |
|
5237 wr32(E1000_RQDPC(i), 0); |
|
5238 |
|
5239 if (rqdpc) { |
|
5240 ring->rx_stats.drops += rqdpc; |
|
5241 net_stats->rx_fifo_errors += rqdpc; |
|
5242 } |
|
5243 |
|
5244 do { |
|
5245 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); |
|
5246 _bytes = ring->rx_stats.bytes; |
|
5247 _packets = ring->rx_stats.packets; |
|
5248 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); |
|
5249 bytes += _bytes; |
|
5250 packets += _packets; |
|
5251 } |
|
5252 |
|
5253 net_stats->rx_bytes = bytes; |
|
5254 net_stats->rx_packets = packets; |
|
5255 |
|
5256 bytes = 0; |
|
5257 packets = 0; |
|
5258 for (i = 0; i < adapter->num_tx_queues; i++) { |
|
5259 struct igb_ring *ring = adapter->tx_ring[i]; |
|
5260 do { |
|
5261 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); |
|
5262 _bytes = ring->tx_stats.bytes; |
|
5263 _packets = ring->tx_stats.packets; |
|
5264 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); |
|
5265 bytes += _bytes; |
|
5266 packets += _packets; |
|
5267 } |
|
5268 net_stats->tx_bytes = bytes; |
|
5269 net_stats->tx_packets = packets; |
|
5270 rcu_read_unlock(); |
|
5271 |
|
5272 /* read stats registers */ |
|
5273 adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
|
5274 adapter->stats.gprc += rd32(E1000_GPRC); |
|
5275 adapter->stats.gorc += rd32(E1000_GORCL); |
|
5276 rd32(E1000_GORCH); /* clear GORCL */ |
|
5277 adapter->stats.bprc += rd32(E1000_BPRC); |
|
5278 adapter->stats.mprc += rd32(E1000_MPRC); |
|
5279 adapter->stats.roc += rd32(E1000_ROC); |
|
5280 |
|
5281 adapter->stats.prc64 += rd32(E1000_PRC64); |
|
5282 adapter->stats.prc127 += rd32(E1000_PRC127); |
|
5283 adapter->stats.prc255 += rd32(E1000_PRC255); |
|
5284 adapter->stats.prc511 += rd32(E1000_PRC511); |
|
5285 adapter->stats.prc1023 += rd32(E1000_PRC1023); |
|
5286 adapter->stats.prc1522 += rd32(E1000_PRC1522); |
|
5287 adapter->stats.symerrs += rd32(E1000_SYMERRS); |
|
5288 adapter->stats.sec += rd32(E1000_SEC); |
|
5289 |
|
5290 mpc = rd32(E1000_MPC); |
|
5291 adapter->stats.mpc += mpc; |
|
5292 net_stats->rx_fifo_errors += mpc; |
|
5293 adapter->stats.scc += rd32(E1000_SCC); |
|
5294 adapter->stats.ecol += rd32(E1000_ECOL); |
|
5295 adapter->stats.mcc += rd32(E1000_MCC); |
|
5296 adapter->stats.latecol += rd32(E1000_LATECOL); |
|
5297 adapter->stats.dc += rd32(E1000_DC); |
|
5298 adapter->stats.rlec += rd32(E1000_RLEC); |
|
5299 adapter->stats.xonrxc += rd32(E1000_XONRXC); |
|
5300 adapter->stats.xontxc += rd32(E1000_XONTXC); |
|
5301 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); |
|
5302 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); |
|
5303 adapter->stats.fcruc += rd32(E1000_FCRUC); |
|
5304 adapter->stats.gptc += rd32(E1000_GPTC); |
|
5305 adapter->stats.gotc += rd32(E1000_GOTCL); |
|
5306 rd32(E1000_GOTCH); /* clear GOTCL */ |
|
5307 adapter->stats.rnbc += rd32(E1000_RNBC); |
|
5308 adapter->stats.ruc += rd32(E1000_RUC); |
|
5309 adapter->stats.rfc += rd32(E1000_RFC); |
|
5310 adapter->stats.rjc += rd32(E1000_RJC); |
|
5311 adapter->stats.tor += rd32(E1000_TORH); |
|
5312 adapter->stats.tot += rd32(E1000_TOTH); |
|
5313 adapter->stats.tpr += rd32(E1000_TPR); |
|
5314 |
|
5315 adapter->stats.ptc64 += rd32(E1000_PTC64); |
|
5316 adapter->stats.ptc127 += rd32(E1000_PTC127); |
|
5317 adapter->stats.ptc255 += rd32(E1000_PTC255); |
|
5318 adapter->stats.ptc511 += rd32(E1000_PTC511); |
|
5319 adapter->stats.ptc1023 += rd32(E1000_PTC1023); |
|
5320 adapter->stats.ptc1522 += rd32(E1000_PTC1522); |
|
5321 |
|
5322 adapter->stats.mptc += rd32(E1000_MPTC); |
|
5323 adapter->stats.bptc += rd32(E1000_BPTC); |
|
5324 |
|
5325 adapter->stats.tpt += rd32(E1000_TPT); |
|
5326 adapter->stats.colc += rd32(E1000_COLC); |
|
5327 |
|
5328 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); |
|
5329 /* read internal phy specific stats */ |
|
5330 reg = rd32(E1000_CTRL_EXT); |
|
5331 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { |
|
5332 adapter->stats.rxerrc += rd32(E1000_RXERRC); |
|
5333 |
|
5334 /* this stat has invalid values on i210/i211 */ |
|
5335 if ((hw->mac.type != e1000_i210) && |
|
5336 (hw->mac.type != e1000_i211)) |
|
5337 adapter->stats.tncrs += rd32(E1000_TNCRS); |
|
5338 } |
|
5339 |
|
5340 adapter->stats.tsctc += rd32(E1000_TSCTC); |
|
5341 adapter->stats.tsctfc += rd32(E1000_TSCTFC); |
|
5342 |
|
5343 adapter->stats.iac += rd32(E1000_IAC); |
|
5344 adapter->stats.icrxoc += rd32(E1000_ICRXOC); |
|
5345 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); |
|
5346 adapter->stats.icrxatc += rd32(E1000_ICRXATC); |
|
5347 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); |
|
5348 adapter->stats.ictxatc += rd32(E1000_ICTXATC); |
|
5349 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); |
|
5350 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); |
|
5351 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); |
|
5352 |
|
5353 /* Fill out the OS statistics structure */ |
|
5354 net_stats->multicast = adapter->stats.mprc; |
|
5355 net_stats->collisions = adapter->stats.colc; |
|
5356 |
|
5357 /* Rx Errors */ |
|
5358 |
|
5359 /* RLEC on some newer hardware can be incorrect so build |
|
5360 * our own version based on RUC and ROC |
|
5361 */ |
|
5362 net_stats->rx_errors = adapter->stats.rxerrc + |
|
5363 adapter->stats.crcerrs + adapter->stats.algnerrc + |
|
5364 adapter->stats.ruc + adapter->stats.roc + |
|
5365 adapter->stats.cexterr; |
|
5366 net_stats->rx_length_errors = adapter->stats.ruc + |
|
5367 adapter->stats.roc; |
|
5368 net_stats->rx_crc_errors = adapter->stats.crcerrs; |
|
5369 net_stats->rx_frame_errors = adapter->stats.algnerrc; |
|
5370 net_stats->rx_missed_errors = adapter->stats.mpc; |
|
5371 |
|
5372 /* Tx Errors */ |
|
5373 net_stats->tx_errors = adapter->stats.ecol + |
|
5374 adapter->stats.latecol; |
|
5375 net_stats->tx_aborted_errors = adapter->stats.ecol; |
|
5376 net_stats->tx_window_errors = adapter->stats.latecol; |
|
5377 net_stats->tx_carrier_errors = adapter->stats.tncrs; |
|
5378 |
|
5379 /* Tx Dropped needs to be maintained elsewhere */ |
|
5380 |
|
5381 /* Management Stats */ |
|
5382 adapter->stats.mgptc += rd32(E1000_MGTPTC); |
|
5383 adapter->stats.mgprc += rd32(E1000_MGTPRC); |
|
5384 adapter->stats.mgpdc += rd32(E1000_MGTPDC); |
|
5385 |
|
5386 /* OS2BMC Stats */ |
|
5387 reg = rd32(E1000_MANC); |
|
5388 if (reg & E1000_MANC_EN_BMC2OS) { |
|
5389 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); |
|
5390 adapter->stats.o2bspc += rd32(E1000_O2BSPC); |
|
5391 adapter->stats.b2ospc += rd32(E1000_B2OSPC); |
|
5392 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); |
|
5393 } |
|
5394 } |
|
5395 |
|
5396 static irqreturn_t igb_msix_other(int irq, void *data) |
|
5397 { |
|
5398 struct igb_adapter *adapter = data; |
|
5399 struct e1000_hw *hw = &adapter->hw; |
|
5400 u32 icr = rd32(E1000_ICR); |
|
5401 /* reading ICR causes bit 31 of EICR to be cleared */ |
|
5402 |
|
5403 if (icr & E1000_ICR_DRSTA) |
|
5404 schedule_work(&adapter->reset_task); |
|
5405 |
|
5406 if (icr & E1000_ICR_DOUTSYNC) { |
|
5407 /* HW is reporting DMA is out of sync */ |
|
5408 adapter->stats.doosync++; |
|
5409 /* The DMA Out of Sync is also indication of a spoof event |
|
5410 * in IOV mode. Check the Wrong VM Behavior register to |
|
5411 * see if it is really a spoof event. |
|
5412 */ |
|
5413 igb_check_wvbr(adapter); |
|
5414 } |
|
5415 |
|
5416 /* Check for a mailbox event */ |
|
5417 if (icr & E1000_ICR_VMMB) |
|
5418 igb_msg_task(adapter); |
|
5419 |
|
5420 if (icr & E1000_ICR_LSC) { |
|
5421 hw->mac.get_link_status = 1; |
|
5422 /* guard against interrupt when we're going down */ |
|
5423 if (!test_bit(__IGB_DOWN, &adapter->state)) |
|
5424 mod_timer(&adapter->watchdog_timer, jiffies + 1); |
|
5425 } |
|
5426 |
|
5427 if (icr & E1000_ICR_TS) { |
|
5428 u32 tsicr = rd32(E1000_TSICR); |
|
5429 |
|
5430 if (tsicr & E1000_TSICR_TXTS) { |
|
5431 /* acknowledge the interrupt */ |
|
5432 wr32(E1000_TSICR, E1000_TSICR_TXTS); |
|
5433 /* retrieve hardware timestamp */ |
|
5434 schedule_work(&adapter->ptp_tx_work); |
|
5435 } |
|
5436 } |
|
5437 |
|
5438 wr32(E1000_EIMS, adapter->eims_other); |
|
5439 |
|
5440 return IRQ_HANDLED; |
|
5441 } |
|
5442 |
|
5443 static void igb_write_itr(struct igb_q_vector *q_vector) |
|
5444 { |
|
5445 struct igb_adapter *adapter = q_vector->adapter; |
|
5446 u32 itr_val = q_vector->itr_val & 0x7FFC; |
|
5447 |
|
5448 if (!q_vector->set_itr) |
|
5449 return; |
|
5450 |
|
5451 if (!itr_val) |
|
5452 itr_val = 0x4; |
|
5453 |
|
5454 if (adapter->hw.mac.type == e1000_82575) |
|
5455 itr_val |= itr_val << 16; |
|
5456 else |
|
5457 itr_val |= E1000_EITR_CNT_IGNR; |
|
5458 |
|
5459 writel(itr_val, q_vector->itr_register); |
|
5460 q_vector->set_itr = 0; |
|
5461 } |
|
5462 |
|
5463 static irqreturn_t igb_msix_ring(int irq, void *data) |
|
5464 { |
|
5465 struct igb_q_vector *q_vector = data; |
|
5466 |
|
5467 /* Write the ITR value calculated from the previous interrupt. */ |
|
5468 igb_write_itr(q_vector); |
|
5469 |
|
5470 napi_schedule(&q_vector->napi); |
|
5471 |
|
5472 return IRQ_HANDLED; |
|
5473 } |
|
5474 |
|
5475 #ifdef CONFIG_IGB_DCA |
|
5476 static void igb_update_tx_dca(struct igb_adapter *adapter, |
|
5477 struct igb_ring *tx_ring, |
|
5478 int cpu) |
|
5479 { |
|
5480 struct e1000_hw *hw = &adapter->hw; |
|
5481 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
|
5482 |
|
5483 if (hw->mac.type != e1000_82575) |
|
5484 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; |
|
5485 |
|
5486 /* We can enable relaxed ordering for reads, but not writes when |
|
5487 * DCA is enabled. This is due to a known issue in some chipsets |
|
5488 * which will cause the DCA tag to be cleared. |
|
5489 */ |
|
5490 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | |
|
5491 E1000_DCA_TXCTRL_DATA_RRO_EN | |
|
5492 E1000_DCA_TXCTRL_DESC_DCA_EN; |
|
5493 |
|
5494 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); |
|
5495 } |
|
5496 |
|
5497 static void igb_update_rx_dca(struct igb_adapter *adapter, |
|
5498 struct igb_ring *rx_ring, |
|
5499 int cpu) |
|
5500 { |
|
5501 struct e1000_hw *hw = &adapter->hw; |
|
5502 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); |
|
5503 |
|
5504 if (hw->mac.type != e1000_82575) |
|
5505 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; |
|
5506 |
|
5507 /* We can enable relaxed ordering for reads, but not writes when |
|
5508 * DCA is enabled. This is due to a known issue in some chipsets |
|
5509 * which will cause the DCA tag to be cleared. |
|
5510 */ |
|
5511 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | |
|
5512 E1000_DCA_RXCTRL_DESC_DCA_EN; |
|
5513 |
|
5514 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); |
|
5515 } |
|
5516 |
|
5517 static void igb_update_dca(struct igb_q_vector *q_vector) |
|
5518 { |
|
5519 struct igb_adapter *adapter = q_vector->adapter; |
|
5520 int cpu = get_cpu(); |
|
5521 |
|
5522 if (q_vector->cpu == cpu) |
|
5523 goto out_no_update; |
|
5524 |
|
5525 if (q_vector->tx.ring) |
|
5526 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); |
|
5527 |
|
5528 if (q_vector->rx.ring) |
|
5529 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); |
|
5530 |
|
5531 q_vector->cpu = cpu; |
|
5532 out_no_update: |
|
5533 put_cpu(); |
|
5534 } |
|
5535 |
|
5536 static void igb_setup_dca(struct igb_adapter *adapter) |
|
5537 { |
|
5538 struct e1000_hw *hw = &adapter->hw; |
|
5539 int i; |
|
5540 |
|
5541 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
|
5542 return; |
|
5543 |
|
5544 /* Always use CB2 mode, difference is masked in the CB driver. */ |
|
5545 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
|
5546 |
|
5547 for (i = 0; i < adapter->num_q_vectors; i++) { |
|
5548 adapter->q_vector[i]->cpu = -1; |
|
5549 igb_update_dca(adapter->q_vector[i]); |
|
5550 } |
|
5551 } |
|
5552 |
|
5553 static int __igb_notify_dca(struct device *dev, void *data) |
|
5554 { |
|
5555 struct net_device *netdev = dev_get_drvdata(dev); |
|
5556 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5557 struct pci_dev *pdev = adapter->pdev; |
|
5558 struct e1000_hw *hw = &adapter->hw; |
|
5559 unsigned long event = *(unsigned long *)data; |
|
5560 |
|
5561 switch (event) { |
|
5562 case DCA_PROVIDER_ADD: |
|
5563 /* if already enabled, don't do it again */ |
|
5564 if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
|
5565 break; |
|
5566 if (dca_add_requester(dev) == 0) { |
|
5567 adapter->flags |= IGB_FLAG_DCA_ENABLED; |
|
5568 dev_info(&pdev->dev, "DCA enabled\n"); |
|
5569 igb_setup_dca(adapter); |
|
5570 break; |
|
5571 } |
|
5572 /* Fall Through since DCA is disabled. */ |
|
5573 case DCA_PROVIDER_REMOVE: |
|
5574 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
|
5575 /* without this a class_device is left |
|
5576 * hanging around in the sysfs model |
|
5577 */ |
|
5578 dca_remove_requester(dev); |
|
5579 dev_info(&pdev->dev, "DCA disabled\n"); |
|
5580 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
|
5581 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
|
5582 } |
|
5583 break; |
|
5584 } |
|
5585 |
|
5586 return 0; |
|
5587 } |
|
5588 |
|
5589 static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
|
5590 void *p) |
|
5591 { |
|
5592 int ret_val; |
|
5593 |
|
5594 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, |
|
5595 __igb_notify_dca); |
|
5596 |
|
5597 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; |
|
5598 } |
|
5599 #endif /* CONFIG_IGB_DCA */ |
|
5600 |
|
5601 #ifdef CONFIG_PCI_IOV |
|
5602 static int igb_vf_configure(struct igb_adapter *adapter, int vf) |
|
5603 { |
|
5604 unsigned char mac_addr[ETH_ALEN]; |
|
5605 |
|
5606 eth_zero_addr(mac_addr); |
|
5607 igb_set_vf_mac(adapter, vf, mac_addr); |
|
5608 |
|
5609 /* By default spoof check is enabled for all VFs */ |
|
5610 adapter->vf_data[vf].spoofchk_enabled = true; |
|
5611 |
|
5612 return 0; |
|
5613 } |
|
5614 |
|
5615 #endif |
|
5616 static void igb_ping_all_vfs(struct igb_adapter *adapter) |
|
5617 { |
|
5618 struct e1000_hw *hw = &adapter->hw; |
|
5619 u32 ping; |
|
5620 int i; |
|
5621 |
|
5622 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { |
|
5623 ping = E1000_PF_CONTROL_MSG; |
|
5624 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
|
5625 ping |= E1000_VT_MSGTYPE_CTS; |
|
5626 igb_write_mbx(hw, &ping, 1, i); |
|
5627 } |
|
5628 } |
|
5629 |
|
5630 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
|
5631 { |
|
5632 struct e1000_hw *hw = &adapter->hw; |
|
5633 u32 vmolr = rd32(E1000_VMOLR(vf)); |
|
5634 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
|
5635 |
|
5636 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
|
5637 IGB_VF_FLAG_MULTI_PROMISC); |
|
5638 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); |
|
5639 |
|
5640 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { |
|
5641 vmolr |= E1000_VMOLR_MPME; |
|
5642 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
|
5643 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
|
5644 } else { |
|
5645 /* if we have hashes and we are clearing a multicast promisc |
|
5646 * flag we need to write the hashes to the MTA as this step |
|
5647 * was previously skipped |
|
5648 */ |
|
5649 if (vf_data->num_vf_mc_hashes > 30) { |
|
5650 vmolr |= E1000_VMOLR_MPME; |
|
5651 } else if (vf_data->num_vf_mc_hashes) { |
|
5652 int j; |
|
5653 |
|
5654 vmolr |= E1000_VMOLR_ROMPE; |
|
5655 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) |
|
5656 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); |
|
5657 } |
|
5658 } |
|
5659 |
|
5660 wr32(E1000_VMOLR(vf), vmolr); |
|
5661 |
|
5662 /* there are flags left unprocessed, likely not supported */ |
|
5663 if (*msgbuf & E1000_VT_MSGINFO_MASK) |
|
5664 return -EINVAL; |
|
5665 |
|
5666 return 0; |
|
5667 } |
|
5668 |
|
5669 static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
|
5670 u32 *msgbuf, u32 vf) |
|
5671 { |
|
5672 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; |
|
5673 u16 *hash_list = (u16 *)&msgbuf[1]; |
|
5674 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
|
5675 int i; |
|
5676 |
|
5677 /* salt away the number of multicast addresses assigned |
|
5678 * to this VF for later use to restore when the PF multi cast |
|
5679 * list changes |
|
5680 */ |
|
5681 vf_data->num_vf_mc_hashes = n; |
|
5682 |
|
5683 /* only up to 30 hash values supported */ |
|
5684 if (n > 30) |
|
5685 n = 30; |
|
5686 |
|
5687 /* store the hashes for later use */ |
|
5688 for (i = 0; i < n; i++) |
|
5689 vf_data->vf_mc_hashes[i] = hash_list[i]; |
|
5690 |
|
5691 /* Flush and reset the mta with the new values */ |
|
5692 igb_set_rx_mode(adapter->netdev); |
|
5693 |
|
5694 return 0; |
|
5695 } |
|
5696 |
|
5697 static void igb_restore_vf_multicasts(struct igb_adapter *adapter) |
|
5698 { |
|
5699 struct e1000_hw *hw = &adapter->hw; |
|
5700 struct vf_data_storage *vf_data; |
|
5701 int i, j; |
|
5702 |
|
5703 for (i = 0; i < adapter->vfs_allocated_count; i++) { |
|
5704 u32 vmolr = rd32(E1000_VMOLR(i)); |
|
5705 |
|
5706 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); |
|
5707 |
|
5708 vf_data = &adapter->vf_data[i]; |
|
5709 |
|
5710 if ((vf_data->num_vf_mc_hashes > 30) || |
|
5711 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { |
|
5712 vmolr |= E1000_VMOLR_MPME; |
|
5713 } else if (vf_data->num_vf_mc_hashes) { |
|
5714 vmolr |= E1000_VMOLR_ROMPE; |
|
5715 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) |
|
5716 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); |
|
5717 } |
|
5718 wr32(E1000_VMOLR(i), vmolr); |
|
5719 } |
|
5720 } |
|
5721 |
|
5722 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) |
|
5723 { |
|
5724 struct e1000_hw *hw = &adapter->hw; |
|
5725 u32 pool_mask, reg, vid; |
|
5726 int i; |
|
5727 |
|
5728 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); |
|
5729 |
|
5730 /* Find the vlan filter for this id */ |
|
5731 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { |
|
5732 reg = rd32(E1000_VLVF(i)); |
|
5733 |
|
5734 /* remove the vf from the pool */ |
|
5735 reg &= ~pool_mask; |
|
5736 |
|
5737 /* if pool is empty then remove entry from vfta */ |
|
5738 if (!(reg & E1000_VLVF_POOLSEL_MASK) && |
|
5739 (reg & E1000_VLVF_VLANID_ENABLE)) { |
|
5740 reg = 0; |
|
5741 vid = reg & E1000_VLVF_VLANID_MASK; |
|
5742 igb_vfta_set(hw, vid, false); |
|
5743 } |
|
5744 |
|
5745 wr32(E1000_VLVF(i), reg); |
|
5746 } |
|
5747 |
|
5748 adapter->vf_data[vf].vlans_enabled = 0; |
|
5749 } |
|
5750 |
|
5751 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) |
|
5752 { |
|
5753 struct e1000_hw *hw = &adapter->hw; |
|
5754 u32 reg, i; |
|
5755 |
|
5756 /* The vlvf table only exists on 82576 hardware and newer */ |
|
5757 if (hw->mac.type < e1000_82576) |
|
5758 return -1; |
|
5759 |
|
5760 /* we only need to do this if VMDq is enabled */ |
|
5761 if (!adapter->vfs_allocated_count) |
|
5762 return -1; |
|
5763 |
|
5764 /* Find the vlan filter for this id */ |
|
5765 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { |
|
5766 reg = rd32(E1000_VLVF(i)); |
|
5767 if ((reg & E1000_VLVF_VLANID_ENABLE) && |
|
5768 vid == (reg & E1000_VLVF_VLANID_MASK)) |
|
5769 break; |
|
5770 } |
|
5771 |
|
5772 if (add) { |
|
5773 if (i == E1000_VLVF_ARRAY_SIZE) { |
|
5774 /* Did not find a matching VLAN ID entry that was |
|
5775 * enabled. Search for a free filter entry, i.e. |
|
5776 * one without the enable bit set |
|
5777 */ |
|
5778 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { |
|
5779 reg = rd32(E1000_VLVF(i)); |
|
5780 if (!(reg & E1000_VLVF_VLANID_ENABLE)) |
|
5781 break; |
|
5782 } |
|
5783 } |
|
5784 if (i < E1000_VLVF_ARRAY_SIZE) { |
|
5785 /* Found an enabled/available entry */ |
|
5786 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); |
|
5787 |
|
5788 /* if !enabled we need to set this up in vfta */ |
|
5789 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { |
|
5790 /* add VID to filter table */ |
|
5791 igb_vfta_set(hw, vid, true); |
|
5792 reg |= E1000_VLVF_VLANID_ENABLE; |
|
5793 } |
|
5794 reg &= ~E1000_VLVF_VLANID_MASK; |
|
5795 reg |= vid; |
|
5796 wr32(E1000_VLVF(i), reg); |
|
5797 |
|
5798 /* do not modify RLPML for PF devices */ |
|
5799 if (vf >= adapter->vfs_allocated_count) |
|
5800 return 0; |
|
5801 |
|
5802 if (!adapter->vf_data[vf].vlans_enabled) { |
|
5803 u32 size; |
|
5804 |
|
5805 reg = rd32(E1000_VMOLR(vf)); |
|
5806 size = reg & E1000_VMOLR_RLPML_MASK; |
|
5807 size += 4; |
|
5808 reg &= ~E1000_VMOLR_RLPML_MASK; |
|
5809 reg |= size; |
|
5810 wr32(E1000_VMOLR(vf), reg); |
|
5811 } |
|
5812 |
|
5813 adapter->vf_data[vf].vlans_enabled++; |
|
5814 } |
|
5815 } else { |
|
5816 if (i < E1000_VLVF_ARRAY_SIZE) { |
|
5817 /* remove vf from the pool */ |
|
5818 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); |
|
5819 /* if pool is empty then remove entry from vfta */ |
|
5820 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { |
|
5821 reg = 0; |
|
5822 igb_vfta_set(hw, vid, false); |
|
5823 } |
|
5824 wr32(E1000_VLVF(i), reg); |
|
5825 |
|
5826 /* do not modify RLPML for PF devices */ |
|
5827 if (vf >= adapter->vfs_allocated_count) |
|
5828 return 0; |
|
5829 |
|
5830 adapter->vf_data[vf].vlans_enabled--; |
|
5831 if (!adapter->vf_data[vf].vlans_enabled) { |
|
5832 u32 size; |
|
5833 |
|
5834 reg = rd32(E1000_VMOLR(vf)); |
|
5835 size = reg & E1000_VMOLR_RLPML_MASK; |
|
5836 size -= 4; |
|
5837 reg &= ~E1000_VMOLR_RLPML_MASK; |
|
5838 reg |= size; |
|
5839 wr32(E1000_VMOLR(vf), reg); |
|
5840 } |
|
5841 } |
|
5842 } |
|
5843 return 0; |
|
5844 } |
|
5845 |
|
5846 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) |
|
5847 { |
|
5848 struct e1000_hw *hw = &adapter->hw; |
|
5849 |
|
5850 if (vid) |
|
5851 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); |
|
5852 else |
|
5853 wr32(E1000_VMVIR(vf), 0); |
|
5854 } |
|
5855 |
|
5856 static int igb_ndo_set_vf_vlan(struct net_device *netdev, |
|
5857 int vf, u16 vlan, u8 qos) |
|
5858 { |
|
5859 int err = 0; |
|
5860 struct igb_adapter *adapter = netdev_priv(netdev); |
|
5861 |
|
5862 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) |
|
5863 return -EINVAL; |
|
5864 if (vlan || qos) { |
|
5865 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); |
|
5866 if (err) |
|
5867 goto out; |
|
5868 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); |
|
5869 igb_set_vmolr(adapter, vf, !vlan); |
|
5870 adapter->vf_data[vf].pf_vlan = vlan; |
|
5871 adapter->vf_data[vf].pf_qos = qos; |
|
5872 dev_info(&adapter->pdev->dev, |
|
5873 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); |
|
5874 if (test_bit(__IGB_DOWN, &adapter->state)) { |
|
5875 dev_warn(&adapter->pdev->dev, |
|
5876 "The VF VLAN has been set, but the PF device is not up.\n"); |
|
5877 dev_warn(&adapter->pdev->dev, |
|
5878 "Bring the PF device up before attempting to use the VF device.\n"); |
|
5879 } |
|
5880 } else { |
|
5881 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, |
|
5882 false, vf); |
|
5883 igb_set_vmvir(adapter, vlan, vf); |
|
5884 igb_set_vmolr(adapter, vf, true); |
|
5885 adapter->vf_data[vf].pf_vlan = 0; |
|
5886 adapter->vf_data[vf].pf_qos = 0; |
|
5887 } |
|
5888 out: |
|
5889 return err; |
|
5890 } |
|
5891 |
|
5892 static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) |
|
5893 { |
|
5894 struct e1000_hw *hw = &adapter->hw; |
|
5895 int i; |
|
5896 u32 reg; |
|
5897 |
|
5898 /* Find the vlan filter for this id */ |
|
5899 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { |
|
5900 reg = rd32(E1000_VLVF(i)); |
|
5901 if ((reg & E1000_VLVF_VLANID_ENABLE) && |
|
5902 vid == (reg & E1000_VLVF_VLANID_MASK)) |
|
5903 break; |
|
5904 } |
|
5905 |
|
5906 if (i >= E1000_VLVF_ARRAY_SIZE) |
|
5907 i = -1; |
|
5908 |
|
5909 return i; |
|
5910 } |
|
5911 |
|
5912 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
|
5913 { |
|
5914 struct e1000_hw *hw = &adapter->hw; |
|
5915 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; |
|
5916 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); |
|
5917 int err = 0; |
|
5918 |
|
5919 /* If in promiscuous mode we need to make sure the PF also has |
|
5920 * the VLAN filter set. |
|
5921 */ |
|
5922 if (add && (adapter->netdev->flags & IFF_PROMISC)) |
|
5923 err = igb_vlvf_set(adapter, vid, add, |
|
5924 adapter->vfs_allocated_count); |
|
5925 if (err) |
|
5926 goto out; |
|
5927 |
|
5928 err = igb_vlvf_set(adapter, vid, add, vf); |
|
5929 |
|
5930 if (err) |
|
5931 goto out; |
|
5932 |
|
5933 /* Go through all the checks to see if the VLAN filter should |
|
5934 * be wiped completely. |
|
5935 */ |
|
5936 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { |
|
5937 u32 vlvf, bits; |
|
5938 int regndx = igb_find_vlvf_entry(adapter, vid); |
|
5939 |
|
5940 if (regndx < 0) |
|
5941 goto out; |
|
5942 /* See if any other pools are set for this VLAN filter |
|
5943 * entry other than the PF. |
|
5944 */ |
|
5945 vlvf = bits = rd32(E1000_VLVF(regndx)); |
|
5946 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + |
|
5947 adapter->vfs_allocated_count); |
|
5948 /* If the filter was removed then ensure PF pool bit |
|
5949 * is cleared if the PF only added itself to the pool |
|
5950 * because the PF is in promiscuous mode. |
|
5951 */ |
|
5952 if ((vlvf & VLAN_VID_MASK) == vid && |
|
5953 !test_bit(vid, adapter->active_vlans) && |
|
5954 !bits) |
|
5955 igb_vlvf_set(adapter, vid, add, |
|
5956 adapter->vfs_allocated_count); |
|
5957 } |
|
5958 |
|
5959 out: |
|
5960 return err; |
|
5961 } |
|
5962 |
|
5963 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
|
5964 { |
|
5965 /* clear flags - except flag that indicates PF has set the MAC */ |
|
5966 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; |
|
5967 adapter->vf_data[vf].last_nack = jiffies; |
|
5968 |
|
5969 /* reset offloads to defaults */ |
|
5970 igb_set_vmolr(adapter, vf, true); |
|
5971 |
|
5972 /* reset vlans for device */ |
|
5973 igb_clear_vf_vfta(adapter, vf); |
|
5974 if (adapter->vf_data[vf].pf_vlan) |
|
5975 igb_ndo_set_vf_vlan(adapter->netdev, vf, |
|
5976 adapter->vf_data[vf].pf_vlan, |
|
5977 adapter->vf_data[vf].pf_qos); |
|
5978 else |
|
5979 igb_clear_vf_vfta(adapter, vf); |
|
5980 |
|
5981 /* reset multicast table array for vf */ |
|
5982 adapter->vf_data[vf].num_vf_mc_hashes = 0; |
|
5983 |
|
5984 /* Flush and reset the mta with the new values */ |
|
5985 igb_set_rx_mode(adapter->netdev); |
|
5986 } |
|
5987 |
|
5988 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
|
5989 { |
|
5990 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; |
|
5991 |
|
5992 /* clear mac address as we were hotplug removed/added */ |
|
5993 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
|
5994 eth_zero_addr(vf_mac); |
|
5995 |
|
5996 /* process remaining reset events */ |
|
5997 igb_vf_reset(adapter, vf); |
|
5998 } |
|
5999 |
|
6000 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) |
|
6001 { |
|
6002 struct e1000_hw *hw = &adapter->hw; |
|
6003 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; |
|
6004 int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
|
6005 u32 reg, msgbuf[3]; |
|
6006 u8 *addr = (u8 *)(&msgbuf[1]); |
|
6007 |
|
6008 /* process all the same items cleared in a function level reset */ |
|
6009 igb_vf_reset(adapter, vf); |
|
6010 |
|
6011 /* set vf mac address */ |
|
6012 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
|
6013 |
|
6014 /* enable transmit and receive for vf */ |
|
6015 reg = rd32(E1000_VFTE); |
|
6016 wr32(E1000_VFTE, reg | (1 << vf)); |
|
6017 reg = rd32(E1000_VFRE); |
|
6018 wr32(E1000_VFRE, reg | (1 << vf)); |
|
6019 |
|
6020 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
|
6021 |
|
6022 /* reply to reset with ack and vf mac address */ |
|
6023 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; |
|
6024 memcpy(addr, vf_mac, ETH_ALEN); |
|
6025 igb_write_mbx(hw, msgbuf, 3, vf); |
|
6026 } |
|
6027 |
|
6028 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) |
|
6029 { |
|
6030 /* The VF MAC Address is stored in a packed array of bytes |
|
6031 * starting at the second 32 bit word of the msg array |
|
6032 */ |
|
6033 unsigned char *addr = (char *)&msg[1]; |
|
6034 int err = -1; |
|
6035 |
|
6036 if (is_valid_ether_addr(addr)) |
|
6037 err = igb_set_vf_mac(adapter, vf, addr); |
|
6038 |
|
6039 return err; |
|
6040 } |
|
6041 |
|
6042 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) |
|
6043 { |
|
6044 struct e1000_hw *hw = &adapter->hw; |
|
6045 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
|
6046 u32 msg = E1000_VT_MSGTYPE_NACK; |
|
6047 |
|
6048 /* if device isn't clear to send it shouldn't be reading either */ |
|
6049 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
|
6050 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { |
|
6051 igb_write_mbx(hw, &msg, 1, vf); |
|
6052 vf_data->last_nack = jiffies; |
|
6053 } |
|
6054 } |
|
6055 |
|
6056 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
|
6057 { |
|
6058 struct pci_dev *pdev = adapter->pdev; |
|
6059 u32 msgbuf[E1000_VFMAILBOX_SIZE]; |
|
6060 struct e1000_hw *hw = &adapter->hw; |
|
6061 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
|
6062 s32 retval; |
|
6063 |
|
6064 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
|
6065 |
|
6066 if (retval) { |
|
6067 /* if receive failed revoke VF CTS stats and restart init */ |
|
6068 dev_err(&pdev->dev, "Error receiving message from VF\n"); |
|
6069 vf_data->flags &= ~IGB_VF_FLAG_CTS; |
|
6070 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
|
6071 return; |
|
6072 goto out; |
|
6073 } |
|
6074 |
|
6075 /* this is a message we already processed, do nothing */ |
|
6076 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) |
|
6077 return; |
|
6078 |
|
6079 /* until the vf completes a reset it should not be |
|
6080 * allowed to start any configuration. |
|
6081 */ |
|
6082 if (msgbuf[0] == E1000_VF_RESET) { |
|
6083 igb_vf_reset_msg(adapter, vf); |
|
6084 return; |
|
6085 } |
|
6086 |
|
6087 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
|
6088 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
|
6089 return; |
|
6090 retval = -1; |
|
6091 goto out; |
|
6092 } |
|
6093 |
|
6094 switch ((msgbuf[0] & 0xFFFF)) { |
|
6095 case E1000_VF_SET_MAC_ADDR: |
|
6096 retval = -EINVAL; |
|
6097 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) |
|
6098 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); |
|
6099 else |
|
6100 dev_warn(&pdev->dev, |
|
6101 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", |
|
6102 vf); |
|
6103 break; |
|
6104 case E1000_VF_SET_PROMISC: |
|
6105 retval = igb_set_vf_promisc(adapter, msgbuf, vf); |
|
6106 break; |
|
6107 case E1000_VF_SET_MULTICAST: |
|
6108 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); |
|
6109 break; |
|
6110 case E1000_VF_SET_LPE: |
|
6111 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); |
|
6112 break; |
|
6113 case E1000_VF_SET_VLAN: |
|
6114 retval = -1; |
|
6115 if (vf_data->pf_vlan) |
|
6116 dev_warn(&pdev->dev, |
|
6117 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", |
|
6118 vf); |
|
6119 else |
|
6120 retval = igb_set_vf_vlan(adapter, msgbuf, vf); |
|
6121 break; |
|
6122 default: |
|
6123 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
|
6124 retval = -1; |
|
6125 break; |
|
6126 } |
|
6127 |
|
6128 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
|
6129 out: |
|
6130 /* notify the VF of the results of what it sent us */ |
|
6131 if (retval) |
|
6132 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; |
|
6133 else |
|
6134 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; |
|
6135 |
|
6136 igb_write_mbx(hw, msgbuf, 1, vf); |
|
6137 } |
|
6138 |
|
6139 static void igb_msg_task(struct igb_adapter *adapter) |
|
6140 { |
|
6141 struct e1000_hw *hw = &adapter->hw; |
|
6142 u32 vf; |
|
6143 |
|
6144 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { |
|
6145 /* process any reset requests */ |
|
6146 if (!igb_check_for_rst(hw, vf)) |
|
6147 igb_vf_reset_event(adapter, vf); |
|
6148 |
|
6149 /* process any messages pending */ |
|
6150 if (!igb_check_for_msg(hw, vf)) |
|
6151 igb_rcv_msg_from_vf(adapter, vf); |
|
6152 |
|
6153 /* process any acks */ |
|
6154 if (!igb_check_for_ack(hw, vf)) |
|
6155 igb_rcv_ack_from_vf(adapter, vf); |
|
6156 } |
|
6157 } |
|
6158 |
|
6159 /** |
|
6160 * igb_set_uta - Set unicast filter table address |
|
6161 * @adapter: board private structure |
|
6162 * |
|
6163 * The unicast table address is a register array of 32-bit registers. |
|
6164 * The table is meant to be used in a way similar to how the MTA is used |
|
6165 * however due to certain limitations in the hardware it is necessary to |
|
6166 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
|
6167 * enable bit to allow vlan tag stripping when promiscuous mode is enabled |
|
6168 **/ |
|
6169 static void igb_set_uta(struct igb_adapter *adapter) |
|
6170 { |
|
6171 struct e1000_hw *hw = &adapter->hw; |
|
6172 int i; |
|
6173 |
|
6174 /* The UTA table only exists on 82576 hardware and newer */ |
|
6175 if (hw->mac.type < e1000_82576) |
|
6176 return; |
|
6177 |
|
6178 /* we only need to do this if VMDq is enabled */ |
|
6179 if (!adapter->vfs_allocated_count) |
|
6180 return; |
|
6181 |
|
6182 for (i = 0; i < hw->mac.uta_reg_count; i++) |
|
6183 array_wr32(E1000_UTA, i, ~0); |
|
6184 } |
|
6185 |
|
6186 /** |
|
6187 * igb_intr_msi - Interrupt Handler |
|
6188 * @irq: interrupt number |
|
6189 * @data: pointer to a network interface device structure |
|
6190 **/ |
|
6191 static irqreturn_t igb_intr_msi(int irq, void *data) |
|
6192 { |
|
6193 struct igb_adapter *adapter = data; |
|
6194 struct igb_q_vector *q_vector = adapter->q_vector[0]; |
|
6195 struct e1000_hw *hw = &adapter->hw; |
|
6196 /* read ICR disables interrupts using IAM */ |
|
6197 u32 icr = rd32(E1000_ICR); |
|
6198 |
|
6199 igb_write_itr(q_vector); |
|
6200 |
|
6201 if (icr & E1000_ICR_DRSTA) |
|
6202 schedule_work(&adapter->reset_task); |
|
6203 |
|
6204 if (icr & E1000_ICR_DOUTSYNC) { |
|
6205 /* HW is reporting DMA is out of sync */ |
|
6206 adapter->stats.doosync++; |
|
6207 } |
|
6208 |
|
6209 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
|
6210 hw->mac.get_link_status = 1; |
|
6211 if (!test_bit(__IGB_DOWN, &adapter->state)) |
|
6212 mod_timer(&adapter->watchdog_timer, jiffies + 1); |
|
6213 } |
|
6214 |
|
6215 if (icr & E1000_ICR_TS) { |
|
6216 u32 tsicr = rd32(E1000_TSICR); |
|
6217 |
|
6218 if (tsicr & E1000_TSICR_TXTS) { |
|
6219 /* acknowledge the interrupt */ |
|
6220 wr32(E1000_TSICR, E1000_TSICR_TXTS); |
|
6221 /* retrieve hardware timestamp */ |
|
6222 schedule_work(&adapter->ptp_tx_work); |
|
6223 } |
|
6224 } |
|
6225 |
|
6226 napi_schedule(&q_vector->napi); |
|
6227 |
|
6228 return IRQ_HANDLED; |
|
6229 } |
|
6230 |
|
6231 /** |
|
6232 * igb_intr - Legacy Interrupt Handler |
|
6233 * @irq: interrupt number |
|
6234 * @data: pointer to a network interface device structure |
|
6235 **/ |
|
6236 static irqreturn_t igb_intr(int irq, void *data) |
|
6237 { |
|
6238 struct igb_adapter *adapter = data; |
|
6239 struct igb_q_vector *q_vector = adapter->q_vector[0]; |
|
6240 struct e1000_hw *hw = &adapter->hw; |
|
6241 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No |
|
6242 * need for the IMC write |
|
6243 */ |
|
6244 u32 icr = rd32(E1000_ICR); |
|
6245 |
|
6246 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is |
|
6247 * not set, then the adapter didn't send an interrupt |
|
6248 */ |
|
6249 if (!(icr & E1000_ICR_INT_ASSERTED)) |
|
6250 return IRQ_NONE; |
|
6251 |
|
6252 igb_write_itr(q_vector); |
|
6253 |
|
6254 if (icr & E1000_ICR_DRSTA) |
|
6255 schedule_work(&adapter->reset_task); |
|
6256 |
|
6257 if (icr & E1000_ICR_DOUTSYNC) { |
|
6258 /* HW is reporting DMA is out of sync */ |
|
6259 adapter->stats.doosync++; |
|
6260 } |
|
6261 |
|
6262 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
|
6263 hw->mac.get_link_status = 1; |
|
6264 /* guard against interrupt when we're going down */ |
|
6265 if (!test_bit(__IGB_DOWN, &adapter->state)) |
|
6266 mod_timer(&adapter->watchdog_timer, jiffies + 1); |
|
6267 } |
|
6268 |
|
6269 if (icr & E1000_ICR_TS) { |
|
6270 u32 tsicr = rd32(E1000_TSICR); |
|
6271 |
|
6272 if (tsicr & E1000_TSICR_TXTS) { |
|
6273 /* acknowledge the interrupt */ |
|
6274 wr32(E1000_TSICR, E1000_TSICR_TXTS); |
|
6275 /* retrieve hardware timestamp */ |
|
6276 schedule_work(&adapter->ptp_tx_work); |
|
6277 } |
|
6278 } |
|
6279 |
|
6280 napi_schedule(&q_vector->napi); |
|
6281 |
|
6282 return IRQ_HANDLED; |
|
6283 } |
|
6284 |
|
6285 static void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
|
6286 { |
|
6287 struct igb_adapter *adapter = q_vector->adapter; |
|
6288 struct e1000_hw *hw = &adapter->hw; |
|
6289 |
|
6290 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || |
|
6291 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { |
|
6292 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) |
|
6293 igb_set_itr(q_vector); |
|
6294 else |
|
6295 igb_update_ring_itr(q_vector); |
|
6296 } |
|
6297 |
|
6298 if (!test_bit(__IGB_DOWN, &adapter->state)) { |
|
6299 if (adapter->flags & IGB_FLAG_HAS_MSIX) |
|
6300 wr32(E1000_EIMS, q_vector->eims_value); |
|
6301 else |
|
6302 igb_irq_enable(adapter); |
|
6303 } |
|
6304 } |
|
6305 |
|
6306 /** |
|
6307 * igb_poll - NAPI Rx polling callback |
|
6308 * @napi: napi polling structure |
|
6309 * @budget: count of how many packets we should handle |
|
6310 **/ |
|
6311 static int igb_poll(struct napi_struct *napi, int budget) |
|
6312 { |
|
6313 struct igb_q_vector *q_vector = container_of(napi, |
|
6314 struct igb_q_vector, |
|
6315 napi); |
|
6316 bool clean_complete = true; |
|
6317 |
|
6318 #ifdef CONFIG_IGB_DCA |
|
6319 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
|
6320 igb_update_dca(q_vector); |
|
6321 #endif |
|
6322 if (q_vector->tx.ring) |
|
6323 clean_complete = igb_clean_tx_irq(q_vector); |
|
6324 |
|
6325 if (q_vector->rx.ring) |
|
6326 clean_complete &= igb_clean_rx_irq(q_vector, budget); |
|
6327 |
|
6328 /* If all work not completed, return budget and keep polling */ |
|
6329 if (!clean_complete) |
|
6330 return budget; |
|
6331 |
|
6332 /* If not enough Rx work done, exit the polling mode */ |
|
6333 napi_complete(napi); |
|
6334 igb_ring_irq_enable(q_vector); |
|
6335 |
|
6336 return 0; |
|
6337 } |
|
6338 |
|
6339 /** |
|
6340 * igb_clean_tx_irq - Reclaim resources after transmit completes |
|
6341 * @q_vector: pointer to q_vector containing needed info |
|
6342 * |
|
6343 * returns true if ring is completely cleaned |
|
6344 **/ |
|
6345 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
|
6346 { |
|
6347 struct igb_adapter *adapter = q_vector->adapter; |
|
6348 struct igb_ring *tx_ring = q_vector->tx.ring; |
|
6349 struct igb_tx_buffer *tx_buffer; |
|
6350 union e1000_adv_tx_desc *tx_desc; |
|
6351 unsigned int total_bytes = 0, total_packets = 0; |
|
6352 unsigned int budget = q_vector->tx.work_limit; |
|
6353 unsigned int i = tx_ring->next_to_clean; |
|
6354 |
|
6355 if (test_bit(__IGB_DOWN, &adapter->state)) |
|
6356 return true; |
|
6357 |
|
6358 tx_buffer = &tx_ring->tx_buffer_info[i]; |
|
6359 tx_desc = IGB_TX_DESC(tx_ring, i); |
|
6360 i -= tx_ring->count; |
|
6361 |
|
6362 do { |
|
6363 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
|
6364 |
|
6365 /* if next_to_watch is not set then there is no work pending */ |
|
6366 if (!eop_desc) |
|
6367 break; |
|
6368 |
|
6369 /* prevent any other reads prior to eop_desc */ |
|
6370 read_barrier_depends(); |
|
6371 |
|
6372 /* if DD is not set pending work has not been completed */ |
|
6373 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) |
|
6374 break; |
|
6375 |
|
6376 /* clear next_to_watch to prevent false hangs */ |
|
6377 tx_buffer->next_to_watch = NULL; |
|
6378 |
|
6379 /* update the statistics for this packet */ |
|
6380 total_bytes += tx_buffer->bytecount; |
|
6381 total_packets += tx_buffer->gso_segs; |
|
6382 |
|
6383 /* free the skb */ |
|
6384 dev_consume_skb_any(tx_buffer->skb); |
|
6385 |
|
6386 /* unmap skb header data */ |
|
6387 dma_unmap_single(tx_ring->dev, |
|
6388 dma_unmap_addr(tx_buffer, dma), |
|
6389 dma_unmap_len(tx_buffer, len), |
|
6390 DMA_TO_DEVICE); |
|
6391 |
|
6392 /* clear tx_buffer data */ |
|
6393 tx_buffer->skb = NULL; |
|
6394 dma_unmap_len_set(tx_buffer, len, 0); |
|
6395 |
|
6396 /* clear last DMA location and unmap remaining buffers */ |
|
6397 while (tx_desc != eop_desc) { |
|
6398 tx_buffer++; |
|
6399 tx_desc++; |
|
6400 i++; |
|
6401 if (unlikely(!i)) { |
|
6402 i -= tx_ring->count; |
|
6403 tx_buffer = tx_ring->tx_buffer_info; |
|
6404 tx_desc = IGB_TX_DESC(tx_ring, 0); |
|
6405 } |
|
6406 |
|
6407 /* unmap any remaining paged data */ |
|
6408 if (dma_unmap_len(tx_buffer, len)) { |
|
6409 dma_unmap_page(tx_ring->dev, |
|
6410 dma_unmap_addr(tx_buffer, dma), |
|
6411 dma_unmap_len(tx_buffer, len), |
|
6412 DMA_TO_DEVICE); |
|
6413 dma_unmap_len_set(tx_buffer, len, 0); |
|
6414 } |
|
6415 } |
|
6416 |
|
6417 /* move us one more past the eop_desc for start of next pkt */ |
|
6418 tx_buffer++; |
|
6419 tx_desc++; |
|
6420 i++; |
|
6421 if (unlikely(!i)) { |
|
6422 i -= tx_ring->count; |
|
6423 tx_buffer = tx_ring->tx_buffer_info; |
|
6424 tx_desc = IGB_TX_DESC(tx_ring, 0); |
|
6425 } |
|
6426 |
|
6427 /* issue prefetch for next Tx descriptor */ |
|
6428 prefetch(tx_desc); |
|
6429 |
|
6430 /* update budget accounting */ |
|
6431 budget--; |
|
6432 } while (likely(budget)); |
|
6433 |
|
6434 netdev_tx_completed_queue(txring_txq(tx_ring), |
|
6435 total_packets, total_bytes); |
|
6436 i += tx_ring->count; |
|
6437 tx_ring->next_to_clean = i; |
|
6438 u64_stats_update_begin(&tx_ring->tx_syncp); |
|
6439 tx_ring->tx_stats.bytes += total_bytes; |
|
6440 tx_ring->tx_stats.packets += total_packets; |
|
6441 u64_stats_update_end(&tx_ring->tx_syncp); |
|
6442 q_vector->tx.total_bytes += total_bytes; |
|
6443 q_vector->tx.total_packets += total_packets; |
|
6444 |
|
6445 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { |
|
6446 struct e1000_hw *hw = &adapter->hw; |
|
6447 |
|
6448 /* Detect a transmit hang in hardware, this serializes the |
|
6449 * check with the clearing of time_stamp and movement of i |
|
6450 */ |
|
6451 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
|
6452 if (tx_buffer->next_to_watch && |
|
6453 time_after(jiffies, tx_buffer->time_stamp + |
|
6454 (adapter->tx_timeout_factor * HZ)) && |
|
6455 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { |
|
6456 |
|
6457 /* detected Tx unit hang */ |
|
6458 dev_err(tx_ring->dev, |
|
6459 "Detected Tx Unit Hang\n" |
|
6460 " Tx Queue <%d>\n" |
|
6461 " TDH <%x>\n" |
|
6462 " TDT <%x>\n" |
|
6463 " next_to_use <%x>\n" |
|
6464 " next_to_clean <%x>\n" |
|
6465 "buffer_info[next_to_clean]\n" |
|
6466 " time_stamp <%lx>\n" |
|
6467 " next_to_watch <%p>\n" |
|
6468 " jiffies <%lx>\n" |
|
6469 " desc.status <%x>\n", |
|
6470 tx_ring->queue_index, |
|
6471 rd32(E1000_TDH(tx_ring->reg_idx)), |
|
6472 readl(tx_ring->tail), |
|
6473 tx_ring->next_to_use, |
|
6474 tx_ring->next_to_clean, |
|
6475 tx_buffer->time_stamp, |
|
6476 tx_buffer->next_to_watch, |
|
6477 jiffies, |
|
6478 tx_buffer->next_to_watch->wb.status); |
|
6479 netif_stop_subqueue(tx_ring->netdev, |
|
6480 tx_ring->queue_index); |
|
6481 |
|
6482 /* we are about to reset, no point in enabling stuff */ |
|
6483 return true; |
|
6484 } |
|
6485 } |
|
6486 |
|
6487 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
|
6488 if (unlikely(total_packets && |
|
6489 netif_carrier_ok(tx_ring->netdev) && |
|
6490 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { |
|
6491 /* Make sure that anybody stopping the queue after this |
|
6492 * sees the new next_to_clean. |
|
6493 */ |
|
6494 smp_mb(); |
|
6495 if (__netif_subqueue_stopped(tx_ring->netdev, |
|
6496 tx_ring->queue_index) && |
|
6497 !(test_bit(__IGB_DOWN, &adapter->state))) { |
|
6498 netif_wake_subqueue(tx_ring->netdev, |
|
6499 tx_ring->queue_index); |
|
6500 |
|
6501 u64_stats_update_begin(&tx_ring->tx_syncp); |
|
6502 tx_ring->tx_stats.restart_queue++; |
|
6503 u64_stats_update_end(&tx_ring->tx_syncp); |
|
6504 } |
|
6505 } |
|
6506 |
|
6507 return !!budget; |
|
6508 } |
|
6509 |
|
6510 /** |
|
6511 * igb_reuse_rx_page - page flip buffer and store it back on the ring |
|
6512 * @rx_ring: rx descriptor ring to store buffers on |
|
6513 * @old_buff: donor buffer to have page reused |
|
6514 * |
|
6515 * Synchronizes page for reuse by the adapter |
|
6516 **/ |
|
6517 static void igb_reuse_rx_page(struct igb_ring *rx_ring, |
|
6518 struct igb_rx_buffer *old_buff) |
|
6519 { |
|
6520 struct igb_rx_buffer *new_buff; |
|
6521 u16 nta = rx_ring->next_to_alloc; |
|
6522 |
|
6523 new_buff = &rx_ring->rx_buffer_info[nta]; |
|
6524 |
|
6525 /* update, and store next to alloc */ |
|
6526 nta++; |
|
6527 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; |
|
6528 |
|
6529 /* transfer page from old buffer to new buffer */ |
|
6530 *new_buff = *old_buff; |
|
6531 |
|
6532 /* sync the buffer for use by the device */ |
|
6533 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, |
|
6534 old_buff->page_offset, |
|
6535 IGB_RX_BUFSZ, |
|
6536 DMA_FROM_DEVICE); |
|
6537 } |
|
6538 |
|
6539 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, |
|
6540 struct page *page, |
|
6541 unsigned int truesize) |
|
6542 { |
|
6543 /* avoid re-using remote pages */ |
|
6544 if (unlikely(page_to_nid(page) != numa_node_id())) |
|
6545 return false; |
|
6546 |
|
6547 if (unlikely(page->pfmemalloc)) |
|
6548 return false; |
|
6549 |
|
6550 #if (PAGE_SIZE < 8192) |
|
6551 /* if we are only owner of page we can reuse it */ |
|
6552 if (unlikely(page_count(page) != 1)) |
|
6553 return false; |
|
6554 |
|
6555 /* flip page offset to other buffer */ |
|
6556 rx_buffer->page_offset ^= IGB_RX_BUFSZ; |
|
6557 |
|
6558 /* Even if we own the page, we are not allowed to use atomic_set() |
|
6559 * This would break get_page_unless_zero() users. |
|
6560 */ |
|
6561 atomic_inc(&page->_count); |
|
6562 #else |
|
6563 /* move offset up to the next cache line */ |
|
6564 rx_buffer->page_offset += truesize; |
|
6565 |
|
6566 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) |
|
6567 return false; |
|
6568 |
|
6569 /* bump ref count on page before it is given to the stack */ |
|
6570 get_page(page); |
|
6571 #endif |
|
6572 |
|
6573 return true; |
|
6574 } |
|
6575 |
|
6576 /** |
|
6577 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff |
|
6578 * @rx_ring: rx descriptor ring to transact packets on |
|
6579 * @rx_buffer: buffer containing page to add |
|
6580 * @rx_desc: descriptor containing length of buffer written by hardware |
|
6581 * @skb: sk_buff to place the data into |
|
6582 * |
|
6583 * This function will add the data contained in rx_buffer->page to the skb. |
|
6584 * This is done either through a direct copy if the data in the buffer is |
|
6585 * less than the skb header size, otherwise it will just attach the page as |
|
6586 * a frag to the skb. |
|
6587 * |
|
6588 * The function will then update the page offset if necessary and return |
|
6589 * true if the buffer can be reused by the adapter. |
|
6590 **/ |
|
6591 static bool igb_add_rx_frag(struct igb_ring *rx_ring, |
|
6592 struct igb_rx_buffer *rx_buffer, |
|
6593 union e1000_adv_rx_desc *rx_desc, |
|
6594 struct sk_buff *skb) |
|
6595 { |
|
6596 struct page *page = rx_buffer->page; |
|
6597 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); |
|
6598 #if (PAGE_SIZE < 8192) |
|
6599 unsigned int truesize = IGB_RX_BUFSZ; |
|
6600 #else |
|
6601 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); |
|
6602 #endif |
|
6603 |
|
6604 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { |
|
6605 unsigned char *va = page_address(page) + rx_buffer->page_offset; |
|
6606 |
|
6607 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
|
6608 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); |
|
6609 va += IGB_TS_HDR_LEN; |
|
6610 size -= IGB_TS_HDR_LEN; |
|
6611 } |
|
6612 |
|
6613 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
|
6614 |
|
6615 /* we can reuse buffer as-is, just make sure it is local */ |
|
6616 if (likely((page_to_nid(page) == numa_node_id()) && |
|
6617 !page->pfmemalloc)) |
|
6618 return true; |
|
6619 |
|
6620 /* this page cannot be reused so discard it */ |
|
6621 put_page(page); |
|
6622 return false; |
|
6623 } |
|
6624 |
|
6625 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, |
|
6626 rx_buffer->page_offset, size, truesize); |
|
6627 |
|
6628 return igb_can_reuse_rx_page(rx_buffer, page, truesize); |
|
6629 } |
|
6630 |
|
6631 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, |
|
6632 union e1000_adv_rx_desc *rx_desc, |
|
6633 struct sk_buff *skb) |
|
6634 { |
|
6635 struct igb_rx_buffer *rx_buffer; |
|
6636 struct page *page; |
|
6637 |
|
6638 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; |
|
6639 |
|
6640 page = rx_buffer->page; |
|
6641 prefetchw(page); |
|
6642 |
|
6643 if (likely(!skb)) { |
|
6644 void *page_addr = page_address(page) + |
|
6645 rx_buffer->page_offset; |
|
6646 |
|
6647 /* prefetch first cache line of first page */ |
|
6648 prefetch(page_addr); |
|
6649 #if L1_CACHE_BYTES < 128 |
|
6650 prefetch(page_addr + L1_CACHE_BYTES); |
|
6651 #endif |
|
6652 |
|
6653 /* allocate a skb to store the frags */ |
|
6654 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
|
6655 IGB_RX_HDR_LEN); |
|
6656 if (unlikely(!skb)) { |
|
6657 rx_ring->rx_stats.alloc_failed++; |
|
6658 return NULL; |
|
6659 } |
|
6660 |
|
6661 /* we will be copying header into skb->data in |
|
6662 * pskb_may_pull so it is in our interest to prefetch |
|
6663 * it now to avoid a possible cache miss |
|
6664 */ |
|
6665 prefetchw(skb->data); |
|
6666 } |
|
6667 |
|
6668 /* we are reusing so sync this buffer for CPU use */ |
|
6669 dma_sync_single_range_for_cpu(rx_ring->dev, |
|
6670 rx_buffer->dma, |
|
6671 rx_buffer->page_offset, |
|
6672 IGB_RX_BUFSZ, |
|
6673 DMA_FROM_DEVICE); |
|
6674 |
|
6675 /* pull page into skb */ |
|
6676 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { |
|
6677 /* hand second half of page back to the ring */ |
|
6678 igb_reuse_rx_page(rx_ring, rx_buffer); |
|
6679 } else { |
|
6680 /* we are not reusing the buffer so unmap it */ |
|
6681 dma_unmap_page(rx_ring->dev, rx_buffer->dma, |
|
6682 PAGE_SIZE, DMA_FROM_DEVICE); |
|
6683 } |
|
6684 |
|
6685 /* clear contents of rx_buffer */ |
|
6686 rx_buffer->page = NULL; |
|
6687 |
|
6688 return skb; |
|
6689 } |
|
6690 |
|
6691 static inline void igb_rx_checksum(struct igb_ring *ring, |
|
6692 union e1000_adv_rx_desc *rx_desc, |
|
6693 struct sk_buff *skb) |
|
6694 { |
|
6695 skb_checksum_none_assert(skb); |
|
6696 |
|
6697 /* Ignore Checksum bit is set */ |
|
6698 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) |
|
6699 return; |
|
6700 |
|
6701 /* Rx checksum disabled via ethtool */ |
|
6702 if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
|
6703 return; |
|
6704 |
|
6705 /* TCP/UDP checksum error bit is set */ |
|
6706 if (igb_test_staterr(rx_desc, |
|
6707 E1000_RXDEXT_STATERR_TCPE | |
|
6708 E1000_RXDEXT_STATERR_IPE)) { |
|
6709 /* work around errata with sctp packets where the TCPE aka |
|
6710 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) |
|
6711 * packets, (aka let the stack check the crc32c) |
|
6712 */ |
|
6713 if (!((skb->len == 60) && |
|
6714 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { |
|
6715 u64_stats_update_begin(&ring->rx_syncp); |
|
6716 ring->rx_stats.csum_err++; |
|
6717 u64_stats_update_end(&ring->rx_syncp); |
|
6718 } |
|
6719 /* let the stack verify checksum errors */ |
|
6720 return; |
|
6721 } |
|
6722 /* It must be a TCP or UDP packet with a valid checksum */ |
|
6723 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | |
|
6724 E1000_RXD_STAT_UDPCS)) |
|
6725 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
6726 |
|
6727 dev_dbg(ring->dev, "cksum success: bits %08X\n", |
|
6728 le32_to_cpu(rx_desc->wb.upper.status_error)); |
|
6729 } |
|
6730 |
|
6731 static inline void igb_rx_hash(struct igb_ring *ring, |
|
6732 union e1000_adv_rx_desc *rx_desc, |
|
6733 struct sk_buff *skb) |
|
6734 { |
|
6735 if (ring->netdev->features & NETIF_F_RXHASH) |
|
6736 skb_set_hash(skb, |
|
6737 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), |
|
6738 PKT_HASH_TYPE_L3); |
|
6739 } |
|
6740 |
|
6741 /** |
|
6742 * igb_is_non_eop - process handling of non-EOP buffers |
|
6743 * @rx_ring: Rx ring being processed |
|
6744 * @rx_desc: Rx descriptor for current buffer |
|
6745 * @skb: current socket buffer containing buffer in progress |
|
6746 * |
|
6747 * This function updates next to clean. If the buffer is an EOP buffer |
|
6748 * this function exits returning false, otherwise it will place the |
|
6749 * sk_buff in the next buffer to be chained and return true indicating |
|
6750 * that this is in fact a non-EOP buffer. |
|
6751 **/ |
|
6752 static bool igb_is_non_eop(struct igb_ring *rx_ring, |
|
6753 union e1000_adv_rx_desc *rx_desc) |
|
6754 { |
|
6755 u32 ntc = rx_ring->next_to_clean + 1; |
|
6756 |
|
6757 /* fetch, update, and store next to clean */ |
|
6758 ntc = (ntc < rx_ring->count) ? ntc : 0; |
|
6759 rx_ring->next_to_clean = ntc; |
|
6760 |
|
6761 prefetch(IGB_RX_DESC(rx_ring, ntc)); |
|
6762 |
|
6763 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) |
|
6764 return false; |
|
6765 |
|
6766 return true; |
|
6767 } |
|
6768 |
|
6769 /** |
|
6770 * igb_pull_tail - igb specific version of skb_pull_tail |
|
6771 * @rx_ring: rx descriptor ring packet is being transacted on |
|
6772 * @rx_desc: pointer to the EOP Rx descriptor |
|
6773 * @skb: pointer to current skb being adjusted |
|
6774 * |
|
6775 * This function is an igb specific version of __pskb_pull_tail. The |
|
6776 * main difference between this version and the original function is that |
|
6777 * this function can make several assumptions about the state of things |
|
6778 * that allow for significant optimizations versus the standard function. |
|
6779 * As a result we can do things like drop a frag and maintain an accurate |
|
6780 * truesize for the skb. |
|
6781 */ |
|
6782 static void igb_pull_tail(struct igb_ring *rx_ring, |
|
6783 union e1000_adv_rx_desc *rx_desc, |
|
6784 struct sk_buff *skb) |
|
6785 { |
|
6786 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
|
6787 unsigned char *va; |
|
6788 unsigned int pull_len; |
|
6789 |
|
6790 /* it is valid to use page_address instead of kmap since we are |
|
6791 * working with pages allocated out of the lomem pool per |
|
6792 * alloc_page(GFP_ATOMIC) |
|
6793 */ |
|
6794 va = skb_frag_address(frag); |
|
6795 |
|
6796 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
|
6797 /* retrieve timestamp from buffer */ |
|
6798 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); |
|
6799 |
|
6800 /* update pointers to remove timestamp header */ |
|
6801 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); |
|
6802 frag->page_offset += IGB_TS_HDR_LEN; |
|
6803 skb->data_len -= IGB_TS_HDR_LEN; |
|
6804 skb->len -= IGB_TS_HDR_LEN; |
|
6805 |
|
6806 /* move va to start of packet data */ |
|
6807 va += IGB_TS_HDR_LEN; |
|
6808 } |
|
6809 |
|
6810 /* we need the header to contain the greater of either ETH_HLEN or |
|
6811 * 60 bytes if the skb->len is less than 60 for skb_pad. |
|
6812 */ |
|
6813 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN); |
|
6814 |
|
6815 /* align pull length to size of long to optimize memcpy performance */ |
|
6816 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); |
|
6817 |
|
6818 /* update all of the pointers */ |
|
6819 skb_frag_size_sub(frag, pull_len); |
|
6820 frag->page_offset += pull_len; |
|
6821 skb->data_len -= pull_len; |
|
6822 skb->tail += pull_len; |
|
6823 } |
|
6824 |
|
6825 /** |
|
6826 * igb_cleanup_headers - Correct corrupted or empty headers |
|
6827 * @rx_ring: rx descriptor ring packet is being transacted on |
|
6828 * @rx_desc: pointer to the EOP Rx descriptor |
|
6829 * @skb: pointer to current skb being fixed |
|
6830 * |
|
6831 * Address the case where we are pulling data in on pages only |
|
6832 * and as such no data is present in the skb header. |
|
6833 * |
|
6834 * In addition if skb is not at least 60 bytes we need to pad it so that |
|
6835 * it is large enough to qualify as a valid Ethernet frame. |
|
6836 * |
|
6837 * Returns true if an error was encountered and skb was freed. |
|
6838 **/ |
|
6839 static bool igb_cleanup_headers(struct igb_ring *rx_ring, |
|
6840 union e1000_adv_rx_desc *rx_desc, |
|
6841 struct sk_buff *skb) |
|
6842 { |
|
6843 if (unlikely((igb_test_staterr(rx_desc, |
|
6844 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { |
|
6845 struct net_device *netdev = rx_ring->netdev; |
|
6846 if (!(netdev->features & NETIF_F_RXALL)) { |
|
6847 dev_kfree_skb_any(skb); |
|
6848 return true; |
|
6849 } |
|
6850 } |
|
6851 |
|
6852 /* place header in linear portion of buffer */ |
|
6853 if (skb_is_nonlinear(skb)) |
|
6854 igb_pull_tail(rx_ring, rx_desc, skb); |
|
6855 |
|
6856 /* if skb_pad returns an error the skb was freed */ |
|
6857 if (unlikely(skb->len < 60)) { |
|
6858 int pad_len = 60 - skb->len; |
|
6859 |
|
6860 if (skb_pad(skb, pad_len)) |
|
6861 return true; |
|
6862 __skb_put(skb, pad_len); |
|
6863 } |
|
6864 |
|
6865 return false; |
|
6866 } |
|
6867 |
|
6868 /** |
|
6869 * igb_process_skb_fields - Populate skb header fields from Rx descriptor |
|
6870 * @rx_ring: rx descriptor ring packet is being transacted on |
|
6871 * @rx_desc: pointer to the EOP Rx descriptor |
|
6872 * @skb: pointer to current skb being populated |
|
6873 * |
|
6874 * This function checks the ring, descriptor, and packet information in |
|
6875 * order to populate the hash, checksum, VLAN, timestamp, protocol, and |
|
6876 * other fields within the skb. |
|
6877 **/ |
|
6878 static void igb_process_skb_fields(struct igb_ring *rx_ring, |
|
6879 union e1000_adv_rx_desc *rx_desc, |
|
6880 struct sk_buff *skb) |
|
6881 { |
|
6882 struct net_device *dev = rx_ring->netdev; |
|
6883 |
|
6884 igb_rx_hash(rx_ring, rx_desc, skb); |
|
6885 |
|
6886 igb_rx_checksum(rx_ring, rx_desc, skb); |
|
6887 |
|
6888 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && |
|
6889 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) |
|
6890 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); |
|
6891 |
|
6892 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
|
6893 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { |
|
6894 u16 vid; |
|
6895 |
|
6896 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && |
|
6897 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) |
|
6898 vid = be16_to_cpu(rx_desc->wb.upper.vlan); |
|
6899 else |
|
6900 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
|
6901 |
|
6902 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
|
6903 } |
|
6904 |
|
6905 skb_record_rx_queue(skb, rx_ring->queue_index); |
|
6906 |
|
6907 skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
|
6908 } |
|
6909 |
|
6910 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) |
|
6911 { |
|
6912 struct igb_ring *rx_ring = q_vector->rx.ring; |
|
6913 struct sk_buff *skb = rx_ring->skb; |
|
6914 unsigned int total_bytes = 0, total_packets = 0; |
|
6915 u16 cleaned_count = igb_desc_unused(rx_ring); |
|
6916 |
|
6917 while (likely(total_packets < budget)) { |
|
6918 union e1000_adv_rx_desc *rx_desc; |
|
6919 |
|
6920 /* return some buffers to hardware, one at a time is too slow */ |
|
6921 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { |
|
6922 igb_alloc_rx_buffers(rx_ring, cleaned_count); |
|
6923 cleaned_count = 0; |
|
6924 } |
|
6925 |
|
6926 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); |
|
6927 |
|
6928 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) |
|
6929 break; |
|
6930 |
|
6931 /* This memory barrier is needed to keep us from reading |
|
6932 * any other fields out of the rx_desc until we know the |
|
6933 * RXD_STAT_DD bit is set |
|
6934 */ |
|
6935 rmb(); |
|
6936 |
|
6937 /* retrieve a buffer from the ring */ |
|
6938 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); |
|
6939 |
|
6940 /* exit if we failed to retrieve a buffer */ |
|
6941 if (!skb) |
|
6942 break; |
|
6943 |
|
6944 cleaned_count++; |
|
6945 |
|
6946 /* fetch next buffer in frame if non-eop */ |
|
6947 if (igb_is_non_eop(rx_ring, rx_desc)) |
|
6948 continue; |
|
6949 |
|
6950 /* verify the packet layout is correct */ |
|
6951 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { |
|
6952 skb = NULL; |
|
6953 continue; |
|
6954 } |
|
6955 |
|
6956 /* probably a little skewed due to removing CRC */ |
|
6957 total_bytes += skb->len; |
|
6958 |
|
6959 /* populate checksum, timestamp, VLAN, and protocol */ |
|
6960 igb_process_skb_fields(rx_ring, rx_desc, skb); |
|
6961 |
|
6962 napi_gro_receive(&q_vector->napi, skb); |
|
6963 |
|
6964 /* reset skb pointer */ |
|
6965 skb = NULL; |
|
6966 |
|
6967 /* update budget accounting */ |
|
6968 total_packets++; |
|
6969 } |
|
6970 |
|
6971 /* place incomplete frames back on ring for completion */ |
|
6972 rx_ring->skb = skb; |
|
6973 |
|
6974 u64_stats_update_begin(&rx_ring->rx_syncp); |
|
6975 rx_ring->rx_stats.packets += total_packets; |
|
6976 rx_ring->rx_stats.bytes += total_bytes; |
|
6977 u64_stats_update_end(&rx_ring->rx_syncp); |
|
6978 q_vector->rx.total_packets += total_packets; |
|
6979 q_vector->rx.total_bytes += total_bytes; |
|
6980 |
|
6981 if (cleaned_count) |
|
6982 igb_alloc_rx_buffers(rx_ring, cleaned_count); |
|
6983 |
|
6984 return total_packets < budget; |
|
6985 } |
|
6986 |
|
6987 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, |
|
6988 struct igb_rx_buffer *bi) |
|
6989 { |
|
6990 struct page *page = bi->page; |
|
6991 dma_addr_t dma; |
|
6992 |
|
6993 /* since we are recycling buffers we should seldom need to alloc */ |
|
6994 if (likely(page)) |
|
6995 return true; |
|
6996 |
|
6997 /* alloc new page for storage */ |
|
6998 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); |
|
6999 if (unlikely(!page)) { |
|
7000 rx_ring->rx_stats.alloc_failed++; |
|
7001 return false; |
|
7002 } |
|
7003 |
|
7004 /* map page for use */ |
|
7005 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); |
|
7006 |
|
7007 /* if mapping failed free memory back to system since |
|
7008 * there isn't much point in holding memory we can't use |
|
7009 */ |
|
7010 if (dma_mapping_error(rx_ring->dev, dma)) { |
|
7011 __free_page(page); |
|
7012 |
|
7013 rx_ring->rx_stats.alloc_failed++; |
|
7014 return false; |
|
7015 } |
|
7016 |
|
7017 bi->dma = dma; |
|
7018 bi->page = page; |
|
7019 bi->page_offset = 0; |
|
7020 |
|
7021 return true; |
|
7022 } |
|
7023 |
|
7024 /** |
|
7025 * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
|
7026 * @adapter: address of board private structure |
|
7027 **/ |
|
7028 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
|
7029 { |
|
7030 union e1000_adv_rx_desc *rx_desc; |
|
7031 struct igb_rx_buffer *bi; |
|
7032 u16 i = rx_ring->next_to_use; |
|
7033 |
|
7034 /* nothing to do */ |
|
7035 if (!cleaned_count) |
|
7036 return; |
|
7037 |
|
7038 rx_desc = IGB_RX_DESC(rx_ring, i); |
|
7039 bi = &rx_ring->rx_buffer_info[i]; |
|
7040 i -= rx_ring->count; |
|
7041 |
|
7042 do { |
|
7043 if (!igb_alloc_mapped_page(rx_ring, bi)) |
|
7044 break; |
|
7045 |
|
7046 /* Refresh the desc even if buffer_addrs didn't change |
|
7047 * because each write-back erases this info. |
|
7048 */ |
|
7049 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); |
|
7050 |
|
7051 rx_desc++; |
|
7052 bi++; |
|
7053 i++; |
|
7054 if (unlikely(!i)) { |
|
7055 rx_desc = IGB_RX_DESC(rx_ring, 0); |
|
7056 bi = rx_ring->rx_buffer_info; |
|
7057 i -= rx_ring->count; |
|
7058 } |
|
7059 |
|
7060 /* clear the hdr_addr for the next_to_use descriptor */ |
|
7061 rx_desc->read.hdr_addr = 0; |
|
7062 |
|
7063 cleaned_count--; |
|
7064 } while (cleaned_count); |
|
7065 |
|
7066 i += rx_ring->count; |
|
7067 |
|
7068 if (rx_ring->next_to_use != i) { |
|
7069 /* record the next descriptor to use */ |
|
7070 rx_ring->next_to_use = i; |
|
7071 |
|
7072 /* update next to alloc since we have filled the ring */ |
|
7073 rx_ring->next_to_alloc = i; |
|
7074 |
|
7075 /* Force memory writes to complete before letting h/w |
|
7076 * know there are new descriptors to fetch. (Only |
|
7077 * applicable for weak-ordered memory model archs, |
|
7078 * such as IA-64). |
|
7079 */ |
|
7080 wmb(); |
|
7081 writel(i, rx_ring->tail); |
|
7082 } |
|
7083 } |
|
7084 |
|
7085 /** |
|
7086 * igb_mii_ioctl - |
|
7087 * @netdev: |
|
7088 * @ifreq: |
|
7089 * @cmd: |
|
7090 **/ |
|
7091 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
|
7092 { |
|
7093 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7094 struct mii_ioctl_data *data = if_mii(ifr); |
|
7095 |
|
7096 if (adapter->hw.phy.media_type != e1000_media_type_copper) |
|
7097 return -EOPNOTSUPP; |
|
7098 |
|
7099 switch (cmd) { |
|
7100 case SIOCGMIIPHY: |
|
7101 data->phy_id = adapter->hw.phy.addr; |
|
7102 break; |
|
7103 case SIOCGMIIREG: |
|
7104 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
|
7105 &data->val_out)) |
|
7106 return -EIO; |
|
7107 break; |
|
7108 case SIOCSMIIREG: |
|
7109 default: |
|
7110 return -EOPNOTSUPP; |
|
7111 } |
|
7112 return 0; |
|
7113 } |
|
7114 |
|
7115 /** |
|
7116 * igb_ioctl - |
|
7117 * @netdev: |
|
7118 * @ifreq: |
|
7119 * @cmd: |
|
7120 **/ |
|
7121 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
|
7122 { |
|
7123 switch (cmd) { |
|
7124 case SIOCGMIIPHY: |
|
7125 case SIOCGMIIREG: |
|
7126 case SIOCSMIIREG: |
|
7127 return igb_mii_ioctl(netdev, ifr, cmd); |
|
7128 case SIOCGHWTSTAMP: |
|
7129 return igb_ptp_get_ts_config(netdev, ifr); |
|
7130 case SIOCSHWTSTAMP: |
|
7131 return igb_ptp_set_ts_config(netdev, ifr); |
|
7132 default: |
|
7133 return -EOPNOTSUPP; |
|
7134 } |
|
7135 } |
|
7136 |
|
7137 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) |
|
7138 { |
|
7139 struct igb_adapter *adapter = hw->back; |
|
7140 |
|
7141 pci_read_config_word(adapter->pdev, reg, value); |
|
7142 } |
|
7143 |
|
7144 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) |
|
7145 { |
|
7146 struct igb_adapter *adapter = hw->back; |
|
7147 |
|
7148 pci_write_config_word(adapter->pdev, reg, *value); |
|
7149 } |
|
7150 |
|
7151 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
|
7152 { |
|
7153 struct igb_adapter *adapter = hw->back; |
|
7154 |
|
7155 if (pcie_capability_read_word(adapter->pdev, reg, value)) |
|
7156 return -E1000_ERR_CONFIG; |
|
7157 |
|
7158 return 0; |
|
7159 } |
|
7160 |
|
7161 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
|
7162 { |
|
7163 struct igb_adapter *adapter = hw->back; |
|
7164 |
|
7165 if (pcie_capability_write_word(adapter->pdev, reg, *value)) |
|
7166 return -E1000_ERR_CONFIG; |
|
7167 |
|
7168 return 0; |
|
7169 } |
|
7170 |
|
7171 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) |
|
7172 { |
|
7173 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7174 struct e1000_hw *hw = &adapter->hw; |
|
7175 u32 ctrl, rctl; |
|
7176 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); |
|
7177 |
|
7178 if (enable) { |
|
7179 /* enable VLAN tag insert/strip */ |
|
7180 ctrl = rd32(E1000_CTRL); |
|
7181 ctrl |= E1000_CTRL_VME; |
|
7182 wr32(E1000_CTRL, ctrl); |
|
7183 |
|
7184 /* Disable CFI check */ |
|
7185 rctl = rd32(E1000_RCTL); |
|
7186 rctl &= ~E1000_RCTL_CFIEN; |
|
7187 wr32(E1000_RCTL, rctl); |
|
7188 } else { |
|
7189 /* disable VLAN tag insert/strip */ |
|
7190 ctrl = rd32(E1000_CTRL); |
|
7191 ctrl &= ~E1000_CTRL_VME; |
|
7192 wr32(E1000_CTRL, ctrl); |
|
7193 } |
|
7194 |
|
7195 igb_rlpml_set(adapter); |
|
7196 } |
|
7197 |
|
7198 static int igb_vlan_rx_add_vid(struct net_device *netdev, |
|
7199 __be16 proto, u16 vid) |
|
7200 { |
|
7201 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7202 struct e1000_hw *hw = &adapter->hw; |
|
7203 int pf_id = adapter->vfs_allocated_count; |
|
7204 |
|
7205 /* attempt to add filter to vlvf array */ |
|
7206 igb_vlvf_set(adapter, vid, true, pf_id); |
|
7207 |
|
7208 /* add the filter since PF can receive vlans w/o entry in vlvf */ |
|
7209 igb_vfta_set(hw, vid, true); |
|
7210 |
|
7211 set_bit(vid, adapter->active_vlans); |
|
7212 |
|
7213 return 0; |
|
7214 } |
|
7215 |
|
7216 static int igb_vlan_rx_kill_vid(struct net_device *netdev, |
|
7217 __be16 proto, u16 vid) |
|
7218 { |
|
7219 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7220 struct e1000_hw *hw = &adapter->hw; |
|
7221 int pf_id = adapter->vfs_allocated_count; |
|
7222 s32 err; |
|
7223 |
|
7224 /* remove vlan from VLVF table array */ |
|
7225 err = igb_vlvf_set(adapter, vid, false, pf_id); |
|
7226 |
|
7227 /* if vid was not present in VLVF just remove it from table */ |
|
7228 if (err) |
|
7229 igb_vfta_set(hw, vid, false); |
|
7230 |
|
7231 clear_bit(vid, adapter->active_vlans); |
|
7232 |
|
7233 return 0; |
|
7234 } |
|
7235 |
|
7236 static void igb_restore_vlan(struct igb_adapter *adapter) |
|
7237 { |
|
7238 u16 vid; |
|
7239 |
|
7240 igb_vlan_mode(adapter->netdev, adapter->netdev->features); |
|
7241 |
|
7242 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
|
7243 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
|
7244 } |
|
7245 |
|
7246 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
|
7247 { |
|
7248 struct pci_dev *pdev = adapter->pdev; |
|
7249 struct e1000_mac_info *mac = &adapter->hw.mac; |
|
7250 |
|
7251 mac->autoneg = 0; |
|
7252 |
|
7253 /* Make sure dplx is at most 1 bit and lsb of speed is not set |
|
7254 * for the switch() below to work |
|
7255 */ |
|
7256 if ((spd & 1) || (dplx & ~1)) |
|
7257 goto err_inval; |
|
7258 |
|
7259 /* Fiber NIC's only allow 1000 gbps Full duplex |
|
7260 * and 100Mbps Full duplex for 100baseFx sfp |
|
7261 */ |
|
7262 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { |
|
7263 switch (spd + dplx) { |
|
7264 case SPEED_10 + DUPLEX_HALF: |
|
7265 case SPEED_10 + DUPLEX_FULL: |
|
7266 case SPEED_100 + DUPLEX_HALF: |
|
7267 goto err_inval; |
|
7268 default: |
|
7269 break; |
|
7270 } |
|
7271 } |
|
7272 |
|
7273 switch (spd + dplx) { |
|
7274 case SPEED_10 + DUPLEX_HALF: |
|
7275 mac->forced_speed_duplex = ADVERTISE_10_HALF; |
|
7276 break; |
|
7277 case SPEED_10 + DUPLEX_FULL: |
|
7278 mac->forced_speed_duplex = ADVERTISE_10_FULL; |
|
7279 break; |
|
7280 case SPEED_100 + DUPLEX_HALF: |
|
7281 mac->forced_speed_duplex = ADVERTISE_100_HALF; |
|
7282 break; |
|
7283 case SPEED_100 + DUPLEX_FULL: |
|
7284 mac->forced_speed_duplex = ADVERTISE_100_FULL; |
|
7285 break; |
|
7286 case SPEED_1000 + DUPLEX_FULL: |
|
7287 mac->autoneg = 1; |
|
7288 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; |
|
7289 break; |
|
7290 case SPEED_1000 + DUPLEX_HALF: /* not supported */ |
|
7291 default: |
|
7292 goto err_inval; |
|
7293 } |
|
7294 |
|
7295 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ |
|
7296 adapter->hw.phy.mdix = AUTO_ALL_MODES; |
|
7297 |
|
7298 return 0; |
|
7299 |
|
7300 err_inval: |
|
7301 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); |
|
7302 return -EINVAL; |
|
7303 } |
|
7304 |
|
7305 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, |
|
7306 bool runtime) |
|
7307 { |
|
7308 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7309 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7310 struct e1000_hw *hw = &adapter->hw; |
|
7311 u32 ctrl, rctl, status; |
|
7312 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; |
|
7313 #ifdef CONFIG_PM |
|
7314 int retval = 0; |
|
7315 #endif |
|
7316 |
|
7317 netif_device_detach(netdev); |
|
7318 |
|
7319 if (netif_running(netdev)) |
|
7320 __igb_close(netdev, true); |
|
7321 |
|
7322 igb_clear_interrupt_scheme(adapter); |
|
7323 |
|
7324 #ifdef CONFIG_PM |
|
7325 retval = pci_save_state(pdev); |
|
7326 if (retval) |
|
7327 return retval; |
|
7328 #endif |
|
7329 |
|
7330 status = rd32(E1000_STATUS); |
|
7331 if (status & E1000_STATUS_LU) |
|
7332 wufc &= ~E1000_WUFC_LNKC; |
|
7333 |
|
7334 if (wufc) { |
|
7335 igb_setup_rctl(adapter); |
|
7336 igb_set_rx_mode(netdev); |
|
7337 |
|
7338 /* turn on all-multi mode if wake on multicast is enabled */ |
|
7339 if (wufc & E1000_WUFC_MC) { |
|
7340 rctl = rd32(E1000_RCTL); |
|
7341 rctl |= E1000_RCTL_MPE; |
|
7342 wr32(E1000_RCTL, rctl); |
|
7343 } |
|
7344 |
|
7345 ctrl = rd32(E1000_CTRL); |
|
7346 /* advertise wake from D3Cold */ |
|
7347 #define E1000_CTRL_ADVD3WUC 0x00100000 |
|
7348 /* phy power management enable */ |
|
7349 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 |
|
7350 ctrl |= E1000_CTRL_ADVD3WUC; |
|
7351 wr32(E1000_CTRL, ctrl); |
|
7352 |
|
7353 /* Allow time for pending master requests to run */ |
|
7354 igb_disable_pcie_master(hw); |
|
7355 |
|
7356 wr32(E1000_WUC, E1000_WUC_PME_EN); |
|
7357 wr32(E1000_WUFC, wufc); |
|
7358 } else { |
|
7359 wr32(E1000_WUC, 0); |
|
7360 wr32(E1000_WUFC, 0); |
|
7361 } |
|
7362 |
|
7363 *enable_wake = wufc || adapter->en_mng_pt; |
|
7364 if (!*enable_wake) |
|
7365 igb_power_down_link(adapter); |
|
7366 else |
|
7367 igb_power_up_link(adapter); |
|
7368 |
|
7369 /* Release control of h/w to f/w. If f/w is AMT enabled, this |
|
7370 * would have already happened in close and is redundant. |
|
7371 */ |
|
7372 igb_release_hw_control(adapter); |
|
7373 |
|
7374 pci_disable_device(pdev); |
|
7375 |
|
7376 return 0; |
|
7377 } |
|
7378 |
|
7379 #ifdef CONFIG_PM |
|
7380 #ifdef CONFIG_PM_SLEEP |
|
7381 static int igb_suspend(struct device *dev) |
|
7382 { |
|
7383 int retval; |
|
7384 bool wake; |
|
7385 struct pci_dev *pdev = to_pci_dev(dev); |
|
7386 |
|
7387 retval = __igb_shutdown(pdev, &wake, 0); |
|
7388 if (retval) |
|
7389 return retval; |
|
7390 |
|
7391 if (wake) { |
|
7392 pci_prepare_to_sleep(pdev); |
|
7393 } else { |
|
7394 pci_wake_from_d3(pdev, false); |
|
7395 pci_set_power_state(pdev, PCI_D3hot); |
|
7396 } |
|
7397 |
|
7398 return 0; |
|
7399 } |
|
7400 #endif /* CONFIG_PM_SLEEP */ |
|
7401 |
|
7402 static int igb_resume(struct device *dev) |
|
7403 { |
|
7404 struct pci_dev *pdev = to_pci_dev(dev); |
|
7405 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7406 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7407 struct e1000_hw *hw = &adapter->hw; |
|
7408 u32 err; |
|
7409 |
|
7410 pci_set_power_state(pdev, PCI_D0); |
|
7411 pci_restore_state(pdev); |
|
7412 pci_save_state(pdev); |
|
7413 |
|
7414 if (!pci_device_is_present(pdev)) |
|
7415 return -ENODEV; |
|
7416 err = pci_enable_device_mem(pdev); |
|
7417 if (err) { |
|
7418 dev_err(&pdev->dev, |
|
7419 "igb: Cannot enable PCI device from suspend\n"); |
|
7420 return err; |
|
7421 } |
|
7422 pci_set_master(pdev); |
|
7423 |
|
7424 pci_enable_wake(pdev, PCI_D3hot, 0); |
|
7425 pci_enable_wake(pdev, PCI_D3cold, 0); |
|
7426 |
|
7427 if (igb_init_interrupt_scheme(adapter, true)) { |
|
7428 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
|
7429 return -ENOMEM; |
|
7430 } |
|
7431 |
|
7432 igb_reset(adapter); |
|
7433 |
|
7434 /* let the f/w know that the h/w is now under the control of the |
|
7435 * driver. |
|
7436 */ |
|
7437 igb_get_hw_control(adapter); |
|
7438 |
|
7439 wr32(E1000_WUS, ~0); |
|
7440 |
|
7441 if (netdev->flags & IFF_UP) { |
|
7442 rtnl_lock(); |
|
7443 err = __igb_open(netdev, true); |
|
7444 rtnl_unlock(); |
|
7445 if (err) |
|
7446 return err; |
|
7447 } |
|
7448 |
|
7449 netif_device_attach(netdev); |
|
7450 return 0; |
|
7451 } |
|
7452 |
|
7453 #ifdef CONFIG_PM_RUNTIME |
|
7454 static int igb_runtime_idle(struct device *dev) |
|
7455 { |
|
7456 struct pci_dev *pdev = to_pci_dev(dev); |
|
7457 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7458 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7459 |
|
7460 if (!igb_has_link(adapter)) |
|
7461 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); |
|
7462 |
|
7463 return -EBUSY; |
|
7464 } |
|
7465 |
|
7466 static int igb_runtime_suspend(struct device *dev) |
|
7467 { |
|
7468 struct pci_dev *pdev = to_pci_dev(dev); |
|
7469 int retval; |
|
7470 bool wake; |
|
7471 |
|
7472 retval = __igb_shutdown(pdev, &wake, 1); |
|
7473 if (retval) |
|
7474 return retval; |
|
7475 |
|
7476 if (wake) { |
|
7477 pci_prepare_to_sleep(pdev); |
|
7478 } else { |
|
7479 pci_wake_from_d3(pdev, false); |
|
7480 pci_set_power_state(pdev, PCI_D3hot); |
|
7481 } |
|
7482 |
|
7483 return 0; |
|
7484 } |
|
7485 |
|
7486 static int igb_runtime_resume(struct device *dev) |
|
7487 { |
|
7488 return igb_resume(dev); |
|
7489 } |
|
7490 #endif /* CONFIG_PM_RUNTIME */ |
|
7491 #endif |
|
7492 |
|
7493 static void igb_shutdown(struct pci_dev *pdev) |
|
7494 { |
|
7495 bool wake; |
|
7496 |
|
7497 __igb_shutdown(pdev, &wake, 0); |
|
7498 |
|
7499 if (system_state == SYSTEM_POWER_OFF) { |
|
7500 pci_wake_from_d3(pdev, wake); |
|
7501 pci_set_power_state(pdev, PCI_D3hot); |
|
7502 } |
|
7503 } |
|
7504 |
|
7505 #ifdef CONFIG_PCI_IOV |
|
7506 static int igb_sriov_reinit(struct pci_dev *dev) |
|
7507 { |
|
7508 struct net_device *netdev = pci_get_drvdata(dev); |
|
7509 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7510 struct pci_dev *pdev = adapter->pdev; |
|
7511 |
|
7512 rtnl_lock(); |
|
7513 |
|
7514 if (netif_running(netdev)) |
|
7515 igb_close(netdev); |
|
7516 else |
|
7517 igb_reset(adapter); |
|
7518 |
|
7519 igb_clear_interrupt_scheme(adapter); |
|
7520 |
|
7521 igb_init_queue_configuration(adapter); |
|
7522 |
|
7523 if (igb_init_interrupt_scheme(adapter, true)) { |
|
7524 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
|
7525 return -ENOMEM; |
|
7526 } |
|
7527 |
|
7528 if (netif_running(netdev)) |
|
7529 igb_open(netdev); |
|
7530 |
|
7531 rtnl_unlock(); |
|
7532 |
|
7533 return 0; |
|
7534 } |
|
7535 |
|
7536 static int igb_pci_disable_sriov(struct pci_dev *dev) |
|
7537 { |
|
7538 int err = igb_disable_sriov(dev); |
|
7539 |
|
7540 if (!err) |
|
7541 err = igb_sriov_reinit(dev); |
|
7542 |
|
7543 return err; |
|
7544 } |
|
7545 |
|
7546 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) |
|
7547 { |
|
7548 int err = igb_enable_sriov(dev, num_vfs); |
|
7549 |
|
7550 if (err) |
|
7551 goto out; |
|
7552 |
|
7553 err = igb_sriov_reinit(dev); |
|
7554 if (!err) |
|
7555 return num_vfs; |
|
7556 |
|
7557 out: |
|
7558 return err; |
|
7559 } |
|
7560 |
|
7561 #endif |
|
7562 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) |
|
7563 { |
|
7564 #ifdef CONFIG_PCI_IOV |
|
7565 if (num_vfs == 0) |
|
7566 return igb_pci_disable_sriov(dev); |
|
7567 else |
|
7568 return igb_pci_enable_sriov(dev, num_vfs); |
|
7569 #endif |
|
7570 return 0; |
|
7571 } |
|
7572 |
|
7573 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
7574 /* Polling 'interrupt' - used by things like netconsole to send skbs |
|
7575 * without having to re-enable interrupts. It's not called while |
|
7576 * the interrupt routine is executing. |
|
7577 */ |
|
7578 static void igb_netpoll(struct net_device *netdev) |
|
7579 { |
|
7580 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7581 struct e1000_hw *hw = &adapter->hw; |
|
7582 struct igb_q_vector *q_vector; |
|
7583 int i; |
|
7584 |
|
7585 for (i = 0; i < adapter->num_q_vectors; i++) { |
|
7586 q_vector = adapter->q_vector[i]; |
|
7587 if (adapter->flags & IGB_FLAG_HAS_MSIX) |
|
7588 wr32(E1000_EIMC, q_vector->eims_value); |
|
7589 else |
|
7590 igb_irq_disable(adapter); |
|
7591 napi_schedule(&q_vector->napi); |
|
7592 } |
|
7593 } |
|
7594 #endif /* CONFIG_NET_POLL_CONTROLLER */ |
|
7595 |
|
7596 /** |
|
7597 * igb_io_error_detected - called when PCI error is detected |
|
7598 * @pdev: Pointer to PCI device |
|
7599 * @state: The current pci connection state |
|
7600 * |
|
7601 * This function is called after a PCI bus error affecting |
|
7602 * this device has been detected. |
|
7603 **/ |
|
7604 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, |
|
7605 pci_channel_state_t state) |
|
7606 { |
|
7607 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7608 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7609 |
|
7610 netif_device_detach(netdev); |
|
7611 |
|
7612 if (state == pci_channel_io_perm_failure) |
|
7613 return PCI_ERS_RESULT_DISCONNECT; |
|
7614 |
|
7615 if (netif_running(netdev)) |
|
7616 igb_down(adapter); |
|
7617 pci_disable_device(pdev); |
|
7618 |
|
7619 /* Request a slot slot reset. */ |
|
7620 return PCI_ERS_RESULT_NEED_RESET; |
|
7621 } |
|
7622 |
|
7623 /** |
|
7624 * igb_io_slot_reset - called after the pci bus has been reset. |
|
7625 * @pdev: Pointer to PCI device |
|
7626 * |
|
7627 * Restart the card from scratch, as if from a cold-boot. Implementation |
|
7628 * resembles the first-half of the igb_resume routine. |
|
7629 **/ |
|
7630 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) |
|
7631 { |
|
7632 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7633 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7634 struct e1000_hw *hw = &adapter->hw; |
|
7635 pci_ers_result_t result; |
|
7636 int err; |
|
7637 |
|
7638 if (pci_enable_device_mem(pdev)) { |
|
7639 dev_err(&pdev->dev, |
|
7640 "Cannot re-enable PCI device after reset.\n"); |
|
7641 result = PCI_ERS_RESULT_DISCONNECT; |
|
7642 } else { |
|
7643 pci_set_master(pdev); |
|
7644 pci_restore_state(pdev); |
|
7645 pci_save_state(pdev); |
|
7646 |
|
7647 pci_enable_wake(pdev, PCI_D3hot, 0); |
|
7648 pci_enable_wake(pdev, PCI_D3cold, 0); |
|
7649 |
|
7650 igb_reset(adapter); |
|
7651 wr32(E1000_WUS, ~0); |
|
7652 result = PCI_ERS_RESULT_RECOVERED; |
|
7653 } |
|
7654 |
|
7655 err = pci_cleanup_aer_uncorrect_error_status(pdev); |
|
7656 if (err) { |
|
7657 dev_err(&pdev->dev, |
|
7658 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", |
|
7659 err); |
|
7660 /* non-fatal, continue */ |
|
7661 } |
|
7662 |
|
7663 return result; |
|
7664 } |
|
7665 |
|
7666 /** |
|
7667 * igb_io_resume - called when traffic can start flowing again. |
|
7668 * @pdev: Pointer to PCI device |
|
7669 * |
|
7670 * This callback is called when the error recovery driver tells us that |
|
7671 * its OK to resume normal operation. Implementation resembles the |
|
7672 * second-half of the igb_resume routine. |
|
7673 */ |
|
7674 static void igb_io_resume(struct pci_dev *pdev) |
|
7675 { |
|
7676 struct net_device *netdev = pci_get_drvdata(pdev); |
|
7677 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7678 |
|
7679 if (netif_running(netdev)) { |
|
7680 if (igb_up(adapter)) { |
|
7681 dev_err(&pdev->dev, "igb_up failed after reset\n"); |
|
7682 return; |
|
7683 } |
|
7684 } |
|
7685 |
|
7686 netif_device_attach(netdev); |
|
7687 |
|
7688 /* let the f/w know that the h/w is now under the control of the |
|
7689 * driver. |
|
7690 */ |
|
7691 igb_get_hw_control(adapter); |
|
7692 } |
|
7693 |
|
7694 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
|
7695 u8 qsel) |
|
7696 { |
|
7697 u32 rar_low, rar_high; |
|
7698 struct e1000_hw *hw = &adapter->hw; |
|
7699 |
|
7700 /* HW expects these in little endian so we reverse the byte order |
|
7701 * from network order (big endian) to little endian |
|
7702 */ |
|
7703 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | |
|
7704 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
|
7705 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
|
7706 |
|
7707 /* Indicate to hardware the Address is Valid. */ |
|
7708 rar_high |= E1000_RAH_AV; |
|
7709 |
|
7710 if (hw->mac.type == e1000_82575) |
|
7711 rar_high |= E1000_RAH_POOL_1 * qsel; |
|
7712 else |
|
7713 rar_high |= E1000_RAH_POOL_1 << qsel; |
|
7714 |
|
7715 wr32(E1000_RAL(index), rar_low); |
|
7716 wrfl(); |
|
7717 wr32(E1000_RAH(index), rar_high); |
|
7718 wrfl(); |
|
7719 } |
|
7720 |
|
7721 static int igb_set_vf_mac(struct igb_adapter *adapter, |
|
7722 int vf, unsigned char *mac_addr) |
|
7723 { |
|
7724 struct e1000_hw *hw = &adapter->hw; |
|
7725 /* VF MAC addresses start at end of receive addresses and moves |
|
7726 * towards the first, as a result a collision should not be possible |
|
7727 */ |
|
7728 int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
|
7729 |
|
7730 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
|
7731 |
|
7732 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
|
7733 |
|
7734 return 0; |
|
7735 } |
|
7736 |
|
7737 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
|
7738 { |
|
7739 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7740 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) |
|
7741 return -EINVAL; |
|
7742 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; |
|
7743 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); |
|
7744 dev_info(&adapter->pdev->dev, |
|
7745 "Reload the VF driver to make this change effective."); |
|
7746 if (test_bit(__IGB_DOWN, &adapter->state)) { |
|
7747 dev_warn(&adapter->pdev->dev, |
|
7748 "The VF MAC address has been set, but the PF device is not up.\n"); |
|
7749 dev_warn(&adapter->pdev->dev, |
|
7750 "Bring the PF device up before attempting to use the VF device.\n"); |
|
7751 } |
|
7752 return igb_set_vf_mac(adapter, vf, mac); |
|
7753 } |
|
7754 |
|
7755 static int igb_link_mbps(int internal_link_speed) |
|
7756 { |
|
7757 switch (internal_link_speed) { |
|
7758 case SPEED_100: |
|
7759 return 100; |
|
7760 case SPEED_1000: |
|
7761 return 1000; |
|
7762 default: |
|
7763 return 0; |
|
7764 } |
|
7765 } |
|
7766 |
|
7767 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, |
|
7768 int link_speed) |
|
7769 { |
|
7770 int rf_dec, rf_int; |
|
7771 u32 bcnrc_val; |
|
7772 |
|
7773 if (tx_rate != 0) { |
|
7774 /* Calculate the rate factor values to set */ |
|
7775 rf_int = link_speed / tx_rate; |
|
7776 rf_dec = (link_speed - (rf_int * tx_rate)); |
|
7777 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / |
|
7778 tx_rate; |
|
7779 |
|
7780 bcnrc_val = E1000_RTTBCNRC_RS_ENA; |
|
7781 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & |
|
7782 E1000_RTTBCNRC_RF_INT_MASK); |
|
7783 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); |
|
7784 } else { |
|
7785 bcnrc_val = 0; |
|
7786 } |
|
7787 |
|
7788 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ |
|
7789 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM |
|
7790 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. |
|
7791 */ |
|
7792 wr32(E1000_RTTBCNRM, 0x14); |
|
7793 wr32(E1000_RTTBCNRC, bcnrc_val); |
|
7794 } |
|
7795 |
|
7796 static void igb_check_vf_rate_limit(struct igb_adapter *adapter) |
|
7797 { |
|
7798 int actual_link_speed, i; |
|
7799 bool reset_rate = false; |
|
7800 |
|
7801 /* VF TX rate limit was not set or not supported */ |
|
7802 if ((adapter->vf_rate_link_speed == 0) || |
|
7803 (adapter->hw.mac.type != e1000_82576)) |
|
7804 return; |
|
7805 |
|
7806 actual_link_speed = igb_link_mbps(adapter->link_speed); |
|
7807 if (actual_link_speed != adapter->vf_rate_link_speed) { |
|
7808 reset_rate = true; |
|
7809 adapter->vf_rate_link_speed = 0; |
|
7810 dev_info(&adapter->pdev->dev, |
|
7811 "Link speed has been changed. VF Transmit rate is disabled\n"); |
|
7812 } |
|
7813 |
|
7814 for (i = 0; i < adapter->vfs_allocated_count; i++) { |
|
7815 if (reset_rate) |
|
7816 adapter->vf_data[i].tx_rate = 0; |
|
7817 |
|
7818 igb_set_vf_rate_limit(&adapter->hw, i, |
|
7819 adapter->vf_data[i].tx_rate, |
|
7820 actual_link_speed); |
|
7821 } |
|
7822 } |
|
7823 |
|
7824 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, |
|
7825 int min_tx_rate, int max_tx_rate) |
|
7826 { |
|
7827 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7828 struct e1000_hw *hw = &adapter->hw; |
|
7829 int actual_link_speed; |
|
7830 |
|
7831 if (hw->mac.type != e1000_82576) |
|
7832 return -EOPNOTSUPP; |
|
7833 |
|
7834 if (min_tx_rate) |
|
7835 return -EINVAL; |
|
7836 |
|
7837 actual_link_speed = igb_link_mbps(adapter->link_speed); |
|
7838 if ((vf >= adapter->vfs_allocated_count) || |
|
7839 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || |
|
7840 (max_tx_rate < 0) || |
|
7841 (max_tx_rate > actual_link_speed)) |
|
7842 return -EINVAL; |
|
7843 |
|
7844 adapter->vf_rate_link_speed = actual_link_speed; |
|
7845 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate; |
|
7846 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed); |
|
7847 |
|
7848 return 0; |
|
7849 } |
|
7850 |
|
7851 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
|
7852 bool setting) |
|
7853 { |
|
7854 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7855 struct e1000_hw *hw = &adapter->hw; |
|
7856 u32 reg_val, reg_offset; |
|
7857 |
|
7858 if (!adapter->vfs_allocated_count) |
|
7859 return -EOPNOTSUPP; |
|
7860 |
|
7861 if (vf >= adapter->vfs_allocated_count) |
|
7862 return -EINVAL; |
|
7863 |
|
7864 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; |
|
7865 reg_val = rd32(reg_offset); |
|
7866 if (setting) |
|
7867 reg_val |= ((1 << vf) | |
|
7868 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); |
|
7869 else |
|
7870 reg_val &= ~((1 << vf) | |
|
7871 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); |
|
7872 wr32(reg_offset, reg_val); |
|
7873 |
|
7874 adapter->vf_data[vf].spoofchk_enabled = setting; |
|
7875 return 0; |
|
7876 } |
|
7877 |
|
7878 static int igb_ndo_get_vf_config(struct net_device *netdev, |
|
7879 int vf, struct ifla_vf_info *ivi) |
|
7880 { |
|
7881 struct igb_adapter *adapter = netdev_priv(netdev); |
|
7882 if (vf >= adapter->vfs_allocated_count) |
|
7883 return -EINVAL; |
|
7884 ivi->vf = vf; |
|
7885 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); |
|
7886 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate; |
|
7887 ivi->min_tx_rate = 0; |
|
7888 ivi->vlan = adapter->vf_data[vf].pf_vlan; |
|
7889 ivi->qos = adapter->vf_data[vf].pf_qos; |
|
7890 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; |
|
7891 return 0; |
|
7892 } |
|
7893 |
|
7894 static void igb_vmm_control(struct igb_adapter *adapter) |
|
7895 { |
|
7896 struct e1000_hw *hw = &adapter->hw; |
|
7897 u32 reg; |
|
7898 |
|
7899 switch (hw->mac.type) { |
|
7900 case e1000_82575: |
|
7901 case e1000_i210: |
|
7902 case e1000_i211: |
|
7903 case e1000_i354: |
|
7904 default: |
|
7905 /* replication is not supported for 82575 */ |
|
7906 return; |
|
7907 case e1000_82576: |
|
7908 /* notify HW that the MAC is adding vlan tags */ |
|
7909 reg = rd32(E1000_DTXCTL); |
|
7910 reg |= E1000_DTXCTL_VLAN_ADDED; |
|
7911 wr32(E1000_DTXCTL, reg); |
|
7912 /* Fall through */ |
|
7913 case e1000_82580: |
|
7914 /* enable replication vlan tag stripping */ |
|
7915 reg = rd32(E1000_RPLOLR); |
|
7916 reg |= E1000_RPLOLR_STRVLAN; |
|
7917 wr32(E1000_RPLOLR, reg); |
|
7918 /* Fall through */ |
|
7919 case e1000_i350: |
|
7920 /* none of the above registers are supported by i350 */ |
|
7921 break; |
|
7922 } |
|
7923 |
|
7924 if (adapter->vfs_allocated_count) { |
|
7925 igb_vmdq_set_loopback_pf(hw, true); |
|
7926 igb_vmdq_set_replication_pf(hw, true); |
|
7927 igb_vmdq_set_anti_spoofing_pf(hw, true, |
|
7928 adapter->vfs_allocated_count); |
|
7929 } else { |
|
7930 igb_vmdq_set_loopback_pf(hw, false); |
|
7931 igb_vmdq_set_replication_pf(hw, false); |
|
7932 } |
|
7933 } |
|
7934 |
|
7935 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) |
|
7936 { |
|
7937 struct e1000_hw *hw = &adapter->hw; |
|
7938 u32 dmac_thr; |
|
7939 u16 hwm; |
|
7940 |
|
7941 if (hw->mac.type > e1000_82580) { |
|
7942 if (adapter->flags & IGB_FLAG_DMAC) { |
|
7943 u32 reg; |
|
7944 |
|
7945 /* force threshold to 0. */ |
|
7946 wr32(E1000_DMCTXTH, 0); |
|
7947 |
|
7948 /* DMA Coalescing high water mark needs to be greater |
|
7949 * than the Rx threshold. Set hwm to PBA - max frame |
|
7950 * size in 16B units, capping it at PBA - 6KB. |
|
7951 */ |
|
7952 hwm = 64 * pba - adapter->max_frame_size / 16; |
|
7953 if (hwm < 64 * (pba - 6)) |
|
7954 hwm = 64 * (pba - 6); |
|
7955 reg = rd32(E1000_FCRTC); |
|
7956 reg &= ~E1000_FCRTC_RTH_COAL_MASK; |
|
7957 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) |
|
7958 & E1000_FCRTC_RTH_COAL_MASK); |
|
7959 wr32(E1000_FCRTC, reg); |
|
7960 |
|
7961 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max |
|
7962 * frame size, capping it at PBA - 10KB. |
|
7963 */ |
|
7964 dmac_thr = pba - adapter->max_frame_size / 512; |
|
7965 if (dmac_thr < pba - 10) |
|
7966 dmac_thr = pba - 10; |
|
7967 reg = rd32(E1000_DMACR); |
|
7968 reg &= ~E1000_DMACR_DMACTHR_MASK; |
|
7969 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) |
|
7970 & E1000_DMACR_DMACTHR_MASK); |
|
7971 |
|
7972 /* transition to L0x or L1 if available..*/ |
|
7973 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); |
|
7974 |
|
7975 /* watchdog timer= +-1000 usec in 32usec intervals */ |
|
7976 reg |= (1000 >> 5); |
|
7977 |
|
7978 /* Disable BMC-to-OS Watchdog Enable */ |
|
7979 if (hw->mac.type != e1000_i354) |
|
7980 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; |
|
7981 |
|
7982 wr32(E1000_DMACR, reg); |
|
7983 |
|
7984 /* no lower threshold to disable |
|
7985 * coalescing(smart fifb)-UTRESH=0 |
|
7986 */ |
|
7987 wr32(E1000_DMCRTRH, 0); |
|
7988 |
|
7989 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); |
|
7990 |
|
7991 wr32(E1000_DMCTLX, reg); |
|
7992 |
|
7993 /* free space in tx packet buffer to wake from |
|
7994 * DMA coal |
|
7995 */ |
|
7996 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - |
|
7997 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); |
|
7998 |
|
7999 /* make low power state decision controlled |
|
8000 * by DMA coal |
|
8001 */ |
|
8002 reg = rd32(E1000_PCIEMISC); |
|
8003 reg &= ~E1000_PCIEMISC_LX_DECISION; |
|
8004 wr32(E1000_PCIEMISC, reg); |
|
8005 } /* endif adapter->dmac is not disabled */ |
|
8006 } else if (hw->mac.type == e1000_82580) { |
|
8007 u32 reg = rd32(E1000_PCIEMISC); |
|
8008 |
|
8009 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); |
|
8010 wr32(E1000_DMACR, 0); |
|
8011 } |
|
8012 } |
|
8013 |
|
8014 /** |
|
8015 * igb_read_i2c_byte - Reads 8 bit word over I2C |
|
8016 * @hw: pointer to hardware structure |
|
8017 * @byte_offset: byte offset to read |
|
8018 * @dev_addr: device address |
|
8019 * @data: value read |
|
8020 * |
|
8021 * Performs byte read operation over I2C interface at |
|
8022 * a specified device address. |
|
8023 **/ |
|
8024 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
|
8025 u8 dev_addr, u8 *data) |
|
8026 { |
|
8027 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); |
|
8028 struct i2c_client *this_client = adapter->i2c_client; |
|
8029 s32 status; |
|
8030 u16 swfw_mask = 0; |
|
8031 |
|
8032 if (!this_client) |
|
8033 return E1000_ERR_I2C; |
|
8034 |
|
8035 swfw_mask = E1000_SWFW_PHY0_SM; |
|
8036 |
|
8037 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) |
|
8038 return E1000_ERR_SWFW_SYNC; |
|
8039 |
|
8040 status = i2c_smbus_read_byte_data(this_client, byte_offset); |
|
8041 hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
|
8042 |
|
8043 if (status < 0) |
|
8044 return E1000_ERR_I2C; |
|
8045 else { |
|
8046 *data = status; |
|
8047 return 0; |
|
8048 } |
|
8049 } |
|
8050 |
|
8051 /** |
|
8052 * igb_write_i2c_byte - Writes 8 bit word over I2C |
|
8053 * @hw: pointer to hardware structure |
|
8054 * @byte_offset: byte offset to write |
|
8055 * @dev_addr: device address |
|
8056 * @data: value to write |
|
8057 * |
|
8058 * Performs byte write operation over I2C interface at |
|
8059 * a specified device address. |
|
8060 **/ |
|
8061 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
|
8062 u8 dev_addr, u8 data) |
|
8063 { |
|
8064 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); |
|
8065 struct i2c_client *this_client = adapter->i2c_client; |
|
8066 s32 status; |
|
8067 u16 swfw_mask = E1000_SWFW_PHY0_SM; |
|
8068 |
|
8069 if (!this_client) |
|
8070 return E1000_ERR_I2C; |
|
8071 |
|
8072 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) |
|
8073 return E1000_ERR_SWFW_SYNC; |
|
8074 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); |
|
8075 hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
|
8076 |
|
8077 if (status) |
|
8078 return E1000_ERR_I2C; |
|
8079 else |
|
8080 return 0; |
|
8081 |
|
8082 } |
|
8083 |
|
8084 int igb_reinit_queues(struct igb_adapter *adapter) |
|
8085 { |
|
8086 struct net_device *netdev = adapter->netdev; |
|
8087 struct pci_dev *pdev = adapter->pdev; |
|
8088 int err = 0; |
|
8089 |
|
8090 if (netif_running(netdev)) |
|
8091 igb_close(netdev); |
|
8092 |
|
8093 igb_reset_interrupt_capability(adapter); |
|
8094 |
|
8095 if (igb_init_interrupt_scheme(adapter, true)) { |
|
8096 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
|
8097 return -ENOMEM; |
|
8098 } |
|
8099 |
|
8100 if (netif_running(netdev)) |
|
8101 err = igb_open(netdev); |
|
8102 |
|
8103 return err; |
|
8104 } |
|
8105 /* igb_main.c */ |