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1 /* Intel(R) Gigabit Ethernet Linux driver |
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2 * Copyright(c) 2007-2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * You should have received a copy of the GNU General Public License along with |
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14 * this program; if not, see <http://www.gnu.org/licenses/>. |
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15 * |
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16 * The full GNU General Public License is included in this distribution in |
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17 * the file called "COPYING". |
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18 * |
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19 * Contact Information: |
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20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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22 */ |
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23 |
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24 /* Linux PRO/1000 Ethernet Driver main header file */ |
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25 |
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26 #ifndef _IGB_H_ |
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27 #define _IGB_H_ |
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28 |
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29 #include "e1000_mac-3.18-ethercat.h" |
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30 #include "e1000_82575-3.18-ethercat.h" |
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31 |
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32 #include <linux/clocksource.h> |
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33 #include <linux/net_tstamp.h> |
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34 #include <linux/ptp_clock_kernel.h> |
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35 #include <linux/bitops.h> |
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36 #include <linux/if_vlan.h> |
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37 #include <linux/i2c.h> |
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38 #include <linux/i2c-algo-bit.h> |
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39 #include <linux/pci.h> |
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40 #include <linux/mdio.h> |
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41 |
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42 struct igb_adapter; |
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43 |
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44 #define E1000_PCS_CFG_IGN_SD 1 |
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45 |
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46 /* Interrupt defines */ |
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47 #define IGB_START_ITR 648 /* ~6000 ints/sec */ |
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48 #define IGB_4K_ITR 980 |
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49 #define IGB_20K_ITR 196 |
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50 #define IGB_70K_ITR 56 |
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51 |
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52 /* TX/RX descriptor defines */ |
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53 #define IGB_DEFAULT_TXD 256 |
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54 #define IGB_DEFAULT_TX_WORK 128 |
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55 #define IGB_MIN_TXD 80 |
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56 #define IGB_MAX_TXD 4096 |
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57 |
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58 #define IGB_DEFAULT_RXD 256 |
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59 #define IGB_MIN_RXD 80 |
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60 #define IGB_MAX_RXD 4096 |
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61 |
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62 #define IGB_DEFAULT_ITR 3 /* dynamic */ |
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63 #define IGB_MAX_ITR_USECS 10000 |
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64 #define IGB_MIN_ITR_USECS 10 |
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65 #define NON_Q_VECTORS 1 |
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66 #define MAX_Q_VECTORS 8 |
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67 #define MAX_MSIX_ENTRIES 10 |
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68 |
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69 /* Transmit and receive queues */ |
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70 #define IGB_MAX_RX_QUEUES 8 |
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71 #define IGB_MAX_RX_QUEUES_82575 4 |
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72 #define IGB_MAX_RX_QUEUES_I211 2 |
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73 #define IGB_MAX_TX_QUEUES 8 |
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74 #define IGB_MAX_VF_MC_ENTRIES 30 |
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75 #define IGB_MAX_VF_FUNCTIONS 8 |
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76 #define IGB_MAX_VFTA_ENTRIES 128 |
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77 #define IGB_82576_VF_DEV_ID 0x10CA |
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78 #define IGB_I350_VF_DEV_ID 0x1520 |
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79 |
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80 /* NVM version defines */ |
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81 #define IGB_MAJOR_MASK 0xF000 |
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82 #define IGB_MINOR_MASK 0x0FF0 |
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83 #define IGB_BUILD_MASK 0x000F |
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84 #define IGB_COMB_VER_MASK 0x00FF |
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85 #define IGB_MAJOR_SHIFT 12 |
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86 #define IGB_MINOR_SHIFT 4 |
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87 #define IGB_COMB_VER_SHFT 8 |
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88 #define IGB_NVM_VER_INVALID 0xFFFF |
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89 #define IGB_ETRACK_SHIFT 16 |
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90 #define NVM_ETRACK_WORD 0x0042 |
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91 #define NVM_COMB_VER_OFF 0x0083 |
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92 #define NVM_COMB_VER_PTR 0x003d |
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93 |
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94 struct vf_data_storage { |
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95 unsigned char vf_mac_addresses[ETH_ALEN]; |
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96 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; |
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97 u16 num_vf_mc_hashes; |
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98 u16 vlans_enabled; |
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99 u32 flags; |
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100 unsigned long last_nack; |
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101 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
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102 u16 pf_qos; |
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103 u16 tx_rate; |
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104 bool spoofchk_enabled; |
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105 }; |
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106 |
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107 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
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108 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
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109 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ |
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110 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
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111 |
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112 /* RX descriptor control thresholds. |
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113 * PTHRESH - MAC will consider prefetch if it has fewer than this number of |
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114 * descriptors available in its onboard memory. |
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115 * Setting this to 0 disables RX descriptor prefetch. |
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116 * HTHRESH - MAC will only prefetch if there are at least this many descriptors |
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117 * available in host memory. |
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118 * If PTHRESH is 0, this should also be 0. |
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119 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back |
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120 * descriptors until either it has this many to write back, or the |
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121 * ITR timer expires. |
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122 */ |
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123 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) |
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124 #define IGB_RX_HTHRESH 8 |
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125 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) |
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126 #define IGB_TX_HTHRESH 1 |
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127 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
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128 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) |
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129 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
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130 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) |
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131 |
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132 /* this is the size past which hardware will drop packets when setting LPE=0 */ |
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133 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 |
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134 |
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135 /* Supported Rx Buffer Sizes */ |
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136 #define IGB_RXBUFFER_256 256 |
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137 #define IGB_RXBUFFER_2048 2048 |
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138 #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 |
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139 #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 |
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140 |
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141 /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
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142 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
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143 |
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144 #define AUTO_ALL_MODES 0 |
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145 #define IGB_EEPROM_APME 0x0400 |
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146 |
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147 #ifndef IGB_MASTER_SLAVE |
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148 /* Switch to override PHY master/slave setting */ |
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149 #define IGB_MASTER_SLAVE e1000_ms_hw_default |
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150 #endif |
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151 |
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152 #define IGB_MNG_VLAN_NONE -1 |
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153 |
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154 enum igb_tx_flags { |
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155 /* cmd_type flags */ |
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156 IGB_TX_FLAGS_VLAN = 0x01, |
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157 IGB_TX_FLAGS_TSO = 0x02, |
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158 IGB_TX_FLAGS_TSTAMP = 0x04, |
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159 |
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160 /* olinfo flags */ |
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161 IGB_TX_FLAGS_IPV4 = 0x10, |
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162 IGB_TX_FLAGS_CSUM = 0x20, |
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163 }; |
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164 |
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165 /* VLAN info */ |
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166 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
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167 #define IGB_TX_FLAGS_VLAN_SHIFT 16 |
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168 |
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169 /* The largest size we can write to the descriptor is 65535. In order to |
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170 * maintain a power of two alignment we have to limit ourselves to 32K. |
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171 */ |
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172 #define IGB_MAX_TXD_PWR 15 |
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173 #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR) |
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174 |
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175 /* Tx Descriptors needed, worst case */ |
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176 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) |
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177 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
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178 |
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179 /* EEPROM byte offsets */ |
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180 #define IGB_SFF_8472_SWAP 0x5C |
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181 #define IGB_SFF_8472_COMP 0x5E |
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182 |
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183 /* Bitmasks */ |
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184 #define IGB_SFF_ADDRESSING_MODE 0x4 |
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185 #define IGB_SFF_8472_UNSUP 0x00 |
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186 |
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187 /* wrapper around a pointer to a socket buffer, |
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188 * so a DMA handle can be stored along with the buffer |
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189 */ |
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190 struct igb_tx_buffer { |
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191 union e1000_adv_tx_desc *next_to_watch; |
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192 unsigned long time_stamp; |
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193 struct sk_buff *skb; |
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194 unsigned int bytecount; |
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195 u16 gso_segs; |
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196 __be16 protocol; |
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197 |
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198 DEFINE_DMA_UNMAP_ADDR(dma); |
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199 DEFINE_DMA_UNMAP_LEN(len); |
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200 u32 tx_flags; |
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201 }; |
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202 |
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203 struct igb_rx_buffer { |
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204 dma_addr_t dma; |
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205 struct page *page; |
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206 unsigned int page_offset; |
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207 }; |
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208 |
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209 struct igb_tx_queue_stats { |
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210 u64 packets; |
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211 u64 bytes; |
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212 u64 restart_queue; |
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213 u64 restart_queue2; |
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214 }; |
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215 |
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216 struct igb_rx_queue_stats { |
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217 u64 packets; |
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218 u64 bytes; |
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219 u64 drops; |
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220 u64 csum_err; |
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221 u64 alloc_failed; |
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222 }; |
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223 |
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224 struct igb_ring_container { |
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225 struct igb_ring *ring; /* pointer to linked list of rings */ |
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226 unsigned int total_bytes; /* total bytes processed this int */ |
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227 unsigned int total_packets; /* total packets processed this int */ |
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228 u16 work_limit; /* total work allowed per interrupt */ |
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229 u8 count; /* total number of rings in vector */ |
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230 u8 itr; /* current ITR setting for ring */ |
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231 }; |
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232 |
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233 struct igb_ring { |
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234 struct igb_q_vector *q_vector; /* backlink to q_vector */ |
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235 struct net_device *netdev; /* back pointer to net_device */ |
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236 struct device *dev; /* device pointer for dma mapping */ |
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237 union { /* array of buffer info structs */ |
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238 struct igb_tx_buffer *tx_buffer_info; |
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239 struct igb_rx_buffer *rx_buffer_info; |
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240 }; |
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241 void *desc; /* descriptor ring memory */ |
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242 unsigned long flags; /* ring specific flags */ |
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243 void __iomem *tail; /* pointer to ring tail register */ |
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244 dma_addr_t dma; /* phys address of the ring */ |
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245 unsigned int size; /* length of desc. ring in bytes */ |
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246 |
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247 u16 count; /* number of desc. in the ring */ |
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248 u8 queue_index; /* logical index of the ring*/ |
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249 u8 reg_idx; /* physical index of the ring */ |
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250 |
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251 /* everything past this point are written often */ |
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252 u16 next_to_clean; |
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253 u16 next_to_use; |
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254 u16 next_to_alloc; |
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255 |
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256 union { |
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257 /* TX */ |
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258 struct { |
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259 struct igb_tx_queue_stats tx_stats; |
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260 struct u64_stats_sync tx_syncp; |
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261 struct u64_stats_sync tx_syncp2; |
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262 }; |
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263 /* RX */ |
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264 struct { |
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265 struct sk_buff *skb; |
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266 struct igb_rx_queue_stats rx_stats; |
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267 struct u64_stats_sync rx_syncp; |
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268 }; |
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269 }; |
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270 } ____cacheline_internodealigned_in_smp; |
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271 |
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272 struct igb_q_vector { |
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273 struct igb_adapter *adapter; /* backlink */ |
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274 int cpu; /* CPU for DCA */ |
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275 u32 eims_value; /* EIMS mask value */ |
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276 |
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277 u16 itr_val; |
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278 u8 set_itr; |
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279 void __iomem *itr_register; |
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280 |
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281 struct igb_ring_container rx, tx; |
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282 |
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283 struct napi_struct napi; |
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284 struct rcu_head rcu; /* to avoid race with update stats on free */ |
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285 char name[IFNAMSIZ + 9]; |
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286 |
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287 /* for dynamic allocation of rings associated with this q_vector */ |
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288 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; |
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289 }; |
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290 |
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291 enum e1000_ring_flags_t { |
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292 IGB_RING_FLAG_RX_SCTP_CSUM, |
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293 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, |
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294 IGB_RING_FLAG_TX_CTX_IDX, |
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295 IGB_RING_FLAG_TX_DETECT_HANG |
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296 }; |
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297 |
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298 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) |
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299 |
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300 #define IGB_RX_DESC(R, i) \ |
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301 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) |
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302 #define IGB_TX_DESC(R, i) \ |
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303 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) |
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304 #define IGB_TX_CTXTDESC(R, i) \ |
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305 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) |
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306 |
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307 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ |
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308 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, |
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309 const u32 stat_err_bits) |
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310 { |
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311 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); |
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312 } |
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313 |
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314 /* igb_desc_unused - calculate if we have unused descriptors */ |
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315 static inline int igb_desc_unused(struct igb_ring *ring) |
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316 { |
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317 if (ring->next_to_clean > ring->next_to_use) |
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318 return ring->next_to_clean - ring->next_to_use - 1; |
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319 |
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320 return ring->count + ring->next_to_clean - ring->next_to_use - 1; |
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321 } |
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322 |
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323 #ifdef CONFIG_IGB_HWMON |
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324 |
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325 #define IGB_HWMON_TYPE_LOC 0 |
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326 #define IGB_HWMON_TYPE_TEMP 1 |
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327 #define IGB_HWMON_TYPE_CAUTION 2 |
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328 #define IGB_HWMON_TYPE_MAX 3 |
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329 |
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330 struct hwmon_attr { |
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331 struct device_attribute dev_attr; |
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332 struct e1000_hw *hw; |
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333 struct e1000_thermal_diode_data *sensor; |
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334 char name[12]; |
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335 }; |
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336 |
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337 struct hwmon_buff { |
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338 struct attribute_group group; |
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339 const struct attribute_group *groups[2]; |
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340 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; |
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341 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; |
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342 unsigned int n_hwmon; |
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343 }; |
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344 #endif |
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345 |
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346 #define IGB_RETA_SIZE 128 |
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347 |
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348 /* board specific private data structure */ |
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349 struct igb_adapter { |
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350 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
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351 |
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352 struct net_device *netdev; |
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353 |
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354 unsigned long state; |
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355 unsigned int flags; |
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356 |
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357 unsigned int num_q_vectors; |
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358 struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; |
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359 |
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360 /* Interrupt Throttle Rate */ |
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361 u32 rx_itr_setting; |
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362 u32 tx_itr_setting; |
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363 u16 tx_itr; |
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364 u16 rx_itr; |
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365 |
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366 /* TX */ |
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367 u16 tx_work_limit; |
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368 u32 tx_timeout_count; |
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369 int num_tx_queues; |
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370 struct igb_ring *tx_ring[16]; |
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371 |
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372 /* RX */ |
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373 int num_rx_queues; |
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374 struct igb_ring *rx_ring[16]; |
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375 |
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376 u32 max_frame_size; |
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377 u32 min_frame_size; |
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378 |
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379 struct timer_list watchdog_timer; |
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380 struct timer_list phy_info_timer; |
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381 |
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382 u16 mng_vlan_id; |
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383 u32 bd_number; |
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384 u32 wol; |
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385 u32 en_mng_pt; |
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386 u16 link_speed; |
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387 u16 link_duplex; |
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388 |
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389 struct work_struct reset_task; |
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390 struct work_struct watchdog_task; |
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391 bool fc_autoneg; |
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392 u8 tx_timeout_factor; |
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393 struct timer_list blink_timer; |
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394 unsigned long led_status; |
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395 |
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396 /* OS defined structs */ |
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397 struct pci_dev *pdev; |
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398 |
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399 spinlock_t stats64_lock; |
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400 struct rtnl_link_stats64 stats64; |
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401 |
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402 /* structs defined in e1000_hw.h */ |
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403 struct e1000_hw hw; |
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404 struct e1000_hw_stats stats; |
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405 struct e1000_phy_info phy_info; |
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406 |
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407 u32 test_icr; |
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408 struct igb_ring test_tx_ring; |
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409 struct igb_ring test_rx_ring; |
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410 |
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411 int msg_enable; |
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412 |
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413 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
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414 u32 eims_enable_mask; |
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415 u32 eims_other; |
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416 |
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417 /* to not mess up cache alignment, always add to the bottom */ |
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418 u16 tx_ring_count; |
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419 u16 rx_ring_count; |
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420 unsigned int vfs_allocated_count; |
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421 struct vf_data_storage *vf_data; |
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422 int vf_rate_link_speed; |
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423 u32 rss_queues; |
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424 u32 wvbr; |
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425 u32 *shadow_vfta; |
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426 |
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427 struct ptp_clock *ptp_clock; |
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428 struct ptp_clock_info ptp_caps; |
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429 struct delayed_work ptp_overflow_work; |
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430 struct work_struct ptp_tx_work; |
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431 struct sk_buff *ptp_tx_skb; |
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432 struct hwtstamp_config tstamp_config; |
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433 unsigned long ptp_tx_start; |
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434 unsigned long last_rx_ptp_check; |
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435 unsigned long last_rx_timestamp; |
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436 spinlock_t tmreg_lock; |
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437 struct cyclecounter cc; |
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438 struct timecounter tc; |
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439 u32 tx_hwtstamp_timeouts; |
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440 u32 rx_hwtstamp_cleared; |
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441 |
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442 char fw_version[32]; |
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443 #ifdef CONFIG_IGB_HWMON |
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444 struct hwmon_buff *igb_hwmon_buff; |
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445 bool ets; |
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446 #endif |
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447 struct i2c_algo_bit_data i2c_algo; |
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448 struct i2c_adapter i2c_adap; |
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449 struct i2c_client *i2c_client; |
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450 u32 rss_indir_tbl_init; |
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451 u8 rss_indir_tbl[IGB_RETA_SIZE]; |
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452 |
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453 unsigned long link_check_timeout; |
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454 int copper_tries; |
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455 struct e1000_info ei; |
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456 u16 eee_advert; |
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457 }; |
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458 |
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459 #define IGB_FLAG_HAS_MSI (1 << 0) |
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460 #define IGB_FLAG_DCA_ENABLED (1 << 1) |
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461 #define IGB_FLAG_QUAD_PORT_A (1 << 2) |
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462 #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
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463 #define IGB_FLAG_DMAC (1 << 4) |
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464 #define IGB_FLAG_PTP (1 << 5) |
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465 #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) |
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466 #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) |
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467 #define IGB_FLAG_WOL_SUPPORTED (1 << 8) |
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468 #define IGB_FLAG_NEED_LINK_UPDATE (1 << 9) |
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469 #define IGB_FLAG_MEDIA_RESET (1 << 10) |
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470 #define IGB_FLAG_MAS_CAPABLE (1 << 11) |
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471 #define IGB_FLAG_MAS_ENABLE (1 << 12) |
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472 #define IGB_FLAG_HAS_MSIX (1 << 13) |
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473 #define IGB_FLAG_EEE (1 << 14) |
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474 |
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475 /* Media Auto Sense */ |
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476 #define IGB_MAS_ENABLE_0 0X0001 |
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477 #define IGB_MAS_ENABLE_1 0X0002 |
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478 #define IGB_MAS_ENABLE_2 0X0004 |
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479 #define IGB_MAS_ENABLE_3 0X0008 |
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480 |
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481 /* DMA Coalescing defines */ |
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482 #define IGB_MIN_TXPBSIZE 20408 |
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483 #define IGB_TX_BUF_4096 4096 |
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484 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ |
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485 |
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486 #define IGB_82576_TSYNC_SHIFT 19 |
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487 #define IGB_TS_HDR_LEN 16 |
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488 enum e1000_state_t { |
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489 __IGB_TESTING, |
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490 __IGB_RESETTING, |
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491 __IGB_DOWN, |
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492 __IGB_PTP_TX_IN_PROGRESS, |
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493 }; |
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494 |
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495 enum igb_boards { |
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496 board_82575, |
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497 }; |
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498 |
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499 extern char igb_driver_name[]; |
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500 extern char igb_driver_version[]; |
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501 |
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502 int igb_up(struct igb_adapter *); |
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503 void igb_down(struct igb_adapter *); |
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504 void igb_reinit_locked(struct igb_adapter *); |
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505 void igb_reset(struct igb_adapter *); |
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506 int igb_reinit_queues(struct igb_adapter *); |
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507 void igb_write_rss_indir_tbl(struct igb_adapter *); |
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508 int igb_set_spd_dplx(struct igb_adapter *, u32, u8); |
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509 int igb_setup_tx_resources(struct igb_ring *); |
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510 int igb_setup_rx_resources(struct igb_ring *); |
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511 void igb_free_tx_resources(struct igb_ring *); |
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512 void igb_free_rx_resources(struct igb_ring *); |
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513 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
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514 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); |
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515 void igb_setup_tctl(struct igb_adapter *); |
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516 void igb_setup_rctl(struct igb_adapter *); |
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517 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); |
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518 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *); |
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519 void igb_alloc_rx_buffers(struct igb_ring *, u16); |
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520 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); |
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521 bool igb_has_link(struct igb_adapter *adapter); |
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522 void igb_set_ethtool_ops(struct net_device *); |
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523 void igb_power_up_link(struct igb_adapter *); |
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524 void igb_set_fw_version(struct igb_adapter *); |
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525 void igb_ptp_init(struct igb_adapter *adapter); |
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526 void igb_ptp_stop(struct igb_adapter *adapter); |
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527 void igb_ptp_reset(struct igb_adapter *adapter); |
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528 void igb_ptp_rx_hang(struct igb_adapter *adapter); |
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529 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); |
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530 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va, |
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531 struct sk_buff *skb); |
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532 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); |
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533 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); |
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534 #ifdef CONFIG_IGB_HWMON |
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535 void igb_sysfs_exit(struct igb_adapter *adapter); |
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536 int igb_sysfs_init(struct igb_adapter *adapter); |
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537 #endif |
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538 static inline s32 igb_reset_phy(struct e1000_hw *hw) |
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539 { |
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540 if (hw->phy.ops.reset) |
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541 return hw->phy.ops.reset(hw); |
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542 |
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543 return 0; |
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544 } |
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545 |
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546 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
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547 { |
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548 if (hw->phy.ops.read_reg) |
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549 return hw->phy.ops.read_reg(hw, offset, data); |
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550 |
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551 return 0; |
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552 } |
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553 |
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554 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) |
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555 { |
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556 if (hw->phy.ops.write_reg) |
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557 return hw->phy.ops.write_reg(hw, offset, data); |
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558 |
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559 return 0; |
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560 } |
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561 |
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562 static inline s32 igb_get_phy_info(struct e1000_hw *hw) |
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563 { |
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564 if (hw->phy.ops.get_phy_info) |
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565 return hw->phy.ops.get_phy_info(hw); |
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566 |
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567 return 0; |
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568 } |
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569 |
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570 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) |
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571 { |
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572 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); |
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573 } |
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574 |
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575 #endif /* _IGB_H_ */ |