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1 /* Intel(R) Gigabit Ethernet Linux driver |
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2 * Copyright(c) 2007-2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * You should have received a copy of the GNU General Public License along with |
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14 * this program; if not, see <http://www.gnu.org/licenses/>. |
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15 * |
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16 * The full GNU General Public License is included in this distribution in |
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17 * the file called "COPYING". |
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18 * |
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19 * Contact Information: |
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20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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22 */ |
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23 |
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24 #ifndef _E1000_PHY_H_ |
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25 #define _E1000_PHY_H_ |
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26 |
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27 enum e1000_ms_type { |
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28 e1000_ms_hw_default = 0, |
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29 e1000_ms_force_master, |
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30 e1000_ms_force_slave, |
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31 e1000_ms_auto |
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32 }; |
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33 |
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34 enum e1000_smart_speed { |
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35 e1000_smart_speed_default = 0, |
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36 e1000_smart_speed_on, |
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37 e1000_smart_speed_off |
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38 }; |
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39 |
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40 s32 igb_check_downshift(struct e1000_hw *hw); |
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41 s32 igb_check_reset_block(struct e1000_hw *hw); |
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42 s32 igb_copper_link_setup_igp(struct e1000_hw *hw); |
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43 s32 igb_copper_link_setup_m88(struct e1000_hw *hw); |
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44 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw); |
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45 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); |
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46 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
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47 s32 igb_get_cable_length_m88(struct e1000_hw *hw); |
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48 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw); |
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49 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); |
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50 s32 igb_get_phy_id(struct e1000_hw *hw); |
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51 s32 igb_get_phy_info_igp(struct e1000_hw *hw); |
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52 s32 igb_get_phy_info_m88(struct e1000_hw *hw); |
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53 s32 igb_phy_sw_reset(struct e1000_hw *hw); |
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54 s32 igb_phy_hw_reset(struct e1000_hw *hw); |
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55 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
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56 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
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57 s32 igb_setup_copper_link(struct e1000_hw *hw); |
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58 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
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59 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, |
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60 u32 usec_interval, bool *success); |
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61 void igb_power_up_phy_copper(struct e1000_hw *hw); |
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62 void igb_power_down_phy_copper(struct e1000_hw *hw); |
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63 s32 igb_phy_init_script_igp3(struct e1000_hw *hw); |
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64 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); |
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65 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); |
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66 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); |
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67 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); |
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68 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); |
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69 s32 igb_copper_link_setup_82580(struct e1000_hw *hw); |
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70 s32 igb_get_phy_info_82580(struct e1000_hw *hw); |
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71 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); |
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72 s32 igb_get_cable_length_82580(struct e1000_hw *hw); |
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73 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); |
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74 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); |
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75 s32 igb_check_polarity_m88(struct e1000_hw *hw); |
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76 |
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77 /* IGP01E1000 Specific Registers */ |
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78 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ |
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79 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ |
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80 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ |
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81 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
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82 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
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83 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
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84 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
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85 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
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86 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
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87 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ |
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88 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
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89 |
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90 #define I82580_ADDR_REG 16 |
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91 #define I82580_CFG_REG 22 |
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92 #define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15) |
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93 #define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ |
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94 #define I82580_CTRL_REG 23 |
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95 #define I82580_CTRL_DOWNSHIFT_MASK (7 << 10) |
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96 |
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97 /* 82580 specific PHY registers */ |
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98 #define I82580_PHY_CTRL_2 18 |
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99 #define I82580_PHY_LBK_CTRL 19 |
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100 #define I82580_PHY_STATUS_2 26 |
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101 #define I82580_PHY_DIAG_STATUS 31 |
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102 |
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103 /* I82580 PHY Status 2 */ |
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104 #define I82580_PHY_STATUS2_REV_POLARITY 0x0400 |
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105 #define I82580_PHY_STATUS2_MDIX 0x0800 |
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106 #define I82580_PHY_STATUS2_SPEED_MASK 0x0300 |
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107 #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
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108 #define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100 |
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109 |
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110 /* I82580 PHY Control 2 */ |
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111 #define I82580_PHY_CTRL2_MANUAL_MDIX 0x0200 |
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112 #define I82580_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 |
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113 #define I82580_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
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114 |
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115 /* I82580 PHY Diagnostics Status */ |
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116 #define I82580_DSTATUS_CABLE_LENGTH 0x03FC |
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117 #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2 |
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118 |
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119 /* 82580 PHY Power Management */ |
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120 #define E1000_82580_PHY_POWER_MGMT 0xE14 |
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121 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ |
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122 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ |
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123 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ |
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124 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ |
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125 |
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126 /* Enable flexible speed on link-up */ |
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127 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ |
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128 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ |
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129 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
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130 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
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131 #define IGP01E1000_PSSR_MDIX 0x0800 |
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132 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
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133 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
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134 #define IGP02E1000_PHY_CHANNEL_NUM 4 |
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135 #define IGP02E1000_PHY_AGC_A 0x11B1 |
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136 #define IGP02E1000_PHY_AGC_B 0x12B1 |
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137 #define IGP02E1000_PHY_AGC_C 0x14B1 |
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138 #define IGP02E1000_PHY_AGC_D 0x18B1 |
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139 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ |
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140 #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
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141 #define IGP02E1000_AGC_RANGE 15 |
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142 |
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143 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
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144 |
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145 /* GS40G - I210 PHY defines */ |
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146 #define GS40G_PAGE_SELECT 0x16 |
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147 #define GS40G_PAGE_SHIFT 16 |
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148 #define GS40G_OFFSET_MASK 0xFFFF |
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149 #define GS40G_PAGE_2 0x20000 |
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150 #define GS40G_MAC_REG2 0x15 |
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151 #define GS40G_MAC_LB 0x4140 |
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152 #define GS40G_MAC_SPEED_1G 0X0006 |
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153 #define GS40G_COPPER_SPEC 0x0010 |
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154 #define GS40G_LINE_LB 0x4000 |
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155 |
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156 /* SFP modules ID memory locations */ |
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157 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 |
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158 #define E1000_SFF_IDENTIFIER_SFF 0x02 |
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159 #define E1000_SFF_IDENTIFIER_SFP 0x03 |
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160 |
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161 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 |
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162 /* Flags for SFP modules compatible with ETH up to 1Gb */ |
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163 struct e1000_sfp_flags { |
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164 u8 e1000_base_sx:1; |
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165 u8 e1000_base_lx:1; |
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166 u8 e1000_base_cx:1; |
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167 u8 e1000_base_t:1; |
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168 u8 e100_base_lx:1; |
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169 u8 e100_base_fx:1; |
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170 u8 e10_base_bx10:1; |
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171 u8 e10_base_px:1; |
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172 }; |
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173 |
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174 #endif |