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1 /* Intel(R) Gigabit Ethernet Linux driver |
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2 * Copyright(c) 2007-2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * |
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7 * This program is distributed in the hope it will be useful, but WITHOUT |
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8 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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9 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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10 * more details. |
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11 * |
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12 * You should have received a copy of the GNU General Public License along with |
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13 * this program; if not, see <http://www.gnu.org/licenses/>. |
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14 * |
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15 * The full GNU General Public License is included in this distribution in |
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16 * the file called "COPYING". |
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17 * |
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18 * Contact Information: |
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19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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21 */ |
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22 |
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23 #ifndef _E1000_HW_H_ |
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24 #define _E1000_HW_H_ |
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25 |
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26 #include <linux/types.h> |
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27 #include <linux/delay.h> |
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28 #include <linux/io.h> |
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29 #include <linux/netdevice.h> |
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30 |
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31 #include "e1000_regs.h" |
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32 #include "e1000_defines.h" |
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33 |
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34 struct e1000_hw; |
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35 |
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36 #define E1000_DEV_ID_82576 0x10C9 |
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37 #define E1000_DEV_ID_82576_FIBER 0x10E6 |
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38 #define E1000_DEV_ID_82576_SERDES 0x10E7 |
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39 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 |
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40 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 |
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41 #define E1000_DEV_ID_82576_NS 0x150A |
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42 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 |
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43 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D |
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44 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 |
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45 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 |
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46 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 |
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47 #define E1000_DEV_ID_82580_COPPER 0x150E |
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48 #define E1000_DEV_ID_82580_FIBER 0x150F |
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49 #define E1000_DEV_ID_82580_SERDES 0x1510 |
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50 #define E1000_DEV_ID_82580_SGMII 0x1511 |
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51 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 |
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52 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 |
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53 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 |
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54 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A |
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55 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C |
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56 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 |
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57 #define E1000_DEV_ID_I350_COPPER 0x1521 |
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58 #define E1000_DEV_ID_I350_FIBER 0x1522 |
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59 #define E1000_DEV_ID_I350_SERDES 0x1523 |
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60 #define E1000_DEV_ID_I350_SGMII 0x1524 |
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61 #define E1000_DEV_ID_I210_COPPER 0x1533 |
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62 #define E1000_DEV_ID_I210_FIBER 0x1536 |
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63 #define E1000_DEV_ID_I210_SERDES 0x1537 |
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64 #define E1000_DEV_ID_I210_SGMII 0x1538 |
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65 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B |
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66 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C |
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67 #define E1000_DEV_ID_I211_COPPER 0x1539 |
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68 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 |
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69 #define E1000_DEV_ID_I354_SGMII 0x1F41 |
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70 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 |
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71 |
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72 #define E1000_REVISION_2 2 |
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73 #define E1000_REVISION_4 4 |
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74 |
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75 #define E1000_FUNC_0 0 |
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76 #define E1000_FUNC_1 1 |
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77 #define E1000_FUNC_2 2 |
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78 #define E1000_FUNC_3 3 |
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79 |
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80 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 |
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81 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 |
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82 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 |
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83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 |
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84 |
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85 enum e1000_mac_type { |
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86 e1000_undefined = 0, |
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87 e1000_82575, |
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88 e1000_82576, |
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89 e1000_82580, |
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90 e1000_i350, |
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91 e1000_i354, |
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92 e1000_i210, |
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93 e1000_i211, |
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94 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ |
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95 }; |
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96 |
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97 enum e1000_media_type { |
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98 e1000_media_type_unknown = 0, |
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99 e1000_media_type_copper = 1, |
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100 e1000_media_type_fiber = 2, |
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101 e1000_media_type_internal_serdes = 3, |
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102 e1000_num_media_types |
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103 }; |
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104 |
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105 enum e1000_nvm_type { |
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106 e1000_nvm_unknown = 0, |
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107 e1000_nvm_none, |
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108 e1000_nvm_eeprom_spi, |
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109 e1000_nvm_flash_hw, |
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110 e1000_nvm_invm, |
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111 e1000_nvm_flash_sw |
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112 }; |
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113 |
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114 enum e1000_nvm_override { |
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115 e1000_nvm_override_none = 0, |
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116 e1000_nvm_override_spi_small, |
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117 e1000_nvm_override_spi_large, |
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118 }; |
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119 |
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120 enum e1000_phy_type { |
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121 e1000_phy_unknown = 0, |
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122 e1000_phy_none, |
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123 e1000_phy_m88, |
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124 e1000_phy_igp, |
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125 e1000_phy_igp_2, |
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126 e1000_phy_gg82563, |
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127 e1000_phy_igp_3, |
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128 e1000_phy_ife, |
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129 e1000_phy_82580, |
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130 e1000_phy_i210, |
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131 }; |
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132 |
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133 enum e1000_bus_type { |
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134 e1000_bus_type_unknown = 0, |
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135 e1000_bus_type_pci, |
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136 e1000_bus_type_pcix, |
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137 e1000_bus_type_pci_express, |
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138 e1000_bus_type_reserved |
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139 }; |
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140 |
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141 enum e1000_bus_speed { |
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142 e1000_bus_speed_unknown = 0, |
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143 e1000_bus_speed_33, |
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144 e1000_bus_speed_66, |
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145 e1000_bus_speed_100, |
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146 e1000_bus_speed_120, |
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147 e1000_bus_speed_133, |
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148 e1000_bus_speed_2500, |
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149 e1000_bus_speed_5000, |
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150 e1000_bus_speed_reserved |
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151 }; |
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152 |
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153 enum e1000_bus_width { |
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154 e1000_bus_width_unknown = 0, |
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155 e1000_bus_width_pcie_x1, |
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156 e1000_bus_width_pcie_x2, |
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157 e1000_bus_width_pcie_x4 = 4, |
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158 e1000_bus_width_pcie_x8 = 8, |
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159 e1000_bus_width_32, |
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160 e1000_bus_width_64, |
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161 e1000_bus_width_reserved |
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162 }; |
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163 |
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164 enum e1000_1000t_rx_status { |
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165 e1000_1000t_rx_status_not_ok = 0, |
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166 e1000_1000t_rx_status_ok, |
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167 e1000_1000t_rx_status_undefined = 0xFF |
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168 }; |
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169 |
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170 enum e1000_rev_polarity { |
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171 e1000_rev_polarity_normal = 0, |
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172 e1000_rev_polarity_reversed, |
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173 e1000_rev_polarity_undefined = 0xFF |
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174 }; |
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175 |
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176 enum e1000_fc_mode { |
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177 e1000_fc_none = 0, |
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178 e1000_fc_rx_pause, |
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179 e1000_fc_tx_pause, |
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180 e1000_fc_full, |
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181 e1000_fc_default = 0xFF |
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182 }; |
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183 |
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184 /* Statistics counters collected by the MAC */ |
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185 struct e1000_hw_stats { |
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186 u64 crcerrs; |
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187 u64 algnerrc; |
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188 u64 symerrs; |
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189 u64 rxerrc; |
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190 u64 mpc; |
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191 u64 scc; |
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192 u64 ecol; |
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193 u64 mcc; |
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194 u64 latecol; |
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195 u64 colc; |
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196 u64 dc; |
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197 u64 tncrs; |
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198 u64 sec; |
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199 u64 cexterr; |
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200 u64 rlec; |
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201 u64 xonrxc; |
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202 u64 xontxc; |
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203 u64 xoffrxc; |
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204 u64 xofftxc; |
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205 u64 fcruc; |
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206 u64 prc64; |
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207 u64 prc127; |
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208 u64 prc255; |
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209 u64 prc511; |
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210 u64 prc1023; |
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211 u64 prc1522; |
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212 u64 gprc; |
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213 u64 bprc; |
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214 u64 mprc; |
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215 u64 gptc; |
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216 u64 gorc; |
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217 u64 gotc; |
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218 u64 rnbc; |
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219 u64 ruc; |
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220 u64 rfc; |
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221 u64 roc; |
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222 u64 rjc; |
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223 u64 mgprc; |
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224 u64 mgpdc; |
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225 u64 mgptc; |
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226 u64 tor; |
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227 u64 tot; |
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228 u64 tpr; |
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229 u64 tpt; |
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230 u64 ptc64; |
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231 u64 ptc127; |
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232 u64 ptc255; |
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233 u64 ptc511; |
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234 u64 ptc1023; |
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235 u64 ptc1522; |
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236 u64 mptc; |
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237 u64 bptc; |
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238 u64 tsctc; |
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239 u64 tsctfc; |
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240 u64 iac; |
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241 u64 icrxptc; |
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242 u64 icrxatc; |
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243 u64 ictxptc; |
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244 u64 ictxatc; |
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245 u64 ictxqec; |
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246 u64 ictxqmtc; |
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247 u64 icrxdmtc; |
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248 u64 icrxoc; |
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249 u64 cbtmpc; |
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250 u64 htdpmc; |
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251 u64 cbrdpc; |
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252 u64 cbrmpc; |
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253 u64 rpthc; |
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254 u64 hgptc; |
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255 u64 htcbdpc; |
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256 u64 hgorc; |
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257 u64 hgotc; |
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258 u64 lenerrs; |
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259 u64 scvpc; |
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260 u64 hrmpc; |
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261 u64 doosync; |
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262 u64 o2bgptc; |
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263 u64 o2bspc; |
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264 u64 b2ospc; |
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265 u64 b2ogprc; |
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266 }; |
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267 |
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268 struct e1000_host_mng_dhcp_cookie { |
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269 u32 signature; |
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270 u8 status; |
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271 u8 reserved0; |
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272 u16 vlan_id; |
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273 u32 reserved1; |
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274 u16 reserved2; |
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275 u8 reserved3; |
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276 u8 checksum; |
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277 }; |
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278 |
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279 /* Host Interface "Rev 1" */ |
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280 struct e1000_host_command_header { |
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281 u8 command_id; |
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282 u8 command_length; |
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283 u8 command_options; |
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284 u8 checksum; |
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285 }; |
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286 |
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287 #define E1000_HI_MAX_DATA_LENGTH 252 |
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288 struct e1000_host_command_info { |
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289 struct e1000_host_command_header command_header; |
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290 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; |
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291 }; |
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292 |
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293 /* Host Interface "Rev 2" */ |
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294 struct e1000_host_mng_command_header { |
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295 u8 command_id; |
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296 u8 checksum; |
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297 u16 reserved1; |
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298 u16 reserved2; |
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299 u16 command_length; |
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300 }; |
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301 |
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302 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 |
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303 struct e1000_host_mng_command_info { |
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304 struct e1000_host_mng_command_header command_header; |
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305 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; |
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306 }; |
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307 |
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308 #include "e1000_mac.h" |
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309 #include "e1000_phy.h" |
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310 #include "e1000_nvm.h" |
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311 #include "e1000_mbx.h" |
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312 |
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313 struct e1000_mac_operations { |
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314 s32 (*check_for_link)(struct e1000_hw *); |
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315 s32 (*reset_hw)(struct e1000_hw *); |
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316 s32 (*init_hw)(struct e1000_hw *); |
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317 bool (*check_mng_mode)(struct e1000_hw *); |
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318 s32 (*setup_physical_interface)(struct e1000_hw *); |
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319 void (*rar_set)(struct e1000_hw *, u8 *, u32); |
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320 s32 (*read_mac_addr)(struct e1000_hw *); |
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321 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); |
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322 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); |
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323 void (*release_swfw_sync)(struct e1000_hw *, u16); |
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324 #ifdef CONFIG_IGB_HWMON |
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325 s32 (*get_thermal_sensor_data)(struct e1000_hw *); |
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326 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *); |
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327 #endif |
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328 |
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329 }; |
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330 |
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331 struct e1000_phy_operations { |
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332 s32 (*acquire)(struct e1000_hw *); |
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333 s32 (*check_polarity)(struct e1000_hw *); |
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334 s32 (*check_reset_block)(struct e1000_hw *); |
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335 s32 (*force_speed_duplex)(struct e1000_hw *); |
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336 s32 (*get_cfg_done)(struct e1000_hw *hw); |
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337 s32 (*get_cable_length)(struct e1000_hw *); |
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338 s32 (*get_phy_info)(struct e1000_hw *); |
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339 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); |
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340 void (*release)(struct e1000_hw *); |
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341 s32 (*reset)(struct e1000_hw *); |
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342 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
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343 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); |
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344 s32 (*write_reg)(struct e1000_hw *, u32, u16); |
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345 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); |
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346 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); |
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347 }; |
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348 |
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349 struct e1000_nvm_operations { |
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350 s32 (*acquire)(struct e1000_hw *); |
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351 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); |
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352 void (*release)(struct e1000_hw *); |
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353 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); |
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354 s32 (*update)(struct e1000_hw *); |
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355 s32 (*validate)(struct e1000_hw *); |
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356 s32 (*valid_led_default)(struct e1000_hw *, u16 *); |
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357 }; |
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358 |
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359 #define E1000_MAX_SENSORS 3 |
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360 |
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361 struct e1000_thermal_diode_data { |
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362 u8 location; |
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363 u8 temp; |
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364 u8 caution_thresh; |
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365 u8 max_op_thresh; |
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366 }; |
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367 |
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368 struct e1000_thermal_sensor_data { |
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369 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS]; |
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370 }; |
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371 |
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372 struct e1000_info { |
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373 s32 (*get_invariants)(struct e1000_hw *); |
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374 struct e1000_mac_operations *mac_ops; |
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375 struct e1000_phy_operations *phy_ops; |
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376 struct e1000_nvm_operations *nvm_ops; |
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377 }; |
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378 |
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379 extern const struct e1000_info e1000_82575_info; |
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380 |
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381 struct e1000_mac_info { |
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382 struct e1000_mac_operations ops; |
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383 |
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384 u8 addr[6]; |
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385 u8 perm_addr[6]; |
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386 |
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387 enum e1000_mac_type type; |
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388 |
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389 u32 ledctl_default; |
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390 u32 ledctl_mode1; |
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391 u32 ledctl_mode2; |
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392 u32 mc_filter_type; |
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393 u32 txcw; |
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394 |
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395 u16 mta_reg_count; |
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396 u16 uta_reg_count; |
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397 |
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398 /* Maximum size of the MTA register table in all supported adapters */ |
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399 #define MAX_MTA_REG 128 |
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400 u32 mta_shadow[MAX_MTA_REG]; |
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401 u16 rar_entry_count; |
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402 |
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403 u8 forced_speed_duplex; |
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404 |
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405 bool adaptive_ifs; |
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406 bool arc_subsystem_valid; |
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407 bool asf_firmware_present; |
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408 bool autoneg; |
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409 bool autoneg_failed; |
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410 bool disable_hw_init_bits; |
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411 bool get_link_status; |
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412 bool ifs_params_forced; |
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413 bool in_ifs_mode; |
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414 bool report_tx_early; |
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415 bool serdes_has_link; |
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416 bool tx_pkt_filtering; |
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417 struct e1000_thermal_sensor_data thermal_sensor_data; |
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418 }; |
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419 |
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420 struct e1000_phy_info { |
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421 struct e1000_phy_operations ops; |
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422 |
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423 enum e1000_phy_type type; |
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424 |
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425 enum e1000_1000t_rx_status local_rx; |
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426 enum e1000_1000t_rx_status remote_rx; |
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427 enum e1000_ms_type ms_type; |
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428 enum e1000_ms_type original_ms_type; |
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429 enum e1000_rev_polarity cable_polarity; |
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430 enum e1000_smart_speed smart_speed; |
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431 |
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432 u32 addr; |
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433 u32 id; |
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434 u32 reset_delay_us; /* in usec */ |
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435 u32 revision; |
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436 |
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437 enum e1000_media_type media_type; |
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438 |
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439 u16 autoneg_advertised; |
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440 u16 autoneg_mask; |
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441 u16 cable_length; |
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442 u16 max_cable_length; |
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443 u16 min_cable_length; |
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444 |
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445 u8 mdix; |
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446 |
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447 bool disable_polarity_correction; |
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448 bool is_mdix; |
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449 bool polarity_correction; |
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450 bool reset_disable; |
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451 bool speed_downgraded; |
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452 bool autoneg_wait_to_complete; |
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453 }; |
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454 |
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455 struct e1000_nvm_info { |
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456 struct e1000_nvm_operations ops; |
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457 enum e1000_nvm_type type; |
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458 enum e1000_nvm_override override; |
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459 |
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460 u32 flash_bank_size; |
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461 u32 flash_base_addr; |
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462 |
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463 u16 word_size; |
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464 u16 delay_usec; |
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465 u16 address_bits; |
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466 u16 opcode_bits; |
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467 u16 page_size; |
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468 }; |
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469 |
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470 struct e1000_bus_info { |
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471 enum e1000_bus_type type; |
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472 enum e1000_bus_speed speed; |
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473 enum e1000_bus_width width; |
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474 |
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475 u32 snoop; |
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476 |
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477 u16 func; |
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478 u16 pci_cmd_word; |
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479 }; |
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480 |
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481 struct e1000_fc_info { |
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482 u32 high_water; /* Flow control high-water mark */ |
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483 u32 low_water; /* Flow control low-water mark */ |
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484 u16 pause_time; /* Flow control pause timer */ |
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485 bool send_xon; /* Flow control send XON */ |
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486 bool strict_ieee; /* Strict IEEE mode */ |
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487 enum e1000_fc_mode current_mode; /* Type of flow control */ |
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488 enum e1000_fc_mode requested_mode; |
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489 }; |
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490 |
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491 struct e1000_mbx_operations { |
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492 s32 (*init_params)(struct e1000_hw *hw); |
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493 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); |
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494 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); |
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495 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); |
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496 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); |
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497 s32 (*check_for_msg)(struct e1000_hw *, u16); |
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498 s32 (*check_for_ack)(struct e1000_hw *, u16); |
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499 s32 (*check_for_rst)(struct e1000_hw *, u16); |
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500 }; |
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501 |
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502 struct e1000_mbx_stats { |
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503 u32 msgs_tx; |
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504 u32 msgs_rx; |
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505 |
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506 u32 acks; |
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507 u32 reqs; |
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508 u32 rsts; |
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509 }; |
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510 |
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511 struct e1000_mbx_info { |
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512 struct e1000_mbx_operations ops; |
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513 struct e1000_mbx_stats stats; |
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514 u32 timeout; |
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515 u32 usec_delay; |
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516 u16 size; |
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517 }; |
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518 |
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519 struct e1000_dev_spec_82575 { |
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520 bool sgmii_active; |
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521 bool global_device_reset; |
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522 bool eee_disable; |
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523 bool clear_semaphore_once; |
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524 struct e1000_sfp_flags eth_flags; |
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525 bool module_plugged; |
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526 u8 media_port; |
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527 bool media_changed; |
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528 bool mas_capable; |
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529 }; |
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530 |
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531 struct e1000_hw { |
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532 void *back; |
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533 |
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534 u8 __iomem *hw_addr; |
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535 u8 __iomem *flash_address; |
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536 unsigned long io_base; |
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537 |
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538 struct e1000_mac_info mac; |
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539 struct e1000_fc_info fc; |
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540 struct e1000_phy_info phy; |
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541 struct e1000_nvm_info nvm; |
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542 struct e1000_bus_info bus; |
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543 struct e1000_mbx_info mbx; |
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544 struct e1000_host_mng_dhcp_cookie mng_cookie; |
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545 |
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546 union { |
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547 struct e1000_dev_spec_82575 _82575; |
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548 } dev_spec; |
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549 |
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550 u16 device_id; |
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551 u16 subsystem_vendor_id; |
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552 u16 subsystem_device_id; |
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553 u16 vendor_id; |
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554 |
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555 u8 revision_id; |
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556 }; |
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557 |
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558 struct net_device *igb_get_hw_dev(struct e1000_hw *hw); |
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559 #define hw_dbg(format, arg...) \ |
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560 netdev_dbg(igb_get_hw_dev(hw), format, ##arg) |
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561 |
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562 /* These functions must be implemented by drivers */ |
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563 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); |
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564 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); |
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565 |
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566 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); |
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567 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); |
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568 #endif /* _E1000_HW_H_ */ |