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1 /* Intel(R) Gigabit Ethernet Linux driver |
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2 * Copyright(c) 2007-2014 Intel Corporation. |
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3 * |
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4 * This program is free software; you can redistribute it and/or modify it |
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5 * under the terms and conditions of the GNU General Public License, |
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6 * version 2, as published by the Free Software Foundation. |
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7 * |
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8 * This program is distributed in the hope it will be useful, but WITHOUT |
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9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 * more details. |
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12 * |
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13 * You should have received a copy of the GNU General Public License along with |
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14 * this program; if not, see <http://www.gnu.org/licenses/>. |
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15 * |
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16 * The full GNU General Public License is included in this distribution in |
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17 * the file called "COPYING". |
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18 * |
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19 * Contact Information: |
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20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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22 */ |
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23 |
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24 #ifndef _E1000_DEFINES_H_ |
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25 #define _E1000_DEFINES_H_ |
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26 |
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27 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
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28 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 |
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29 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 |
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30 |
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31 /* Definitions for power management and wakeup registers */ |
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32 /* Wake Up Control */ |
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33 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ |
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34 |
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35 /* Wake Up Filter Control */ |
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36 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ |
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37 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ |
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38 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
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39 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
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40 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
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41 |
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42 /* Extended Device Control */ |
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43 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */ |
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44 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ |
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45 #define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ |
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46 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */ |
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47 |
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48 /* Physical Func Reset Done Indication */ |
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49 #define E1000_CTRL_EXT_PFRSTD 0x00004000 |
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50 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ |
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51 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
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52 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
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53 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 |
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54 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 |
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55 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 |
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56 #define E1000_CTRL_EXT_EIAME 0x01000000 |
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57 #define E1000_CTRL_EXT_IRCA 0x00000001 |
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58 /* Interrupt delay cancellation */ |
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59 /* Driver loaded bit for FW */ |
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60 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 |
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61 /* Interrupt acknowledge Auto-mask */ |
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62 /* Clear Interrupt timers after IMS clear */ |
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63 /* packet buffer parity error detection enabled */ |
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64 /* descriptor FIFO parity error detection enable */ |
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65 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ |
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66 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 |
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67 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 |
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68 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 |
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69 #define E1000_I2CCMD_OPCODE_READ 0x08000000 |
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70 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 |
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71 #define E1000_I2CCMD_READY 0x20000000 |
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72 #define E1000_I2CCMD_ERROR 0x80000000 |
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73 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) |
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74 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) |
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75 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 |
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76 #define E1000_I2CCMD_PHY_TIMEOUT 200 |
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77 #define E1000_IVAR_VALID 0x80 |
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78 #define E1000_GPIE_NSICR 0x00000001 |
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79 #define E1000_GPIE_MSIX_MODE 0x00000010 |
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80 #define E1000_GPIE_EIAME 0x40000000 |
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81 #define E1000_GPIE_PBA 0x80000000 |
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82 |
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83 /* Receive Descriptor bit definitions */ |
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84 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
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85 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
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86 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
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87 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
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88 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
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89 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
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90 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ |
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91 |
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92 #define E1000_RXDEXT_STATERR_LB 0x00040000 |
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93 #define E1000_RXDEXT_STATERR_CE 0x01000000 |
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94 #define E1000_RXDEXT_STATERR_SE 0x02000000 |
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95 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 |
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96 #define E1000_RXDEXT_STATERR_CXE 0x10000000 |
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97 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 |
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98 #define E1000_RXDEXT_STATERR_IPE 0x40000000 |
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99 #define E1000_RXDEXT_STATERR_RXE 0x80000000 |
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100 |
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101 /* Same mask, but for extended and packet split descriptors */ |
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102 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ |
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103 E1000_RXDEXT_STATERR_CE | \ |
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104 E1000_RXDEXT_STATERR_SE | \ |
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105 E1000_RXDEXT_STATERR_SEQ | \ |
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106 E1000_RXDEXT_STATERR_CXE | \ |
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107 E1000_RXDEXT_STATERR_RXE) |
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108 |
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109 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 |
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110 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 |
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111 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 |
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112 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 |
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113 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 |
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114 |
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115 |
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116 /* Management Control */ |
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117 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ |
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118 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ |
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119 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ |
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120 /* Enable Neighbor Discovery Filtering */ |
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121 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
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122 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ |
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123 /* Enable MAC address filtering */ |
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124 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 |
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125 |
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126 /* Receive Control */ |
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127 #define E1000_RCTL_EN 0x00000002 /* enable */ |
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128 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ |
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129 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ |
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130 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ |
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131 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ |
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132 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
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133 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
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134 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ |
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135 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
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136 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
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137 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ |
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138 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ |
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139 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
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140 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ |
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141 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ |
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142 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
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143 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ |
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144 |
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145 /* Use byte values for the following shift parameters |
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146 * Usage: |
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147 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & |
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148 * E1000_PSRCTL_BSIZE0_MASK) | |
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149 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & |
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150 * E1000_PSRCTL_BSIZE1_MASK) | |
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151 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & |
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152 * E1000_PSRCTL_BSIZE2_MASK) | |
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153 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; |
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154 * E1000_PSRCTL_BSIZE3_MASK)) |
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155 * where value0 = [128..16256], default=256 |
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156 * value1 = [1024..64512], default=4096 |
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157 * value2 = [0..64512], default=4096 |
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158 * value3 = [0..64512], default=0 |
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159 */ |
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160 |
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161 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F |
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162 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 |
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163 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 |
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164 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 |
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165 |
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166 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ |
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167 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ |
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168 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ |
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169 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ |
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170 |
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171 /* SWFW_SYNC Definitions */ |
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172 #define E1000_SWFW_EEP_SM 0x1 |
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173 #define E1000_SWFW_PHY0_SM 0x2 |
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174 #define E1000_SWFW_PHY1_SM 0x4 |
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175 #define E1000_SWFW_PHY2_SM 0x20 |
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176 #define E1000_SWFW_PHY3_SM 0x40 |
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177 |
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178 /* FACTPS Definitions */ |
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179 /* Device Control */ |
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180 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
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181 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ |
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182 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
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183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
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184 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
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185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
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186 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ |
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187 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ |
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188 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ |
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189 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
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190 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
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191 /* Defined polarity of Dock/Undock indication in SDP[0] */ |
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192 /* Reset both PHY ports, through PHYRST_N pin */ |
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193 /* enable link status from external LINK_0 and LINK_1 pins */ |
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194 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
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195 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
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196 #define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ |
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197 #define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ |
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198 #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
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199 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ |
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200 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ |
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201 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ |
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202 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ |
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203 /* Initiate an interrupt to manageability engine */ |
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204 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ |
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205 |
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206 /* Bit definitions for the Management Data IO (MDIO) and Management Data |
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207 * Clock (MDC) pins in the Device Control Register. |
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208 */ |
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209 |
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210 #define E1000_CONNSW_ENRGSRC 0x4 |
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211 #define E1000_CONNSW_PHYSD 0x400 |
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212 #define E1000_CONNSW_PHY_PDN 0x800 |
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213 #define E1000_CONNSW_SERDESD 0x200 |
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214 #define E1000_CONNSW_AUTOSENSE_CONF 0x2 |
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215 #define E1000_CONNSW_AUTOSENSE_EN 0x1 |
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216 #define E1000_PCS_CFG_PCS_EN 8 |
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217 #define E1000_PCS_LCTL_FLV_LINK_UP 1 |
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218 #define E1000_PCS_LCTL_FSV_100 2 |
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219 #define E1000_PCS_LCTL_FSV_1000 4 |
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220 #define E1000_PCS_LCTL_FDV_FULL 8 |
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221 #define E1000_PCS_LCTL_FSD 0x10 |
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222 #define E1000_PCS_LCTL_FORCE_LINK 0x20 |
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223 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 |
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224 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 |
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225 #define E1000_PCS_LCTL_AN_RESTART 0x20000 |
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226 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 |
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227 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 |
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228 |
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229 #define E1000_PCS_LSTS_LINK_OK 1 |
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230 #define E1000_PCS_LSTS_SPEED_100 2 |
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231 #define E1000_PCS_LSTS_SPEED_1000 4 |
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232 #define E1000_PCS_LSTS_DUPLEX_FULL 8 |
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233 #define E1000_PCS_LSTS_SYNK_OK 0x10 |
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234 |
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235 /* Device Status */ |
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236 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ |
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237 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ |
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238 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ |
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239 #define E1000_STATUS_FUNC_SHIFT 2 |
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240 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ |
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241 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ |
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242 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ |
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243 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ |
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244 /* Change in Dock/Undock state. Clear on write '0'. */ |
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245 /* Status of Master requests. */ |
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246 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 |
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247 /* BMC external code execution disabled */ |
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248 |
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249 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ |
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250 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ |
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251 /* Constants used to intrepret the masked PCI-X bus speed. */ |
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252 |
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253 #define SPEED_10 10 |
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254 #define SPEED_100 100 |
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255 #define SPEED_1000 1000 |
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256 #define SPEED_2500 2500 |
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257 #define HALF_DUPLEX 1 |
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258 #define FULL_DUPLEX 2 |
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259 |
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260 |
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261 #define ADVERTISE_10_HALF 0x0001 |
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262 #define ADVERTISE_10_FULL 0x0002 |
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263 #define ADVERTISE_100_HALF 0x0004 |
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264 #define ADVERTISE_100_FULL 0x0008 |
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265 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ |
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266 #define ADVERTISE_1000_FULL 0x0020 |
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267 |
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268 /* 1000/H is not supported, nor spec-compliant. */ |
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269 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ |
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270 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ |
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271 ADVERTISE_1000_FULL) |
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272 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ |
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273 ADVERTISE_100_HALF | ADVERTISE_100_FULL) |
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274 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) |
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275 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) |
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276 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ |
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277 ADVERTISE_1000_FULL) |
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278 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) |
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279 |
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280 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX |
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281 |
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282 /* LED Control */ |
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283 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
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284 #define E1000_LEDCTL_LED0_BLINK 0x00000080 |
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285 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F |
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286 #define E1000_LEDCTL_LED0_IVRT 0x00000040 |
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287 |
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288 #define E1000_LEDCTL_MODE_LED_ON 0xE |
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289 #define E1000_LEDCTL_MODE_LED_OFF 0xF |
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290 |
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291 /* Transmit Descriptor bit definitions */ |
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292 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
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293 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
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294 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
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295 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
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296 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ |
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297 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
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298 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
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299 /* Extended desc bits for Linksec and timesync */ |
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300 |
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301 /* Transmit Control */ |
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302 #define E1000_TCTL_EN 0x00000002 /* enable tx */ |
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303 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ |
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304 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ |
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305 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ |
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306 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ |
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307 |
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308 /* DMA Coalescing register fields */ |
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309 #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */ |
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310 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */ |
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311 #define E1000_DMACR_DMACTHR_SHIFT 16 |
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312 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */ |
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313 #define E1000_DMACR_DMAC_LX_SHIFT 28 |
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314 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ |
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315 /* DMA Coalescing BMC-to-OS Watchdog Enable */ |
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316 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 |
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317 |
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318 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */ |
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319 |
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320 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ |
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321 |
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322 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */ |
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323 #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */ |
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324 |
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325 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */ |
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326 |
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327 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */ |
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328 #define E1000_FCRTC_RTH_COAL_SHIFT 4 |
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329 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ |
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330 |
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331 /* Timestamp in Rx buffer */ |
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332 #define E1000_RXPBS_CFG_TS_EN 0x80000000 |
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333 |
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334 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ |
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335 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ |
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336 |
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337 /* SerDes Control */ |
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338 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 |
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339 |
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340 /* Receive Checksum Control */ |
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341 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ |
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342 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
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343 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ |
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344 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
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345 |
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346 /* Header split receive */ |
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347 #define E1000_RFCTL_LEF 0x00040000 |
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348 |
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349 /* Collision related configuration parameters */ |
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350 #define E1000_COLLISION_THRESHOLD 15 |
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351 #define E1000_CT_SHIFT 4 |
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352 #define E1000_COLLISION_DISTANCE 63 |
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353 #define E1000_COLD_SHIFT 12 |
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354 |
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355 /* Ethertype field values */ |
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356 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ |
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357 |
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358 #define MAX_JUMBO_FRAME_SIZE 0x3F00 |
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359 |
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360 /* PBA constants */ |
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361 #define E1000_PBA_34K 0x0022 |
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362 #define E1000_PBA_64K 0x0040 /* 64KB */ |
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363 |
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364 /* SW Semaphore Register */ |
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365 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ |
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366 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ |
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367 |
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368 /* Interrupt Cause Read */ |
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369 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ |
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370 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
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371 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ |
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372 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ |
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373 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
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374 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ |
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375 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ |
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376 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ |
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377 /* If this bit asserted, the driver should claim the interrupt */ |
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378 #define E1000_ICR_INT_ASSERTED 0x80000000 |
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379 /* LAN connected device generates an interrupt */ |
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380 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ |
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381 |
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382 /* Extended Interrupt Cause Read */ |
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383 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ |
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384 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ |
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385 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ |
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386 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ |
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387 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ |
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388 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ |
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389 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ |
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390 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ |
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391 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ |
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392 /* TCP Timer */ |
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393 |
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394 /* This defines the bits that are set in the Interrupt Mask |
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395 * Set/Read Register. Each bit is documented below: |
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396 * o RXT0 = Receiver Timer Interrupt (ring 0) |
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397 * o TXDW = Transmit Descriptor Written Back |
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398 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) |
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399 * o RXSEQ = Receive Sequence Error |
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400 * o LSC = Link Status Change |
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401 */ |
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402 #define IMS_ENABLE_MASK ( \ |
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403 E1000_IMS_RXT0 | \ |
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404 E1000_IMS_TXDW | \ |
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405 E1000_IMS_RXDMT0 | \ |
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406 E1000_IMS_RXSEQ | \ |
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407 E1000_IMS_LSC | \ |
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408 E1000_IMS_DOUTSYNC) |
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409 |
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410 /* Interrupt Mask Set */ |
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411 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
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412 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ |
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413 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ |
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414 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ |
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415 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
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416 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
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417 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
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418 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ |
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419 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ |
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420 |
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421 /* Extended Interrupt Mask Set */ |
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422 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ |
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423 |
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424 /* Interrupt Cause Set */ |
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425 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
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426 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
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427 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ |
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428 |
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429 /* Extended Interrupt Cause Set */ |
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430 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ |
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431 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ |
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432 |
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433 |
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434 /* Transmit Descriptor Control */ |
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435 /* Enable the counting of descriptors still to be processed. */ |
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436 |
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437 /* Flow Control Constants */ |
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438 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 |
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439 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 |
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440 #define FLOW_CONTROL_TYPE 0x8808 |
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441 |
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442 /* Transmit Config Word */ |
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443 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ |
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444 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ |
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445 |
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446 /* 802.1q VLAN Packet Size */ |
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447 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ |
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448 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ |
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449 |
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450 /* Receive Address */ |
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451 /* Number of high/low register pairs in the RAR. The RAR (Receive Address |
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452 * Registers) holds the directed and multicast addresses that we monitor. |
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453 * Technically, we have 16 spots. However, we reserve one of these spots |
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454 * (RAR[15]) for our directed address used by controllers with |
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455 * manageability enabled, allowing us room for 15 multicast addresses. |
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456 */ |
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457 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ |
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458 #define E1000_RAL_MAC_ADDR_LEN 4 |
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459 #define E1000_RAH_MAC_ADDR_LEN 2 |
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460 #define E1000_RAH_POOL_MASK 0x03FC0000 |
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461 #define E1000_RAH_POOL_1 0x00040000 |
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462 |
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463 /* Error Codes */ |
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464 #define E1000_ERR_NVM 1 |
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465 #define E1000_ERR_PHY 2 |
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466 #define E1000_ERR_CONFIG 3 |
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467 #define E1000_ERR_PARAM 4 |
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468 #define E1000_ERR_MAC_INIT 5 |
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469 #define E1000_ERR_RESET 9 |
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470 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 |
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471 #define E1000_BLK_PHY_RESET 12 |
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472 #define E1000_ERR_SWFW_SYNC 13 |
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473 #define E1000_NOT_IMPLEMENTED 14 |
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474 #define E1000_ERR_MBX 15 |
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475 #define E1000_ERR_INVALID_ARGUMENT 16 |
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476 #define E1000_ERR_NO_SPACE 17 |
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477 #define E1000_ERR_NVM_PBA_SECTION 18 |
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478 #define E1000_ERR_INVM_VALUE_NOT_FOUND 19 |
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479 #define E1000_ERR_I2C 20 |
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480 |
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481 /* Loop limit on how long we wait for auto-negotiation to complete */ |
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482 #define COPPER_LINK_UP_LIMIT 10 |
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483 #define PHY_AUTO_NEG_LIMIT 45 |
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484 #define PHY_FORCE_LIMIT 20 |
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485 /* Number of 100 microseconds we wait for PCI Express master disable */ |
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486 #define MASTER_DISABLE_TIMEOUT 800 |
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487 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ |
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488 #define PHY_CFG_TIMEOUT 100 |
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489 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ |
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490 /* Number of milliseconds for NVM auto read done after MAC reset. */ |
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491 #define AUTO_READ_DONE_TIMEOUT 10 |
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492 |
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493 /* Flow Control */ |
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494 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
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495 |
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496 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ |
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497 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ |
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498 |
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499 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ |
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500 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ |
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501 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 |
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502 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 |
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503 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 |
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504 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 |
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505 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A |
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506 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ |
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507 |
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508 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF |
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509 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 |
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510 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 |
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511 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 |
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512 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 |
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513 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 |
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514 |
|
515 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 |
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516 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 |
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517 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 |
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518 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 |
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519 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 |
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520 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 |
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521 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 |
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522 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 |
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523 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 |
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524 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 |
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525 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 |
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526 |
|
527 #define E1000_TIMINCA_16NS_SHIFT 24 |
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528 |
|
529 /* Time Sync Interrupt Cause/Mask Register Bits */ |
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530 |
|
531 #define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ |
|
532 #define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ |
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533 #define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */ |
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534 #define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ |
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535 #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ |
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536 #define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ |
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537 #define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ |
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538 #define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */ |
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539 |
|
540 #define TSYNC_INTERRUPTS TSINTR_TXTS |
|
541 #define E1000_TSICR_TXTS TSINTR_TXTS |
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542 |
|
543 /* TSAUXC Configuration Bits */ |
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544 #define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ |
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545 #define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ |
|
546 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ |
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547 #define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */ |
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548 #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ |
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549 #define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ |
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550 #define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */ |
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551 #define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ |
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552 #define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ |
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553 #define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */ |
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554 #define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ |
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555 #define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */ |
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556 #define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */ |
|
557 #define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */ |
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558 |
|
559 /* SDP Configuration Bits */ |
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560 #define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */ |
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561 #define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */ |
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562 #define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */ |
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563 #define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */ |
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564 #define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */ |
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565 #define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */ |
|
566 #define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */ |
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567 #define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */ |
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568 #define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */ |
|
569 #define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */ |
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570 #define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */ |
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571 #define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */ |
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572 #define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */ |
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573 #define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */ |
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574 #define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */ |
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575 #define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */ |
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576 #define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */ |
|
577 #define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */ |
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578 #define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */ |
|
579 #define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */ |
|
580 #define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */ |
|
581 #define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */ |
|
582 #define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */ |
|
583 #define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */ |
|
584 #define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */ |
|
585 #define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */ |
|
586 #define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */ |
|
587 #define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */ |
|
588 #define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */ |
|
589 #define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */ |
|
590 |
|
591 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ |
|
592 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ |
|
593 #define E1000_MDICNFG_PHY_MASK 0x03E00000 |
|
594 #define E1000_MDICNFG_PHY_SHIFT 21 |
|
595 |
|
596 #define E1000_MEDIA_PORT_COPPER 1 |
|
597 #define E1000_MEDIA_PORT_OTHER 2 |
|
598 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 |
|
599 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 |
|
600 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ |
|
601 #define E1000_M88E1112_MAC_CTRL_1 0x10 |
|
602 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ |
|
603 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 |
|
604 #define E1000_M88E1112_PAGE_ADDR 0x16 |
|
605 #define E1000_M88E1112_STATUS 0x01 |
|
606 |
|
607 /* PCI Express Control */ |
|
608 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 |
|
609 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 |
|
610 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 |
|
611 #define E1000_GCR_CAP_VER2 0x00040000 |
|
612 |
|
613 /* mPHY Address Control and Data Registers */ |
|
614 #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ |
|
615 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 |
|
616 #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ |
|
617 |
|
618 /* mPHY PCS CLK Register */ |
|
619 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ |
|
620 /* mPHY Near End Digital Loopback Override Bit */ |
|
621 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 |
|
622 |
|
623 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 |
|
624 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 |
|
625 |
|
626 /* PHY Control Register */ |
|
627 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
|
628 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
|
629 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
|
630 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
|
631 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
|
632 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
|
633 #define MII_CR_SPEED_1000 0x0040 |
|
634 #define MII_CR_SPEED_100 0x2000 |
|
635 #define MII_CR_SPEED_10 0x0000 |
|
636 |
|
637 /* PHY Status Register */ |
|
638 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ |
|
639 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ |
|
640 |
|
641 /* Autoneg Advertisement Register */ |
|
642 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ |
|
643 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ |
|
644 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ |
|
645 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ |
|
646 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ |
|
647 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ |
|
648 |
|
649 /* Link Partner Ability Register (Base Page) */ |
|
650 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ |
|
651 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
|
652 |
|
653 /* Autoneg Expansion Register */ |
|
654 |
|
655 /* 1000BASE-T Control Register */ |
|
656 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
|
657 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
|
658 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
|
659 /* 0=Configure PHY as Slave */ |
|
660 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ |
|
661 /* 0=Automatic Master/Slave config */ |
|
662 |
|
663 /* 1000BASE-T Status Register */ |
|
664 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ |
|
665 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ |
|
666 |
|
667 |
|
668 /* PHY 1000 MII Register/Bit Definitions */ |
|
669 /* PHY Registers defined by IEEE */ |
|
670 #define PHY_CONTROL 0x00 /* Control Register */ |
|
671 #define PHY_STATUS 0x01 /* Status Register */ |
|
672 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
|
673 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
|
674 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
|
675 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ |
|
676 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ |
|
677 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ |
|
678 |
|
679 /* NVM Control */ |
|
680 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ |
|
681 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ |
|
682 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ |
|
683 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ |
|
684 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ |
|
685 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ |
|
686 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ |
|
687 /* NVM Addressing bits based on type 0=small, 1=large */ |
|
688 #define E1000_EECD_ADDR_BITS 0x00000400 |
|
689 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ |
|
690 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ |
|
691 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ |
|
692 #define E1000_EECD_SIZE_EX_SHIFT 11 |
|
693 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ |
|
694 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ |
|
695 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ |
|
696 #define E1000_FLUDONE_ATTEMPTS 20000 |
|
697 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ |
|
698 #define E1000_I210_FIFO_SEL_RX 0x00 |
|
699 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) |
|
700 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) |
|
701 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 |
|
702 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 |
|
703 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ |
|
704 /* Secure FLASH mode requires removing MSb */ |
|
705 #define E1000_I210_FW_PTR_MASK 0x7FFF |
|
706 /* Firmware code revision field word offset*/ |
|
707 #define E1000_I210_FW_VER_OFFSET 328 |
|
708 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ |
|
709 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ |
|
710 #define E1000_FLUDONE_ATTEMPTS 20000 |
|
711 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ |
|
712 #define E1000_I210_FIFO_SEL_RX 0x00 |
|
713 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) |
|
714 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) |
|
715 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 |
|
716 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 |
|
717 |
|
718 |
|
719 /* Offset to data in NVM read/write registers */ |
|
720 #define E1000_NVM_RW_REG_DATA 16 |
|
721 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ |
|
722 #define E1000_NVM_RW_REG_START 1 /* Start operation */ |
|
723 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ |
|
724 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ |
|
725 |
|
726 /* NVM Word Offsets */ |
|
727 #define NVM_COMPAT 0x0003 |
|
728 #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ |
|
729 #define NVM_VERSION 0x0005 |
|
730 #define NVM_INIT_CONTROL2_REG 0x000F |
|
731 #define NVM_INIT_CONTROL3_PORT_B 0x0014 |
|
732 #define NVM_INIT_CONTROL3_PORT_A 0x0024 |
|
733 #define NVM_ALT_MAC_ADDR_PTR 0x0037 |
|
734 #define NVM_CHECKSUM_REG 0x003F |
|
735 #define NVM_COMPATIBILITY_REG_3 0x0003 |
|
736 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 |
|
737 #define NVM_MAC_ADDR 0x0000 |
|
738 #define NVM_SUB_DEV_ID 0x000B |
|
739 #define NVM_SUB_VEN_ID 0x000C |
|
740 #define NVM_DEV_ID 0x000D |
|
741 #define NVM_VEN_ID 0x000E |
|
742 #define NVM_INIT_CTRL_2 0x000F |
|
743 #define NVM_INIT_CTRL_4 0x0013 |
|
744 #define NVM_LED_1_CFG 0x001C |
|
745 #define NVM_LED_0_2_CFG 0x001F |
|
746 #define NVM_ETRACK_WORD 0x0042 |
|
747 #define NVM_ETRACK_HIWORD 0x0043 |
|
748 #define NVM_COMB_VER_OFF 0x0083 |
|
749 #define NVM_COMB_VER_PTR 0x003d |
|
750 |
|
751 /* NVM version defines */ |
|
752 #define NVM_MAJOR_MASK 0xF000 |
|
753 #define NVM_MINOR_MASK 0x0FF0 |
|
754 #define NVM_IMAGE_ID_MASK 0x000F |
|
755 #define NVM_COMB_VER_MASK 0x00FF |
|
756 #define NVM_MAJOR_SHIFT 12 |
|
757 #define NVM_MINOR_SHIFT 4 |
|
758 #define NVM_COMB_VER_SHFT 8 |
|
759 #define NVM_VER_INVALID 0xFFFF |
|
760 #define NVM_ETRACK_SHIFT 16 |
|
761 #define NVM_ETRACK_VALID 0x8000 |
|
762 #define NVM_NEW_DEC_MASK 0x0F00 |
|
763 #define NVM_HEX_CONV 16 |
|
764 #define NVM_HEX_TENS 10 |
|
765 |
|
766 #define NVM_ETS_CFG 0x003E |
|
767 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 |
|
768 #define NVM_ETS_LTHRES_DELTA_SHIFT 6 |
|
769 #define NVM_ETS_TYPE_MASK 0x0038 |
|
770 #define NVM_ETS_TYPE_SHIFT 3 |
|
771 #define NVM_ETS_TYPE_EMC 0x000 |
|
772 #define NVM_ETS_NUM_SENSORS_MASK 0x0007 |
|
773 #define NVM_ETS_DATA_LOC_MASK 0x3C00 |
|
774 #define NVM_ETS_DATA_LOC_SHIFT 10 |
|
775 #define NVM_ETS_DATA_INDEX_MASK 0x0300 |
|
776 #define NVM_ETS_DATA_INDEX_SHIFT 8 |
|
777 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF |
|
778 |
|
779 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ |
|
780 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ |
|
781 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ |
|
782 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ |
|
783 |
|
784 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) |
|
785 |
|
786 /* Mask bits for fields in Word 0x24 of the NVM */ |
|
787 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ |
|
788 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ |
|
789 |
|
790 /* Mask bits for fields in Word 0x0f of the NVM */ |
|
791 #define NVM_WORD0F_PAUSE_MASK 0x3000 |
|
792 #define NVM_WORD0F_ASM_DIR 0x2000 |
|
793 |
|
794 /* Mask bits for fields in Word 0x1a of the NVM */ |
|
795 |
|
796 /* length of string needed to store part num */ |
|
797 #define E1000_PBANUM_LENGTH 11 |
|
798 |
|
799 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ |
|
800 #define NVM_SUM 0xBABA |
|
801 |
|
802 #define NVM_PBA_OFFSET_0 8 |
|
803 #define NVM_PBA_OFFSET_1 9 |
|
804 #define NVM_RESERVED_WORD 0xFFFF |
|
805 #define NVM_PBA_PTR_GUARD 0xFAFA |
|
806 #define NVM_WORD_SIZE_BASE_SHIFT 6 |
|
807 |
|
808 /* NVM Commands - Microwire */ |
|
809 |
|
810 /* NVM Commands - SPI */ |
|
811 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
|
812 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ |
|
813 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ |
|
814 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
|
815 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ |
|
816 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ |
|
817 |
|
818 /* SPI NVM Status Register */ |
|
819 #define NVM_STATUS_RDY_SPI 0x01 |
|
820 |
|
821 /* Word definitions for ID LED Settings */ |
|
822 #define ID_LED_RESERVED_0000 0x0000 |
|
823 #define ID_LED_RESERVED_FFFF 0xFFFF |
|
824 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ |
|
825 (ID_LED_OFF1_OFF2 << 8) | \ |
|
826 (ID_LED_DEF1_DEF2 << 4) | \ |
|
827 (ID_LED_DEF1_DEF2)) |
|
828 #define ID_LED_DEF1_DEF2 0x1 |
|
829 #define ID_LED_DEF1_ON2 0x2 |
|
830 #define ID_LED_DEF1_OFF2 0x3 |
|
831 #define ID_LED_ON1_DEF2 0x4 |
|
832 #define ID_LED_ON1_ON2 0x5 |
|
833 #define ID_LED_ON1_OFF2 0x6 |
|
834 #define ID_LED_OFF1_DEF2 0x7 |
|
835 #define ID_LED_OFF1_ON2 0x8 |
|
836 #define ID_LED_OFF1_OFF2 0x9 |
|
837 |
|
838 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF |
|
839 #define IGP_ACTIVITY_LED_ENABLE 0x0300 |
|
840 #define IGP_LED3_MODE 0x07000000 |
|
841 |
|
842 /* PCI/PCI-X/PCI-EX Config space */ |
|
843 #define PCIE_DEVICE_CONTROL2 0x28 |
|
844 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 |
|
845 |
|
846 #define PHY_REVISION_MASK 0xFFFFFFF0 |
|
847 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ |
|
848 #define MAX_PHY_MULTI_PAGE_REG 0xF |
|
849 |
|
850 /* Bit definitions for valid PHY IDs. */ |
|
851 /* I = Integrated |
|
852 * E = External |
|
853 */ |
|
854 #define M88E1111_I_PHY_ID 0x01410CC0 |
|
855 #define M88E1112_E_PHY_ID 0x01410C90 |
|
856 #define I347AT4_E_PHY_ID 0x01410DC0 |
|
857 #define IGP03E1000_E_PHY_ID 0x02A80390 |
|
858 #define I82580_I_PHY_ID 0x015403A0 |
|
859 #define I350_I_PHY_ID 0x015403B0 |
|
860 #define M88_VENDOR 0x0141 |
|
861 #define I210_I_PHY_ID 0x01410C00 |
|
862 #define M88E1543_E_PHY_ID 0x01410EA0 |
|
863 |
|
864 /* M88E1000 Specific Registers */ |
|
865 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ |
|
866 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ |
|
867 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ |
|
868 |
|
869 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ |
|
870 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ |
|
871 |
|
872 /* M88E1000 PHY Specific Control Register */ |
|
873 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ |
|
874 /* 1=CLK125 low, 0=CLK125 toggling */ |
|
875 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ |
|
876 /* Manual MDI configuration */ |
|
877 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ |
|
878 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ |
|
879 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 |
|
880 /* Auto crossover enabled all speeds */ |
|
881 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 |
|
882 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold |
|
883 * 0=Normal 10BASE-T Rx Threshold |
|
884 */ |
|
885 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ |
|
886 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |
|
887 |
|
888 /* M88E1000 PHY Specific Status Register */ |
|
889 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ |
|
890 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ |
|
891 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ |
|
892 /* 0 = <50M |
|
893 * 1 = 50-80M |
|
894 * 2 = 80-110M |
|
895 * 3 = 110-140M |
|
896 * 4 = >140M |
|
897 */ |
|
898 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 |
|
899 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ |
|
900 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ |
|
901 |
|
902 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 |
|
903 |
|
904 /* M88E1000 Extended PHY Specific Control Register */ |
|
905 /* 1 = Lost lock detect enabled. |
|
906 * Will assert lost lock and bring |
|
907 * link down if idle not seen |
|
908 * within 1ms in 1000BASE-T |
|
909 */ |
|
910 /* Number of times we will attempt to autonegotiate before downshifting if we |
|
911 * are the master |
|
912 */ |
|
913 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 |
|
914 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 |
|
915 /* Number of times we will attempt to autonegotiate before downshifting if we |
|
916 * are the slave |
|
917 */ |
|
918 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 |
|
919 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 |
|
920 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ |
|
921 |
|
922 /* Intel i347-AT4 Registers */ |
|
923 |
|
924 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ |
|
925 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ |
|
926 #define I347AT4_PAGE_SELECT 0x16 |
|
927 |
|
928 /* i347-AT4 Extended PHY Specific Control Register */ |
|
929 |
|
930 /* Number of times we will attempt to autonegotiate before downshifting if we |
|
931 * are the master |
|
932 */ |
|
933 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 |
|
934 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 |
|
935 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 |
|
936 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 |
|
937 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 |
|
938 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 |
|
939 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 |
|
940 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 |
|
941 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 |
|
942 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 |
|
943 |
|
944 /* i347-AT4 PHY Cable Diagnostics Control */ |
|
945 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ |
|
946 |
|
947 /* Marvell 1112 only registers */ |
|
948 #define M88E1112_VCT_DSP_DISTANCE 0x001A |
|
949 |
|
950 /* M88EC018 Rev 2 specific DownShift settings */ |
|
951 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 |
|
952 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 |
|
953 |
|
954 /* MDI Control */ |
|
955 #define E1000_MDIC_DATA_MASK 0x0000FFFF |
|
956 #define E1000_MDIC_REG_MASK 0x001F0000 |
|
957 #define E1000_MDIC_REG_SHIFT 16 |
|
958 #define E1000_MDIC_PHY_MASK 0x03E00000 |
|
959 #define E1000_MDIC_PHY_SHIFT 21 |
|
960 #define E1000_MDIC_OP_WRITE 0x04000000 |
|
961 #define E1000_MDIC_OP_READ 0x08000000 |
|
962 #define E1000_MDIC_READY 0x10000000 |
|
963 #define E1000_MDIC_INT_EN 0x20000000 |
|
964 #define E1000_MDIC_ERROR 0x40000000 |
|
965 #define E1000_MDIC_DEST 0x80000000 |
|
966 |
|
967 /* Thermal Sensor */ |
|
968 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ |
|
969 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ |
|
970 |
|
971 /* Energy Efficient Ethernet */ |
|
972 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ |
|
973 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ |
|
974 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ |
|
975 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ |
|
976 #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ |
|
977 #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ |
|
978 #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ |
|
979 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ |
|
980 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ |
|
981 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ |
|
982 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ |
|
983 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ |
|
984 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ |
|
985 #define E1000_M88E1543_EEE_CTRL_1 0x0 |
|
986 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ |
|
987 #define E1000_EEE_ADV_DEV_I354 7 |
|
988 #define E1000_EEE_ADV_ADDR_I354 60 |
|
989 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ |
|
990 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ |
|
991 #define E1000_PCS_STATUS_DEV_I354 3 |
|
992 #define E1000_PCS_STATUS_ADDR_I354 1 |
|
993 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ |
|
994 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 |
|
995 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 |
|
996 |
|
997 /* SerDes Control */ |
|
998 #define E1000_GEN_CTL_READY 0x80000000 |
|
999 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 |
|
1000 #define E1000_GEN_POLL_TIMEOUT 640 |
|
1001 |
|
1002 #define E1000_VFTA_ENTRY_SHIFT 5 |
|
1003 #define E1000_VFTA_ENTRY_MASK 0x7F |
|
1004 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F |
|
1005 |
|
1006 /* DMA Coalescing register fields */ |
|
1007 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */ |
|
1008 |
|
1009 /* Tx Rate-Scheduler Config fields */ |
|
1010 #define E1000_RTTBCNRC_RS_ENA 0x80000000 |
|
1011 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF |
|
1012 #define E1000_RTTBCNRC_RF_INT_SHIFT 14 |
|
1013 #define E1000_RTTBCNRC_RF_INT_MASK \ |
|
1014 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) |
|
1015 |
|
1016 #endif |