devices/e1000e/phy-2.6.32-ethercat.c
branchredundancy
changeset 2136 729df853b3fb
equal deleted inserted replaced
2135:f99b2249704c 2136:729df853b3fb
       
     1 /*******************************************************************************
       
     2 
       
     3   Intel PRO/1000 Linux driver
       
     4   Copyright(c) 1999 - 2008 Intel Corporation.
       
     5 
       
     6   This program is free software; you can redistribute it and/or modify it
       
     7   under the terms and conditions of the GNU General Public License,
       
     8   version 2, as published by the Free Software Foundation.
       
     9 
       
    10   This program is distributed in the hope it will be useful, but WITHOUT
       
    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
       
    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
       
    13   more details.
       
    14 
       
    15   You should have received a copy of the GNU General Public License along with
       
    16   this program; if not, write to the Free Software Foundation, Inc.,
       
    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
       
    18 
       
    19   The full GNU General Public License is included in this distribution in
       
    20   the file called "COPYING".
       
    21 
       
    22   Contact Information:
       
    23   Linux NICS <linux.nics@intel.com>
       
    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
       
    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
       
    26 
       
    27 *******************************************************************************/
       
    28 
       
    29 #include <linux/delay.h>
       
    30 
       
    31 #include "e1000-2.6.32-ethercat.h"
       
    32 
       
    33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
       
    34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
       
    35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
       
    36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
       
    37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
       
    38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
       
    39 					  u16 *data, bool read);
       
    40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
       
    41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
       
    42                                           u16 *data, bool read);
       
    43 
       
    44 /* Cable length tables */
       
    45 static const u16 e1000_m88_cable_length_table[] =
       
    46 	{ 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
       
    47 
       
    48 static const u16 e1000_igp_2_cable_length_table[] =
       
    49 	{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
       
    50 	  6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
       
    51 	  26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
       
    52 	  44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
       
    53 	  66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
       
    54 	  87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
       
    55 	  100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
       
    56 	  124};
       
    57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
       
    58 		ARRAY_SIZE(e1000_igp_2_cable_length_table)
       
    59 
       
    60 #define BM_PHY_REG_PAGE(offset) \
       
    61 	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
       
    62 #define BM_PHY_REG_NUM(offset) \
       
    63 	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
       
    64 	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
       
    65 		~MAX_PHY_REG_ADDRESS)))
       
    66 
       
    67 #define HV_INTC_FC_PAGE_START             768
       
    68 #define I82578_ADDR_REG                   29
       
    69 #define I82577_ADDR_REG                   16
       
    70 #define I82577_CFG_REG                    22
       
    71 #define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
       
    72 #define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
       
    73 #define I82577_CTRL_REG                   23
       
    74 
       
    75 /* 82577 specific PHY registers */
       
    76 #define I82577_PHY_CTRL_2            18
       
    77 #define I82577_PHY_STATUS_2          26
       
    78 #define I82577_PHY_DIAG_STATUS       31
       
    79 
       
    80 /* I82577 PHY Status 2 */
       
    81 #define I82577_PHY_STATUS2_REV_POLARITY   0x0400
       
    82 #define I82577_PHY_STATUS2_MDIX           0x0800
       
    83 #define I82577_PHY_STATUS2_SPEED_MASK     0x0300
       
    84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
       
    85 
       
    86 /* I82577 PHY Control 2 */
       
    87 #define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
       
    88 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
       
    89 
       
    90 /* I82577 PHY Diagnostics Status */
       
    91 #define I82577_DSTATUS_CABLE_LENGTH       0x03FC
       
    92 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
       
    93 
       
    94 /* BM PHY Copper Specific Control 1 */
       
    95 #define BM_CS_CTRL1                       16
       
    96 
       
    97 #define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
       
    98 #define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
       
    99 #define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
       
   100 
       
   101 /**
       
   102  *  e1000e_check_reset_block_generic - Check if PHY reset is blocked
       
   103  *  @hw: pointer to the HW structure
       
   104  *
       
   105  *  Read the PHY management control register and check whether a PHY reset
       
   106  *  is blocked.  If a reset is not blocked return 0, otherwise
       
   107  *  return E1000_BLK_PHY_RESET (12).
       
   108  **/
       
   109 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
       
   110 {
       
   111 	u32 manc;
       
   112 
       
   113 	manc = er32(MANC);
       
   114 
       
   115 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
       
   116 	       E1000_BLK_PHY_RESET : 0;
       
   117 }
       
   118 
       
   119 /**
       
   120  *  e1000e_get_phy_id - Retrieve the PHY ID and revision
       
   121  *  @hw: pointer to the HW structure
       
   122  *
       
   123  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
       
   124  *  revision in the hardware structure.
       
   125  **/
       
   126 s32 e1000e_get_phy_id(struct e1000_hw *hw)
       
   127 {
       
   128 	struct e1000_phy_info *phy = &hw->phy;
       
   129 	s32 ret_val = 0;
       
   130 	u16 phy_id;
       
   131 	u16 retry_count = 0;
       
   132 
       
   133 	if (!(phy->ops.read_phy_reg))
       
   134 		goto out;
       
   135 
       
   136 	while (retry_count < 2) {
       
   137 		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
       
   138 		if (ret_val)
       
   139 			goto out;
       
   140 
       
   141 		phy->id = (u32)(phy_id << 16);
       
   142 		udelay(20);
       
   143 		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
       
   144 		if (ret_val)
       
   145 			goto out;
       
   146 
       
   147 		phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
       
   148 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
       
   149 
       
   150 		if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
       
   151 			goto out;
       
   152 
       
   153 		/*
       
   154 		 * If the PHY ID is still unknown, we may have an 82577i
       
   155 		 * without link.  We will try again after setting Slow
       
   156 		 * MDIC mode. No harm in trying again in this case since
       
   157 		 * the PHY ID is unknown at this point anyway
       
   158 		 */
       
   159 		ret_val = phy->ops.acquire_phy(hw);
       
   160 		if (ret_val)
       
   161 			goto out;
       
   162 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
       
   163 		if (ret_val)
       
   164 			goto out;
       
   165 		phy->ops.release_phy(hw);
       
   166 
       
   167 		retry_count++;
       
   168 	}
       
   169 out:
       
   170 	/* Revert to MDIO fast mode, if applicable */
       
   171 	if (retry_count) {
       
   172 		ret_val = phy->ops.acquire_phy(hw);
       
   173 		if (ret_val)
       
   174 			return ret_val;
       
   175 		ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
       
   176 		phy->ops.release_phy(hw);
       
   177 	}
       
   178 
       
   179 	return ret_val;
       
   180 }
       
   181 
       
   182 /**
       
   183  *  e1000e_phy_reset_dsp - Reset PHY DSP
       
   184  *  @hw: pointer to the HW structure
       
   185  *
       
   186  *  Reset the digital signal processor.
       
   187  **/
       
   188 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
       
   189 {
       
   190 	s32 ret_val;
       
   191 
       
   192 	ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
       
   193 	if (ret_val)
       
   194 		return ret_val;
       
   195 
       
   196 	return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
       
   197 }
       
   198 
       
   199 /**
       
   200  *  e1000e_read_phy_reg_mdic - Read MDI control register
       
   201  *  @hw: pointer to the HW structure
       
   202  *  @offset: register offset to be read
       
   203  *  @data: pointer to the read data
       
   204  *
       
   205  *  Reads the MDI control register in the PHY at offset and stores the
       
   206  *  information read to data.
       
   207  **/
       
   208 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
       
   209 {
       
   210 	struct e1000_phy_info *phy = &hw->phy;
       
   211 	u32 i, mdic = 0;
       
   212 
       
   213 	if (offset > MAX_PHY_REG_ADDRESS) {
       
   214 		hw_dbg(hw, "PHY Address %d is out of range\n", offset);
       
   215 		return -E1000_ERR_PARAM;
       
   216 	}
       
   217 
       
   218 	/*
       
   219 	 * Set up Op-code, Phy Address, and register offset in the MDI
       
   220 	 * Control register.  The MAC will take care of interfacing with the
       
   221 	 * PHY to retrieve the desired data.
       
   222 	 */
       
   223 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
       
   224 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
       
   225 		(E1000_MDIC_OP_READ));
       
   226 
       
   227 	ew32(MDIC, mdic);
       
   228 
       
   229 	/*
       
   230 	 * Poll the ready bit to see if the MDI read completed
       
   231 	 * Increasing the time out as testing showed failures with
       
   232 	 * the lower time out
       
   233 	 */
       
   234 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
       
   235 		udelay(50);
       
   236 		mdic = er32(MDIC);
       
   237 		if (mdic & E1000_MDIC_READY)
       
   238 			break;
       
   239 	}
       
   240 	if (!(mdic & E1000_MDIC_READY)) {
       
   241 		hw_dbg(hw, "MDI Read did not complete\n");
       
   242 		return -E1000_ERR_PHY;
       
   243 	}
       
   244 	if (mdic & E1000_MDIC_ERROR) {
       
   245 		hw_dbg(hw, "MDI Error\n");
       
   246 		return -E1000_ERR_PHY;
       
   247 	}
       
   248 	*data = (u16) mdic;
       
   249 
       
   250 	return 0;
       
   251 }
       
   252 
       
   253 /**
       
   254  *  e1000e_write_phy_reg_mdic - Write MDI control register
       
   255  *  @hw: pointer to the HW structure
       
   256  *  @offset: register offset to write to
       
   257  *  @data: data to write to register at offset
       
   258  *
       
   259  *  Writes data to MDI control register in the PHY at offset.
       
   260  **/
       
   261 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
       
   262 {
       
   263 	struct e1000_phy_info *phy = &hw->phy;
       
   264 	u32 i, mdic = 0;
       
   265 
       
   266 	if (offset > MAX_PHY_REG_ADDRESS) {
       
   267 		hw_dbg(hw, "PHY Address %d is out of range\n", offset);
       
   268 		return -E1000_ERR_PARAM;
       
   269 	}
       
   270 
       
   271 	/*
       
   272 	 * Set up Op-code, Phy Address, and register offset in the MDI
       
   273 	 * Control register.  The MAC will take care of interfacing with the
       
   274 	 * PHY to retrieve the desired data.
       
   275 	 */
       
   276 	mdic = (((u32)data) |
       
   277 		(offset << E1000_MDIC_REG_SHIFT) |
       
   278 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
       
   279 		(E1000_MDIC_OP_WRITE));
       
   280 
       
   281 	ew32(MDIC, mdic);
       
   282 
       
   283 	/*
       
   284 	 * Poll the ready bit to see if the MDI read completed
       
   285 	 * Increasing the time out as testing showed failures with
       
   286 	 * the lower time out
       
   287 	 */
       
   288 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
       
   289 		udelay(50);
       
   290 		mdic = er32(MDIC);
       
   291 		if (mdic & E1000_MDIC_READY)
       
   292 			break;
       
   293 	}
       
   294 	if (!(mdic & E1000_MDIC_READY)) {
       
   295 		hw_dbg(hw, "MDI Write did not complete\n");
       
   296 		return -E1000_ERR_PHY;
       
   297 	}
       
   298 	if (mdic & E1000_MDIC_ERROR) {
       
   299 		hw_dbg(hw, "MDI Error\n");
       
   300 		return -E1000_ERR_PHY;
       
   301 	}
       
   302 
       
   303 	return 0;
       
   304 }
       
   305 
       
   306 /**
       
   307  *  e1000e_read_phy_reg_m88 - Read m88 PHY register
       
   308  *  @hw: pointer to the HW structure
       
   309  *  @offset: register offset to be read
       
   310  *  @data: pointer to the read data
       
   311  *
       
   312  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
   313  *  and storing the retrieved information in data.  Release any acquired
       
   314  *  semaphores before exiting.
       
   315  **/
       
   316 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
       
   317 {
       
   318 	s32 ret_val;
       
   319 
       
   320 	ret_val = hw->phy.ops.acquire_phy(hw);
       
   321 	if (ret_val)
       
   322 		return ret_val;
       
   323 
       
   324 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
   325 					   data);
       
   326 
       
   327 	hw->phy.ops.release_phy(hw);
       
   328 
       
   329 	return ret_val;
       
   330 }
       
   331 
       
   332 /**
       
   333  *  e1000e_write_phy_reg_m88 - Write m88 PHY register
       
   334  *  @hw: pointer to the HW structure
       
   335  *  @offset: register offset to write to
       
   336  *  @data: data to write at register offset
       
   337  *
       
   338  *  Acquires semaphore, if necessary, then writes the data to PHY register
       
   339  *  at the offset.  Release any acquired semaphores before exiting.
       
   340  **/
       
   341 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
       
   342 {
       
   343 	s32 ret_val;
       
   344 
       
   345 	ret_val = hw->phy.ops.acquire_phy(hw);
       
   346 	if (ret_val)
       
   347 		return ret_val;
       
   348 
       
   349 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
   350 					    data);
       
   351 
       
   352 	hw->phy.ops.release_phy(hw);
       
   353 
       
   354 	return ret_val;
       
   355 }
       
   356 
       
   357 /**
       
   358  *  __e1000e_read_phy_reg_igp - Read igp PHY register
       
   359  *  @hw: pointer to the HW structure
       
   360  *  @offset: register offset to be read
       
   361  *  @data: pointer to the read data
       
   362  *  @locked: semaphore has already been acquired or not
       
   363  *
       
   364  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
   365  *  and stores the retrieved information in data.  Release any acquired
       
   366  *  semaphores before exiting.
       
   367  **/
       
   368 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
       
   369                                     bool locked)
       
   370 {
       
   371 	s32 ret_val = 0;
       
   372 
       
   373 	if (!locked) {
       
   374 		if (!(hw->phy.ops.acquire_phy))
       
   375 			goto out;
       
   376 
       
   377 		ret_val = hw->phy.ops.acquire_phy(hw);
       
   378 		if (ret_val)
       
   379 			goto out;
       
   380 	}
       
   381 
       
   382 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
   383 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
   384 						    IGP01E1000_PHY_PAGE_SELECT,
       
   385 						    (u16)offset);
       
   386 		if (ret_val)
       
   387 			goto release;
       
   388 	}
       
   389 
       
   390 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
   391 	                                  data);
       
   392 
       
   393 release:
       
   394 	if (!locked)
       
   395 		hw->phy.ops.release_phy(hw);
       
   396 out:
       
   397 	return ret_val;
       
   398 }
       
   399 
       
   400 /**
       
   401  *  e1000e_read_phy_reg_igp - Read igp PHY register
       
   402  *  @hw: pointer to the HW structure
       
   403  *  @offset: register offset to be read
       
   404  *  @data: pointer to the read data
       
   405  *
       
   406  *  Acquires semaphore then reads the PHY register at offset and stores the
       
   407  *  retrieved information in data.
       
   408  *  Release the acquired semaphore before exiting.
       
   409  **/
       
   410 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
       
   411 {
       
   412 	return __e1000e_read_phy_reg_igp(hw, offset, data, false);
       
   413 }
       
   414 
       
   415 /**
       
   416  *  e1000e_read_phy_reg_igp_locked - Read igp PHY register
       
   417  *  @hw: pointer to the HW structure
       
   418  *  @offset: register offset to be read
       
   419  *  @data: pointer to the read data
       
   420  *
       
   421  *  Reads the PHY register at offset and stores the retrieved information
       
   422  *  in data.  Assumes semaphore already acquired.
       
   423  **/
       
   424 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
       
   425 {
       
   426 	return __e1000e_read_phy_reg_igp(hw, offset, data, true);
       
   427 }
       
   428 
       
   429 /**
       
   430  *  e1000e_write_phy_reg_igp - Write igp PHY register
       
   431  *  @hw: pointer to the HW structure
       
   432  *  @offset: register offset to write to
       
   433  *  @data: data to write at register offset
       
   434  *  @locked: semaphore has already been acquired or not
       
   435  *
       
   436  *  Acquires semaphore, if necessary, then writes the data to PHY register
       
   437  *  at the offset.  Release any acquired semaphores before exiting.
       
   438  **/
       
   439 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
       
   440                                      bool locked)
       
   441 {
       
   442 	s32 ret_val = 0;
       
   443 
       
   444 	if (!locked) {
       
   445 		if (!(hw->phy.ops.acquire_phy))
       
   446 			goto out;
       
   447 
       
   448 		ret_val = hw->phy.ops.acquire_phy(hw);
       
   449 		if (ret_val)
       
   450 			goto out;
       
   451 	}
       
   452 
       
   453 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
   454 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
   455 						    IGP01E1000_PHY_PAGE_SELECT,
       
   456 						    (u16)offset);
       
   457 		if (ret_val)
       
   458 			goto release;
       
   459 	}
       
   460 
       
   461 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
   462 					    data);
       
   463 
       
   464 release:
       
   465 	if (!locked)
       
   466 		hw->phy.ops.release_phy(hw);
       
   467 
       
   468 out:
       
   469 	return ret_val;
       
   470 }
       
   471 
       
   472 /**
       
   473  *  e1000e_write_phy_reg_igp - Write igp PHY register
       
   474  *  @hw: pointer to the HW structure
       
   475  *  @offset: register offset to write to
       
   476  *  @data: data to write at register offset
       
   477  *
       
   478  *  Acquires semaphore then writes the data to PHY register
       
   479  *  at the offset.  Release any acquired semaphores before exiting.
       
   480  **/
       
   481 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
       
   482 {
       
   483 	return __e1000e_write_phy_reg_igp(hw, offset, data, false);
       
   484 }
       
   485 
       
   486 /**
       
   487  *  e1000e_write_phy_reg_igp_locked - Write igp PHY register
       
   488  *  @hw: pointer to the HW structure
       
   489  *  @offset: register offset to write to
       
   490  *  @data: data to write at register offset
       
   491  *
       
   492  *  Writes the data to PHY register at the offset.
       
   493  *  Assumes semaphore already acquired.
       
   494  **/
       
   495 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
       
   496 {
       
   497 	return __e1000e_write_phy_reg_igp(hw, offset, data, true);
       
   498 }
       
   499 
       
   500 /**
       
   501  *  __e1000_read_kmrn_reg - Read kumeran register
       
   502  *  @hw: pointer to the HW structure
       
   503  *  @offset: register offset to be read
       
   504  *  @data: pointer to the read data
       
   505  *  @locked: semaphore has already been acquired or not
       
   506  *
       
   507  *  Acquires semaphore, if necessary.  Then reads the PHY register at offset
       
   508  *  using the kumeran interface.  The information retrieved is stored in data.
       
   509  *  Release any acquired semaphores before exiting.
       
   510  **/
       
   511 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
       
   512                                  bool locked)
       
   513 {
       
   514 	u32 kmrnctrlsta;
       
   515 	s32 ret_val = 0;
       
   516 
       
   517 	if (!locked) {
       
   518 		if (!(hw->phy.ops.acquire_phy))
       
   519 			goto out;
       
   520 
       
   521 		ret_val = hw->phy.ops.acquire_phy(hw);
       
   522 		if (ret_val)
       
   523 			goto out;
       
   524 	}
       
   525 
       
   526 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
       
   527 		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
       
   528 	ew32(KMRNCTRLSTA, kmrnctrlsta);
       
   529 
       
   530 	udelay(2);
       
   531 
       
   532 	kmrnctrlsta = er32(KMRNCTRLSTA);
       
   533 	*data = (u16)kmrnctrlsta;
       
   534 
       
   535 	if (!locked)
       
   536 		hw->phy.ops.release_phy(hw);
       
   537 
       
   538 out:
       
   539 	return ret_val;
       
   540 }
       
   541 
       
   542 /**
       
   543  *  e1000e_read_kmrn_reg -  Read kumeran register
       
   544  *  @hw: pointer to the HW structure
       
   545  *  @offset: register offset to be read
       
   546  *  @data: pointer to the read data
       
   547  *
       
   548  *  Acquires semaphore then reads the PHY register at offset using the
       
   549  *  kumeran interface.  The information retrieved is stored in data.
       
   550  *  Release the acquired semaphore before exiting.
       
   551  **/
       
   552 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
       
   553 {
       
   554 	return __e1000_read_kmrn_reg(hw, offset, data, false);
       
   555 }
       
   556 
       
   557 /**
       
   558  *  e1000e_read_kmrn_reg_locked -  Read kumeran register
       
   559  *  @hw: pointer to the HW structure
       
   560  *  @offset: register offset to be read
       
   561  *  @data: pointer to the read data
       
   562  *
       
   563  *  Reads the PHY register at offset using the kumeran interface.  The
       
   564  *  information retrieved is stored in data.
       
   565  *  Assumes semaphore already acquired.
       
   566  **/
       
   567 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
       
   568 {
       
   569 	return __e1000_read_kmrn_reg(hw, offset, data, true);
       
   570 }
       
   571 
       
   572 /**
       
   573  *  __e1000_write_kmrn_reg - Write kumeran register
       
   574  *  @hw: pointer to the HW structure
       
   575  *  @offset: register offset to write to
       
   576  *  @data: data to write at register offset
       
   577  *  @locked: semaphore has already been acquired or not
       
   578  *
       
   579  *  Acquires semaphore, if necessary.  Then write the data to PHY register
       
   580  *  at the offset using the kumeran interface.  Release any acquired semaphores
       
   581  *  before exiting.
       
   582  **/
       
   583 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
       
   584                                   bool locked)
       
   585 {
       
   586 	u32 kmrnctrlsta;
       
   587 	s32 ret_val = 0;
       
   588 
       
   589 	if (!locked) {
       
   590 		if (!(hw->phy.ops.acquire_phy))
       
   591 			goto out;
       
   592 
       
   593 		ret_val = hw->phy.ops.acquire_phy(hw);
       
   594 		if (ret_val)
       
   595 			goto out;
       
   596 	}
       
   597 
       
   598 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
       
   599 		       E1000_KMRNCTRLSTA_OFFSET) | data;
       
   600 	ew32(KMRNCTRLSTA, kmrnctrlsta);
       
   601 
       
   602 	udelay(2);
       
   603 
       
   604 	if (!locked)
       
   605 		hw->phy.ops.release_phy(hw);
       
   606 
       
   607 out:
       
   608 	return ret_val;
       
   609 }
       
   610 
       
   611 /**
       
   612  *  e1000e_write_kmrn_reg -  Write kumeran register
       
   613  *  @hw: pointer to the HW structure
       
   614  *  @offset: register offset to write to
       
   615  *  @data: data to write at register offset
       
   616  *
       
   617  *  Acquires semaphore then writes the data to the PHY register at the offset
       
   618  *  using the kumeran interface.  Release the acquired semaphore before exiting.
       
   619  **/
       
   620 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
       
   621 {
       
   622 	return __e1000_write_kmrn_reg(hw, offset, data, false);
       
   623 }
       
   624 
       
   625 /**
       
   626  *  e1000e_write_kmrn_reg_locked -  Write kumeran register
       
   627  *  @hw: pointer to the HW structure
       
   628  *  @offset: register offset to write to
       
   629  *  @data: data to write at register offset
       
   630  *
       
   631  *  Write the data to PHY register at the offset using the kumeran interface.
       
   632  *  Assumes semaphore already acquired.
       
   633  **/
       
   634 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
       
   635 {
       
   636 	return __e1000_write_kmrn_reg(hw, offset, data, true);
       
   637 }
       
   638 
       
   639 /**
       
   640  *  e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
       
   641  *  @hw: pointer to the HW structure
       
   642  *
       
   643  *  Sets up Carrier-sense on Transmit and downshift values.
       
   644  **/
       
   645 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
       
   646 {
       
   647 	struct e1000_phy_info *phy = &hw->phy;
       
   648 	s32 ret_val;
       
   649 	u16 phy_data;
       
   650 
       
   651 	/* Enable CRS on TX. This must be set for half-duplex operation. */
       
   652 	ret_val = phy->ops.read_phy_reg(hw, I82577_CFG_REG, &phy_data);
       
   653 	if (ret_val)
       
   654 		goto out;
       
   655 
       
   656 	phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
       
   657 
       
   658 	/* Enable downshift */
       
   659 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
       
   660 
       
   661 	ret_val = phy->ops.write_phy_reg(hw, I82577_CFG_REG, phy_data);
       
   662 
       
   663 out:
       
   664 	return ret_val;
       
   665 }
       
   666 
       
   667 /**
       
   668  *  e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
       
   669  *  @hw: pointer to the HW structure
       
   670  *
       
   671  *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
       
   672  *  and downshift values are set also.
       
   673  **/
       
   674 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
       
   675 {
       
   676 	struct e1000_phy_info *phy = &hw->phy;
       
   677 	s32 ret_val;
       
   678 	u16 phy_data;
       
   679 
       
   680 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
       
   681 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
       
   682 	if (ret_val)
       
   683 		return ret_val;
       
   684 
       
   685 	/* For BM PHY this bit is downshift enable */
       
   686 	if (phy->type != e1000_phy_bm)
       
   687 		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
       
   688 
       
   689 	/*
       
   690 	 * Options:
       
   691 	 *   MDI/MDI-X = 0 (default)
       
   692 	 *   0 - Auto for all speeds
       
   693 	 *   1 - MDI mode
       
   694 	 *   2 - MDI-X mode
       
   695 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
       
   696 	 */
       
   697 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
       
   698 
       
   699 	switch (phy->mdix) {
       
   700 	case 1:
       
   701 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
       
   702 		break;
       
   703 	case 2:
       
   704 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
       
   705 		break;
       
   706 	case 3:
       
   707 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
       
   708 		break;
       
   709 	case 0:
       
   710 	default:
       
   711 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
       
   712 		break;
       
   713 	}
       
   714 
       
   715 	/*
       
   716 	 * Options:
       
   717 	 *   disable_polarity_correction = 0 (default)
       
   718 	 *       Automatic Correction for Reversed Cable Polarity
       
   719 	 *   0 - Disabled
       
   720 	 *   1 - Enabled
       
   721 	 */
       
   722 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
       
   723 	if (phy->disable_polarity_correction == 1)
       
   724 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
       
   725 
       
   726 	/* Enable downshift on BM (disabled by default) */
       
   727 	if (phy->type == e1000_phy_bm)
       
   728 		phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
       
   729 
       
   730 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
       
   731 	if (ret_val)
       
   732 		return ret_val;
       
   733 
       
   734 	if ((phy->type == e1000_phy_m88) &&
       
   735 	    (phy->revision < E1000_REVISION_4) &&
       
   736 	    (phy->id != BME1000_E_PHY_ID_R2)) {
       
   737 		/*
       
   738 		 * Force TX_CLK in the Extended PHY Specific Control Register
       
   739 		 * to 25MHz clock.
       
   740 		 */
       
   741 		ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
       
   742 		if (ret_val)
       
   743 			return ret_val;
       
   744 
       
   745 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
       
   746 
       
   747 		if ((phy->revision == 2) &&
       
   748 		    (phy->id == M88E1111_I_PHY_ID)) {
       
   749 			/* 82573L PHY - set the downshift counter to 5x. */
       
   750 			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
       
   751 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
       
   752 		} else {
       
   753 			/* Configure Master and Slave downshift values */
       
   754 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
       
   755 				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
       
   756 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
       
   757 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
       
   758 		}
       
   759 		ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
       
   760 		if (ret_val)
       
   761 			return ret_val;
       
   762 	}
       
   763 
       
   764 	if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
       
   765 		/* Set PHY page 0, register 29 to 0x0003 */
       
   766 		ret_val = e1e_wphy(hw, 29, 0x0003);
       
   767 		if (ret_val)
       
   768 			return ret_val;
       
   769 
       
   770 		/* Set PHY page 0, register 30 to 0x0000 */
       
   771 		ret_val = e1e_wphy(hw, 30, 0x0000);
       
   772 		if (ret_val)
       
   773 			return ret_val;
       
   774 	}
       
   775 
       
   776 	/* Commit the changes. */
       
   777 	ret_val = e1000e_commit_phy(hw);
       
   778 	if (ret_val) {
       
   779 		hw_dbg(hw, "Error committing the PHY changes\n");
       
   780 		return ret_val;
       
   781 	}
       
   782 
       
   783 	if (phy->type == e1000_phy_82578) {
       
   784 		ret_val = phy->ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
       
   785 		                            &phy_data);
       
   786 		if (ret_val)
       
   787 			return ret_val;
       
   788 
       
   789 		/* 82578 PHY - set the downshift count to 1x. */
       
   790 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
       
   791 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
       
   792 		ret_val = phy->ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
       
   793 		                             phy_data);
       
   794 		if (ret_val)
       
   795 			return ret_val;
       
   796 	}
       
   797 
       
   798 	return 0;
       
   799 }
       
   800 
       
   801 /**
       
   802  *  e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
       
   803  *  @hw: pointer to the HW structure
       
   804  *
       
   805  *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
       
   806  *  igp PHY's.
       
   807  **/
       
   808 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
       
   809 {
       
   810 	struct e1000_phy_info *phy = &hw->phy;
       
   811 	s32 ret_val;
       
   812 	u16 data;
       
   813 
       
   814 	ret_val = e1000_phy_hw_reset(hw);
       
   815 	if (ret_val) {
       
   816 		hw_dbg(hw, "Error resetting the PHY.\n");
       
   817 		return ret_val;
       
   818 	}
       
   819 
       
   820 	/*
       
   821 	 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
       
   822 	 * timeout issues when LFS is enabled.
       
   823 	 */
       
   824 	msleep(100);
       
   825 
       
   826 	/* disable lplu d0 during driver init */
       
   827 	ret_val = e1000_set_d0_lplu_state(hw, 0);
       
   828 	if (ret_val) {
       
   829 		hw_dbg(hw, "Error Disabling LPLU D0\n");
       
   830 		return ret_val;
       
   831 	}
       
   832 	/* Configure mdi-mdix settings */
       
   833 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
       
   834 	if (ret_val)
       
   835 		return ret_val;
       
   836 
       
   837 	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
       
   838 
       
   839 	switch (phy->mdix) {
       
   840 	case 1:
       
   841 		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
       
   842 		break;
       
   843 	case 2:
       
   844 		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
       
   845 		break;
       
   846 	case 0:
       
   847 	default:
       
   848 		data |= IGP01E1000_PSCR_AUTO_MDIX;
       
   849 		break;
       
   850 	}
       
   851 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
       
   852 	if (ret_val)
       
   853 		return ret_val;
       
   854 
       
   855 	/* set auto-master slave resolution settings */
       
   856 	if (hw->mac.autoneg) {
       
   857 		/*
       
   858 		 * when autonegotiation advertisement is only 1000Mbps then we
       
   859 		 * should disable SmartSpeed and enable Auto MasterSlave
       
   860 		 * resolution as hardware default.
       
   861 		 */
       
   862 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
       
   863 			/* Disable SmartSpeed */
       
   864 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
   865 					   &data);
       
   866 			if (ret_val)
       
   867 				return ret_val;
       
   868 
       
   869 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
   870 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
   871 					   data);
       
   872 			if (ret_val)
       
   873 				return ret_val;
       
   874 
       
   875 			/* Set auto Master/Slave resolution process */
       
   876 			ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
       
   877 			if (ret_val)
       
   878 				return ret_val;
       
   879 
       
   880 			data &= ~CR_1000T_MS_ENABLE;
       
   881 			ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
       
   882 			if (ret_val)
       
   883 				return ret_val;
       
   884 		}
       
   885 
       
   886 		ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
       
   887 		if (ret_val)
       
   888 			return ret_val;
       
   889 
       
   890 		/* load defaults for future use */
       
   891 		phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
       
   892 			((data & CR_1000T_MS_VALUE) ?
       
   893 			e1000_ms_force_master :
       
   894 			e1000_ms_force_slave) :
       
   895 			e1000_ms_auto;
       
   896 
       
   897 		switch (phy->ms_type) {
       
   898 		case e1000_ms_force_master:
       
   899 			data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
       
   900 			break;
       
   901 		case e1000_ms_force_slave:
       
   902 			data |= CR_1000T_MS_ENABLE;
       
   903 			data &= ~(CR_1000T_MS_VALUE);
       
   904 			break;
       
   905 		case e1000_ms_auto:
       
   906 			data &= ~CR_1000T_MS_ENABLE;
       
   907 		default:
       
   908 			break;
       
   909 		}
       
   910 		ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
       
   911 	}
       
   912 
       
   913 	return ret_val;
       
   914 }
       
   915 
       
   916 /**
       
   917  *  e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
       
   918  *  @hw: pointer to the HW structure
       
   919  *
       
   920  *  Reads the MII auto-neg advertisement register and/or the 1000T control
       
   921  *  register and if the PHY is already setup for auto-negotiation, then
       
   922  *  return successful.  Otherwise, setup advertisement and flow control to
       
   923  *  the appropriate values for the wanted auto-negotiation.
       
   924  **/
       
   925 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
       
   926 {
       
   927 	struct e1000_phy_info *phy = &hw->phy;
       
   928 	s32 ret_val;
       
   929 	u16 mii_autoneg_adv_reg;
       
   930 	u16 mii_1000t_ctrl_reg = 0;
       
   931 
       
   932 	phy->autoneg_advertised &= phy->autoneg_mask;
       
   933 
       
   934 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
       
   935 	ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
       
   936 	if (ret_val)
       
   937 		return ret_val;
       
   938 
       
   939 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
       
   940 		/* Read the MII 1000Base-T Control Register (Address 9). */
       
   941 		ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
       
   942 		if (ret_val)
       
   943 			return ret_val;
       
   944 	}
       
   945 
       
   946 	/*
       
   947 	 * Need to parse both autoneg_advertised and fc and set up
       
   948 	 * the appropriate PHY registers.  First we will parse for
       
   949 	 * autoneg_advertised software override.  Since we can advertise
       
   950 	 * a plethora of combinations, we need to check each bit
       
   951 	 * individually.
       
   952 	 */
       
   953 
       
   954 	/*
       
   955 	 * First we clear all the 10/100 mb speed bits in the Auto-Neg
       
   956 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
       
   957 	 * the  1000Base-T Control Register (Address 9).
       
   958 	 */
       
   959 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
       
   960 				 NWAY_AR_100TX_HD_CAPS |
       
   961 				 NWAY_AR_10T_FD_CAPS   |
       
   962 				 NWAY_AR_10T_HD_CAPS);
       
   963 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
       
   964 
       
   965 	hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
       
   966 
       
   967 	/* Do we want to advertise 10 Mb Half Duplex? */
       
   968 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
       
   969 		hw_dbg(hw, "Advertise 10mb Half duplex\n");
       
   970 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
       
   971 	}
       
   972 
       
   973 	/* Do we want to advertise 10 Mb Full Duplex? */
       
   974 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
       
   975 		hw_dbg(hw, "Advertise 10mb Full duplex\n");
       
   976 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
       
   977 	}
       
   978 
       
   979 	/* Do we want to advertise 100 Mb Half Duplex? */
       
   980 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
       
   981 		hw_dbg(hw, "Advertise 100mb Half duplex\n");
       
   982 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
       
   983 	}
       
   984 
       
   985 	/* Do we want to advertise 100 Mb Full Duplex? */
       
   986 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
       
   987 		hw_dbg(hw, "Advertise 100mb Full duplex\n");
       
   988 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
       
   989 	}
       
   990 
       
   991 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
       
   992 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
       
   993 		hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
       
   994 
       
   995 	/* Do we want to advertise 1000 Mb Full Duplex? */
       
   996 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
       
   997 		hw_dbg(hw, "Advertise 1000mb Full duplex\n");
       
   998 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
       
   999 	}
       
  1000 
       
  1001 	/*
       
  1002 	 * Check for a software override of the flow control settings, and
       
  1003 	 * setup the PHY advertisement registers accordingly.  If
       
  1004 	 * auto-negotiation is enabled, then software will have to set the
       
  1005 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
       
  1006 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
       
  1007 	 * negotiation.
       
  1008 	 *
       
  1009 	 * The possible values of the "fc" parameter are:
       
  1010 	 *      0:  Flow control is completely disabled
       
  1011 	 *      1:  Rx flow control is enabled (we can receive pause frames
       
  1012 	 *	  but not send pause frames).
       
  1013 	 *      2:  Tx flow control is enabled (we can send pause frames
       
  1014 	 *	  but we do not support receiving pause frames).
       
  1015 	 *      3:  Both Rx and Tx flow control (symmetric) are enabled.
       
  1016 	 *  other:  No software override.  The flow control configuration
       
  1017 	 *	  in the EEPROM is used.
       
  1018 	 */
       
  1019 	switch (hw->fc.current_mode) {
       
  1020 	case e1000_fc_none:
       
  1021 		/*
       
  1022 		 * Flow control (Rx & Tx) is completely disabled by a
       
  1023 		 * software over-ride.
       
  1024 		 */
       
  1025 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
       
  1026 		break;
       
  1027 	case e1000_fc_rx_pause:
       
  1028 		/*
       
  1029 		 * Rx Flow control is enabled, and Tx Flow control is
       
  1030 		 * disabled, by a software over-ride.
       
  1031 		 *
       
  1032 		 * Since there really isn't a way to advertise that we are
       
  1033 		 * capable of Rx Pause ONLY, we will advertise that we
       
  1034 		 * support both symmetric and asymmetric Rx PAUSE.  Later
       
  1035 		 * (in e1000e_config_fc_after_link_up) we will disable the
       
  1036 		 * hw's ability to send PAUSE frames.
       
  1037 		 */
       
  1038 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
       
  1039 		break;
       
  1040 	case e1000_fc_tx_pause:
       
  1041 		/*
       
  1042 		 * Tx Flow control is enabled, and Rx Flow control is
       
  1043 		 * disabled, by a software over-ride.
       
  1044 		 */
       
  1045 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
       
  1046 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
       
  1047 		break;
       
  1048 	case e1000_fc_full:
       
  1049 		/*
       
  1050 		 * Flow control (both Rx and Tx) is enabled by a software
       
  1051 		 * over-ride.
       
  1052 		 */
       
  1053 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
       
  1054 		break;
       
  1055 	default:
       
  1056 		hw_dbg(hw, "Flow control param set incorrectly\n");
       
  1057 		ret_val = -E1000_ERR_CONFIG;
       
  1058 		return ret_val;
       
  1059 	}
       
  1060 
       
  1061 	ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
       
  1062 	if (ret_val)
       
  1063 		return ret_val;
       
  1064 
       
  1065 	hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
       
  1066 
       
  1067 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
       
  1068 		ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
       
  1069 	}
       
  1070 
       
  1071 	return ret_val;
       
  1072 }
       
  1073 
       
  1074 /**
       
  1075  *  e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
       
  1076  *  @hw: pointer to the HW structure
       
  1077  *
       
  1078  *  Performs initial bounds checking on autoneg advertisement parameter, then
       
  1079  *  configure to advertise the full capability.  Setup the PHY to autoneg
       
  1080  *  and restart the negotiation process between the link partner.  If
       
  1081  *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
       
  1082  **/
       
  1083 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
       
  1084 {
       
  1085 	struct e1000_phy_info *phy = &hw->phy;
       
  1086 	s32 ret_val;
       
  1087 	u16 phy_ctrl;
       
  1088 
       
  1089 	/*
       
  1090 	 * Perform some bounds checking on the autoneg advertisement
       
  1091 	 * parameter.
       
  1092 	 */
       
  1093 	phy->autoneg_advertised &= phy->autoneg_mask;
       
  1094 
       
  1095 	/*
       
  1096 	 * If autoneg_advertised is zero, we assume it was not defaulted
       
  1097 	 * by the calling code so we set to advertise full capability.
       
  1098 	 */
       
  1099 	if (phy->autoneg_advertised == 0)
       
  1100 		phy->autoneg_advertised = phy->autoneg_mask;
       
  1101 
       
  1102 	hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
       
  1103 	ret_val = e1000_phy_setup_autoneg(hw);
       
  1104 	if (ret_val) {
       
  1105 		hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
       
  1106 		return ret_val;
       
  1107 	}
       
  1108 	hw_dbg(hw, "Restarting Auto-Neg\n");
       
  1109 
       
  1110 	/*
       
  1111 	 * Restart auto-negotiation by setting the Auto Neg Enable bit and
       
  1112 	 * the Auto Neg Restart bit in the PHY control register.
       
  1113 	 */
       
  1114 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
       
  1115 	if (ret_val)
       
  1116 		return ret_val;
       
  1117 
       
  1118 	phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
       
  1119 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
       
  1120 	if (ret_val)
       
  1121 		return ret_val;
       
  1122 
       
  1123 	/*
       
  1124 	 * Does the user want to wait for Auto-Neg to complete here, or
       
  1125 	 * check at a later time (for example, callback routine).
       
  1126 	 */
       
  1127 	if (phy->autoneg_wait_to_complete) {
       
  1128 		ret_val = e1000_wait_autoneg(hw);
       
  1129 		if (ret_val) {
       
  1130 			hw_dbg(hw, "Error while waiting for "
       
  1131 				 "autoneg to complete\n");
       
  1132 			return ret_val;
       
  1133 		}
       
  1134 	}
       
  1135 
       
  1136 	hw->mac.get_link_status = 1;
       
  1137 
       
  1138 	return ret_val;
       
  1139 }
       
  1140 
       
  1141 /**
       
  1142  *  e1000e_setup_copper_link - Configure copper link settings
       
  1143  *  @hw: pointer to the HW structure
       
  1144  *
       
  1145  *  Calls the appropriate function to configure the link for auto-neg or forced
       
  1146  *  speed and duplex.  Then we check for link, once link is established calls
       
  1147  *  to configure collision distance and flow control are called.  If link is
       
  1148  *  not established, we return -E1000_ERR_PHY (-2).
       
  1149  **/
       
  1150 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
       
  1151 {
       
  1152 	s32 ret_val;
       
  1153 	bool link;
       
  1154 
       
  1155 	if (hw->mac.autoneg) {
       
  1156 		/*
       
  1157 		 * Setup autoneg and flow control advertisement and perform
       
  1158 		 * autonegotiation.
       
  1159 		 */
       
  1160 		ret_val = e1000_copper_link_autoneg(hw);
       
  1161 		if (ret_val)
       
  1162 			return ret_val;
       
  1163 	} else {
       
  1164 		/*
       
  1165 		 * PHY will be set to 10H, 10F, 100H or 100F
       
  1166 		 * depending on user settings.
       
  1167 		 */
       
  1168 		hw_dbg(hw, "Forcing Speed and Duplex\n");
       
  1169 		ret_val = e1000_phy_force_speed_duplex(hw);
       
  1170 		if (ret_val) {
       
  1171 			hw_dbg(hw, "Error Forcing Speed and Duplex\n");
       
  1172 			return ret_val;
       
  1173 		}
       
  1174 	}
       
  1175 
       
  1176 	/*
       
  1177 	 * Check link status. Wait up to 100 microseconds for link to become
       
  1178 	 * valid.
       
  1179 	 */
       
  1180 	ret_val = e1000e_phy_has_link_generic(hw,
       
  1181 					     COPPER_LINK_UP_LIMIT,
       
  1182 					     10,
       
  1183 					     &link);
       
  1184 	if (ret_val)
       
  1185 		return ret_val;
       
  1186 
       
  1187 	if (link) {
       
  1188 		hw_dbg(hw, "Valid link established!!!\n");
       
  1189 		e1000e_config_collision_dist(hw);
       
  1190 		ret_val = e1000e_config_fc_after_link_up(hw);
       
  1191 	} else {
       
  1192 		hw_dbg(hw, "Unable to establish link!!!\n");
       
  1193 	}
       
  1194 
       
  1195 	return ret_val;
       
  1196 }
       
  1197 
       
  1198 /**
       
  1199  *  e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
       
  1200  *  @hw: pointer to the HW structure
       
  1201  *
       
  1202  *  Calls the PHY setup function to force speed and duplex.  Clears the
       
  1203  *  auto-crossover to force MDI manually.  Waits for link and returns
       
  1204  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
       
  1205  **/
       
  1206 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
       
  1207 {
       
  1208 	struct e1000_phy_info *phy = &hw->phy;
       
  1209 	s32 ret_val;
       
  1210 	u16 phy_data;
       
  1211 	bool link;
       
  1212 
       
  1213 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
       
  1214 	if (ret_val)
       
  1215 		return ret_val;
       
  1216 
       
  1217 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
       
  1218 
       
  1219 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
       
  1220 	if (ret_val)
       
  1221 		return ret_val;
       
  1222 
       
  1223 	/*
       
  1224 	 * Clear Auto-Crossover to force MDI manually.  IGP requires MDI
       
  1225 	 * forced whenever speed and duplex are forced.
       
  1226 	 */
       
  1227 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
       
  1228 	if (ret_val)
       
  1229 		return ret_val;
       
  1230 
       
  1231 	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
       
  1232 	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
       
  1233 
       
  1234 	ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
       
  1235 	if (ret_val)
       
  1236 		return ret_val;
       
  1237 
       
  1238 	hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
       
  1239 
       
  1240 	udelay(1);
       
  1241 
       
  1242 	if (phy->autoneg_wait_to_complete) {
       
  1243 		hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
       
  1244 
       
  1245 		ret_val = e1000e_phy_has_link_generic(hw,
       
  1246 						     PHY_FORCE_LIMIT,
       
  1247 						     100000,
       
  1248 						     &link);
       
  1249 		if (ret_val)
       
  1250 			return ret_val;
       
  1251 
       
  1252 		if (!link)
       
  1253 			hw_dbg(hw, "Link taking longer than expected.\n");
       
  1254 
       
  1255 		/* Try once more */
       
  1256 		ret_val = e1000e_phy_has_link_generic(hw,
       
  1257 						     PHY_FORCE_LIMIT,
       
  1258 						     100000,
       
  1259 						     &link);
       
  1260 		if (ret_val)
       
  1261 			return ret_val;
       
  1262 	}
       
  1263 
       
  1264 	return ret_val;
       
  1265 }
       
  1266 
       
  1267 /**
       
  1268  *  e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
       
  1269  *  @hw: pointer to the HW structure
       
  1270  *
       
  1271  *  Calls the PHY setup function to force speed and duplex.  Clears the
       
  1272  *  auto-crossover to force MDI manually.  Resets the PHY to commit the
       
  1273  *  changes.  If time expires while waiting for link up, we reset the DSP.
       
  1274  *  After reset, TX_CLK and CRS on Tx must be set.  Return successful upon
       
  1275  *  successful completion, else return corresponding error code.
       
  1276  **/
       
  1277 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
       
  1278 {
       
  1279 	struct e1000_phy_info *phy = &hw->phy;
       
  1280 	s32 ret_val;
       
  1281 	u16 phy_data;
       
  1282 	bool link;
       
  1283 
       
  1284 	/*
       
  1285 	 * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
       
  1286 	 * forced whenever speed and duplex are forced.
       
  1287 	 */
       
  1288 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
       
  1289 	if (ret_val)
       
  1290 		return ret_val;
       
  1291 
       
  1292 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
       
  1293 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
       
  1294 	if (ret_val)
       
  1295 		return ret_val;
       
  1296 
       
  1297 	hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
       
  1298 
       
  1299 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
       
  1300 	if (ret_val)
       
  1301 		return ret_val;
       
  1302 
       
  1303 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
       
  1304 
       
  1305 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
       
  1306 	if (ret_val)
       
  1307 		return ret_val;
       
  1308 
       
  1309 	/* Reset the phy to commit changes. */
       
  1310 	ret_val = e1000e_commit_phy(hw);
       
  1311 	if (ret_val)
       
  1312 		return ret_val;
       
  1313 
       
  1314 	if (phy->autoneg_wait_to_complete) {
       
  1315 		hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
       
  1316 
       
  1317 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
       
  1318 						     100000, &link);
       
  1319 		if (ret_val)
       
  1320 			return ret_val;
       
  1321 
       
  1322 		if (!link) {
       
  1323 			/*
       
  1324 			 * We didn't get link.
       
  1325 			 * Reset the DSP and cross our fingers.
       
  1326 			 */
       
  1327 			ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
       
  1328 					   0x001d);
       
  1329 			if (ret_val)
       
  1330 				return ret_val;
       
  1331 			ret_val = e1000e_phy_reset_dsp(hw);
       
  1332 			if (ret_val)
       
  1333 				return ret_val;
       
  1334 		}
       
  1335 
       
  1336 		/* Try once more */
       
  1337 		ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
       
  1338 						     100000, &link);
       
  1339 		if (ret_val)
       
  1340 			return ret_val;
       
  1341 	}
       
  1342 
       
  1343 	ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
       
  1344 	if (ret_val)
       
  1345 		return ret_val;
       
  1346 
       
  1347 	/*
       
  1348 	 * Resetting the phy means we need to re-force TX_CLK in the
       
  1349 	 * Extended PHY Specific Control Register to 25MHz clock from
       
  1350 	 * the reset value of 2.5MHz.
       
  1351 	 */
       
  1352 	phy_data |= M88E1000_EPSCR_TX_CLK_25;
       
  1353 	ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
       
  1354 	if (ret_val)
       
  1355 		return ret_val;
       
  1356 
       
  1357 	/*
       
  1358 	 * In addition, we must re-enable CRS on Tx for both half and full
       
  1359 	 * duplex.
       
  1360 	 */
       
  1361 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
       
  1362 	if (ret_val)
       
  1363 		return ret_val;
       
  1364 
       
  1365 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
       
  1366 	ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
       
  1367 
       
  1368 	return ret_val;
       
  1369 }
       
  1370 
       
  1371 /**
       
  1372  *  e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
       
  1373  *  @hw: pointer to the HW structure
       
  1374  *  @phy_ctrl: pointer to current value of PHY_CONTROL
       
  1375  *
       
  1376  *  Forces speed and duplex on the PHY by doing the following: disable flow
       
  1377  *  control, force speed/duplex on the MAC, disable auto speed detection,
       
  1378  *  disable auto-negotiation, configure duplex, configure speed, configure
       
  1379  *  the collision distance, write configuration to CTRL register.  The
       
  1380  *  caller must write to the PHY_CONTROL register for these settings to
       
  1381  *  take affect.
       
  1382  **/
       
  1383 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
       
  1384 {
       
  1385 	struct e1000_mac_info *mac = &hw->mac;
       
  1386 	u32 ctrl;
       
  1387 
       
  1388 	/* Turn off flow control when forcing speed/duplex */
       
  1389 	hw->fc.current_mode = e1000_fc_none;
       
  1390 
       
  1391 	/* Force speed/duplex on the mac */
       
  1392 	ctrl = er32(CTRL);
       
  1393 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
       
  1394 	ctrl &= ~E1000_CTRL_SPD_SEL;
       
  1395 
       
  1396 	/* Disable Auto Speed Detection */
       
  1397 	ctrl &= ~E1000_CTRL_ASDE;
       
  1398 
       
  1399 	/* Disable autoneg on the phy */
       
  1400 	*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
       
  1401 
       
  1402 	/* Forcing Full or Half Duplex? */
       
  1403 	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
       
  1404 		ctrl &= ~E1000_CTRL_FD;
       
  1405 		*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
       
  1406 		hw_dbg(hw, "Half Duplex\n");
       
  1407 	} else {
       
  1408 		ctrl |= E1000_CTRL_FD;
       
  1409 		*phy_ctrl |= MII_CR_FULL_DUPLEX;
       
  1410 		hw_dbg(hw, "Full Duplex\n");
       
  1411 	}
       
  1412 
       
  1413 	/* Forcing 10mb or 100mb? */
       
  1414 	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
       
  1415 		ctrl |= E1000_CTRL_SPD_100;
       
  1416 		*phy_ctrl |= MII_CR_SPEED_100;
       
  1417 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
       
  1418 		hw_dbg(hw, "Forcing 100mb\n");
       
  1419 	} else {
       
  1420 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
       
  1421 		*phy_ctrl |= MII_CR_SPEED_10;
       
  1422 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
       
  1423 		hw_dbg(hw, "Forcing 10mb\n");
       
  1424 	}
       
  1425 
       
  1426 	e1000e_config_collision_dist(hw);
       
  1427 
       
  1428 	ew32(CTRL, ctrl);
       
  1429 }
       
  1430 
       
  1431 /**
       
  1432  *  e1000e_set_d3_lplu_state - Sets low power link up state for D3
       
  1433  *  @hw: pointer to the HW structure
       
  1434  *  @active: boolean used to enable/disable lplu
       
  1435  *
       
  1436  *  Success returns 0, Failure returns 1
       
  1437  *
       
  1438  *  The low power link up (lplu) state is set to the power management level D3
       
  1439  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
       
  1440  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
       
  1441  *  is used during Dx states where the power conservation is most important.
       
  1442  *  During driver activity, SmartSpeed should be enabled so performance is
       
  1443  *  maintained.
       
  1444  **/
       
  1445 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
       
  1446 {
       
  1447 	struct e1000_phy_info *phy = &hw->phy;
       
  1448 	s32 ret_val;
       
  1449 	u16 data;
       
  1450 
       
  1451 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
       
  1452 	if (ret_val)
       
  1453 		return ret_val;
       
  1454 
       
  1455 	if (!active) {
       
  1456 		data &= ~IGP02E1000_PM_D3_LPLU;
       
  1457 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
       
  1458 		if (ret_val)
       
  1459 			return ret_val;
       
  1460 		/*
       
  1461 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
       
  1462 		 * during Dx states where the power conservation is most
       
  1463 		 * important.  During driver activity we should enable
       
  1464 		 * SmartSpeed, so performance is maintained.
       
  1465 		 */
       
  1466 		if (phy->smart_speed == e1000_smart_speed_on) {
       
  1467 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1468 					   &data);
       
  1469 			if (ret_val)
       
  1470 				return ret_val;
       
  1471 
       
  1472 			data |= IGP01E1000_PSCFR_SMART_SPEED;
       
  1473 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1474 					   data);
       
  1475 			if (ret_val)
       
  1476 				return ret_val;
       
  1477 		} else if (phy->smart_speed == e1000_smart_speed_off) {
       
  1478 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1479 					   &data);
       
  1480 			if (ret_val)
       
  1481 				return ret_val;
       
  1482 
       
  1483 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1484 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
       
  1485 					   data);
       
  1486 			if (ret_val)
       
  1487 				return ret_val;
       
  1488 		}
       
  1489 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
       
  1490 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
       
  1491 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
       
  1492 		data |= IGP02E1000_PM_D3_LPLU;
       
  1493 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
       
  1494 		if (ret_val)
       
  1495 			return ret_val;
       
  1496 
       
  1497 		/* When LPLU is enabled, we should disable SmartSpeed */
       
  1498 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
       
  1499 		if (ret_val)
       
  1500 			return ret_val;
       
  1501 
       
  1502 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
       
  1503 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
       
  1504 	}
       
  1505 
       
  1506 	return ret_val;
       
  1507 }
       
  1508 
       
  1509 /**
       
  1510  *  e1000e_check_downshift - Checks whether a downshift in speed occurred
       
  1511  *  @hw: pointer to the HW structure
       
  1512  *
       
  1513  *  Success returns 0, Failure returns 1
       
  1514  *
       
  1515  *  A downshift is detected by querying the PHY link health.
       
  1516  **/
       
  1517 s32 e1000e_check_downshift(struct e1000_hw *hw)
       
  1518 {
       
  1519 	struct e1000_phy_info *phy = &hw->phy;
       
  1520 	s32 ret_val;
       
  1521 	u16 phy_data, offset, mask;
       
  1522 
       
  1523 	switch (phy->type) {
       
  1524 	case e1000_phy_m88:
       
  1525 	case e1000_phy_gg82563:
       
  1526 	case e1000_phy_82578:
       
  1527 	case e1000_phy_82577:
       
  1528 		offset	= M88E1000_PHY_SPEC_STATUS;
       
  1529 		mask	= M88E1000_PSSR_DOWNSHIFT;
       
  1530 		break;
       
  1531 	case e1000_phy_igp_2:
       
  1532 	case e1000_phy_igp_3:
       
  1533 		offset	= IGP01E1000_PHY_LINK_HEALTH;
       
  1534 		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
       
  1535 		break;
       
  1536 	default:
       
  1537 		/* speed downshift not supported */
       
  1538 		phy->speed_downgraded = 0;
       
  1539 		return 0;
       
  1540 	}
       
  1541 
       
  1542 	ret_val = e1e_rphy(hw, offset, &phy_data);
       
  1543 
       
  1544 	if (!ret_val)
       
  1545 		phy->speed_downgraded = (phy_data & mask);
       
  1546 
       
  1547 	return ret_val;
       
  1548 }
       
  1549 
       
  1550 /**
       
  1551  *  e1000_check_polarity_m88 - Checks the polarity.
       
  1552  *  @hw: pointer to the HW structure
       
  1553  *
       
  1554  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
       
  1555  *
       
  1556  *  Polarity is determined based on the PHY specific status register.
       
  1557  **/
       
  1558 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
       
  1559 {
       
  1560 	struct e1000_phy_info *phy = &hw->phy;
       
  1561 	s32 ret_val;
       
  1562 	u16 data;
       
  1563 
       
  1564 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
       
  1565 
       
  1566 	if (!ret_val)
       
  1567 		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
       
  1568 				      ? e1000_rev_polarity_reversed
       
  1569 				      : e1000_rev_polarity_normal;
       
  1570 
       
  1571 	return ret_val;
       
  1572 }
       
  1573 
       
  1574 /**
       
  1575  *  e1000_check_polarity_igp - Checks the polarity.
       
  1576  *  @hw: pointer to the HW structure
       
  1577  *
       
  1578  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
       
  1579  *
       
  1580  *  Polarity is determined based on the PHY port status register, and the
       
  1581  *  current speed (since there is no polarity at 100Mbps).
       
  1582  **/
       
  1583 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
       
  1584 {
       
  1585 	struct e1000_phy_info *phy = &hw->phy;
       
  1586 	s32 ret_val;
       
  1587 	u16 data, offset, mask;
       
  1588 
       
  1589 	/*
       
  1590 	 * Polarity is determined based on the speed of
       
  1591 	 * our connection.
       
  1592 	 */
       
  1593 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
       
  1594 	if (ret_val)
       
  1595 		return ret_val;
       
  1596 
       
  1597 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
       
  1598 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
       
  1599 		offset	= IGP01E1000_PHY_PCS_INIT_REG;
       
  1600 		mask	= IGP01E1000_PHY_POLARITY_MASK;
       
  1601 	} else {
       
  1602 		/*
       
  1603 		 * This really only applies to 10Mbps since
       
  1604 		 * there is no polarity for 100Mbps (always 0).
       
  1605 		 */
       
  1606 		offset	= IGP01E1000_PHY_PORT_STATUS;
       
  1607 		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
       
  1608 	}
       
  1609 
       
  1610 	ret_val = e1e_rphy(hw, offset, &data);
       
  1611 
       
  1612 	if (!ret_val)
       
  1613 		phy->cable_polarity = (data & mask)
       
  1614 				      ? e1000_rev_polarity_reversed
       
  1615 				      : e1000_rev_polarity_normal;
       
  1616 
       
  1617 	return ret_val;
       
  1618 }
       
  1619 
       
  1620 /**
       
  1621  *  e1000_wait_autoneg - Wait for auto-neg completion
       
  1622  *  @hw: pointer to the HW structure
       
  1623  *
       
  1624  *  Waits for auto-negotiation to complete or for the auto-negotiation time
       
  1625  *  limit to expire, which ever happens first.
       
  1626  **/
       
  1627 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
       
  1628 {
       
  1629 	s32 ret_val = 0;
       
  1630 	u16 i, phy_status;
       
  1631 
       
  1632 	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
       
  1633 	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
       
  1634 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
       
  1635 		if (ret_val)
       
  1636 			break;
       
  1637 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
       
  1638 		if (ret_val)
       
  1639 			break;
       
  1640 		if (phy_status & MII_SR_AUTONEG_COMPLETE)
       
  1641 			break;
       
  1642 		msleep(100);
       
  1643 	}
       
  1644 
       
  1645 	/*
       
  1646 	 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
       
  1647 	 * has completed.
       
  1648 	 */
       
  1649 	return ret_val;
       
  1650 }
       
  1651 
       
  1652 /**
       
  1653  *  e1000e_phy_has_link_generic - Polls PHY for link
       
  1654  *  @hw: pointer to the HW structure
       
  1655  *  @iterations: number of times to poll for link
       
  1656  *  @usec_interval: delay between polling attempts
       
  1657  *  @success: pointer to whether polling was successful or not
       
  1658  *
       
  1659  *  Polls the PHY status register for link, 'iterations' number of times.
       
  1660  **/
       
  1661 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
       
  1662 			       u32 usec_interval, bool *success)
       
  1663 {
       
  1664 	s32 ret_val = 0;
       
  1665 	u16 i, phy_status;
       
  1666 
       
  1667 	for (i = 0; i < iterations; i++) {
       
  1668 		/*
       
  1669 		 * Some PHYs require the PHY_STATUS register to be read
       
  1670 		 * twice due to the link bit being sticky.  No harm doing
       
  1671 		 * it across the board.
       
  1672 		 */
       
  1673 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
       
  1674 		if (ret_val)
       
  1675 			/*
       
  1676 			 * If the first read fails, another entity may have
       
  1677 			 * ownership of the resources, wait and try again to
       
  1678 			 * see if they have relinquished the resources yet.
       
  1679 			 */
       
  1680 			udelay(usec_interval);
       
  1681 		ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
       
  1682 		if (ret_val)
       
  1683 			break;
       
  1684 		if (phy_status & MII_SR_LINK_STATUS)
       
  1685 			break;
       
  1686 		if (usec_interval >= 1000)
       
  1687 			mdelay(usec_interval/1000);
       
  1688 		else
       
  1689 			udelay(usec_interval);
       
  1690 	}
       
  1691 
       
  1692 	*success = (i < iterations);
       
  1693 
       
  1694 	return ret_val;
       
  1695 }
       
  1696 
       
  1697 /**
       
  1698  *  e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
       
  1699  *  @hw: pointer to the HW structure
       
  1700  *
       
  1701  *  Reads the PHY specific status register to retrieve the cable length
       
  1702  *  information.  The cable length is determined by averaging the minimum and
       
  1703  *  maximum values to get the "average" cable length.  The m88 PHY has four
       
  1704  *  possible cable length values, which are:
       
  1705  *	Register Value		Cable Length
       
  1706  *	0			< 50 meters
       
  1707  *	1			50 - 80 meters
       
  1708  *	2			80 - 110 meters
       
  1709  *	3			110 - 140 meters
       
  1710  *	4			> 140 meters
       
  1711  **/
       
  1712 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
       
  1713 {
       
  1714 	struct e1000_phy_info *phy = &hw->phy;
       
  1715 	s32 ret_val;
       
  1716 	u16 phy_data, index;
       
  1717 
       
  1718 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
       
  1719 	if (ret_val)
       
  1720 		return ret_val;
       
  1721 
       
  1722 	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
       
  1723 		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
       
  1724 	phy->min_cable_length = e1000_m88_cable_length_table[index];
       
  1725 	phy->max_cable_length = e1000_m88_cable_length_table[index+1];
       
  1726 
       
  1727 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
       
  1728 
       
  1729 	return ret_val;
       
  1730 }
       
  1731 
       
  1732 /**
       
  1733  *  e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
       
  1734  *  @hw: pointer to the HW structure
       
  1735  *
       
  1736  *  The automatic gain control (agc) normalizes the amplitude of the
       
  1737  *  received signal, adjusting for the attenuation produced by the
       
  1738  *  cable.  By reading the AGC registers, which represent the
       
  1739  *  combination of course and fine gain value, the value can be put
       
  1740  *  into a lookup table to obtain the approximate cable length
       
  1741  *  for each channel.
       
  1742  **/
       
  1743 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
       
  1744 {
       
  1745 	struct e1000_phy_info *phy = &hw->phy;
       
  1746 	s32 ret_val;
       
  1747 	u16 phy_data, i, agc_value = 0;
       
  1748 	u16 cur_agc_index, max_agc_index = 0;
       
  1749 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
       
  1750 	u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
       
  1751 							 {IGP02E1000_PHY_AGC_A,
       
  1752 							  IGP02E1000_PHY_AGC_B,
       
  1753 							  IGP02E1000_PHY_AGC_C,
       
  1754 							  IGP02E1000_PHY_AGC_D};
       
  1755 
       
  1756 	/* Read the AGC registers for all channels */
       
  1757 	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
       
  1758 		ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
       
  1759 		if (ret_val)
       
  1760 			return ret_val;
       
  1761 
       
  1762 		/*
       
  1763 		 * Getting bits 15:9, which represent the combination of
       
  1764 		 * course and fine gain values.  The result is a number
       
  1765 		 * that can be put into the lookup table to obtain the
       
  1766 		 * approximate cable length.
       
  1767 		 */
       
  1768 		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
       
  1769 				IGP02E1000_AGC_LENGTH_MASK;
       
  1770 
       
  1771 		/* Array index bound check. */
       
  1772 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
       
  1773 		    (cur_agc_index == 0))
       
  1774 			return -E1000_ERR_PHY;
       
  1775 
       
  1776 		/* Remove min & max AGC values from calculation. */
       
  1777 		if (e1000_igp_2_cable_length_table[min_agc_index] >
       
  1778 		    e1000_igp_2_cable_length_table[cur_agc_index])
       
  1779 			min_agc_index = cur_agc_index;
       
  1780 		if (e1000_igp_2_cable_length_table[max_agc_index] <
       
  1781 		    e1000_igp_2_cable_length_table[cur_agc_index])
       
  1782 			max_agc_index = cur_agc_index;
       
  1783 
       
  1784 		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
       
  1785 	}
       
  1786 
       
  1787 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
       
  1788 		      e1000_igp_2_cable_length_table[max_agc_index]);
       
  1789 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
       
  1790 
       
  1791 	/* Calculate cable length with the error range of +/- 10 meters. */
       
  1792 	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
       
  1793 				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
       
  1794 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
       
  1795 
       
  1796 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
       
  1797 
       
  1798 	return ret_val;
       
  1799 }
       
  1800 
       
  1801 /**
       
  1802  *  e1000e_get_phy_info_m88 - Retrieve PHY information
       
  1803  *  @hw: pointer to the HW structure
       
  1804  *
       
  1805  *  Valid for only copper links.  Read the PHY status register (sticky read)
       
  1806  *  to verify that link is up.  Read the PHY special control register to
       
  1807  *  determine the polarity and 10base-T extended distance.  Read the PHY
       
  1808  *  special status register to determine MDI/MDIx and current speed.  If
       
  1809  *  speed is 1000, then determine cable length, local and remote receiver.
       
  1810  **/
       
  1811 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
       
  1812 {
       
  1813 	struct e1000_phy_info *phy = &hw->phy;
       
  1814 	s32  ret_val;
       
  1815 	u16 phy_data;
       
  1816 	bool link;
       
  1817 
       
  1818 	if (hw->phy.media_type != e1000_media_type_copper) {
       
  1819 		hw_dbg(hw, "Phy info is only valid for copper media\n");
       
  1820 		return -E1000_ERR_CONFIG;
       
  1821 	}
       
  1822 
       
  1823 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
       
  1824 	if (ret_val)
       
  1825 		return ret_val;
       
  1826 
       
  1827 	if (!link) {
       
  1828 		hw_dbg(hw, "Phy info is only valid if link is up\n");
       
  1829 		return -E1000_ERR_CONFIG;
       
  1830 	}
       
  1831 
       
  1832 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
       
  1833 	if (ret_val)
       
  1834 		return ret_val;
       
  1835 
       
  1836 	phy->polarity_correction = (phy_data &
       
  1837 				    M88E1000_PSCR_POLARITY_REVERSAL);
       
  1838 
       
  1839 	ret_val = e1000_check_polarity_m88(hw);
       
  1840 	if (ret_val)
       
  1841 		return ret_val;
       
  1842 
       
  1843 	ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
       
  1844 	if (ret_val)
       
  1845 		return ret_val;
       
  1846 
       
  1847 	phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
       
  1848 
       
  1849 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
       
  1850 		ret_val = e1000_get_cable_length(hw);
       
  1851 		if (ret_val)
       
  1852 			return ret_val;
       
  1853 
       
  1854 		ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
       
  1855 		if (ret_val)
       
  1856 			return ret_val;
       
  1857 
       
  1858 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
       
  1859 				? e1000_1000t_rx_status_ok
       
  1860 				: e1000_1000t_rx_status_not_ok;
       
  1861 
       
  1862 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
       
  1863 				 ? e1000_1000t_rx_status_ok
       
  1864 				 : e1000_1000t_rx_status_not_ok;
       
  1865 	} else {
       
  1866 		/* Set values to "undefined" */
       
  1867 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
       
  1868 		phy->local_rx = e1000_1000t_rx_status_undefined;
       
  1869 		phy->remote_rx = e1000_1000t_rx_status_undefined;
       
  1870 	}
       
  1871 
       
  1872 	return ret_val;
       
  1873 }
       
  1874 
       
  1875 /**
       
  1876  *  e1000e_get_phy_info_igp - Retrieve igp PHY information
       
  1877  *  @hw: pointer to the HW structure
       
  1878  *
       
  1879  *  Read PHY status to determine if link is up.  If link is up, then
       
  1880  *  set/determine 10base-T extended distance and polarity correction.  Read
       
  1881  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
       
  1882  *  determine on the cable length, local and remote receiver.
       
  1883  **/
       
  1884 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
       
  1885 {
       
  1886 	struct e1000_phy_info *phy = &hw->phy;
       
  1887 	s32 ret_val;
       
  1888 	u16 data;
       
  1889 	bool link;
       
  1890 
       
  1891 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
       
  1892 	if (ret_val)
       
  1893 		return ret_val;
       
  1894 
       
  1895 	if (!link) {
       
  1896 		hw_dbg(hw, "Phy info is only valid if link is up\n");
       
  1897 		return -E1000_ERR_CONFIG;
       
  1898 	}
       
  1899 
       
  1900 	phy->polarity_correction = 1;
       
  1901 
       
  1902 	ret_val = e1000_check_polarity_igp(hw);
       
  1903 	if (ret_val)
       
  1904 		return ret_val;
       
  1905 
       
  1906 	ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
       
  1907 	if (ret_val)
       
  1908 		return ret_val;
       
  1909 
       
  1910 	phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
       
  1911 
       
  1912 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
       
  1913 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
       
  1914 		ret_val = e1000_get_cable_length(hw);
       
  1915 		if (ret_val)
       
  1916 			return ret_val;
       
  1917 
       
  1918 		ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
       
  1919 		if (ret_val)
       
  1920 			return ret_val;
       
  1921 
       
  1922 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
       
  1923 				? e1000_1000t_rx_status_ok
       
  1924 				: e1000_1000t_rx_status_not_ok;
       
  1925 
       
  1926 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
       
  1927 				 ? e1000_1000t_rx_status_ok
       
  1928 				 : e1000_1000t_rx_status_not_ok;
       
  1929 	} else {
       
  1930 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
       
  1931 		phy->local_rx = e1000_1000t_rx_status_undefined;
       
  1932 		phy->remote_rx = e1000_1000t_rx_status_undefined;
       
  1933 	}
       
  1934 
       
  1935 	return ret_val;
       
  1936 }
       
  1937 
       
  1938 /**
       
  1939  *  e1000e_phy_sw_reset - PHY software reset
       
  1940  *  @hw: pointer to the HW structure
       
  1941  *
       
  1942  *  Does a software reset of the PHY by reading the PHY control register and
       
  1943  *  setting/write the control register reset bit to the PHY.
       
  1944  **/
       
  1945 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
       
  1946 {
       
  1947 	s32 ret_val;
       
  1948 	u16 phy_ctrl;
       
  1949 
       
  1950 	ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
       
  1951 	if (ret_val)
       
  1952 		return ret_val;
       
  1953 
       
  1954 	phy_ctrl |= MII_CR_RESET;
       
  1955 	ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
       
  1956 	if (ret_val)
       
  1957 		return ret_val;
       
  1958 
       
  1959 	udelay(1);
       
  1960 
       
  1961 	return ret_val;
       
  1962 }
       
  1963 
       
  1964 /**
       
  1965  *  e1000e_phy_hw_reset_generic - PHY hardware reset
       
  1966  *  @hw: pointer to the HW structure
       
  1967  *
       
  1968  *  Verify the reset block is not blocking us from resetting.  Acquire
       
  1969  *  semaphore (if necessary) and read/set/write the device control reset
       
  1970  *  bit in the PHY.  Wait the appropriate delay time for the device to
       
  1971  *  reset and release the semaphore (if necessary).
       
  1972  **/
       
  1973 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
       
  1974 {
       
  1975 	struct e1000_phy_info *phy = &hw->phy;
       
  1976 	s32 ret_val;
       
  1977 	u32 ctrl;
       
  1978 
       
  1979 	ret_val = e1000_check_reset_block(hw);
       
  1980 	if (ret_val)
       
  1981 		return 0;
       
  1982 
       
  1983 	ret_val = phy->ops.acquire_phy(hw);
       
  1984 	if (ret_val)
       
  1985 		return ret_val;
       
  1986 
       
  1987 	ctrl = er32(CTRL);
       
  1988 	ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
       
  1989 	e1e_flush();
       
  1990 
       
  1991 	udelay(phy->reset_delay_us);
       
  1992 
       
  1993 	ew32(CTRL, ctrl);
       
  1994 	e1e_flush();
       
  1995 
       
  1996 	udelay(150);
       
  1997 
       
  1998 	phy->ops.release_phy(hw);
       
  1999 
       
  2000 	return e1000_get_phy_cfg_done(hw);
       
  2001 }
       
  2002 
       
  2003 /**
       
  2004  *  e1000e_get_cfg_done - Generic configuration done
       
  2005  *  @hw: pointer to the HW structure
       
  2006  *
       
  2007  *  Generic function to wait 10 milli-seconds for configuration to complete
       
  2008  *  and return success.
       
  2009  **/
       
  2010 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
       
  2011 {
       
  2012 	mdelay(10);
       
  2013 	return 0;
       
  2014 }
       
  2015 
       
  2016 /**
       
  2017  *  e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
       
  2018  *  @hw: pointer to the HW structure
       
  2019  *
       
  2020  *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
       
  2021  **/
       
  2022 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
       
  2023 {
       
  2024 	hw_dbg(hw, "Running IGP 3 PHY init script\n");
       
  2025 
       
  2026 	/* PHY init IGP 3 */
       
  2027 	/* Enable rise/fall, 10-mode work in class-A */
       
  2028 	e1e_wphy(hw, 0x2F5B, 0x9018);
       
  2029 	/* Remove all caps from Replica path filter */
       
  2030 	e1e_wphy(hw, 0x2F52, 0x0000);
       
  2031 	/* Bias trimming for ADC, AFE and Driver (Default) */
       
  2032 	e1e_wphy(hw, 0x2FB1, 0x8B24);
       
  2033 	/* Increase Hybrid poly bias */
       
  2034 	e1e_wphy(hw, 0x2FB2, 0xF8F0);
       
  2035 	/* Add 4% to Tx amplitude in Gig mode */
       
  2036 	e1e_wphy(hw, 0x2010, 0x10B0);
       
  2037 	/* Disable trimming (TTT) */
       
  2038 	e1e_wphy(hw, 0x2011, 0x0000);
       
  2039 	/* Poly DC correction to 94.6% + 2% for all channels */
       
  2040 	e1e_wphy(hw, 0x20DD, 0x249A);
       
  2041 	/* ABS DC correction to 95.9% */
       
  2042 	e1e_wphy(hw, 0x20DE, 0x00D3);
       
  2043 	/* BG temp curve trim */
       
  2044 	e1e_wphy(hw, 0x28B4, 0x04CE);
       
  2045 	/* Increasing ADC OPAMP stage 1 currents to max */
       
  2046 	e1e_wphy(hw, 0x2F70, 0x29E4);
       
  2047 	/* Force 1000 ( required for enabling PHY regs configuration) */
       
  2048 	e1e_wphy(hw, 0x0000, 0x0140);
       
  2049 	/* Set upd_freq to 6 */
       
  2050 	e1e_wphy(hw, 0x1F30, 0x1606);
       
  2051 	/* Disable NPDFE */
       
  2052 	e1e_wphy(hw, 0x1F31, 0xB814);
       
  2053 	/* Disable adaptive fixed FFE (Default) */
       
  2054 	e1e_wphy(hw, 0x1F35, 0x002A);
       
  2055 	/* Enable FFE hysteresis */
       
  2056 	e1e_wphy(hw, 0x1F3E, 0x0067);
       
  2057 	/* Fixed FFE for short cable lengths */
       
  2058 	e1e_wphy(hw, 0x1F54, 0x0065);
       
  2059 	/* Fixed FFE for medium cable lengths */
       
  2060 	e1e_wphy(hw, 0x1F55, 0x002A);
       
  2061 	/* Fixed FFE for long cable lengths */
       
  2062 	e1e_wphy(hw, 0x1F56, 0x002A);
       
  2063 	/* Enable Adaptive Clip Threshold */
       
  2064 	e1e_wphy(hw, 0x1F72, 0x3FB0);
       
  2065 	/* AHT reset limit to 1 */
       
  2066 	e1e_wphy(hw, 0x1F76, 0xC0FF);
       
  2067 	/* Set AHT master delay to 127 msec */
       
  2068 	e1e_wphy(hw, 0x1F77, 0x1DEC);
       
  2069 	/* Set scan bits for AHT */
       
  2070 	e1e_wphy(hw, 0x1F78, 0xF9EF);
       
  2071 	/* Set AHT Preset bits */
       
  2072 	e1e_wphy(hw, 0x1F79, 0x0210);
       
  2073 	/* Change integ_factor of channel A to 3 */
       
  2074 	e1e_wphy(hw, 0x1895, 0x0003);
       
  2075 	/* Change prop_factor of channels BCD to 8 */
       
  2076 	e1e_wphy(hw, 0x1796, 0x0008);
       
  2077 	/* Change cg_icount + enable integbp for channels BCD */
       
  2078 	e1e_wphy(hw, 0x1798, 0xD008);
       
  2079 	/*
       
  2080 	 * Change cg_icount + enable integbp + change prop_factor_master
       
  2081 	 * to 8 for channel A
       
  2082 	 */
       
  2083 	e1e_wphy(hw, 0x1898, 0xD918);
       
  2084 	/* Disable AHT in Slave mode on channel A */
       
  2085 	e1e_wphy(hw, 0x187A, 0x0800);
       
  2086 	/*
       
  2087 	 * Enable LPLU and disable AN to 1000 in non-D0a states,
       
  2088 	 * Enable SPD+B2B
       
  2089 	 */
       
  2090 	e1e_wphy(hw, 0x0019, 0x008D);
       
  2091 	/* Enable restart AN on an1000_dis change */
       
  2092 	e1e_wphy(hw, 0x001B, 0x2080);
       
  2093 	/* Enable wh_fifo read clock in 10/100 modes */
       
  2094 	e1e_wphy(hw, 0x0014, 0x0045);
       
  2095 	/* Restart AN, Speed selection is 1000 */
       
  2096 	e1e_wphy(hw, 0x0000, 0x1340);
       
  2097 
       
  2098 	return 0;
       
  2099 }
       
  2100 
       
  2101 /* Internal function pointers */
       
  2102 
       
  2103 /**
       
  2104  *  e1000_get_phy_cfg_done - Generic PHY configuration done
       
  2105  *  @hw: pointer to the HW structure
       
  2106  *
       
  2107  *  Return success if silicon family did not implement a family specific
       
  2108  *  get_cfg_done function.
       
  2109  **/
       
  2110 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
       
  2111 {
       
  2112 	if (hw->phy.ops.get_cfg_done)
       
  2113 		return hw->phy.ops.get_cfg_done(hw);
       
  2114 
       
  2115 	return 0;
       
  2116 }
       
  2117 
       
  2118 /**
       
  2119  *  e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
       
  2120  *  @hw: pointer to the HW structure
       
  2121  *
       
  2122  *  When the silicon family has not implemented a forced speed/duplex
       
  2123  *  function for the PHY, simply return 0.
       
  2124  **/
       
  2125 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
       
  2126 {
       
  2127 	if (hw->phy.ops.force_speed_duplex)
       
  2128 		return hw->phy.ops.force_speed_duplex(hw);
       
  2129 
       
  2130 	return 0;
       
  2131 }
       
  2132 
       
  2133 /**
       
  2134  *  e1000e_get_phy_type_from_id - Get PHY type from id
       
  2135  *  @phy_id: phy_id read from the phy
       
  2136  *
       
  2137  *  Returns the phy type from the id.
       
  2138  **/
       
  2139 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
       
  2140 {
       
  2141 	enum e1000_phy_type phy_type = e1000_phy_unknown;
       
  2142 
       
  2143 	switch (phy_id) {
       
  2144 	case M88E1000_I_PHY_ID:
       
  2145 	case M88E1000_E_PHY_ID:
       
  2146 	case M88E1111_I_PHY_ID:
       
  2147 	case M88E1011_I_PHY_ID:
       
  2148 		phy_type = e1000_phy_m88;
       
  2149 		break;
       
  2150 	case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
       
  2151 		phy_type = e1000_phy_igp_2;
       
  2152 		break;
       
  2153 	case GG82563_E_PHY_ID:
       
  2154 		phy_type = e1000_phy_gg82563;
       
  2155 		break;
       
  2156 	case IGP03E1000_E_PHY_ID:
       
  2157 		phy_type = e1000_phy_igp_3;
       
  2158 		break;
       
  2159 	case IFE_E_PHY_ID:
       
  2160 	case IFE_PLUS_E_PHY_ID:
       
  2161 	case IFE_C_E_PHY_ID:
       
  2162 		phy_type = e1000_phy_ife;
       
  2163 		break;
       
  2164 	case BME1000_E_PHY_ID:
       
  2165 	case BME1000_E_PHY_ID_R2:
       
  2166 		phy_type = e1000_phy_bm;
       
  2167 		break;
       
  2168 	case I82578_E_PHY_ID:
       
  2169 		phy_type = e1000_phy_82578;
       
  2170 		break;
       
  2171 	case I82577_E_PHY_ID:
       
  2172 		phy_type = e1000_phy_82577;
       
  2173 		break;
       
  2174 	default:
       
  2175 		phy_type = e1000_phy_unknown;
       
  2176 		break;
       
  2177 	}
       
  2178 	return phy_type;
       
  2179 }
       
  2180 
       
  2181 /**
       
  2182  *  e1000e_determine_phy_address - Determines PHY address.
       
  2183  *  @hw: pointer to the HW structure
       
  2184  *
       
  2185  *  This uses a trial and error method to loop through possible PHY
       
  2186  *  addresses. It tests each by reading the PHY ID registers and
       
  2187  *  checking for a match.
       
  2188  **/
       
  2189 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
       
  2190 {
       
  2191 	s32 ret_val = -E1000_ERR_PHY_TYPE;
       
  2192 	u32 phy_addr= 0;
       
  2193 	u32 i = 0;
       
  2194 	enum e1000_phy_type phy_type = e1000_phy_unknown;
       
  2195 
       
  2196 	do {
       
  2197 		for (phy_addr = 0; phy_addr < 4; phy_addr++) {
       
  2198 			hw->phy.addr = phy_addr;
       
  2199 			e1000e_get_phy_id(hw);
       
  2200 			phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
       
  2201 
       
  2202 			/* 
       
  2203 			 * If phy_type is valid, break - we found our
       
  2204 			 * PHY address
       
  2205 			 */
       
  2206 			if (phy_type  != e1000_phy_unknown) {
       
  2207 				ret_val = 0;
       
  2208 				break;
       
  2209 			}
       
  2210 		}
       
  2211 		i++;
       
  2212 	} while ((ret_val != 0) && (i < 100));
       
  2213 
       
  2214 	return ret_val;
       
  2215 }
       
  2216 
       
  2217 /**
       
  2218  *  e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
       
  2219  *  @page: page to access
       
  2220  *
       
  2221  *  Returns the phy address for the page requested.
       
  2222  **/
       
  2223 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
       
  2224 {
       
  2225 	u32 phy_addr = 2;
       
  2226 
       
  2227 	if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
       
  2228 		phy_addr = 1;
       
  2229 
       
  2230 	return phy_addr;
       
  2231 }
       
  2232 
       
  2233 /**
       
  2234  *  e1000e_write_phy_reg_bm - Write BM PHY register
       
  2235  *  @hw: pointer to the HW structure
       
  2236  *  @offset: register offset to write to
       
  2237  *  @data: data to write at register offset
       
  2238  *
       
  2239  *  Acquires semaphore, if necessary, then writes the data to PHY register
       
  2240  *  at the offset.  Release any acquired semaphores before exiting.
       
  2241  **/
       
  2242 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
       
  2243 {
       
  2244 	s32 ret_val;
       
  2245 	u32 page_select = 0;
       
  2246 	u32 page = offset >> IGP_PAGE_SHIFT;
       
  2247 	u32 page_shift = 0;
       
  2248 
       
  2249 	ret_val = hw->phy.ops.acquire_phy(hw);
       
  2250 	if (ret_val)
       
  2251 		return ret_val;
       
  2252 
       
  2253 	/* Page 800 works differently than the rest so it has its own func */
       
  2254 	if (page == BM_WUC_PAGE) {
       
  2255 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
       
  2256 							 false);
       
  2257 		goto out;
       
  2258 	}
       
  2259 
       
  2260 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
       
  2261 
       
  2262 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
  2263 		/*
       
  2264 		 * Page select is register 31 for phy address 1 and 22 for
       
  2265 		 * phy address 2 and 3. Page select is shifted only for
       
  2266 		 * phy address 1.
       
  2267 		 */
       
  2268 		if (hw->phy.addr == 1) {
       
  2269 			page_shift = IGP_PAGE_SHIFT;
       
  2270 			page_select = IGP01E1000_PHY_PAGE_SELECT;
       
  2271 		} else {
       
  2272 			page_shift = 0;
       
  2273 			page_select = BM_PHY_PAGE_SELECT;
       
  2274 		}
       
  2275 
       
  2276 		/* Page is shifted left, PHY expects (page x 32) */
       
  2277 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
       
  2278 		                                    (page << page_shift));
       
  2279 		if (ret_val)
       
  2280 			goto out;
       
  2281 	}
       
  2282 
       
  2283 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
  2284 	                                    data);
       
  2285 
       
  2286 out:
       
  2287 	hw->phy.ops.release_phy(hw);
       
  2288 	return ret_val;
       
  2289 }
       
  2290 
       
  2291 /**
       
  2292  *  e1000e_read_phy_reg_bm - Read BM PHY register
       
  2293  *  @hw: pointer to the HW structure
       
  2294  *  @offset: register offset to be read
       
  2295  *  @data: pointer to the read data
       
  2296  *
       
  2297  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
  2298  *  and storing the retrieved information in data.  Release any acquired
       
  2299  *  semaphores before exiting.
       
  2300  **/
       
  2301 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
       
  2302 {
       
  2303 	s32 ret_val;
       
  2304 	u32 page_select = 0;
       
  2305 	u32 page = offset >> IGP_PAGE_SHIFT;
       
  2306 	u32 page_shift = 0;
       
  2307 
       
  2308 	ret_val = hw->phy.ops.acquire_phy(hw);
       
  2309 	if (ret_val)
       
  2310 		return ret_val;
       
  2311 
       
  2312 	/* Page 800 works differently than the rest so it has its own func */
       
  2313 	if (page == BM_WUC_PAGE) {
       
  2314 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
       
  2315 							 true);
       
  2316 		goto out;
       
  2317 	}
       
  2318 
       
  2319 	hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
       
  2320 
       
  2321 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
  2322 		/*
       
  2323 		 * Page select is register 31 for phy address 1 and 22 for
       
  2324 		 * phy address 2 and 3. Page select is shifted only for
       
  2325 		 * phy address 1.
       
  2326 		 */
       
  2327 		if (hw->phy.addr == 1) {
       
  2328 			page_shift = IGP_PAGE_SHIFT;
       
  2329 			page_select = IGP01E1000_PHY_PAGE_SELECT;
       
  2330 		} else {
       
  2331 			page_shift = 0;
       
  2332 			page_select = BM_PHY_PAGE_SELECT;
       
  2333 		}
       
  2334 
       
  2335 		/* Page is shifted left, PHY expects (page x 32) */
       
  2336 		ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
       
  2337 		                                    (page << page_shift));
       
  2338 		if (ret_val)
       
  2339 			goto out;
       
  2340 	}
       
  2341 
       
  2342 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
  2343 	                                   data);
       
  2344 out:
       
  2345 	hw->phy.ops.release_phy(hw);
       
  2346 	return ret_val;
       
  2347 }
       
  2348 
       
  2349 /**
       
  2350  *  e1000e_read_phy_reg_bm2 - Read BM PHY register
       
  2351  *  @hw: pointer to the HW structure
       
  2352  *  @offset: register offset to be read
       
  2353  *  @data: pointer to the read data
       
  2354  *
       
  2355  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
  2356  *  and storing the retrieved information in data.  Release any acquired
       
  2357  *  semaphores before exiting.
       
  2358  **/
       
  2359 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
       
  2360 {
       
  2361 	s32 ret_val;
       
  2362 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
       
  2363 
       
  2364 	ret_val = hw->phy.ops.acquire_phy(hw);
       
  2365 	if (ret_val)
       
  2366 		return ret_val;
       
  2367 
       
  2368 	/* Page 800 works differently than the rest so it has its own func */
       
  2369 	if (page == BM_WUC_PAGE) {
       
  2370 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
       
  2371 							 true);
       
  2372 		goto out;
       
  2373 	}
       
  2374 
       
  2375 	hw->phy.addr = 1;
       
  2376 
       
  2377 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
  2378 
       
  2379 		/* Page is shifted left, PHY expects (page x 32) */
       
  2380 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
       
  2381 						    page);
       
  2382 
       
  2383 		if (ret_val)
       
  2384 			goto out;
       
  2385 	}
       
  2386 
       
  2387 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
  2388 					   data);
       
  2389 out:
       
  2390 	hw->phy.ops.release_phy(hw);
       
  2391 	return ret_val;
       
  2392 }
       
  2393 
       
  2394 /**
       
  2395  *  e1000e_write_phy_reg_bm2 - Write BM PHY register
       
  2396  *  @hw: pointer to the HW structure
       
  2397  *  @offset: register offset to write to
       
  2398  *  @data: data to write at register offset
       
  2399  *
       
  2400  *  Acquires semaphore, if necessary, then writes the data to PHY register
       
  2401  *  at the offset.  Release any acquired semaphores before exiting.
       
  2402  **/
       
  2403 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
       
  2404 {
       
  2405 	s32 ret_val;
       
  2406 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
       
  2407 
       
  2408 	ret_val = hw->phy.ops.acquire_phy(hw);
       
  2409 	if (ret_val)
       
  2410 		return ret_val;
       
  2411 
       
  2412 	/* Page 800 works differently than the rest so it has its own func */
       
  2413 	if (page == BM_WUC_PAGE) {
       
  2414 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
       
  2415 							 false);
       
  2416 		goto out;
       
  2417 	}
       
  2418 
       
  2419 	hw->phy.addr = 1;
       
  2420 
       
  2421 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
       
  2422 		/* Page is shifted left, PHY expects (page x 32) */
       
  2423 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
       
  2424 						    page);
       
  2425 
       
  2426 		if (ret_val)
       
  2427 			goto out;
       
  2428 	}
       
  2429 
       
  2430 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
       
  2431 					    data);
       
  2432 
       
  2433 out:
       
  2434 	hw->phy.ops.release_phy(hw);
       
  2435 	return ret_val;
       
  2436 }
       
  2437 
       
  2438 /**
       
  2439  *  e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
       
  2440  *  @hw: pointer to the HW structure
       
  2441  *  @offset: register offset to be read or written
       
  2442  *  @data: pointer to the data to read or write
       
  2443  *  @read: determines if operation is read or write
       
  2444  *
       
  2445  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
  2446  *  and storing the retrieved information in data.  Release any acquired
       
  2447  *  semaphores before exiting. Note that procedure to read the wakeup
       
  2448  *  registers are different. It works as such:
       
  2449  *  1) Set page 769, register 17, bit 2 = 1
       
  2450  *  2) Set page to 800 for host (801 if we were manageability)
       
  2451  *  3) Write the address using the address opcode (0x11)
       
  2452  *  4) Read or write the data using the data opcode (0x12)
       
  2453  *  5) Restore 769_17.2 to its original value
       
  2454  *
       
  2455  *  Assumes semaphore already acquired.
       
  2456  **/
       
  2457 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
       
  2458 					  u16 *data, bool read)
       
  2459 {
       
  2460 	s32 ret_val;
       
  2461 	u16 reg = BM_PHY_REG_NUM(offset);
       
  2462 	u16 phy_reg = 0;
       
  2463 
       
  2464 	/* Gig must be disabled for MDIO accesses to page 800 */
       
  2465 	if ((hw->mac.type == e1000_pchlan) &&
       
  2466 	   (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
       
  2467 		hw_dbg(hw, "Attempting to access page 800 while gig enabled\n");
       
  2468 
       
  2469 	/* All operations in this function are phy address 1 */
       
  2470 	hw->phy.addr = 1;
       
  2471 
       
  2472 	/* Set page 769 */
       
  2473 	e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
       
  2474 	                          (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
       
  2475 
       
  2476 	ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
       
  2477 	if (ret_val)
       
  2478 		goto out;
       
  2479 
       
  2480 	/* First clear bit 4 to avoid a power state change */
       
  2481 	phy_reg &= ~(BM_WUC_HOST_WU_BIT);
       
  2482 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
       
  2483 	if (ret_val)
       
  2484 		goto out;
       
  2485 
       
  2486 	/* Write bit 2 = 1, and clear bit 4 to 769_17 */
       
  2487 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
       
  2488 	                                    phy_reg | BM_WUC_ENABLE_BIT);
       
  2489 	if (ret_val)
       
  2490 		goto out;
       
  2491 
       
  2492 	/* Select page 800 */
       
  2493 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
       
  2494 	                                    (BM_WUC_PAGE << IGP_PAGE_SHIFT));
       
  2495 
       
  2496 	/* Write the page 800 offset value using opcode 0x11 */
       
  2497 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
       
  2498 	if (ret_val)
       
  2499 		goto out;
       
  2500 
       
  2501 	if (read) {
       
  2502 	        /* Read the page 800 value using opcode 0x12 */
       
  2503 		ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
       
  2504 		                                   data);
       
  2505 	} else {
       
  2506 	        /* Read the page 800 value using opcode 0x12 */
       
  2507 		ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
       
  2508 						    *data);
       
  2509 	}
       
  2510 
       
  2511 	if (ret_val)
       
  2512 		goto out;
       
  2513 
       
  2514 	/*
       
  2515 	 * Restore 769_17.2 to its original value
       
  2516 	 * Set page 769
       
  2517 	 */
       
  2518 	e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
       
  2519 	                          (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
       
  2520 
       
  2521 	/* Clear 769_17.2 */
       
  2522 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
       
  2523 
       
  2524 out:
       
  2525 	return ret_val;
       
  2526 }
       
  2527 
       
  2528 /**
       
  2529  *  e1000e_commit_phy - Soft PHY reset
       
  2530  *  @hw: pointer to the HW structure
       
  2531  *
       
  2532  *  Performs a soft PHY reset on those that apply. This is a function pointer
       
  2533  *  entry point called by drivers.
       
  2534  **/
       
  2535 s32 e1000e_commit_phy(struct e1000_hw *hw)
       
  2536 {
       
  2537 	if (hw->phy.ops.commit_phy)
       
  2538 		return hw->phy.ops.commit_phy(hw);
       
  2539 
       
  2540 	return 0;
       
  2541 }
       
  2542 
       
  2543 /**
       
  2544  *  e1000_set_d0_lplu_state - Sets low power link up state for D0
       
  2545  *  @hw: pointer to the HW structure
       
  2546  *  @active: boolean used to enable/disable lplu
       
  2547  *
       
  2548  *  Success returns 0, Failure returns 1
       
  2549  *
       
  2550  *  The low power link up (lplu) state is set to the power management level D0
       
  2551  *  and SmartSpeed is disabled when active is true, else clear lplu for D0
       
  2552  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
       
  2553  *  is used during Dx states where the power conservation is most important.
       
  2554  *  During driver activity, SmartSpeed should be enabled so performance is
       
  2555  *  maintained.  This is a function pointer entry point called by drivers.
       
  2556  **/
       
  2557 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
       
  2558 {
       
  2559 	if (hw->phy.ops.set_d0_lplu_state)
       
  2560 		return hw->phy.ops.set_d0_lplu_state(hw, active);
       
  2561 
       
  2562 	return 0;
       
  2563 }
       
  2564 
       
  2565 /**
       
  2566  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
       
  2567  *  @hw:   pointer to the HW structure
       
  2568  *  @slow: true for slow mode, false for normal mode
       
  2569  *
       
  2570  *  Assumes semaphore already acquired.
       
  2571  **/
       
  2572 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
       
  2573 {
       
  2574 	s32 ret_val = 0;
       
  2575 	u16 data = 0;
       
  2576 
       
  2577 	/* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
       
  2578 	hw->phy.addr = 1;
       
  2579 	ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
       
  2580 				         (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
       
  2581 	if (ret_val)
       
  2582 		goto out;
       
  2583 
       
  2584 	ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
       
  2585 	                                   (0x2180 | (slow << 10)));
       
  2586 	if (ret_val)
       
  2587 		goto out;
       
  2588 
       
  2589 	/* dummy read when reverting to fast mode - throw away result */
       
  2590 	if (!slow)
       
  2591 		ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
       
  2592 
       
  2593 out:
       
  2594 	return ret_val;
       
  2595 }
       
  2596 
       
  2597 /**
       
  2598  *  __e1000_read_phy_reg_hv -  Read HV PHY register
       
  2599  *  @hw: pointer to the HW structure
       
  2600  *  @offset: register offset to be read
       
  2601  *  @data: pointer to the read data
       
  2602  *  @locked: semaphore has already been acquired or not
       
  2603  *
       
  2604  *  Acquires semaphore, if necessary, then reads the PHY register at offset
       
  2605  *  and stores the retrieved information in data.  Release any acquired
       
  2606  *  semaphore before exiting.
       
  2607  **/
       
  2608 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
       
  2609                                    bool locked)
       
  2610 {
       
  2611 	s32 ret_val;
       
  2612 	u16 page = BM_PHY_REG_PAGE(offset);
       
  2613 	u16 reg = BM_PHY_REG_NUM(offset);
       
  2614 	bool in_slow_mode = false;
       
  2615 
       
  2616 	if (!locked) {
       
  2617 		ret_val = hw->phy.ops.acquire_phy(hw);
       
  2618 		if (ret_val)
       
  2619 			return ret_val;
       
  2620 	}
       
  2621 
       
  2622 	/* Workaround failure in MDIO access while cable is disconnected */
       
  2623 	if ((hw->phy.type == e1000_phy_82577) &&
       
  2624 	    !(er32(STATUS) & E1000_STATUS_LU)) {
       
  2625 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
       
  2626 		if (ret_val)
       
  2627 			goto out;
       
  2628 
       
  2629 		in_slow_mode = true;
       
  2630 	}
       
  2631 
       
  2632 	/* Page 800 works differently than the rest so it has its own func */
       
  2633 	if (page == BM_WUC_PAGE) {
       
  2634 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
       
  2635 		                                         data, true);
       
  2636 		goto out;
       
  2637 	}
       
  2638 
       
  2639 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
       
  2640 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
       
  2641 		                                         data, true);
       
  2642 		goto out;
       
  2643 	}
       
  2644 
       
  2645 	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
       
  2646 
       
  2647 	if (page == HV_INTC_FC_PAGE_START)
       
  2648 		page = 0;
       
  2649 
       
  2650 	if (reg > MAX_PHY_MULTI_PAGE_REG) {
       
  2651 		u32 phy_addr = hw->phy.addr;
       
  2652 
       
  2653 		hw->phy.addr = 1;
       
  2654 
       
  2655 		/* Page is shifted left, PHY expects (page x 32) */
       
  2656 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
  2657 					     IGP01E1000_PHY_PAGE_SELECT,
       
  2658 					     (page << IGP_PAGE_SHIFT));
       
  2659 		hw->phy.addr = phy_addr;
       
  2660 
       
  2661 		if (ret_val)
       
  2662 			goto out;
       
  2663 	}
       
  2664 
       
  2665 	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
       
  2666 	                                  data);
       
  2667 out:
       
  2668 	/* Revert to MDIO fast mode, if applicable */
       
  2669 	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
       
  2670 		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
       
  2671 
       
  2672 	if (!locked)
       
  2673 		hw->phy.ops.release_phy(hw);
       
  2674 
       
  2675 	return ret_val;
       
  2676 }
       
  2677 
       
  2678 /**
       
  2679  *  e1000_read_phy_reg_hv -  Read HV PHY register
       
  2680  *  @hw: pointer to the HW structure
       
  2681  *  @offset: register offset to be read
       
  2682  *  @data: pointer to the read data
       
  2683  *
       
  2684  *  Acquires semaphore then reads the PHY register at offset and stores
       
  2685  *  the retrieved information in data.  Release the acquired semaphore
       
  2686  *  before exiting.
       
  2687  **/
       
  2688 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
       
  2689 {
       
  2690 	return __e1000_read_phy_reg_hv(hw, offset, data, false);
       
  2691 }
       
  2692 
       
  2693 /**
       
  2694  *  e1000_read_phy_reg_hv_locked -  Read HV PHY register
       
  2695  *  @hw: pointer to the HW structure
       
  2696  *  @offset: register offset to be read
       
  2697  *  @data: pointer to the read data
       
  2698  *
       
  2699  *  Reads the PHY register at offset and stores the retrieved information
       
  2700  *  in data.  Assumes semaphore already acquired.
       
  2701  **/
       
  2702 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
       
  2703 {
       
  2704 	return __e1000_read_phy_reg_hv(hw, offset, data, true);
       
  2705 }
       
  2706 
       
  2707 /**
       
  2708  *  __e1000_write_phy_reg_hv - Write HV PHY register
       
  2709  *  @hw: pointer to the HW structure
       
  2710  *  @offset: register offset to write to
       
  2711  *  @data: data to write at register offset
       
  2712  *  @locked: semaphore has already been acquired or not
       
  2713  *
       
  2714  *  Acquires semaphore, if necessary, then writes the data to PHY register
       
  2715  *  at the offset.  Release any acquired semaphores before exiting.
       
  2716  **/
       
  2717 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
       
  2718                                     bool locked)
       
  2719 {
       
  2720 	s32 ret_val;
       
  2721 	u16 page = BM_PHY_REG_PAGE(offset);
       
  2722 	u16 reg = BM_PHY_REG_NUM(offset);
       
  2723 	bool in_slow_mode = false;
       
  2724 
       
  2725 	if (!locked) {
       
  2726 		ret_val = hw->phy.ops.acquire_phy(hw);
       
  2727 		if (ret_val)
       
  2728 			return ret_val;
       
  2729 	}
       
  2730 
       
  2731 	/* Workaround failure in MDIO access while cable is disconnected */
       
  2732 	if ((hw->phy.type == e1000_phy_82577) &&
       
  2733 	    !(er32(STATUS) & E1000_STATUS_LU)) {
       
  2734 		ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
       
  2735 		if (ret_val)
       
  2736 			goto out;
       
  2737 
       
  2738 		in_slow_mode = true;
       
  2739 	}
       
  2740 
       
  2741 	/* Page 800 works differently than the rest so it has its own func */
       
  2742 	if (page == BM_WUC_PAGE) {
       
  2743 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
       
  2744 		                                         &data, false);
       
  2745 		goto out;
       
  2746 	}
       
  2747 
       
  2748 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
       
  2749 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
       
  2750 		                                         &data, false);
       
  2751 		goto out;
       
  2752 	}
       
  2753 
       
  2754 	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
       
  2755 
       
  2756 	if (page == HV_INTC_FC_PAGE_START)
       
  2757 		page = 0;
       
  2758 
       
  2759 	/*
       
  2760 	 * Workaround MDIO accesses being disabled after entering IEEE Power
       
  2761 	 * Down (whenever bit 11 of the PHY Control register is set)
       
  2762 	 */
       
  2763 	if ((hw->phy.type == e1000_phy_82578) &&
       
  2764 	    (hw->phy.revision >= 1) &&
       
  2765 	    (hw->phy.addr == 2) &&
       
  2766 	    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
       
  2767 	    (data & (1 << 11))) {
       
  2768 		u16 data2 = 0x7EFF;
       
  2769 		ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
       
  2770 		                                         &data2, false);
       
  2771 		if (ret_val)
       
  2772 			goto out;
       
  2773 	}
       
  2774 
       
  2775 	if (reg > MAX_PHY_MULTI_PAGE_REG) {
       
  2776 		u32 phy_addr = hw->phy.addr;
       
  2777 
       
  2778 		hw->phy.addr = 1;
       
  2779 
       
  2780 		/* Page is shifted left, PHY expects (page x 32) */
       
  2781 		ret_val = e1000e_write_phy_reg_mdic(hw,
       
  2782 					     IGP01E1000_PHY_PAGE_SELECT,
       
  2783 					     (page << IGP_PAGE_SHIFT));
       
  2784 		hw->phy.addr = phy_addr;
       
  2785 
       
  2786 		if (ret_val)
       
  2787 			goto out;
       
  2788 	}
       
  2789 
       
  2790 	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
       
  2791 	                                  data);
       
  2792 
       
  2793 out:
       
  2794 	/* Revert to MDIO fast mode, if applicable */
       
  2795 	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
       
  2796 		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
       
  2797 
       
  2798 	if (!locked)
       
  2799 		hw->phy.ops.release_phy(hw);
       
  2800 
       
  2801 	return ret_val;
       
  2802 }
       
  2803 
       
  2804 /**
       
  2805  *  e1000_write_phy_reg_hv - Write HV PHY register
       
  2806  *  @hw: pointer to the HW structure
       
  2807  *  @offset: register offset to write to
       
  2808  *  @data: data to write at register offset
       
  2809  *
       
  2810  *  Acquires semaphore then writes the data to PHY register at the offset.
       
  2811  *  Release the acquired semaphores before exiting.
       
  2812  **/
       
  2813 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
       
  2814 {
       
  2815 	return __e1000_write_phy_reg_hv(hw, offset, data, false);
       
  2816 }
       
  2817 
       
  2818 /**
       
  2819  *  e1000_write_phy_reg_hv_locked - Write HV PHY register
       
  2820  *  @hw: pointer to the HW structure
       
  2821  *  @offset: register offset to write to
       
  2822  *  @data: data to write at register offset
       
  2823  *
       
  2824  *  Writes the data to PHY register at the offset.  Assumes semaphore
       
  2825  *  already acquired.
       
  2826  **/
       
  2827 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
       
  2828 {
       
  2829 	return __e1000_write_phy_reg_hv(hw, offset, data, true);
       
  2830 }
       
  2831 
       
  2832 /**
       
  2833  *  e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
       
  2834  *  @page: page to be accessed
       
  2835  **/
       
  2836 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
       
  2837 {
       
  2838 	u32 phy_addr = 2;
       
  2839 
       
  2840 	if (page >= HV_INTC_FC_PAGE_START)
       
  2841 		phy_addr = 1;
       
  2842 
       
  2843 	return phy_addr;
       
  2844 }
       
  2845 
       
  2846 /**
       
  2847  *  e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
       
  2848  *  @hw: pointer to the HW structure
       
  2849  *  @offset: register offset to be read or written
       
  2850  *  @data: pointer to the data to be read or written
       
  2851  *  @read: determines if operation is read or written
       
  2852  *
       
  2853  *  Reads the PHY register at offset and stores the retreived information
       
  2854  *  in data.  Assumes semaphore already acquired.  Note that the procedure
       
  2855  *  to read these regs uses the address port and data port to read/write.
       
  2856  **/
       
  2857 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
       
  2858                                           u16 *data, bool read)
       
  2859 {
       
  2860 	s32 ret_val;
       
  2861 	u32 addr_reg = 0;
       
  2862 	u32 data_reg = 0;
       
  2863 
       
  2864 	/* This takes care of the difference with desktop vs mobile phy */
       
  2865 	addr_reg = (hw->phy.type == e1000_phy_82578) ?
       
  2866 	           I82578_ADDR_REG : I82577_ADDR_REG;
       
  2867 	data_reg = addr_reg + 1;
       
  2868 
       
  2869 	/* All operations in this function are phy address 2 */
       
  2870 	hw->phy.addr = 2;
       
  2871 
       
  2872 	/* masking with 0x3F to remove the page from offset */
       
  2873 	ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
       
  2874 	if (ret_val) {
       
  2875 		hw_dbg(hw, "Could not write PHY the HV address register\n");
       
  2876 		goto out;
       
  2877 	}
       
  2878 
       
  2879 	/* Read or write the data value next */
       
  2880 	if (read)
       
  2881 		ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
       
  2882 	else
       
  2883 		ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
       
  2884 
       
  2885 	if (ret_val) {
       
  2886 		hw_dbg(hw, "Could not read data value from HV data register\n");
       
  2887 		goto out;
       
  2888 	}
       
  2889 
       
  2890 out:
       
  2891 	return ret_val;
       
  2892 }
       
  2893 
       
  2894 /**
       
  2895  *  e1000_link_stall_workaround_hv - Si workaround
       
  2896  *  @hw: pointer to the HW structure
       
  2897  *
       
  2898  *  This function works around a Si bug where the link partner can get
       
  2899  *  a link up indication before the PHY does.  If small packets are sent
       
  2900  *  by the link partner they can be placed in the packet buffer without
       
  2901  *  being properly accounted for by the PHY and will stall preventing
       
  2902  *  further packets from being received.  The workaround is to clear the
       
  2903  *  packet buffer after the PHY detects link up.
       
  2904  **/
       
  2905 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
       
  2906 {
       
  2907 	s32 ret_val = 0;
       
  2908 	u16 data;
       
  2909 
       
  2910 	if (hw->phy.type != e1000_phy_82578)
       
  2911 		goto out;
       
  2912 
       
  2913 	/* Do not apply workaround if in PHY loopback bit 14 set */
       
  2914 	hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &data);
       
  2915 	if (data & PHY_CONTROL_LB)
       
  2916 		goto out;
       
  2917 
       
  2918 	/* check if link is up and at 1Gbps */
       
  2919 	ret_val = hw->phy.ops.read_phy_reg(hw, BM_CS_STATUS, &data);
       
  2920 	if (ret_val)
       
  2921 		goto out;
       
  2922 
       
  2923 	data &= BM_CS_STATUS_LINK_UP |
       
  2924 	        BM_CS_STATUS_RESOLVED |
       
  2925 	        BM_CS_STATUS_SPEED_MASK;
       
  2926 
       
  2927 	if (data != (BM_CS_STATUS_LINK_UP |
       
  2928 	             BM_CS_STATUS_RESOLVED |
       
  2929 	             BM_CS_STATUS_SPEED_1000))
       
  2930 		goto out;
       
  2931 
       
  2932 	mdelay(200);
       
  2933 
       
  2934 	/* flush the packets in the fifo buffer */
       
  2935 	ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
       
  2936 	                                HV_MUX_DATA_CTRL_GEN_TO_MAC |
       
  2937 	                                HV_MUX_DATA_CTRL_FORCE_SPEED);
       
  2938 	if (ret_val)
       
  2939 		goto out;
       
  2940 
       
  2941 	ret_val = hw->phy.ops.write_phy_reg(hw, HV_MUX_DATA_CTRL,
       
  2942 	                                HV_MUX_DATA_CTRL_GEN_TO_MAC);
       
  2943 
       
  2944 out:
       
  2945 	return ret_val;
       
  2946 }
       
  2947 
       
  2948 /**
       
  2949  *  e1000_check_polarity_82577 - Checks the polarity.
       
  2950  *  @hw: pointer to the HW structure
       
  2951  *
       
  2952  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
       
  2953  *
       
  2954  *  Polarity is determined based on the PHY specific status register.
       
  2955  **/
       
  2956 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
       
  2957 {
       
  2958 	struct e1000_phy_info *phy = &hw->phy;
       
  2959 	s32 ret_val;
       
  2960 	u16 data;
       
  2961 
       
  2962 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
       
  2963 
       
  2964 	if (!ret_val)
       
  2965 		phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
       
  2966 		                      ? e1000_rev_polarity_reversed
       
  2967 		                      : e1000_rev_polarity_normal;
       
  2968 
       
  2969 	return ret_val;
       
  2970 }
       
  2971 
       
  2972 /**
       
  2973  *  e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
       
  2974  *  @hw: pointer to the HW structure
       
  2975  *
       
  2976  *  Calls the PHY setup function to force speed and duplex.  Clears the
       
  2977  *  auto-crossover to force MDI manually.  Waits for link and returns
       
  2978  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
       
  2979  **/
       
  2980 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
       
  2981 {
       
  2982 	struct e1000_phy_info *phy = &hw->phy;
       
  2983 	s32 ret_val;
       
  2984 	u16 phy_data;
       
  2985 	bool link;
       
  2986 
       
  2987 	ret_val = phy->ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
       
  2988 	if (ret_val)
       
  2989 		goto out;
       
  2990 
       
  2991 	e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
       
  2992 
       
  2993 	ret_val = phy->ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
       
  2994 	if (ret_val)
       
  2995 		goto out;
       
  2996 
       
  2997 	/*
       
  2998 	 * Clear Auto-Crossover to force MDI manually.  82577 requires MDI
       
  2999 	 * forced whenever speed and duplex are forced.
       
  3000 	 */
       
  3001 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_CTRL_2, &phy_data);
       
  3002 	if (ret_val)
       
  3003 		goto out;
       
  3004 
       
  3005 	phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
       
  3006 	phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
       
  3007 
       
  3008 	ret_val = phy->ops.write_phy_reg(hw, I82577_PHY_CTRL_2, phy_data);
       
  3009 	if (ret_val)
       
  3010 		goto out;
       
  3011 
       
  3012 	hw_dbg(hw, "I82577_PHY_CTRL_2: %X\n", phy_data);
       
  3013 
       
  3014 	udelay(1);
       
  3015 
       
  3016 	if (phy->autoneg_wait_to_complete) {
       
  3017 		hw_dbg(hw, "Waiting for forced speed/duplex link on 82577 phy\n");
       
  3018 
       
  3019 		ret_val = e1000e_phy_has_link_generic(hw,
       
  3020 		                                     PHY_FORCE_LIMIT,
       
  3021 		                                     100000,
       
  3022 		                                     &link);
       
  3023 		if (ret_val)
       
  3024 			goto out;
       
  3025 
       
  3026 		if (!link)
       
  3027 			hw_dbg(hw, "Link taking longer than expected.\n");
       
  3028 
       
  3029 		/* Try once more */
       
  3030 		ret_val = e1000e_phy_has_link_generic(hw,
       
  3031 		                                     PHY_FORCE_LIMIT,
       
  3032 		                                     100000,
       
  3033 		                                     &link);
       
  3034 		if (ret_val)
       
  3035 			goto out;
       
  3036 	}
       
  3037 
       
  3038 out:
       
  3039 	return ret_val;
       
  3040 }
       
  3041 
       
  3042 /**
       
  3043  *  e1000_get_phy_info_82577 - Retrieve I82577 PHY information
       
  3044  *  @hw: pointer to the HW structure
       
  3045  *
       
  3046  *  Read PHY status to determine if link is up.  If link is up, then
       
  3047  *  set/determine 10base-T extended distance and polarity correction.  Read
       
  3048  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
       
  3049  *  determine on the cable length, local and remote receiver.
       
  3050  **/
       
  3051 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
       
  3052 {
       
  3053 	struct e1000_phy_info *phy = &hw->phy;
       
  3054 	s32 ret_val;
       
  3055 	u16 data;
       
  3056 	bool link;
       
  3057 
       
  3058 	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
       
  3059 	if (ret_val)
       
  3060 		goto out;
       
  3061 
       
  3062 	if (!link) {
       
  3063 		hw_dbg(hw, "Phy info is only valid if link is up\n");
       
  3064 		ret_val = -E1000_ERR_CONFIG;
       
  3065 		goto out;
       
  3066 	}
       
  3067 
       
  3068 	phy->polarity_correction = true;
       
  3069 
       
  3070 	ret_val = e1000_check_polarity_82577(hw);
       
  3071 	if (ret_val)
       
  3072 		goto out;
       
  3073 
       
  3074 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_STATUS_2, &data);
       
  3075 	if (ret_val)
       
  3076 		goto out;
       
  3077 
       
  3078 	phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
       
  3079 
       
  3080 	if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
       
  3081 	    I82577_PHY_STATUS2_SPEED_1000MBPS) {
       
  3082 		ret_val = hw->phy.ops.get_cable_length(hw);
       
  3083 		if (ret_val)
       
  3084 			goto out;
       
  3085 
       
  3086 		ret_val = phy->ops.read_phy_reg(hw, PHY_1000T_STATUS, &data);
       
  3087 		if (ret_val)
       
  3088 			goto out;
       
  3089 
       
  3090 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
       
  3091 		                ? e1000_1000t_rx_status_ok
       
  3092 		                : e1000_1000t_rx_status_not_ok;
       
  3093 
       
  3094 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
       
  3095 		                 ? e1000_1000t_rx_status_ok
       
  3096 		                 : e1000_1000t_rx_status_not_ok;
       
  3097 	} else {
       
  3098 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
       
  3099 		phy->local_rx = e1000_1000t_rx_status_undefined;
       
  3100 		phy->remote_rx = e1000_1000t_rx_status_undefined;
       
  3101 	}
       
  3102 
       
  3103 out:
       
  3104 	return ret_val;
       
  3105 }
       
  3106 
       
  3107 /**
       
  3108  *  e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
       
  3109  *  @hw: pointer to the HW structure
       
  3110  *
       
  3111  * Reads the diagnostic status register and verifies result is valid before
       
  3112  * placing it in the phy_cable_length field.
       
  3113  **/
       
  3114 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
       
  3115 {
       
  3116 	struct e1000_phy_info *phy = &hw->phy;
       
  3117 	s32 ret_val;
       
  3118 	u16 phy_data, length;
       
  3119 
       
  3120 	ret_val = phy->ops.read_phy_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
       
  3121 	if (ret_val)
       
  3122 		goto out;
       
  3123 
       
  3124 	length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
       
  3125 	         I82577_DSTATUS_CABLE_LENGTH_SHIFT;
       
  3126 
       
  3127 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
       
  3128 		ret_val = E1000_ERR_PHY;
       
  3129 
       
  3130 	phy->cable_length = length;
       
  3131 
       
  3132 out:
       
  3133 	return ret_val;
       
  3134 }