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1 /** |
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2 Network Driver for Beckhoff CCAT communication controller |
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3 Copyright (C) 2014 Beckhoff Automation GmbH |
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4 Author: Patrick Bruenn <p.bruenn@beckhoff.com> |
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5 |
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6 This program is free software; you can redistribute it and/or modify |
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7 it under the terms of the GNU General Public License as published by |
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8 the Free Software Foundation; either version 2 of the License, or |
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9 (at your option) any later version. |
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10 |
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11 This program is distributed in the hope that it will be useful, |
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 GNU General Public License for more details. |
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15 |
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16 You should have received a copy of the GNU General Public License along |
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17 with this program; if not, write to the Free Software Foundation, Inc., |
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18 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 */ |
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20 |
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21 #include <linux/kernel.h> |
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22 #include "CCatDefinitions.h" |
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23 #include "module.h" |
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24 #include "print.h" |
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25 |
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26 #define TESTING_ENABLED 1 |
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27 void print_mem(const unsigned char *p, size_t lines) |
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28 { |
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29 #if TESTING_ENABLED |
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30 pr_info("mem at: %p\n", p); |
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31 pr_info(" 0 1 2 3 4 5 6 7 8 9 A B C D E F\n"); |
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32 while (lines > 0) { |
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33 pr_info |
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34 ("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", |
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35 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8], p[9], |
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36 p[10], p[11], p[12], p[13], p[14], p[15]); |
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37 p += 16; |
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38 --lines; |
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39 } |
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40 #endif /* #if TESTING_ENABLED */ |
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41 } |
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42 |
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43 static const char *CCatFunctionTypes[CCATINFO_MAX + 1] = { |
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44 "not used", |
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45 "Informationblock", |
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46 "EtherCAT Slave", |
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47 "EtherCAT Master without DMA", |
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48 "Ethernet MAC without DMA", |
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49 "Ethernet Switch", |
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50 "Sercos III", |
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51 "Profibus", |
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52 "CAN Controller", |
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53 "KBUS Master", |
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54 "IP-Link Master (planned)", |
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55 "SPI Master", |
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56 "I²C", |
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57 "GPIO", |
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58 "Drive", |
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59 "CCAT Update", |
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60 "Systemtime", |
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61 "Interrupt Controller", |
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62 "EEPROM Controller", |
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63 "DMA Controller", |
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64 "EtherCAT Master with DMA", |
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65 "Ethernet MAC with DMA", |
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66 "SRAM Interface", |
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67 "Internal Copy block", |
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68 "unknown" |
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69 }; |
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70 |
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71 static void print_CCatDmaRxActBuf(const struct ccat_eth_priv *const priv) |
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72 { |
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73 CCatDmaRxActBuf rx_fifo; |
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74 memcpy_fromio(&rx_fifo, priv->reg.rx_fifo, sizeof(rx_fifo)); |
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75 pr_debug("Rx FIFO base address: %p\n", priv->reg.rx_fifo); |
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76 pr_debug(" Rx Frame Header start: 0x%08x\n", rx_fifo.startAddr); |
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77 pr_debug(" reserved: 0x%08x\n", rx_fifo.reserved1); |
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78 pr_debug(" Rx start address valid: %8u\n", rx_fifo.nextValid); |
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79 pr_debug(" reserved: 0x%08x\n", rx_fifo.reserved2); |
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80 pr_debug(" FIFO level: 0x%08x\n", rx_fifo.FifoLevel); |
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81 pr_debug(" Buffer level: 0x%08x\n", rx_fifo.bufferLevel); |
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82 pr_debug(" next address: 0x%08x\n", rx_fifo.nextAddr); |
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83 } |
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84 |
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85 static void print_CCatDmaTxFifo(const struct ccat_eth_priv *const priv) |
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86 { |
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87 CCatDmaTxFifo tx_fifo; |
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88 memcpy_fromio(&tx_fifo, priv->reg.tx_fifo, sizeof(tx_fifo)); |
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89 pr_debug("Tx FIFO base address: %p\n", priv->reg.tx_fifo); |
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90 pr_debug(" Tx Frame Header start: 0x%08x\n", tx_fifo.startAddr); |
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91 pr_debug(" # 64 bit words: %10d\n", tx_fifo.numQuadWords); |
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92 pr_debug(" reserved: 0x%08x\n", tx_fifo.reserved1); |
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93 pr_debug(" FIFO reset: 0x%08x\n", tx_fifo.fifoReset); |
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94 } |
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95 |
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96 static void print_CCatInfoBlock(const CCatInfoBlock * info, |
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97 const void __iomem * const base_addr) |
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98 { |
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99 const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX); |
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100 pr_debug("%s\n", CCatFunctionTypes[index]); |
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101 pr_debug(" revision: 0x%x\n", info->nRevision); |
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102 pr_debug(" RX channel: %d\n", info->rxDmaChn); |
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103 pr_debug(" TX channel: %d\n", info->txDmaChn); |
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104 pr_debug(" baseaddr: 0x%x\n", info->nAddr); |
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105 pr_debug(" size: 0x%x\n", info->nSize); |
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106 pr_debug(" subfunction: %p\n", base_addr); |
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107 } |
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108 |
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109 static void print_CCatMacRegs(const struct ccat_eth_priv *const priv) |
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110 { |
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111 CCatMacRegs mac; |
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112 memcpy_fromio(&mac, priv->reg.mac, sizeof(mac)); |
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113 pr_debug("MAC base address: %p\n", priv->reg.mac); |
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114 pr_debug(" frame length error count: %10d\n", mac.frameLenErrCnt); |
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115 pr_debug(" RX error count: %10d\n", mac.rxErrCnt); |
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116 pr_debug(" CRC error count: %10d\n", mac.crcErrCnt); |
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117 pr_debug(" Link lost error count: %10d\n", mac.linkLostErrCnt); |
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118 pr_debug(" reserved: 0x%08x\n", mac.reserved1); |
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119 pr_debug(" RX overflow count: %10d\n", |
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120 mac.dropFrameErrCnt); |
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121 pr_debug(" DMA overflow count: %10d\n", mac.reserved2[0]); |
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122 //pr_debug(" reserverd: %10d\n", DRV_NAME, mac.reserved2[1]); |
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123 pr_debug(" TX frame counter: %10d\n", mac.txFrameCnt); |
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124 pr_debug(" RX frame counter: %10d\n", mac.rxFrameCnt); |
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125 pr_debug(" TX-FIFO level: 0x%08x\n", mac.txFifoLevel); |
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126 pr_debug(" MII connection: 0x%08x\n", mac.miiConnected); |
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127 } |
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128 |
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129 static void print_CCatMii(const struct ccat_eth_priv *const priv) |
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130 { |
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131 CCatMii mii; |
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132 memcpy_fromio(&mii, priv->reg.mii, sizeof(mii)); |
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133 pr_debug("MII base address: %p\n", priv->reg.mii); |
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134 pr_debug(" MII cycle: %s\n", |
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135 mii.startMiCycle ? "running" : "no cycle"); |
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136 pr_debug(" reserved: 0x%x\n", mii.reserved1); |
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137 pr_debug(" cmd valid: %s\n", mii.cmdErr ? "no" : "yes"); |
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138 pr_debug(" cmd: 0x%x\n", mii.cmd); |
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139 pr_debug(" reserved: 0x%x\n", mii.reserved2); |
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140 pr_debug(" PHY addr: 0x%x\n", mii.phyAddr); |
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141 pr_debug(" reserved: 0x%x\n", mii.reserved3); |
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142 pr_debug(" PHY reg: 0x%x\n", mii.phyReg); |
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143 pr_debug(" reserved: 0x%x\n", mii.reserved4); |
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144 pr_debug(" PHY write: 0x%x\n", mii.phyWriteData); |
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145 pr_debug(" PHY read: 0x%x\n", mii.phyReadData); |
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146 pr_debug(" MAC addr: %02x:%02x:%02x:%02x:%02x:%02x\n", |
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147 mii.macAddr.b[0], mii.macAddr.b[1], mii.macAddr.b[2], |
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148 mii.macAddr.b[3], mii.macAddr.b[4], mii.macAddr.b[5]); |
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149 pr_debug(" MAC filter enable: %s\n", |
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150 mii.macFilterEnabled ? "enabled" : "disabled"); |
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151 pr_debug(" reserved: 0x%x\n", mii.reserved6); |
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152 pr_debug(" Link State: %s\n", |
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153 mii.linkStatus ? "link" : "no link"); |
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154 pr_debug(" reserved: 0x%x\n", mii.reserved7); |
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155 //pr_debug(" reserved: 0x%x\n", DRV_NAME, mii.reserved8); |
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156 //TODO add leds, systemtime insertion and interrupts |
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157 } |
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158 |
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159 void ccat_print_function_info(struct ccat_eth_priv *priv) |
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160 { |
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161 print_CCatInfoBlock(&priv->info, priv->ccatdev->bar[0].ioaddr); |
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162 print_CCatMii(priv); |
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163 print_CCatDmaTxFifo(priv); |
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164 print_CCatDmaRxActBuf(priv); |
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165 print_CCatMacRegs(priv); |
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166 pr_debug(" RX window: %p\n", priv->reg.rx_mem); |
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167 pr_debug(" TX memory: %p\n", priv->reg.tx_mem); |
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168 pr_debug(" misc: %p\n", priv->reg.misc); |
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169 } |
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170 |
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171 void print_update_info(const CCatInfoBlock * const info, |
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172 void __iomem * const ioaddr) |
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173 { |
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174 const size_t index = min((int)info->eCCatInfoType, CCATINFO_MAX); |
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175 pr_debug("%s\n", CCatFunctionTypes[index]); |
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176 pr_debug(" revision: 0x%x\n", info->nRevision); |
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177 pr_debug(" baseaddr: 0x%x\n", info->nAddr); |
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178 pr_debug(" size: 0x%x\n", info->nSize); |
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179 pr_debug(" PROM ID is: 0x%x\n", ccat_get_prom_id(ioaddr)); |
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180 } |