1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 

   111 /**

   112  * e1000_set_phy_type - Set the phy type member in the hw struct.

   113  * @hw: Struct containing variables accessed by shared code

   114  */

   115 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   116 {

   117 	e_dbg("e1000_set_phy_type");

   118 

   119 	if (hw->mac_type == e1000_undefined)

   120 		return -E1000_ERR_PHY_TYPE;

   121 

   122 	switch (hw->phy_id) {

   123 	case M88E1000_E_PHY_ID:

   124 	case M88E1000_I_PHY_ID:

   125 	case M88E1011_I_PHY_ID:

   126 	case M88E1111_I_PHY_ID:

   127 	case M88E1118_E_PHY_ID:

   128 		hw->phy_type = e1000_phy_m88;

   129 		break;

   130 	case IGP01E1000_I_PHY_ID:

   131 		if (hw->mac_type == e1000_82541 ||

   132 		    hw->mac_type == e1000_82541_rev_2 ||

   133 		    hw->mac_type == e1000_82547 ||

   134 		    hw->mac_type == e1000_82547_rev_2)

   135 			hw->phy_type = e1000_phy_igp;

   136 		break;

   137 	case RTL8211B_PHY_ID:

   138 		hw->phy_type = e1000_phy_8211;

   139 		break;

   140 	case RTL8201N_PHY_ID:

   141 		hw->phy_type = e1000_phy_8201;

   142 		break;

   143 	default:

   144 		/* Should never have loaded on this device */

   145 		hw->phy_type = e1000_phy_undefined;

   146 		return -E1000_ERR_PHY_TYPE;

   147 	}

   148 

   149 	return E1000_SUCCESS;

   150 }

   151 

   152 /**

   153  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   154  * @hw: Struct containing variables accessed by shared code

   155  */

   156 static void e1000_phy_init_script(struct e1000_hw *hw)

   157 {

   158 	u32 ret_val;

   159 	u16 phy_saved_data;

   160 

   161 	e_dbg("e1000_phy_init_script");

   162 

   163 	if (hw->phy_init_script) {

   164 		msleep(20);

   165 

   166 		/* Save off the current value of register 0x2F5B to be restored at

   167 		 * the end of this routine. */

   168 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   169 

   170 		/* Disabled the PHY transmitter */

   171 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   172 		msleep(20);

   173 

   174 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   175 		msleep(5);

   176 

   177 		switch (hw->mac_type) {

   178 		case e1000_82541:

   179 		case e1000_82547:

   180 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   181 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   182 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   183 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   184 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   185 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   186 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   187 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   188 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   189 			break;

   190 

   191 		case e1000_82541_rev_2:

   192 		case e1000_82547_rev_2:

   193 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   194 			break;

   195 		default:

   196 			break;

   197 		}

   198 

   199 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   200 		msleep(20);

   201 

   202 		/* Now enable the transmitter */

   203 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   204 

   205 		if (hw->mac_type == e1000_82547) {

   206 			u16 fused, fine, coarse;

   207 

   208 			/* Move to analog registers page */

   209 			e1000_read_phy_reg(hw,

   210 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   211 					   &fused);

   212 

   213 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   214 				e1000_read_phy_reg(hw,

   215 						   IGP01E1000_ANALOG_FUSE_STATUS,

   216 						   &fused);

   217 

   218 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   219 				coarse =

   220 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   221 

   222 				if (coarse >

   223 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   224 					coarse -=

   225 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   226 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   227 				} else if (coarse ==

   228 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   229 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   230 

   231 				fused =

   232 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   233 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   234 				    (coarse &

   235 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   236 

   237 				e1000_write_phy_reg(hw,

   238 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   239 						    fused);

   240 				e1000_write_phy_reg(hw,

   241 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   242 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   243 			}

   244 		}

   245 	}

   246 }

   247 

   248 /**

   249  * e1000_set_mac_type - Set the mac type member in the hw struct.

   250  * @hw: Struct containing variables accessed by shared code

   251  */

   252 s32 e1000_set_mac_type(struct e1000_hw *hw)

   253 {

   254 	e_dbg("e1000_set_mac_type");

   255 

   256 	switch (hw->device_id) {

   257 	case E1000_DEV_ID_82542:

   258 		switch (hw->revision_id) {

   259 		case E1000_82542_2_0_REV_ID:

   260 			hw->mac_type = e1000_82542_rev2_0;

   261 			break;

   262 		case E1000_82542_2_1_REV_ID:

   263 			hw->mac_type = e1000_82542_rev2_1;

   264 			break;

   265 		default:

   266 			/* Invalid 82542 revision ID */

   267 			return -E1000_ERR_MAC_TYPE;

   268 		}

   269 		break;

   270 	case E1000_DEV_ID_82543GC_FIBER:

   271 	case E1000_DEV_ID_82543GC_COPPER:

   272 		hw->mac_type = e1000_82543;

   273 		break;

   274 	case E1000_DEV_ID_82544EI_COPPER:

   275 	case E1000_DEV_ID_82544EI_FIBER:

   276 	case E1000_DEV_ID_82544GC_COPPER:

   277 	case E1000_DEV_ID_82544GC_LOM:

   278 		hw->mac_type = e1000_82544;

   279 		break;

   280 	case E1000_DEV_ID_82540EM:

   281 	case E1000_DEV_ID_82540EM_LOM:

   282 	case E1000_DEV_ID_82540EP:

   283 	case E1000_DEV_ID_82540EP_LOM:

   284 	case E1000_DEV_ID_82540EP_LP:

   285 		hw->mac_type = e1000_82540;

   286 		break;

   287 	case E1000_DEV_ID_82545EM_COPPER:

   288 	case E1000_DEV_ID_82545EM_FIBER:

   289 		hw->mac_type = e1000_82545;

   290 		break;

   291 	case E1000_DEV_ID_82545GM_COPPER:

   292 	case E1000_DEV_ID_82545GM_FIBER:

   293 	case E1000_DEV_ID_82545GM_SERDES:

   294 		hw->mac_type = e1000_82545_rev_3;

   295 		break;

   296 	case E1000_DEV_ID_82546EB_COPPER:

   297 	case E1000_DEV_ID_82546EB_FIBER:

   298 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   299 		hw->mac_type = e1000_82546;

   300 		break;

   301 	case E1000_DEV_ID_82546GB_COPPER:

   302 	case E1000_DEV_ID_82546GB_FIBER:

   303 	case E1000_DEV_ID_82546GB_SERDES:

   304 	case E1000_DEV_ID_82546GB_PCIE:

   305 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   306 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   307 		hw->mac_type = e1000_82546_rev_3;

   308 		break;

   309 	case E1000_DEV_ID_82541EI:

   310 	case E1000_DEV_ID_82541EI_MOBILE:

   311 	case E1000_DEV_ID_82541ER_LOM:

   312 		hw->mac_type = e1000_82541;

   313 		break;

   314 	case E1000_DEV_ID_82541ER:

   315 	case E1000_DEV_ID_82541GI:

   316 	case E1000_DEV_ID_82541GI_LF:

   317 	case E1000_DEV_ID_82541GI_MOBILE:

   318 		hw->mac_type = e1000_82541_rev_2;

   319 		break;

   320 	case E1000_DEV_ID_82547EI:

   321 	case E1000_DEV_ID_82547EI_MOBILE:

   322 		hw->mac_type = e1000_82547;

   323 		break;

   324 	case E1000_DEV_ID_82547GI:

   325 		hw->mac_type = e1000_82547_rev_2;

   326 		break;

   327 	case E1000_DEV_ID_INTEL_CE4100_GBE:

   328 		hw->mac_type = e1000_ce4100;

   329 		break;

   330 	default:

   331 		/* Should never have loaded on this device */

   332 		return -E1000_ERR_MAC_TYPE;

   333 	}

   334 

   335 	switch (hw->mac_type) {

   336 	case e1000_82541:

   337 	case e1000_82547:

   338 	case e1000_82541_rev_2:

   339 	case e1000_82547_rev_2:

   340 		hw->asf_firmware_present = true;

   341 		break;

   342 	default:

   343 		break;

   344 	}

   345 

   346 	/* The 82543 chip does not count tx_carrier_errors properly in

   347 	 * FD mode

   348 	 */

   349 	if (hw->mac_type == e1000_82543)

   350 		hw->bad_tx_carr_stats_fd = true;

   351 

   352 	if (hw->mac_type > e1000_82544)

   353 		hw->has_smbus = true;

   354 

   355 	return E1000_SUCCESS;

   356 }

   357 

   358 /**

   359  * e1000_set_media_type - Set media type and TBI compatibility.

   360  * @hw: Struct containing variables accessed by shared code

   361  */

   362 void e1000_set_media_type(struct e1000_hw *hw)

   363 {

   364 	u32 status;

   365 

   366 	e_dbg("e1000_set_media_type");

   367 

   368 	if (hw->mac_type != e1000_82543) {

   369 		/* tbi_compatibility is only valid on 82543 */

   370 		hw->tbi_compatibility_en = false;

   371 	}

   372 

   373 	switch (hw->device_id) {

   374 	case E1000_DEV_ID_82545GM_SERDES:

   375 	case E1000_DEV_ID_82546GB_SERDES:

   376 		hw->media_type = e1000_media_type_internal_serdes;

   377 		break;

   378 	default:

   379 		switch (hw->mac_type) {

   380 		case e1000_82542_rev2_0:

   381 		case e1000_82542_rev2_1:

   382 			hw->media_type = e1000_media_type_fiber;

   383 			break;

   384 		case e1000_ce4100:

   385 			hw->media_type = e1000_media_type_copper;

   386 			break;

   387 		default:

   388 			status = er32(STATUS);

   389 			if (status & E1000_STATUS_TBIMODE) {

   390 				hw->media_type = e1000_media_type_fiber;

   391 				/* tbi_compatibility not valid on fiber */

   392 				hw->tbi_compatibility_en = false;

   393 			} else {

   394 				hw->media_type = e1000_media_type_copper;

   395 			}

   396 			break;

   397 		}

   398 	}

   399 }

   400 

   401 /**

   402  * e1000_reset_hw: reset the hardware completely

   403  * @hw: Struct containing variables accessed by shared code

   404  *

   405  * Reset the transmit and receive units; mask and clear all interrupts.

   406  */

   407 s32 e1000_reset_hw(struct e1000_hw *hw)

   408 {

   409 	u32 ctrl;

   410 	u32 ctrl_ext;

   411 	u32 icr;

   412 	u32 manc;

   413 	u32 led_ctrl;

   414 	s32 ret_val;

   415 

   416 	e_dbg("e1000_reset_hw");

   417 

   418 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   419 	if (hw->mac_type == e1000_82542_rev2_0) {

   420 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   421 		e1000_pci_clear_mwi(hw);

   422 	}

   423 

   424 	/* Clear interrupt mask to stop board from generating interrupts */

   425 	e_dbg("Masking off all interrupts\n");

   426 	ew32(IMC, 0xffffffff);

   427 

   428 	/* Disable the Transmit and Receive units.  Then delay to allow

   429 	 * any pending transactions to complete before we hit the MAC with

   430 	 * the global reset.

   431 	 */

   432 	ew32(RCTL, 0);

   433 	ew32(TCTL, E1000_TCTL_PSP);

   434 	E1000_WRITE_FLUSH();

   435 

   436 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   437 	hw->tbi_compatibility_on = false;

   438 

   439 	/* Delay to allow any outstanding PCI transactions to complete before

   440 	 * resetting the device

   441 	 */

   442 	msleep(10);

   443 

   444 	ctrl = er32(CTRL);

   445 

   446 	/* Must reset the PHY before resetting the MAC */

   447 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   448 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   449 		msleep(5);

   450 	}

   451 

   452 	/* Issue a global reset to the MAC.  This will reset the chip's

   453 	 * transmit, receive, DMA, and link units.  It will not effect

   454 	 * the current PCI configuration.  The global reset bit is self-

   455 	 * clearing, and should clear within a microsecond.

   456 	 */

   457 	e_dbg("Issuing a global reset to MAC\n");

   458 

   459 	switch (hw->mac_type) {

   460 	case e1000_82544:

   461 	case e1000_82540:

   462 	case e1000_82545:

   463 	case e1000_82546:

   464 	case e1000_82541:

   465 	case e1000_82541_rev_2:

   466 		/* These controllers can't ack the 64-bit write when issuing the

   467 		 * reset, so use IO-mapping as a workaround to issue the reset */

   468 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   469 		break;

   470 	case e1000_82545_rev_3:

   471 	case e1000_82546_rev_3:

   472 		/* Reset is performed on a shadow of the control register */

   473 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   474 		break;

   475 	case e1000_ce4100:

   476 	default:

   477 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   478 		break;

   479 	}

   480 

   481 	/* After MAC reset, force reload of EEPROM to restore power-on settings to

   482 	 * device.  Later controllers reload the EEPROM automatically, so just wait

   483 	 * for reload to complete.

   484 	 */

   485 	switch (hw->mac_type) {

   486 	case e1000_82542_rev2_0:

   487 	case e1000_82542_rev2_1:

   488 	case e1000_82543:

   489 	case e1000_82544:

   490 		/* Wait for reset to complete */

   491 		udelay(10);

   492 		ctrl_ext = er32(CTRL_EXT);

   493 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   494 		ew32(CTRL_EXT, ctrl_ext);

   495 		E1000_WRITE_FLUSH();

   496 		/* Wait for EEPROM reload */

   497 		msleep(2);

   498 		break;

   499 	case e1000_82541:

   500 	case e1000_82541_rev_2:

   501 	case e1000_82547:

   502 	case e1000_82547_rev_2:

   503 		/* Wait for EEPROM reload */

   504 		msleep(20);

   505 		break;

   506 	default:

   507 		/* Auto read done will delay 5ms or poll based on mac type */

   508 		ret_val = e1000_get_auto_rd_done(hw);

   509 		if (ret_val)

   510 			return ret_val;

   511 		break;

   512 	}

   513 

   514 	/* Disable HW ARPs on ASF enabled adapters */

   515 	if (hw->mac_type >= e1000_82540) {

   516 		manc = er32(MANC);

   517 		manc &= ~(E1000_MANC_ARP_EN);

   518 		ew32(MANC, manc);

   519 	}

   520 

   521 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   522 		e1000_phy_init_script(hw);

   523 

   524 		/* Configure activity LED after PHY reset */

   525 		led_ctrl = er32(LEDCTL);

   526 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   527 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   528 		ew32(LEDCTL, led_ctrl);

   529 	}

   530 

   531 	/* Clear interrupt mask to stop board from generating interrupts */

   532 	e_dbg("Masking off all interrupts\n");

   533 	ew32(IMC, 0xffffffff);

   534 

   535 	/* Clear any pending interrupt events. */

   536 	icr = er32(ICR);

   537 

   538 	/* If MWI was previously enabled, reenable it. */

   539 	if (hw->mac_type == e1000_82542_rev2_0) {

   540 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   541 			e1000_pci_set_mwi(hw);

   542 	}

   543 

   544 	return E1000_SUCCESS;

   545 }

   546 

   547 /**

   548  * e1000_init_hw: Performs basic configuration of the adapter.

   549  * @hw: Struct containing variables accessed by shared code

   550  *

   551  * Assumes that the controller has previously been reset and is in a

   552  * post-reset uninitialized state. Initializes the receive address registers,

   553  * multicast table, and VLAN filter table. Calls routines to setup link

   554  * configuration and flow control settings. Clears all on-chip counters. Leaves

   555  * the transmit and receive units disabled and uninitialized.

   556  */

   557 s32 e1000_init_hw(struct e1000_hw *hw)

   558 {

   559 	u32 ctrl;

   560 	u32 i;

   561 	s32 ret_val;

   562 	u32 mta_size;

   563 	u32 ctrl_ext;

   564 

   565 	e_dbg("e1000_init_hw");

   566 

   567 	/* Initialize Identification LED */

   568 	ret_val = e1000_id_led_init(hw);

   569 	if (ret_val) {

   570 		e_dbg("Error Initializing Identification LED\n");

   571 		return ret_val;

   572 	}

   573 

   574 	/* Set the media type and TBI compatibility */

   575 	e1000_set_media_type(hw);

   576 

   577 	/* Disabling VLAN filtering. */

   578 	e_dbg("Initializing the IEEE VLAN\n");

   579 	if (hw->mac_type < e1000_82545_rev_3)

   580 		ew32(VET, 0);

   581 	e1000_clear_vfta(hw);

   582 

   583 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   584 	if (hw->mac_type == e1000_82542_rev2_0) {

   585 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   586 		e1000_pci_clear_mwi(hw);

   587 		ew32(RCTL, E1000_RCTL_RST);

   588 		E1000_WRITE_FLUSH();

   589 		msleep(5);

   590 	}

   591 

   592 	/* Setup the receive address. This involves initializing all of the Receive

   593 	 * Address Registers (RARs 0 - 15).

   594 	 */

   595 	e1000_init_rx_addrs(hw);

   596 

   597 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   598 	if (hw->mac_type == e1000_82542_rev2_0) {

   599 		ew32(RCTL, 0);

   600 		E1000_WRITE_FLUSH();

   601 		msleep(1);

   602 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   603 			e1000_pci_set_mwi(hw);

   604 	}

   605 

   606 	/* Zero out the Multicast HASH table */

   607 	e_dbg("Zeroing the MTA\n");

   608 	mta_size = E1000_MC_TBL_SIZE;

   609 	for (i = 0; i < mta_size; i++) {

   610 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   611 		/* use write flush to prevent Memory Write Block (MWB) from

   612 		 * occurring when accessing our register space */

   613 		E1000_WRITE_FLUSH();

   614 	}

   615 

   616 	/* Set the PCI priority bit correctly in the CTRL register.  This

   617 	 * determines if the adapter gives priority to receives, or if it

   618 	 * gives equal priority to transmits and receives.  Valid only on

   619 	 * 82542 and 82543 silicon.

   620 	 */

   621 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   622 		ctrl = er32(CTRL);

   623 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   624 	}

   625 

   626 	switch (hw->mac_type) {

   627 	case e1000_82545_rev_3:

   628 	case e1000_82546_rev_3:

   629 		break;

   630 	default:

   631 		/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */

   632 		if (hw->bus_type == e1000_bus_type_pcix

   633 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   634 			e1000_pcix_set_mmrbc(hw, 2048);

   635 		break;

   636 	}

   637 

   638 	/* Call a subroutine to configure the link and setup flow control. */

   639 	ret_val = e1000_setup_link(hw);

   640 

   641 	/* Set the transmit descriptor write-back policy */

   642 	if (hw->mac_type > e1000_82544) {

   643 		ctrl = er32(TXDCTL);

   644 		ctrl =

   645 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   646 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   647 		ew32(TXDCTL, ctrl);

   648 	}

   649 

   650 	/* Clear all of the statistics registers (clear on read).  It is

   651 	 * important that we do this after we have tried to establish link

   652 	 * because the symbol error count will increment wildly if there

   653 	 * is no link.

   654 	 */

   655 	e1000_clear_hw_cntrs(hw);

   656 

   657 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   658 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   659 		ctrl_ext = er32(CTRL_EXT);

   660 		/* Relaxed ordering must be disabled to avoid a parity

   661 		 * error crash in a PCI slot. */

   662 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   663 		ew32(CTRL_EXT, ctrl_ext);

   664 	}

   665 

   666 	return ret_val;

   667 }

   668 

   669 /**

   670  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   671  * @hw: Struct containing variables accessed by shared code.

   672  */

   673 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   674 {

   675 	u16 eeprom_data;

   676 	s32 ret_val;

   677 

   678 	e_dbg("e1000_adjust_serdes_amplitude");

   679 

   680 	if (hw->media_type != e1000_media_type_internal_serdes)

   681 		return E1000_SUCCESS;

   682 

   683 	switch (hw->mac_type) {

   684 	case e1000_82545_rev_3:

   685 	case e1000_82546_rev_3:

   686 		break;

   687 	default:

   688 		return E1000_SUCCESS;

   689 	}

   690 

   691 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   692 	                            &eeprom_data);

   693 	if (ret_val) {

   694 		return ret_val;

   695 	}

   696 

   697 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   698 		/* Adjust SERDES output amplitude only. */

   699 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   700 		ret_val =

   701 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   702 		if (ret_val)

   703 			return ret_val;

   704 	}

   705 

   706 	return E1000_SUCCESS;

   707 }

   708 

   709 /**

   710  * e1000_setup_link - Configures flow control and link settings.

   711  * @hw: Struct containing variables accessed by shared code

   712  *

   713  * Determines which flow control settings to use. Calls the appropriate media-

   714  * specific link configuration function. Configures the flow control settings.

   715  * Assuming the adapter has a valid link partner, a valid link should be

   716  * established. Assumes the hardware has previously been reset and the

   717  * transmitter and receiver are not enabled.

   718  */

   719 s32 e1000_setup_link(struct e1000_hw *hw)

   720 {

   721 	u32 ctrl_ext;

   722 	s32 ret_val;

   723 	u16 eeprom_data;

   724 

   725 	e_dbg("e1000_setup_link");

   726 

   727 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   728 	 * that determine the hardware's default PAUSE (flow control) mode,

   729 	 * a bit that determines whether the HW defaults to enabling or

   730 	 * disabling auto-negotiation, and the direction of the

   731 	 * SW defined pins. If there is no SW over-ride of the flow

   732 	 * control setting, then the variable hw->fc will

   733 	 * be initialized based on a value in the EEPROM.

   734 	 */

   735 	if (hw->fc == E1000_FC_DEFAULT) {

   736 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   737 					    1, &eeprom_data);

   738 		if (ret_val) {

   739 			e_dbg("EEPROM Read Error\n");

   740 			return -E1000_ERR_EEPROM;

   741 		}

   742 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   743 			hw->fc = E1000_FC_NONE;

   744 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   745 			 EEPROM_WORD0F_ASM_DIR)

   746 			hw->fc = E1000_FC_TX_PAUSE;

   747 		else

   748 			hw->fc = E1000_FC_FULL;

   749 	}

   750 

   751 	/* We want to save off the original Flow Control configuration just

   752 	 * in case we get disconnected and then reconnected into a different

   753 	 * hub or switch with different Flow Control capabilities.

   754 	 */

   755 	if (hw->mac_type == e1000_82542_rev2_0)

   756 		hw->fc &= (~E1000_FC_TX_PAUSE);

   757 

   758 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   759 		hw->fc &= (~E1000_FC_RX_PAUSE);

   760 

   761 	hw->original_fc = hw->fc;

   762 

   763 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   764 

   765 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   766 	 * polarity value for the SW controlled pins, and setup the

   767 	 * Extended Device Control reg with that info.

   768 	 * This is needed because one of the SW controlled pins is used for

   769 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   770 	 * or e1000_phy_setup() is called.

   771 	 */

   772 	if (hw->mac_type == e1000_82543) {

   773 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   774 					    1, &eeprom_data);

   775 		if (ret_val) {

   776 			e_dbg("EEPROM Read Error\n");

   777 			return -E1000_ERR_EEPROM;

   778 		}

   779 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   780 			    SWDPIO__EXT_SHIFT);

   781 		ew32(CTRL_EXT, ctrl_ext);

   782 	}

   783 

   784 	/* Call the necessary subroutine to configure the link. */

   785 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   786 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   787 

   788 	/* Initialize the flow control address, type, and PAUSE timer

   789 	 * registers to their default values.  This is done even if flow

   790 	 * control is disabled, because it does not hurt anything to

   791 	 * initialize these registers.

   792 	 */

   793 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   794 

   795 	ew32(FCT, FLOW_CONTROL_TYPE);

   796 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   797 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   798 

   799 	ew32(FCTTV, hw->fc_pause_time);

   800 

   801 	/* Set the flow control receive threshold registers.  Normally,

   802 	 * these registers will be set to a default threshold that may be

   803 	 * adjusted later by the driver's runtime code.  However, if the

   804 	 * ability to transmit pause frames in not enabled, then these

   805 	 * registers will be set to 0.

   806 	 */

   807 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   808 		ew32(FCRTL, 0);

   809 		ew32(FCRTH, 0);

   810 	} else {

   811 		/* We need to set up the Receive Threshold high and low water marks

   812 		 * as well as (optionally) enabling the transmission of XON frames.

   813 		 */

   814 		if (hw->fc_send_xon) {

   815 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   816 			ew32(FCRTH, hw->fc_high_water);

   817 		} else {

   818 			ew32(FCRTL, hw->fc_low_water);

   819 			ew32(FCRTH, hw->fc_high_water);

   820 		}

   821 	}

   822 	return ret_val;

   823 }

   824 

   825 /**

   826  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   827  * @hw: Struct containing variables accessed by shared code

   828  *

   829  * Manipulates Physical Coding Sublayer functions in order to configure

   830  * link. Assumes the hardware has been previously reset and the transmitter

   831  * and receiver are not enabled.

   832  */

   833 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   834 {

   835 	u32 ctrl;

   836 	u32 status;

   837 	u32 txcw = 0;

   838 	u32 i;

   839 	u32 signal = 0;

   840 	s32 ret_val;

   841 

   842 	e_dbg("e1000_setup_fiber_serdes_link");

   843 

   844 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   845 	 * set when the optics detect a signal. On older adapters, it will be

   846 	 * cleared when there is a signal.  This applies to fiber media only.

   847 	 * If we're on serdes media, adjust the output amplitude to value

   848 	 * set in the EEPROM.

   849 	 */

   850 	ctrl = er32(CTRL);

   851 	if (hw->media_type == e1000_media_type_fiber)

   852 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   853 

   854 	ret_val = e1000_adjust_serdes_amplitude(hw);

   855 	if (ret_val)

   856 		return ret_val;

   857 

   858 	/* Take the link out of reset */

   859 	ctrl &= ~(E1000_CTRL_LRST);

   860 

   861 	/* Adjust VCO speed to improve BER performance */

   862 	ret_val = e1000_set_vco_speed(hw);

   863 	if (ret_val)

   864 		return ret_val;

   865 

   866 	e1000_config_collision_dist(hw);

   867 

   868 	/* Check for a software override of the flow control settings, and setup

   869 	 * the device accordingly.  If auto-negotiation is enabled, then software

   870 	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit

   871 	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if

   872 	 * auto-negotiation is disabled, then software will have to manually

   873 	 * configure the two flow control enable bits in the CTRL register.

   874 	 *

   875 	 * The possible values of the "fc" parameter are:

   876 	 *      0:  Flow control is completely disabled

   877 	 *      1:  Rx flow control is enabled (we can receive pause frames, but

   878 	 *          not send pause frames).

   879 	 *      2:  Tx flow control is enabled (we can send pause frames but we do

   880 	 *          not support receiving pause frames).

   881 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.

   882 	 */

   883 	switch (hw->fc) {

   884 	case E1000_FC_NONE:

   885 		/* Flow control is completely disabled by a software over-ride. */

   886 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   887 		break;

   888 	case E1000_FC_RX_PAUSE:

   889 		/* RX Flow control is enabled and TX Flow control is disabled by a

   890 		 * software over-ride. Since there really isn't a way to advertise

   891 		 * that we are capable of RX Pause ONLY, we will advertise that we

   892 		 * support both symmetric and asymmetric RX PAUSE. Later, we will

   893 		 *  disable the adapter's ability to send PAUSE frames.

   894 		 */

   895 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   896 		break;

   897 	case E1000_FC_TX_PAUSE:

   898 		/* TX Flow control is enabled, and RX Flow control is disabled, by a

   899 		 * software over-ride.

   900 		 */

   901 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   902 		break;

   903 	case E1000_FC_FULL:

   904 		/* Flow control (both RX and TX) is enabled by a software over-ride. */

   905 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   906 		break;

   907 	default:

   908 		e_dbg("Flow control param set incorrectly\n");

   909 		return -E1000_ERR_CONFIG;

   910 		break;

   911 	}

   912 

   913 	/* Since auto-negotiation is enabled, take the link out of reset (the link

   914 	 * will be in reset, because we previously reset the chip). This will

   915 	 * restart auto-negotiation.  If auto-negotiation is successful then the

   916 	 * link-up status bit will be set and the flow control enable bits (RFCE

   917 	 * and TFCE) will be set according to their negotiated value.

   918 	 */

   919 	e_dbg("Auto-negotiation enabled\n");

   920 

   921 	ew32(TXCW, txcw);

   922 	ew32(CTRL, ctrl);

   923 	E1000_WRITE_FLUSH();

   924 

   925 	hw->txcw = txcw;

   926 	msleep(1);

   927 

   928 	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"

   929 	 * indication in the Device Status Register.  Time-out if a link isn't

   930 	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in

   931 	 * less than 500 milliseconds even if the other end is doing it in SW).

   932 	 * For internal serdes, we just assume a signal is present, then poll.

   933 	 */

   934 	if (hw->media_type == e1000_media_type_internal_serdes ||

   935 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   936 		e_dbg("Looking for Link\n");

   937 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   938 			msleep(10);

   939 			status = er32(STATUS);

   940 			if (status & E1000_STATUS_LU)

   941 				break;

   942 		}

   943 		if (i == (LINK_UP_TIMEOUT / 10)) {

   944 			e_dbg("Never got a valid link from auto-neg!!!\n");

   945 			hw->autoneg_failed = 1;

   946 			/* AutoNeg failed to achieve a link, so we'll call

   947 			 * e1000_check_for_link. This routine will force the link up if

   948 			 * we detect a signal. This will allow us to communicate with

   949 			 * non-autonegotiating link partners.

   950 			 */

   951 			ret_val = e1000_check_for_link(hw);

   952 			if (ret_val) {

   953 				e_dbg("Error while checking for link\n");

   954 				return ret_val;

   955 			}

   956 			hw->autoneg_failed = 0;

   957 		} else {

   958 			hw->autoneg_failed = 0;

   959 			e_dbg("Valid Link Found\n");

   960 		}

   961 	} else {

   962 		e_dbg("No Signal Detected\n");

   963 	}

   964 	return E1000_SUCCESS;

   965 }

   966 

   967 /**

   968  * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.

   969  * @hw: Struct containing variables accessed by shared code

   970  *

   971  * Commits changes to PHY configuration by calling e1000_phy_reset().

   972  */

   973 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)

   974 {

   975 	s32 ret_val;

   976 

   977 	/* SW reset the PHY so all changes take effect */

   978 	ret_val = e1000_phy_reset(hw);

   979 	if (ret_val) {

   980 		e_dbg("Error Resetting the PHY\n");

   981 		return ret_val;

   982 	}

   983 

   984 	return E1000_SUCCESS;

   985 }

   986 

   987 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)

   988 {

   989 	s32 ret_val;

   990 	u32 ctrl_aux;

   991 

   992 	switch (hw->phy_type) {

   993 	case e1000_phy_8211:

   994 		ret_val = e1000_copper_link_rtl_setup(hw);

   995 		if (ret_val) {

   996 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

   997 			return ret_val;

   998 		}

   999 		break;

  1000 	case e1000_phy_8201:

  1001 		/* Set RMII mode */

  1002 		ctrl_aux = er32(CTL_AUX);

  1003 		ctrl_aux |= E1000_CTL_AUX_RMII;

  1004 		ew32(CTL_AUX, ctrl_aux);

  1005 		E1000_WRITE_FLUSH();

  1006 

  1007 		/* Disable the J/K bits required for receive */

  1008 		ctrl_aux = er32(CTL_AUX);

  1009 		ctrl_aux |= 0x4;

  1010 		ctrl_aux &= ~0x2;

  1011 		ew32(CTL_AUX, ctrl_aux);

  1012 		E1000_WRITE_FLUSH();

  1013 		ret_val = e1000_copper_link_rtl_setup(hw);

  1014 

  1015 		if (ret_val) {

  1016 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1017 			return ret_val;

  1018 		}

  1019 		break;

  1020 	default:

  1021 		e_dbg("Error Resetting the PHY\n");

  1022 		return E1000_ERR_PHY_TYPE;

  1023 	}

  1024 

  1025 	return E1000_SUCCESS;

  1026 }

  1027 

  1028 /**

  1029  * e1000_copper_link_preconfig - early configuration for copper

  1030  * @hw: Struct containing variables accessed by shared code

  1031  *

  1032  * Make sure we have a valid PHY and change PHY mode before link setup.

  1033  */

  1034 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1035 {

  1036 	u32 ctrl;

  1037 	s32 ret_val;

  1038 	u16 phy_data;

  1039 

  1040 	e_dbg("e1000_copper_link_preconfig");

  1041 

  1042 	ctrl = er32(CTRL);

  1043 	/* With 82543, we need to force speed and duplex on the MAC equal to what

  1044 	 * the PHY speed and duplex configuration is. In addition, we need to

  1045 	 * perform a hardware reset on the PHY to take it out of reset.

  1046 	 */

  1047 	if (hw->mac_type > e1000_82543) {

  1048 		ctrl |= E1000_CTRL_SLU;

  1049 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1050 		ew32(CTRL, ctrl);

  1051 	} else {

  1052 		ctrl |=

  1053 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1054 		ew32(CTRL, ctrl);

  1055 		ret_val = e1000_phy_hw_reset(hw);

  1056 		if (ret_val)

  1057 			return ret_val;

  1058 	}

  1059 

  1060 	/* Make sure we have a valid PHY */

  1061 	ret_val = e1000_detect_gig_phy(hw);

  1062 	if (ret_val) {

  1063 		e_dbg("Error, did not detect valid phy.\n");

  1064 		return ret_val;

  1065 	}

  1066 	e_dbg("Phy ID = %x\n", hw->phy_id);

  1067 

  1068 	/* Set PHY to class A mode (if necessary) */

  1069 	ret_val = e1000_set_phy_mode(hw);

  1070 	if (ret_val)

  1071 		return ret_val;

  1072 

  1073 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1074 	    (hw->mac_type == e1000_82546_rev_3)) {

  1075 		ret_val =

  1076 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1077 		phy_data |= 0x00000008;

  1078 		ret_val =

  1079 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1080 	}

  1081 

  1082 	if (hw->mac_type <= e1000_82543 ||

  1083 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1084 	    hw->mac_type == e1000_82541_rev_2

  1085 	    || hw->mac_type == e1000_82547_rev_2)

  1086 		hw->phy_reset_disable = false;

  1087 

  1088 	return E1000_SUCCESS;

  1089 }

  1090 

  1091 /**

  1092  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1093  * @hw: Struct containing variables accessed by shared code

  1094  */

  1095 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1096 {

  1097 	u32 led_ctrl;

  1098 	s32 ret_val;

  1099 	u16 phy_data;

  1100 

  1101 	e_dbg("e1000_copper_link_igp_setup");

  1102 

  1103 	if (hw->phy_reset_disable)

  1104 		return E1000_SUCCESS;

  1105 

  1106 	ret_val = e1000_phy_reset(hw);

  1107 	if (ret_val) {

  1108 		e_dbg("Error Resetting the PHY\n");

  1109 		return ret_val;

  1110 	}

  1111 

  1112 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1113 	msleep(15);

  1114 	/* Configure activity LED after PHY reset */

  1115 	led_ctrl = er32(LEDCTL);

  1116 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1117 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1118 	ew32(LEDCTL, led_ctrl);

  1119 

  1120 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1121 	if (hw->phy_type == e1000_phy_igp) {

  1122 		/* disable lplu d3 during driver init */

  1123 		ret_val = e1000_set_d3_lplu_state(hw, false);

  1124 		if (ret_val) {

  1125 			e_dbg("Error Disabling LPLU D3\n");

  1126 			return ret_val;

  1127 		}

  1128 	}

  1129 

  1130 	/* Configure mdi-mdix settings */

  1131 	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);

  1132 	if (ret_val)

  1133 		return ret_val;

  1134 

  1135 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

  1136 		hw->dsp_config_state = e1000_dsp_config_disabled;