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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2012 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 /* |
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30 * 82571EB Gigabit Ethernet Controller |
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31 * 82571EB Gigabit Ethernet Controller (Copper) |
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32 * 82571EB Gigabit Ethernet Controller (Fiber) |
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33 * 82571EB Dual Port Gigabit Mezzanine Adapter |
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34 * 82571EB Quad Port Gigabit Mezzanine Adapter |
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35 * 82571PT Gigabit PT Quad Port Server ExpressModule |
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36 * 82572EI Gigabit Ethernet Controller (Copper) |
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37 * 82572EI Gigabit Ethernet Controller (Fiber) |
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38 * 82572EI Gigabit Ethernet Controller |
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39 * 82573V Gigabit Ethernet Controller (Copper) |
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40 * 82573E Gigabit Ethernet Controller (Copper) |
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41 * 82573L Gigabit Ethernet Controller |
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42 * 82574L Gigabit Network Connection |
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43 * 82583V Gigabit Network Connection |
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44 */ |
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45 |
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46 #include "e1000-3.4-ethercat.h" |
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47 |
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48 #define ID_LED_RESERVED_F746 0xF746 |
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49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ |
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50 (ID_LED_OFF1_ON2 << 8) | \ |
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51 (ID_LED_DEF1_DEF2 << 4) | \ |
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52 (ID_LED_DEF1_DEF2)) |
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53 |
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54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 |
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55 #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ |
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56 #define E1000_BASE1000T_STATUS 10 |
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57 #define E1000_IDLE_ERROR_COUNT_MASK 0xFF |
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58 #define E1000_RECEIVE_ERROR_COUNTER 21 |
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59 #define E1000_RECEIVE_ERROR_MAX 0xFFFF |
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60 |
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61 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
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62 |
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63 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
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64 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); |
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65 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); |
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66 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
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67 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
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68 u16 words, u16 *data); |
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69 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); |
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70 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); |
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71 static s32 e1000_setup_link_82571(struct e1000_hw *hw); |
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72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); |
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73 static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
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74 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
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75 static s32 e1000_led_on_82574(struct e1000_hw *hw); |
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76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
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77 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
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78 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); |
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79 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); |
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80 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); |
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81 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active); |
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82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active); |
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83 |
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84 /** |
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85 * e1000_init_phy_params_82571 - Init PHY func ptrs. |
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86 * @hw: pointer to the HW structure |
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87 **/ |
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88 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) |
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89 { |
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90 struct e1000_phy_info *phy = &hw->phy; |
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91 s32 ret_val __attribute__ ((unused)); |
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92 |
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93 if (hw->phy.media_type != e1000_media_type_copper) { |
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94 phy->type = e1000_phy_none; |
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95 return 0; |
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96 } |
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97 |
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98 phy->addr = 1; |
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99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
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100 phy->reset_delay_us = 100; |
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101 |
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102 phy->ops.power_up = e1000_power_up_phy_copper; |
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103 phy->ops.power_down = e1000_power_down_phy_copper_82571; |
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104 |
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105 switch (hw->mac.type) { |
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106 case e1000_82571: |
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107 case e1000_82572: |
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108 phy->type = e1000_phy_igp_2; |
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109 break; |
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110 case e1000_82573: |
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111 phy->type = e1000_phy_m88; |
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112 break; |
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113 case e1000_82574: |
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114 case e1000_82583: |
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115 phy->type = e1000_phy_bm; |
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116 phy->ops.acquire = e1000_get_hw_semaphore_82574; |
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117 phy->ops.release = e1000_put_hw_semaphore_82574; |
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118 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; |
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119 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; |
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120 break; |
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121 default: |
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122 return -E1000_ERR_PHY; |
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123 break; |
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124 } |
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125 |
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126 /* This can only be done after all function pointers are setup. */ |
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127 ret_val = e1000_get_phy_id_82571(hw); |
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128 if (ret_val) { |
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129 e_dbg("Error getting PHY ID\n"); |
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130 return ret_val; |
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131 } |
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132 |
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133 /* Verify phy id */ |
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134 switch (hw->mac.type) { |
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135 case e1000_82571: |
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136 case e1000_82572: |
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137 if (phy->id != IGP01E1000_I_PHY_ID) |
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138 ret_val = -E1000_ERR_PHY; |
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139 break; |
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140 case e1000_82573: |
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141 if (phy->id != M88E1111_I_PHY_ID) |
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142 ret_val = -E1000_ERR_PHY; |
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143 break; |
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144 case e1000_82574: |
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145 case e1000_82583: |
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146 if (phy->id != BME1000_E_PHY_ID_R2) |
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147 ret_val = -E1000_ERR_PHY; |
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148 break; |
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149 default: |
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150 ret_val = -E1000_ERR_PHY; |
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151 break; |
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152 } |
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153 |
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154 if (ret_val) |
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155 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); |
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156 |
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157 return ret_val; |
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158 } |
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159 |
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160 /** |
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161 * e1000_init_nvm_params_82571 - Init NVM func ptrs. |
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162 * @hw: pointer to the HW structure |
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163 **/ |
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164 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) |
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165 { |
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166 struct e1000_nvm_info *nvm = &hw->nvm; |
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167 u32 eecd = er32(EECD); |
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168 u16 size; |
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169 |
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170 nvm->opcode_bits = 8; |
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171 nvm->delay_usec = 1; |
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172 switch (nvm->override) { |
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173 case e1000_nvm_override_spi_large: |
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174 nvm->page_size = 32; |
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175 nvm->address_bits = 16; |
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176 break; |
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177 case e1000_nvm_override_spi_small: |
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178 nvm->page_size = 8; |
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179 nvm->address_bits = 8; |
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180 break; |
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181 default: |
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182 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; |
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183 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; |
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184 break; |
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185 } |
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186 |
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187 switch (hw->mac.type) { |
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188 case e1000_82573: |
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189 case e1000_82574: |
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190 case e1000_82583: |
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191 if (((eecd >> 15) & 0x3) == 0x3) { |
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192 nvm->type = e1000_nvm_flash_hw; |
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193 nvm->word_size = 2048; |
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194 /* |
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195 * Autonomous Flash update bit must be cleared due |
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196 * to Flash update issue. |
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197 */ |
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198 eecd &= ~E1000_EECD_AUPDEN; |
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199 ew32(EECD, eecd); |
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200 break; |
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201 } |
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202 /* Fall Through */ |
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203 default: |
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204 nvm->type = e1000_nvm_eeprom_spi; |
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205 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
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206 E1000_EECD_SIZE_EX_SHIFT); |
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207 /* |
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208 * Added to a constant, "size" becomes the left-shift value |
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209 * for setting word_size. |
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210 */ |
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211 size += NVM_WORD_SIZE_BASE_SHIFT; |
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212 |
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213 /* EEPROM access above 16k is unsupported */ |
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214 if (size > 14) |
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215 size = 14; |
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216 nvm->word_size = 1 << size; |
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217 break; |
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218 } |
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219 |
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220 /* Function Pointers */ |
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221 switch (hw->mac.type) { |
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222 case e1000_82574: |
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223 case e1000_82583: |
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224 nvm->ops.acquire = e1000_get_hw_semaphore_82574; |
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225 nvm->ops.release = e1000_put_hw_semaphore_82574; |
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226 break; |
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227 default: |
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228 break; |
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229 } |
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230 |
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231 return 0; |
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232 } |
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233 |
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234 /** |
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235 * e1000_init_mac_params_82571 - Init MAC func ptrs. |
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236 * @hw: pointer to the HW structure |
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237 **/ |
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238 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw) |
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239 { |
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240 struct e1000_mac_info *mac = &hw->mac; |
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241 u32 swsm = 0; |
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242 u32 swsm2 = 0; |
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243 bool force_clear_smbi = false; |
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244 |
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245 /* Set media type and media-dependent function pointers */ |
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246 switch (hw->adapter->pdev->device) { |
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247 case E1000_DEV_ID_82571EB_FIBER: |
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248 case E1000_DEV_ID_82572EI_FIBER: |
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249 case E1000_DEV_ID_82571EB_QUAD_FIBER: |
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250 hw->phy.media_type = e1000_media_type_fiber; |
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251 mac->ops.setup_physical_interface = |
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252 e1000_setup_fiber_serdes_link_82571; |
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253 mac->ops.check_for_link = e1000e_check_for_fiber_link; |
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254 mac->ops.get_link_up_info = |
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255 e1000e_get_speed_and_duplex_fiber_serdes; |
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256 break; |
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257 case E1000_DEV_ID_82571EB_SERDES: |
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258 case E1000_DEV_ID_82571EB_SERDES_DUAL: |
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259 case E1000_DEV_ID_82571EB_SERDES_QUAD: |
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260 case E1000_DEV_ID_82572EI_SERDES: |
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261 hw->phy.media_type = e1000_media_type_internal_serdes; |
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262 mac->ops.setup_physical_interface = |
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263 e1000_setup_fiber_serdes_link_82571; |
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264 mac->ops.check_for_link = e1000_check_for_serdes_link_82571; |
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265 mac->ops.get_link_up_info = |
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266 e1000e_get_speed_and_duplex_fiber_serdes; |
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267 break; |
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268 default: |
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269 hw->phy.media_type = e1000_media_type_copper; |
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270 mac->ops.setup_physical_interface = |
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271 e1000_setup_copper_link_82571; |
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272 mac->ops.check_for_link = e1000e_check_for_copper_link; |
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273 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper; |
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274 break; |
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275 } |
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276 |
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277 /* Set mta register count */ |
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278 mac->mta_reg_count = 128; |
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279 /* Set rar entry count */ |
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280 mac->rar_entry_count = E1000_RAR_ENTRIES; |
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281 /* Adaptive IFS supported */ |
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282 mac->adaptive_ifs = true; |
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283 |
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284 /* MAC-specific function pointers */ |
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285 switch (hw->mac.type) { |
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286 case e1000_82573: |
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287 mac->ops.set_lan_id = e1000_set_lan_id_single_port; |
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288 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; |
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289 mac->ops.led_on = e1000e_led_on_generic; |
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290 mac->ops.blink_led = e1000e_blink_led_generic; |
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291 |
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292 /* FWSM register */ |
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293 mac->has_fwsm = true; |
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294 /* |
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295 * ARC supported; valid only if manageability features are |
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296 * enabled. |
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297 */ |
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298 mac->arc_subsystem_valid = |
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299 (er32(FWSM) & E1000_FWSM_MODE_MASK) |
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300 ? true : false; |
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301 break; |
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302 case e1000_82574: |
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303 case e1000_82583: |
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304 mac->ops.set_lan_id = e1000_set_lan_id_single_port; |
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305 mac->ops.check_mng_mode = e1000_check_mng_mode_82574; |
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306 mac->ops.led_on = e1000_led_on_82574; |
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307 break; |
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308 default: |
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309 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; |
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310 mac->ops.led_on = e1000e_led_on_generic; |
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311 mac->ops.blink_led = e1000e_blink_led_generic; |
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312 |
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313 /* FWSM register */ |
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314 mac->has_fwsm = true; |
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315 break; |
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316 } |
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317 |
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318 /* |
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319 * Ensure that the inter-port SWSM.SMBI lock bit is clear before |
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320 * first NVM or PHY access. This should be done for single-port |
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321 * devices, and for one port only on dual-port devices so that |
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322 * for those devices we can still use the SMBI lock to synchronize |
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323 * inter-port accesses to the PHY & NVM. |
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324 */ |
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325 switch (hw->mac.type) { |
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326 case e1000_82571: |
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327 case e1000_82572: |
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328 swsm2 = er32(SWSM2); |
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329 |
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330 if (!(swsm2 & E1000_SWSM2_LOCK)) { |
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331 /* Only do this for the first interface on this card */ |
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332 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK); |
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333 force_clear_smbi = true; |
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334 } else { |
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335 force_clear_smbi = false; |
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336 } |
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337 break; |
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338 default: |
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339 force_clear_smbi = true; |
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340 break; |
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341 } |
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342 |
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343 if (force_clear_smbi) { |
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344 /* Make sure SWSM.SMBI is clear */ |
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345 swsm = er32(SWSM); |
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346 if (swsm & E1000_SWSM_SMBI) { |
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347 /* This bit should not be set on a first interface, and |
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348 * indicates that the bootagent or EFI code has |
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349 * improperly left this bit enabled |
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350 */ |
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351 e_dbg("Please update your 82571 Bootagent\n"); |
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352 } |
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353 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); |
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354 } |
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355 |
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356 /* |
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357 * Initialize device specific counter of SMBI acquisition |
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358 * timeouts. |
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359 */ |
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360 hw->dev_spec.e82571.smb_counter = 0; |
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361 |
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362 return 0; |
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363 } |
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364 |
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365 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
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366 { |
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367 struct e1000_hw *hw = &adapter->hw; |
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368 static int global_quad_port_a; /* global port a indication */ |
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369 struct pci_dev *pdev = adapter->pdev; |
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370 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
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371 s32 rc; |
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372 |
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373 rc = e1000_init_mac_params_82571(hw); |
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374 if (rc) |
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375 return rc; |
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376 |
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377 rc = e1000_init_nvm_params_82571(hw); |
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378 if (rc) |
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379 return rc; |
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380 |
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381 rc = e1000_init_phy_params_82571(hw); |
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382 if (rc) |
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383 return rc; |
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384 |
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385 /* tag quad port adapters first, it's used below */ |
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386 switch (pdev->device) { |
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387 case E1000_DEV_ID_82571EB_QUAD_COPPER: |
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388 case E1000_DEV_ID_82571EB_QUAD_FIBER: |
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389 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: |
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390 case E1000_DEV_ID_82571PT_QUAD_COPPER: |
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391 adapter->flags |= FLAG_IS_QUAD_PORT; |
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392 /* mark the first port */ |
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393 if (global_quad_port_a == 0) |
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394 adapter->flags |= FLAG_IS_QUAD_PORT_A; |
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395 /* Reset for multiple quad port adapters */ |
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396 global_quad_port_a++; |
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397 if (global_quad_port_a == 4) |
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398 global_quad_port_a = 0; |
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399 break; |
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400 default: |
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401 break; |
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402 } |
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403 |
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404 switch (adapter->hw.mac.type) { |
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405 case e1000_82571: |
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406 /* these dual ports don't have WoL on port B at all */ |
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407 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || |
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408 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || |
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409 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && |
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410 (is_port_b)) |
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411 adapter->flags &= ~FLAG_HAS_WOL; |
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412 /* quad ports only support WoL on port A */ |
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413 if (adapter->flags & FLAG_IS_QUAD_PORT && |
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414 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
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415 adapter->flags &= ~FLAG_HAS_WOL; |
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416 /* Does not support WoL on any port */ |
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417 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) |
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418 adapter->flags &= ~FLAG_HAS_WOL; |
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419 break; |
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420 case e1000_82573: |
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421 if (pdev->device == E1000_DEV_ID_82573L) { |
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422 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
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423 adapter->max_hw_frame_size = DEFAULT_JUMBO; |
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424 } |
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425 break; |
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426 default: |
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427 break; |
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428 } |
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429 |
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430 return 0; |
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431 } |
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432 |
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433 /** |
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434 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision |
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435 * @hw: pointer to the HW structure |
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436 * |
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437 * Reads the PHY registers and stores the PHY ID and possibly the PHY |
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438 * revision in the hardware structure. |
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439 **/ |
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440 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) |
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441 { |
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442 struct e1000_phy_info *phy = &hw->phy; |
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443 s32 ret_val; |
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444 u16 phy_id = 0; |
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445 |
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446 switch (hw->mac.type) { |
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447 case e1000_82571: |
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448 case e1000_82572: |
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449 /* |
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450 * The 82571 firmware may still be configuring the PHY. |
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451 * In this case, we cannot access the PHY until the |
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452 * configuration is done. So we explicitly set the |
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453 * PHY ID. |
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454 */ |
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455 phy->id = IGP01E1000_I_PHY_ID; |
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456 break; |
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457 case e1000_82573: |
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458 return e1000e_get_phy_id(hw); |
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459 break; |
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460 case e1000_82574: |
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461 case e1000_82583: |
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462 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
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463 if (ret_val) |
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464 return ret_val; |
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465 |
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466 phy->id = (u32)(phy_id << 16); |
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467 udelay(20); |
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468 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); |
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469 if (ret_val) |
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470 return ret_val; |
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471 |
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472 phy->id |= (u32)(phy_id); |
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473 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
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474 break; |
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475 default: |
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476 return -E1000_ERR_PHY; |
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477 break; |
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478 } |
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479 |
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480 return 0; |
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481 } |
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482 |
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483 /** |
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484 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore |
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485 * @hw: pointer to the HW structure |
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486 * |
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487 * Acquire the HW semaphore to access the PHY or NVM |
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488 **/ |
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489 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) |
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490 { |
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491 u32 swsm; |
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492 s32 sw_timeout = hw->nvm.word_size + 1; |
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493 s32 fw_timeout = hw->nvm.word_size + 1; |
|
494 s32 i = 0; |
|
495 |
|
496 /* |
|
497 * If we have timedout 3 times on trying to acquire |
|
498 * the inter-port SMBI semaphore, there is old code |
|
499 * operating on the other port, and it is not |
|
500 * releasing SMBI. Modify the number of times that |
|
501 * we try for the semaphore to interwork with this |
|
502 * older code. |
|
503 */ |
|
504 if (hw->dev_spec.e82571.smb_counter > 2) |
|
505 sw_timeout = 1; |
|
506 |
|
507 /* Get the SW semaphore */ |
|
508 while (i < sw_timeout) { |
|
509 swsm = er32(SWSM); |
|
510 if (!(swsm & E1000_SWSM_SMBI)) |
|
511 break; |
|
512 |
|
513 udelay(50); |
|
514 i++; |
|
515 } |
|
516 |
|
517 if (i == sw_timeout) { |
|
518 e_dbg("Driver can't access device - SMBI bit is set.\n"); |
|
519 hw->dev_spec.e82571.smb_counter++; |
|
520 } |
|
521 /* Get the FW semaphore. */ |
|
522 for (i = 0; i < fw_timeout; i++) { |
|
523 swsm = er32(SWSM); |
|
524 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
|
525 |
|
526 /* Semaphore acquired if bit latched */ |
|
527 if (er32(SWSM) & E1000_SWSM_SWESMBI) |
|
528 break; |
|
529 |
|
530 udelay(50); |
|
531 } |
|
532 |
|
533 if (i == fw_timeout) { |
|
534 /* Release semaphores */ |
|
535 e1000_put_hw_semaphore_82571(hw); |
|
536 e_dbg("Driver can't access the NVM\n"); |
|
537 return -E1000_ERR_NVM; |
|
538 } |
|
539 |
|
540 return 0; |
|
541 } |
|
542 |
|
543 /** |
|
544 * e1000_put_hw_semaphore_82571 - Release hardware semaphore |
|
545 * @hw: pointer to the HW structure |
|
546 * |
|
547 * Release hardware semaphore used to access the PHY or NVM |
|
548 **/ |
|
549 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) |
|
550 { |
|
551 u32 swsm; |
|
552 |
|
553 swsm = er32(SWSM); |
|
554 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
|
555 ew32(SWSM, swsm); |
|
556 } |
|
557 /** |
|
558 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore |
|
559 * @hw: pointer to the HW structure |
|
560 * |
|
561 * Acquire the HW semaphore during reset. |
|
562 * |
|
563 **/ |
|
564 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) |
|
565 { |
|
566 u32 extcnf_ctrl; |
|
567 s32 i = 0; |
|
568 |
|
569 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
570 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
571 do { |
|
572 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
573 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
574 |
|
575 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
|
576 break; |
|
577 |
|
578 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
579 |
|
580 usleep_range(2000, 4000); |
|
581 i++; |
|
582 } while (i < MDIO_OWNERSHIP_TIMEOUT); |
|
583 |
|
584 if (i == MDIO_OWNERSHIP_TIMEOUT) { |
|
585 /* Release semaphores */ |
|
586 e1000_put_hw_semaphore_82573(hw); |
|
587 e_dbg("Driver can't access the PHY\n"); |
|
588 return -E1000_ERR_PHY; |
|
589 } |
|
590 |
|
591 return 0; |
|
592 } |
|
593 |
|
594 /** |
|
595 * e1000_put_hw_semaphore_82573 - Release hardware semaphore |
|
596 * @hw: pointer to the HW structure |
|
597 * |
|
598 * Release hardware semaphore used during reset. |
|
599 * |
|
600 **/ |
|
601 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) |
|
602 { |
|
603 u32 extcnf_ctrl; |
|
604 |
|
605 extcnf_ctrl = er32(EXTCNF_CTRL); |
|
606 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
|
607 ew32(EXTCNF_CTRL, extcnf_ctrl); |
|
608 } |
|
609 |
|
610 static DEFINE_MUTEX(swflag_mutex); |
|
611 |
|
612 /** |
|
613 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore |
|
614 * @hw: pointer to the HW structure |
|
615 * |
|
616 * Acquire the HW semaphore to access the PHY or NVM. |
|
617 * |
|
618 **/ |
|
619 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) |
|
620 { |
|
621 s32 ret_val; |
|
622 |
|
623 mutex_lock(&swflag_mutex); |
|
624 ret_val = e1000_get_hw_semaphore_82573(hw); |
|
625 if (ret_val) |
|
626 mutex_unlock(&swflag_mutex); |
|
627 return ret_val; |
|
628 } |
|
629 |
|
630 /** |
|
631 * e1000_put_hw_semaphore_82574 - Release hardware semaphore |
|
632 * @hw: pointer to the HW structure |
|
633 * |
|
634 * Release hardware semaphore used to access the PHY or NVM |
|
635 * |
|
636 **/ |
|
637 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) |
|
638 { |
|
639 e1000_put_hw_semaphore_82573(hw); |
|
640 mutex_unlock(&swflag_mutex); |
|
641 } |
|
642 |
|
643 /** |
|
644 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state |
|
645 * @hw: pointer to the HW structure |
|
646 * @active: true to enable LPLU, false to disable |
|
647 * |
|
648 * Sets the LPLU D0 state according to the active flag. |
|
649 * LPLU will not be activated unless the |
|
650 * device autonegotiation advertisement meets standards of |
|
651 * either 10 or 10/100 or 10/100/1000 at all duplexes. |
|
652 * This is a function pointer entry point only called by |
|
653 * PHY setup routines. |
|
654 **/ |
|
655 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) |
|
656 { |
|
657 u16 data = er32(POEMB); |
|
658 |
|
659 if (active) |
|
660 data |= E1000_PHY_CTRL_D0A_LPLU; |
|
661 else |
|
662 data &= ~E1000_PHY_CTRL_D0A_LPLU; |
|
663 |
|
664 ew32(POEMB, data); |
|
665 return 0; |
|
666 } |
|
667 |
|
668 /** |
|
669 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 |
|
670 * @hw: pointer to the HW structure |
|
671 * @active: boolean used to enable/disable lplu |
|
672 * |
|
673 * The low power link up (lplu) state is set to the power management level D3 |
|
674 * when active is true, else clear lplu for D3. LPLU |
|
675 * is used during Dx states where the power conservation is most important. |
|
676 * During driver activity, SmartSpeed should be enabled so performance is |
|
677 * maintained. |
|
678 **/ |
|
679 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) |
|
680 { |
|
681 u16 data = er32(POEMB); |
|
682 |
|
683 if (!active) { |
|
684 data &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
|
685 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
|
686 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || |
|
687 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { |
|
688 data |= E1000_PHY_CTRL_NOND0A_LPLU; |
|
689 } |
|
690 |
|
691 ew32(POEMB, data); |
|
692 return 0; |
|
693 } |
|
694 |
|
695 /** |
|
696 * e1000_acquire_nvm_82571 - Request for access to the EEPROM |
|
697 * @hw: pointer to the HW structure |
|
698 * |
|
699 * To gain access to the EEPROM, first we must obtain a hardware semaphore. |
|
700 * Then for non-82573 hardware, set the EEPROM access request bit and wait |
|
701 * for EEPROM access grant bit. If the access grant bit is not set, release |
|
702 * hardware semaphore. |
|
703 **/ |
|
704 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) |
|
705 { |
|
706 s32 ret_val; |
|
707 |
|
708 ret_val = e1000_get_hw_semaphore_82571(hw); |
|
709 if (ret_val) |
|
710 return ret_val; |
|
711 |
|
712 switch (hw->mac.type) { |
|
713 case e1000_82573: |
|
714 break; |
|
715 default: |
|
716 ret_val = e1000e_acquire_nvm(hw); |
|
717 break; |
|
718 } |
|
719 |
|
720 if (ret_val) |
|
721 e1000_put_hw_semaphore_82571(hw); |
|
722 |
|
723 return ret_val; |
|
724 } |
|
725 |
|
726 /** |
|
727 * e1000_release_nvm_82571 - Release exclusive access to EEPROM |
|
728 * @hw: pointer to the HW structure |
|
729 * |
|
730 * Stop any current commands to the EEPROM and clear the EEPROM request bit. |
|
731 **/ |
|
732 static void e1000_release_nvm_82571(struct e1000_hw *hw) |
|
733 { |
|
734 e1000e_release_nvm(hw); |
|
735 e1000_put_hw_semaphore_82571(hw); |
|
736 } |
|
737 |
|
738 /** |
|
739 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface |
|
740 * @hw: pointer to the HW structure |
|
741 * @offset: offset within the EEPROM to be written to |
|
742 * @words: number of words to write |
|
743 * @data: 16 bit word(s) to be written to the EEPROM |
|
744 * |
|
745 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. |
|
746 * |
|
747 * If e1000e_update_nvm_checksum is not called after this function, the |
|
748 * EEPROM will most likely contain an invalid checksum. |
|
749 **/ |
|
750 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, |
|
751 u16 *data) |
|
752 { |
|
753 s32 ret_val; |
|
754 |
|
755 switch (hw->mac.type) { |
|
756 case e1000_82573: |
|
757 case e1000_82574: |
|
758 case e1000_82583: |
|
759 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
|
760 break; |
|
761 case e1000_82571: |
|
762 case e1000_82572: |
|
763 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); |
|
764 break; |
|
765 default: |
|
766 ret_val = -E1000_ERR_NVM; |
|
767 break; |
|
768 } |
|
769 |
|
770 return ret_val; |
|
771 } |
|
772 |
|
773 /** |
|
774 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum |
|
775 * @hw: pointer to the HW structure |
|
776 * |
|
777 * Updates the EEPROM checksum by reading/adding each word of the EEPROM |
|
778 * up to the checksum. Then calculates the EEPROM checksum and writes the |
|
779 * value to the EEPROM. |
|
780 **/ |
|
781 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) |
|
782 { |
|
783 u32 eecd; |
|
784 s32 ret_val; |
|
785 u16 i; |
|
786 |
|
787 ret_val = e1000e_update_nvm_checksum_generic(hw); |
|
788 if (ret_val) |
|
789 return ret_val; |
|
790 |
|
791 /* |
|
792 * If our nvm is an EEPROM, then we're done |
|
793 * otherwise, commit the checksum to the flash NVM. |
|
794 */ |
|
795 if (hw->nvm.type != e1000_nvm_flash_hw) |
|
796 return 0; |
|
797 |
|
798 /* Check for pending operations. */ |
|
799 for (i = 0; i < E1000_FLASH_UPDATES; i++) { |
|
800 usleep_range(1000, 2000); |
|
801 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
|
802 break; |
|
803 } |
|
804 |
|
805 if (i == E1000_FLASH_UPDATES) |
|
806 return -E1000_ERR_NVM; |
|
807 |
|
808 /* Reset the firmware if using STM opcode. */ |
|
809 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { |
|
810 /* |
|
811 * The enabling of and the actual reset must be done |
|
812 * in two write cycles. |
|
813 */ |
|
814 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); |
|
815 e1e_flush(); |
|
816 ew32(HICR, E1000_HICR_FW_RESET); |
|
817 } |
|
818 |
|
819 /* Commit the write to flash */ |
|
820 eecd = er32(EECD) | E1000_EECD_FLUPD; |
|
821 ew32(EECD, eecd); |
|
822 |
|
823 for (i = 0; i < E1000_FLASH_UPDATES; i++) { |
|
824 usleep_range(1000, 2000); |
|
825 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) |
|
826 break; |
|
827 } |
|
828 |
|
829 if (i == E1000_FLASH_UPDATES) |
|
830 return -E1000_ERR_NVM; |
|
831 |
|
832 return 0; |
|
833 } |
|
834 |
|
835 /** |
|
836 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum |
|
837 * @hw: pointer to the HW structure |
|
838 * |
|
839 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
|
840 * and then verifies that the sum of the EEPROM is equal to 0xBABA. |
|
841 **/ |
|
842 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) |
|
843 { |
|
844 if (hw->nvm.type == e1000_nvm_flash_hw) |
|
845 e1000_fix_nvm_checksum_82571(hw); |
|
846 |
|
847 return e1000e_validate_nvm_checksum_generic(hw); |
|
848 } |
|
849 |
|
850 /** |
|
851 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon |
|
852 * @hw: pointer to the HW structure |
|
853 * @offset: offset within the EEPROM to be written to |
|
854 * @words: number of words to write |
|
855 * @data: 16 bit word(s) to be written to the EEPROM |
|
856 * |
|
857 * After checking for invalid values, poll the EEPROM to ensure the previous |
|
858 * command has completed before trying to write the next word. After write |
|
859 * poll for completion. |
|
860 * |
|
861 * If e1000e_update_nvm_checksum is not called after this function, the |
|
862 * EEPROM will most likely contain an invalid checksum. |
|
863 **/ |
|
864 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
|
865 u16 words, u16 *data) |
|
866 { |
|
867 struct e1000_nvm_info *nvm = &hw->nvm; |
|
868 u32 i, eewr = 0; |
|
869 s32 ret_val = 0; |
|
870 |
|
871 /* |
|
872 * A check for invalid values: offset too large, too many words, |
|
873 * and not enough words. |
|
874 */ |
|
875 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
|
876 (words == 0)) { |
|
877 e_dbg("nvm parameter(s) out of bounds\n"); |
|
878 return -E1000_ERR_NVM; |
|
879 } |
|
880 |
|
881 for (i = 0; i < words; i++) { |
|
882 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | |
|
883 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | |
|
884 E1000_NVM_RW_REG_START; |
|
885 |
|
886 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); |
|
887 if (ret_val) |
|
888 break; |
|
889 |
|
890 ew32(EEWR, eewr); |
|
891 |
|
892 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); |
|
893 if (ret_val) |
|
894 break; |
|
895 } |
|
896 |
|
897 return ret_val; |
|
898 } |
|
899 |
|
900 /** |
|
901 * e1000_get_cfg_done_82571 - Poll for configuration done |
|
902 * @hw: pointer to the HW structure |
|
903 * |
|
904 * Reads the management control register for the config done bit to be set. |
|
905 **/ |
|
906 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) |
|
907 { |
|
908 s32 timeout = PHY_CFG_TIMEOUT; |
|
909 |
|
910 while (timeout) { |
|
911 if (er32(EEMNGCTL) & |
|
912 E1000_NVM_CFG_DONE_PORT_0) |
|
913 break; |
|
914 usleep_range(1000, 2000); |
|
915 timeout--; |
|
916 } |
|
917 if (!timeout) { |
|
918 e_dbg("MNG configuration cycle has not completed.\n"); |
|
919 return -E1000_ERR_RESET; |
|
920 } |
|
921 |
|
922 return 0; |
|
923 } |
|
924 |
|
925 /** |
|
926 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state |
|
927 * @hw: pointer to the HW structure |
|
928 * @active: true to enable LPLU, false to disable |
|
929 * |
|
930 * Sets the LPLU D0 state according to the active flag. When activating LPLU |
|
931 * this function also disables smart speed and vice versa. LPLU will not be |
|
932 * activated unless the device autonegotiation advertisement meets standards |
|
933 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function |
|
934 * pointer entry point only called by PHY setup routines. |
|
935 **/ |
|
936 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) |
|
937 { |
|
938 struct e1000_phy_info *phy = &hw->phy; |
|
939 s32 ret_val; |
|
940 u16 data; |
|
941 |
|
942 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
|
943 if (ret_val) |
|
944 return ret_val; |
|
945 |
|
946 if (active) { |
|
947 data |= IGP02E1000_PM_D0_LPLU; |
|
948 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
949 if (ret_val) |
|
950 return ret_val; |
|
951 |
|
952 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
953 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
954 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
955 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
956 if (ret_val) |
|
957 return ret_val; |
|
958 } else { |
|
959 data &= ~IGP02E1000_PM_D0_LPLU; |
|
960 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
961 /* |
|
962 * LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
963 * during Dx states where the power conservation is most |
|
964 * important. During driver activity we should enable |
|
965 * SmartSpeed, so performance is maintained. |
|
966 */ |
|
967 if (phy->smart_speed == e1000_smart_speed_on) { |
|
968 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
969 &data); |
|
970 if (ret_val) |
|
971 return ret_val; |
|
972 |
|
973 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
974 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
975 data); |
|
976 if (ret_val) |
|
977 return ret_val; |
|
978 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
979 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
980 &data); |
|
981 if (ret_val) |
|
982 return ret_val; |
|
983 |
|
984 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
985 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
986 data); |
|
987 if (ret_val) |
|
988 return ret_val; |
|
989 } |
|
990 } |
|
991 |
|
992 return 0; |
|
993 } |
|
994 |
|
995 /** |
|
996 * e1000_reset_hw_82571 - Reset hardware |
|
997 * @hw: pointer to the HW structure |
|
998 * |
|
999 * This resets the hardware into a known state. |
|
1000 **/ |
|
1001 static s32 e1000_reset_hw_82571(struct e1000_hw *hw) |
|
1002 { |
|
1003 u32 ctrl, ctrl_ext; |
|
1004 s32 ret_val; |
|
1005 |
|
1006 /* |
|
1007 * Prevent the PCI-E bus from sticking if there is no TLP connection |
|
1008 * on the last TLP read/write transaction when MAC is reset. |
|
1009 */ |
|
1010 ret_val = e1000e_disable_pcie_master(hw); |
|
1011 if (ret_val) |
|
1012 e_dbg("PCI-E Master disable polling has failed.\n"); |
|
1013 |
|
1014 e_dbg("Masking off all interrupts\n"); |
|
1015 ew32(IMC, 0xffffffff); |
|
1016 |
|
1017 ew32(RCTL, 0); |
|
1018 ew32(TCTL, E1000_TCTL_PSP); |
|
1019 e1e_flush(); |
|
1020 |
|
1021 usleep_range(10000, 20000); |
|
1022 |
|
1023 /* |
|
1024 * Must acquire the MDIO ownership before MAC reset. |
|
1025 * Ownership defaults to firmware after a reset. |
|
1026 */ |
|
1027 switch (hw->mac.type) { |
|
1028 case e1000_82573: |
|
1029 ret_val = e1000_get_hw_semaphore_82573(hw); |
|
1030 break; |
|
1031 case e1000_82574: |
|
1032 case e1000_82583: |
|
1033 ret_val = e1000_get_hw_semaphore_82574(hw); |
|
1034 break; |
|
1035 default: |
|
1036 break; |
|
1037 } |
|
1038 if (ret_val) |
|
1039 e_dbg("Cannot acquire MDIO ownership\n"); |
|
1040 |
|
1041 ctrl = er32(CTRL); |
|
1042 |
|
1043 e_dbg("Issuing a global reset to MAC\n"); |
|
1044 ew32(CTRL, ctrl | E1000_CTRL_RST); |
|
1045 |
|
1046 /* Must release MDIO ownership and mutex after MAC reset. */ |
|
1047 switch (hw->mac.type) { |
|
1048 case e1000_82574: |
|
1049 case e1000_82583: |
|
1050 e1000_put_hw_semaphore_82574(hw); |
|
1051 break; |
|
1052 default: |
|
1053 break; |
|
1054 } |
|
1055 |
|
1056 if (hw->nvm.type == e1000_nvm_flash_hw) { |
|
1057 udelay(10); |
|
1058 ctrl_ext = er32(CTRL_EXT); |
|
1059 ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
|
1060 ew32(CTRL_EXT, ctrl_ext); |
|
1061 e1e_flush(); |
|
1062 } |
|
1063 |
|
1064 ret_val = e1000e_get_auto_rd_done(hw); |
|
1065 if (ret_val) |
|
1066 /* We don't want to continue accessing MAC registers. */ |
|
1067 return ret_val; |
|
1068 |
|
1069 /* |
|
1070 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. |
|
1071 * Need to wait for Phy configuration completion before accessing |
|
1072 * NVM and Phy. |
|
1073 */ |
|
1074 |
|
1075 switch (hw->mac.type) { |
|
1076 case e1000_82573: |
|
1077 case e1000_82574: |
|
1078 case e1000_82583: |
|
1079 msleep(25); |
|
1080 break; |
|
1081 default: |
|
1082 break; |
|
1083 } |
|
1084 |
|
1085 /* Clear any pending interrupt events. */ |
|
1086 ew32(IMC, 0xffffffff); |
|
1087 er32(ICR); |
|
1088 |
|
1089 if (hw->mac.type == e1000_82571) { |
|
1090 /* Install any alternate MAC address into RAR0 */ |
|
1091 ret_val = e1000_check_alt_mac_addr_generic(hw); |
|
1092 if (ret_val) |
|
1093 return ret_val; |
|
1094 |
|
1095 e1000e_set_laa_state_82571(hw, true); |
|
1096 } |
|
1097 |
|
1098 /* Reinitialize the 82571 serdes link state machine */ |
|
1099 if (hw->phy.media_type == e1000_media_type_internal_serdes) |
|
1100 hw->mac.serdes_link_state = e1000_serdes_link_down; |
|
1101 |
|
1102 return 0; |
|
1103 } |
|
1104 |
|
1105 /** |
|
1106 * e1000_init_hw_82571 - Initialize hardware |
|
1107 * @hw: pointer to the HW structure |
|
1108 * |
|
1109 * This inits the hardware readying it for operation. |
|
1110 **/ |
|
1111 static s32 e1000_init_hw_82571(struct e1000_hw *hw) |
|
1112 { |
|
1113 struct e1000_mac_info *mac = &hw->mac; |
|
1114 u32 reg_data; |
|
1115 s32 ret_val; |
|
1116 u16 i, rar_count = mac->rar_entry_count; |
|
1117 |
|
1118 e1000_initialize_hw_bits_82571(hw); |
|
1119 |
|
1120 /* Initialize identification LED */ |
|
1121 ret_val = mac->ops.id_led_init(hw); |
|
1122 if (ret_val) |
|
1123 e_dbg("Error initializing identification LED\n"); |
|
1124 /* This is not fatal and we should not stop init due to this */ |
|
1125 |
|
1126 /* Disabling VLAN filtering */ |
|
1127 e_dbg("Initializing the IEEE VLAN\n"); |
|
1128 mac->ops.clear_vfta(hw); |
|
1129 |
|
1130 /* Setup the receive address. */ |
|
1131 /* |
|
1132 * If, however, a locally administered address was assigned to the |
|
1133 * 82571, we must reserve a RAR for it to work around an issue where |
|
1134 * resetting one port will reload the MAC on the other port. |
|
1135 */ |
|
1136 if (e1000e_get_laa_state_82571(hw)) |
|
1137 rar_count--; |
|
1138 e1000e_init_rx_addrs(hw, rar_count); |
|
1139 |
|
1140 /* Zero out the Multicast HASH table */ |
|
1141 e_dbg("Zeroing the MTA\n"); |
|
1142 for (i = 0; i < mac->mta_reg_count; i++) |
|
1143 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); |
|
1144 |
|
1145 /* Setup link and flow control */ |
|
1146 ret_val = mac->ops.setup_link(hw); |
|
1147 |
|
1148 /* Set the transmit descriptor write-back policy */ |
|
1149 reg_data = er32(TXDCTL(0)); |
|
1150 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
1151 E1000_TXDCTL_FULL_TX_DESC_WB | |
|
1152 E1000_TXDCTL_COUNT_DESC; |
|
1153 ew32(TXDCTL(0), reg_data); |
|
1154 |
|
1155 /* ...for both queues. */ |
|
1156 switch (mac->type) { |
|
1157 case e1000_82573: |
|
1158 e1000e_enable_tx_pkt_filtering(hw); |
|
1159 /* fall through */ |
|
1160 case e1000_82574: |
|
1161 case e1000_82583: |
|
1162 reg_data = er32(GCR); |
|
1163 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
|
1164 ew32(GCR, reg_data); |
|
1165 break; |
|
1166 default: |
|
1167 reg_data = er32(TXDCTL(1)); |
|
1168 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
|
1169 E1000_TXDCTL_FULL_TX_DESC_WB | |
|
1170 E1000_TXDCTL_COUNT_DESC; |
|
1171 ew32(TXDCTL(1), reg_data); |
|
1172 break; |
|
1173 } |
|
1174 |
|
1175 /* |
|
1176 * Clear all of the statistics registers (clear on read). It is |
|
1177 * important that we do this after we have tried to establish link |
|
1178 * because the symbol error count will increment wildly if there |
|
1179 * is no link. |
|
1180 */ |
|
1181 e1000_clear_hw_cntrs_82571(hw); |
|
1182 |
|
1183 return ret_val; |
|
1184 } |
|
1185 |
|
1186 /** |
|
1187 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits |
|
1188 * @hw: pointer to the HW structure |
|
1189 * |
|
1190 * Initializes required hardware-dependent bits needed for normal operation. |
|
1191 **/ |
|
1192 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) |
|
1193 { |
|
1194 u32 reg; |
|
1195 |
|
1196 /* Transmit Descriptor Control 0 */ |
|
1197 reg = er32(TXDCTL(0)); |
|
1198 reg |= (1 << 22); |
|
1199 ew32(TXDCTL(0), reg); |
|
1200 |
|
1201 /* Transmit Descriptor Control 1 */ |
|
1202 reg = er32(TXDCTL(1)); |
|
1203 reg |= (1 << 22); |
|
1204 ew32(TXDCTL(1), reg); |
|
1205 |
|
1206 /* Transmit Arbitration Control 0 */ |
|
1207 reg = er32(TARC(0)); |
|
1208 reg &= ~(0xF << 27); /* 30:27 */ |
|
1209 switch (hw->mac.type) { |
|
1210 case e1000_82571: |
|
1211 case e1000_82572: |
|
1212 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); |
|
1213 break; |
|
1214 case e1000_82574: |
|
1215 case e1000_82583: |
|
1216 reg |= (1 << 26); |
|
1217 break; |
|
1218 default: |
|
1219 break; |
|
1220 } |
|
1221 ew32(TARC(0), reg); |
|
1222 |
|
1223 /* Transmit Arbitration Control 1 */ |
|
1224 reg = er32(TARC(1)); |
|
1225 switch (hw->mac.type) { |
|
1226 case e1000_82571: |
|
1227 case e1000_82572: |
|
1228 reg &= ~((1 << 29) | (1 << 30)); |
|
1229 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); |
|
1230 if (er32(TCTL) & E1000_TCTL_MULR) |
|
1231 reg &= ~(1 << 28); |
|
1232 else |
|
1233 reg |= (1 << 28); |
|
1234 ew32(TARC(1), reg); |
|
1235 break; |
|
1236 default: |
|
1237 break; |
|
1238 } |
|
1239 |
|
1240 /* Device Control */ |
|
1241 switch (hw->mac.type) { |
|
1242 case e1000_82573: |
|
1243 case e1000_82574: |
|
1244 case e1000_82583: |
|
1245 reg = er32(CTRL); |
|
1246 reg &= ~(1 << 29); |
|
1247 ew32(CTRL, reg); |
|
1248 break; |
|
1249 default: |
|
1250 break; |
|
1251 } |
|
1252 |
|
1253 /* Extended Device Control */ |
|
1254 switch (hw->mac.type) { |
|
1255 case e1000_82573: |
|
1256 case e1000_82574: |
|
1257 case e1000_82583: |
|
1258 reg = er32(CTRL_EXT); |
|
1259 reg &= ~(1 << 23); |
|
1260 reg |= (1 << 22); |
|
1261 ew32(CTRL_EXT, reg); |
|
1262 break; |
|
1263 default: |
|
1264 break; |
|
1265 } |
|
1266 |
|
1267 if (hw->mac.type == e1000_82571) { |
|
1268 reg = er32(PBA_ECC); |
|
1269 reg |= E1000_PBA_ECC_CORR_EN; |
|
1270 ew32(PBA_ECC, reg); |
|
1271 } |
|
1272 |
|
1273 /* |
|
1274 * Workaround for hardware errata. |
|
1275 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 |
|
1276 */ |
|
1277 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { |
|
1278 reg = er32(CTRL_EXT); |
|
1279 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; |
|
1280 ew32(CTRL_EXT, reg); |
|
1281 } |
|
1282 |
|
1283 /* PCI-Ex Control Registers */ |
|
1284 switch (hw->mac.type) { |
|
1285 case e1000_82574: |
|
1286 case e1000_82583: |
|
1287 reg = er32(GCR); |
|
1288 reg |= (1 << 22); |
|
1289 ew32(GCR, reg); |
|
1290 |
|
1291 /* |
|
1292 * Workaround for hardware errata. |
|
1293 * apply workaround for hardware errata documented in errata |
|
1294 * docs Fixes issue where some error prone or unreliable PCIe |
|
1295 * completions are occurring, particularly with ASPM enabled. |
|
1296 * Without fix, issue can cause Tx timeouts. |
|
1297 */ |
|
1298 reg = er32(GCR2); |
|
1299 reg |= 1; |
|
1300 ew32(GCR2, reg); |
|
1301 break; |
|
1302 default: |
|
1303 break; |
|
1304 } |
|
1305 } |
|
1306 |
|
1307 /** |
|
1308 * e1000_clear_vfta_82571 - Clear VLAN filter table |
|
1309 * @hw: pointer to the HW structure |
|
1310 * |
|
1311 * Clears the register array which contains the VLAN filter table by |
|
1312 * setting all the values to 0. |
|
1313 **/ |
|
1314 static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
|
1315 { |
|
1316 u32 offset; |
|
1317 u32 vfta_value = 0; |
|
1318 u32 vfta_offset = 0; |
|
1319 u32 vfta_bit_in_reg = 0; |
|
1320 |
|
1321 switch (hw->mac.type) { |
|
1322 case e1000_82573: |
|
1323 case e1000_82574: |
|
1324 case e1000_82583: |
|
1325 if (hw->mng_cookie.vlan_id != 0) { |
|
1326 /* |
|
1327 * The VFTA is a 4096b bit-field, each identifying |
|
1328 * a single VLAN ID. The following operations |
|
1329 * determine which 32b entry (i.e. offset) into the |
|
1330 * array we want to set the VLAN ID (i.e. bit) of |
|
1331 * the manageability unit. |
|
1332 */ |
|
1333 vfta_offset = (hw->mng_cookie.vlan_id >> |
|
1334 E1000_VFTA_ENTRY_SHIFT) & |
|
1335 E1000_VFTA_ENTRY_MASK; |
|
1336 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
|
1337 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
|
1338 } |
|
1339 break; |
|
1340 default: |
|
1341 break; |
|
1342 } |
|
1343 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
|
1344 /* |
|
1345 * If the offset we want to clear is the same offset of the |
|
1346 * manageability VLAN ID, then clear all bits except that of |
|
1347 * the manageability unit. |
|
1348 */ |
|
1349 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
|
1350 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); |
|
1351 e1e_flush(); |
|
1352 } |
|
1353 } |
|
1354 |
|
1355 /** |
|
1356 * e1000_check_mng_mode_82574 - Check manageability is enabled |
|
1357 * @hw: pointer to the HW structure |
|
1358 * |
|
1359 * Reads the NVM Initialization Control Word 2 and returns true |
|
1360 * (>0) if any manageability is enabled, else false (0). |
|
1361 **/ |
|
1362 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) |
|
1363 { |
|
1364 u16 data; |
|
1365 |
|
1366 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); |
|
1367 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; |
|
1368 } |
|
1369 |
|
1370 /** |
|
1371 * e1000_led_on_82574 - Turn LED on |
|
1372 * @hw: pointer to the HW structure |
|
1373 * |
|
1374 * Turn LED on. |
|
1375 **/ |
|
1376 static s32 e1000_led_on_82574(struct e1000_hw *hw) |
|
1377 { |
|
1378 u32 ctrl; |
|
1379 u32 i; |
|
1380 |
|
1381 ctrl = hw->mac.ledctl_mode2; |
|
1382 if (!(E1000_STATUS_LU & er32(STATUS))) { |
|
1383 /* |
|
1384 * If no link, then turn LED on by setting the invert bit |
|
1385 * for each LED that's "on" (0x0E) in ledctl_mode2. |
|
1386 */ |
|
1387 for (i = 0; i < 4; i++) |
|
1388 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
|
1389 E1000_LEDCTL_MODE_LED_ON) |
|
1390 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); |
|
1391 } |
|
1392 ew32(LEDCTL, ctrl); |
|
1393 |
|
1394 return 0; |
|
1395 } |
|
1396 |
|
1397 /** |
|
1398 * e1000_check_phy_82574 - check 82574 phy hung state |
|
1399 * @hw: pointer to the HW structure |
|
1400 * |
|
1401 * Returns whether phy is hung or not |
|
1402 **/ |
|
1403 bool e1000_check_phy_82574(struct e1000_hw *hw) |
|
1404 { |
|
1405 u16 status_1kbt = 0; |
|
1406 u16 receive_errors = 0; |
|
1407 s32 ret_val = 0; |
|
1408 |
|
1409 /* |
|
1410 * Read PHY Receive Error counter first, if its is max - all F's then |
|
1411 * read the Base1000T status register If both are max then PHY is hung. |
|
1412 */ |
|
1413 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); |
|
1414 if (ret_val) |
|
1415 return false; |
|
1416 if (receive_errors == E1000_RECEIVE_ERROR_MAX) { |
|
1417 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); |
|
1418 if (ret_val) |
|
1419 return false; |
|
1420 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == |
|
1421 E1000_IDLE_ERROR_COUNT_MASK) |
|
1422 return true; |
|
1423 } |
|
1424 |
|
1425 return false; |
|
1426 } |
|
1427 |
|
1428 /** |
|
1429 * e1000_setup_link_82571 - Setup flow control and link settings |
|
1430 * @hw: pointer to the HW structure |
|
1431 * |
|
1432 * Determines which flow control settings to use, then configures flow |
|
1433 * control. Calls the appropriate media-specific link configuration |
|
1434 * function. Assuming the adapter has a valid link partner, a valid link |
|
1435 * should be established. Assumes the hardware has previously been reset |
|
1436 * and the transmitter and receiver are not enabled. |
|
1437 **/ |
|
1438 static s32 e1000_setup_link_82571(struct e1000_hw *hw) |
|
1439 { |
|
1440 /* |
|
1441 * 82573 does not have a word in the NVM to determine |
|
1442 * the default flow control setting, so we explicitly |
|
1443 * set it to full. |
|
1444 */ |
|
1445 switch (hw->mac.type) { |
|
1446 case e1000_82573: |
|
1447 case e1000_82574: |
|
1448 case e1000_82583: |
|
1449 if (hw->fc.requested_mode == e1000_fc_default) |
|
1450 hw->fc.requested_mode = e1000_fc_full; |
|
1451 break; |
|
1452 default: |
|
1453 break; |
|
1454 } |
|
1455 |
|
1456 return e1000e_setup_link_generic(hw); |
|
1457 } |
|
1458 |
|
1459 /** |
|
1460 * e1000_setup_copper_link_82571 - Configure copper link settings |
|
1461 * @hw: pointer to the HW structure |
|
1462 * |
|
1463 * Configures the link for auto-neg or forced speed and duplex. Then we check |
|
1464 * for link, once link is established calls to configure collision distance |
|
1465 * and flow control are called. |
|
1466 **/ |
|
1467 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) |
|
1468 { |
|
1469 u32 ctrl; |
|
1470 s32 ret_val; |
|
1471 |
|
1472 ctrl = er32(CTRL); |
|
1473 ctrl |= E1000_CTRL_SLU; |
|
1474 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1475 ew32(CTRL, ctrl); |
|
1476 |
|
1477 switch (hw->phy.type) { |
|
1478 case e1000_phy_m88: |
|
1479 case e1000_phy_bm: |
|
1480 ret_val = e1000e_copper_link_setup_m88(hw); |
|
1481 break; |
|
1482 case e1000_phy_igp_2: |
|
1483 ret_val = e1000e_copper_link_setup_igp(hw); |
|
1484 break; |
|
1485 default: |
|
1486 return -E1000_ERR_PHY; |
|
1487 break; |
|
1488 } |
|
1489 |
|
1490 if (ret_val) |
|
1491 return ret_val; |
|
1492 |
|
1493 return e1000e_setup_copper_link(hw); |
|
1494 } |
|
1495 |
|
1496 /** |
|
1497 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes |
|
1498 * @hw: pointer to the HW structure |
|
1499 * |
|
1500 * Configures collision distance and flow control for fiber and serdes links. |
|
1501 * Upon successful setup, poll for link. |
|
1502 **/ |
|
1503 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) |
|
1504 { |
|
1505 switch (hw->mac.type) { |
|
1506 case e1000_82571: |
|
1507 case e1000_82572: |
|
1508 /* |
|
1509 * If SerDes loopback mode is entered, there is no form |
|
1510 * of reset to take the adapter out of that mode. So we |
|
1511 * have to explicitly take the adapter out of loopback |
|
1512 * mode. This prevents drivers from twiddling their thumbs |
|
1513 * if another tool failed to take it out of loopback mode. |
|
1514 */ |
|
1515 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
|
1516 break; |
|
1517 default: |
|
1518 break; |
|
1519 } |
|
1520 |
|
1521 return e1000e_setup_fiber_serdes_link(hw); |
|
1522 } |
|
1523 |
|
1524 /** |
|
1525 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) |
|
1526 * @hw: pointer to the HW structure |
|
1527 * |
|
1528 * Reports the link state as up or down. |
|
1529 * |
|
1530 * If autonegotiation is supported by the link partner, the link state is |
|
1531 * determined by the result of autonegotiation. This is the most likely case. |
|
1532 * If autonegotiation is not supported by the link partner, and the link |
|
1533 * has a valid signal, force the link up. |
|
1534 * |
|
1535 * The link state is represented internally here by 4 states: |
|
1536 * |
|
1537 * 1) down |
|
1538 * 2) autoneg_progress |
|
1539 * 3) autoneg_complete (the link successfully autonegotiated) |
|
1540 * 4) forced_up (the link has been forced up, it did not autonegotiate) |
|
1541 * |
|
1542 **/ |
|
1543 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
|
1544 { |
|
1545 struct e1000_mac_info *mac = &hw->mac; |
|
1546 u32 rxcw; |
|
1547 u32 ctrl; |
|
1548 u32 status; |
|
1549 u32 txcw; |
|
1550 u32 i; |
|
1551 s32 ret_val = 0; |
|
1552 |
|
1553 ctrl = er32(CTRL); |
|
1554 status = er32(STATUS); |
|
1555 rxcw = er32(RXCW); |
|
1556 /* SYNCH bit and IV bit are sticky */ |
|
1557 udelay(10); |
|
1558 rxcw = er32(RXCW); |
|
1559 |
|
1560 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { |
|
1561 |
|
1562 /* Receiver is synchronized with no invalid bits. */ |
|
1563 switch (mac->serdes_link_state) { |
|
1564 case e1000_serdes_link_autoneg_complete: |
|
1565 if (!(status & E1000_STATUS_LU)) { |
|
1566 /* |
|
1567 * We have lost link, retry autoneg before |
|
1568 * reporting link failure |
|
1569 */ |
|
1570 mac->serdes_link_state = |
|
1571 e1000_serdes_link_autoneg_progress; |
|
1572 mac->serdes_has_link = false; |
|
1573 e_dbg("AN_UP -> AN_PROG\n"); |
|
1574 } else { |
|
1575 mac->serdes_has_link = true; |
|
1576 } |
|
1577 break; |
|
1578 |
|
1579 case e1000_serdes_link_forced_up: |
|
1580 /* |
|
1581 * If we are receiving /C/ ordered sets, re-enable |
|
1582 * auto-negotiation in the TXCW register and disable |
|
1583 * forced link in the Device Control register in an |
|
1584 * attempt to auto-negotiate with our link partner. |
|
1585 */ |
|
1586 if (rxcw & E1000_RXCW_C) { |
|
1587 /* Enable autoneg, and unforce link up */ |
|
1588 ew32(TXCW, mac->txcw); |
|
1589 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
1590 mac->serdes_link_state = |
|
1591 e1000_serdes_link_autoneg_progress; |
|
1592 mac->serdes_has_link = false; |
|
1593 e_dbg("FORCED_UP -> AN_PROG\n"); |
|
1594 } else { |
|
1595 mac->serdes_has_link = true; |
|
1596 } |
|
1597 break; |
|
1598 |
|
1599 case e1000_serdes_link_autoneg_progress: |
|
1600 if (rxcw & E1000_RXCW_C) { |
|
1601 /* |
|
1602 * We received /C/ ordered sets, meaning the |
|
1603 * link partner has autonegotiated, and we can |
|
1604 * trust the Link Up (LU) status bit. |
|
1605 */ |
|
1606 if (status & E1000_STATUS_LU) { |
|
1607 mac->serdes_link_state = |
|
1608 e1000_serdes_link_autoneg_complete; |
|
1609 e_dbg("AN_PROG -> AN_UP\n"); |
|
1610 mac->serdes_has_link = true; |
|
1611 } else { |
|
1612 /* Autoneg completed, but failed. */ |
|
1613 mac->serdes_link_state = |
|
1614 e1000_serdes_link_down; |
|
1615 e_dbg("AN_PROG -> DOWN\n"); |
|
1616 } |
|
1617 } else { |
|
1618 /* |
|
1619 * The link partner did not autoneg. |
|
1620 * Force link up and full duplex, and change |
|
1621 * state to forced. |
|
1622 */ |
|
1623 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
|
1624 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
|
1625 ew32(CTRL, ctrl); |
|
1626 |
|
1627 /* Configure Flow Control after link up. */ |
|
1628 ret_val = e1000e_config_fc_after_link_up(hw); |
|
1629 if (ret_val) { |
|
1630 e_dbg("Error config flow control\n"); |
|
1631 break; |
|
1632 } |
|
1633 mac->serdes_link_state = |
|
1634 e1000_serdes_link_forced_up; |
|
1635 mac->serdes_has_link = true; |
|
1636 e_dbg("AN_PROG -> FORCED_UP\n"); |
|
1637 } |
|
1638 break; |
|
1639 |
|
1640 case e1000_serdes_link_down: |
|
1641 default: |
|
1642 /* |
|
1643 * The link was down but the receiver has now gained |
|
1644 * valid sync, so lets see if we can bring the link |
|
1645 * up. |
|
1646 */ |
|
1647 ew32(TXCW, mac->txcw); |
|
1648 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
|
1649 mac->serdes_link_state = |
|
1650 e1000_serdes_link_autoneg_progress; |
|
1651 mac->serdes_has_link = false; |
|
1652 e_dbg("DOWN -> AN_PROG\n"); |
|
1653 break; |
|
1654 } |
|
1655 } else { |
|
1656 if (!(rxcw & E1000_RXCW_SYNCH)) { |
|
1657 mac->serdes_has_link = false; |
|
1658 mac->serdes_link_state = e1000_serdes_link_down; |
|
1659 e_dbg("ANYSTATE -> DOWN\n"); |
|
1660 } else { |
|
1661 /* |
|
1662 * Check several times, if Sync and Config |
|
1663 * both are consistently 1 then simply ignore |
|
1664 * the Invalid bit and restart Autoneg |
|
1665 */ |
|
1666 for (i = 0; i < AN_RETRY_COUNT; i++) { |
|
1667 udelay(10); |
|
1668 rxcw = er32(RXCW); |
|
1669 if ((rxcw & E1000_RXCW_IV) && |
|
1670 !((rxcw & E1000_RXCW_SYNCH) && |
|
1671 (rxcw & E1000_RXCW_C))) { |
|
1672 mac->serdes_has_link = false; |
|
1673 mac->serdes_link_state = |
|
1674 e1000_serdes_link_down; |
|
1675 e_dbg("ANYSTATE -> DOWN\n"); |
|
1676 break; |
|
1677 } |
|
1678 } |
|
1679 |
|
1680 if (i == AN_RETRY_COUNT) { |
|
1681 txcw = er32(TXCW); |
|
1682 txcw |= E1000_TXCW_ANE; |
|
1683 ew32(TXCW, txcw); |
|
1684 mac->serdes_link_state = |
|
1685 e1000_serdes_link_autoneg_progress; |
|
1686 mac->serdes_has_link = false; |
|
1687 e_dbg("ANYSTATE -> AN_PROG\n"); |
|
1688 } |
|
1689 } |
|
1690 } |
|
1691 |
|
1692 return ret_val; |
|
1693 } |
|
1694 |
|
1695 /** |
|
1696 * e1000_valid_led_default_82571 - Verify a valid default LED config |
|
1697 * @hw: pointer to the HW structure |
|
1698 * @data: pointer to the NVM (EEPROM) |
|
1699 * |
|
1700 * Read the EEPROM for the current default LED configuration. If the |
|
1701 * LED configuration is not valid, set to a valid LED configuration. |
|
1702 **/ |
|
1703 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) |
|
1704 { |
|
1705 s32 ret_val; |
|
1706 |
|
1707 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
|
1708 if (ret_val) { |
|
1709 e_dbg("NVM Read Error\n"); |
|
1710 return ret_val; |
|
1711 } |
|
1712 |
|
1713 switch (hw->mac.type) { |
|
1714 case e1000_82573: |
|
1715 case e1000_82574: |
|
1716 case e1000_82583: |
|
1717 if (*data == ID_LED_RESERVED_F746) |
|
1718 *data = ID_LED_DEFAULT_82573; |
|
1719 break; |
|
1720 default: |
|
1721 if (*data == ID_LED_RESERVED_0000 || |
|
1722 *data == ID_LED_RESERVED_FFFF) |
|
1723 *data = ID_LED_DEFAULT; |
|
1724 break; |
|
1725 } |
|
1726 |
|
1727 return 0; |
|
1728 } |
|
1729 |
|
1730 /** |
|
1731 * e1000e_get_laa_state_82571 - Get locally administered address state |
|
1732 * @hw: pointer to the HW structure |
|
1733 * |
|
1734 * Retrieve and return the current locally administered address state. |
|
1735 **/ |
|
1736 bool e1000e_get_laa_state_82571(struct e1000_hw *hw) |
|
1737 { |
|
1738 if (hw->mac.type != e1000_82571) |
|
1739 return false; |
|
1740 |
|
1741 return hw->dev_spec.e82571.laa_is_present; |
|
1742 } |
|
1743 |
|
1744 /** |
|
1745 * e1000e_set_laa_state_82571 - Set locally administered address state |
|
1746 * @hw: pointer to the HW structure |
|
1747 * @state: enable/disable locally administered address |
|
1748 * |
|
1749 * Enable/Disable the current locally administered address state. |
|
1750 **/ |
|
1751 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) |
|
1752 { |
|
1753 if (hw->mac.type != e1000_82571) |
|
1754 return; |
|
1755 |
|
1756 hw->dev_spec.e82571.laa_is_present = state; |
|
1757 |
|
1758 /* If workaround is activated... */ |
|
1759 if (state) |
|
1760 /* |
|
1761 * Hold a copy of the LAA in RAR[14] This is done so that |
|
1762 * between the time RAR[0] gets clobbered and the time it |
|
1763 * gets fixed, the actual LAA is in one of the RARs and no |
|
1764 * incoming packets directed to this port are dropped. |
|
1765 * Eventually the LAA will be in RAR[0] and RAR[14]. |
|
1766 */ |
|
1767 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); |
|
1768 } |
|
1769 |
|
1770 /** |
|
1771 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum |
|
1772 * @hw: pointer to the HW structure |
|
1773 * |
|
1774 * Verifies that the EEPROM has completed the update. After updating the |
|
1775 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If |
|
1776 * the checksum fix is not implemented, we need to set the bit and update |
|
1777 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, |
|
1778 * we need to return bad checksum. |
|
1779 **/ |
|
1780 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) |
|
1781 { |
|
1782 struct e1000_nvm_info *nvm = &hw->nvm; |
|
1783 s32 ret_val; |
|
1784 u16 data; |
|
1785 |
|
1786 if (nvm->type != e1000_nvm_flash_hw) |
|
1787 return 0; |
|
1788 |
|
1789 /* |
|
1790 * Check bit 4 of word 10h. If it is 0, firmware is done updating |
|
1791 * 10h-12h. Checksum may need to be fixed. |
|
1792 */ |
|
1793 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); |
|
1794 if (ret_val) |
|
1795 return ret_val; |
|
1796 |
|
1797 if (!(data & 0x10)) { |
|
1798 /* |
|
1799 * Read 0x23 and check bit 15. This bit is a 1 |
|
1800 * when the checksum has already been fixed. If |
|
1801 * the checksum is still wrong and this bit is a |
|
1802 * 1, we need to return bad checksum. Otherwise, |
|
1803 * we need to set this bit to a 1 and update the |
|
1804 * checksum. |
|
1805 */ |
|
1806 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); |
|
1807 if (ret_val) |
|
1808 return ret_val; |
|
1809 |
|
1810 if (!(data & 0x8000)) { |
|
1811 data |= 0x8000; |
|
1812 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); |
|
1813 if (ret_val) |
|
1814 return ret_val; |
|
1815 ret_val = e1000e_update_nvm_checksum(hw); |
|
1816 } |
|
1817 } |
|
1818 |
|
1819 return 0; |
|
1820 } |
|
1821 |
|
1822 /** |
|
1823 * e1000_read_mac_addr_82571 - Read device MAC address |
|
1824 * @hw: pointer to the HW structure |
|
1825 **/ |
|
1826 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) |
|
1827 { |
|
1828 if (hw->mac.type == e1000_82571) { |
|
1829 s32 ret_val = 0; |
|
1830 |
|
1831 /* |
|
1832 * If there's an alternate MAC address place it in RAR0 |
|
1833 * so that it will override the Si installed default perm |
|
1834 * address. |
|
1835 */ |
|
1836 ret_val = e1000_check_alt_mac_addr_generic(hw); |
|
1837 if (ret_val) |
|
1838 return ret_val; |
|
1839 } |
|
1840 |
|
1841 return e1000_read_mac_addr_generic(hw); |
|
1842 } |
|
1843 |
|
1844 /** |
|
1845 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down |
|
1846 * @hw: pointer to the HW structure |
|
1847 * |
|
1848 * In the case of a PHY power down to save power, or to turn off link during a |
|
1849 * driver unload, or wake on lan is not enabled, remove the link. |
|
1850 **/ |
|
1851 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) |
|
1852 { |
|
1853 struct e1000_phy_info *phy = &hw->phy; |
|
1854 struct e1000_mac_info *mac = &hw->mac; |
|
1855 |
|
1856 if (!phy->ops.check_reset_block) |
|
1857 return; |
|
1858 |
|
1859 /* If the management interface is not enabled, then power down */ |
|
1860 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) |
|
1861 e1000_power_down_phy_copper(hw); |
|
1862 } |
|
1863 |
|
1864 /** |
|
1865 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters |
|
1866 * @hw: pointer to the HW structure |
|
1867 * |
|
1868 * Clears the hardware counters by reading the counter registers. |
|
1869 **/ |
|
1870 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) |
|
1871 { |
|
1872 e1000e_clear_hw_cntrs_base(hw); |
|
1873 |
|
1874 er32(PRC64); |
|
1875 er32(PRC127); |
|
1876 er32(PRC255); |
|
1877 er32(PRC511); |
|
1878 er32(PRC1023); |
|
1879 er32(PRC1522); |
|
1880 er32(PTC64); |
|
1881 er32(PTC127); |
|
1882 er32(PTC255); |
|
1883 er32(PTC511); |
|
1884 er32(PTC1023); |
|
1885 er32(PTC1522); |
|
1886 |
|
1887 er32(ALGNERRC); |
|
1888 er32(RXERRC); |
|
1889 er32(TNCRS); |
|
1890 er32(CEXTERR); |
|
1891 er32(TSCTC); |
|
1892 er32(TSCTFC); |
|
1893 |
|
1894 er32(MGTPRC); |
|
1895 er32(MGTPDC); |
|
1896 er32(MGTPTC); |
|
1897 |
|
1898 er32(IAC); |
|
1899 er32(ICRXOC); |
|
1900 |
|
1901 er32(ICRXPTC); |
|
1902 er32(ICRXATC); |
|
1903 er32(ICTXPTC); |
|
1904 er32(ICTXATC); |
|
1905 er32(ICTXQEC); |
|
1906 er32(ICTXQMTC); |
|
1907 er32(ICRXDMTC); |
|
1908 } |
|
1909 |
|
1910 static const struct e1000_mac_operations e82571_mac_ops = { |
|
1911 /* .check_mng_mode: mac type dependent */ |
|
1912 /* .check_for_link: media type dependent */ |
|
1913 .id_led_init = e1000e_id_led_init_generic, |
|
1914 .cleanup_led = e1000e_cleanup_led_generic, |
|
1915 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, |
|
1916 .get_bus_info = e1000e_get_bus_info_pcie, |
|
1917 .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
|
1918 /* .get_link_up_info: media type dependent */ |
|
1919 /* .led_on: mac type dependent */ |
|
1920 .led_off = e1000e_led_off_generic, |
|
1921 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
|
1922 .write_vfta = e1000_write_vfta_generic, |
|
1923 .clear_vfta = e1000_clear_vfta_82571, |
|
1924 .reset_hw = e1000_reset_hw_82571, |
|
1925 .init_hw = e1000_init_hw_82571, |
|
1926 .setup_link = e1000_setup_link_82571, |
|
1927 /* .setup_physical_interface: media type dependent */ |
|
1928 .setup_led = e1000e_setup_led_generic, |
|
1929 .config_collision_dist = e1000e_config_collision_dist_generic, |
|
1930 .read_mac_addr = e1000_read_mac_addr_82571, |
|
1931 }; |
|
1932 |
|
1933 static const struct e1000_phy_operations e82_phy_ops_igp = { |
|
1934 .acquire = e1000_get_hw_semaphore_82571, |
|
1935 .check_polarity = e1000_check_polarity_igp, |
|
1936 .check_reset_block = e1000e_check_reset_block_generic, |
|
1937 .commit = NULL, |
|
1938 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
|
1939 .get_cfg_done = e1000_get_cfg_done_82571, |
|
1940 .get_cable_length = e1000e_get_cable_length_igp_2, |
|
1941 .get_info = e1000e_get_phy_info_igp, |
|
1942 .read_reg = e1000e_read_phy_reg_igp, |
|
1943 .release = e1000_put_hw_semaphore_82571, |
|
1944 .reset = e1000e_phy_hw_reset_generic, |
|
1945 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1946 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1947 .write_reg = e1000e_write_phy_reg_igp, |
|
1948 .cfg_on_link_up = NULL, |
|
1949 }; |
|
1950 |
|
1951 static const struct e1000_phy_operations e82_phy_ops_m88 = { |
|
1952 .acquire = e1000_get_hw_semaphore_82571, |
|
1953 .check_polarity = e1000_check_polarity_m88, |
|
1954 .check_reset_block = e1000e_check_reset_block_generic, |
|
1955 .commit = e1000e_phy_sw_reset, |
|
1956 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
|
1957 .get_cfg_done = e1000e_get_cfg_done, |
|
1958 .get_cable_length = e1000e_get_cable_length_m88, |
|
1959 .get_info = e1000e_get_phy_info_m88, |
|
1960 .read_reg = e1000e_read_phy_reg_m88, |
|
1961 .release = e1000_put_hw_semaphore_82571, |
|
1962 .reset = e1000e_phy_hw_reset_generic, |
|
1963 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1964 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1965 .write_reg = e1000e_write_phy_reg_m88, |
|
1966 .cfg_on_link_up = NULL, |
|
1967 }; |
|
1968 |
|
1969 static const struct e1000_phy_operations e82_phy_ops_bm = { |
|
1970 .acquire = e1000_get_hw_semaphore_82571, |
|
1971 .check_polarity = e1000_check_polarity_m88, |
|
1972 .check_reset_block = e1000e_check_reset_block_generic, |
|
1973 .commit = e1000e_phy_sw_reset, |
|
1974 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
|
1975 .get_cfg_done = e1000e_get_cfg_done, |
|
1976 .get_cable_length = e1000e_get_cable_length_m88, |
|
1977 .get_info = e1000e_get_phy_info_m88, |
|
1978 .read_reg = e1000e_read_phy_reg_bm2, |
|
1979 .release = e1000_put_hw_semaphore_82571, |
|
1980 .reset = e1000e_phy_hw_reset_generic, |
|
1981 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
|
1982 .set_d3_lplu_state = e1000e_set_d3_lplu_state, |
|
1983 .write_reg = e1000e_write_phy_reg_bm2, |
|
1984 .cfg_on_link_up = NULL, |
|
1985 }; |
|
1986 |
|
1987 static const struct e1000_nvm_operations e82571_nvm_ops = { |
|
1988 .acquire = e1000_acquire_nvm_82571, |
|
1989 .read = e1000e_read_nvm_eerd, |
|
1990 .release = e1000_release_nvm_82571, |
|
1991 .reload = e1000e_reload_nvm_generic, |
|
1992 .update = e1000_update_nvm_checksum_82571, |
|
1993 .valid_led_default = e1000_valid_led_default_82571, |
|
1994 .validate = e1000_validate_nvm_checksum_82571, |
|
1995 .write = e1000_write_nvm_82571, |
|
1996 }; |
|
1997 |
|
1998 const struct e1000_info e1000_82571_info = { |
|
1999 .mac = e1000_82571, |
|
2000 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
2001 | FLAG_HAS_JUMBO_FRAMES |
|
2002 | FLAG_HAS_WOL |
|
2003 | FLAG_APME_IN_CTRL3 |
|
2004 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
2005 | FLAG_HAS_SMART_POWER_DOWN |
|
2006 | FLAG_RESET_OVERWRITES_LAA /* errata */ |
|
2007 | FLAG_TARC_SPEED_MODE_BIT /* errata */ |
|
2008 | FLAG_APME_CHECK_PORT_B, |
|
2009 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
|
2010 | FLAG2_DMA_BURST, |
|
2011 .pba = 38, |
|
2012 .max_hw_frame_size = DEFAULT_JUMBO, |
|
2013 .get_variants = e1000_get_variants_82571, |
|
2014 .mac_ops = &e82571_mac_ops, |
|
2015 .phy_ops = &e82_phy_ops_igp, |
|
2016 .nvm_ops = &e82571_nvm_ops, |
|
2017 }; |
|
2018 |
|
2019 const struct e1000_info e1000_82572_info = { |
|
2020 .mac = e1000_82572, |
|
2021 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
2022 | FLAG_HAS_JUMBO_FRAMES |
|
2023 | FLAG_HAS_WOL |
|
2024 | FLAG_APME_IN_CTRL3 |
|
2025 | FLAG_HAS_CTRLEXT_ON_LOAD |
|
2026 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
|
2027 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
|
2028 | FLAG2_DMA_BURST, |
|
2029 .pba = 38, |
|
2030 .max_hw_frame_size = DEFAULT_JUMBO, |
|
2031 .get_variants = e1000_get_variants_82571, |
|
2032 .mac_ops = &e82571_mac_ops, |
|
2033 .phy_ops = &e82_phy_ops_igp, |
|
2034 .nvm_ops = &e82571_nvm_ops, |
|
2035 }; |
|
2036 |
|
2037 const struct e1000_info e1000_82573_info = { |
|
2038 .mac = e1000_82573, |
|
2039 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
2040 | FLAG_HAS_WOL |
|
2041 | FLAG_APME_IN_CTRL3 |
|
2042 | FLAG_HAS_SMART_POWER_DOWN |
|
2043 | FLAG_HAS_AMT |
|
2044 | FLAG_HAS_SWSM_ON_LOAD, |
|
2045 .flags2 = FLAG2_DISABLE_ASPM_L1 |
|
2046 | FLAG2_DISABLE_ASPM_L0S, |
|
2047 .pba = 20, |
|
2048 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
|
2049 .get_variants = e1000_get_variants_82571, |
|
2050 .mac_ops = &e82571_mac_ops, |
|
2051 .phy_ops = &e82_phy_ops_m88, |
|
2052 .nvm_ops = &e82571_nvm_ops, |
|
2053 }; |
|
2054 |
|
2055 const struct e1000_info e1000_82574_info = { |
|
2056 .mac = e1000_82574, |
|
2057 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
2058 | FLAG_HAS_MSIX |
|
2059 | FLAG_HAS_JUMBO_FRAMES |
|
2060 | FLAG_HAS_WOL |
|
2061 | FLAG_APME_IN_CTRL3 |
|
2062 | FLAG_HAS_SMART_POWER_DOWN |
|
2063 | FLAG_HAS_AMT |
|
2064 | FLAG_HAS_CTRLEXT_ON_LOAD, |
|
2065 .flags2 = FLAG2_CHECK_PHY_HANG |
|
2066 | FLAG2_DISABLE_ASPM_L0S |
|
2067 | FLAG2_DISABLE_ASPM_L1 |
|
2068 | FLAG2_NO_DISABLE_RX, |
|
2069 .pba = 32, |
|
2070 .max_hw_frame_size = DEFAULT_JUMBO, |
|
2071 .get_variants = e1000_get_variants_82571, |
|
2072 .mac_ops = &e82571_mac_ops, |
|
2073 .phy_ops = &e82_phy_ops_bm, |
|
2074 .nvm_ops = &e82571_nvm_ops, |
|
2075 }; |
|
2076 |
|
2077 const struct e1000_info e1000_82583_info = { |
|
2078 .mac = e1000_82583, |
|
2079 .flags = FLAG_HAS_HW_VLAN_FILTER |
|
2080 | FLAG_HAS_WOL |
|
2081 | FLAG_APME_IN_CTRL3 |
|
2082 | FLAG_HAS_SMART_POWER_DOWN |
|
2083 | FLAG_HAS_AMT |
|
2084 | FLAG_HAS_JUMBO_FRAMES |
|
2085 | FLAG_HAS_CTRLEXT_ON_LOAD, |
|
2086 .flags2 = FLAG2_DISABLE_ASPM_L0S |
|
2087 | FLAG2_NO_DISABLE_RX, |
|
2088 .pba = 32, |
|
2089 .max_hw_frame_size = DEFAULT_JUMBO, |
|
2090 .get_variants = e1000_get_variants_82571, |
|
2091 .mac_ops = &e82571_mac_ops, |
|
2092 .phy_ops = &e82_phy_ops_bm, |
|
2093 .nvm_ops = &e82571_nvm_ops, |
|
2094 }; |
|
2095 |