244 master->stats.timeouts = 0; |
244 master->stats.timeouts = 0; |
245 master->stats.delayed = 0; |
245 master->stats.delayed = 0; |
246 master->stats.corrupted = 0; |
246 master->stats.corrupted = 0; |
247 master->stats.skipped = 0; |
247 master->stats.skipped = 0; |
248 master->stats.unmatched = 0; |
248 master->stats.unmatched = 0; |
249 master->stats.t_last = 0; |
249 master->stats.output_jiffies = 0; |
250 |
250 |
251 master->mode = EC_MASTER_MODE_ORPHANED; |
251 master->mode = EC_MASTER_MODE_ORPHANED; |
252 |
252 |
253 master->request_cb = NULL; |
253 master->request_cb = NULL; |
254 master->release_cb = NULL; |
254 master->release_cb = NULL; |
314 { |
314 { |
315 ec_datagram_t *datagram; |
315 ec_datagram_t *datagram; |
316 size_t datagram_size; |
316 size_t datagram_size; |
317 uint8_t *frame_data, *cur_data; |
317 uint8_t *frame_data, *cur_data; |
318 void *follows_word; |
318 void *follows_word; |
319 cycles_t t_start, t_end; |
319 cycles_t cycles_start, cycles_end; |
320 unsigned int frame_count, more_datagrams_waiting; |
320 unsigned int frame_count, more_datagrams_waiting; |
321 |
321 |
322 frame_count = 0; |
322 frame_count = 0; |
323 t_start = get_cycles(); |
323 cycles_start = get_cycles(); |
324 |
324 |
325 if (unlikely(master->debug_level > 1)) |
325 if (unlikely(master->debug_level > 1)) |
326 EC_DBG("ec_master_send_datagrams\n"); |
326 EC_DBG("ec_master_send_datagrams\n"); |
327 |
327 |
328 do { |
328 do { |
343 more_datagrams_waiting = 1; |
343 more_datagrams_waiting = 1; |
344 break; |
344 break; |
345 } |
345 } |
346 |
346 |
347 datagram->state = EC_DATAGRAM_SENT; |
347 datagram->state = EC_DATAGRAM_SENT; |
348 datagram->t_sent = t_start; |
348 datagram->cycles_sent = cycles_start; |
349 datagram->index = master->datagram_index++; |
349 datagram->index = master->datagram_index++; |
350 |
350 |
351 if (unlikely(master->debug_level > 1)) |
351 if (unlikely(master->debug_level > 1)) |
352 EC_DBG("adding datagram 0x%02X\n", datagram->index); |
352 EC_DBG("adding datagram 0x%02X\n", datagram->index); |
353 |
353 |
395 frame_count++; |
395 frame_count++; |
396 } |
396 } |
397 while (more_datagrams_waiting); |
397 while (more_datagrams_waiting); |
398 |
398 |
399 if (unlikely(master->debug_level > 1)) { |
399 if (unlikely(master->debug_level > 1)) { |
400 t_end = get_cycles(); |
400 cycles_end = get_cycles(); |
401 EC_DBG("ec_master_send_datagrams sent %i frames in %ius.\n", |
401 EC_DBG("ec_master_send_datagrams sent %i frames in %ius.\n", |
402 frame_count, (unsigned int) (t_end - t_start) * 1000 / cpu_khz); |
402 frame_count, |
|
403 (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz); |
403 } |
404 } |
404 } |
405 } |
405 |
406 |
406 /*****************************************************************************/ |
407 /*****************************************************************************/ |
407 |
408 |
526 necessary. The output happens at most once a second. |
527 necessary. The output happens at most once a second. |
527 */ |
528 */ |
528 |
529 |
529 void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */) |
530 void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */) |
530 { |
531 { |
531 cycles_t t_now = get_cycles(); |
532 if (unlikely(jiffies - master->stats.output_jiffies >= HZ)) { |
532 |
533 master->stats.output_jiffies = jiffies; |
533 if (unlikely((u32) (t_now - master->stats.t_last) / cpu_khz > 1000)) { |
534 |
534 if (master->stats.timeouts) { |
535 if (master->stats.timeouts) { |
535 EC_WARN("%i datagrams TIMED OUT!\n", master->stats.timeouts); |
536 EC_WARN("%i datagrams TIMED OUT!\n", master->stats.timeouts); |
536 master->stats.timeouts = 0; |
537 master->stats.timeouts = 0; |
537 } |
538 } |
538 if (master->stats.delayed) { |
539 if (master->stats.delayed) { |
608 */ |
608 */ |
609 |
609 |
610 void ec_master_idle_run(void *data /**< master pointer */) |
610 void ec_master_idle_run(void *data /**< master pointer */) |
611 { |
611 { |
612 ec_master_t *master = (ec_master_t *) data; |
612 ec_master_t *master = (ec_master_t *) data; |
613 cycles_t start, end; |
613 cycles_t cycles_start, cycles_end; |
614 |
614 |
615 // aquire master lock |
615 // aquire master lock |
616 spin_lock_bh(&master->internal_lock); |
616 spin_lock_bh(&master->internal_lock); |
617 |
617 |
618 start = get_cycles(); |
618 cycles_start = get_cycles(); |
619 ecrt_master_receive(master); |
619 ecrt_master_receive(master); |
620 |
620 |
621 // execute master state machine |
621 // execute master state machine |
622 ec_fsm_execute(&master->fsm); |
622 ec_fsm_execute(&master->fsm); |
623 |
623 |
624 ecrt_master_send(master); |
624 ecrt_master_send(master); |
625 end = get_cycles(); |
625 cycles_end = get_cycles(); |
626 |
626 |
627 // release master lock |
627 // release master lock |
628 spin_unlock_bh(&master->internal_lock); |
628 spin_unlock_bh(&master->internal_lock); |
629 |
629 |
630 master->idle_cycle_times[master->idle_cycle_time_pos] |
630 master->idle_cycle_times[master->idle_cycle_time_pos] |
631 = (u32) (end - start) * 1000 / cpu_khz; |
631 = (u32) (cycles_end - cycles_start) * 1000 / cpu_khz; |
632 master->idle_cycle_time_pos++; |
632 master->idle_cycle_time_pos++; |
633 master->idle_cycle_time_pos %= HZ; |
633 master->idle_cycle_time_pos %= HZ; |
634 |
634 |
635 if (master->mode == EC_MASTER_MODE_IDLE) |
635 if (master->mode == EC_MASTER_MODE_IDLE) |
636 queue_delayed_work(master->workqueue, &master->idle_work, 1); |
636 queue_delayed_work(master->workqueue, &master->idle_work, 1); |
956 void ec_master_eoe_run(unsigned long data /**< master pointer */) |
956 void ec_master_eoe_run(unsigned long data /**< master pointer */) |
957 { |
957 { |
958 ec_master_t *master = (ec_master_t *) data; |
958 ec_master_t *master = (ec_master_t *) data; |
959 ec_eoe_t *eoe; |
959 ec_eoe_t *eoe; |
960 unsigned int active = 0; |
960 unsigned int active = 0; |
961 cycles_t start, end; |
961 cycles_t cycles_start, cycles_end; |
|
962 unsigned long restart_jiffies; |
962 |
963 |
963 list_for_each_entry(eoe, &master->eoe_handlers, list) { |
964 list_for_each_entry(eoe, &master->eoe_handlers, list) { |
964 if (ec_eoe_active(eoe)) active++; |
965 if (ec_eoe_active(eoe)) active++; |
965 } |
966 } |
966 if (!active) goto queue_timer; |
967 if (!active) goto queue_timer; |
975 spin_lock(&master->internal_lock); |
976 spin_lock(&master->internal_lock); |
976 } |
977 } |
977 else |
978 else |
978 goto queue_timer; |
979 goto queue_timer; |
979 |
980 |
980 // actual EoE stuff |
981 // actual EoE processing |
981 start = get_cycles(); |
982 cycles_start = get_cycles(); |
982 ecrt_master_receive(master); |
983 ecrt_master_receive(master); |
983 |
984 |
984 list_for_each_entry(eoe, &master->eoe_handlers, list) { |
985 list_for_each_entry(eoe, &master->eoe_handlers, list) { |
985 ec_eoe_run(eoe); |
986 ec_eoe_run(eoe); |
986 } |
987 } |
987 |
988 |
988 ecrt_master_send(master); |
989 ecrt_master_send(master); |
989 end = get_cycles(); |
990 cycles_end = get_cycles(); |
990 |
991 |
991 // release lock... |
992 // release lock... |
992 if (master->mode == EC_MASTER_MODE_OPERATION) { |
993 if (master->mode == EC_MASTER_MODE_OPERATION) { |
993 master->release_cb(master->cb_data); |
994 master->release_cb(master->cb_data); |
994 } |
995 } |
995 else if (master->mode == EC_MASTER_MODE_IDLE) { |
996 else if (master->mode == EC_MASTER_MODE_IDLE) { |
996 spin_unlock(&master->internal_lock); |
997 spin_unlock(&master->internal_lock); |
997 } |
998 } |
998 |
999 |
999 master->eoe_cycle_times[master->eoe_cycle_time_pos] |
1000 master->eoe_cycle_times[master->eoe_cycle_time_pos] |
1000 = (u32) (end - start) * 1000 / cpu_khz; |
1001 = (u32) (cycles_end - cycles_start) * 1000 / cpu_khz; |
1001 master->eoe_cycle_time_pos++; |
1002 master->eoe_cycle_time_pos++; |
1002 master->eoe_cycle_time_pos %= HZ; |
1003 master->eoe_cycle_time_pos %= HZ; |
1003 |
1004 |
1004 queue_timer: |
1005 queue_timer: |
1005 master->eoe_timer.expires += HZ / EC_EOE_FREQUENCY; |
1006 restart_jiffies = HZ / EC_EOE_FREQUENCY; |
|
1007 if (!restart_jiffies) restart_jiffies = 1; |
|
1008 master->eoe_timer.expires += restart_jiffies; |
1006 add_timer(&master->eoe_timer); |
1009 add_timer(&master->eoe_timer); |
1007 } |
1010 } |
1008 |
1011 |
1009 /*****************************************************************************/ |
1012 /*****************************************************************************/ |
1010 |
1013 |
1045 */ |
1048 */ |
1046 |
1049 |
1047 void ec_master_measure_bus_time(ec_master_t *master) |
1050 void ec_master_measure_bus_time(ec_master_t *master) |
1048 { |
1051 { |
1049 ec_datagram_t datagram; |
1052 ec_datagram_t datagram; |
1050 cycles_t t_start, t_end, t_timeout; |
1053 cycles_t cycles_start, cycles_end, cycles_timeout; |
1051 uint32_t times[100], sum, min, max, i; |
1054 uint32_t times[100], sum, min, max, i; |
1052 |
1055 |
1053 ec_datagram_init(&datagram); |
1056 ec_datagram_init(&datagram); |
1054 |
1057 |
1055 if (ec_datagram_brd(&datagram, 0x130, 2)) { |
1058 if (ec_datagram_brd(&datagram, 0x130, 2)) { |
1056 EC_ERR("Failed to allocate datagram for bus time measuring.\n"); |
1059 EC_ERR("Failed to allocate datagram for bus time measuring.\n"); |
1057 ec_datagram_clear(&datagram); |
1060 ec_datagram_clear(&datagram); |
1058 return; |
1061 return; |
1059 } |
1062 } |
1060 |
1063 |
1061 t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1064 cycles_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1062 |
1065 |
1063 sum = 0; |
1066 sum = 0; |
1064 min = 0xFFFFFFFF; |
1067 min = 0xFFFFFFFF; |
1065 max = 0; |
1068 max = 0; |
1066 |
1069 |
1067 for (i = 0; i < 100; i++) { |
1070 for (i = 0; i < 100; i++) { |
1068 ec_master_queue_datagram(master, &datagram); |
1071 ec_master_queue_datagram(master, &datagram); |
1069 ecrt_master_send(master); |
1072 ecrt_master_send(master); |
1070 t_start = get_cycles(); |
1073 cycles_start = get_cycles(); |
1071 |
1074 |
1072 while (1) { // active waiting |
1075 while (1) { // active waiting |
1073 ec_device_call_isr(master->device); |
1076 ec_device_call_isr(master->device); |
1074 t_end = get_cycles(); // take current time |
1077 cycles_end = get_cycles(); // take current time |
1075 |
1078 |
1076 if (datagram.state == EC_DATAGRAM_RECEIVED) { |
1079 if (datagram.state == EC_DATAGRAM_RECEIVED) { |
1077 break; |
1080 break; |
1078 } |
1081 } |
1079 else if (datagram.state == EC_DATAGRAM_ERROR) { |
1082 else if (datagram.state == EC_DATAGRAM_ERROR) { |
1080 EC_WARN("Failed to measure bus time.\n"); |
1083 EC_WARN("Failed to measure bus time.\n"); |
1081 goto error; |
1084 goto error; |
1082 } |
1085 } |
1083 else if (t_end - t_start >= t_timeout) { |
1086 else if (cycles_end - cycles_start >= cycles_timeout) { |
1084 EC_WARN("Timeout while measuring bus time.\n"); |
1087 EC_WARN("Timeout while measuring bus time.\n"); |
1085 goto error; |
1088 goto error; |
1086 } |
1089 } |
1087 } |
1090 } |
1088 |
1091 |
1089 times[i] = (unsigned int) (t_end - t_start) * 1000 / cpu_khz; |
1092 times[i] = (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz; |
1090 sum += times[i]; |
1093 sum += times[i]; |
1091 if (times[i] > max) max = times[i]; |
1094 if (times[i] > max) max = times[i]; |
1092 if (times[i] < min) min = times[i]; |
1095 if (times[i] < min) min = times[i]; |
1093 } |
1096 } |
1094 |
1097 |
1234 |
1237 |
1235 void ec_master_sync_io(ec_master_t *master /**< EtherCAT master */) |
1238 void ec_master_sync_io(ec_master_t *master /**< EtherCAT master */) |
1236 { |
1239 { |
1237 ec_datagram_t *datagram, *n; |
1240 ec_datagram_t *datagram, *n; |
1238 unsigned int datagrams_sent; |
1241 unsigned int datagrams_sent; |
1239 cycles_t t_start, t_end, t_timeout; |
1242 cycles_t cycles_start, cycles_end, cycles_timeout; |
1240 |
1243 |
1241 // send datagrams |
1244 // send datagrams |
1242 ecrt_master_send(master); |
1245 ecrt_master_send(master); |
1243 |
1246 |
1244 t_start = get_cycles(); // measure io time |
1247 cycles_start = get_cycles(); // measure io time |
1245 t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1248 cycles_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1246 |
1249 |
1247 while (1) { // active waiting |
1250 while (1) { // active waiting |
1248 ec_device_call_isr(master->device); |
1251 ec_device_call_isr(master->device); |
1249 |
1252 |
1250 t_end = get_cycles(); // take current time |
1253 cycles_end = get_cycles(); // take current time |
1251 if (t_end - t_start >= t_timeout) break; // timeout! |
1254 if (cycles_end - cycles_start >= cycles_timeout) break; // timeout! |
1252 |
1255 |
1253 datagrams_sent = 0; |
1256 datagrams_sent = 0; |
1254 list_for_each_entry_safe(datagram, n, &master->datagram_queue, queue) { |
1257 list_for_each_entry_safe(datagram, n, &master->datagram_queue, queue) { |
1255 if (datagram->state == EC_DATAGRAM_RECEIVED) |
1258 if (datagram->state == EC_DATAGRAM_RECEIVED) |
1256 list_del_init(&datagram->queue); |
1259 list_del_init(&datagram->queue); |
1316 */ |
1319 */ |
1317 |
1320 |
1318 void ecrt_master_receive(ec_master_t *master /**< EtherCAT master */) |
1321 void ecrt_master_receive(ec_master_t *master /**< EtherCAT master */) |
1319 { |
1322 { |
1320 ec_datagram_t *datagram, *next; |
1323 ec_datagram_t *datagram, *next; |
1321 cycles_t t_received, t_timeout; |
1324 cycles_t cycles_received, cycles_timeout; |
1322 |
1325 |
1323 ec_device_call_isr(master->device); |
1326 ec_device_call_isr(master->device); |
1324 |
1327 |
1325 t_received = get_cycles(); |
1328 cycles_received = get_cycles(); |
1326 t_timeout = EC_IO_TIMEOUT * cpu_khz / 1000; |
1329 cycles_timeout = EC_IO_TIMEOUT * cpu_khz / 1000; |
1327 |
1330 |
1328 // dequeue all received datagrams |
1331 // dequeue all received datagrams |
1329 list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) |
1332 list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) |
1330 if (datagram->state == EC_DATAGRAM_RECEIVED) |
1333 if (datagram->state == EC_DATAGRAM_RECEIVED) |
1331 list_del_init(&datagram->queue); |
1334 list_del_init(&datagram->queue); |
1333 // dequeue all datagrams that timed out |
1336 // dequeue all datagrams that timed out |
1334 list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) { |
1337 list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) { |
1335 switch (datagram->state) { |
1338 switch (datagram->state) { |
1336 case EC_DATAGRAM_SENT: |
1339 case EC_DATAGRAM_SENT: |
1337 case EC_DATAGRAM_QUEUED: |
1340 case EC_DATAGRAM_QUEUED: |
1338 if (t_received - datagram->t_sent > t_timeout) { |
1341 if (cycles_received - datagram->cycles_sent > cycles_timeout) { |
1339 list_del_init(&datagram->queue); |
1342 list_del_init(&datagram->queue); |
1340 datagram->state = EC_DATAGRAM_TIMED_OUT; |
1343 datagram->state = EC_DATAGRAM_TIMED_OUT; |
1341 master->stats.timeouts++; |
1344 master->stats.timeouts++; |
1342 ec_master_output_stats(master); |
1345 ec_master_output_stats(master); |
1343 } |
1346 } |
1358 */ |
1361 */ |
1359 |
1362 |
1360 void ecrt_master_prepare(ec_master_t *master /**< EtherCAT master */) |
1363 void ecrt_master_prepare(ec_master_t *master /**< EtherCAT master */) |
1361 { |
1364 { |
1362 ec_domain_t *domain; |
1365 ec_domain_t *domain; |
1363 cycles_t t_start, t_end, t_timeout; |
1366 cycles_t cycles_start, cycles_end, cycles_timeout; |
1364 |
1367 |
1365 // queue datagrams of all domains |
1368 // queue datagrams of all domains |
1366 list_for_each_entry(domain, &master->domains, list) |
1369 list_for_each_entry(domain, &master->domains, list) |
1367 ec_domain_queue(domain); |
1370 ec_domain_queue(domain); |
1368 |
1371 |
1369 ecrt_master_send(master); |
1372 ecrt_master_send(master); |
1370 |
1373 |
1371 t_start = get_cycles(); // take sending time |
1374 cycles_start = get_cycles(); // take sending time |
1372 t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1375 cycles_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000); |
1373 |
1376 |
1374 // active waiting |
1377 // active waiting |
1375 while (1) { |
1378 while (1) { |
1376 t_end = get_cycles(); |
1379 cycles_end = get_cycles(); |
1377 if (t_end - t_start >= t_timeout) break; |
1380 if (cycles_end - cycles_start >= cycles_timeout) break; |
1378 } |
1381 } |
1379 } |
1382 } |
1380 |
1383 |
1381 /*****************************************************************************/ |
1384 /*****************************************************************************/ |
1382 |
1385 |