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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 */ |
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10 |
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11 #include <linux/module.h> |
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12 #include <linux/moduleparam.h> |
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13 #include <linux/pci.h> |
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14 #include <linux/netdevice.h> |
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15 #include <linux/etherdevice.h> |
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16 #include <linux/delay.h> |
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17 #include <linux/ethtool.h> |
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18 #include <linux/mii.h> |
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19 #include <linux/if_vlan.h> |
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20 #include <linux/crc32.h> |
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21 #include <linux/in.h> |
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22 #include <linux/ip.h> |
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23 #include <linux/tcp.h> |
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24 #include <linux/init.h> |
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25 #include <linux/interrupt.h> |
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26 #include <linux/dma-mapping.h> |
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27 #include <linux/pm_runtime.h> |
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28 #include <linux/firmware.h> |
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29 #include <linux/pci-aspm.h> |
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30 #include <linux/prefetch.h> |
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31 |
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32 #include <asm/system.h> |
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33 #include <asm/io.h> |
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34 #include <asm/irq.h> |
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35 |
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36 #define RTL8169_VERSION "2.3LK-NAPI" |
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37 #define MODULENAME "r8169" |
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38 #define PFX MODULENAME ": " |
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39 |
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40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
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41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
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42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
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43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" |
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44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
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45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
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46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" |
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47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
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48 |
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49 #ifdef RTL8169_DEBUG |
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50 #define assert(expr) \ |
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51 if (!(expr)) { \ |
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52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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53 #expr,__FILE__,__func__,__LINE__); \ |
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54 } |
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55 #define dprintk(fmt, args...) \ |
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56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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57 #else |
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58 #define assert(expr) do {} while (0) |
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59 #define dprintk(fmt, args...) do {} while (0) |
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60 #endif /* RTL8169_DEBUG */ |
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61 |
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62 #define R8169_MSG_DEFAULT \ |
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63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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64 |
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65 #define TX_BUFFS_AVAIL(tp) \ |
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66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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67 |
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68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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70 static const int multicast_filter_limit = 32; |
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71 |
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72 /* MAC address length */ |
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73 #define MAC_ADDR_LEN 6 |
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74 |
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75 #define MAX_READ_REQUEST_SHIFT 12 |
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76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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77 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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78 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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79 |
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80 #define R8169_REGS_SIZE 256 |
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81 #define R8169_NAPI_WEIGHT 64 |
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82 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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83 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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84 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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85 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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86 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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87 |
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88 #define RTL8169_TX_TIMEOUT (6*HZ) |
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89 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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90 |
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91 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
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92 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
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93 #define RTL_EEPROM_SIG_ADDR 0x0000 |
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94 |
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95 /* write/read MMIO register */ |
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96 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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97 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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98 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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99 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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100 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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101 #define RTL_R32(reg) readl (ioaddr + (reg)) |
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102 |
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103 enum mac_version { |
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104 RTL_GIGA_MAC_VER_01 = 0, |
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105 RTL_GIGA_MAC_VER_02, |
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106 RTL_GIGA_MAC_VER_03, |
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107 RTL_GIGA_MAC_VER_04, |
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108 RTL_GIGA_MAC_VER_05, |
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109 RTL_GIGA_MAC_VER_06, |
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110 RTL_GIGA_MAC_VER_07, |
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111 RTL_GIGA_MAC_VER_08, |
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112 RTL_GIGA_MAC_VER_09, |
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113 RTL_GIGA_MAC_VER_10, |
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114 RTL_GIGA_MAC_VER_11, |
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115 RTL_GIGA_MAC_VER_12, |
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116 RTL_GIGA_MAC_VER_13, |
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117 RTL_GIGA_MAC_VER_14, |
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118 RTL_GIGA_MAC_VER_15, |
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119 RTL_GIGA_MAC_VER_16, |
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120 RTL_GIGA_MAC_VER_17, |
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121 RTL_GIGA_MAC_VER_18, |
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122 RTL_GIGA_MAC_VER_19, |
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123 RTL_GIGA_MAC_VER_20, |
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124 RTL_GIGA_MAC_VER_21, |
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125 RTL_GIGA_MAC_VER_22, |
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126 RTL_GIGA_MAC_VER_23, |
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127 RTL_GIGA_MAC_VER_24, |
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128 RTL_GIGA_MAC_VER_25, |
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129 RTL_GIGA_MAC_VER_26, |
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130 RTL_GIGA_MAC_VER_27, |
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131 RTL_GIGA_MAC_VER_28, |
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132 RTL_GIGA_MAC_VER_29, |
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133 RTL_GIGA_MAC_VER_30, |
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134 RTL_GIGA_MAC_VER_31, |
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135 RTL_GIGA_MAC_VER_32, |
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136 RTL_GIGA_MAC_VER_33, |
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137 RTL_GIGA_MAC_VER_34, |
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138 RTL_GIGA_MAC_VER_35, |
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139 RTL_GIGA_MAC_VER_36, |
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140 RTL_GIGA_MAC_NONE = 0xff, |
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141 }; |
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142 |
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143 enum rtl_tx_desc_version { |
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144 RTL_TD_0 = 0, |
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145 RTL_TD_1 = 1, |
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146 }; |
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147 |
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148 #define JUMBO_1K ETH_DATA_LEN |
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149 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) |
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150 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) |
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151 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) |
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152 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) |
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153 |
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154 #define _R(NAME,TD,FW,SZ,B) { \ |
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155 .name = NAME, \ |
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156 .txd_version = TD, \ |
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157 .fw_name = FW, \ |
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158 .jumbo_max = SZ, \ |
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159 .jumbo_tx_csum = B \ |
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160 } |
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161 |
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162 static const struct { |
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163 const char *name; |
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164 enum rtl_tx_desc_version txd_version; |
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165 const char *fw_name; |
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166 u16 jumbo_max; |
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167 bool jumbo_tx_csum; |
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168 } rtl_chip_infos[] = { |
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169 /* PCI devices. */ |
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170 [RTL_GIGA_MAC_VER_01] = |
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171 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
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172 [RTL_GIGA_MAC_VER_02] = |
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173 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
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174 [RTL_GIGA_MAC_VER_03] = |
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175 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
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176 [RTL_GIGA_MAC_VER_04] = |
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177 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
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178 [RTL_GIGA_MAC_VER_05] = |
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179 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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180 [RTL_GIGA_MAC_VER_06] = |
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181 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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182 /* PCI-E devices. */ |
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183 [RTL_GIGA_MAC_VER_07] = |
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184 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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185 [RTL_GIGA_MAC_VER_08] = |
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186 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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187 [RTL_GIGA_MAC_VER_09] = |
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188 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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189 [RTL_GIGA_MAC_VER_10] = |
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190 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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191 [RTL_GIGA_MAC_VER_11] = |
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192 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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193 [RTL_GIGA_MAC_VER_12] = |
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194 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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195 [RTL_GIGA_MAC_VER_13] = |
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196 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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197 [RTL_GIGA_MAC_VER_14] = |
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198 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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199 [RTL_GIGA_MAC_VER_15] = |
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200 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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201 [RTL_GIGA_MAC_VER_16] = |
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202 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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203 [RTL_GIGA_MAC_VER_17] = |
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204 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
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205 [RTL_GIGA_MAC_VER_18] = |
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206 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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207 [RTL_GIGA_MAC_VER_19] = |
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208 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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209 [RTL_GIGA_MAC_VER_20] = |
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210 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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211 [RTL_GIGA_MAC_VER_21] = |
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212 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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213 [RTL_GIGA_MAC_VER_22] = |
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214 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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215 [RTL_GIGA_MAC_VER_23] = |
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216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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217 [RTL_GIGA_MAC_VER_24] = |
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218 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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219 [RTL_GIGA_MAC_VER_25] = |
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220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
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221 JUMBO_9K, false), |
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222 [RTL_GIGA_MAC_VER_26] = |
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223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
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224 JUMBO_9K, false), |
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225 [RTL_GIGA_MAC_VER_27] = |
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226 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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227 [RTL_GIGA_MAC_VER_28] = |
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228 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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229 [RTL_GIGA_MAC_VER_29] = |
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230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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231 JUMBO_1K, true), |
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232 [RTL_GIGA_MAC_VER_30] = |
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233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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234 JUMBO_1K, true), |
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235 [RTL_GIGA_MAC_VER_31] = |
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236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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237 [RTL_GIGA_MAC_VER_32] = |
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238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
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239 JUMBO_9K, false), |
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240 [RTL_GIGA_MAC_VER_33] = |
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241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
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242 JUMBO_9K, false), |
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243 [RTL_GIGA_MAC_VER_34] = |
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244 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
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245 JUMBO_9K, false), |
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246 [RTL_GIGA_MAC_VER_35] = |
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247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
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248 JUMBO_9K, false), |
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249 [RTL_GIGA_MAC_VER_36] = |
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250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
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251 JUMBO_9K, false), |
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252 }; |
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253 #undef _R |
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254 |
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255 enum cfg_version { |
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256 RTL_CFG_0 = 0x00, |
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257 RTL_CFG_1, |
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258 RTL_CFG_2 |
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259 }; |
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260 |
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261 static void rtl_hw_start_8169(struct net_device *); |
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262 static void rtl_hw_start_8168(struct net_device *); |
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263 static void rtl_hw_start_8101(struct net_device *); |
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264 |
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265 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
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266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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269 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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270 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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271 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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272 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
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273 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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274 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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275 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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276 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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277 { 0x0001, 0x8168, |
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278 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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279 {0,}, |
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280 }; |
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281 |
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282 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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283 |
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284 static int rx_buf_sz = 16383; |
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285 static int use_dac; |
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286 static struct { |
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287 u32 msg_enable; |
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288 } debug = { -1 }; |
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289 |
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290 enum rtl_registers { |
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291 MAC0 = 0, /* Ethernet hardware address. */ |
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292 MAC4 = 4, |
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293 MAR0 = 8, /* Multicast filter. */ |
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294 CounterAddrLow = 0x10, |
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295 CounterAddrHigh = 0x14, |
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296 TxDescStartAddrLow = 0x20, |
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297 TxDescStartAddrHigh = 0x24, |
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298 TxHDescStartAddrLow = 0x28, |
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299 TxHDescStartAddrHigh = 0x2c, |
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300 FLASH = 0x30, |
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301 ERSR = 0x36, |
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302 ChipCmd = 0x37, |
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303 TxPoll = 0x38, |
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304 IntrMask = 0x3c, |
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305 IntrStatus = 0x3e, |
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306 |
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307 TxConfig = 0x40, |
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308 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
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309 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ |
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310 |
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311 RxConfig = 0x44, |
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312 #define RX128_INT_EN (1 << 15) /* 8111c and later */ |
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313 #define RX_MULTI_EN (1 << 14) /* 8111c only */ |
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314 #define RXCFG_FIFO_SHIFT 13 |
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315 /* No threshold before first PCI xfer */ |
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316 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) |
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317 #define RXCFG_DMA_SHIFT 8 |
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318 /* Unlimited maximum PCI burst. */ |
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319 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) |
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320 |
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321 RxMissed = 0x4c, |
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322 Cfg9346 = 0x50, |
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323 Config0 = 0x51, |
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324 Config1 = 0x52, |
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325 Config2 = 0x53, |
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326 Config3 = 0x54, |
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327 Config4 = 0x55, |
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328 Config5 = 0x56, |
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329 MultiIntr = 0x5c, |
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330 PHYAR = 0x60, |
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331 PHYstatus = 0x6c, |
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332 RxMaxSize = 0xda, |
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333 CPlusCmd = 0xe0, |
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334 IntrMitigate = 0xe2, |
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335 RxDescAddrLow = 0xe4, |
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336 RxDescAddrHigh = 0xe8, |
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337 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
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338 |
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339 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ |
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340 |
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341 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ |
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342 |
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343 #define TxPacketMax (8064 >> 7) |
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344 #define EarlySize 0x27 |
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345 |
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346 FuncEvent = 0xf0, |
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347 FuncEventMask = 0xf4, |
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348 FuncPresetState = 0xf8, |
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349 FuncForceEvent = 0xfc, |
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350 }; |
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351 |
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352 enum rtl8110_registers { |
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353 TBICSR = 0x64, |
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354 TBI_ANAR = 0x68, |
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355 TBI_LPAR = 0x6a, |
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356 }; |
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357 |
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358 enum rtl8168_8101_registers { |
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359 CSIDR = 0x64, |
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360 CSIAR = 0x68, |
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361 #define CSIAR_FLAG 0x80000000 |
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362 #define CSIAR_WRITE_CMD 0x80000000 |
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363 #define CSIAR_BYTE_ENABLE 0x0f |
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364 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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365 #define CSIAR_ADDR_MASK 0x0fff |
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366 PMCH = 0x6f, |
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367 EPHYAR = 0x80, |
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368 #define EPHYAR_FLAG 0x80000000 |
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369 #define EPHYAR_WRITE_CMD 0x80000000 |
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370 #define EPHYAR_REG_MASK 0x1f |
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371 #define EPHYAR_REG_SHIFT 16 |
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372 #define EPHYAR_DATA_MASK 0xffff |
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373 DLLPR = 0xd0, |
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374 #define PFM_EN (1 << 6) |
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375 DBG_REG = 0xd1, |
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376 #define FIX_NAK_1 (1 << 4) |
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377 #define FIX_NAK_2 (1 << 3) |
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378 TWSI = 0xd2, |
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379 MCU = 0xd3, |
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380 #define NOW_IS_OOB (1 << 7) |
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381 #define EN_NDP (1 << 3) |
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382 #define EN_OOB_RESET (1 << 2) |
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383 EFUSEAR = 0xdc, |
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384 #define EFUSEAR_FLAG 0x80000000 |
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385 #define EFUSEAR_WRITE_CMD 0x80000000 |
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386 #define EFUSEAR_READ_CMD 0x00000000 |
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387 #define EFUSEAR_REG_MASK 0x03ff |
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388 #define EFUSEAR_REG_SHIFT 8 |
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389 #define EFUSEAR_DATA_MASK 0xff |
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390 }; |
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391 |
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392 enum rtl8168_registers { |
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393 LED_FREQ = 0x1a, |
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394 EEE_LED = 0x1b, |
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395 ERIDR = 0x70, |
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396 ERIAR = 0x74, |
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397 #define ERIAR_FLAG 0x80000000 |
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398 #define ERIAR_WRITE_CMD 0x80000000 |
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399 #define ERIAR_READ_CMD 0x00000000 |
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400 #define ERIAR_ADDR_BYTE_ALIGN 4 |
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401 #define ERIAR_TYPE_SHIFT 16 |
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402 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
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403 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) |
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404 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) |
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405 #define ERIAR_MASK_SHIFT 12 |
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406 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) |
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407 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) |
|
408 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
|
409 EPHY_RXER_NUM = 0x7c, |
|
410 OCPDR = 0xb0, /* OCP GPHY access */ |
|
411 #define OCPDR_WRITE_CMD 0x80000000 |
|
412 #define OCPDR_READ_CMD 0x00000000 |
|
413 #define OCPDR_REG_MASK 0x7f |
|
414 #define OCPDR_GPHY_REG_SHIFT 16 |
|
415 #define OCPDR_DATA_MASK 0xffff |
|
416 OCPAR = 0xb4, |
|
417 #define OCPAR_FLAG 0x80000000 |
|
418 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 |
|
419 #define OCPAR_GPHY_READ_CMD 0x0000f060 |
|
420 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
|
421 MISC = 0xf0, /* 8168e only. */ |
|
422 #define TXPLA_RST (1 << 29) |
|
423 #define PWM_EN (1 << 22) |
|
424 }; |
|
425 |
|
426 enum rtl_register_content { |
|
427 /* InterruptStatusBits */ |
|
428 SYSErr = 0x8000, |
|
429 PCSTimeout = 0x4000, |
|
430 SWInt = 0x0100, |
|
431 TxDescUnavail = 0x0080, |
|
432 RxFIFOOver = 0x0040, |
|
433 LinkChg = 0x0020, |
|
434 RxOverflow = 0x0010, |
|
435 TxErr = 0x0008, |
|
436 TxOK = 0x0004, |
|
437 RxErr = 0x0002, |
|
438 RxOK = 0x0001, |
|
439 |
|
440 /* RxStatusDesc */ |
|
441 RxBOVF = (1 << 24), |
|
442 RxFOVF = (1 << 23), |
|
443 RxRWT = (1 << 22), |
|
444 RxRES = (1 << 21), |
|
445 RxRUNT = (1 << 20), |
|
446 RxCRC = (1 << 19), |
|
447 |
|
448 /* ChipCmdBits */ |
|
449 StopReq = 0x80, |
|
450 CmdReset = 0x10, |
|
451 CmdRxEnb = 0x08, |
|
452 CmdTxEnb = 0x04, |
|
453 RxBufEmpty = 0x01, |
|
454 |
|
455 /* TXPoll register p.5 */ |
|
456 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
457 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
458 FSWInt = 0x01, /* Forced software interrupt */ |
|
459 |
|
460 /* Cfg9346Bits */ |
|
461 Cfg9346_Lock = 0x00, |
|
462 Cfg9346_Unlock = 0xc0, |
|
463 |
|
464 /* rx_mode_bits */ |
|
465 AcceptErr = 0x20, |
|
466 AcceptRunt = 0x10, |
|
467 AcceptBroadcast = 0x08, |
|
468 AcceptMulticast = 0x04, |
|
469 AcceptMyPhys = 0x02, |
|
470 AcceptAllPhys = 0x01, |
|
471 #define RX_CONFIG_ACCEPT_MASK 0x3f |
|
472 |
|
473 /* TxConfigBits */ |
|
474 TxInterFrameGapShift = 24, |
|
475 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
476 |
|
477 /* Config1 register p.24 */ |
|
478 LEDS1 = (1 << 7), |
|
479 LEDS0 = (1 << 6), |
|
480 Speed_down = (1 << 4), |
|
481 MEMMAP = (1 << 3), |
|
482 IOMAP = (1 << 2), |
|
483 VPD = (1 << 1), |
|
484 PMEnable = (1 << 0), /* Power Management Enable */ |
|
485 |
|
486 /* Config2 register p. 25 */ |
|
487 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
|
488 PCI_Clock_66MHz = 0x01, |
|
489 PCI_Clock_33MHz = 0x00, |
|
490 |
|
491 /* Config3 register p.25 */ |
|
492 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
493 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
494 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
|
495 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
|
496 |
|
497 /* Config4 register */ |
|
498 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ |
|
499 |
|
500 /* Config5 register p.27 */ |
|
501 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
502 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
503 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
504 Spi_en = (1 << 3), |
|
505 LanWake = (1 << 1), /* LanWake enable/disable */ |
|
506 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
507 |
|
508 /* TBICSR p.28 */ |
|
509 TBIReset = 0x80000000, |
|
510 TBILoopback = 0x40000000, |
|
511 TBINwEnable = 0x20000000, |
|
512 TBINwRestart = 0x10000000, |
|
513 TBILinkOk = 0x02000000, |
|
514 TBINwComplete = 0x01000000, |
|
515 |
|
516 /* CPlusCmd p.31 */ |
|
517 EnableBist = (1 << 15), // 8168 8101 |
|
518 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
|
519 Normal_mode = (1 << 13), // unused |
|
520 Force_half_dup = (1 << 12), // 8168 8101 |
|
521 Force_rxflow_en = (1 << 11), // 8168 8101 |
|
522 Force_txflow_en = (1 << 10), // 8168 8101 |
|
523 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
|
524 ASF = (1 << 8), // 8168 8101 |
|
525 PktCntrDisable = (1 << 7), // 8168 8101 |
|
526 Mac_dbgo_sel = 0x001c, // 8168 |
|
527 RxVlan = (1 << 6), |
|
528 RxChkSum = (1 << 5), |
|
529 PCIDAC = (1 << 4), |
|
530 PCIMulRW = (1 << 3), |
|
531 INTT_0 = 0x0000, // 8168 |
|
532 INTT_1 = 0x0001, // 8168 |
|
533 INTT_2 = 0x0002, // 8168 |
|
534 INTT_3 = 0x0003, // 8168 |
|
535 |
|
536 /* rtl8169_PHYstatus */ |
|
537 TBI_Enable = 0x80, |
|
538 TxFlowCtrl = 0x40, |
|
539 RxFlowCtrl = 0x20, |
|
540 _1000bpsF = 0x10, |
|
541 _100bps = 0x08, |
|
542 _10bps = 0x04, |
|
543 LinkStatus = 0x02, |
|
544 FullDup = 0x01, |
|
545 |
|
546 /* _TBICSRBit */ |
|
547 TBILinkOK = 0x02000000, |
|
548 |
|
549 /* DumpCounterCommand */ |
|
550 CounterDump = 0x8, |
|
551 }; |
|
552 |
|
553 enum rtl_desc_bit { |
|
554 /* First doubleword. */ |
|
555 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
556 RingEnd = (1 << 30), /* End of descriptor ring */ |
|
557 FirstFrag = (1 << 29), /* First segment of a packet */ |
|
558 LastFrag = (1 << 28), /* Final segment of a packet */ |
|
559 }; |
|
560 |
|
561 /* Generic case. */ |
|
562 enum rtl_tx_desc_bit { |
|
563 /* First doubleword. */ |
|
564 TD_LSO = (1 << 27), /* Large Send Offload */ |
|
565 #define TD_MSS_MAX 0x07ffu /* MSS value */ |
|
566 |
|
567 /* Second doubleword. */ |
|
568 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
569 }; |
|
570 |
|
571 /* 8169, 8168b and 810x except 8102e. */ |
|
572 enum rtl_tx_desc_bit_0 { |
|
573 /* First doubleword. */ |
|
574 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ |
|
575 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
576 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
577 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ |
|
578 }; |
|
579 |
|
580 /* 8102e, 8168c and beyond. */ |
|
581 enum rtl_tx_desc_bit_1 { |
|
582 /* Second doubleword. */ |
|
583 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
|
584 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ |
|
585 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
|
586 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ |
|
587 }; |
|
588 |
|
589 static const struct rtl_tx_desc_info { |
|
590 struct { |
|
591 u32 udp; |
|
592 u32 tcp; |
|
593 } checksum; |
|
594 u16 mss_shift; |
|
595 u16 opts_offset; |
|
596 } tx_desc_info [] = { |
|
597 [RTL_TD_0] = { |
|
598 .checksum = { |
|
599 .udp = TD0_IP_CS | TD0_UDP_CS, |
|
600 .tcp = TD0_IP_CS | TD0_TCP_CS |
|
601 }, |
|
602 .mss_shift = TD0_MSS_SHIFT, |
|
603 .opts_offset = 0 |
|
604 }, |
|
605 [RTL_TD_1] = { |
|
606 .checksum = { |
|
607 .udp = TD1_IP_CS | TD1_UDP_CS, |
|
608 .tcp = TD1_IP_CS | TD1_TCP_CS |
|
609 }, |
|
610 .mss_shift = TD1_MSS_SHIFT, |
|
611 .opts_offset = 1 |
|
612 } |
|
613 }; |
|
614 |
|
615 enum rtl_rx_desc_bit { |
|
616 /* Rx private */ |
|
617 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
618 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
619 |
|
620 #define RxProtoUDP (PID1) |
|
621 #define RxProtoTCP (PID0) |
|
622 #define RxProtoIP (PID1 | PID0) |
|
623 #define RxProtoMask RxProtoIP |
|
624 |
|
625 IPFail = (1 << 16), /* IP checksum failed */ |
|
626 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
627 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
628 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
629 }; |
|
630 |
|
631 #define RsvdMask 0x3fffc000 |
|
632 |
|
633 struct TxDesc { |
|
634 __le32 opts1; |
|
635 __le32 opts2; |
|
636 __le64 addr; |
|
637 }; |
|
638 |
|
639 struct RxDesc { |
|
640 __le32 opts1; |
|
641 __le32 opts2; |
|
642 __le64 addr; |
|
643 }; |
|
644 |
|
645 struct ring_info { |
|
646 struct sk_buff *skb; |
|
647 u32 len; |
|
648 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
649 }; |
|
650 |
|
651 enum features { |
|
652 RTL_FEATURE_WOL = (1 << 0), |
|
653 RTL_FEATURE_MSI = (1 << 1), |
|
654 RTL_FEATURE_GMII = (1 << 2), |
|
655 }; |
|
656 |
|
657 struct rtl8169_counters { |
|
658 __le64 tx_packets; |
|
659 __le64 rx_packets; |
|
660 __le64 tx_errors; |
|
661 __le32 rx_errors; |
|
662 __le16 rx_missed; |
|
663 __le16 align_errors; |
|
664 __le32 tx_one_collision; |
|
665 __le32 tx_multi_collision; |
|
666 __le64 rx_unicast; |
|
667 __le64 rx_broadcast; |
|
668 __le32 rx_multicast; |
|
669 __le16 tx_aborted; |
|
670 __le16 tx_underun; |
|
671 }; |
|
672 |
|
673 struct rtl8169_private { |
|
674 void __iomem *mmio_addr; /* memory map physical address */ |
|
675 struct pci_dev *pci_dev; |
|
676 struct net_device *dev; |
|
677 struct napi_struct napi; |
|
678 spinlock_t lock; |
|
679 u32 msg_enable; |
|
680 u16 txd_version; |
|
681 u16 mac_version; |
|
682 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
683 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
684 u32 dirty_rx; |
|
685 u32 dirty_tx; |
|
686 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
687 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
688 dma_addr_t TxPhyAddr; |
|
689 dma_addr_t RxPhyAddr; |
|
690 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
691 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
692 struct timer_list timer; |
|
693 u16 cp_cmd; |
|
694 u16 intr_event; |
|
695 u16 napi_event; |
|
696 u16 intr_mask; |
|
697 |
|
698 struct mdio_ops { |
|
699 void (*write)(void __iomem *, int, int); |
|
700 int (*read)(void __iomem *, int); |
|
701 } mdio_ops; |
|
702 |
|
703 struct pll_power_ops { |
|
704 void (*down)(struct rtl8169_private *); |
|
705 void (*up)(struct rtl8169_private *); |
|
706 } pll_power_ops; |
|
707 |
|
708 struct jumbo_ops { |
|
709 void (*enable)(struct rtl8169_private *); |
|
710 void (*disable)(struct rtl8169_private *); |
|
711 } jumbo_ops; |
|
712 |
|
713 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
|
714 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
715 void (*phy_reset_enable)(struct rtl8169_private *tp); |
|
716 void (*hw_start)(struct net_device *); |
|
717 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
|
718 unsigned int (*link_ok)(void __iomem *); |
|
719 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
720 struct delayed_work task; |
|
721 unsigned features; |
|
722 |
|
723 struct mii_if_info mii; |
|
724 struct rtl8169_counters counters; |
|
725 u32 saved_wolopts; |
|
726 u32 opts1_mask; |
|
727 |
|
728 struct rtl_fw { |
|
729 const struct firmware *fw; |
|
730 |
|
731 #define RTL_VER_SIZE 32 |
|
732 |
|
733 char version[RTL_VER_SIZE]; |
|
734 |
|
735 struct rtl_fw_phy_action { |
|
736 __le32 *code; |
|
737 size_t size; |
|
738 } phy_action; |
|
739 } *rtl_fw; |
|
740 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
|
741 }; |
|
742 |
|
743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
|
745 module_param(use_dac, int, 0); |
|
746 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
747 module_param_named(debug, debug.msg_enable, int, 0); |
|
748 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
749 MODULE_LICENSE("GPL"); |
|
750 MODULE_VERSION(RTL8169_VERSION); |
|
751 MODULE_FIRMWARE(FIRMWARE_8168D_1); |
|
752 MODULE_FIRMWARE(FIRMWARE_8168D_2); |
|
753 MODULE_FIRMWARE(FIRMWARE_8168E_1); |
|
754 MODULE_FIRMWARE(FIRMWARE_8168E_2); |
|
755 MODULE_FIRMWARE(FIRMWARE_8168E_3); |
|
756 MODULE_FIRMWARE(FIRMWARE_8105E_1); |
|
757 MODULE_FIRMWARE(FIRMWARE_8168F_1); |
|
758 MODULE_FIRMWARE(FIRMWARE_8168F_2); |
|
759 |
|
760 static int rtl8169_open(struct net_device *dev); |
|
761 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
762 struct net_device *dev); |
|
763 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
764 static int rtl8169_init_ring(struct net_device *dev); |
|
765 static void rtl_hw_start(struct net_device *dev); |
|
766 static int rtl8169_close(struct net_device *dev); |
|
767 static void rtl_set_rx_mode(struct net_device *dev); |
|
768 static void rtl8169_tx_timeout(struct net_device *dev); |
|
769 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
770 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
771 void __iomem *, u32 budget); |
|
772 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
773 static void rtl8169_down(struct net_device *dev); |
|
774 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
775 static int rtl8169_poll(struct napi_struct *napi, int budget); |
|
776 |
|
777 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
778 { |
|
779 int cap = pci_pcie_cap(pdev); |
|
780 |
|
781 if (cap) { |
|
782 u16 ctl; |
|
783 |
|
784 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
785 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
786 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
787 } |
|
788 } |
|
789 |
|
790 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
|
791 { |
|
792 void __iomem *ioaddr = tp->mmio_addr; |
|
793 int i; |
|
794 |
|
795 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
796 for (i = 0; i < 20; i++) { |
|
797 udelay(100); |
|
798 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
799 break; |
|
800 } |
|
801 return RTL_R32(OCPDR); |
|
802 } |
|
803 |
|
804 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) |
|
805 { |
|
806 void __iomem *ioaddr = tp->mmio_addr; |
|
807 int i; |
|
808 |
|
809 RTL_W32(OCPDR, data); |
|
810 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
811 for (i = 0; i < 20; i++) { |
|
812 udelay(100); |
|
813 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) |
|
814 break; |
|
815 } |
|
816 } |
|
817 |
|
818 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
|
819 { |
|
820 void __iomem *ioaddr = tp->mmio_addr; |
|
821 int i; |
|
822 |
|
823 RTL_W8(ERIDR, cmd); |
|
824 RTL_W32(ERIAR, 0x800010e8); |
|
825 msleep(2); |
|
826 for (i = 0; i < 5; i++) { |
|
827 udelay(100); |
|
828 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
829 break; |
|
830 } |
|
831 |
|
832 ocp_write(tp, 0x1, 0x30, 0x00000001); |
|
833 } |
|
834 |
|
835 #define OOB_CMD_RESET 0x00 |
|
836 #define OOB_CMD_DRIVER_START 0x05 |
|
837 #define OOB_CMD_DRIVER_STOP 0x06 |
|
838 |
|
839 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
|
840 { |
|
841 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; |
|
842 } |
|
843 |
|
844 static void rtl8168_driver_start(struct rtl8169_private *tp) |
|
845 { |
|
846 u16 reg; |
|
847 int i; |
|
848 |
|
849 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
|
850 |
|
851 reg = rtl8168_get_ocp_reg(tp); |
|
852 |
|
853 for (i = 0; i < 10; i++) { |
|
854 msleep(10); |
|
855 if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
|
856 break; |
|
857 } |
|
858 } |
|
859 |
|
860 static void rtl8168_driver_stop(struct rtl8169_private *tp) |
|
861 { |
|
862 u16 reg; |
|
863 int i; |
|
864 |
|
865 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); |
|
866 |
|
867 reg = rtl8168_get_ocp_reg(tp); |
|
868 |
|
869 for (i = 0; i < 10; i++) { |
|
870 msleep(10); |
|
871 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
|
872 break; |
|
873 } |
|
874 } |
|
875 |
|
876 static int r8168dp_check_dash(struct rtl8169_private *tp) |
|
877 { |
|
878 u16 reg = rtl8168_get_ocp_reg(tp); |
|
879 |
|
880 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
|
881 } |
|
882 |
|
883 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
884 { |
|
885 int i; |
|
886 |
|
887 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
888 |
|
889 for (i = 20; i > 0; i--) { |
|
890 /* |
|
891 * Check if the RTL8169 has completed writing to the specified |
|
892 * MII register. |
|
893 */ |
|
894 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
895 break; |
|
896 udelay(25); |
|
897 } |
|
898 /* |
|
899 * According to hardware specs a 20us delay is required after write |
|
900 * complete indication, but before sending next command. |
|
901 */ |
|
902 udelay(20); |
|
903 } |
|
904 |
|
905 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
906 { |
|
907 int i, value = -1; |
|
908 |
|
909 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
910 |
|
911 for (i = 20; i > 0; i--) { |
|
912 /* |
|
913 * Check if the RTL8169 has completed retrieving data from |
|
914 * the specified MII register. |
|
915 */ |
|
916 if (RTL_R32(PHYAR) & 0x80000000) { |
|
917 value = RTL_R32(PHYAR) & 0xffff; |
|
918 break; |
|
919 } |
|
920 udelay(25); |
|
921 } |
|
922 /* |
|
923 * According to hardware specs a 20us delay is required after read |
|
924 * complete indication, but before sending next command. |
|
925 */ |
|
926 udelay(20); |
|
927 |
|
928 return value; |
|
929 } |
|
930 |
|
931 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
|
932 { |
|
933 int i; |
|
934 |
|
935 RTL_W32(OCPDR, data | |
|
936 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
|
937 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
|
938 RTL_W32(EPHY_RXER_NUM, 0); |
|
939 |
|
940 for (i = 0; i < 100; i++) { |
|
941 mdelay(1); |
|
942 if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) |
|
943 break; |
|
944 } |
|
945 } |
|
946 |
|
947 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
948 { |
|
949 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | |
|
950 (value & OCPDR_DATA_MASK)); |
|
951 } |
|
952 |
|
953 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
954 { |
|
955 int i; |
|
956 |
|
957 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); |
|
958 |
|
959 mdelay(1); |
|
960 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); |
|
961 RTL_W32(EPHY_RXER_NUM, 0); |
|
962 |
|
963 for (i = 0; i < 100; i++) { |
|
964 mdelay(1); |
|
965 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
966 break; |
|
967 } |
|
968 |
|
969 return RTL_R32(OCPDR) & OCPDR_DATA_MASK; |
|
970 } |
|
971 |
|
972 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
|
973 |
|
974 static void r8168dp_2_mdio_start(void __iomem *ioaddr) |
|
975 { |
|
976 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
|
977 } |
|
978 |
|
979 static void r8168dp_2_mdio_stop(void __iomem *ioaddr) |
|
980 { |
|
981 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
|
982 } |
|
983 |
|
984 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
985 { |
|
986 r8168dp_2_mdio_start(ioaddr); |
|
987 |
|
988 r8169_mdio_write(ioaddr, reg_addr, value); |
|
989 |
|
990 r8168dp_2_mdio_stop(ioaddr); |
|
991 } |
|
992 |
|
993 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
994 { |
|
995 int value; |
|
996 |
|
997 r8168dp_2_mdio_start(ioaddr); |
|
998 |
|
999 value = r8169_mdio_read(ioaddr, reg_addr); |
|
1000 |
|
1001 r8168dp_2_mdio_stop(ioaddr); |
|
1002 |
|
1003 return value; |
|
1004 } |
|
1005 |
|
1006 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
|
1007 { |
|
1008 tp->mdio_ops.write(tp->mmio_addr, location, val); |
|
1009 } |
|
1010 |
|
1011 static int rtl_readphy(struct rtl8169_private *tp, int location) |
|
1012 { |
|
1013 return tp->mdio_ops.read(tp->mmio_addr, location); |
|
1014 } |
|
1015 |
|
1016 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) |
|
1017 { |
|
1018 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); |
|
1019 } |
|
1020 |
|
1021 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
|
1022 { |
|
1023 int val; |
|
1024 |
|
1025 val = rtl_readphy(tp, reg_addr); |
|
1026 rtl_writephy(tp, reg_addr, (val | p) & ~m); |
|
1027 } |
|
1028 |
|
1029 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
1030 int val) |
|
1031 { |
|
1032 struct rtl8169_private *tp = netdev_priv(dev); |
|
1033 |
|
1034 rtl_writephy(tp, location, val); |
|
1035 } |
|
1036 |
|
1037 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
1038 { |
|
1039 struct rtl8169_private *tp = netdev_priv(dev); |
|
1040 |
|
1041 return rtl_readphy(tp, location); |
|
1042 } |
|
1043 |
|
1044 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
1045 { |
|
1046 unsigned int i; |
|
1047 |
|
1048 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1050 |
|
1051 for (i = 0; i < 100; i++) { |
|
1052 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
1053 break; |
|
1054 udelay(10); |
|
1055 } |
|
1056 } |
|
1057 |
|
1058 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
1059 { |
|
1060 u16 value = 0xffff; |
|
1061 unsigned int i; |
|
1062 |
|
1063 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1064 |
|
1065 for (i = 0; i < 100; i++) { |
|
1066 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
1067 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
1068 break; |
|
1069 } |
|
1070 udelay(10); |
|
1071 } |
|
1072 |
|
1073 return value; |
|
1074 } |
|
1075 |
|
1076 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
1077 { |
|
1078 unsigned int i; |
|
1079 |
|
1080 RTL_W32(CSIDR, value); |
|
1081 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
1082 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1083 |
|
1084 for (i = 0; i < 100; i++) { |
|
1085 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
1086 break; |
|
1087 udelay(10); |
|
1088 } |
|
1089 } |
|
1090 |
|
1091 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
1092 { |
|
1093 u32 value = ~0x00; |
|
1094 unsigned int i; |
|
1095 |
|
1096 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
1097 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1098 |
|
1099 for (i = 0; i < 100; i++) { |
|
1100 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
1101 value = RTL_R32(CSIDR); |
|
1102 break; |
|
1103 } |
|
1104 udelay(10); |
|
1105 } |
|
1106 |
|
1107 return value; |
|
1108 } |
|
1109 |
|
1110 static |
|
1111 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) |
|
1112 { |
|
1113 unsigned int i; |
|
1114 |
|
1115 BUG_ON((addr & 3) || (mask == 0)); |
|
1116 RTL_W32(ERIDR, val); |
|
1117 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); |
|
1118 |
|
1119 for (i = 0; i < 100; i++) { |
|
1120 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
1121 break; |
|
1122 udelay(100); |
|
1123 } |
|
1124 } |
|
1125 |
|
1126 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) |
|
1127 { |
|
1128 u32 value = ~0x00; |
|
1129 unsigned int i; |
|
1130 |
|
1131 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); |
|
1132 |
|
1133 for (i = 0; i < 100; i++) { |
|
1134 if (RTL_R32(ERIAR) & ERIAR_FLAG) { |
|
1135 value = RTL_R32(ERIDR); |
|
1136 break; |
|
1137 } |
|
1138 udelay(100); |
|
1139 } |
|
1140 |
|
1141 return value; |
|
1142 } |
|
1143 |
|
1144 static void |
|
1145 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) |
|
1146 { |
|
1147 u32 val; |
|
1148 |
|
1149 val = rtl_eri_read(ioaddr, addr, type); |
|
1150 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); |
|
1151 } |
|
1152 |
|
1153 struct exgmac_reg { |
|
1154 u16 addr; |
|
1155 u16 mask; |
|
1156 u32 val; |
|
1157 }; |
|
1158 |
|
1159 static void rtl_write_exgmac_batch(void __iomem *ioaddr, |
|
1160 const struct exgmac_reg *r, int len) |
|
1161 { |
|
1162 while (len-- > 0) { |
|
1163 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
|
1164 r++; |
|
1165 } |
|
1166 } |
|
1167 |
|
1168 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
|
1169 { |
|
1170 u8 value = 0xff; |
|
1171 unsigned int i; |
|
1172 |
|
1173 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
1174 |
|
1175 for (i = 0; i < 300; i++) { |
|
1176 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { |
|
1177 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; |
|
1178 break; |
|
1179 } |
|
1180 udelay(100); |
|
1181 } |
|
1182 |
|
1183 return value; |
|
1184 } |
|
1185 |
|
1186 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
|
1187 { |
|
1188 void __iomem *ioaddr = tp->mmio_addr; |
|
1189 |
|
1190 RTL_W16(IntrMask, 0x0000); |
|
1191 RTL_W16(IntrStatus, tp->intr_event); |
|
1192 RTL_R8(ChipCmd); |
|
1193 } |
|
1194 |
|
1195 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
|
1196 { |
|
1197 void __iomem *ioaddr = tp->mmio_addr; |
|
1198 |
|
1199 return RTL_R32(TBICSR) & TBIReset; |
|
1200 } |
|
1201 |
|
1202 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
|
1203 { |
|
1204 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
|
1205 } |
|
1206 |
|
1207 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
1208 { |
|
1209 return RTL_R32(TBICSR) & TBILinkOk; |
|
1210 } |
|
1211 |
|
1212 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
1213 { |
|
1214 return RTL_R8(PHYstatus) & LinkStatus; |
|
1215 } |
|
1216 |
|
1217 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
|
1218 { |
|
1219 void __iomem *ioaddr = tp->mmio_addr; |
|
1220 |
|
1221 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
1222 } |
|
1223 |
|
1224 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
|
1225 { |
|
1226 unsigned int val; |
|
1227 |
|
1228 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
|
1229 rtl_writephy(tp, MII_BMCR, val & 0xffff); |
|
1230 } |
|
1231 |
|
1232 static void rtl_link_chg_patch(struct rtl8169_private *tp) |
|
1233 { |
|
1234 void __iomem *ioaddr = tp->mmio_addr; |
|
1235 struct net_device *dev = tp->dev; |
|
1236 |
|
1237 if (!netif_running(dev)) |
|
1238 return; |
|
1239 |
|
1240 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
1241 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1242 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1243 0x00000011, ERIAR_EXGMAC); |
|
1244 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1245 0x00000005, ERIAR_EXGMAC); |
|
1246 } else if (RTL_R8(PHYstatus) & _100bps) { |
|
1247 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1248 0x0000001f, ERIAR_EXGMAC); |
|
1249 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1250 0x00000005, ERIAR_EXGMAC); |
|
1251 } else { |
|
1252 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1253 0x0000001f, ERIAR_EXGMAC); |
|
1254 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1255 0x0000003f, ERIAR_EXGMAC); |
|
1256 } |
|
1257 /* Reset packet filter */ |
|
1258 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
|
1259 ERIAR_EXGMAC); |
|
1260 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
|
1261 ERIAR_EXGMAC); |
|
1262 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
1263 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
1264 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1265 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1266 0x00000011, ERIAR_EXGMAC); |
|
1267 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1268 0x00000005, ERIAR_EXGMAC); |
|
1269 } else { |
|
1270 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1271 0x0000001f, ERIAR_EXGMAC); |
|
1272 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1273 0x0000003f, ERIAR_EXGMAC); |
|
1274 } |
|
1275 } |
|
1276 } |
|
1277 |
|
1278 static void __rtl8169_check_link_status(struct net_device *dev, |
|
1279 struct rtl8169_private *tp, |
|
1280 void __iomem *ioaddr, bool pm) |
|
1281 { |
|
1282 unsigned long flags; |
|
1283 |
|
1284 spin_lock_irqsave(&tp->lock, flags); |
|
1285 if (tp->link_ok(ioaddr)) { |
|
1286 rtl_link_chg_patch(tp); |
|
1287 /* This is to cancel a scheduled suspend if there's one. */ |
|
1288 if (pm) |
|
1289 pm_request_resume(&tp->pci_dev->dev); |
|
1290 netif_carrier_on(dev); |
|
1291 if (net_ratelimit()) |
|
1292 netif_info(tp, ifup, dev, "link up\n"); |
|
1293 } else { |
|
1294 netif_carrier_off(dev); |
|
1295 netif_info(tp, ifdown, dev, "link down\n"); |
|
1296 if (pm) |
|
1297 pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
|
1298 } |
|
1299 spin_unlock_irqrestore(&tp->lock, flags); |
|
1300 } |
|
1301 |
|
1302 static void rtl8169_check_link_status(struct net_device *dev, |
|
1303 struct rtl8169_private *tp, |
|
1304 void __iomem *ioaddr) |
|
1305 { |
|
1306 __rtl8169_check_link_status(dev, tp, ioaddr, false); |
|
1307 } |
|
1308 |
|
1309 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
1310 |
|
1311 static u32 __rtl8169_get_wol(struct rtl8169_private *tp) |
|
1312 { |
|
1313 void __iomem *ioaddr = tp->mmio_addr; |
|
1314 u8 options; |
|
1315 u32 wolopts = 0; |
|
1316 |
|
1317 options = RTL_R8(Config1); |
|
1318 if (!(options & PMEnable)) |
|
1319 return 0; |
|
1320 |
|
1321 options = RTL_R8(Config3); |
|
1322 if (options & LinkUp) |
|
1323 wolopts |= WAKE_PHY; |
|
1324 if (options & MagicPacket) |
|
1325 wolopts |= WAKE_MAGIC; |
|
1326 |
|
1327 options = RTL_R8(Config5); |
|
1328 if (options & UWF) |
|
1329 wolopts |= WAKE_UCAST; |
|
1330 if (options & BWF) |
|
1331 wolopts |= WAKE_BCAST; |
|
1332 if (options & MWF) |
|
1333 wolopts |= WAKE_MCAST; |
|
1334 |
|
1335 return wolopts; |
|
1336 } |
|
1337 |
|
1338 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1339 { |
|
1340 struct rtl8169_private *tp = netdev_priv(dev); |
|
1341 |
|
1342 spin_lock_irq(&tp->lock); |
|
1343 |
|
1344 wol->supported = WAKE_ANY; |
|
1345 wol->wolopts = __rtl8169_get_wol(tp); |
|
1346 |
|
1347 spin_unlock_irq(&tp->lock); |
|
1348 } |
|
1349 |
|
1350 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) |
|
1351 { |
|
1352 void __iomem *ioaddr = tp->mmio_addr; |
|
1353 unsigned int i; |
|
1354 static const struct { |
|
1355 u32 opt; |
|
1356 u16 reg; |
|
1357 u8 mask; |
|
1358 } cfg[] = { |
|
1359 { WAKE_ANY, Config1, PMEnable }, |
|
1360 { WAKE_PHY, Config3, LinkUp }, |
|
1361 { WAKE_MAGIC, Config3, MagicPacket }, |
|
1362 { WAKE_UCAST, Config5, UWF }, |
|
1363 { WAKE_BCAST, Config5, BWF }, |
|
1364 { WAKE_MCAST, Config5, MWF }, |
|
1365 { WAKE_ANY, Config5, LanWake } |
|
1366 }; |
|
1367 |
|
1368 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1369 |
|
1370 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
1371 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
1372 if (wolopts & cfg[i].opt) |
|
1373 options |= cfg[i].mask; |
|
1374 RTL_W8(cfg[i].reg, options); |
|
1375 } |
|
1376 |
|
1377 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1378 } |
|
1379 |
|
1380 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1381 { |
|
1382 struct rtl8169_private *tp = netdev_priv(dev); |
|
1383 |
|
1384 spin_lock_irq(&tp->lock); |
|
1385 |
|
1386 if (wol->wolopts) |
|
1387 tp->features |= RTL_FEATURE_WOL; |
|
1388 else |
|
1389 tp->features &= ~RTL_FEATURE_WOL; |
|
1390 __rtl8169_set_wol(tp, wol->wolopts); |
|
1391 spin_unlock_irq(&tp->lock); |
|
1392 |
|
1393 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
1394 |
|
1395 return 0; |
|
1396 } |
|
1397 |
|
1398 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
|
1399 { |
|
1400 return rtl_chip_infos[tp->mac_version].fw_name; |
|
1401 } |
|
1402 |
|
1403 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
1404 struct ethtool_drvinfo *info) |
|
1405 { |
|
1406 struct rtl8169_private *tp = netdev_priv(dev); |
|
1407 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
1408 |
|
1409 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
|
1410 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); |
|
1411 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
|
1412 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
|
1413 strlcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" : |
|
1414 rtl_fw->version, sizeof(info->fw_version)); |
|
1415 } |
|
1416 |
|
1417 static int rtl8169_get_regs_len(struct net_device *dev) |
|
1418 { |
|
1419 return R8169_REGS_SIZE; |
|
1420 } |
|
1421 |
|
1422 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
1423 u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
|
1424 { |
|
1425 struct rtl8169_private *tp = netdev_priv(dev); |
|
1426 void __iomem *ioaddr = tp->mmio_addr; |
|
1427 int ret = 0; |
|
1428 u32 reg; |
|
1429 |
|
1430 reg = RTL_R32(TBICSR); |
|
1431 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
1432 (duplex == DUPLEX_FULL)) { |
|
1433 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
1434 } else if (autoneg == AUTONEG_ENABLE) |
|
1435 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
1436 else { |
|
1437 netif_warn(tp, link, dev, |
|
1438 "incorrect speed setting refused in TBI mode\n"); |
|
1439 ret = -EOPNOTSUPP; |
|
1440 } |
|
1441 |
|
1442 return ret; |
|
1443 } |
|
1444 |
|
1445 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
1446 u8 autoneg, u16 speed, u8 duplex, u32 adv) |
|
1447 { |
|
1448 struct rtl8169_private *tp = netdev_priv(dev); |
|
1449 int giga_ctrl, bmcr; |
|
1450 int rc = -EINVAL; |
|
1451 |
|
1452 rtl_writephy(tp, 0x1f, 0x0000); |
|
1453 |
|
1454 if (autoneg == AUTONEG_ENABLE) { |
|
1455 int auto_nego; |
|
1456 |
|
1457 auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
|
1458 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
1459 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
1460 |
|
1461 if (adv & ADVERTISED_10baseT_Half) |
|
1462 auto_nego |= ADVERTISE_10HALF; |
|
1463 if (adv & ADVERTISED_10baseT_Full) |
|
1464 auto_nego |= ADVERTISE_10FULL; |
|
1465 if (adv & ADVERTISED_100baseT_Half) |
|
1466 auto_nego |= ADVERTISE_100HALF; |
|
1467 if (adv & ADVERTISED_100baseT_Full) |
|
1468 auto_nego |= ADVERTISE_100FULL; |
|
1469 |
|
1470 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
1471 |
|
1472 giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
|
1473 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
1474 |
|
1475 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
1476 if (tp->mii.supports_gmii) { |
|
1477 if (adv & ADVERTISED_1000baseT_Half) |
|
1478 giga_ctrl |= ADVERTISE_1000HALF; |
|
1479 if (adv & ADVERTISED_1000baseT_Full) |
|
1480 giga_ctrl |= ADVERTISE_1000FULL; |
|
1481 } else if (adv & (ADVERTISED_1000baseT_Half | |
|
1482 ADVERTISED_1000baseT_Full)) { |
|
1483 netif_info(tp, link, dev, |
|
1484 "PHY does not support 1000Mbps\n"); |
|
1485 goto out; |
|
1486 } |
|
1487 |
|
1488 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
1489 |
|
1490 rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
|
1491 rtl_writephy(tp, MII_CTRL1000, giga_ctrl); |
|
1492 } else { |
|
1493 giga_ctrl = 0; |
|
1494 |
|
1495 if (speed == SPEED_10) |
|
1496 bmcr = 0; |
|
1497 else if (speed == SPEED_100) |
|
1498 bmcr = BMCR_SPEED100; |
|
1499 else |
|
1500 goto out; |
|
1501 |
|
1502 if (duplex == DUPLEX_FULL) |
|
1503 bmcr |= BMCR_FULLDPLX; |
|
1504 } |
|
1505 |
|
1506 rtl_writephy(tp, MII_BMCR, bmcr); |
|
1507 |
|
1508 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
1509 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
1510 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
1511 rtl_writephy(tp, 0x17, 0x2138); |
|
1512 rtl_writephy(tp, 0x0e, 0x0260); |
|
1513 } else { |
|
1514 rtl_writephy(tp, 0x17, 0x2108); |
|
1515 rtl_writephy(tp, 0x0e, 0x0000); |
|
1516 } |
|
1517 } |
|
1518 |
|
1519 rc = 0; |
|
1520 out: |
|
1521 return rc; |
|
1522 } |
|
1523 |
|
1524 static int rtl8169_set_speed(struct net_device *dev, |
|
1525 u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
|
1526 { |
|
1527 struct rtl8169_private *tp = netdev_priv(dev); |
|
1528 int ret; |
|
1529 |
|
1530 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
|
1531 if (ret < 0) |
|
1532 goto out; |
|
1533 |
|
1534 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
|
1535 (advertising & ADVERTISED_1000baseT_Full)) { |
|
1536 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1537 } |
|
1538 out: |
|
1539 return ret; |
|
1540 } |
|
1541 |
|
1542 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1543 { |
|
1544 struct rtl8169_private *tp = netdev_priv(dev); |
|
1545 unsigned long flags; |
|
1546 int ret; |
|
1547 |
|
1548 del_timer_sync(&tp->timer); |
|
1549 |
|
1550 spin_lock_irqsave(&tp->lock, flags); |
|
1551 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
|
1552 cmd->duplex, cmd->advertising); |
|
1553 spin_unlock_irqrestore(&tp->lock, flags); |
|
1554 |
|
1555 return ret; |
|
1556 } |
|
1557 |
|
1558 static u32 rtl8169_fix_features(struct net_device *dev, u32 features) |
|
1559 { |
|
1560 struct rtl8169_private *tp = netdev_priv(dev); |
|
1561 |
|
1562 if (dev->mtu > TD_MSS_MAX) |
|
1563 features &= ~NETIF_F_ALL_TSO; |
|
1564 |
|
1565 if (dev->mtu > JUMBO_1K && |
|
1566 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) |
|
1567 features &= ~NETIF_F_IP_CSUM; |
|
1568 |
|
1569 return features; |
|
1570 } |
|
1571 |
|
1572 static int rtl8169_set_features(struct net_device *dev, u32 features) |
|
1573 { |
|
1574 struct rtl8169_private *tp = netdev_priv(dev); |
|
1575 void __iomem *ioaddr = tp->mmio_addr; |
|
1576 unsigned long flags; |
|
1577 |
|
1578 spin_lock_irqsave(&tp->lock, flags); |
|
1579 |
|
1580 if (features & NETIF_F_RXCSUM) |
|
1581 tp->cp_cmd |= RxChkSum; |
|
1582 else |
|
1583 tp->cp_cmd &= ~RxChkSum; |
|
1584 |
|
1585 if (dev->features & NETIF_F_HW_VLAN_RX) |
|
1586 tp->cp_cmd |= RxVlan; |
|
1587 else |
|
1588 tp->cp_cmd &= ~RxVlan; |
|
1589 |
|
1590 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1591 RTL_R16(CPlusCmd); |
|
1592 |
|
1593 spin_unlock_irqrestore(&tp->lock, flags); |
|
1594 |
|
1595 return 0; |
|
1596 } |
|
1597 |
|
1598 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1599 struct sk_buff *skb) |
|
1600 { |
|
1601 return (vlan_tx_tag_present(skb)) ? |
|
1602 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1603 } |
|
1604 |
|
1605 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
|
1606 { |
|
1607 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1608 |
|
1609 if (opts2 & RxVlanTag) |
|
1610 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); |
|
1611 |
|
1612 desc->opts2 = 0; |
|
1613 } |
|
1614 |
|
1615 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1616 { |
|
1617 struct rtl8169_private *tp = netdev_priv(dev); |
|
1618 void __iomem *ioaddr = tp->mmio_addr; |
|
1619 u32 status; |
|
1620 |
|
1621 cmd->supported = |
|
1622 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1623 cmd->port = PORT_FIBRE; |
|
1624 cmd->transceiver = XCVR_INTERNAL; |
|
1625 |
|
1626 status = RTL_R32(TBICSR); |
|
1627 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1628 cmd->autoneg = !!(status & TBINwEnable); |
|
1629 |
|
1630 ethtool_cmd_speed_set(cmd, SPEED_1000); |
|
1631 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1632 |
|
1633 return 0; |
|
1634 } |
|
1635 |
|
1636 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1637 { |
|
1638 struct rtl8169_private *tp = netdev_priv(dev); |
|
1639 |
|
1640 return mii_ethtool_gset(&tp->mii, cmd); |
|
1641 } |
|
1642 |
|
1643 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1644 { |
|
1645 struct rtl8169_private *tp = netdev_priv(dev); |
|
1646 unsigned long flags; |
|
1647 int rc; |
|
1648 |
|
1649 spin_lock_irqsave(&tp->lock, flags); |
|
1650 |
|
1651 rc = tp->get_settings(dev, cmd); |
|
1652 |
|
1653 spin_unlock_irqrestore(&tp->lock, flags); |
|
1654 return rc; |
|
1655 } |
|
1656 |
|
1657 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1658 void *p) |
|
1659 { |
|
1660 struct rtl8169_private *tp = netdev_priv(dev); |
|
1661 unsigned long flags; |
|
1662 |
|
1663 if (regs->len > R8169_REGS_SIZE) |
|
1664 regs->len = R8169_REGS_SIZE; |
|
1665 |
|
1666 spin_lock_irqsave(&tp->lock, flags); |
|
1667 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1668 spin_unlock_irqrestore(&tp->lock, flags); |
|
1669 } |
|
1670 |
|
1671 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1672 { |
|
1673 struct rtl8169_private *tp = netdev_priv(dev); |
|
1674 |
|
1675 return tp->msg_enable; |
|
1676 } |
|
1677 |
|
1678 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1679 { |
|
1680 struct rtl8169_private *tp = netdev_priv(dev); |
|
1681 |
|
1682 tp->msg_enable = value; |
|
1683 } |
|
1684 |
|
1685 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1686 "tx_packets", |
|
1687 "rx_packets", |
|
1688 "tx_errors", |
|
1689 "rx_errors", |
|
1690 "rx_missed", |
|
1691 "align_errors", |
|
1692 "tx_single_collisions", |
|
1693 "tx_multi_collisions", |
|
1694 "unicast", |
|
1695 "broadcast", |
|
1696 "multicast", |
|
1697 "tx_aborted", |
|
1698 "tx_underrun", |
|
1699 }; |
|
1700 |
|
1701 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1702 { |
|
1703 switch (sset) { |
|
1704 case ETH_SS_STATS: |
|
1705 return ARRAY_SIZE(rtl8169_gstrings); |
|
1706 default: |
|
1707 return -EOPNOTSUPP; |
|
1708 } |
|
1709 } |
|
1710 |
|
1711 static void rtl8169_update_counters(struct net_device *dev) |
|
1712 { |
|
1713 struct rtl8169_private *tp = netdev_priv(dev); |
|
1714 void __iomem *ioaddr = tp->mmio_addr; |
|
1715 struct device *d = &tp->pci_dev->dev; |
|
1716 struct rtl8169_counters *counters; |
|
1717 dma_addr_t paddr; |
|
1718 u32 cmd; |
|
1719 int wait = 1000; |
|
1720 |
|
1721 /* |
|
1722 * Some chips are unable to dump tally counters when the receiver |
|
1723 * is disabled. |
|
1724 */ |
|
1725 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1726 return; |
|
1727 |
|
1728 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
|
1729 if (!counters) |
|
1730 return; |
|
1731 |
|
1732 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1733 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1734 RTL_W32(CounterAddrLow, cmd); |
|
1735 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1736 |
|
1737 while (wait--) { |
|
1738 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1739 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1740 break; |
|
1741 } |
|
1742 udelay(10); |
|
1743 } |
|
1744 |
|
1745 RTL_W32(CounterAddrLow, 0); |
|
1746 RTL_W32(CounterAddrHigh, 0); |
|
1747 |
|
1748 dma_free_coherent(d, sizeof(*counters), counters, paddr); |
|
1749 } |
|
1750 |
|
1751 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1752 struct ethtool_stats *stats, u64 *data) |
|
1753 { |
|
1754 struct rtl8169_private *tp = netdev_priv(dev); |
|
1755 |
|
1756 ASSERT_RTNL(); |
|
1757 |
|
1758 rtl8169_update_counters(dev); |
|
1759 |
|
1760 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1761 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1762 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1763 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1764 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1765 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1766 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1767 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1768 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1769 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1770 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1771 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1772 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1773 } |
|
1774 |
|
1775 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1776 { |
|
1777 switch(stringset) { |
|
1778 case ETH_SS_STATS: |
|
1779 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1780 break; |
|
1781 } |
|
1782 } |
|
1783 |
|
1784 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1785 .get_drvinfo = rtl8169_get_drvinfo, |
|
1786 .get_regs_len = rtl8169_get_regs_len, |
|
1787 .get_link = ethtool_op_get_link, |
|
1788 .get_settings = rtl8169_get_settings, |
|
1789 .set_settings = rtl8169_set_settings, |
|
1790 .get_msglevel = rtl8169_get_msglevel, |
|
1791 .set_msglevel = rtl8169_set_msglevel, |
|
1792 .get_regs = rtl8169_get_regs, |
|
1793 .get_wol = rtl8169_get_wol, |
|
1794 .set_wol = rtl8169_set_wol, |
|
1795 .get_strings = rtl8169_get_strings, |
|
1796 .get_sset_count = rtl8169_get_sset_count, |
|
1797 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1798 }; |
|
1799 |
|
1800 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1801 struct net_device *dev, u8 default_version) |
|
1802 { |
|
1803 void __iomem *ioaddr = tp->mmio_addr; |
|
1804 /* |
|
1805 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1806 * but they can be identified more specifically through the test below |
|
1807 * if needed: |
|
1808 * |
|
1809 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1810 * |
|
1811 * Same thing for the 8101Eb and the 8101Ec: |
|
1812 * |
|
1813 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1814 */ |
|
1815 static const struct rtl_mac_info { |
|
1816 u32 mask; |
|
1817 u32 val; |
|
1818 int mac_version; |
|
1819 } mac_info[] = { |
|
1820 /* 8168F family. */ |
|
1821 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
|
1822 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, |
|
1823 |
|
1824 /* 8168E family. */ |
|
1825 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
|
1826 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
|
1827 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, |
|
1828 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, |
|
1829 |
|
1830 /* 8168D family. */ |
|
1831 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
1832 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
1833 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
1834 |
|
1835 /* 8168DP family. */ |
|
1836 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
1837 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, |
|
1838 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
|
1839 |
|
1840 /* 8168C family. */ |
|
1841 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
|
1842 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1843 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1844 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1845 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1846 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1847 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1848 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1849 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1850 |
|
1851 /* 8168B family. */ |
|
1852 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1853 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1854 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1855 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1856 |
|
1857 /* 8101 family. */ |
|
1858 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
|
1859 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
|
1860 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, |
|
1861 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, |
|
1862 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1863 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1864 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1865 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1866 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1867 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1868 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1869 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1870 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1871 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1872 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1873 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1874 /* FIXME: where did these entries come from ? -- FR */ |
|
1875 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1876 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1877 |
|
1878 /* 8110 family. */ |
|
1879 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1880 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1881 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1882 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1883 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1884 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1885 |
|
1886 /* Catch-all */ |
|
1887 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1888 }; |
|
1889 const struct rtl_mac_info *p = mac_info; |
|
1890 u32 reg; |
|
1891 |
|
1892 reg = RTL_R32(TxConfig); |
|
1893 while ((reg & p->mask) != p->val) |
|
1894 p++; |
|
1895 tp->mac_version = p->mac_version; |
|
1896 |
|
1897 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
1898 netif_notice(tp, probe, dev, |
|
1899 "unknown MAC, using family default\n"); |
|
1900 tp->mac_version = default_version; |
|
1901 } |
|
1902 } |
|
1903 |
|
1904 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1905 { |
|
1906 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1907 } |
|
1908 |
|
1909 struct phy_reg { |
|
1910 u16 reg; |
|
1911 u16 val; |
|
1912 }; |
|
1913 |
|
1914 static void rtl_writephy_batch(struct rtl8169_private *tp, |
|
1915 const struct phy_reg *regs, int len) |
|
1916 { |
|
1917 while (len-- > 0) { |
|
1918 rtl_writephy(tp, regs->reg, regs->val); |
|
1919 regs++; |
|
1920 } |
|
1921 } |
|
1922 |
|
1923 #define PHY_READ 0x00000000 |
|
1924 #define PHY_DATA_OR 0x10000000 |
|
1925 #define PHY_DATA_AND 0x20000000 |
|
1926 #define PHY_BJMPN 0x30000000 |
|
1927 #define PHY_READ_EFUSE 0x40000000 |
|
1928 #define PHY_READ_MAC_BYTE 0x50000000 |
|
1929 #define PHY_WRITE_MAC_BYTE 0x60000000 |
|
1930 #define PHY_CLEAR_READCOUNT 0x70000000 |
|
1931 #define PHY_WRITE 0x80000000 |
|
1932 #define PHY_READCOUNT_EQ_SKIP 0x90000000 |
|
1933 #define PHY_COMP_EQ_SKIPN 0xa0000000 |
|
1934 #define PHY_COMP_NEQ_SKIPN 0xb0000000 |
|
1935 #define PHY_WRITE_PREVIOUS 0xc0000000 |
|
1936 #define PHY_SKIPN 0xd0000000 |
|
1937 #define PHY_DELAY_MS 0xe0000000 |
|
1938 #define PHY_WRITE_ERI_WORD 0xf0000000 |
|
1939 |
|
1940 struct fw_info { |
|
1941 u32 magic; |
|
1942 char version[RTL_VER_SIZE]; |
|
1943 __le32 fw_start; |
|
1944 __le32 fw_len; |
|
1945 u8 chksum; |
|
1946 } __packed; |
|
1947 |
|
1948 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
|
1949 |
|
1950 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
1951 { |
|
1952 const struct firmware *fw = rtl_fw->fw; |
|
1953 struct fw_info *fw_info = (struct fw_info *)fw->data; |
|
1954 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
1955 char *version = rtl_fw->version; |
|
1956 bool rc = false; |
|
1957 |
|
1958 if (fw->size < FW_OPCODE_SIZE) |
|
1959 goto out; |
|
1960 |
|
1961 if (!fw_info->magic) { |
|
1962 size_t i, size, start; |
|
1963 u8 checksum = 0; |
|
1964 |
|
1965 if (fw->size < sizeof(*fw_info)) |
|
1966 goto out; |
|
1967 |
|
1968 for (i = 0; i < fw->size; i++) |
|
1969 checksum += fw->data[i]; |
|
1970 if (checksum != 0) |
|
1971 goto out; |
|
1972 |
|
1973 start = le32_to_cpu(fw_info->fw_start); |
|
1974 if (start > fw->size) |
|
1975 goto out; |
|
1976 |
|
1977 size = le32_to_cpu(fw_info->fw_len); |
|
1978 if (size > (fw->size - start) / FW_OPCODE_SIZE) |
|
1979 goto out; |
|
1980 |
|
1981 memcpy(version, fw_info->version, RTL_VER_SIZE); |
|
1982 |
|
1983 pa->code = (__le32 *)(fw->data + start); |
|
1984 pa->size = size; |
|
1985 } else { |
|
1986 if (fw->size % FW_OPCODE_SIZE) |
|
1987 goto out; |
|
1988 |
|
1989 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); |
|
1990 |
|
1991 pa->code = (__le32 *)fw->data; |
|
1992 pa->size = fw->size / FW_OPCODE_SIZE; |
|
1993 } |
|
1994 version[RTL_VER_SIZE - 1] = 0; |
|
1995 |
|
1996 rc = true; |
|
1997 out: |
|
1998 return rc; |
|
1999 } |
|
2000 |
|
2001 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
|
2002 struct rtl_fw_phy_action *pa) |
|
2003 { |
|
2004 bool rc = false; |
|
2005 size_t index; |
|
2006 |
|
2007 for (index = 0; index < pa->size; index++) { |
|
2008 u32 action = le32_to_cpu(pa->code[index]); |
|
2009 u32 regno = (action & 0x0fff0000) >> 16; |
|
2010 |
|
2011 switch(action & 0xf0000000) { |
|
2012 case PHY_READ: |
|
2013 case PHY_DATA_OR: |
|
2014 case PHY_DATA_AND: |
|
2015 case PHY_READ_EFUSE: |
|
2016 case PHY_CLEAR_READCOUNT: |
|
2017 case PHY_WRITE: |
|
2018 case PHY_WRITE_PREVIOUS: |
|
2019 case PHY_DELAY_MS: |
|
2020 break; |
|
2021 |
|
2022 case PHY_BJMPN: |
|
2023 if (regno > index) { |
|
2024 netif_err(tp, ifup, tp->dev, |
|
2025 "Out of range of firmware\n"); |
|
2026 goto out; |
|
2027 } |
|
2028 break; |
|
2029 case PHY_READCOUNT_EQ_SKIP: |
|
2030 if (index + 2 >= pa->size) { |
|
2031 netif_err(tp, ifup, tp->dev, |
|
2032 "Out of range of firmware\n"); |
|
2033 goto out; |
|
2034 } |
|
2035 break; |
|
2036 case PHY_COMP_EQ_SKIPN: |
|
2037 case PHY_COMP_NEQ_SKIPN: |
|
2038 case PHY_SKIPN: |
|
2039 if (index + 1 + regno >= pa->size) { |
|
2040 netif_err(tp, ifup, tp->dev, |
|
2041 "Out of range of firmware\n"); |
|
2042 goto out; |
|
2043 } |
|
2044 break; |
|
2045 |
|
2046 case PHY_READ_MAC_BYTE: |
|
2047 case PHY_WRITE_MAC_BYTE: |
|
2048 case PHY_WRITE_ERI_WORD: |
|
2049 default: |
|
2050 netif_err(tp, ifup, tp->dev, |
|
2051 "Invalid action 0x%08x\n", action); |
|
2052 goto out; |
|
2053 } |
|
2054 } |
|
2055 rc = true; |
|
2056 out: |
|
2057 return rc; |
|
2058 } |
|
2059 |
|
2060 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2061 { |
|
2062 struct net_device *dev = tp->dev; |
|
2063 int rc = -EINVAL; |
|
2064 |
|
2065 if (!rtl_fw_format_ok(tp, rtl_fw)) { |
|
2066 netif_err(tp, ifup, dev, "invalid firwmare\n"); |
|
2067 goto out; |
|
2068 } |
|
2069 |
|
2070 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) |
|
2071 rc = 0; |
|
2072 out: |
|
2073 return rc; |
|
2074 } |
|
2075 |
|
2076 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2077 { |
|
2078 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2079 u32 predata, count; |
|
2080 size_t index; |
|
2081 |
|
2082 predata = count = 0; |
|
2083 |
|
2084 for (index = 0; index < pa->size; ) { |
|
2085 u32 action = le32_to_cpu(pa->code[index]); |
|
2086 u32 data = action & 0x0000ffff; |
|
2087 u32 regno = (action & 0x0fff0000) >> 16; |
|
2088 |
|
2089 if (!action) |
|
2090 break; |
|
2091 |
|
2092 switch(action & 0xf0000000) { |
|
2093 case PHY_READ: |
|
2094 predata = rtl_readphy(tp, regno); |
|
2095 count++; |
|
2096 index++; |
|
2097 break; |
|
2098 case PHY_DATA_OR: |
|
2099 predata |= data; |
|
2100 index++; |
|
2101 break; |
|
2102 case PHY_DATA_AND: |
|
2103 predata &= data; |
|
2104 index++; |
|
2105 break; |
|
2106 case PHY_BJMPN: |
|
2107 index -= regno; |
|
2108 break; |
|
2109 case PHY_READ_EFUSE: |
|
2110 predata = rtl8168d_efuse_read(tp->mmio_addr, regno); |
|
2111 index++; |
|
2112 break; |
|
2113 case PHY_CLEAR_READCOUNT: |
|
2114 count = 0; |
|
2115 index++; |
|
2116 break; |
|
2117 case PHY_WRITE: |
|
2118 rtl_writephy(tp, regno, data); |
|
2119 index++; |
|
2120 break; |
|
2121 case PHY_READCOUNT_EQ_SKIP: |
|
2122 index += (count == data) ? 2 : 1; |
|
2123 break; |
|
2124 case PHY_COMP_EQ_SKIPN: |
|
2125 if (predata == data) |
|
2126 index += regno; |
|
2127 index++; |
|
2128 break; |
|
2129 case PHY_COMP_NEQ_SKIPN: |
|
2130 if (predata != data) |
|
2131 index += regno; |
|
2132 index++; |
|
2133 break; |
|
2134 case PHY_WRITE_PREVIOUS: |
|
2135 rtl_writephy(tp, regno, predata); |
|
2136 index++; |
|
2137 break; |
|
2138 case PHY_SKIPN: |
|
2139 index += regno + 1; |
|
2140 break; |
|
2141 case PHY_DELAY_MS: |
|
2142 mdelay(data); |
|
2143 index++; |
|
2144 break; |
|
2145 |
|
2146 case PHY_READ_MAC_BYTE: |
|
2147 case PHY_WRITE_MAC_BYTE: |
|
2148 case PHY_WRITE_ERI_WORD: |
|
2149 default: |
|
2150 BUG(); |
|
2151 } |
|
2152 } |
|
2153 } |
|
2154 |
|
2155 static void rtl_release_firmware(struct rtl8169_private *tp) |
|
2156 { |
|
2157 if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
|
2158 release_firmware(tp->rtl_fw->fw); |
|
2159 kfree(tp->rtl_fw); |
|
2160 } |
|
2161 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
2162 } |
|
2163 |
|
2164 static void rtl_apply_firmware(struct rtl8169_private *tp) |
|
2165 { |
|
2166 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
2167 |
|
2168 /* TODO: release firmware once rtl_phy_write_fw signals failures. */ |
|
2169 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
2170 rtl_phy_write_fw(tp, rtl_fw); |
|
2171 } |
|
2172 |
|
2173 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) |
|
2174 { |
|
2175 if (rtl_readphy(tp, reg) != val) |
|
2176 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); |
|
2177 else |
|
2178 rtl_apply_firmware(tp); |
|
2179 } |
|
2180 |
|
2181 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
|
2182 { |
|
2183 static const struct phy_reg phy_reg_init[] = { |
|
2184 { 0x1f, 0x0001 }, |
|
2185 { 0x06, 0x006e }, |
|
2186 { 0x08, 0x0708 }, |
|
2187 { 0x15, 0x4000 }, |
|
2188 { 0x18, 0x65c7 }, |
|
2189 |
|
2190 { 0x1f, 0x0001 }, |
|
2191 { 0x03, 0x00a1 }, |
|
2192 { 0x02, 0x0008 }, |
|
2193 { 0x01, 0x0120 }, |
|
2194 { 0x00, 0x1000 }, |
|
2195 { 0x04, 0x0800 }, |
|
2196 { 0x04, 0x0000 }, |
|
2197 |
|
2198 { 0x03, 0xff41 }, |
|
2199 { 0x02, 0xdf60 }, |
|
2200 { 0x01, 0x0140 }, |
|
2201 { 0x00, 0x0077 }, |
|
2202 { 0x04, 0x7800 }, |
|
2203 { 0x04, 0x7000 }, |
|
2204 |
|
2205 { 0x03, 0x802f }, |
|
2206 { 0x02, 0x4f02 }, |
|
2207 { 0x01, 0x0409 }, |
|
2208 { 0x00, 0xf0f9 }, |
|
2209 { 0x04, 0x9800 }, |
|
2210 { 0x04, 0x9000 }, |
|
2211 |
|
2212 { 0x03, 0xdf01 }, |
|
2213 { 0x02, 0xdf20 }, |
|
2214 { 0x01, 0xff95 }, |
|
2215 { 0x00, 0xba00 }, |
|
2216 { 0x04, 0xa800 }, |
|
2217 { 0x04, 0xa000 }, |
|
2218 |
|
2219 { 0x03, 0xff41 }, |
|
2220 { 0x02, 0xdf20 }, |
|
2221 { 0x01, 0x0140 }, |
|
2222 { 0x00, 0x00bb }, |
|
2223 { 0x04, 0xb800 }, |
|
2224 { 0x04, 0xb000 }, |
|
2225 |
|
2226 { 0x03, 0xdf41 }, |
|
2227 { 0x02, 0xdc60 }, |
|
2228 { 0x01, 0x6340 }, |
|
2229 { 0x00, 0x007d }, |
|
2230 { 0x04, 0xd800 }, |
|
2231 { 0x04, 0xd000 }, |
|
2232 |
|
2233 { 0x03, 0xdf01 }, |
|
2234 { 0x02, 0xdf20 }, |
|
2235 { 0x01, 0x100a }, |
|
2236 { 0x00, 0xa0ff }, |
|
2237 { 0x04, 0xf800 }, |
|
2238 { 0x04, 0xf000 }, |
|
2239 |
|
2240 { 0x1f, 0x0000 }, |
|
2241 { 0x0b, 0x0000 }, |
|
2242 { 0x00, 0x9200 } |
|
2243 }; |
|
2244 |
|
2245 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2246 } |
|
2247 |
|
2248 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
|
2249 { |
|
2250 static const struct phy_reg phy_reg_init[] = { |
|
2251 { 0x1f, 0x0002 }, |
|
2252 { 0x01, 0x90d0 }, |
|
2253 { 0x1f, 0x0000 } |
|
2254 }; |
|
2255 |
|
2256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2257 } |
|
2258 |
|
2259 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
|
2260 { |
|
2261 struct pci_dev *pdev = tp->pci_dev; |
|
2262 |
|
2263 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
|
2264 (pdev->subsystem_device != 0xe000)) |
|
2265 return; |
|
2266 |
|
2267 rtl_writephy(tp, 0x1f, 0x0001); |
|
2268 rtl_writephy(tp, 0x10, 0xf01b); |
|
2269 rtl_writephy(tp, 0x1f, 0x0000); |
|
2270 } |
|
2271 |
|
2272 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
|
2273 { |
|
2274 static const struct phy_reg phy_reg_init[] = { |
|
2275 { 0x1f, 0x0001 }, |
|
2276 { 0x04, 0x0000 }, |
|
2277 { 0x03, 0x00a1 }, |
|
2278 { 0x02, 0x0008 }, |
|
2279 { 0x01, 0x0120 }, |
|
2280 { 0x00, 0x1000 }, |
|
2281 { 0x04, 0x0800 }, |
|
2282 { 0x04, 0x9000 }, |
|
2283 { 0x03, 0x802f }, |
|
2284 { 0x02, 0x4f02 }, |
|
2285 { 0x01, 0x0409 }, |
|
2286 { 0x00, 0xf099 }, |
|
2287 { 0x04, 0x9800 }, |
|
2288 { 0x04, 0xa000 }, |
|
2289 { 0x03, 0xdf01 }, |
|
2290 { 0x02, 0xdf20 }, |
|
2291 { 0x01, 0xff95 }, |
|
2292 { 0x00, 0xba00 }, |
|
2293 { 0x04, 0xa800 }, |
|
2294 { 0x04, 0xf000 }, |
|
2295 { 0x03, 0xdf01 }, |
|
2296 { 0x02, 0xdf20 }, |
|
2297 { 0x01, 0x101a }, |
|
2298 { 0x00, 0xa0ff }, |
|
2299 { 0x04, 0xf800 }, |
|
2300 { 0x04, 0x0000 }, |
|
2301 { 0x1f, 0x0000 }, |
|
2302 |
|
2303 { 0x1f, 0x0001 }, |
|
2304 { 0x10, 0xf41b }, |
|
2305 { 0x14, 0xfb54 }, |
|
2306 { 0x18, 0xf5c7 }, |
|
2307 { 0x1f, 0x0000 }, |
|
2308 |
|
2309 { 0x1f, 0x0001 }, |
|
2310 { 0x17, 0x0cc0 }, |
|
2311 { 0x1f, 0x0000 } |
|
2312 }; |
|
2313 |
|
2314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2315 |
|
2316 rtl8169scd_hw_phy_config_quirk(tp); |
|
2317 } |
|
2318 |
|
2319 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
|
2320 { |
|
2321 static const struct phy_reg phy_reg_init[] = { |
|
2322 { 0x1f, 0x0001 }, |
|
2323 { 0x04, 0x0000 }, |
|
2324 { 0x03, 0x00a1 }, |
|
2325 { 0x02, 0x0008 }, |
|
2326 { 0x01, 0x0120 }, |
|
2327 { 0x00, 0x1000 }, |
|
2328 { 0x04, 0x0800 }, |
|
2329 { 0x04, 0x9000 }, |
|
2330 { 0x03, 0x802f }, |
|
2331 { 0x02, 0x4f02 }, |
|
2332 { 0x01, 0x0409 }, |
|
2333 { 0x00, 0xf099 }, |
|
2334 { 0x04, 0x9800 }, |
|
2335 { 0x04, 0xa000 }, |
|
2336 { 0x03, 0xdf01 }, |
|
2337 { 0x02, 0xdf20 }, |
|
2338 { 0x01, 0xff95 }, |
|
2339 { 0x00, 0xba00 }, |
|
2340 { 0x04, 0xa800 }, |
|
2341 { 0x04, 0xf000 }, |
|
2342 { 0x03, 0xdf01 }, |
|
2343 { 0x02, 0xdf20 }, |
|
2344 { 0x01, 0x101a }, |
|
2345 { 0x00, 0xa0ff }, |
|
2346 { 0x04, 0xf800 }, |
|
2347 { 0x04, 0x0000 }, |
|
2348 { 0x1f, 0x0000 }, |
|
2349 |
|
2350 { 0x1f, 0x0001 }, |
|
2351 { 0x0b, 0x8480 }, |
|
2352 { 0x1f, 0x0000 }, |
|
2353 |
|
2354 { 0x1f, 0x0001 }, |
|
2355 { 0x18, 0x67c7 }, |
|
2356 { 0x04, 0x2000 }, |
|
2357 { 0x03, 0x002f }, |
|
2358 { 0x02, 0x4360 }, |
|
2359 { 0x01, 0x0109 }, |
|
2360 { 0x00, 0x3022 }, |
|
2361 { 0x04, 0x2800 }, |
|
2362 { 0x1f, 0x0000 }, |
|
2363 |
|
2364 { 0x1f, 0x0001 }, |
|
2365 { 0x17, 0x0cc0 }, |
|
2366 { 0x1f, 0x0000 } |
|
2367 }; |
|
2368 |
|
2369 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2370 } |
|
2371 |
|
2372 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
|
2373 { |
|
2374 static const struct phy_reg phy_reg_init[] = { |
|
2375 { 0x10, 0xf41b }, |
|
2376 { 0x1f, 0x0000 } |
|
2377 }; |
|
2378 |
|
2379 rtl_writephy(tp, 0x1f, 0x0001); |
|
2380 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2381 |
|
2382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2383 } |
|
2384 |
|
2385 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
|
2386 { |
|
2387 static const struct phy_reg phy_reg_init[] = { |
|
2388 { 0x1f, 0x0001 }, |
|
2389 { 0x10, 0xf41b }, |
|
2390 { 0x1f, 0x0000 } |
|
2391 }; |
|
2392 |
|
2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2394 } |
|
2395 |
|
2396 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
|
2397 { |
|
2398 static const struct phy_reg phy_reg_init[] = { |
|
2399 { 0x1f, 0x0000 }, |
|
2400 { 0x1d, 0x0f00 }, |
|
2401 { 0x1f, 0x0002 }, |
|
2402 { 0x0c, 0x1ec8 }, |
|
2403 { 0x1f, 0x0000 } |
|
2404 }; |
|
2405 |
|
2406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2407 } |
|
2408 |
|
2409 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
|
2410 { |
|
2411 static const struct phy_reg phy_reg_init[] = { |
|
2412 { 0x1f, 0x0001 }, |
|
2413 { 0x1d, 0x3d98 }, |
|
2414 { 0x1f, 0x0000 } |
|
2415 }; |
|
2416 |
|
2417 rtl_writephy(tp, 0x1f, 0x0000); |
|
2418 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2419 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2420 |
|
2421 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2422 } |
|
2423 |
|
2424 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
|
2425 { |
|
2426 static const struct phy_reg phy_reg_init[] = { |
|
2427 { 0x1f, 0x0001 }, |
|
2428 { 0x12, 0x2300 }, |
|
2429 { 0x1f, 0x0002 }, |
|
2430 { 0x00, 0x88d4 }, |
|
2431 { 0x01, 0x82b1 }, |
|
2432 { 0x03, 0x7002 }, |
|
2433 { 0x08, 0x9e30 }, |
|
2434 { 0x09, 0x01f0 }, |
|
2435 { 0x0a, 0x5500 }, |
|
2436 { 0x0c, 0x00c8 }, |
|
2437 { 0x1f, 0x0003 }, |
|
2438 { 0x12, 0xc096 }, |
|
2439 { 0x16, 0x000a }, |
|
2440 { 0x1f, 0x0000 }, |
|
2441 { 0x1f, 0x0000 }, |
|
2442 { 0x09, 0x2000 }, |
|
2443 { 0x09, 0x0000 } |
|
2444 }; |
|
2445 |
|
2446 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2447 |
|
2448 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2449 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2450 rtl_writephy(tp, 0x1f, 0x0000); |
|
2451 } |
|
2452 |
|
2453 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
|
2454 { |
|
2455 static const struct phy_reg phy_reg_init[] = { |
|
2456 { 0x1f, 0x0001 }, |
|
2457 { 0x12, 0x2300 }, |
|
2458 { 0x03, 0x802f }, |
|
2459 { 0x02, 0x4f02 }, |
|
2460 { 0x01, 0x0409 }, |
|
2461 { 0x00, 0xf099 }, |
|
2462 { 0x04, 0x9800 }, |
|
2463 { 0x04, 0x9000 }, |
|
2464 { 0x1d, 0x3d98 }, |
|
2465 { 0x1f, 0x0002 }, |
|
2466 { 0x0c, 0x7eb8 }, |
|
2467 { 0x06, 0x0761 }, |
|
2468 { 0x1f, 0x0003 }, |
|
2469 { 0x16, 0x0f0a }, |
|
2470 { 0x1f, 0x0000 } |
|
2471 }; |
|
2472 |
|
2473 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2474 |
|
2475 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2476 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2477 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2478 rtl_writephy(tp, 0x1f, 0x0000); |
|
2479 } |
|
2480 |
|
2481 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
|
2482 { |
|
2483 static const struct phy_reg phy_reg_init[] = { |
|
2484 { 0x1f, 0x0001 }, |
|
2485 { 0x12, 0x2300 }, |
|
2486 { 0x1d, 0x3d98 }, |
|
2487 { 0x1f, 0x0002 }, |
|
2488 { 0x0c, 0x7eb8 }, |
|
2489 { 0x06, 0x5461 }, |
|
2490 { 0x1f, 0x0003 }, |
|
2491 { 0x16, 0x0f0a }, |
|
2492 { 0x1f, 0x0000 } |
|
2493 }; |
|
2494 |
|
2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2496 |
|
2497 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2498 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2499 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2500 rtl_writephy(tp, 0x1f, 0x0000); |
|
2501 } |
|
2502 |
|
2503 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
|
2504 { |
|
2505 rtl8168c_3_hw_phy_config(tp); |
|
2506 } |
|
2507 |
|
2508 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
|
2509 { |
|
2510 static const struct phy_reg phy_reg_init_0[] = { |
|
2511 /* Channel Estimation */ |
|
2512 { 0x1f, 0x0001 }, |
|
2513 { 0x06, 0x4064 }, |
|
2514 { 0x07, 0x2863 }, |
|
2515 { 0x08, 0x059c }, |
|
2516 { 0x09, 0x26b4 }, |
|
2517 { 0x0a, 0x6a19 }, |
|
2518 { 0x0b, 0xdcc8 }, |
|
2519 { 0x10, 0xf06d }, |
|
2520 { 0x14, 0x7f68 }, |
|
2521 { 0x18, 0x7fd9 }, |
|
2522 { 0x1c, 0xf0ff }, |
|
2523 { 0x1d, 0x3d9c }, |
|
2524 { 0x1f, 0x0003 }, |
|
2525 { 0x12, 0xf49f }, |
|
2526 { 0x13, 0x070b }, |
|
2527 { 0x1a, 0x05ad }, |
|
2528 { 0x14, 0x94c0 }, |
|
2529 |
|
2530 /* |
|
2531 * Tx Error Issue |
|
2532 * Enhance line driver power |
|
2533 */ |
|
2534 { 0x1f, 0x0002 }, |
|
2535 { 0x06, 0x5561 }, |
|
2536 { 0x1f, 0x0005 }, |
|
2537 { 0x05, 0x8332 }, |
|
2538 { 0x06, 0x5561 }, |
|
2539 |
|
2540 /* |
|
2541 * Can not link to 1Gbps with bad cable |
|
2542 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2543 */ |
|
2544 { 0x1f, 0x0001 }, |
|
2545 { 0x17, 0x0cc0 }, |
|
2546 |
|
2547 { 0x1f, 0x0000 }, |
|
2548 { 0x0d, 0xf880 } |
|
2549 }; |
|
2550 void __iomem *ioaddr = tp->mmio_addr; |
|
2551 |
|
2552 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2553 |
|
2554 /* |
|
2555 * Rx Error Issue |
|
2556 * Fine Tune Switching regulator parameter |
|
2557 */ |
|
2558 rtl_writephy(tp, 0x1f, 0x0002); |
|
2559 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); |
|
2560 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); |
|
2561 |
|
2562 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2563 static const struct phy_reg phy_reg_init[] = { |
|
2564 { 0x1f, 0x0002 }, |
|
2565 { 0x05, 0x669a }, |
|
2566 { 0x1f, 0x0005 }, |
|
2567 { 0x05, 0x8330 }, |
|
2568 { 0x06, 0x669a }, |
|
2569 { 0x1f, 0x0002 } |
|
2570 }; |
|
2571 int val; |
|
2572 |
|
2573 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2574 |
|
2575 val = rtl_readphy(tp, 0x0d); |
|
2576 |
|
2577 if ((val & 0x00ff) != 0x006c) { |
|
2578 static const u32 set[] = { |
|
2579 0x0065, 0x0066, 0x0067, 0x0068, |
|
2580 0x0069, 0x006a, 0x006b, 0x006c |
|
2581 }; |
|
2582 int i; |
|
2583 |
|
2584 rtl_writephy(tp, 0x1f, 0x0002); |
|
2585 |
|
2586 val &= 0xff00; |
|
2587 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2588 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2589 } |
|
2590 } else { |
|
2591 static const struct phy_reg phy_reg_init[] = { |
|
2592 { 0x1f, 0x0002 }, |
|
2593 { 0x05, 0x6662 }, |
|
2594 { 0x1f, 0x0005 }, |
|
2595 { 0x05, 0x8330 }, |
|
2596 { 0x06, 0x6662 } |
|
2597 }; |
|
2598 |
|
2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2600 } |
|
2601 |
|
2602 /* RSET couple improve */ |
|
2603 rtl_writephy(tp, 0x1f, 0x0002); |
|
2604 rtl_patchphy(tp, 0x0d, 0x0300); |
|
2605 rtl_patchphy(tp, 0x0f, 0x0010); |
|
2606 |
|
2607 /* Fine tune PLL performance */ |
|
2608 rtl_writephy(tp, 0x1f, 0x0002); |
|
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2611 |
|
2612 rtl_writephy(tp, 0x1f, 0x0005); |
|
2613 rtl_writephy(tp, 0x05, 0x001b); |
|
2614 |
|
2615 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); |
|
2616 |
|
2617 rtl_writephy(tp, 0x1f, 0x0000); |
|
2618 } |
|
2619 |
|
2620 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
|
2621 { |
|
2622 static const struct phy_reg phy_reg_init_0[] = { |
|
2623 /* Channel Estimation */ |
|
2624 { 0x1f, 0x0001 }, |
|
2625 { 0x06, 0x4064 }, |
|
2626 { 0x07, 0x2863 }, |
|
2627 { 0x08, 0x059c }, |
|
2628 { 0x09, 0x26b4 }, |
|
2629 { 0x0a, 0x6a19 }, |
|
2630 { 0x0b, 0xdcc8 }, |
|
2631 { 0x10, 0xf06d }, |
|
2632 { 0x14, 0x7f68 }, |
|
2633 { 0x18, 0x7fd9 }, |
|
2634 { 0x1c, 0xf0ff }, |
|
2635 { 0x1d, 0x3d9c }, |
|
2636 { 0x1f, 0x0003 }, |
|
2637 { 0x12, 0xf49f }, |
|
2638 { 0x13, 0x070b }, |
|
2639 { 0x1a, 0x05ad }, |
|
2640 { 0x14, 0x94c0 }, |
|
2641 |
|
2642 /* |
|
2643 * Tx Error Issue |
|
2644 * Enhance line driver power |
|
2645 */ |
|
2646 { 0x1f, 0x0002 }, |
|
2647 { 0x06, 0x5561 }, |
|
2648 { 0x1f, 0x0005 }, |
|
2649 { 0x05, 0x8332 }, |
|
2650 { 0x06, 0x5561 }, |
|
2651 |
|
2652 /* |
|
2653 * Can not link to 1Gbps with bad cable |
|
2654 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2655 */ |
|
2656 { 0x1f, 0x0001 }, |
|
2657 { 0x17, 0x0cc0 }, |
|
2658 |
|
2659 { 0x1f, 0x0000 }, |
|
2660 { 0x0d, 0xf880 } |
|
2661 }; |
|
2662 void __iomem *ioaddr = tp->mmio_addr; |
|
2663 |
|
2664 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2665 |
|
2666 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2667 static const struct phy_reg phy_reg_init[] = { |
|
2668 { 0x1f, 0x0002 }, |
|
2669 { 0x05, 0x669a }, |
|
2670 { 0x1f, 0x0005 }, |
|
2671 { 0x05, 0x8330 }, |
|
2672 { 0x06, 0x669a }, |
|
2673 |
|
2674 { 0x1f, 0x0002 } |
|
2675 }; |
|
2676 int val; |
|
2677 |
|
2678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2679 |
|
2680 val = rtl_readphy(tp, 0x0d); |
|
2681 if ((val & 0x00ff) != 0x006c) { |
|
2682 static const u32 set[] = { |
|
2683 0x0065, 0x0066, 0x0067, 0x0068, |
|
2684 0x0069, 0x006a, 0x006b, 0x006c |
|
2685 }; |
|
2686 int i; |
|
2687 |
|
2688 rtl_writephy(tp, 0x1f, 0x0002); |
|
2689 |
|
2690 val &= 0xff00; |
|
2691 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2692 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2693 } |
|
2694 } else { |
|
2695 static const struct phy_reg phy_reg_init[] = { |
|
2696 { 0x1f, 0x0002 }, |
|
2697 { 0x05, 0x2642 }, |
|
2698 { 0x1f, 0x0005 }, |
|
2699 { 0x05, 0x8330 }, |
|
2700 { 0x06, 0x2642 } |
|
2701 }; |
|
2702 |
|
2703 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2704 } |
|
2705 |
|
2706 /* Fine tune PLL performance */ |
|
2707 rtl_writephy(tp, 0x1f, 0x0002); |
|
2708 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2709 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2710 |
|
2711 /* Switching regulator Slew rate */ |
|
2712 rtl_writephy(tp, 0x1f, 0x0002); |
|
2713 rtl_patchphy(tp, 0x0f, 0x0017); |
|
2714 |
|
2715 rtl_writephy(tp, 0x1f, 0x0005); |
|
2716 rtl_writephy(tp, 0x05, 0x001b); |
|
2717 |
|
2718 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); |
|
2719 |
|
2720 rtl_writephy(tp, 0x1f, 0x0000); |
|
2721 } |
|
2722 |
|
2723 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
|
2724 { |
|
2725 static const struct phy_reg phy_reg_init[] = { |
|
2726 { 0x1f, 0x0002 }, |
|
2727 { 0x10, 0x0008 }, |
|
2728 { 0x0d, 0x006c }, |
|
2729 |
|
2730 { 0x1f, 0x0000 }, |
|
2731 { 0x0d, 0xf880 }, |
|
2732 |
|
2733 { 0x1f, 0x0001 }, |
|
2734 { 0x17, 0x0cc0 }, |
|
2735 |
|
2736 { 0x1f, 0x0001 }, |
|
2737 { 0x0b, 0xa4d8 }, |
|
2738 { 0x09, 0x281c }, |
|
2739 { 0x07, 0x2883 }, |
|
2740 { 0x0a, 0x6b35 }, |
|
2741 { 0x1d, 0x3da4 }, |
|
2742 { 0x1c, 0xeffd }, |
|
2743 { 0x14, 0x7f52 }, |
|
2744 { 0x18, 0x7fc6 }, |
|
2745 { 0x08, 0x0601 }, |
|
2746 { 0x06, 0x4063 }, |
|
2747 { 0x10, 0xf074 }, |
|
2748 { 0x1f, 0x0003 }, |
|
2749 { 0x13, 0x0789 }, |
|
2750 { 0x12, 0xf4bd }, |
|
2751 { 0x1a, 0x04fd }, |
|
2752 { 0x14, 0x84b0 }, |
|
2753 { 0x1f, 0x0000 }, |
|
2754 { 0x00, 0x9200 }, |
|
2755 |
|
2756 { 0x1f, 0x0005 }, |
|
2757 { 0x01, 0x0340 }, |
|
2758 { 0x1f, 0x0001 }, |
|
2759 { 0x04, 0x4000 }, |
|
2760 { 0x03, 0x1d21 }, |
|
2761 { 0x02, 0x0c32 }, |
|
2762 { 0x01, 0x0200 }, |
|
2763 { 0x00, 0x5554 }, |
|
2764 { 0x04, 0x4800 }, |
|
2765 { 0x04, 0x4000 }, |
|
2766 { 0x04, 0xf000 }, |
|
2767 { 0x03, 0xdf01 }, |
|
2768 { 0x02, 0xdf20 }, |
|
2769 { 0x01, 0x101a }, |
|
2770 { 0x00, 0xa0ff }, |
|
2771 { 0x04, 0xf800 }, |
|
2772 { 0x04, 0xf000 }, |
|
2773 { 0x1f, 0x0000 }, |
|
2774 |
|
2775 { 0x1f, 0x0007 }, |
|
2776 { 0x1e, 0x0023 }, |
|
2777 { 0x16, 0x0000 }, |
|
2778 { 0x1f, 0x0000 } |
|
2779 }; |
|
2780 |
|
2781 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2782 } |
|
2783 |
|
2784 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
|
2785 { |
|
2786 static const struct phy_reg phy_reg_init[] = { |
|
2787 { 0x1f, 0x0001 }, |
|
2788 { 0x17, 0x0cc0 }, |
|
2789 |
|
2790 { 0x1f, 0x0007 }, |
|
2791 { 0x1e, 0x002d }, |
|
2792 { 0x18, 0x0040 }, |
|
2793 { 0x1f, 0x0000 } |
|
2794 }; |
|
2795 |
|
2796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2797 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2798 } |
|
2799 |
|
2800 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
|
2801 { |
|
2802 static const struct phy_reg phy_reg_init[] = { |
|
2803 /* Enable Delay cap */ |
|
2804 { 0x1f, 0x0005 }, |
|
2805 { 0x05, 0x8b80 }, |
|
2806 { 0x06, 0xc896 }, |
|
2807 { 0x1f, 0x0000 }, |
|
2808 |
|
2809 /* Channel estimation fine tune */ |
|
2810 { 0x1f, 0x0001 }, |
|
2811 { 0x0b, 0x6c20 }, |
|
2812 { 0x07, 0x2872 }, |
|
2813 { 0x1c, 0xefff }, |
|
2814 { 0x1f, 0x0003 }, |
|
2815 { 0x14, 0x6420 }, |
|
2816 { 0x1f, 0x0000 }, |
|
2817 |
|
2818 /* Update PFM & 10M TX idle timer */ |
|
2819 { 0x1f, 0x0007 }, |
|
2820 { 0x1e, 0x002f }, |
|
2821 { 0x15, 0x1919 }, |
|
2822 { 0x1f, 0x0000 }, |
|
2823 |
|
2824 { 0x1f, 0x0007 }, |
|
2825 { 0x1e, 0x00ac }, |
|
2826 { 0x18, 0x0006 }, |
|
2827 { 0x1f, 0x0000 } |
|
2828 }; |
|
2829 |
|
2830 rtl_apply_firmware(tp); |
|
2831 |
|
2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2833 |
|
2834 /* DCO enable for 10M IDLE Power */ |
|
2835 rtl_writephy(tp, 0x1f, 0x0007); |
|
2836 rtl_writephy(tp, 0x1e, 0x0023); |
|
2837 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
2838 rtl_writephy(tp, 0x1f, 0x0000); |
|
2839 |
|
2840 /* For impedance matching */ |
|
2841 rtl_writephy(tp, 0x1f, 0x0002); |
|
2842 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); |
|
2843 rtl_writephy(tp, 0x1f, 0x0000); |
|
2844 |
|
2845 /* PHY auto speed down */ |
|
2846 rtl_writephy(tp, 0x1f, 0x0007); |
|
2847 rtl_writephy(tp, 0x1e, 0x002d); |
|
2848 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); |
|
2849 rtl_writephy(tp, 0x1f, 0x0000); |
|
2850 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
2851 |
|
2852 rtl_writephy(tp, 0x1f, 0x0005); |
|
2853 rtl_writephy(tp, 0x05, 0x8b86); |
|
2854 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
2855 rtl_writephy(tp, 0x1f, 0x0000); |
|
2856 |
|
2857 rtl_writephy(tp, 0x1f, 0x0005); |
|
2858 rtl_writephy(tp, 0x05, 0x8b85); |
|
2859 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
2860 rtl_writephy(tp, 0x1f, 0x0007); |
|
2861 rtl_writephy(tp, 0x1e, 0x0020); |
|
2862 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); |
|
2863 rtl_writephy(tp, 0x1f, 0x0006); |
|
2864 rtl_writephy(tp, 0x00, 0x5a00); |
|
2865 rtl_writephy(tp, 0x1f, 0x0000); |
|
2866 rtl_writephy(tp, 0x0d, 0x0007); |
|
2867 rtl_writephy(tp, 0x0e, 0x003c); |
|
2868 rtl_writephy(tp, 0x0d, 0x4007); |
|
2869 rtl_writephy(tp, 0x0e, 0x0000); |
|
2870 rtl_writephy(tp, 0x0d, 0x0000); |
|
2871 } |
|
2872 |
|
2873 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
|
2874 { |
|
2875 static const struct phy_reg phy_reg_init[] = { |
|
2876 /* Enable Delay cap */ |
|
2877 { 0x1f, 0x0004 }, |
|
2878 { 0x1f, 0x0007 }, |
|
2879 { 0x1e, 0x00ac }, |
|
2880 { 0x18, 0x0006 }, |
|
2881 { 0x1f, 0x0002 }, |
|
2882 { 0x1f, 0x0000 }, |
|
2883 { 0x1f, 0x0000 }, |
|
2884 |
|
2885 /* Channel estimation fine tune */ |
|
2886 { 0x1f, 0x0003 }, |
|
2887 { 0x09, 0xa20f }, |
|
2888 { 0x1f, 0x0000 }, |
|
2889 { 0x1f, 0x0000 }, |
|
2890 |
|
2891 /* Green Setting */ |
|
2892 { 0x1f, 0x0005 }, |
|
2893 { 0x05, 0x8b5b }, |
|
2894 { 0x06, 0x9222 }, |
|
2895 { 0x05, 0x8b6d }, |
|
2896 { 0x06, 0x8000 }, |
|
2897 { 0x05, 0x8b76 }, |
|
2898 { 0x06, 0x8000 }, |
|
2899 { 0x1f, 0x0000 } |
|
2900 }; |
|
2901 |
|
2902 rtl_apply_firmware(tp); |
|
2903 |
|
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2905 |
|
2906 /* For 4-corner performance improve */ |
|
2907 rtl_writephy(tp, 0x1f, 0x0005); |
|
2908 rtl_writephy(tp, 0x05, 0x8b80); |
|
2909 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
2910 rtl_writephy(tp, 0x1f, 0x0000); |
|
2911 |
|
2912 /* PHY auto speed down */ |
|
2913 rtl_writephy(tp, 0x1f, 0x0004); |
|
2914 rtl_writephy(tp, 0x1f, 0x0007); |
|
2915 rtl_writephy(tp, 0x1e, 0x002d); |
|
2916 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
2917 rtl_writephy(tp, 0x1f, 0x0002); |
|
2918 rtl_writephy(tp, 0x1f, 0x0000); |
|
2919 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
2920 |
|
2921 /* improve 10M EEE waveform */ |
|
2922 rtl_writephy(tp, 0x1f, 0x0005); |
|
2923 rtl_writephy(tp, 0x05, 0x8b86); |
|
2924 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
2925 rtl_writephy(tp, 0x1f, 0x0000); |
|
2926 |
|
2927 /* Improve 2-pair detection performance */ |
|
2928 rtl_writephy(tp, 0x1f, 0x0005); |
|
2929 rtl_writephy(tp, 0x05, 0x8b85); |
|
2930 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
2931 rtl_writephy(tp, 0x1f, 0x0000); |
|
2932 |
|
2933 /* EEE setting */ |
|
2934 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, |
|
2935 ERIAR_EXGMAC); |
|
2936 rtl_writephy(tp, 0x1f, 0x0005); |
|
2937 rtl_writephy(tp, 0x05, 0x8b85); |
|
2938 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
2939 rtl_writephy(tp, 0x1f, 0x0004); |
|
2940 rtl_writephy(tp, 0x1f, 0x0007); |
|
2941 rtl_writephy(tp, 0x1e, 0x0020); |
|
2942 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
|
2943 rtl_writephy(tp, 0x1f, 0x0002); |
|
2944 rtl_writephy(tp, 0x1f, 0x0000); |
|
2945 rtl_writephy(tp, 0x0d, 0x0007); |
|
2946 rtl_writephy(tp, 0x0e, 0x003c); |
|
2947 rtl_writephy(tp, 0x0d, 0x4007); |
|
2948 rtl_writephy(tp, 0x0e, 0x0000); |
|
2949 rtl_writephy(tp, 0x0d, 0x0000); |
|
2950 |
|
2951 /* Green feature */ |
|
2952 rtl_writephy(tp, 0x1f, 0x0003); |
|
2953 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); |
|
2954 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); |
|
2955 rtl_writephy(tp, 0x1f, 0x0000); |
|
2956 } |
|
2957 |
|
2958 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
|
2959 { |
|
2960 static const struct phy_reg phy_reg_init[] = { |
|
2961 /* Channel estimation fine tune */ |
|
2962 { 0x1f, 0x0003 }, |
|
2963 { 0x09, 0xa20f }, |
|
2964 { 0x1f, 0x0000 }, |
|
2965 |
|
2966 /* Modify green table for giga & fnet */ |
|
2967 { 0x1f, 0x0005 }, |
|
2968 { 0x05, 0x8b55 }, |
|
2969 { 0x06, 0x0000 }, |
|
2970 { 0x05, 0x8b5e }, |
|
2971 { 0x06, 0x0000 }, |
|
2972 { 0x05, 0x8b67 }, |
|
2973 { 0x06, 0x0000 }, |
|
2974 { 0x05, 0x8b70 }, |
|
2975 { 0x06, 0x0000 }, |
|
2976 { 0x1f, 0x0000 }, |
|
2977 { 0x1f, 0x0007 }, |
|
2978 { 0x1e, 0x0078 }, |
|
2979 { 0x17, 0x0000 }, |
|
2980 { 0x19, 0x00fb }, |
|
2981 { 0x1f, 0x0000 }, |
|
2982 |
|
2983 /* Modify green table for 10M */ |
|
2984 { 0x1f, 0x0005 }, |
|
2985 { 0x05, 0x8b79 }, |
|
2986 { 0x06, 0xaa00 }, |
|
2987 { 0x1f, 0x0000 }, |
|
2988 |
|
2989 /* Disable hiimpedance detection (RTCT) */ |
|
2990 { 0x1f, 0x0003 }, |
|
2991 { 0x01, 0x328a }, |
|
2992 { 0x1f, 0x0000 } |
|
2993 }; |
|
2994 |
|
2995 rtl_apply_firmware(tp); |
|
2996 |
|
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2998 |
|
2999 /* For 4-corner performance improve */ |
|
3000 rtl_writephy(tp, 0x1f, 0x0005); |
|
3001 rtl_writephy(tp, 0x05, 0x8b80); |
|
3002 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3003 rtl_writephy(tp, 0x1f, 0x0000); |
|
3004 |
|
3005 /* PHY auto speed down */ |
|
3006 rtl_writephy(tp, 0x1f, 0x0007); |
|
3007 rtl_writephy(tp, 0x1e, 0x002d); |
|
3008 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3009 rtl_writephy(tp, 0x1f, 0x0000); |
|
3010 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3011 |
|
3012 /* Improve 10M EEE waveform */ |
|
3013 rtl_writephy(tp, 0x1f, 0x0005); |
|
3014 rtl_writephy(tp, 0x05, 0x8b86); |
|
3015 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3016 rtl_writephy(tp, 0x1f, 0x0000); |
|
3017 |
|
3018 /* Improve 2-pair detection performance */ |
|
3019 rtl_writephy(tp, 0x1f, 0x0005); |
|
3020 rtl_writephy(tp, 0x05, 0x8b85); |
|
3021 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3022 rtl_writephy(tp, 0x1f, 0x0000); |
|
3023 } |
|
3024 |
|
3025 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) |
|
3026 { |
|
3027 rtl_apply_firmware(tp); |
|
3028 |
|
3029 /* For 4-corner performance improve */ |
|
3030 rtl_writephy(tp, 0x1f, 0x0005); |
|
3031 rtl_writephy(tp, 0x05, 0x8b80); |
|
3032 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3033 rtl_writephy(tp, 0x1f, 0x0000); |
|
3034 |
|
3035 /* PHY auto speed down */ |
|
3036 rtl_writephy(tp, 0x1f, 0x0007); |
|
3037 rtl_writephy(tp, 0x1e, 0x002d); |
|
3038 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3039 rtl_writephy(tp, 0x1f, 0x0000); |
|
3040 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3041 |
|
3042 /* Improve 10M EEE waveform */ |
|
3043 rtl_writephy(tp, 0x1f, 0x0005); |
|
3044 rtl_writephy(tp, 0x05, 0x8b86); |
|
3045 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3046 rtl_writephy(tp, 0x1f, 0x0000); |
|
3047 } |
|
3048 |
|
3049 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
|
3050 { |
|
3051 static const struct phy_reg phy_reg_init[] = { |
|
3052 { 0x1f, 0x0003 }, |
|
3053 { 0x08, 0x441d }, |
|
3054 { 0x01, 0x9100 }, |
|
3055 { 0x1f, 0x0000 } |
|
3056 }; |
|
3057 |
|
3058 rtl_writephy(tp, 0x1f, 0x0000); |
|
3059 rtl_patchphy(tp, 0x11, 1 << 12); |
|
3060 rtl_patchphy(tp, 0x19, 1 << 13); |
|
3061 rtl_patchphy(tp, 0x10, 1 << 15); |
|
3062 |
|
3063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3064 } |
|
3065 |
|
3066 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
|
3067 { |
|
3068 static const struct phy_reg phy_reg_init[] = { |
|
3069 { 0x1f, 0x0005 }, |
|
3070 { 0x1a, 0x0000 }, |
|
3071 { 0x1f, 0x0000 }, |
|
3072 |
|
3073 { 0x1f, 0x0004 }, |
|
3074 { 0x1c, 0x0000 }, |
|
3075 { 0x1f, 0x0000 }, |
|
3076 |
|
3077 { 0x1f, 0x0001 }, |
|
3078 { 0x15, 0x7701 }, |
|
3079 { 0x1f, 0x0000 } |
|
3080 }; |
|
3081 |
|
3082 /* Disable ALDPS before ram code */ |
|
3083 rtl_writephy(tp, 0x1f, 0x0000); |
|
3084 rtl_writephy(tp, 0x18, 0x0310); |
|
3085 msleep(100); |
|
3086 |
|
3087 rtl_apply_firmware(tp); |
|
3088 |
|
3089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3090 } |
|
3091 |
|
3092 static void rtl_hw_phy_config(struct net_device *dev) |
|
3093 { |
|
3094 struct rtl8169_private *tp = netdev_priv(dev); |
|
3095 |
|
3096 rtl8169_print_mac_version(tp); |
|
3097 |
|
3098 switch (tp->mac_version) { |
|
3099 case RTL_GIGA_MAC_VER_01: |
|
3100 break; |
|
3101 case RTL_GIGA_MAC_VER_02: |
|
3102 case RTL_GIGA_MAC_VER_03: |
|
3103 rtl8169s_hw_phy_config(tp); |
|
3104 break; |
|
3105 case RTL_GIGA_MAC_VER_04: |
|
3106 rtl8169sb_hw_phy_config(tp); |
|
3107 break; |
|
3108 case RTL_GIGA_MAC_VER_05: |
|
3109 rtl8169scd_hw_phy_config(tp); |
|
3110 break; |
|
3111 case RTL_GIGA_MAC_VER_06: |
|
3112 rtl8169sce_hw_phy_config(tp); |
|
3113 break; |
|
3114 case RTL_GIGA_MAC_VER_07: |
|
3115 case RTL_GIGA_MAC_VER_08: |
|
3116 case RTL_GIGA_MAC_VER_09: |
|
3117 rtl8102e_hw_phy_config(tp); |
|
3118 break; |
|
3119 case RTL_GIGA_MAC_VER_11: |
|
3120 rtl8168bb_hw_phy_config(tp); |
|
3121 break; |
|
3122 case RTL_GIGA_MAC_VER_12: |
|
3123 rtl8168bef_hw_phy_config(tp); |
|
3124 break; |
|
3125 case RTL_GIGA_MAC_VER_17: |
|
3126 rtl8168bef_hw_phy_config(tp); |
|
3127 break; |
|
3128 case RTL_GIGA_MAC_VER_18: |
|
3129 rtl8168cp_1_hw_phy_config(tp); |
|
3130 break; |
|
3131 case RTL_GIGA_MAC_VER_19: |
|
3132 rtl8168c_1_hw_phy_config(tp); |
|
3133 break; |
|
3134 case RTL_GIGA_MAC_VER_20: |
|
3135 rtl8168c_2_hw_phy_config(tp); |
|
3136 break; |
|
3137 case RTL_GIGA_MAC_VER_21: |
|
3138 rtl8168c_3_hw_phy_config(tp); |
|
3139 break; |
|
3140 case RTL_GIGA_MAC_VER_22: |
|
3141 rtl8168c_4_hw_phy_config(tp); |
|
3142 break; |
|
3143 case RTL_GIGA_MAC_VER_23: |
|
3144 case RTL_GIGA_MAC_VER_24: |
|
3145 rtl8168cp_2_hw_phy_config(tp); |
|
3146 break; |
|
3147 case RTL_GIGA_MAC_VER_25: |
|
3148 rtl8168d_1_hw_phy_config(tp); |
|
3149 break; |
|
3150 case RTL_GIGA_MAC_VER_26: |
|
3151 rtl8168d_2_hw_phy_config(tp); |
|
3152 break; |
|
3153 case RTL_GIGA_MAC_VER_27: |
|
3154 rtl8168d_3_hw_phy_config(tp); |
|
3155 break; |
|
3156 case RTL_GIGA_MAC_VER_28: |
|
3157 rtl8168d_4_hw_phy_config(tp); |
|
3158 break; |
|
3159 case RTL_GIGA_MAC_VER_29: |
|
3160 case RTL_GIGA_MAC_VER_30: |
|
3161 rtl8105e_hw_phy_config(tp); |
|
3162 break; |
|
3163 case RTL_GIGA_MAC_VER_31: |
|
3164 /* None. */ |
|
3165 break; |
|
3166 case RTL_GIGA_MAC_VER_32: |
|
3167 case RTL_GIGA_MAC_VER_33: |
|
3168 rtl8168e_1_hw_phy_config(tp); |
|
3169 break; |
|
3170 case RTL_GIGA_MAC_VER_34: |
|
3171 rtl8168e_2_hw_phy_config(tp); |
|
3172 break; |
|
3173 case RTL_GIGA_MAC_VER_35: |
|
3174 rtl8168f_1_hw_phy_config(tp); |
|
3175 break; |
|
3176 case RTL_GIGA_MAC_VER_36: |
|
3177 rtl8168f_2_hw_phy_config(tp); |
|
3178 break; |
|
3179 |
|
3180 default: |
|
3181 break; |
|
3182 } |
|
3183 } |
|
3184 |
|
3185 static void rtl8169_phy_timer(unsigned long __opaque) |
|
3186 { |
|
3187 struct net_device *dev = (struct net_device *)__opaque; |
|
3188 struct rtl8169_private *tp = netdev_priv(dev); |
|
3189 struct timer_list *timer = &tp->timer; |
|
3190 void __iomem *ioaddr = tp->mmio_addr; |
|
3191 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
3192 |
|
3193 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
3194 |
|
3195 spin_lock_irq(&tp->lock); |
|
3196 |
|
3197 if (tp->phy_reset_pending(tp)) { |
|
3198 /* |
|
3199 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
3200 * Let's delay the execution of the timer for a few ticks. |
|
3201 */ |
|
3202 timeout = HZ/10; |
|
3203 goto out_mod_timer; |
|
3204 } |
|
3205 |
|
3206 if (tp->link_ok(ioaddr)) |
|
3207 goto out_unlock; |
|
3208 |
|
3209 netif_warn(tp, link, dev, "PHY reset until link up\n"); |
|
3210 |
|
3211 tp->phy_reset_enable(tp); |
|
3212 |
|
3213 out_mod_timer: |
|
3214 mod_timer(timer, jiffies + timeout); |
|
3215 out_unlock: |
|
3216 spin_unlock_irq(&tp->lock); |
|
3217 } |
|
3218 |
|
3219 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
3220 /* |
|
3221 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
3222 * without having to re-enable interrupts. It's not called while |
|
3223 * the interrupt routine is executing. |
|
3224 */ |
|
3225 static void rtl8169_netpoll(struct net_device *dev) |
|
3226 { |
|
3227 struct rtl8169_private *tp = netdev_priv(dev); |
|
3228 struct pci_dev *pdev = tp->pci_dev; |
|
3229 |
|
3230 disable_irq(pdev->irq); |
|
3231 rtl8169_interrupt(pdev->irq, dev); |
|
3232 enable_irq(pdev->irq); |
|
3233 } |
|
3234 #endif |
|
3235 |
|
3236 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
3237 void __iomem *ioaddr) |
|
3238 { |
|
3239 iounmap(ioaddr); |
|
3240 pci_release_regions(pdev); |
|
3241 pci_clear_mwi(pdev); |
|
3242 pci_disable_device(pdev); |
|
3243 free_netdev(dev); |
|
3244 } |
|
3245 |
|
3246 static void rtl8169_phy_reset(struct net_device *dev, |
|
3247 struct rtl8169_private *tp) |
|
3248 { |
|
3249 unsigned int i; |
|
3250 |
|
3251 tp->phy_reset_enable(tp); |
|
3252 for (i = 0; i < 100; i++) { |
|
3253 if (!tp->phy_reset_pending(tp)) |
|
3254 return; |
|
3255 msleep(1); |
|
3256 } |
|
3257 netif_err(tp, link, dev, "PHY reset failed\n"); |
|
3258 } |
|
3259 |
|
3260 static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
|
3261 { |
|
3262 void __iomem *ioaddr = tp->mmio_addr; |
|
3263 |
|
3264 return (tp->mac_version == RTL_GIGA_MAC_VER_01) && |
|
3265 (RTL_R8(PHYstatus) & TBI_Enable); |
|
3266 } |
|
3267 |
|
3268 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
3269 { |
|
3270 void __iomem *ioaddr = tp->mmio_addr; |
|
3271 |
|
3272 rtl_hw_phy_config(dev); |
|
3273 |
|
3274 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
3275 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3276 RTL_W8(0x82, 0x01); |
|
3277 } |
|
3278 |
|
3279 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
3280 |
|
3281 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
3282 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3283 |
|
3284 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
3285 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3286 RTL_W8(0x82, 0x01); |
|
3287 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
3288 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
3289 } |
|
3290 |
|
3291 rtl8169_phy_reset(dev, tp); |
|
3292 |
|
3293 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
|
3294 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
3295 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | |
|
3296 (tp->mii.supports_gmii ? |
|
3297 ADVERTISED_1000baseT_Half | |
|
3298 ADVERTISED_1000baseT_Full : 0)); |
|
3299 |
|
3300 if (rtl_tbi_enabled(tp)) |
|
3301 netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
|
3302 } |
|
3303 |
|
3304 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
3305 { |
|
3306 void __iomem *ioaddr = tp->mmio_addr; |
|
3307 u32 high; |
|
3308 u32 low; |
|
3309 |
|
3310 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
3311 high = addr[4] | (addr[5] << 8); |
|
3312 |
|
3313 spin_lock_irq(&tp->lock); |
|
3314 |
|
3315 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3316 |
|
3317 RTL_W32(MAC4, high); |
|
3318 RTL_R32(MAC4); |
|
3319 |
|
3320 RTL_W32(MAC0, low); |
|
3321 RTL_R32(MAC0); |
|
3322 |
|
3323 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
3324 const struct exgmac_reg e[] = { |
|
3325 { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, |
|
3326 { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, |
|
3327 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, |
|
3328 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | |
|
3329 low >> 16 }, |
|
3330 }; |
|
3331 |
|
3332 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); |
|
3333 } |
|
3334 |
|
3335 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3336 |
|
3337 spin_unlock_irq(&tp->lock); |
|
3338 } |
|
3339 |
|
3340 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
3341 { |
|
3342 struct rtl8169_private *tp = netdev_priv(dev); |
|
3343 struct sockaddr *addr = p; |
|
3344 |
|
3345 if (!is_valid_ether_addr(addr->sa_data)) |
|
3346 return -EADDRNOTAVAIL; |
|
3347 |
|
3348 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
3349 |
|
3350 rtl_rar_set(tp, dev->dev_addr); |
|
3351 |
|
3352 return 0; |
|
3353 } |
|
3354 |
|
3355 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
3356 { |
|
3357 struct rtl8169_private *tp = netdev_priv(dev); |
|
3358 struct mii_ioctl_data *data = if_mii(ifr); |
|
3359 |
|
3360 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
3361 } |
|
3362 |
|
3363 static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
|
3364 struct mii_ioctl_data *data, int cmd) |
|
3365 { |
|
3366 switch (cmd) { |
|
3367 case SIOCGMIIPHY: |
|
3368 data->phy_id = 32; /* Internal PHY */ |
|
3369 return 0; |
|
3370 |
|
3371 case SIOCGMIIREG: |
|
3372 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
|
3373 return 0; |
|
3374 |
|
3375 case SIOCSMIIREG: |
|
3376 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
|
3377 return 0; |
|
3378 } |
|
3379 return -EOPNOTSUPP; |
|
3380 } |
|
3381 |
|
3382 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
3383 { |
|
3384 return -EOPNOTSUPP; |
|
3385 } |
|
3386 |
|
3387 static const struct rtl_cfg_info { |
|
3388 void (*hw_start)(struct net_device *); |
|
3389 unsigned int region; |
|
3390 unsigned int align; |
|
3391 u16 intr_event; |
|
3392 u16 napi_event; |
|
3393 unsigned features; |
|
3394 u8 default_ver; |
|
3395 } rtl_cfg_infos [] = { |
|
3396 [RTL_CFG_0] = { |
|
3397 .hw_start = rtl_hw_start_8169, |
|
3398 .region = 1, |
|
3399 .align = 0, |
|
3400 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
3401 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
3402 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
3403 .features = RTL_FEATURE_GMII, |
|
3404 .default_ver = RTL_GIGA_MAC_VER_01, |
|
3405 }, |
|
3406 [RTL_CFG_1] = { |
|
3407 .hw_start = rtl_hw_start_8168, |
|
3408 .region = 2, |
|
3409 .align = 8, |
|
3410 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
3411 TxErr | TxOK | RxOK | RxErr, |
|
3412 .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
3413 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
3414 .default_ver = RTL_GIGA_MAC_VER_11, |
|
3415 }, |
|
3416 [RTL_CFG_2] = { |
|
3417 .hw_start = rtl_hw_start_8101, |
|
3418 .region = 2, |
|
3419 .align = 8, |
|
3420 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
3421 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
3422 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
3423 .features = RTL_FEATURE_MSI, |
|
3424 .default_ver = RTL_GIGA_MAC_VER_13, |
|
3425 } |
|
3426 }; |
|
3427 |
|
3428 /* Cfg9346_Unlock assumed. */ |
|
3429 static unsigned rtl_try_msi(struct rtl8169_private *tp, |
|
3430 const struct rtl_cfg_info *cfg) |
|
3431 { |
|
3432 void __iomem *ioaddr = tp->mmio_addr; |
|
3433 unsigned msi = 0; |
|
3434 u8 cfg2; |
|
3435 |
|
3436 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
3437 if (cfg->features & RTL_FEATURE_MSI) { |
|
3438 if (pci_enable_msi(tp->pci_dev)) { |
|
3439 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); |
|
3440 } else { |
|
3441 cfg2 |= MSIEnable; |
|
3442 msi = RTL_FEATURE_MSI; |
|
3443 } |
|
3444 } |
|
3445 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
3446 RTL_W8(Config2, cfg2); |
|
3447 return msi; |
|
3448 } |
|
3449 |
|
3450 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
3451 { |
|
3452 if (tp->features & RTL_FEATURE_MSI) { |
|
3453 pci_disable_msi(pdev); |
|
3454 tp->features &= ~RTL_FEATURE_MSI; |
|
3455 } |
|
3456 } |
|
3457 |
|
3458 static const struct net_device_ops rtl8169_netdev_ops = { |
|
3459 .ndo_open = rtl8169_open, |
|
3460 .ndo_stop = rtl8169_close, |
|
3461 .ndo_get_stats = rtl8169_get_stats, |
|
3462 .ndo_start_xmit = rtl8169_start_xmit, |
|
3463 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
3464 .ndo_validate_addr = eth_validate_addr, |
|
3465 .ndo_change_mtu = rtl8169_change_mtu, |
|
3466 .ndo_fix_features = rtl8169_fix_features, |
|
3467 .ndo_set_features = rtl8169_set_features, |
|
3468 .ndo_set_mac_address = rtl_set_mac_address, |
|
3469 .ndo_do_ioctl = rtl8169_ioctl, |
|
3470 .ndo_set_rx_mode = rtl_set_rx_mode, |
|
3471 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
3472 .ndo_poll_controller = rtl8169_netpoll, |
|
3473 #endif |
|
3474 |
|
3475 }; |
|
3476 |
|
3477 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
|
3478 { |
|
3479 struct mdio_ops *ops = &tp->mdio_ops; |
|
3480 |
|
3481 switch (tp->mac_version) { |
|
3482 case RTL_GIGA_MAC_VER_27: |
|
3483 ops->write = r8168dp_1_mdio_write; |
|
3484 ops->read = r8168dp_1_mdio_read; |
|
3485 break; |
|
3486 case RTL_GIGA_MAC_VER_28: |
|
3487 case RTL_GIGA_MAC_VER_31: |
|
3488 ops->write = r8168dp_2_mdio_write; |
|
3489 ops->read = r8168dp_2_mdio_read; |
|
3490 break; |
|
3491 default: |
|
3492 ops->write = r8169_mdio_write; |
|
3493 ops->read = r8169_mdio_read; |
|
3494 break; |
|
3495 } |
|
3496 } |
|
3497 |
|
3498 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
|
3499 { |
|
3500 void __iomem *ioaddr = tp->mmio_addr; |
|
3501 |
|
3502 switch (tp->mac_version) { |
|
3503 case RTL_GIGA_MAC_VER_29: |
|
3504 case RTL_GIGA_MAC_VER_30: |
|
3505 case RTL_GIGA_MAC_VER_32: |
|
3506 case RTL_GIGA_MAC_VER_33: |
|
3507 case RTL_GIGA_MAC_VER_34: |
|
3508 RTL_W32(RxConfig, RTL_R32(RxConfig) | |
|
3509 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
|
3510 break; |
|
3511 default: |
|
3512 break; |
|
3513 } |
|
3514 } |
|
3515 |
|
3516 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) |
|
3517 { |
|
3518 if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) |
|
3519 return false; |
|
3520 |
|
3521 rtl_writephy(tp, 0x1f, 0x0000); |
|
3522 rtl_writephy(tp, MII_BMCR, 0x0000); |
|
3523 |
|
3524 rtl_wol_suspend_quirk(tp); |
|
3525 |
|
3526 return true; |
|
3527 } |
|
3528 |
|
3529 static void r810x_phy_power_down(struct rtl8169_private *tp) |
|
3530 { |
|
3531 rtl_writephy(tp, 0x1f, 0x0000); |
|
3532 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3533 } |
|
3534 |
|
3535 static void r810x_phy_power_up(struct rtl8169_private *tp) |
|
3536 { |
|
3537 rtl_writephy(tp, 0x1f, 0x0000); |
|
3538 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3539 } |
|
3540 |
|
3541 static void r810x_pll_power_down(struct rtl8169_private *tp) |
|
3542 { |
|
3543 if (rtl_wol_pll_power_down(tp)) |
|
3544 return; |
|
3545 |
|
3546 r810x_phy_power_down(tp); |
|
3547 } |
|
3548 |
|
3549 static void r810x_pll_power_up(struct rtl8169_private *tp) |
|
3550 { |
|
3551 r810x_phy_power_up(tp); |
|
3552 } |
|
3553 |
|
3554 static void r8168_phy_power_up(struct rtl8169_private *tp) |
|
3555 { |
|
3556 rtl_writephy(tp, 0x1f, 0x0000); |
|
3557 switch (tp->mac_version) { |
|
3558 case RTL_GIGA_MAC_VER_11: |
|
3559 case RTL_GIGA_MAC_VER_12: |
|
3560 case RTL_GIGA_MAC_VER_17: |
|
3561 case RTL_GIGA_MAC_VER_18: |
|
3562 case RTL_GIGA_MAC_VER_19: |
|
3563 case RTL_GIGA_MAC_VER_20: |
|
3564 case RTL_GIGA_MAC_VER_21: |
|
3565 case RTL_GIGA_MAC_VER_22: |
|
3566 case RTL_GIGA_MAC_VER_23: |
|
3567 case RTL_GIGA_MAC_VER_24: |
|
3568 case RTL_GIGA_MAC_VER_25: |
|
3569 case RTL_GIGA_MAC_VER_26: |
|
3570 case RTL_GIGA_MAC_VER_27: |
|
3571 case RTL_GIGA_MAC_VER_28: |
|
3572 case RTL_GIGA_MAC_VER_31: |
|
3573 rtl_writephy(tp, 0x0e, 0x0000); |
|
3574 break; |
|
3575 default: |
|
3576 break; |
|
3577 } |
|
3578 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3579 } |
|
3580 |
|
3581 static void r8168_phy_power_down(struct rtl8169_private *tp) |
|
3582 { |
|
3583 rtl_writephy(tp, 0x1f, 0x0000); |
|
3584 switch (tp->mac_version) { |
|
3585 case RTL_GIGA_MAC_VER_32: |
|
3586 case RTL_GIGA_MAC_VER_33: |
|
3587 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
|
3588 break; |
|
3589 |
|
3590 case RTL_GIGA_MAC_VER_11: |
|
3591 case RTL_GIGA_MAC_VER_12: |
|
3592 case RTL_GIGA_MAC_VER_17: |
|
3593 case RTL_GIGA_MAC_VER_18: |
|
3594 case RTL_GIGA_MAC_VER_19: |
|
3595 case RTL_GIGA_MAC_VER_20: |
|
3596 case RTL_GIGA_MAC_VER_21: |
|
3597 case RTL_GIGA_MAC_VER_22: |
|
3598 case RTL_GIGA_MAC_VER_23: |
|
3599 case RTL_GIGA_MAC_VER_24: |
|
3600 case RTL_GIGA_MAC_VER_25: |
|
3601 case RTL_GIGA_MAC_VER_26: |
|
3602 case RTL_GIGA_MAC_VER_27: |
|
3603 case RTL_GIGA_MAC_VER_28: |
|
3604 case RTL_GIGA_MAC_VER_31: |
|
3605 rtl_writephy(tp, 0x0e, 0x0200); |
|
3606 default: |
|
3607 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3608 break; |
|
3609 } |
|
3610 } |
|
3611 |
|
3612 static void r8168_pll_power_down(struct rtl8169_private *tp) |
|
3613 { |
|
3614 void __iomem *ioaddr = tp->mmio_addr; |
|
3615 |
|
3616 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3617 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3618 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3619 r8168dp_check_dash(tp)) { |
|
3620 return; |
|
3621 } |
|
3622 |
|
3623 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
|
3624 tp->mac_version == RTL_GIGA_MAC_VER_24) && |
|
3625 (RTL_R16(CPlusCmd) & ASF)) { |
|
3626 return; |
|
3627 } |
|
3628 |
|
3629 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
|
3630 tp->mac_version == RTL_GIGA_MAC_VER_33) |
|
3631 rtl_ephy_write(ioaddr, 0x19, 0xff64); |
|
3632 |
|
3633 if (rtl_wol_pll_power_down(tp)) |
|
3634 return; |
|
3635 |
|
3636 r8168_phy_power_down(tp); |
|
3637 |
|
3638 switch (tp->mac_version) { |
|
3639 case RTL_GIGA_MAC_VER_25: |
|
3640 case RTL_GIGA_MAC_VER_26: |
|
3641 case RTL_GIGA_MAC_VER_27: |
|
3642 case RTL_GIGA_MAC_VER_28: |
|
3643 case RTL_GIGA_MAC_VER_31: |
|
3644 case RTL_GIGA_MAC_VER_32: |
|
3645 case RTL_GIGA_MAC_VER_33: |
|
3646 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
|
3647 break; |
|
3648 } |
|
3649 } |
|
3650 |
|
3651 static void r8168_pll_power_up(struct rtl8169_private *tp) |
|
3652 { |
|
3653 void __iomem *ioaddr = tp->mmio_addr; |
|
3654 |
|
3655 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3656 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3657 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3658 r8168dp_check_dash(tp)) { |
|
3659 return; |
|
3660 } |
|
3661 |
|
3662 switch (tp->mac_version) { |
|
3663 case RTL_GIGA_MAC_VER_25: |
|
3664 case RTL_GIGA_MAC_VER_26: |
|
3665 case RTL_GIGA_MAC_VER_27: |
|
3666 case RTL_GIGA_MAC_VER_28: |
|
3667 case RTL_GIGA_MAC_VER_31: |
|
3668 case RTL_GIGA_MAC_VER_32: |
|
3669 case RTL_GIGA_MAC_VER_33: |
|
3670 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
|
3671 break; |
|
3672 } |
|
3673 |
|
3674 r8168_phy_power_up(tp); |
|
3675 } |
|
3676 |
|
3677 static void rtl_generic_op(struct rtl8169_private *tp, |
|
3678 void (*op)(struct rtl8169_private *)) |
|
3679 { |
|
3680 if (op) |
|
3681 op(tp); |
|
3682 } |
|
3683 |
|
3684 static void rtl_pll_power_down(struct rtl8169_private *tp) |
|
3685 { |
|
3686 rtl_generic_op(tp, tp->pll_power_ops.down); |
|
3687 } |
|
3688 |
|
3689 static void rtl_pll_power_up(struct rtl8169_private *tp) |
|
3690 { |
|
3691 rtl_generic_op(tp, tp->pll_power_ops.up); |
|
3692 } |
|
3693 |
|
3694 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) |
|
3695 { |
|
3696 struct pll_power_ops *ops = &tp->pll_power_ops; |
|
3697 |
|
3698 switch (tp->mac_version) { |
|
3699 case RTL_GIGA_MAC_VER_07: |
|
3700 case RTL_GIGA_MAC_VER_08: |
|
3701 case RTL_GIGA_MAC_VER_09: |
|
3702 case RTL_GIGA_MAC_VER_10: |
|
3703 case RTL_GIGA_MAC_VER_16: |
|
3704 case RTL_GIGA_MAC_VER_29: |
|
3705 case RTL_GIGA_MAC_VER_30: |
|
3706 ops->down = r810x_pll_power_down; |
|
3707 ops->up = r810x_pll_power_up; |
|
3708 break; |
|
3709 |
|
3710 case RTL_GIGA_MAC_VER_11: |
|
3711 case RTL_GIGA_MAC_VER_12: |
|
3712 case RTL_GIGA_MAC_VER_17: |
|
3713 case RTL_GIGA_MAC_VER_18: |
|
3714 case RTL_GIGA_MAC_VER_19: |
|
3715 case RTL_GIGA_MAC_VER_20: |
|
3716 case RTL_GIGA_MAC_VER_21: |
|
3717 case RTL_GIGA_MAC_VER_22: |
|
3718 case RTL_GIGA_MAC_VER_23: |
|
3719 case RTL_GIGA_MAC_VER_24: |
|
3720 case RTL_GIGA_MAC_VER_25: |
|
3721 case RTL_GIGA_MAC_VER_26: |
|
3722 case RTL_GIGA_MAC_VER_27: |
|
3723 case RTL_GIGA_MAC_VER_28: |
|
3724 case RTL_GIGA_MAC_VER_31: |
|
3725 case RTL_GIGA_MAC_VER_32: |
|
3726 case RTL_GIGA_MAC_VER_33: |
|
3727 case RTL_GIGA_MAC_VER_34: |
|
3728 case RTL_GIGA_MAC_VER_35: |
|
3729 case RTL_GIGA_MAC_VER_36: |
|
3730 ops->down = r8168_pll_power_down; |
|
3731 ops->up = r8168_pll_power_up; |
|
3732 break; |
|
3733 |
|
3734 default: |
|
3735 ops->down = NULL; |
|
3736 ops->up = NULL; |
|
3737 break; |
|
3738 } |
|
3739 } |
|
3740 |
|
3741 static void rtl_init_rxcfg(struct rtl8169_private *tp) |
|
3742 { |
|
3743 void __iomem *ioaddr = tp->mmio_addr; |
|
3744 |
|
3745 switch (tp->mac_version) { |
|
3746 case RTL_GIGA_MAC_VER_01: |
|
3747 case RTL_GIGA_MAC_VER_02: |
|
3748 case RTL_GIGA_MAC_VER_03: |
|
3749 case RTL_GIGA_MAC_VER_04: |
|
3750 case RTL_GIGA_MAC_VER_05: |
|
3751 case RTL_GIGA_MAC_VER_06: |
|
3752 case RTL_GIGA_MAC_VER_10: |
|
3753 case RTL_GIGA_MAC_VER_11: |
|
3754 case RTL_GIGA_MAC_VER_12: |
|
3755 case RTL_GIGA_MAC_VER_13: |
|
3756 case RTL_GIGA_MAC_VER_14: |
|
3757 case RTL_GIGA_MAC_VER_15: |
|
3758 case RTL_GIGA_MAC_VER_16: |
|
3759 case RTL_GIGA_MAC_VER_17: |
|
3760 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
|
3761 break; |
|
3762 case RTL_GIGA_MAC_VER_18: |
|
3763 case RTL_GIGA_MAC_VER_19: |
|
3764 case RTL_GIGA_MAC_VER_20: |
|
3765 case RTL_GIGA_MAC_VER_21: |
|
3766 case RTL_GIGA_MAC_VER_22: |
|
3767 case RTL_GIGA_MAC_VER_23: |
|
3768 case RTL_GIGA_MAC_VER_24: |
|
3769 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
|
3770 break; |
|
3771 default: |
|
3772 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); |
|
3773 break; |
|
3774 } |
|
3775 } |
|
3776 |
|
3777 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
3778 { |
|
3779 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
3780 } |
|
3781 |
|
3782 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3783 { |
|
3784 void __iomem *ioaddr = tp->mmio_addr; |
|
3785 |
|
3786 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3787 rtl_generic_op(tp, tp->jumbo_ops.enable); |
|
3788 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3789 } |
|
3790 |
|
3791 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3792 { |
|
3793 void __iomem *ioaddr = tp->mmio_addr; |
|
3794 |
|
3795 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3796 rtl_generic_op(tp, tp->jumbo_ops.disable); |
|
3797 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3798 } |
|
3799 |
|
3800 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3801 { |
|
3802 void __iomem *ioaddr = tp->mmio_addr; |
|
3803 |
|
3804 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3805 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); |
|
3806 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
3807 } |
|
3808 |
|
3809 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3810 { |
|
3811 void __iomem *ioaddr = tp->mmio_addr; |
|
3812 |
|
3813 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3814 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); |
|
3815 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3816 } |
|
3817 |
|
3818 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3819 { |
|
3820 void __iomem *ioaddr = tp->mmio_addr; |
|
3821 |
|
3822 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3823 } |
|
3824 |
|
3825 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3826 { |
|
3827 void __iomem *ioaddr = tp->mmio_addr; |
|
3828 |
|
3829 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3830 } |
|
3831 |
|
3832 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3833 { |
|
3834 void __iomem *ioaddr = tp->mmio_addr; |
|
3835 struct pci_dev *pdev = tp->pci_dev; |
|
3836 |
|
3837 RTL_W8(MaxTxPacketSize, 0x3f); |
|
3838 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3839 RTL_W8(Config4, RTL_R8(Config4) | 0x01); |
|
3840 pci_write_config_byte(pdev, 0x79, 0x20); |
|
3841 } |
|
3842 |
|
3843 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3844 { |
|
3845 void __iomem *ioaddr = tp->mmio_addr; |
|
3846 struct pci_dev *pdev = tp->pci_dev; |
|
3847 |
|
3848 RTL_W8(MaxTxPacketSize, 0x0c); |
|
3849 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3850 RTL_W8(Config4, RTL_R8(Config4) & ~0x01); |
|
3851 pci_write_config_byte(pdev, 0x79, 0x50); |
|
3852 } |
|
3853 |
|
3854 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3855 { |
|
3856 rtl_tx_performance_tweak(tp->pci_dev, |
|
3857 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3858 } |
|
3859 |
|
3860 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3861 { |
|
3862 rtl_tx_performance_tweak(tp->pci_dev, |
|
3863 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3864 } |
|
3865 |
|
3866 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3867 { |
|
3868 void __iomem *ioaddr = tp->mmio_addr; |
|
3869 |
|
3870 r8168b_0_hw_jumbo_enable(tp); |
|
3871 |
|
3872 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); |
|
3873 } |
|
3874 |
|
3875 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3876 { |
|
3877 void __iomem *ioaddr = tp->mmio_addr; |
|
3878 |
|
3879 r8168b_0_hw_jumbo_disable(tp); |
|
3880 |
|
3881 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
3882 } |
|
3883 |
|
3884 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) |
|
3885 { |
|
3886 struct jumbo_ops *ops = &tp->jumbo_ops; |
|
3887 |
|
3888 switch (tp->mac_version) { |
|
3889 case RTL_GIGA_MAC_VER_11: |
|
3890 ops->disable = r8168b_0_hw_jumbo_disable; |
|
3891 ops->enable = r8168b_0_hw_jumbo_enable; |
|
3892 break; |
|
3893 case RTL_GIGA_MAC_VER_12: |
|
3894 case RTL_GIGA_MAC_VER_17: |
|
3895 ops->disable = r8168b_1_hw_jumbo_disable; |
|
3896 ops->enable = r8168b_1_hw_jumbo_enable; |
|
3897 break; |
|
3898 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ |
|
3899 case RTL_GIGA_MAC_VER_19: |
|
3900 case RTL_GIGA_MAC_VER_20: |
|
3901 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ |
|
3902 case RTL_GIGA_MAC_VER_22: |
|
3903 case RTL_GIGA_MAC_VER_23: |
|
3904 case RTL_GIGA_MAC_VER_24: |
|
3905 case RTL_GIGA_MAC_VER_25: |
|
3906 case RTL_GIGA_MAC_VER_26: |
|
3907 ops->disable = r8168c_hw_jumbo_disable; |
|
3908 ops->enable = r8168c_hw_jumbo_enable; |
|
3909 break; |
|
3910 case RTL_GIGA_MAC_VER_27: |
|
3911 case RTL_GIGA_MAC_VER_28: |
|
3912 ops->disable = r8168dp_hw_jumbo_disable; |
|
3913 ops->enable = r8168dp_hw_jumbo_enable; |
|
3914 break; |
|
3915 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ |
|
3916 case RTL_GIGA_MAC_VER_32: |
|
3917 case RTL_GIGA_MAC_VER_33: |
|
3918 case RTL_GIGA_MAC_VER_34: |
|
3919 ops->disable = r8168e_hw_jumbo_disable; |
|
3920 ops->enable = r8168e_hw_jumbo_enable; |
|
3921 break; |
|
3922 |
|
3923 /* |
|
3924 * No action needed for jumbo frames with 8169. |
|
3925 * No jumbo for 810x at all. |
|
3926 */ |
|
3927 default: |
|
3928 ops->disable = NULL; |
|
3929 ops->enable = NULL; |
|
3930 break; |
|
3931 } |
|
3932 } |
|
3933 |
|
3934 static void rtl_hw_reset(struct rtl8169_private *tp) |
|
3935 { |
|
3936 void __iomem *ioaddr = tp->mmio_addr; |
|
3937 int i; |
|
3938 |
|
3939 /* Soft reset the chip. */ |
|
3940 RTL_W8(ChipCmd, CmdReset); |
|
3941 |
|
3942 /* Check that the chip has finished the reset. */ |
|
3943 for (i = 0; i < 100; i++) { |
|
3944 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3945 break; |
|
3946 udelay(100); |
|
3947 } |
|
3948 } |
|
3949 |
|
3950 static int __devinit |
|
3951 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
3952 { |
|
3953 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
3954 const unsigned int region = cfg->region; |
|
3955 struct rtl8169_private *tp; |
|
3956 struct mii_if_info *mii; |
|
3957 struct net_device *dev; |
|
3958 void __iomem *ioaddr; |
|
3959 int chipset, i; |
|
3960 int rc; |
|
3961 |
|
3962 if (netif_msg_drv(&debug)) { |
|
3963 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
3964 MODULENAME, RTL8169_VERSION); |
|
3965 } |
|
3966 |
|
3967 dev = alloc_etherdev(sizeof (*tp)); |
|
3968 if (!dev) { |
|
3969 if (netif_msg_drv(&debug)) |
|
3970 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
3971 rc = -ENOMEM; |
|
3972 goto out; |
|
3973 } |
|
3974 |
|
3975 SET_NETDEV_DEV(dev, &pdev->dev); |
|
3976 dev->netdev_ops = &rtl8169_netdev_ops; |
|
3977 tp = netdev_priv(dev); |
|
3978 tp->dev = dev; |
|
3979 tp->pci_dev = pdev; |
|
3980 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
3981 |
|
3982 mii = &tp->mii; |
|
3983 mii->dev = dev; |
|
3984 mii->mdio_read = rtl_mdio_read; |
|
3985 mii->mdio_write = rtl_mdio_write; |
|
3986 mii->phy_id_mask = 0x1f; |
|
3987 mii->reg_num_mask = 0x1f; |
|
3988 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
3989 |
|
3990 /* disable ASPM completely as that cause random device stop working |
|
3991 * problems as well as full system hangs for some PCIe devices users */ |
|
3992 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
|
3993 PCIE_LINK_STATE_CLKPM); |
|
3994 |
|
3995 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
3996 rc = pci_enable_device(pdev); |
|
3997 if (rc < 0) { |
|
3998 netif_err(tp, probe, dev, "enable failure\n"); |
|
3999 goto err_out_free_dev_1; |
|
4000 } |
|
4001 |
|
4002 if (pci_set_mwi(pdev) < 0) |
|
4003 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
|
4004 |
|
4005 /* make sure PCI base addr 1 is MMIO */ |
|
4006 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
4007 netif_err(tp, probe, dev, |
|
4008 "region #%d not an MMIO resource, aborting\n", |
|
4009 region); |
|
4010 rc = -ENODEV; |
|
4011 goto err_out_mwi_2; |
|
4012 } |
|
4013 |
|
4014 /* check for weird/broken PCI region reporting */ |
|
4015 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
4016 netif_err(tp, probe, dev, |
|
4017 "Invalid PCI region size(s), aborting\n"); |
|
4018 rc = -ENODEV; |
|
4019 goto err_out_mwi_2; |
|
4020 } |
|
4021 |
|
4022 rc = pci_request_regions(pdev, MODULENAME); |
|
4023 if (rc < 0) { |
|
4024 netif_err(tp, probe, dev, "could not request regions\n"); |
|
4025 goto err_out_mwi_2; |
|
4026 } |
|
4027 |
|
4028 tp->cp_cmd = RxChkSum; |
|
4029 |
|
4030 if ((sizeof(dma_addr_t) > 4) && |
|
4031 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
4032 tp->cp_cmd |= PCIDAC; |
|
4033 dev->features |= NETIF_F_HIGHDMA; |
|
4034 } else { |
|
4035 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
4036 if (rc < 0) { |
|
4037 netif_err(tp, probe, dev, "DMA configuration failed\n"); |
|
4038 goto err_out_free_res_3; |
|
4039 } |
|
4040 } |
|
4041 |
|
4042 /* ioremap MMIO region */ |
|
4043 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
4044 if (!ioaddr) { |
|
4045 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
|
4046 rc = -EIO; |
|
4047 goto err_out_free_res_3; |
|
4048 } |
|
4049 tp->mmio_addr = ioaddr; |
|
4050 |
|
4051 if (!pci_is_pcie(pdev)) |
|
4052 netif_info(tp, probe, dev, "not PCI Express\n"); |
|
4053 |
|
4054 /* Identify chip attached to board */ |
|
4055 rtl8169_get_mac_version(tp, dev, cfg->default_ver); |
|
4056 |
|
4057 rtl_init_rxcfg(tp); |
|
4058 |
|
4059 RTL_W16(IntrMask, 0x0000); |
|
4060 |
|
4061 rtl_hw_reset(tp); |
|
4062 |
|
4063 RTL_W16(IntrStatus, 0xffff); |
|
4064 |
|
4065 pci_set_master(pdev); |
|
4066 |
|
4067 /* |
|
4068 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
4069 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
4070 */ |
|
4071 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
4072 tp->cp_cmd |= RxVlan; |
|
4073 |
|
4074 rtl_init_mdio_ops(tp); |
|
4075 rtl_init_pll_power_ops(tp); |
|
4076 rtl_init_jumbo_ops(tp); |
|
4077 |
|
4078 rtl8169_print_mac_version(tp); |
|
4079 |
|
4080 chipset = tp->mac_version; |
|
4081 tp->txd_version = rtl_chip_infos[chipset].txd_version; |
|
4082 |
|
4083 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4084 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
4085 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
4086 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
4087 tp->features |= RTL_FEATURE_WOL; |
|
4088 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
4089 tp->features |= RTL_FEATURE_WOL; |
|
4090 tp->features |= rtl_try_msi(tp, cfg); |
|
4091 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4092 |
|
4093 if (rtl_tbi_enabled(tp)) { |
|
4094 tp->set_speed = rtl8169_set_speed_tbi; |
|
4095 tp->get_settings = rtl8169_gset_tbi; |
|
4096 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
4097 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
4098 tp->link_ok = rtl8169_tbi_link_ok; |
|
4099 tp->do_ioctl = rtl_tbi_ioctl; |
|
4100 } else { |
|
4101 tp->set_speed = rtl8169_set_speed_xmii; |
|
4102 tp->get_settings = rtl8169_gset_xmii; |
|
4103 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
4104 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
4105 tp->link_ok = rtl8169_xmii_link_ok; |
|
4106 tp->do_ioctl = rtl_xmii_ioctl; |
|
4107 } |
|
4108 |
|
4109 spin_lock_init(&tp->lock); |
|
4110 |
|
4111 /* Get MAC address */ |
|
4112 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
4113 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
4114 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
4115 |
|
4116 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
4117 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
4118 dev->irq = pdev->irq; |
|
4119 dev->base_addr = (unsigned long) ioaddr; |
|
4120 |
|
4121 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
4122 |
|
4123 /* don't enable SG, IP_CSUM and TSO by default - it might not work |
|
4124 * properly for all devices */ |
|
4125 dev->features |= NETIF_F_RXCSUM | |
|
4126 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
4127 |
|
4128 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
4129 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
4130 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
4131 NETIF_F_HIGHDMA; |
|
4132 |
|
4133 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
4134 /* 8110SCd requires hardware Rx VLAN - disallow toggling */ |
|
4135 dev->hw_features &= ~NETIF_F_HW_VLAN_RX; |
|
4136 |
|
4137 tp->intr_mask = 0xffff; |
|
4138 tp->hw_start = cfg->hw_start; |
|
4139 tp->intr_event = cfg->intr_event; |
|
4140 tp->napi_event = cfg->napi_event; |
|
4141 |
|
4142 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
|
4143 ~(RxBOVF | RxFOVF) : ~0; |
|
4144 |
|
4145 init_timer(&tp->timer); |
|
4146 tp->timer.data = (unsigned long) dev; |
|
4147 tp->timer.function = rtl8169_phy_timer; |
|
4148 |
|
4149 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
4150 |
|
4151 rc = register_netdev(dev); |
|
4152 if (rc < 0) |
|
4153 goto err_out_msi_4; |
|
4154 |
|
4155 pci_set_drvdata(pdev, dev); |
|
4156 |
|
4157 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
|
4158 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr, |
|
4159 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); |
|
4160 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
|
4161 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " |
|
4162 "tx checksumming: %s]\n", |
|
4163 rtl_chip_infos[chipset].jumbo_max, |
|
4164 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); |
|
4165 } |
|
4166 |
|
4167 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4168 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4169 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4170 rtl8168_driver_start(tp); |
|
4171 } |
|
4172 |
|
4173 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
4174 |
|
4175 if (pci_dev_run_wake(pdev)) |
|
4176 pm_runtime_put_noidle(&pdev->dev); |
|
4177 |
|
4178 netif_carrier_off(dev); |
|
4179 |
|
4180 out: |
|
4181 return rc; |
|
4182 |
|
4183 err_out_msi_4: |
|
4184 rtl_disable_msi(pdev, tp); |
|
4185 iounmap(ioaddr); |
|
4186 err_out_free_res_3: |
|
4187 pci_release_regions(pdev); |
|
4188 err_out_mwi_2: |
|
4189 pci_clear_mwi(pdev); |
|
4190 pci_disable_device(pdev); |
|
4191 err_out_free_dev_1: |
|
4192 free_netdev(dev); |
|
4193 goto out; |
|
4194 } |
|
4195 |
|
4196 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
4197 { |
|
4198 struct net_device *dev = pci_get_drvdata(pdev); |
|
4199 struct rtl8169_private *tp = netdev_priv(dev); |
|
4200 |
|
4201 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4202 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4203 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4204 rtl8168_driver_stop(tp); |
|
4205 } |
|
4206 |
|
4207 cancel_delayed_work_sync(&tp->task); |
|
4208 |
|
4209 unregister_netdev(dev); |
|
4210 |
|
4211 rtl_release_firmware(tp); |
|
4212 |
|
4213 if (pci_dev_run_wake(pdev)) |
|
4214 pm_runtime_get_noresume(&pdev->dev); |
|
4215 |
|
4216 /* restore original MAC address */ |
|
4217 rtl_rar_set(tp, dev->perm_addr); |
|
4218 |
|
4219 rtl_disable_msi(pdev, tp); |
|
4220 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
4221 pci_set_drvdata(pdev, NULL); |
|
4222 } |
|
4223 |
|
4224 static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
|
4225 { |
|
4226 struct rtl_fw *rtl_fw; |
|
4227 const char *name; |
|
4228 int rc = -ENOMEM; |
|
4229 |
|
4230 name = rtl_lookup_firmware_name(tp); |
|
4231 if (!name) |
|
4232 goto out_no_firmware; |
|
4233 |
|
4234 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
|
4235 if (!rtl_fw) |
|
4236 goto err_warn; |
|
4237 |
|
4238 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
|
4239 if (rc < 0) |
|
4240 goto err_free; |
|
4241 |
|
4242 rc = rtl_check_firmware(tp, rtl_fw); |
|
4243 if (rc < 0) |
|
4244 goto err_release_firmware; |
|
4245 |
|
4246 tp->rtl_fw = rtl_fw; |
|
4247 out: |
|
4248 return; |
|
4249 |
|
4250 err_release_firmware: |
|
4251 release_firmware(rtl_fw->fw); |
|
4252 err_free: |
|
4253 kfree(rtl_fw); |
|
4254 err_warn: |
|
4255 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", |
|
4256 name, rc); |
|
4257 out_no_firmware: |
|
4258 tp->rtl_fw = NULL; |
|
4259 goto out; |
|
4260 } |
|
4261 |
|
4262 static void rtl_request_firmware(struct rtl8169_private *tp) |
|
4263 { |
|
4264 if (IS_ERR(tp->rtl_fw)) |
|
4265 rtl_request_uncached_firmware(tp); |
|
4266 } |
|
4267 |
|
4268 static int rtl8169_open(struct net_device *dev) |
|
4269 { |
|
4270 struct rtl8169_private *tp = netdev_priv(dev); |
|
4271 void __iomem *ioaddr = tp->mmio_addr; |
|
4272 struct pci_dev *pdev = tp->pci_dev; |
|
4273 int retval = -ENOMEM; |
|
4274 |
|
4275 pm_runtime_get_sync(&pdev->dev); |
|
4276 |
|
4277 /* |
|
4278 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
4279 * dma_alloc_coherent provides more. |
|
4280 */ |
|
4281 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
|
4282 &tp->TxPhyAddr, GFP_KERNEL); |
|
4283 if (!tp->TxDescArray) |
|
4284 goto err_pm_runtime_put; |
|
4285 |
|
4286 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
|
4287 &tp->RxPhyAddr, GFP_KERNEL); |
|
4288 if (!tp->RxDescArray) |
|
4289 goto err_free_tx_0; |
|
4290 |
|
4291 retval = rtl8169_init_ring(dev); |
|
4292 if (retval < 0) |
|
4293 goto err_free_rx_1; |
|
4294 |
|
4295 INIT_DELAYED_WORK(&tp->task, NULL); |
|
4296 |
|
4297 smp_mb(); |
|
4298 |
|
4299 rtl_request_firmware(tp); |
|
4300 |
|
4301 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
4302 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
4303 dev->name, dev); |
|
4304 if (retval < 0) |
|
4305 goto err_release_fw_2; |
|
4306 |
|
4307 napi_enable(&tp->napi); |
|
4308 |
|
4309 rtl8169_init_phy(dev, tp); |
|
4310 |
|
4311 rtl8169_set_features(dev, dev->features); |
|
4312 |
|
4313 rtl_pll_power_up(tp); |
|
4314 |
|
4315 rtl_hw_start(dev); |
|
4316 |
|
4317 tp->saved_wolopts = 0; |
|
4318 pm_runtime_put_noidle(&pdev->dev); |
|
4319 |
|
4320 rtl8169_check_link_status(dev, tp, ioaddr); |
|
4321 out: |
|
4322 return retval; |
|
4323 |
|
4324 err_release_fw_2: |
|
4325 rtl_release_firmware(tp); |
|
4326 rtl8169_rx_clear(tp); |
|
4327 err_free_rx_1: |
|
4328 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
4329 tp->RxPhyAddr); |
|
4330 tp->RxDescArray = NULL; |
|
4331 err_free_tx_0: |
|
4332 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
4333 tp->TxPhyAddr); |
|
4334 tp->TxDescArray = NULL; |
|
4335 err_pm_runtime_put: |
|
4336 pm_runtime_put_noidle(&pdev->dev); |
|
4337 goto out; |
|
4338 } |
|
4339 |
|
4340 static void rtl_rx_close(struct rtl8169_private *tp) |
|
4341 { |
|
4342 void __iomem *ioaddr = tp->mmio_addr; |
|
4343 |
|
4344 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
|
4345 } |
|
4346 |
|
4347 static void rtl8169_hw_reset(struct rtl8169_private *tp) |
|
4348 { |
|
4349 void __iomem *ioaddr = tp->mmio_addr; |
|
4350 |
|
4351 /* Disable interrupts */ |
|
4352 rtl8169_irq_mask_and_ack(tp); |
|
4353 |
|
4354 rtl_rx_close(tp); |
|
4355 |
|
4356 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4357 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4358 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4359 while (RTL_R8(TxPoll) & NPQ) |
|
4360 udelay(20); |
|
4361 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
|
4362 tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
4363 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
4364 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4365 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
|
4366 udelay(100); |
|
4367 } else { |
|
4368 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4369 udelay(100); |
|
4370 } |
|
4371 |
|
4372 rtl_hw_reset(tp); |
|
4373 } |
|
4374 |
|
4375 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
4376 { |
|
4377 void __iomem *ioaddr = tp->mmio_addr; |
|
4378 |
|
4379 /* Set DMA burst size and Interframe Gap Time */ |
|
4380 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4381 (InterFrameGap << TxInterFrameGapShift)); |
|
4382 } |
|
4383 |
|
4384 static void rtl_hw_start(struct net_device *dev) |
|
4385 { |
|
4386 struct rtl8169_private *tp = netdev_priv(dev); |
|
4387 |
|
4388 tp->hw_start(dev); |
|
4389 |
|
4390 netif_start_queue(dev); |
|
4391 } |
|
4392 |
|
4393 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
4394 void __iomem *ioaddr) |
|
4395 { |
|
4396 /* |
|
4397 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
4398 * register to be written before TxDescAddrLow to work. |
|
4399 * Switching from MMIO to I/O access fixes the issue as well. |
|
4400 */ |
|
4401 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
4402 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
4403 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
4404 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
4405 } |
|
4406 |
|
4407 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
4408 { |
|
4409 u16 cmd; |
|
4410 |
|
4411 cmd = RTL_R16(CPlusCmd); |
|
4412 RTL_W16(CPlusCmd, cmd); |
|
4413 return cmd; |
|
4414 } |
|
4415 |
|
4416 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
4417 { |
|
4418 /* Low hurts. Let's disable the filtering. */ |
|
4419 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
4420 } |
|
4421 |
|
4422 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
4423 { |
|
4424 static const struct rtl_cfg2_info { |
|
4425 u32 mac_version; |
|
4426 u32 clk; |
|
4427 u32 val; |
|
4428 } cfg2_info [] = { |
|
4429 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
4430 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
4431 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
4432 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
4433 }; |
|
4434 const struct rtl_cfg2_info *p = cfg2_info; |
|
4435 unsigned int i; |
|
4436 u32 clk; |
|
4437 |
|
4438 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
4439 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
4440 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
4441 RTL_W32(0x7c, p->val); |
|
4442 break; |
|
4443 } |
|
4444 } |
|
4445 } |
|
4446 |
|
4447 static void rtl_hw_start_8169(struct net_device *dev) |
|
4448 { |
|
4449 struct rtl8169_private *tp = netdev_priv(dev); |
|
4450 void __iomem *ioaddr = tp->mmio_addr; |
|
4451 struct pci_dev *pdev = tp->pci_dev; |
|
4452 |
|
4453 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
4454 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
4455 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
4456 } |
|
4457 |
|
4458 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4459 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4460 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4461 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4462 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4463 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4464 |
|
4465 rtl_init_rxcfg(tp); |
|
4466 |
|
4467 RTL_W8(EarlyTxThres, NoEarlyTx); |
|
4468 |
|
4469 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4470 |
|
4471 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4472 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4473 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4474 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4475 rtl_set_rx_tx_config_registers(tp); |
|
4476 |
|
4477 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
4478 |
|
4479 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4480 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
4481 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
4482 "Bit-3 and bit-14 MUST be 1\n"); |
|
4483 tp->cp_cmd |= (1 << 14); |
|
4484 } |
|
4485 |
|
4486 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4487 |
|
4488 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
4489 |
|
4490 /* |
|
4491 * Undocumented corner. Supposedly: |
|
4492 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
4493 */ |
|
4494 RTL_W16(IntrMitigate, 0x0000); |
|
4495 |
|
4496 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4497 |
|
4498 if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
|
4499 tp->mac_version != RTL_GIGA_MAC_VER_02 && |
|
4500 tp->mac_version != RTL_GIGA_MAC_VER_03 && |
|
4501 tp->mac_version != RTL_GIGA_MAC_VER_04) { |
|
4502 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4503 rtl_set_rx_tx_config_registers(tp); |
|
4504 } |
|
4505 |
|
4506 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4507 |
|
4508 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
4509 RTL_R8(IntrMask); |
|
4510 |
|
4511 RTL_W32(RxMissed, 0); |
|
4512 |
|
4513 rtl_set_rx_mode(dev); |
|
4514 |
|
4515 /* no early-rx interrupts */ |
|
4516 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4517 |
|
4518 /* Enable all known interrupts by setting the interrupt mask. */ |
|
4519 RTL_W16(IntrMask, tp->intr_event); |
|
4520 } |
|
4521 |
|
4522 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
|
4523 { |
|
4524 u32 csi; |
|
4525 |
|
4526 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
4527 rtl_csi_write(ioaddr, 0x070c, csi | bits); |
|
4528 } |
|
4529 |
|
4530 static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
|
4531 { |
|
4532 rtl_csi_access_enable(ioaddr, 0x17000000); |
|
4533 } |
|
4534 |
|
4535 static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
|
4536 { |
|
4537 rtl_csi_access_enable(ioaddr, 0x27000000); |
|
4538 } |
|
4539 |
|
4540 struct ephy_info { |
|
4541 unsigned int offset; |
|
4542 u16 mask; |
|
4543 u16 bits; |
|
4544 }; |
|
4545 |
|
4546 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
|
4547 { |
|
4548 u16 w; |
|
4549 |
|
4550 while (len-- > 0) { |
|
4551 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
4552 rtl_ephy_write(ioaddr, e->offset, w); |
|
4553 e++; |
|
4554 } |
|
4555 } |
|
4556 |
|
4557 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
4558 { |
|
4559 int cap = pci_pcie_cap(pdev); |
|
4560 |
|
4561 if (cap) { |
|
4562 u16 ctl; |
|
4563 |
|
4564 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4565 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4566 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4567 } |
|
4568 } |
|
4569 |
|
4570 static void rtl_enable_clock_request(struct pci_dev *pdev) |
|
4571 { |
|
4572 int cap = pci_pcie_cap(pdev); |
|
4573 |
|
4574 if (cap) { |
|
4575 u16 ctl; |
|
4576 |
|
4577 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4578 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4579 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4580 } |
|
4581 } |
|
4582 |
|
4583 #define R8168_CPCMD_QUIRK_MASK (\ |
|
4584 EnableBist | \ |
|
4585 Mac_dbgo_oe | \ |
|
4586 Force_half_dup | \ |
|
4587 Force_rxflow_en | \ |
|
4588 Force_txflow_en | \ |
|
4589 Cxpl_dbg_sel | \ |
|
4590 ASF | \ |
|
4591 PktCntrDisable | \ |
|
4592 Mac_dbgo_sel) |
|
4593 |
|
4594 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4595 { |
|
4596 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4597 |
|
4598 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4599 |
|
4600 rtl_tx_performance_tweak(pdev, |
|
4601 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4602 } |
|
4603 |
|
4604 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4605 { |
|
4606 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4607 |
|
4608 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4609 |
|
4610 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
4611 } |
|
4612 |
|
4613 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4614 { |
|
4615 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
4616 |
|
4617 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4618 |
|
4619 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4620 |
|
4621 rtl_disable_clock_request(pdev); |
|
4622 |
|
4623 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4624 } |
|
4625 |
|
4626 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4627 { |
|
4628 static const struct ephy_info e_info_8168cp[] = { |
|
4629 { 0x01, 0, 0x0001 }, |
|
4630 { 0x02, 0x0800, 0x1000 }, |
|
4631 { 0x03, 0, 0x0042 }, |
|
4632 { 0x06, 0x0080, 0x0000 }, |
|
4633 { 0x07, 0, 0x2000 } |
|
4634 }; |
|
4635 |
|
4636 rtl_csi_access_enable_2(ioaddr); |
|
4637 |
|
4638 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
4639 |
|
4640 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4641 } |
|
4642 |
|
4643 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4644 { |
|
4645 rtl_csi_access_enable_2(ioaddr); |
|
4646 |
|
4647 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4648 |
|
4649 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4650 |
|
4651 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4652 } |
|
4653 |
|
4654 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4655 { |
|
4656 rtl_csi_access_enable_2(ioaddr); |
|
4657 |
|
4658 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4659 |
|
4660 /* Magic. */ |
|
4661 RTL_W8(DBG_REG, 0x20); |
|
4662 |
|
4663 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4664 |
|
4665 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4666 |
|
4667 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4668 } |
|
4669 |
|
4670 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4671 { |
|
4672 static const struct ephy_info e_info_8168c_1[] = { |
|
4673 { 0x02, 0x0800, 0x1000 }, |
|
4674 { 0x03, 0, 0x0002 }, |
|
4675 { 0x06, 0x0080, 0x0000 } |
|
4676 }; |
|
4677 |
|
4678 rtl_csi_access_enable_2(ioaddr); |
|
4679 |
|
4680 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
4681 |
|
4682 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
4683 |
|
4684 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4685 } |
|
4686 |
|
4687 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4688 { |
|
4689 static const struct ephy_info e_info_8168c_2[] = { |
|
4690 { 0x01, 0, 0x0001 }, |
|
4691 { 0x03, 0x0400, 0x0220 } |
|
4692 }; |
|
4693 |
|
4694 rtl_csi_access_enable_2(ioaddr); |
|
4695 |
|
4696 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
4697 |
|
4698 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4699 } |
|
4700 |
|
4701 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4702 { |
|
4703 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4704 } |
|
4705 |
|
4706 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4707 { |
|
4708 rtl_csi_access_enable_2(ioaddr); |
|
4709 |
|
4710 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4711 } |
|
4712 |
|
4713 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4714 { |
|
4715 rtl_csi_access_enable_2(ioaddr); |
|
4716 |
|
4717 rtl_disable_clock_request(pdev); |
|
4718 |
|
4719 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4720 |
|
4721 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4722 |
|
4723 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4724 } |
|
4725 |
|
4726 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4727 { |
|
4728 rtl_csi_access_enable_1(ioaddr); |
|
4729 |
|
4730 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4731 |
|
4732 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4733 |
|
4734 rtl_disable_clock_request(pdev); |
|
4735 } |
|
4736 |
|
4737 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4738 { |
|
4739 static const struct ephy_info e_info_8168d_4[] = { |
|
4740 { 0x0b, ~0, 0x48 }, |
|
4741 { 0x19, 0x20, 0x50 }, |
|
4742 { 0x0c, ~0, 0x20 } |
|
4743 }; |
|
4744 int i; |
|
4745 |
|
4746 rtl_csi_access_enable_1(ioaddr); |
|
4747 |
|
4748 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4749 |
|
4750 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4751 |
|
4752 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { |
|
4753 const struct ephy_info *e = e_info_8168d_4 + i; |
|
4754 u16 w; |
|
4755 |
|
4756 w = rtl_ephy_read(ioaddr, e->offset); |
|
4757 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); |
|
4758 } |
|
4759 |
|
4760 rtl_enable_clock_request(pdev); |
|
4761 } |
|
4762 |
|
4763 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4764 { |
|
4765 static const struct ephy_info e_info_8168e_1[] = { |
|
4766 { 0x00, 0x0200, 0x0100 }, |
|
4767 { 0x00, 0x0000, 0x0004 }, |
|
4768 { 0x06, 0x0002, 0x0001 }, |
|
4769 { 0x06, 0x0000, 0x0030 }, |
|
4770 { 0x07, 0x0000, 0x2000 }, |
|
4771 { 0x00, 0x0000, 0x0020 }, |
|
4772 { 0x03, 0x5800, 0x2000 }, |
|
4773 { 0x03, 0x0000, 0x0001 }, |
|
4774 { 0x01, 0x0800, 0x1000 }, |
|
4775 { 0x07, 0x0000, 0x4000 }, |
|
4776 { 0x1e, 0x0000, 0x2000 }, |
|
4777 { 0x19, 0xffff, 0xfe6c }, |
|
4778 { 0x0a, 0x0000, 0x0040 } |
|
4779 }; |
|
4780 |
|
4781 rtl_csi_access_enable_2(ioaddr); |
|
4782 |
|
4783 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
|
4784 |
|
4785 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4786 |
|
4787 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4788 |
|
4789 rtl_disable_clock_request(pdev); |
|
4790 |
|
4791 /* Reset tx FIFO pointer */ |
|
4792 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
|
4793 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); |
|
4794 |
|
4795 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4796 } |
|
4797 |
|
4798 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4799 { |
|
4800 static const struct ephy_info e_info_8168e_2[] = { |
|
4801 { 0x09, 0x0000, 0x0080 }, |
|
4802 { 0x19, 0x0000, 0x0224 } |
|
4803 }; |
|
4804 |
|
4805 rtl_csi_access_enable_1(ioaddr); |
|
4806 |
|
4807 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
|
4808 |
|
4809 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4810 |
|
4811 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4812 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4813 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4814 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4815 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4816 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); |
|
4817 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4818 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4819 ERIAR_EXGMAC); |
|
4820 |
|
4821 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4822 |
|
4823 rtl_disable_clock_request(pdev); |
|
4824 |
|
4825 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4826 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4827 |
|
4828 /* Adjust EEE LED frequency */ |
|
4829 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4830 |
|
4831 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4832 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4833 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4834 } |
|
4835 |
|
4836 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4837 { |
|
4838 static const struct ephy_info e_info_8168f_1[] = { |
|
4839 { 0x06, 0x00c0, 0x0020 }, |
|
4840 { 0x08, 0x0001, 0x0002 }, |
|
4841 { 0x09, 0x0000, 0x0080 }, |
|
4842 { 0x19, 0x0000, 0x0224 } |
|
4843 }; |
|
4844 |
|
4845 rtl_csi_access_enable_1(ioaddr); |
|
4846 |
|
4847 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
|
4848 |
|
4849 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4850 |
|
4851 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4852 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4853 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4854 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4855 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
4856 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
4857 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4858 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4859 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4860 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); |
|
4861 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4862 ERIAR_EXGMAC); |
|
4863 |
|
4864 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4865 |
|
4866 rtl_disable_clock_request(pdev); |
|
4867 |
|
4868 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4869 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4870 |
|
4871 /* Adjust EEE LED frequency */ |
|
4872 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4873 |
|
4874 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4875 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4876 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4877 } |
|
4878 |
|
4879 static void rtl_hw_start_8168(struct net_device *dev) |
|
4880 { |
|
4881 struct rtl8169_private *tp = netdev_priv(dev); |
|
4882 void __iomem *ioaddr = tp->mmio_addr; |
|
4883 struct pci_dev *pdev = tp->pci_dev; |
|
4884 |
|
4885 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4886 |
|
4887 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4888 |
|
4889 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4890 |
|
4891 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
4892 |
|
4893 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4894 |
|
4895 RTL_W16(IntrMitigate, 0x5151); |
|
4896 |
|
4897 /* Work around for RxFIFO overflow. */ |
|
4898 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
4899 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
4900 tp->intr_event &= ~RxOverflow; |
|
4901 } |
|
4902 |
|
4903 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4904 |
|
4905 rtl_set_rx_mode(dev); |
|
4906 |
|
4907 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4908 (InterFrameGap << TxInterFrameGapShift)); |
|
4909 |
|
4910 RTL_R8(IntrMask); |
|
4911 |
|
4912 switch (tp->mac_version) { |
|
4913 case RTL_GIGA_MAC_VER_11: |
|
4914 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4915 break; |
|
4916 |
|
4917 case RTL_GIGA_MAC_VER_12: |
|
4918 case RTL_GIGA_MAC_VER_17: |
|
4919 rtl_hw_start_8168bef(ioaddr, pdev); |
|
4920 break; |
|
4921 |
|
4922 case RTL_GIGA_MAC_VER_18: |
|
4923 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
4924 break; |
|
4925 |
|
4926 case RTL_GIGA_MAC_VER_19: |
|
4927 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
4928 break; |
|
4929 |
|
4930 case RTL_GIGA_MAC_VER_20: |
|
4931 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4932 break; |
|
4933 |
|
4934 case RTL_GIGA_MAC_VER_21: |
|
4935 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
4936 break; |
|
4937 |
|
4938 case RTL_GIGA_MAC_VER_22: |
|
4939 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
4940 break; |
|
4941 |
|
4942 case RTL_GIGA_MAC_VER_23: |
|
4943 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
4944 break; |
|
4945 |
|
4946 case RTL_GIGA_MAC_VER_24: |
|
4947 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
4948 break; |
|
4949 |
|
4950 case RTL_GIGA_MAC_VER_25: |
|
4951 case RTL_GIGA_MAC_VER_26: |
|
4952 case RTL_GIGA_MAC_VER_27: |
|
4953 rtl_hw_start_8168d(ioaddr, pdev); |
|
4954 break; |
|
4955 |
|
4956 case RTL_GIGA_MAC_VER_28: |
|
4957 rtl_hw_start_8168d_4(ioaddr, pdev); |
|
4958 break; |
|
4959 |
|
4960 case RTL_GIGA_MAC_VER_31: |
|
4961 rtl_hw_start_8168dp(ioaddr, pdev); |
|
4962 break; |
|
4963 |
|
4964 case RTL_GIGA_MAC_VER_32: |
|
4965 case RTL_GIGA_MAC_VER_33: |
|
4966 rtl_hw_start_8168e_1(ioaddr, pdev); |
|
4967 break; |
|
4968 case RTL_GIGA_MAC_VER_34: |
|
4969 rtl_hw_start_8168e_2(ioaddr, pdev); |
|
4970 break; |
|
4971 |
|
4972 case RTL_GIGA_MAC_VER_35: |
|
4973 case RTL_GIGA_MAC_VER_36: |
|
4974 rtl_hw_start_8168f_1(ioaddr, pdev); |
|
4975 break; |
|
4976 |
|
4977 default: |
|
4978 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
4979 dev->name, tp->mac_version); |
|
4980 break; |
|
4981 } |
|
4982 |
|
4983 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4984 |
|
4985 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4986 |
|
4987 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4988 |
|
4989 RTL_W16(IntrMask, tp->intr_event); |
|
4990 } |
|
4991 |
|
4992 #define R810X_CPCMD_QUIRK_MASK (\ |
|
4993 EnableBist | \ |
|
4994 Mac_dbgo_oe | \ |
|
4995 Force_half_dup | \ |
|
4996 Force_rxflow_en | \ |
|
4997 Force_txflow_en | \ |
|
4998 Cxpl_dbg_sel | \ |
|
4999 ASF | \ |
|
5000 PktCntrDisable | \ |
|
5001 Mac_dbgo_sel) |
|
5002 |
|
5003 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
5004 { |
|
5005 static const struct ephy_info e_info_8102e_1[] = { |
|
5006 { 0x01, 0, 0x6e65 }, |
|
5007 { 0x02, 0, 0x091f }, |
|
5008 { 0x03, 0, 0xc2f9 }, |
|
5009 { 0x06, 0, 0xafb5 }, |
|
5010 { 0x07, 0, 0x0e00 }, |
|
5011 { 0x19, 0, 0xec80 }, |
|
5012 { 0x01, 0, 0x2e65 }, |
|
5013 { 0x01, 0, 0x6e65 } |
|
5014 }; |
|
5015 u8 cfg1; |
|
5016 |
|
5017 rtl_csi_access_enable_2(ioaddr); |
|
5018 |
|
5019 RTL_W8(DBG_REG, FIX_NAK_1); |
|
5020 |
|
5021 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5022 |
|
5023 RTL_W8(Config1, |
|
5024 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
5025 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
5026 |
|
5027 cfg1 = RTL_R8(Config1); |
|
5028 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
5029 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
5030 |
|
5031 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
5032 } |
|
5033 |
|
5034 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
5035 { |
|
5036 rtl_csi_access_enable_2(ioaddr); |
|
5037 |
|
5038 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5039 |
|
5040 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
5041 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
5042 } |
|
5043 |
|
5044 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
5045 { |
|
5046 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
5047 |
|
5048 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
5049 } |
|
5050 |
|
5051 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
5052 { |
|
5053 static const struct ephy_info e_info_8105e_1[] = { |
|
5054 { 0x07, 0, 0x4000 }, |
|
5055 { 0x19, 0, 0x0200 }, |
|
5056 { 0x19, 0, 0x0020 }, |
|
5057 { 0x1e, 0, 0x2000 }, |
|
5058 { 0x03, 0, 0x0001 }, |
|
5059 { 0x19, 0, 0x0100 }, |
|
5060 { 0x19, 0, 0x0004 }, |
|
5061 { 0x0a, 0, 0x0020 } |
|
5062 }; |
|
5063 |
|
5064 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
5065 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
5066 |
|
5067 /* Disable Early Tally Counter */ |
|
5068 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
|
5069 |
|
5070 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
|
5071 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
5072 |
|
5073 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
|
5074 } |
|
5075 |
|
5076 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
5077 { |
|
5078 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
5079 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); |
|
5080 } |
|
5081 |
|
5082 static void rtl_hw_start_8101(struct net_device *dev) |
|
5083 { |
|
5084 struct rtl8169_private *tp = netdev_priv(dev); |
|
5085 void __iomem *ioaddr = tp->mmio_addr; |
|
5086 struct pci_dev *pdev = tp->pci_dev; |
|
5087 |
|
5088 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) { |
|
5089 tp->intr_event &= ~RxFIFOOver; |
|
5090 tp->napi_event &= ~RxFIFOOver; |
|
5091 } |
|
5092 |
|
5093 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
|
5094 tp->mac_version == RTL_GIGA_MAC_VER_16) { |
|
5095 int cap = pci_pcie_cap(pdev); |
|
5096 |
|
5097 if (cap) { |
|
5098 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
5099 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
5100 } |
|
5101 } |
|
5102 |
|
5103 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
5104 |
|
5105 switch (tp->mac_version) { |
|
5106 case RTL_GIGA_MAC_VER_07: |
|
5107 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
5108 break; |
|
5109 |
|
5110 case RTL_GIGA_MAC_VER_08: |
|
5111 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
5112 break; |
|
5113 |
|
5114 case RTL_GIGA_MAC_VER_09: |
|
5115 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
5116 break; |
|
5117 |
|
5118 case RTL_GIGA_MAC_VER_29: |
|
5119 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
5120 break; |
|
5121 case RTL_GIGA_MAC_VER_30: |
|
5122 rtl_hw_start_8105e_2(ioaddr, pdev); |
|
5123 break; |
|
5124 } |
|
5125 |
|
5126 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
5127 |
|
5128 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
5129 |
|
5130 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
5131 |
|
5132 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
|
5133 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5134 |
|
5135 RTL_W16(IntrMitigate, 0x0000); |
|
5136 |
|
5137 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
5138 |
|
5139 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
5140 rtl_set_rx_tx_config_registers(tp); |
|
5141 |
|
5142 RTL_R8(IntrMask); |
|
5143 |
|
5144 rtl_set_rx_mode(dev); |
|
5145 |
|
5146 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
5147 |
|
5148 RTL_W16(IntrMask, tp->intr_event); |
|
5149 } |
|
5150 |
|
5151 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
5152 { |
|
5153 struct rtl8169_private *tp = netdev_priv(dev); |
|
5154 |
|
5155 if (new_mtu < ETH_ZLEN || |
|
5156 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) |
|
5157 return -EINVAL; |
|
5158 |
|
5159 if (new_mtu > ETH_DATA_LEN) |
|
5160 rtl_hw_jumbo_enable(tp); |
|
5161 else |
|
5162 rtl_hw_jumbo_disable(tp); |
|
5163 |
|
5164 dev->mtu = new_mtu; |
|
5165 netdev_update_features(dev); |
|
5166 |
|
5167 return 0; |
|
5168 } |
|
5169 |
|
5170 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
5171 { |
|
5172 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
5173 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
5174 } |
|
5175 |
|
5176 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
|
5177 void **data_buff, struct RxDesc *desc) |
|
5178 { |
|
5179 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
|
5180 DMA_FROM_DEVICE); |
|
5181 |
|
5182 kfree(*data_buff); |
|
5183 *data_buff = NULL; |
|
5184 rtl8169_make_unusable_by_asic(desc); |
|
5185 } |
|
5186 |
|
5187 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
5188 { |
|
5189 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
5190 |
|
5191 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
5192 } |
|
5193 |
|
5194 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
5195 u32 rx_buf_sz) |
|
5196 { |
|
5197 desc->addr = cpu_to_le64(mapping); |
|
5198 wmb(); |
|
5199 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5200 } |
|
5201 |
|
5202 static inline void *rtl8169_align(void *data) |
|
5203 { |
|
5204 return (void *)ALIGN((long)data, 16); |
|
5205 } |
|
5206 |
|
5207 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
|
5208 struct RxDesc *desc) |
|
5209 { |
|
5210 void *data; |
|
5211 dma_addr_t mapping; |
|
5212 struct device *d = &tp->pci_dev->dev; |
|
5213 struct net_device *dev = tp->dev; |
|
5214 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
|
5215 |
|
5216 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
|
5217 if (!data) |
|
5218 return NULL; |
|
5219 |
|
5220 if (rtl8169_align(data) != data) { |
|
5221 kfree(data); |
|
5222 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); |
|
5223 if (!data) |
|
5224 return NULL; |
|
5225 } |
|
5226 |
|
5227 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
|
5228 DMA_FROM_DEVICE); |
|
5229 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5230 if (net_ratelimit()) |
|
5231 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); |
|
5232 goto err_out; |
|
5233 } |
|
5234 |
|
5235 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
5236 return data; |
|
5237 |
|
5238 err_out: |
|
5239 kfree(data); |
|
5240 return NULL; |
|
5241 } |
|
5242 |
|
5243 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
5244 { |
|
5245 unsigned int i; |
|
5246 |
|
5247 for (i = 0; i < NUM_RX_DESC; i++) { |
|
5248 if (tp->Rx_databuff[i]) { |
|
5249 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, |
|
5250 tp->RxDescArray + i); |
|
5251 } |
|
5252 } |
|
5253 } |
|
5254 |
|
5255 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
5256 { |
|
5257 desc->opts1 |= cpu_to_le32(RingEnd); |
|
5258 } |
|
5259 |
|
5260 static int rtl8169_rx_fill(struct rtl8169_private *tp) |
|
5261 { |
|
5262 unsigned int i; |
|
5263 |
|
5264 for (i = 0; i < NUM_RX_DESC; i++) { |
|
5265 void *data; |
|
5266 |
|
5267 if (tp->Rx_databuff[i]) |
|
5268 continue; |
|
5269 |
|
5270 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
|
5271 if (!data) { |
|
5272 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); |
|
5273 goto err_out; |
|
5274 } |
|
5275 tp->Rx_databuff[i] = data; |
|
5276 } |
|
5277 |
|
5278 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
5279 return 0; |
|
5280 |
|
5281 err_out: |
|
5282 rtl8169_rx_clear(tp); |
|
5283 return -ENOMEM; |
|
5284 } |
|
5285 |
|
5286 static int rtl8169_init_ring(struct net_device *dev) |
|
5287 { |
|
5288 struct rtl8169_private *tp = netdev_priv(dev); |
|
5289 |
|
5290 rtl8169_init_ring_indexes(tp); |
|
5291 |
|
5292 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
5293 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
|
5294 |
|
5295 return rtl8169_rx_fill(tp); |
|
5296 } |
|
5297 |
|
5298 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
|
5299 struct TxDesc *desc) |
|
5300 { |
|
5301 unsigned int len = tx_skb->len; |
|
5302 |
|
5303 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
|
5304 |
|
5305 desc->opts1 = 0x00; |
|
5306 desc->opts2 = 0x00; |
|
5307 desc->addr = 0x00; |
|
5308 tx_skb->len = 0; |
|
5309 } |
|
5310 |
|
5311 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
|
5312 unsigned int n) |
|
5313 { |
|
5314 unsigned int i; |
|
5315 |
|
5316 for (i = 0; i < n; i++) { |
|
5317 unsigned int entry = (start + i) % NUM_TX_DESC; |
|
5318 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5319 unsigned int len = tx_skb->len; |
|
5320 |
|
5321 if (len) { |
|
5322 struct sk_buff *skb = tx_skb->skb; |
|
5323 |
|
5324 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5325 tp->TxDescArray + entry); |
|
5326 if (skb) { |
|
5327 tp->dev->stats.tx_dropped++; |
|
5328 dev_kfree_skb(skb); |
|
5329 tx_skb->skb = NULL; |
|
5330 } |
|
5331 } |
|
5332 } |
|
5333 } |
|
5334 |
|
5335 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
5336 { |
|
5337 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); |
|
5338 tp->cur_tx = tp->dirty_tx = 0; |
|
5339 } |
|
5340 |
|
5341 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
5342 { |
|
5343 struct rtl8169_private *tp = netdev_priv(dev); |
|
5344 |
|
5345 PREPARE_DELAYED_WORK(&tp->task, task); |
|
5346 schedule_delayed_work(&tp->task, 4); |
|
5347 } |
|
5348 |
|
5349 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
5350 { |
|
5351 struct rtl8169_private *tp = netdev_priv(dev); |
|
5352 void __iomem *ioaddr = tp->mmio_addr; |
|
5353 |
|
5354 synchronize_irq(dev->irq); |
|
5355 |
|
5356 /* Wait for any pending NAPI task to complete */ |
|
5357 napi_disable(&tp->napi); |
|
5358 |
|
5359 rtl8169_irq_mask_and_ack(tp); |
|
5360 |
|
5361 tp->intr_mask = 0xffff; |
|
5362 RTL_W16(IntrMask, tp->intr_event); |
|
5363 napi_enable(&tp->napi); |
|
5364 } |
|
5365 |
|
5366 static void rtl8169_reinit_task(struct work_struct *work) |
|
5367 { |
|
5368 struct rtl8169_private *tp = |
|
5369 container_of(work, struct rtl8169_private, task.work); |
|
5370 struct net_device *dev = tp->dev; |
|
5371 int ret; |
|
5372 |
|
5373 rtnl_lock(); |
|
5374 |
|
5375 if (!netif_running(dev)) |
|
5376 goto out_unlock; |
|
5377 |
|
5378 rtl8169_wait_for_quiescence(dev); |
|
5379 rtl8169_close(dev); |
|
5380 |
|
5381 ret = rtl8169_open(dev); |
|
5382 if (unlikely(ret < 0)) { |
|
5383 if (net_ratelimit()) |
|
5384 netif_err(tp, drv, dev, |
|
5385 "reinit failure (status = %d). Rescheduling\n", |
|
5386 ret); |
|
5387 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
5388 } |
|
5389 |
|
5390 out_unlock: |
|
5391 rtnl_unlock(); |
|
5392 } |
|
5393 |
|
5394 static void rtl8169_reset_task(struct work_struct *work) |
|
5395 { |
|
5396 struct rtl8169_private *tp = |
|
5397 container_of(work, struct rtl8169_private, task.work); |
|
5398 struct net_device *dev = tp->dev; |
|
5399 int i; |
|
5400 |
|
5401 rtnl_lock(); |
|
5402 |
|
5403 if (!netif_running(dev)) |
|
5404 goto out_unlock; |
|
5405 |
|
5406 rtl8169_hw_reset(tp); |
|
5407 |
|
5408 rtl8169_wait_for_quiescence(dev); |
|
5409 |
|
5410 for (i = 0; i < NUM_RX_DESC; i++) |
|
5411 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); |
|
5412 |
|
5413 rtl8169_tx_clear(tp); |
|
5414 rtl8169_init_ring_indexes(tp); |
|
5415 |
|
5416 rtl_hw_start(dev); |
|
5417 netif_wake_queue(dev); |
|
5418 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
5419 |
|
5420 out_unlock: |
|
5421 rtnl_unlock(); |
|
5422 } |
|
5423 |
|
5424 static void rtl8169_tx_timeout(struct net_device *dev) |
|
5425 { |
|
5426 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
5427 } |
|
5428 |
|
5429 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
5430 u32 *opts) |
|
5431 { |
|
5432 struct skb_shared_info *info = skb_shinfo(skb); |
|
5433 unsigned int cur_frag, entry; |
|
5434 struct TxDesc * uninitialized_var(txd); |
|
5435 struct device *d = &tp->pci_dev->dev; |
|
5436 |
|
5437 entry = tp->cur_tx; |
|
5438 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
5439 const skb_frag_t *frag = info->frags + cur_frag; |
|
5440 dma_addr_t mapping; |
|
5441 u32 status, len; |
|
5442 void *addr; |
|
5443 |
|
5444 entry = (entry + 1) % NUM_TX_DESC; |
|
5445 |
|
5446 txd = tp->TxDescArray + entry; |
|
5447 len = skb_frag_size(frag); |
|
5448 addr = skb_frag_address(frag); |
|
5449 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
|
5450 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5451 if (net_ratelimit()) |
|
5452 netif_err(tp, drv, tp->dev, |
|
5453 "Failed to map TX fragments DMA!\n"); |
|
5454 goto err_out; |
|
5455 } |
|
5456 |
|
5457 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5458 status = opts[0] | len | |
|
5459 (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5460 |
|
5461 txd->opts1 = cpu_to_le32(status); |
|
5462 txd->opts2 = cpu_to_le32(opts[1]); |
|
5463 txd->addr = cpu_to_le64(mapping); |
|
5464 |
|
5465 tp->tx_skb[entry].len = len; |
|
5466 } |
|
5467 |
|
5468 if (cur_frag) { |
|
5469 tp->tx_skb[entry].skb = skb; |
|
5470 txd->opts1 |= cpu_to_le32(LastFrag); |
|
5471 } |
|
5472 |
|
5473 return cur_frag; |
|
5474 |
|
5475 err_out: |
|
5476 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); |
|
5477 return -EIO; |
|
5478 } |
|
5479 |
|
5480 static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
|
5481 struct sk_buff *skb, u32 *opts) |
|
5482 { |
|
5483 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
|
5484 u32 mss = skb_shinfo(skb)->gso_size; |
|
5485 int offset = info->opts_offset; |
|
5486 |
|
5487 if (mss) { |
|
5488 opts[0] |= TD_LSO; |
|
5489 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; |
|
5490 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
5491 const struct iphdr *ip = ip_hdr(skb); |
|
5492 |
|
5493 if (ip->protocol == IPPROTO_TCP) |
|
5494 opts[offset] |= info->checksum.tcp; |
|
5495 else if (ip->protocol == IPPROTO_UDP) |
|
5496 opts[offset] |= info->checksum.udp; |
|
5497 else |
|
5498 WARN_ON_ONCE(1); |
|
5499 } |
|
5500 } |
|
5501 |
|
5502 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
5503 struct net_device *dev) |
|
5504 { |
|
5505 struct rtl8169_private *tp = netdev_priv(dev); |
|
5506 unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
|
5507 struct TxDesc *txd = tp->TxDescArray + entry; |
|
5508 void __iomem *ioaddr = tp->mmio_addr; |
|
5509 struct device *d = &tp->pci_dev->dev; |
|
5510 dma_addr_t mapping; |
|
5511 u32 status, len; |
|
5512 u32 opts[2]; |
|
5513 int frags; |
|
5514 |
|
5515 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
5516 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
|
5517 goto err_stop_0; |
|
5518 } |
|
5519 |
|
5520 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
5521 goto err_stop_0; |
|
5522 |
|
5523 len = skb_headlen(skb); |
|
5524 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
|
5525 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5526 if (net_ratelimit()) |
|
5527 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); |
|
5528 goto err_dma_0; |
|
5529 } |
|
5530 |
|
5531 tp->tx_skb[entry].len = len; |
|
5532 txd->addr = cpu_to_le64(mapping); |
|
5533 |
|
5534 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
5535 opts[0] = DescOwn; |
|
5536 |
|
5537 rtl8169_tso_csum(tp, skb, opts); |
|
5538 |
|
5539 frags = rtl8169_xmit_frags(tp, skb, opts); |
|
5540 if (frags < 0) |
|
5541 goto err_dma_1; |
|
5542 else if (frags) |
|
5543 opts[0] |= FirstFrag; |
|
5544 else { |
|
5545 opts[0] |= FirstFrag | LastFrag; |
|
5546 tp->tx_skb[entry].skb = skb; |
|
5547 } |
|
5548 |
|
5549 txd->opts2 = cpu_to_le32(opts[1]); |
|
5550 |
|
5551 wmb(); |
|
5552 |
|
5553 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5554 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5555 txd->opts1 = cpu_to_le32(status); |
|
5556 |
|
5557 tp->cur_tx += frags + 1; |
|
5558 |
|
5559 wmb(); |
|
5560 |
|
5561 RTL_W8(TxPoll, NPQ); |
|
5562 |
|
5563 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
5564 netif_stop_queue(dev); |
|
5565 smp_rmb(); |
|
5566 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
5567 netif_wake_queue(dev); |
|
5568 } |
|
5569 |
|
5570 return NETDEV_TX_OK; |
|
5571 |
|
5572 err_dma_1: |
|
5573 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
|
5574 err_dma_0: |
|
5575 dev_kfree_skb(skb); |
|
5576 dev->stats.tx_dropped++; |
|
5577 return NETDEV_TX_OK; |
|
5578 |
|
5579 err_stop_0: |
|
5580 netif_stop_queue(dev); |
|
5581 dev->stats.tx_dropped++; |
|
5582 return NETDEV_TX_BUSY; |
|
5583 } |
|
5584 |
|
5585 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
5586 { |
|
5587 struct rtl8169_private *tp = netdev_priv(dev); |
|
5588 struct pci_dev *pdev = tp->pci_dev; |
|
5589 u16 pci_status, pci_cmd; |
|
5590 |
|
5591 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
5592 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
5593 |
|
5594 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
|
5595 pci_cmd, pci_status); |
|
5596 |
|
5597 /* |
|
5598 * The recovery sequence below admits a very elaborated explanation: |
|
5599 * - it seems to work; |
|
5600 * - I did not see what else could be done; |
|
5601 * - it makes iop3xx happy. |
|
5602 * |
|
5603 * Feel free to adjust to your needs. |
|
5604 */ |
|
5605 if (pdev->broken_parity_status) |
|
5606 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
5607 else |
|
5608 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
5609 |
|
5610 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
5611 |
|
5612 pci_write_config_word(pdev, PCI_STATUS, |
|
5613 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
5614 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
5615 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
5616 |
|
5617 /* The infamous DAC f*ckup only happens at boot time */ |
|
5618 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
5619 void __iomem *ioaddr = tp->mmio_addr; |
|
5620 |
|
5621 netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
|
5622 tp->cp_cmd &= ~PCIDAC; |
|
5623 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5624 dev->features &= ~NETIF_F_HIGHDMA; |
|
5625 } |
|
5626 |
|
5627 rtl8169_hw_reset(tp); |
|
5628 |
|
5629 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
5630 } |
|
5631 |
|
5632 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
5633 struct rtl8169_private *tp, |
|
5634 void __iomem *ioaddr) |
|
5635 { |
|
5636 unsigned int dirty_tx, tx_left; |
|
5637 |
|
5638 dirty_tx = tp->dirty_tx; |
|
5639 smp_rmb(); |
|
5640 tx_left = tp->cur_tx - dirty_tx; |
|
5641 |
|
5642 while (tx_left > 0) { |
|
5643 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
5644 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5645 u32 status; |
|
5646 |
|
5647 rmb(); |
|
5648 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
5649 if (status & DescOwn) |
|
5650 break; |
|
5651 |
|
5652 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5653 tp->TxDescArray + entry); |
|
5654 if (status & LastFrag) { |
|
5655 dev->stats.tx_packets++; |
|
5656 dev->stats.tx_bytes += tx_skb->skb->len; |
|
5657 dev_kfree_skb(tx_skb->skb); |
|
5658 tx_skb->skb = NULL; |
|
5659 } |
|
5660 dirty_tx++; |
|
5661 tx_left--; |
|
5662 } |
|
5663 |
|
5664 if (tp->dirty_tx != dirty_tx) { |
|
5665 tp->dirty_tx = dirty_tx; |
|
5666 smp_wmb(); |
|
5667 if (netif_queue_stopped(dev) && |
|
5668 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
5669 netif_wake_queue(dev); |
|
5670 } |
|
5671 /* |
|
5672 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
5673 * too close. Let's kick an extra TxPoll request when a burst |
|
5674 * of start_xmit activity is detected (if it is not detected, |
|
5675 * it is slow enough). -- FR |
|
5676 */ |
|
5677 smp_rmb(); |
|
5678 if (tp->cur_tx != dirty_tx) |
|
5679 RTL_W8(TxPoll, NPQ); |
|
5680 } |
|
5681 } |
|
5682 |
|
5683 static inline int rtl8169_fragmented_frame(u32 status) |
|
5684 { |
|
5685 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
5686 } |
|
5687 |
|
5688 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
|
5689 { |
|
5690 u32 status = opts1 & RxProtoMask; |
|
5691 |
|
5692 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
5693 ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
|
5694 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
5695 else |
|
5696 skb_checksum_none_assert(skb); |
|
5697 } |
|
5698 |
|
5699 static struct sk_buff *rtl8169_try_rx_copy(void *data, |
|
5700 struct rtl8169_private *tp, |
|
5701 int pkt_size, |
|
5702 dma_addr_t addr) |
|
5703 { |
|
5704 struct sk_buff *skb; |
|
5705 struct device *d = &tp->pci_dev->dev; |
|
5706 |
|
5707 data = rtl8169_align(data); |
|
5708 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5709 prefetch(data); |
|
5710 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); |
|
5711 if (skb) |
|
5712 memcpy(skb->data, data, pkt_size); |
|
5713 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5714 |
|
5715 return skb; |
|
5716 } |
|
5717 |
|
5718 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
5719 struct rtl8169_private *tp, |
|
5720 void __iomem *ioaddr, u32 budget) |
|
5721 { |
|
5722 unsigned int cur_rx, rx_left; |
|
5723 unsigned int count; |
|
5724 |
|
5725 cur_rx = tp->cur_rx; |
|
5726 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
5727 rx_left = min(rx_left, budget); |
|
5728 |
|
5729 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
5730 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
5731 struct RxDesc *desc = tp->RxDescArray + entry; |
|
5732 u32 status; |
|
5733 |
|
5734 rmb(); |
|
5735 status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
|
5736 |
|
5737 if (status & DescOwn) |
|
5738 break; |
|
5739 if (unlikely(status & RxRES)) { |
|
5740 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
|
5741 status); |
|
5742 dev->stats.rx_errors++; |
|
5743 if (status & (RxRWT | RxRUNT)) |
|
5744 dev->stats.rx_length_errors++; |
|
5745 if (status & RxCRC) |
|
5746 dev->stats.rx_crc_errors++; |
|
5747 if (status & RxFOVF) { |
|
5748 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
5749 dev->stats.rx_fifo_errors++; |
|
5750 } |
|
5751 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5752 } else { |
|
5753 struct sk_buff *skb; |
|
5754 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
5755 int pkt_size = (status & 0x00003fff) - 4; |
|
5756 |
|
5757 /* |
|
5758 * The driver does not support incoming fragmented |
|
5759 * frames. They are seen as a symptom of over-mtu |
|
5760 * sized frames. |
|
5761 */ |
|
5762 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
5763 dev->stats.rx_dropped++; |
|
5764 dev->stats.rx_length_errors++; |
|
5765 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5766 continue; |
|
5767 } |
|
5768 |
|
5769 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
|
5770 tp, pkt_size, addr); |
|
5771 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5772 if (!skb) { |
|
5773 dev->stats.rx_dropped++; |
|
5774 continue; |
|
5775 } |
|
5776 |
|
5777 rtl8169_rx_csum(skb, status); |
|
5778 skb_put(skb, pkt_size); |
|
5779 skb->protocol = eth_type_trans(skb, dev); |
|
5780 |
|
5781 rtl8169_rx_vlan_tag(desc, skb); |
|
5782 |
|
5783 napi_gro_receive(&tp->napi, skb); |
|
5784 |
|
5785 dev->stats.rx_bytes += pkt_size; |
|
5786 dev->stats.rx_packets++; |
|
5787 } |
|
5788 |
|
5789 /* Work around for AMD plateform. */ |
|
5790 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
5791 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
5792 desc->opts2 = 0; |
|
5793 cur_rx++; |
|
5794 } |
|
5795 } |
|
5796 |
|
5797 count = cur_rx - tp->cur_rx; |
|
5798 tp->cur_rx = cur_rx; |
|
5799 |
|
5800 tp->dirty_rx += count; |
|
5801 |
|
5802 return count; |
|
5803 } |
|
5804 |
|
5805 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
5806 { |
|
5807 struct net_device *dev = dev_instance; |
|
5808 struct rtl8169_private *tp = netdev_priv(dev); |
|
5809 void __iomem *ioaddr = tp->mmio_addr; |
|
5810 int handled = 0; |
|
5811 int status; |
|
5812 |
|
5813 /* loop handling interrupts until we have no new ones or |
|
5814 * we hit a invalid/hotplug case. |
|
5815 */ |
|
5816 status = RTL_R16(IntrStatus); |
|
5817 while (status && status != 0xffff) { |
|
5818 status &= tp->intr_event; |
|
5819 if (!status) |
|
5820 break; |
|
5821 |
|
5822 handled = 1; |
|
5823 |
|
5824 /* Handle all of the error cases first. These will reset |
|
5825 * the chip, so just exit the loop. |
|
5826 */ |
|
5827 if (unlikely(!netif_running(dev))) { |
|
5828 rtl8169_hw_reset(tp); |
|
5829 break; |
|
5830 } |
|
5831 |
|
5832 if (unlikely(status & RxFIFOOver)) { |
|
5833 switch (tp->mac_version) { |
|
5834 /* Work around for rx fifo overflow */ |
|
5835 case RTL_GIGA_MAC_VER_11: |
|
5836 netif_stop_queue(dev); |
|
5837 rtl8169_tx_timeout(dev); |
|
5838 goto done; |
|
5839 default: |
|
5840 break; |
|
5841 } |
|
5842 } |
|
5843 |
|
5844 if (unlikely(status & SYSErr)) { |
|
5845 rtl8169_pcierr_interrupt(dev); |
|
5846 break; |
|
5847 } |
|
5848 |
|
5849 if (status & LinkChg) |
|
5850 __rtl8169_check_link_status(dev, tp, ioaddr, true); |
|
5851 |
|
5852 /* We need to see the lastest version of tp->intr_mask to |
|
5853 * avoid ignoring an MSI interrupt and having to wait for |
|
5854 * another event which may never come. |
|
5855 */ |
|
5856 smp_rmb(); |
|
5857 if (status & tp->intr_mask & tp->napi_event) { |
|
5858 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
5859 tp->intr_mask = ~tp->napi_event; |
|
5860 |
|
5861 if (likely(napi_schedule_prep(&tp->napi))) |
|
5862 __napi_schedule(&tp->napi); |
|
5863 else |
|
5864 netif_info(tp, intr, dev, |
|
5865 "interrupt %04x in poll\n", status); |
|
5866 } |
|
5867 |
|
5868 /* We only get a new MSI interrupt when all active irq |
|
5869 * sources on the chip have been acknowledged. So, ack |
|
5870 * everything we've seen and check if new sources have become |
|
5871 * active to avoid blocking all interrupts from the chip. |
|
5872 */ |
|
5873 RTL_W16(IntrStatus, |
|
5874 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
5875 status = RTL_R16(IntrStatus); |
|
5876 } |
|
5877 done: |
|
5878 return IRQ_RETVAL(handled); |
|
5879 } |
|
5880 |
|
5881 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
5882 { |
|
5883 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
5884 struct net_device *dev = tp->dev; |
|
5885 void __iomem *ioaddr = tp->mmio_addr; |
|
5886 int work_done; |
|
5887 |
|
5888 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
5889 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
5890 |
|
5891 if (work_done < budget) { |
|
5892 napi_complete(napi); |
|
5893 |
|
5894 /* We need for force the visibility of tp->intr_mask |
|
5895 * for other CPUs, as we can loose an MSI interrupt |
|
5896 * and potentially wait for a retransmit timeout if we don't. |
|
5897 * The posted write to IntrMask is safe, as it will |
|
5898 * eventually make it to the chip and we won't loose anything |
|
5899 * until it does. |
|
5900 */ |
|
5901 tp->intr_mask = 0xffff; |
|
5902 wmb(); |
|
5903 RTL_W16(IntrMask, tp->intr_event); |
|
5904 } |
|
5905 |
|
5906 return work_done; |
|
5907 } |
|
5908 |
|
5909 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
5910 { |
|
5911 struct rtl8169_private *tp = netdev_priv(dev); |
|
5912 |
|
5913 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
5914 return; |
|
5915 |
|
5916 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
5917 RTL_W32(RxMissed, 0); |
|
5918 } |
|
5919 |
|
5920 static void rtl8169_down(struct net_device *dev) |
|
5921 { |
|
5922 struct rtl8169_private *tp = netdev_priv(dev); |
|
5923 void __iomem *ioaddr = tp->mmio_addr; |
|
5924 |
|
5925 del_timer_sync(&tp->timer); |
|
5926 |
|
5927 netif_stop_queue(dev); |
|
5928 |
|
5929 napi_disable(&tp->napi); |
|
5930 |
|
5931 spin_lock_irq(&tp->lock); |
|
5932 |
|
5933 rtl8169_hw_reset(tp); |
|
5934 /* |
|
5935 * At this point device interrupts can not be enabled in any function, |
|
5936 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, |
|
5937 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). |
|
5938 */ |
|
5939 rtl8169_rx_missed(dev, ioaddr); |
|
5940 |
|
5941 spin_unlock_irq(&tp->lock); |
|
5942 |
|
5943 synchronize_irq(dev->irq); |
|
5944 |
|
5945 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
5946 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
5947 |
|
5948 rtl8169_tx_clear(tp); |
|
5949 |
|
5950 rtl8169_rx_clear(tp); |
|
5951 |
|
5952 rtl_pll_power_down(tp); |
|
5953 } |
|
5954 |
|
5955 static int rtl8169_close(struct net_device *dev) |
|
5956 { |
|
5957 struct rtl8169_private *tp = netdev_priv(dev); |
|
5958 struct pci_dev *pdev = tp->pci_dev; |
|
5959 |
|
5960 pm_runtime_get_sync(&pdev->dev); |
|
5961 |
|
5962 /* Update counters before going down */ |
|
5963 rtl8169_update_counters(dev); |
|
5964 |
|
5965 rtl8169_down(dev); |
|
5966 |
|
5967 free_irq(dev->irq, dev); |
|
5968 |
|
5969 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
5970 tp->RxPhyAddr); |
|
5971 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
5972 tp->TxPhyAddr); |
|
5973 tp->TxDescArray = NULL; |
|
5974 tp->RxDescArray = NULL; |
|
5975 |
|
5976 pm_runtime_put_sync(&pdev->dev); |
|
5977 |
|
5978 return 0; |
|
5979 } |
|
5980 |
|
5981 static void rtl_set_rx_mode(struct net_device *dev) |
|
5982 { |
|
5983 struct rtl8169_private *tp = netdev_priv(dev); |
|
5984 void __iomem *ioaddr = tp->mmio_addr; |
|
5985 unsigned long flags; |
|
5986 u32 mc_filter[2]; /* Multicast hash filter */ |
|
5987 int rx_mode; |
|
5988 u32 tmp = 0; |
|
5989 |
|
5990 if (dev->flags & IFF_PROMISC) { |
|
5991 /* Unconditionally log net taps. */ |
|
5992 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
|
5993 rx_mode = |
|
5994 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
5995 AcceptAllPhys; |
|
5996 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
5997 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
5998 (dev->flags & IFF_ALLMULTI)) { |
|
5999 /* Too many to filter perfectly -- accept all multicasts. */ |
|
6000 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
6001 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
6002 } else { |
|
6003 struct netdev_hw_addr *ha; |
|
6004 |
|
6005 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
6006 mc_filter[1] = mc_filter[0] = 0; |
|
6007 netdev_for_each_mc_addr(ha, dev) { |
|
6008 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
6009 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
6010 rx_mode |= AcceptMulticast; |
|
6011 } |
|
6012 } |
|
6013 |
|
6014 spin_lock_irqsave(&tp->lock, flags); |
|
6015 |
|
6016 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
|
6017 |
|
6018 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
6019 u32 data = mc_filter[0]; |
|
6020 |
|
6021 mc_filter[0] = swab32(mc_filter[1]); |
|
6022 mc_filter[1] = swab32(data); |
|
6023 } |
|
6024 |
|
6025 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
6026 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
6027 |
|
6028 RTL_W32(RxConfig, tmp); |
|
6029 |
|
6030 spin_unlock_irqrestore(&tp->lock, flags); |
|
6031 } |
|
6032 |
|
6033 /** |
|
6034 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
6035 * @dev: The Ethernet Device to get statistics for |
|
6036 * |
|
6037 * Get TX/RX statistics for rtl8169 |
|
6038 */ |
|
6039 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
6040 { |
|
6041 struct rtl8169_private *tp = netdev_priv(dev); |
|
6042 void __iomem *ioaddr = tp->mmio_addr; |
|
6043 unsigned long flags; |
|
6044 |
|
6045 if (netif_running(dev)) { |
|
6046 spin_lock_irqsave(&tp->lock, flags); |
|
6047 rtl8169_rx_missed(dev, ioaddr); |
|
6048 spin_unlock_irqrestore(&tp->lock, flags); |
|
6049 } |
|
6050 |
|
6051 return &dev->stats; |
|
6052 } |
|
6053 |
|
6054 static void rtl8169_net_suspend(struct net_device *dev) |
|
6055 { |
|
6056 struct rtl8169_private *tp = netdev_priv(dev); |
|
6057 |
|
6058 if (!netif_running(dev)) |
|
6059 return; |
|
6060 |
|
6061 rtl_pll_power_down(tp); |
|
6062 |
|
6063 netif_device_detach(dev); |
|
6064 netif_stop_queue(dev); |
|
6065 } |
|
6066 |
|
6067 #ifdef CONFIG_PM |
|
6068 |
|
6069 static int rtl8169_suspend(struct device *device) |
|
6070 { |
|
6071 struct pci_dev *pdev = to_pci_dev(device); |
|
6072 struct net_device *dev = pci_get_drvdata(pdev); |
|
6073 |
|
6074 rtl8169_net_suspend(dev); |
|
6075 |
|
6076 return 0; |
|
6077 } |
|
6078 |
|
6079 static void __rtl8169_resume(struct net_device *dev) |
|
6080 { |
|
6081 struct rtl8169_private *tp = netdev_priv(dev); |
|
6082 |
|
6083 netif_device_attach(dev); |
|
6084 |
|
6085 rtl_pll_power_up(tp); |
|
6086 |
|
6087 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
6088 } |
|
6089 |
|
6090 static int rtl8169_resume(struct device *device) |
|
6091 { |
|
6092 struct pci_dev *pdev = to_pci_dev(device); |
|
6093 struct net_device *dev = pci_get_drvdata(pdev); |
|
6094 struct rtl8169_private *tp = netdev_priv(dev); |
|
6095 |
|
6096 rtl8169_init_phy(dev, tp); |
|
6097 |
|
6098 if (netif_running(dev)) |
|
6099 __rtl8169_resume(dev); |
|
6100 |
|
6101 return 0; |
|
6102 } |
|
6103 |
|
6104 static int rtl8169_runtime_suspend(struct device *device) |
|
6105 { |
|
6106 struct pci_dev *pdev = to_pci_dev(device); |
|
6107 struct net_device *dev = pci_get_drvdata(pdev); |
|
6108 struct rtl8169_private *tp = netdev_priv(dev); |
|
6109 |
|
6110 if (!tp->TxDescArray) |
|
6111 return 0; |
|
6112 |
|
6113 spin_lock_irq(&tp->lock); |
|
6114 tp->saved_wolopts = __rtl8169_get_wol(tp); |
|
6115 __rtl8169_set_wol(tp, WAKE_ANY); |
|
6116 spin_unlock_irq(&tp->lock); |
|
6117 |
|
6118 rtl8169_net_suspend(dev); |
|
6119 |
|
6120 return 0; |
|
6121 } |
|
6122 |
|
6123 static int rtl8169_runtime_resume(struct device *device) |
|
6124 { |
|
6125 struct pci_dev *pdev = to_pci_dev(device); |
|
6126 struct net_device *dev = pci_get_drvdata(pdev); |
|
6127 struct rtl8169_private *tp = netdev_priv(dev); |
|
6128 |
|
6129 if (!tp->TxDescArray) |
|
6130 return 0; |
|
6131 |
|
6132 spin_lock_irq(&tp->lock); |
|
6133 __rtl8169_set_wol(tp, tp->saved_wolopts); |
|
6134 tp->saved_wolopts = 0; |
|
6135 spin_unlock_irq(&tp->lock); |
|
6136 |
|
6137 rtl8169_init_phy(dev, tp); |
|
6138 |
|
6139 __rtl8169_resume(dev); |
|
6140 |
|
6141 return 0; |
|
6142 } |
|
6143 |
|
6144 static int rtl8169_runtime_idle(struct device *device) |
|
6145 { |
|
6146 struct pci_dev *pdev = to_pci_dev(device); |
|
6147 struct net_device *dev = pci_get_drvdata(pdev); |
|
6148 struct rtl8169_private *tp = netdev_priv(dev); |
|
6149 |
|
6150 return tp->TxDescArray ? -EBUSY : 0; |
|
6151 } |
|
6152 |
|
6153 static const struct dev_pm_ops rtl8169_pm_ops = { |
|
6154 .suspend = rtl8169_suspend, |
|
6155 .resume = rtl8169_resume, |
|
6156 .freeze = rtl8169_suspend, |
|
6157 .thaw = rtl8169_resume, |
|
6158 .poweroff = rtl8169_suspend, |
|
6159 .restore = rtl8169_resume, |
|
6160 .runtime_suspend = rtl8169_runtime_suspend, |
|
6161 .runtime_resume = rtl8169_runtime_resume, |
|
6162 .runtime_idle = rtl8169_runtime_idle, |
|
6163 }; |
|
6164 |
|
6165 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
6166 |
|
6167 #else /* !CONFIG_PM */ |
|
6168 |
|
6169 #define RTL8169_PM_OPS NULL |
|
6170 |
|
6171 #endif /* !CONFIG_PM */ |
|
6172 |
|
6173 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
|
6174 { |
|
6175 void __iomem *ioaddr = tp->mmio_addr; |
|
6176 |
|
6177 /* WoL fails with 8168b when the receiver is disabled. */ |
|
6178 switch (tp->mac_version) { |
|
6179 case RTL_GIGA_MAC_VER_11: |
|
6180 case RTL_GIGA_MAC_VER_12: |
|
6181 case RTL_GIGA_MAC_VER_17: |
|
6182 pci_clear_master(tp->pci_dev); |
|
6183 |
|
6184 RTL_W8(ChipCmd, CmdRxEnb); |
|
6185 /* PCI commit */ |
|
6186 RTL_R8(ChipCmd); |
|
6187 break; |
|
6188 default: |
|
6189 break; |
|
6190 } |
|
6191 } |
|
6192 |
|
6193 static void rtl_shutdown(struct pci_dev *pdev) |
|
6194 { |
|
6195 struct net_device *dev = pci_get_drvdata(pdev); |
|
6196 struct rtl8169_private *tp = netdev_priv(dev); |
|
6197 |
|
6198 rtl8169_net_suspend(dev); |
|
6199 |
|
6200 /* Restore original MAC address */ |
|
6201 rtl_rar_set(tp, dev->perm_addr); |
|
6202 |
|
6203 spin_lock_irq(&tp->lock); |
|
6204 |
|
6205 rtl8169_hw_reset(tp); |
|
6206 |
|
6207 spin_unlock_irq(&tp->lock); |
|
6208 |
|
6209 if (system_state == SYSTEM_POWER_OFF) { |
|
6210 if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
|
6211 rtl_wol_suspend_quirk(tp); |
|
6212 rtl_wol_shutdown_quirk(tp); |
|
6213 } |
|
6214 |
|
6215 pci_wake_from_d3(pdev, true); |
|
6216 pci_set_power_state(pdev, PCI_D3hot); |
|
6217 } |
|
6218 } |
|
6219 |
|
6220 static struct pci_driver rtl8169_pci_driver = { |
|
6221 .name = MODULENAME, |
|
6222 .id_table = rtl8169_pci_tbl, |
|
6223 .probe = rtl8169_init_one, |
|
6224 .remove = __devexit_p(rtl8169_remove_one), |
|
6225 .shutdown = rtl_shutdown, |
|
6226 .driver.pm = RTL8169_PM_OPS, |
|
6227 }; |
|
6228 |
|
6229 static int __init rtl8169_init_module(void) |
|
6230 { |
|
6231 return pci_register_driver(&rtl8169_pci_driver); |
|
6232 } |
|
6233 |
|
6234 static void __exit rtl8169_cleanup_module(void) |
|
6235 { |
|
6236 pci_unregister_driver(&rtl8169_pci_driver); |
|
6237 } |
|
6238 |
|
6239 module_init(rtl8169_init_module); |
|
6240 module_exit(rtl8169_cleanup_module); |