|
1 /******************************************************************************* |
|
2 |
|
3 Intel PRO/1000 Linux driver |
|
4 Copyright(c) 1999 - 2013 Intel Corporation. |
|
5 |
|
6 This program is free software; you can redistribute it and/or modify it |
|
7 under the terms and conditions of the GNU General Public License, |
|
8 version 2, as published by the Free Software Foundation. |
|
9 |
|
10 This program is distributed in the hope it will be useful, but WITHOUT |
|
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
|
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
|
13 more details. |
|
14 |
|
15 You should have received a copy of the GNU General Public License along with |
|
16 this program; if not, write to the Free Software Foundation, Inc., |
|
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
|
18 |
|
19 The full GNU General Public License is included in this distribution in |
|
20 the file called "COPYING". |
|
21 |
|
22 Contact Information: |
|
23 Linux NICS <linux.nics@intel.com> |
|
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
|
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
|
26 |
|
27 *******************************************************************************/ |
|
28 |
|
29 #ifndef _E1000E_PHY_H_ |
|
30 #define _E1000E_PHY_H_ |
|
31 |
|
32 s32 e1000e_check_downshift(struct e1000_hw *hw); |
|
33 s32 e1000_check_polarity_m88(struct e1000_hw *hw); |
|
34 s32 e1000_check_polarity_igp(struct e1000_hw *hw); |
|
35 s32 e1000_check_polarity_ife(struct e1000_hw *hw); |
|
36 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); |
|
37 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); |
|
38 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); |
|
39 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); |
|
40 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); |
|
41 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); |
|
42 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); |
|
43 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); |
|
44 s32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); |
|
45 s32 e1000e_get_phy_id(struct e1000_hw *hw); |
|
46 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); |
|
47 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); |
|
48 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); |
|
49 s32 e1000e_phy_sw_reset(struct e1000_hw *hw); |
|
50 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); |
|
51 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); |
|
52 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); |
|
53 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); |
|
54 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
|
55 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); |
|
56 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); |
|
57 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
|
58 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); |
|
59 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); |
|
60 s32 e1000e_setup_copper_link(struct e1000_hw *hw); |
|
61 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); |
|
62 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); |
|
63 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); |
|
64 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); |
|
65 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); |
|
66 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
|
67 u32 usec_interval, bool *success); |
|
68 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); |
|
69 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); |
|
70 s32 e1000e_determine_phy_address(struct e1000_hw *hw); |
|
71 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); |
|
72 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); |
|
73 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
|
74 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); |
|
75 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); |
|
76 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); |
|
77 void e1000_power_up_phy_copper(struct e1000_hw *hw); |
|
78 void e1000_power_down_phy_copper(struct e1000_hw *hw); |
|
79 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); |
|
80 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); |
|
81 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
|
82 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); |
|
83 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
|
84 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); |
|
85 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); |
|
86 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); |
|
87 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); |
|
88 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); |
|
89 s32 e1000_check_polarity_82577(struct e1000_hw *hw); |
|
90 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); |
|
91 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); |
|
92 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); |
|
93 |
|
94 #define E1000_MAX_PHY_ADDR 8 |
|
95 |
|
96 /* IGP01E1000 Specific Registers */ |
|
97 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ |
|
98 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ |
|
99 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ |
|
100 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ |
|
101 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ |
|
102 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ |
|
103 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ |
|
104 #define IGP_PAGE_SHIFT 5 |
|
105 #define PHY_REG_MASK 0x1F |
|
106 |
|
107 /* BM/HV Specific Registers */ |
|
108 #define BM_PORT_CTRL_PAGE 769 |
|
109 #define BM_WUC_PAGE 800 |
|
110 #define BM_WUC_ADDRESS_OPCODE 0x11 |
|
111 #define BM_WUC_DATA_OPCODE 0x12 |
|
112 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE |
|
113 #define BM_WUC_ENABLE_REG 17 |
|
114 #define BM_WUC_ENABLE_BIT (1 << 2) |
|
115 #define BM_WUC_HOST_WU_BIT (1 << 4) |
|
116 #define BM_WUC_ME_WU_BIT (1 << 5) |
|
117 |
|
118 #define PHY_UPPER_SHIFT 21 |
|
119 #define BM_PHY_REG(page, reg) \ |
|
120 (((reg) & MAX_PHY_REG_ADDRESS) |\ |
|
121 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ |
|
122 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) |
|
123 #define BM_PHY_REG_PAGE(offset) \ |
|
124 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
|
125 #define BM_PHY_REG_NUM(offset) \ |
|
126 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ |
|
127 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ |
|
128 ~MAX_PHY_REG_ADDRESS))) |
|
129 |
|
130 #define HV_INTC_FC_PAGE_START 768 |
|
131 #define I82578_ADDR_REG 29 |
|
132 #define I82577_ADDR_REG 16 |
|
133 #define I82577_CFG_REG 22 |
|
134 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
|
135 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ |
|
136 #define I82577_CTRL_REG 23 |
|
137 |
|
138 /* 82577 specific PHY registers */ |
|
139 #define I82577_PHY_CTRL_2 18 |
|
140 #define I82577_PHY_LBK_CTRL 19 |
|
141 #define I82577_PHY_STATUS_2 26 |
|
142 #define I82577_PHY_DIAG_STATUS 31 |
|
143 |
|
144 /* I82577 PHY Status 2 */ |
|
145 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
|
146 #define I82577_PHY_STATUS2_MDIX 0x0800 |
|
147 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
|
148 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
|
149 |
|
150 /* I82577 PHY Control 2 */ |
|
151 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 |
|
152 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 |
|
153 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
|
154 |
|
155 /* I82577 PHY Diagnostics Status */ |
|
156 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
|
157 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
|
158 |
|
159 /* BM PHY Copper Specific Control 1 */ |
|
160 #define BM_CS_CTRL1 16 |
|
161 |
|
162 /* BM PHY Copper Specific Status */ |
|
163 #define BM_CS_STATUS 17 |
|
164 #define BM_CS_STATUS_LINK_UP 0x0400 |
|
165 #define BM_CS_STATUS_RESOLVED 0x0800 |
|
166 #define BM_CS_STATUS_SPEED_MASK 0xC000 |
|
167 #define BM_CS_STATUS_SPEED_1000 0x8000 |
|
168 |
|
169 /* 82577 Mobile Phy Status Register */ |
|
170 #define HV_M_STATUS 26 |
|
171 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
|
172 #define HV_M_STATUS_SPEED_MASK 0x0300 |
|
173 #define HV_M_STATUS_SPEED_1000 0x0200 |
|
174 #define HV_M_STATUS_LINK_UP 0x0040 |
|
175 |
|
176 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
|
177 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
|
178 |
|
179 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
|
180 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ |
|
181 |
|
182 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
|
183 |
|
184 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ |
|
185 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ |
|
186 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ |
|
187 |
|
188 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
|
189 |
|
190 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
|
191 #define IGP01E1000_PSSR_MDIX 0x0800 |
|
192 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
|
193 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
|
194 |
|
195 #define IGP02E1000_PHY_CHANNEL_NUM 4 |
|
196 #define IGP02E1000_PHY_AGC_A 0x11B1 |
|
197 #define IGP02E1000_PHY_AGC_B 0x12B1 |
|
198 #define IGP02E1000_PHY_AGC_C 0x14B1 |
|
199 #define IGP02E1000_PHY_AGC_D 0x18B1 |
|
200 |
|
201 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ |
|
202 #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
|
203 #define IGP02E1000_AGC_RANGE 15 |
|
204 |
|
205 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
|
206 |
|
207 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 |
|
208 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 |
|
209 #define E1000_KMRNCTRLSTA_REN 0x00200000 |
|
210 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ |
|
211 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ |
|
212 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ |
|
213 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ |
|
214 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ |
|
215 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ |
|
216 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 |
|
217 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ |
|
218 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ |
|
219 |
|
220 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 |
|
221 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ |
|
222 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ |
|
223 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ |
|
224 |
|
225 /* IFE PHY Extended Status Control */ |
|
226 #define IFE_PESC_POLARITY_REVERSED 0x0100 |
|
227 |
|
228 /* IFE PHY Special Control */ |
|
229 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 |
|
230 #define IFE_PSC_FORCE_POLARITY 0x0020 |
|
231 |
|
232 /* IFE PHY Special Control and LED Control */ |
|
233 #define IFE_PSCL_PROBE_MODE 0x0020 |
|
234 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ |
|
235 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ |
|
236 |
|
237 /* IFE PHY MDIX Control */ |
|
238 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ |
|
239 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ |
|
240 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ |
|
241 |
|
242 #endif |