1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2013 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /* 82571EB Gigabit Ethernet Controller

    30  * 82571EB Gigabit Ethernet Controller (Copper)

    31  * 82571EB Gigabit Ethernet Controller (Fiber)

    32  * 82571EB Dual Port Gigabit Mezzanine Adapter

    33  * 82571EB Quad Port Gigabit Mezzanine Adapter

    34  * 82571PT Gigabit PT Quad Port Server ExpressModule

    35  * 82572EI Gigabit Ethernet Controller (Copper)

    36  * 82572EI Gigabit Ethernet Controller (Fiber)

    37  * 82572EI Gigabit Ethernet Controller

    38  * 82573V Gigabit Ethernet Controller (Copper)

    39  * 82573E Gigabit Ethernet Controller (Copper)

    40  * 82573L Gigabit Ethernet Controller

    41  * 82574L Gigabit Network Connection

    42  * 82583V Gigabit Network Connection

    43  */

    44 

    45 #include "e1000-3.12-ethercat.h"

    46 

    47 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);

    48 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);

    49 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);

    50 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

    51 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

    52 				      u16 words, u16 *data);

    53 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);

    54 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);

    55 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);

    56 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);

    57 static s32 e1000_led_on_82574(struct e1000_hw *hw);

    58 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);

    59 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);

    60 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);

    61 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);

    62 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);

    63 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);

    64 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);

    65 

    66 /**

    67  *  e1000_init_phy_params_82571 - Init PHY func ptrs.

    68  *  @hw: pointer to the HW structure

    69  **/

    70 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)

    71 {

    72 	struct e1000_phy_info *phy = &hw->phy;

    73 	s32 ret_val __attribute__ ((unused));

    74 

    75 	if (hw->phy.media_type != e1000_media_type_copper) {

    76 		phy->type = e1000_phy_none;

    77 		return 0;

    78 	}

    79 

    80 	phy->addr = 1;

    81 	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;

    82 	phy->reset_delay_us = 100;

    83 

    84 	phy->ops.power_up = e1000_power_up_phy_copper;

    85 	phy->ops.power_down = e1000_power_down_phy_copper_82571;

    86 

    87 	switch (hw->mac.type) {

    88 	case e1000_82571:

    89 	case e1000_82572:

    90 		phy->type = e1000_phy_igp_2;

    91 		break;

    92 	case e1000_82573:

    93 		phy->type = e1000_phy_m88;

    94 		break;

    95 	case e1000_82574:

    96 	case e1000_82583:

    97 		phy->type = e1000_phy_bm;

    98 		phy->ops.acquire = e1000_get_hw_semaphore_82574;

    99 		phy->ops.release = e1000_put_hw_semaphore_82574;

   100 		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;

   101 		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;

   102 		break;

   103 	default:

   104 		return -E1000_ERR_PHY;

   105 		break;

   106 	}

   107 

   108 	/* This can only be done after all function pointers are setup. */

   109 	ret_val = e1000_get_phy_id_82571(hw);

   110 	if (ret_val) {

   111 		e_dbg("Error getting PHY ID\n");

   112 		return ret_val;

   113 	}

   114 

   115 	/* Verify phy id */

   116 	switch (hw->mac.type) {

   117 	case e1000_82571:

   118 	case e1000_82572:

   119 		if (phy->id != IGP01E1000_I_PHY_ID)

   120 			ret_val = -E1000_ERR_PHY;

   121 		break;

   122 	case e1000_82573:

   123 		if (phy->id != M88E1111_I_PHY_ID)

   124 			ret_val = -E1000_ERR_PHY;

   125 		break;

   126 	case e1000_82574:

   127 	case e1000_82583:

   128 		if (phy->id != BME1000_E_PHY_ID_R2)

   129 			ret_val = -E1000_ERR_PHY;

   130 		break;

   131 	default:

   132 		ret_val = -E1000_ERR_PHY;

   133 		break;

   134 	}

   135 

   136 	if (ret_val)

   137 		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);

   138 

   139 	return ret_val;

   140 }

   141 

   142 /**

   143  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.

   144  *  @hw: pointer to the HW structure

   145  **/

   146 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)

   147 {

   148 	struct e1000_nvm_info *nvm = &hw->nvm;

   149 	u32 eecd = er32(EECD);

   150 	u16 size;

   151 

   152 	nvm->opcode_bits = 8;

   153 	nvm->delay_usec = 1;

   154 	switch (nvm->override) {

   155 	case e1000_nvm_override_spi_large:

   156 		nvm->page_size = 32;

   157 		nvm->address_bits = 16;

   158 		break;

   159 	case e1000_nvm_override_spi_small:

   160 		nvm->page_size = 8;

   161 		nvm->address_bits = 8;

   162 		break;

   163 	default:

   164 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;

   165 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;

   166 		break;

   167 	}

   168 

   169 	switch (hw->mac.type) {

   170 	case e1000_82573:

   171 	case e1000_82574:

   172 	case e1000_82583:

   173 		if (((eecd >> 15) & 0x3) == 0x3) {

   174 			nvm->type = e1000_nvm_flash_hw;

   175 			nvm->word_size = 2048;

   176 			/* Autonomous Flash update bit must be cleared due

   177 			 * to Flash update issue.

   178 			 */

   179 			eecd &= ~E1000_EECD_AUPDEN;

   180 			ew32(EECD, eecd);

   181 			break;

   182 		}

   183 		/* Fall Through */

   184 	default:

   185 		nvm->type = e1000_nvm_eeprom_spi;

   186 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>

   187 			     E1000_EECD_SIZE_EX_SHIFT);

   188 		/* Added to a constant, "size" becomes the left-shift value

   189 		 * for setting word_size.

   190 		 */

   191 		size += NVM_WORD_SIZE_BASE_SHIFT;

   192 

   193 		/* EEPROM access above 16k is unsupported */

   194 		if (size > 14)

   195 			size = 14;

   196 		nvm->word_size = 1 << size;

   197 		break;

   198 	}

   199 

   200 	/* Function Pointers */

   201 	switch (hw->mac.type) {

   202 	case e1000_82574:

   203 	case e1000_82583:

   204 		nvm->ops.acquire = e1000_get_hw_semaphore_82574;

   205 		nvm->ops.release = e1000_put_hw_semaphore_82574;

   206 		break;

   207 	default:

   208 		break;

   209 	}

   210 

   211 	return 0;

   212 }

   213 

   214 /**

   215  *  e1000_init_mac_params_82571 - Init MAC func ptrs.

   216  *  @hw: pointer to the HW structure

   217  **/

   218 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)

   219 {

   220 	struct e1000_mac_info *mac = &hw->mac;

   221 	u32 swsm = 0;

   222 	u32 swsm2 = 0;

   223 	bool force_clear_smbi = false;

   224 

   225 	/* Set media type and media-dependent function pointers */

   226 	switch (hw->adapter->pdev->device) {

   227 	case E1000_DEV_ID_82571EB_FIBER:

   228 	case E1000_DEV_ID_82572EI_FIBER:

   229 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   230 		hw->phy.media_type = e1000_media_type_fiber;

   231 		mac->ops.setup_physical_interface =

   232 		    e1000_setup_fiber_serdes_link_82571;

   233 		mac->ops.check_for_link = e1000e_check_for_fiber_link;

   234 		mac->ops.get_link_up_info =

   235 		    e1000e_get_speed_and_duplex_fiber_serdes;

   236 		break;

   237 	case E1000_DEV_ID_82571EB_SERDES:

   238 	case E1000_DEV_ID_82571EB_SERDES_DUAL:

   239 	case E1000_DEV_ID_82571EB_SERDES_QUAD:

   240 	case E1000_DEV_ID_82572EI_SERDES:

   241 		hw->phy.media_type = e1000_media_type_internal_serdes;

   242 		mac->ops.setup_physical_interface =

   243 		    e1000_setup_fiber_serdes_link_82571;

   244 		mac->ops.check_for_link = e1000_check_for_serdes_link_82571;

   245 		mac->ops.get_link_up_info =

   246 		    e1000e_get_speed_and_duplex_fiber_serdes;

   247 		break;

   248 	default:

   249 		hw->phy.media_type = e1000_media_type_copper;

   250 		mac->ops.setup_physical_interface =

   251 		    e1000_setup_copper_link_82571;

   252 		mac->ops.check_for_link = e1000e_check_for_copper_link;

   253 		mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;

   254 		break;

   255 	}

   256 

   257 	/* Set mta register count */

   258 	mac->mta_reg_count = 128;

   259 	/* Set rar entry count */

   260 	mac->rar_entry_count = E1000_RAR_ENTRIES;

   261 	/* Adaptive IFS supported */

   262 	mac->adaptive_ifs = true;

   263 

   264 	/* MAC-specific function pointers */

   265 	switch (hw->mac.type) {

   266 	case e1000_82573:

   267 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   268 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   269 		mac->ops.led_on = e1000e_led_on_generic;

   270 		mac->ops.blink_led = e1000e_blink_led_generic;

   271 

   272 		/* FWSM register */

   273 		mac->has_fwsm = true;

   274 		/* ARC supported; valid only if manageability features are

   275 		 * enabled.

   276 		 */

   277 		mac->arc_subsystem_valid = !!(er32(FWSM) &

   278 					      E1000_FWSM_MODE_MASK);

   279 		break;

   280 	case e1000_82574:

   281 	case e1000_82583:

   282 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;

   283 		mac->ops.check_mng_mode = e1000_check_mng_mode_82574;

   284 		mac->ops.led_on = e1000_led_on_82574;

   285 		break;

   286 	default:

   287 		mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;

   288 		mac->ops.led_on = e1000e_led_on_generic;

   289 		mac->ops.blink_led = e1000e_blink_led_generic;

   290 

   291 		/* FWSM register */

   292 		mac->has_fwsm = true;

   293 		break;

   294 	}

   295 

   296 	/* Ensure that the inter-port SWSM.SMBI lock bit is clear before

   297 	 * first NVM or PHY access. This should be done for single-port

   298 	 * devices, and for one port only on dual-port devices so that

   299 	 * for those devices we can still use the SMBI lock to synchronize

   300 	 * inter-port accesses to the PHY & NVM.

   301 	 */

   302 	switch (hw->mac.type) {

   303 	case e1000_82571:

   304 	case e1000_82572:

   305 		swsm2 = er32(SWSM2);

   306 

   307 		if (!(swsm2 & E1000_SWSM2_LOCK)) {

   308 			/* Only do this for the first interface on this card */

   309 			ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);

   310 			force_clear_smbi = true;

   311 		} else {

   312 			force_clear_smbi = false;

   313 		}

   314 		break;

   315 	default:

   316 		force_clear_smbi = true;

   317 		break;

   318 	}

   319 

   320 	if (force_clear_smbi) {

   321 		/* Make sure SWSM.SMBI is clear */

   322 		swsm = er32(SWSM);

   323 		if (swsm & E1000_SWSM_SMBI) {

   324 			/* This bit should not be set on a first interface, and

   325 			 * indicates that the bootagent or EFI code has

   326 			 * improperly left this bit enabled

   327 			 */

   328 			e_dbg("Please update your 82571 Bootagent\n");

   329 		}

   330 		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);

   331 	}

   332 

   333 	/* Initialize device specific counter of SMBI acquisition timeouts. */

   334 	hw->dev_spec.e82571.smb_counter = 0;

   335 

   336 	return 0;

   337 }

   338 

   339 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)

   340 {

   341 	struct e1000_hw *hw = &adapter->hw;

   342 	static int global_quad_port_a;	/* global port a indication */

   343 	struct pci_dev *pdev = adapter->pdev;

   344 	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;

   345 	s32 rc;

   346 

   347 	rc = e1000_init_mac_params_82571(hw);

   348 	if (rc)

   349 		return rc;

   350 

   351 	rc = e1000_init_nvm_params_82571(hw);

   352 	if (rc)

   353 		return rc;

   354 

   355 	rc = e1000_init_phy_params_82571(hw);

   356 	if (rc)

   357 		return rc;

   358 

   359 	/* tag quad port adapters first, it's used below */

   360 	switch (pdev->device) {

   361 	case E1000_DEV_ID_82571EB_QUAD_COPPER:

   362 	case E1000_DEV_ID_82571EB_QUAD_FIBER:

   363 	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:

   364 	case E1000_DEV_ID_82571PT_QUAD_COPPER:

   365 		adapter->flags |= FLAG_IS_QUAD_PORT;

   366 		/* mark the first port */

   367 		if (global_quad_port_a == 0)

   368 			adapter->flags |= FLAG_IS_QUAD_PORT_A;

   369 		/* Reset for multiple quad port adapters */

   370 		global_quad_port_a++;

   371 		if (global_quad_port_a == 4)

   372 			global_quad_port_a = 0;

   373 		break;

   374 	default:

   375 		break;

   376 	}

   377 

   378 	switch (adapter->hw.mac.type) {

   379 	case e1000_82571:

   380 		/* these dual ports don't have WoL on port B at all */

   381 		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||

   382 		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||

   383 		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&

   384 		    (is_port_b))

   385 			adapter->flags &= ~FLAG_HAS_WOL;

   386 		/* quad ports only support WoL on port A */

   387 		if (adapter->flags & FLAG_IS_QUAD_PORT &&

   388 		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))

   389 			adapter->flags &= ~FLAG_HAS_WOL;

   390 		/* Does not support WoL on any port */

   391 		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)

   392 			adapter->flags &= ~FLAG_HAS_WOL;

   393 		break;

   394 	case e1000_82573:

   395 		if (pdev->device == E1000_DEV_ID_82573L) {

   396 			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;

   397 			adapter->max_hw_frame_size = DEFAULT_JUMBO;

   398 		}

   399 		break;

   400 	default:

   401 		break;

   402 	}

   403 

   404 	return 0;

   405 }

   406 

   407 /**

   408  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision

   409  *  @hw: pointer to the HW structure

   410  *

   411  *  Reads the PHY registers and stores the PHY ID and possibly the PHY

   412  *  revision in the hardware structure.

   413  **/

   414 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)

   415 {

   416 	struct e1000_phy_info *phy = &hw->phy;

   417 	s32 ret_val;

   418 	u16 phy_id = 0;

   419 

   420 	switch (hw->mac.type) {

   421 	case e1000_82571:

   422 	case e1000_82572:

   423 		/* The 82571 firmware may still be configuring the PHY.

   424 		 * In this case, we cannot access the PHY until the

   425 		 * configuration is done.  So we explicitly set the

   426 		 * PHY ID.

   427 		 */

   428 		phy->id = IGP01E1000_I_PHY_ID;

   429 		break;

   430 	case e1000_82573:

   431 		return e1000e_get_phy_id(hw);

   432 		break;

   433 	case e1000_82574:

   434 	case e1000_82583:

   435 		ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);

   436 		if (ret_val)

   437 			return ret_val;

   438 

   439 		phy->id = (u32)(phy_id << 16);

   440 		usleep_range(20, 40);

   441 		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);

   442 		if (ret_val)

   443 			return ret_val;

   444 

   445 		phy->id |= (u32)(phy_id);

   446 		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);

   447 		break;

   448 	default:

   449 		return -E1000_ERR_PHY;

   450 		break;

   451 	}

   452 

   453 	return 0;

   454 }

   455 

   456 /**

   457  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore

   458  *  @hw: pointer to the HW structure

   459  *

   460  *  Acquire the HW semaphore to access the PHY or NVM

   461  **/

   462 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)

   463 {

   464 	u32 swsm;

   465 	s32 sw_timeout = hw->nvm.word_size + 1;

   466 	s32 fw_timeout = hw->nvm.word_size + 1;

   467 	s32 i = 0;

   468 

   469 	/* If we have timedout 3 times on trying to acquire

   470 	 * the inter-port SMBI semaphore, there is old code

   471 	 * operating on the other port, and it is not

   472 	 * releasing SMBI. Modify the number of times that

   473 	 * we try for the semaphore to interwork with this

   474 	 * older code.

   475 	 */

   476 	if (hw->dev_spec.e82571.smb_counter > 2)

   477 		sw_timeout = 1;

   478 

   479 	/* Get the SW semaphore */

   480 	while (i < sw_timeout) {

   481 		swsm = er32(SWSM);

   482 		if (!(swsm & E1000_SWSM_SMBI))

   483 			break;

   484 

   485 		usleep_range(50, 100);

   486 		i++;

   487 	}

   488 

   489 	if (i == sw_timeout) {

   490 		e_dbg("Driver can't access device - SMBI bit is set.\n");

   491 		hw->dev_spec.e82571.smb_counter++;

   492 	}

   493 	/* Get the FW semaphore. */

   494 	for (i = 0; i < fw_timeout; i++) {

   495 		swsm = er32(SWSM);

   496 		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

   497 

   498 		/* Semaphore acquired if bit latched */

   499 		if (er32(SWSM) & E1000_SWSM_SWESMBI)

   500 			break;

   501 

   502 		usleep_range(50, 100);

   503 	}

   504 

   505 	if (i == fw_timeout) {

   506 		/* Release semaphores */

   507 		e1000_put_hw_semaphore_82571(hw);

   508 		e_dbg("Driver can't access the NVM\n");

   509 		return -E1000_ERR_NVM;

   510 	}

   511 

   512 	return 0;

   513 }

   514 

   515 /**

   516  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore

   517  *  @hw: pointer to the HW structure

   518  *

   519  *  Release hardware semaphore used to access the PHY or NVM

   520  **/

   521 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)

   522 {

   523 	u32 swsm;

   524 

   525 	swsm = er32(SWSM);

   526 	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

   527 	ew32(SWSM, swsm);

   528 }

   529 

   530 /**

   531  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore

   532  *  @hw: pointer to the HW structure

   533  *

   534  *  Acquire the HW semaphore during reset.

   535  *

   536  **/

   537 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)

   538 {

   539 	u32 extcnf_ctrl;

   540 	s32 i = 0;

   541 

   542 	extcnf_ctrl = er32(EXTCNF_CTRL);

   543 	do {

   544 		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   545 		ew32(EXTCNF_CTRL, extcnf_ctrl);

   546 		extcnf_ctrl = er32(EXTCNF_CTRL);

   547 

   548 		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

   549 			break;

   550 

   551 		usleep_range(2000, 4000);

   552 		i++;

   553 	} while (i < MDIO_OWNERSHIP_TIMEOUT);

   554 

   555 	if (i == MDIO_OWNERSHIP_TIMEOUT) {

   556 		/* Release semaphores */

   557 		e1000_put_hw_semaphore_82573(hw);

   558 		e_dbg("Driver can't access the PHY\n");

   559 		return -E1000_ERR_PHY;

   560 	}

   561 

   562 	return 0;

   563 }

   564 

   565 /**

   566  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore

   567  *  @hw: pointer to the HW structure

   568  *

   569  *  Release hardware semaphore used during reset.

   570  *

   571  **/

   572 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)

   573 {

   574 	u32 extcnf_ctrl;

   575 

   576 	extcnf_ctrl = er32(EXTCNF_CTRL);

   577 	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

   578 	ew32(EXTCNF_CTRL, extcnf_ctrl);

   579 }

   580 

   581 static DEFINE_MUTEX(swflag_mutex);

   582 

   583 /**

   584  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore

   585  *  @hw: pointer to the HW structure

   586  *

   587  *  Acquire the HW semaphore to access the PHY or NVM.

   588  *

   589  **/

   590 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)

   591 {

   592 	s32 ret_val;

   593 

   594 	mutex_lock(&swflag_mutex);

   595 	ret_val = e1000_get_hw_semaphore_82573(hw);

   596 	if (ret_val)

   597 		mutex_unlock(&swflag_mutex);

   598 	return ret_val;

   599 }

   600 

   601 /**

   602  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore

   603  *  @hw: pointer to the HW structure

   604  *

   605  *  Release hardware semaphore used to access the PHY or NVM

   606  *

   607  **/

   608 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)

   609 {

   610 	e1000_put_hw_semaphore_82573(hw);

   611 	mutex_unlock(&swflag_mutex);

   612 }

   613 

   614 /**

   615  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state

   616  *  @hw: pointer to the HW structure

   617  *  @active: true to enable LPLU, false to disable

   618  *

   619  *  Sets the LPLU D0 state according to the active flag.

   620  *  LPLU will not be activated unless the

   621  *  device autonegotiation advertisement meets standards of

   622  *  either 10 or 10/100 or 10/100/1000 at all duplexes.

   623  *  This is a function pointer entry point only called by

   624  *  PHY setup routines.

   625  **/

   626 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)

   627 {

   628 	u32 data = er32(POEMB);

   629 

   630 	if (active)

   631 		data |= E1000_PHY_CTRL_D0A_LPLU;

   632 	else

   633 		data &= ~E1000_PHY_CTRL_D0A_LPLU;

   634 

   635 	ew32(POEMB, data);

   636 	return 0;

   637 }

   638 

   639 /**

   640  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3

   641  *  @hw: pointer to the HW structure

   642  *  @active: boolean used to enable/disable lplu

   643  *

   644  *  The low power link up (lplu) state is set to the power management level D3

   645  *  when active is true, else clear lplu for D3. LPLU

   646  *  is used during Dx states where the power conservation is most important.

   647  *  During driver activity, SmartSpeed should be enabled so performance is

   648  *  maintained.

   649  **/

   650 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)

   651 {

   652 	u32 data = er32(POEMB);

   653 

   654 	if (!active) {

   655 		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;

   656 	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||

   657 		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||

   658 		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {

   659 		data |= E1000_PHY_CTRL_NOND0A_LPLU;

   660 	}

   661 

   662 	ew32(POEMB, data);

   663 	return 0;

   664 }

   665 

   666 /**

   667  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM

   668  *  @hw: pointer to the HW structure

   669  *

   670  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.

   671  *  Then for non-82573 hardware, set the EEPROM access request bit and wait

   672  *  for EEPROM access grant bit.  If the access grant bit is not set, release

   673  *  hardware semaphore.

   674  **/

   675 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)

   676 {

   677 	s32 ret_val;

   678 

   679 	ret_val = e1000_get_hw_semaphore_82571(hw);

   680 	if (ret_val)

   681 		return ret_val;

   682 

   683 	switch (hw->mac.type) {

   684 	case e1000_82573:

   685 		break;

   686 	default:

   687 		ret_val = e1000e_acquire_nvm(hw);

   688 		break;

   689 	}

   690 

   691 	if (ret_val)

   692 		e1000_put_hw_semaphore_82571(hw);

   693 

   694 	return ret_val;

   695 }

   696 

   697 /**

   698  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM

   699  *  @hw: pointer to the HW structure

   700  *

   701  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.

   702  **/

   703 static void e1000_release_nvm_82571(struct e1000_hw *hw)

   704 {

   705 	e1000e_release_nvm(hw);

   706 	e1000_put_hw_semaphore_82571(hw);

   707 }

   708 

   709 /**

   710  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface

   711  *  @hw: pointer to the HW structure

   712  *  @offset: offset within the EEPROM to be written to

   713  *  @words: number of words to write

   714  *  @data: 16 bit word(s) to be written to the EEPROM

   715  *

   716  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.

   717  *

   718  *  If e1000e_update_nvm_checksum is not called after this function, the

   719  *  EEPROM will most likely contain an invalid checksum.

   720  **/

   721 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,

   722 				 u16 *data)

   723 {

   724 	s32 ret_val;

   725 

   726 	switch (hw->mac.type) {

   727 	case e1000_82573:

   728 	case e1000_82574:

   729 	case e1000_82583:

   730 		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);

   731 		break;

   732 	case e1000_82571:

   733 	case e1000_82572:

   734 		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);

   735 		break;

   736 	default:

   737 		ret_val = -E1000_ERR_NVM;

   738 		break;

   739 	}

   740 

   741 	return ret_val;

   742 }

   743 

   744 /**

   745  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum

   746  *  @hw: pointer to the HW structure

   747  *

   748  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM

   749  *  up to the checksum.  Then calculates the EEPROM checksum and writes the

   750  *  value to the EEPROM.

   751  **/

   752 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)

   753 {

   754 	u32 eecd;

   755 	s32 ret_val;

   756 	u16 i;

   757 

   758 	ret_val = e1000e_update_nvm_checksum_generic(hw);

   759 	if (ret_val)

   760 		return ret_val;

   761 

   762 	/* If our nvm is an EEPROM, then we're done

   763 	 * otherwise, commit the checksum to the flash NVM.

   764 	 */

   765 	if (hw->nvm.type != e1000_nvm_flash_hw)

   766 		return 0;

   767 

   768 	/* Check for pending operations. */

   769 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   770 		usleep_range(1000, 2000);

   771 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   772 			break;

   773 	}

   774 

   775 	if (i == E1000_FLASH_UPDATES)

   776 		return -E1000_ERR_NVM;

   777 

   778 	/* Reset the firmware if using STM opcode. */

   779 	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {

   780 		/* The enabling of and the actual reset must be done

   781 		 * in two write cycles.

   782 		 */

   783 		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);

   784 		e1e_flush();

   785 		ew32(HICR, E1000_HICR_FW_RESET);

   786 	}

   787 

   788 	/* Commit the write to flash */

   789 	eecd = er32(EECD) | E1000_EECD_FLUPD;

   790 	ew32(EECD, eecd);

   791 

   792 	for (i = 0; i < E1000_FLASH_UPDATES; i++) {

   793 		usleep_range(1000, 2000);

   794 		if (!(er32(EECD) & E1000_EECD_FLUPD))

   795 			break;

   796 	}

   797 

   798 	if (i == E1000_FLASH_UPDATES)

   799 		return -E1000_ERR_NVM;

   800 

   801 	return 0;

   802 }

   803 

   804 /**

   805  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum

   806  *  @hw: pointer to the HW structure

   807  *

   808  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM

   809  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.

   810  **/

   811 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)

   812 {

   813 	if (hw->nvm.type == e1000_nvm_flash_hw)

   814 		e1000_fix_nvm_checksum_82571(hw);

   815 

   816 	return e1000e_validate_nvm_checksum_generic(hw);

   817 }

   818 

   819 /**

   820  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon

   821  *  @hw: pointer to the HW structure

   822  *  @offset: offset within the EEPROM to be written to

   823  *  @words: number of words to write

   824  *  @data: 16 bit word(s) to be written to the EEPROM

   825  *

   826  *  After checking for invalid values, poll the EEPROM to ensure the previous

   827  *  command has completed before trying to write the next word.  After write

   828  *  poll for completion.

   829  *

   830  *  If e1000e_update_nvm_checksum is not called after this function, the

   831  *  EEPROM will most likely contain an invalid checksum.

   832  **/

   833 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,

   834 				      u16 words, u16 *data)

   835 {

   836 	struct e1000_nvm_info *nvm = &hw->nvm;

   837 	u32 i, eewr = 0;

   838 	s32 ret_val = 0;

   839 

   840 	/* A check for invalid values:  offset too large, too many words,

   841 	 * and not enough words.

   842 	 */

   843 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||

   844 	    (words == 0)) {

   845 		e_dbg("nvm parameter(s) out of bounds\n");

   846 		return -E1000_ERR_NVM;

   847 	}

   848 

   849 	for (i = 0; i < words; i++) {

   850 		eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |

   851 			((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |

   852 			E1000_NVM_RW_REG_START);

   853 

   854 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   855 		if (ret_val)

   856 			break;

   857 

   858 		ew32(EEWR, eewr);

   859 

   860 		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);

   861 		if (ret_val)

   862 			break;

   863 	}

   864 

   865 	return ret_val;

   866 }

   867 

   868 /**

   869  *  e1000_get_cfg_done_82571 - Poll for configuration done

   870  *  @hw: pointer to the HW structure

   871  *

   872  *  Reads the management control register for the config done bit to be set.

   873  **/

   874 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)

   875 {

   876 	s32 timeout = PHY_CFG_TIMEOUT;

   877 

   878 	while (timeout) {

   879 		if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)

   880 			break;

   881 		usleep_range(1000, 2000);

   882 		timeout--;

   883 	}

   884 	if (!timeout) {

   885 		e_dbg("MNG configuration cycle has not completed.\n");

   886 		return -E1000_ERR_RESET;

   887 	}

   888 

   889 	return 0;

   890 }

   891 

   892 /**

   893  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state

   894  *  @hw: pointer to the HW structure

   895  *  @active: true to enable LPLU, false to disable

   896  *

   897  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU

   898  *  this function also disables smart speed and vice versa.  LPLU will not be

   899  *  activated unless the device autonegotiation advertisement meets standards

   900  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function

   901  *  pointer entry point only called by PHY setup routines.

   902  **/

   903 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)

   904 {

   905 	struct e1000_phy_info *phy = &hw->phy;

   906 	s32 ret_val;

   907 	u16 data;

   908 

   909 	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);

   910 	if (ret_val)

   911 		return ret_val;

   912 

   913 	if (active) {

   914 		data |= IGP02E1000_PM_D0_LPLU;

   915 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   916 		if (ret_val)

   917 			return ret_val;

   918 

   919 		/* When LPLU is enabled, we should disable SmartSpeed */

   920 		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);

   921 		if (ret_val)

   922 			return ret_val;

   923 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   924 		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);

   925 		if (ret_val)

   926 			return ret_val;

   927 	} else {

   928 		data &= ~IGP02E1000_PM_D0_LPLU;

   929 		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);

   930 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used

   931 		 * during Dx states where the power conservation is most

   932 		 * important.  During driver activity we should enable

   933 		 * SmartSpeed, so performance is maintained.

   934 		 */

   935 		if (phy->smart_speed == e1000_smart_speed_on) {

   936 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   937 					   &data);

   938 			if (ret_val)

   939 				return ret_val;

   940 

   941 			data |= IGP01E1000_PSCFR_SMART_SPEED;

   942 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   943 					   data);

   944 			if (ret_val)

   945 				return ret_val;

   946 		} else if (phy->smart_speed == e1000_smart_speed_off) {

   947 			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   948 					   &data);

   949 			if (ret_val)

   950 				return ret_val;

   951 

   952 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;

   953 			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,

   954 					   data);

   955 			if (ret_val)

   956 				return ret_val;

   957 		}

   958 	}

   959 

   960 	return 0;

   961 }

   962 

   963 /**

   964  *  e1000_reset_hw_82571 - Reset hardware

   965  *  @hw: pointer to the HW structure

   966  *

   967  *  This resets the hardware into a known state.

   968  **/

   969 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

   970 {

   971 	u32 ctrl, ctrl_ext, eecd, tctl;

   972 	s32 ret_val;

   973 

   974 	/* Prevent the PCI-E bus from sticking if there is no TLP connection

   975 	 * on the last TLP read/write transaction when MAC is reset.

   976 	 */

   977 	ret_val = e1000e_disable_pcie_master(hw);

   978 	if (ret_val)

   979 		e_dbg("PCI-E Master disable polling has failed.\n");

   980 

   981 	e_dbg("Masking off all interrupts\n");

   982 	ew32(IMC, 0xffffffff);

   983 

   984 	ew32(RCTL, 0);

   985 	tctl = er32(TCTL);

   986 	tctl &= ~E1000_TCTL_EN;

   987 	ew32(TCTL, tctl);

   988 	e1e_flush();

   989 

   990 	usleep_range(10000, 20000);

   991 

   992 	/* Must acquire the MDIO ownership before MAC reset.

   993 	 * Ownership defaults to firmware after a reset.

   994 	 */

   995 	switch (hw->mac.type) {

   996 	case e1000_82573:

   997 		ret_val = e1000_get_hw_semaphore_82573(hw);

   998 		break;

   999 	case e1000_82574:

  1000 	case e1000_82583:

  1001 		ret_val = e1000_get_hw_semaphore_82574(hw);

  1002 		break;

  1003 	default:

  1004 		break;

  1005 	}

  1006 

  1007 	ctrl = er32(CTRL);

  1008 

  1009 	e_dbg("Issuing a global reset to MAC\n");

  1010 	ew32(CTRL, ctrl | E1000_CTRL_RST);

  1011 

  1012 	/* Must release MDIO ownership and mutex after MAC reset. */

  1013 	switch (hw->mac.type) {

  1014 	case e1000_82573:

  1015 		/* Release mutex only if the hw semaphore is acquired */

  1016 		if (!ret_val)

  1017 			e1000_put_hw_semaphore_82573(hw);

  1018 		break;

  1019 	case e1000_82574:

  1020 	case e1000_82583:

  1021 		/* Release mutex only if the hw semaphore is acquired */

  1022 		if (!ret_val)

  1023 			e1000_put_hw_semaphore_82574(hw);

  1024 		break;

  1025 	default:

  1026 		break;

  1027 	}

  1028 

  1029 	if (hw->nvm.type == e1000_nvm_flash_hw) {

  1030 		usleep_range(10, 20);

  1031 		ctrl_ext = er32(CTRL_EXT);

  1032 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

  1033 		ew32(CTRL_EXT, ctrl_ext);

  1034 		e1e_flush();

  1035 	}

  1036 

  1037 	ret_val = e1000e_get_auto_rd_done(hw);

  1038 	if (ret_val)

  1039 		/* We don't want to continue accessing MAC registers. */

  1040 		return ret_val;

  1041 

  1042 	/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.

  1043 	 * Need to wait for Phy configuration completion before accessing

  1044 	 * NVM and Phy.

  1045 	 */

  1046 

  1047 	switch (hw->mac.type) {

  1048 	case e1000_82571:

  1049 	case e1000_82572:

  1050 		/* REQ and GNT bits need to be cleared when using AUTO_RD

  1051 		 * to access the EEPROM.

  1052 		 */

  1053 		eecd = er32(EECD);

  1054 		eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);

  1055 		ew32(EECD, eecd);

  1056 		break;

  1057 	case e1000_82573:

  1058 	case e1000_82574:

  1059 	case e1000_82583:

  1060 		msleep(25);

  1061 		break;

  1062 	default:

  1063 		break;

  1064 	}

  1065 

  1066 	/* Clear any pending interrupt events. */

  1067 	ew32(IMC, 0xffffffff);

  1068 	er32(ICR);

  1069 

  1070 	if (hw->mac.type == e1000_82571) {

  1071 		/* Install any alternate MAC address into RAR0 */

  1072 		ret_val = e1000_check_alt_mac_addr_generic(hw);

  1073 		if (ret_val)

  1074 			return ret_val;

  1075 

  1076 		e1000e_set_laa_state_82571(hw, true);

  1077 	}

  1078 

  1079 	/* Reinitialize the 82571 serdes link state machine */

  1080 	if (hw->phy.media_type == e1000_media_type_internal_serdes)

  1081 		hw->mac.serdes_link_state = e1000_serdes_link_down;

  1082 

  1083 	return 0;

  1084 }

  1085 

  1086 /**

  1087  *  e1000_init_hw_82571 - Initialize hardware

  1088  *  @hw: pointer to the HW structure

  1089  *

  1090  *  This inits the hardware readying it for operation.

  1091  **/

  1092 static s32 e1000_init_hw_82571(struct e1000_hw *hw)

  1093 {

  1094 	struct e1000_mac_info *mac = &hw->mac;

  1095 	u32 reg_data;

  1096 	s32 ret_val;

  1097 	u16 i, rar_count = mac->rar_entry_count;

  1098 

  1099 	e1000_initialize_hw_bits_82571(hw);

  1100 

  1101 	/* Initialize identification LED */

  1102 	ret_val = mac->ops.id_led_init(hw);

  1103 	/* An error is not fatal and we should not stop init due to this */

  1104 	if (ret_val)

  1105 		e_dbg("Error initializing identification LED\n");

  1106 

  1107 	/* Disabling VLAN filtering */

  1108 	e_dbg("Initializing the IEEE VLAN\n");

  1109 	mac->ops.clear_vfta(hw);

  1110 

  1111 	/* Setup the receive address.

  1112 	 * If, however, a locally administered address was assigned to the

  1113 	 * 82571, we must reserve a RAR for it to work around an issue where

  1114 	 * resetting one port will reload the MAC on the other port.

  1115 	 */

  1116 	if (e1000e_get_laa_state_82571(hw))

  1117 		rar_count--;

  1118 	e1000e_init_rx_addrs(hw, rar_count);

  1119 

  1120 	/* Zero out the Multicast HASH table */

  1121 	e_dbg("Zeroing the MTA\n");

  1122 	for (i = 0; i < mac->mta_reg_count; i++)

  1123 		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

  1124 

  1125 	/* Setup link and flow control */

  1126 	ret_val = mac->ops.setup_link(hw);

  1127 

  1128 	/* Set the transmit descriptor write-back policy */

  1129 	reg_data = er32(TXDCTL(0));

  1130 	reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |

  1131 		    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);

  1132 	ew32(TXDCTL(0), reg_data);

  1133 

  1134 	/* ...for both queues. */

  1135 	switch (mac->type) {

  1136 	case e1000_82573: