1 /*******************************************************************************

     2 

     3   Intel PRO/1000 Linux driver

     4   Copyright(c) 1999 - 2006 Intel Corporation.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms and conditions of the GNU General Public License,

     8   version 2, as published by the Free Software Foundation.

     9 

    10   This program is distributed in the hope it will be useful, but WITHOUT

    11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    13   more details.

    14 

    15   You should have received a copy of the GNU General Public License along with

    16   this program; if not, write to the Free Software Foundation, Inc.,

    17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    18 

    19   The full GNU General Public License is included in this distribution in

    20   the file called "COPYING".

    21 

    22   Contact Information:

    23   Linux NICS <linux.nics@intel.com>

    24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27  */

    28 

    29 /* e1000_hw.c

    30  * Shared functions for accessing and configuring the MAC

    31  */

    32 

    33 #include "e1000.h"

    34 

    35 static s32 e1000_check_downshift(struct e1000_hw *hw);

    36 static s32 e1000_check_polarity(struct e1000_hw *hw,

    37 				e1000_rev_polarity *polarity);

    38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);

    39 static void e1000_clear_vfta(struct e1000_hw *hw);

    40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,

    41 					      bool link_up);

    42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);

    43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);

    44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);

    45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,

    46 				  u16 *max_length);

    47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);

    48 static s32 e1000_id_led_init(struct e1000_hw *hw);

    49 static void e1000_init_rx_addrs(struct e1000_hw *hw);

    50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,

    51 				  struct e1000_phy_info *phy_info);

    52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,

    53 				  struct e1000_phy_info *phy_info);

    54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);

    55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);

    56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);

    57 static s32 e1000_set_phy_type(struct e1000_hw *hw);

    58 static void e1000_phy_init_script(struct e1000_hw *hw);

    59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);

    60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);

    61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);

    62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);

    63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);

    64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);

    66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);

    67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);

    68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);

    69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,

    70 				  u16 words, u16 *data);

    71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,

    72 					u16 words, u16 *data);

    73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);

    74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);

    75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);

    76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);

    77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    78 				  u16 phy_data);

    79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,

    80 				 u16 *phy_data);

    81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);

    82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);

    83 static void e1000_release_eeprom(struct e1000_hw *hw);

    84 static void e1000_standby_eeprom(struct e1000_hw *hw);

    85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);

    86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);

    87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);

    88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    89 				u16 *data);

    90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,

    91 				 u16 *data);

    92 

    93 /* IGP cable length table */

    94 static const

    95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {

    96 	5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,

    97 	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,

    98 	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,

    99 	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,

   100 	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,

   101 	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,

   102 	    100,

   103 	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,

   104 	    110, 110,

   105 	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,

   106 	    120, 120

   107 };

   108 

   109 static DEFINE_SPINLOCK(e1000_eeprom_lock);

   110 static DEFINE_SPINLOCK(e1000_phy_lock);

   111 

   112 /**

   113  * e1000_set_phy_type - Set the phy type member in the hw struct.

   114  * @hw: Struct containing variables accessed by shared code

   115  */

   116 static s32 e1000_set_phy_type(struct e1000_hw *hw)

   117 {

   118 	e_dbg("e1000_set_phy_type");

   119 

   120 	if (hw->mac_type == e1000_undefined)

   121 		return -E1000_ERR_PHY_TYPE;

   122 

   123 	switch (hw->phy_id) {

   124 	case M88E1000_E_PHY_ID:

   125 	case M88E1000_I_PHY_ID:

   126 	case M88E1011_I_PHY_ID:

   127 	case M88E1111_I_PHY_ID:

   128 	case M88E1118_E_PHY_ID:

   129 		hw->phy_type = e1000_phy_m88;

   130 		break;

   131 	case IGP01E1000_I_PHY_ID:

   132 		if (hw->mac_type == e1000_82541 ||

   133 		    hw->mac_type == e1000_82541_rev_2 ||

   134 		    hw->mac_type == e1000_82547 ||

   135 		    hw->mac_type == e1000_82547_rev_2)

   136 			hw->phy_type = e1000_phy_igp;

   137 		break;

   138 	case RTL8211B_PHY_ID:

   139 		hw->phy_type = e1000_phy_8211;

   140 		break;

   141 	case RTL8201N_PHY_ID:

   142 		hw->phy_type = e1000_phy_8201;

   143 		break;

   144 	default:

   145 		/* Should never have loaded on this device */

   146 		hw->phy_type = e1000_phy_undefined;

   147 		return -E1000_ERR_PHY_TYPE;

   148 	}

   149 

   150 	return E1000_SUCCESS;

   151 }

   152 

   153 /**

   154  * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY

   155  * @hw: Struct containing variables accessed by shared code

   156  */

   157 static void e1000_phy_init_script(struct e1000_hw *hw)

   158 {

   159 	u32 ret_val;

   160 	u16 phy_saved_data;

   161 

   162 	e_dbg("e1000_phy_init_script");

   163 

   164 	if (hw->phy_init_script) {

   165 		msleep(20);

   166 

   167 		/* Save off the current value of register 0x2F5B to be restored

   168 		 * at the end of this routine.

   169 		 */

   170 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);

   171 

   172 		/* Disabled the PHY transmitter */

   173 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);

   174 		msleep(20);

   175 

   176 		e1000_write_phy_reg(hw, 0x0000, 0x0140);

   177 		msleep(5);

   178 

   179 		switch (hw->mac_type) {

   180 		case e1000_82541:

   181 		case e1000_82547:

   182 			e1000_write_phy_reg(hw, 0x1F95, 0x0001);

   183 			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);

   184 			e1000_write_phy_reg(hw, 0x1F79, 0x0018);

   185 			e1000_write_phy_reg(hw, 0x1F30, 0x1600);

   186 			e1000_write_phy_reg(hw, 0x1F31, 0x0014);

   187 			e1000_write_phy_reg(hw, 0x1F32, 0x161C);

   188 			e1000_write_phy_reg(hw, 0x1F94, 0x0003);

   189 			e1000_write_phy_reg(hw, 0x1F96, 0x003F);

   190 			e1000_write_phy_reg(hw, 0x2010, 0x0008);

   191 			break;

   192 

   193 		case e1000_82541_rev_2:

   194 		case e1000_82547_rev_2:

   195 			e1000_write_phy_reg(hw, 0x1F73, 0x0099);

   196 			break;

   197 		default:

   198 			break;

   199 		}

   200 

   201 		e1000_write_phy_reg(hw, 0x0000, 0x3300);

   202 		msleep(20);

   203 

   204 		/* Now enable the transmitter */

   205 		e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);

   206 

   207 		if (hw->mac_type == e1000_82547) {

   208 			u16 fused, fine, coarse;

   209 

   210 			/* Move to analog registers page */

   211 			e1000_read_phy_reg(hw,

   212 					   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,

   213 					   &fused);

   214 

   215 			if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {

   216 				e1000_read_phy_reg(hw,

   217 						   IGP01E1000_ANALOG_FUSE_STATUS,

   218 						   &fused);

   219 

   220 				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;

   221 				coarse =

   222 				    fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;

   223 

   224 				if (coarse >

   225 				    IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {

   226 					coarse -=

   227 					    IGP01E1000_ANALOG_FUSE_COARSE_10;

   228 					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;

   229 				} else if (coarse ==

   230 					   IGP01E1000_ANALOG_FUSE_COARSE_THRESH)

   231 					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;

   232 

   233 				fused =

   234 				    (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |

   235 				    (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |

   236 				    (coarse &

   237 				     IGP01E1000_ANALOG_FUSE_COARSE_MASK);

   238 

   239 				e1000_write_phy_reg(hw,

   240 						    IGP01E1000_ANALOG_FUSE_CONTROL,

   241 						    fused);

   242 				e1000_write_phy_reg(hw,

   243 						    IGP01E1000_ANALOG_FUSE_BYPASS,

   244 						    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);

   245 			}

   246 		}

   247 	}

   248 }

   249 

   250 /**

   251  * e1000_set_mac_type - Set the mac type member in the hw struct.

   252  * @hw: Struct containing variables accessed by shared code

   253  */

   254 s32 e1000_set_mac_type(struct e1000_hw *hw)

   255 {

   256 	e_dbg("e1000_set_mac_type");

   257 

   258 	switch (hw->device_id) {

   259 	case E1000_DEV_ID_82542:

   260 		switch (hw->revision_id) {

   261 		case E1000_82542_2_0_REV_ID:

   262 			hw->mac_type = e1000_82542_rev2_0;

   263 			break;

   264 		case E1000_82542_2_1_REV_ID:

   265 			hw->mac_type = e1000_82542_rev2_1;

   266 			break;

   267 		default:

   268 			/* Invalid 82542 revision ID */

   269 			return -E1000_ERR_MAC_TYPE;

   270 		}

   271 		break;

   272 	case E1000_DEV_ID_82543GC_FIBER:

   273 	case E1000_DEV_ID_82543GC_COPPER:

   274 		hw->mac_type = e1000_82543;

   275 		break;

   276 	case E1000_DEV_ID_82544EI_COPPER:

   277 	case E1000_DEV_ID_82544EI_FIBER:

   278 	case E1000_DEV_ID_82544GC_COPPER:

   279 	case E1000_DEV_ID_82544GC_LOM:

   280 		hw->mac_type = e1000_82544;

   281 		break;

   282 	case E1000_DEV_ID_82540EM:

   283 	case E1000_DEV_ID_82540EM_LOM:

   284 	case E1000_DEV_ID_82540EP:

   285 	case E1000_DEV_ID_82540EP_LOM:

   286 	case E1000_DEV_ID_82540EP_LP:

   287 		hw->mac_type = e1000_82540;

   288 		break;

   289 	case E1000_DEV_ID_82545EM_COPPER:

   290 	case E1000_DEV_ID_82545EM_FIBER:

   291 		hw->mac_type = e1000_82545;

   292 		break;

   293 	case E1000_DEV_ID_82545GM_COPPER:

   294 	case E1000_DEV_ID_82545GM_FIBER:

   295 	case E1000_DEV_ID_82545GM_SERDES:

   296 		hw->mac_type = e1000_82545_rev_3;

   297 		break;

   298 	case E1000_DEV_ID_82546EB_COPPER:

   299 	case E1000_DEV_ID_82546EB_FIBER:

   300 	case E1000_DEV_ID_82546EB_QUAD_COPPER:

   301 		hw->mac_type = e1000_82546;

   302 		break;

   303 	case E1000_DEV_ID_82546GB_COPPER:

   304 	case E1000_DEV_ID_82546GB_FIBER:

   305 	case E1000_DEV_ID_82546GB_SERDES:

   306 	case E1000_DEV_ID_82546GB_PCIE:

   307 	case E1000_DEV_ID_82546GB_QUAD_COPPER:

   308 	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:

   309 		hw->mac_type = e1000_82546_rev_3;

   310 		break;

   311 	case E1000_DEV_ID_82541EI:

   312 	case E1000_DEV_ID_82541EI_MOBILE:

   313 	case E1000_DEV_ID_82541ER_LOM:

   314 		hw->mac_type = e1000_82541;

   315 		break;

   316 	case E1000_DEV_ID_82541ER:

   317 	case E1000_DEV_ID_82541GI:

   318 	case E1000_DEV_ID_82541GI_LF:

   319 	case E1000_DEV_ID_82541GI_MOBILE:

   320 		hw->mac_type = e1000_82541_rev_2;

   321 		break;

   322 	case E1000_DEV_ID_82547EI:

   323 	case E1000_DEV_ID_82547EI_MOBILE:

   324 		hw->mac_type = e1000_82547;

   325 		break;

   326 	case E1000_DEV_ID_82547GI:

   327 		hw->mac_type = e1000_82547_rev_2;

   328 		break;

   329 	case E1000_DEV_ID_INTEL_CE4100_GBE:

   330 		hw->mac_type = e1000_ce4100;

   331 		break;

   332 	default:

   333 		/* Should never have loaded on this device */

   334 		return -E1000_ERR_MAC_TYPE;

   335 	}

   336 

   337 	switch (hw->mac_type) {

   338 	case e1000_82541:

   339 	case e1000_82547:

   340 	case e1000_82541_rev_2:

   341 	case e1000_82547_rev_2:

   342 		hw->asf_firmware_present = true;

   343 		break;

   344 	default:

   345 		break;

   346 	}

   347 

   348 	/* The 82543 chip does not count tx_carrier_errors properly in

   349 	 * FD mode

   350 	 */

   351 	if (hw->mac_type == e1000_82543)

   352 		hw->bad_tx_carr_stats_fd = true;

   353 

   354 	if (hw->mac_type > e1000_82544)

   355 		hw->has_smbus = true;

   356 

   357 	return E1000_SUCCESS;

   358 }

   359 

   360 /**

   361  * e1000_set_media_type - Set media type and TBI compatibility.

   362  * @hw: Struct containing variables accessed by shared code

   363  */

   364 void e1000_set_media_type(struct e1000_hw *hw)

   365 {

   366 	u32 status;

   367 

   368 	e_dbg("e1000_set_media_type");

   369 

   370 	if (hw->mac_type != e1000_82543) {

   371 		/* tbi_compatibility is only valid on 82543 */

   372 		hw->tbi_compatibility_en = false;

   373 	}

   374 

   375 	switch (hw->device_id) {

   376 	case E1000_DEV_ID_82545GM_SERDES:

   377 	case E1000_DEV_ID_82546GB_SERDES:

   378 		hw->media_type = e1000_media_type_internal_serdes;

   379 		break;

   380 	default:

   381 		switch (hw->mac_type) {

   382 		case e1000_82542_rev2_0:

   383 		case e1000_82542_rev2_1:

   384 			hw->media_type = e1000_media_type_fiber;

   385 			break;

   386 		case e1000_ce4100:

   387 			hw->media_type = e1000_media_type_copper;

   388 			break;

   389 		default:

   390 			status = er32(STATUS);

   391 			if (status & E1000_STATUS_TBIMODE) {

   392 				hw->media_type = e1000_media_type_fiber;

   393 				/* tbi_compatibility not valid on fiber */

   394 				hw->tbi_compatibility_en = false;

   395 			} else {

   396 				hw->media_type = e1000_media_type_copper;

   397 			}

   398 			break;

   399 		}

   400 	}

   401 }

   402 

   403 /**

   404  * e1000_reset_hw - reset the hardware completely

   405  * @hw: Struct containing variables accessed by shared code

   406  *

   407  * Reset the transmit and receive units; mask and clear all interrupts.

   408  */

   409 s32 e1000_reset_hw(struct e1000_hw *hw)

   410 {

   411 	u32 ctrl;

   412 	u32 ctrl_ext;

   413 	u32 icr;

   414 	u32 manc;

   415 	u32 led_ctrl;

   416 	s32 ret_val;

   417 

   418 	e_dbg("e1000_reset_hw");

   419 

   420 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */

   421 	if (hw->mac_type == e1000_82542_rev2_0) {

   422 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   423 		e1000_pci_clear_mwi(hw);

   424 	}

   425 

   426 	/* Clear interrupt mask to stop board from generating interrupts */

   427 	e_dbg("Masking off all interrupts\n");

   428 	ew32(IMC, 0xffffffff);

   429 

   430 	/* Disable the Transmit and Receive units.  Then delay to allow

   431 	 * any pending transactions to complete before we hit the MAC with

   432 	 * the global reset.

   433 	 */

   434 	ew32(RCTL, 0);

   435 	ew32(TCTL, E1000_TCTL_PSP);

   436 	E1000_WRITE_FLUSH();

   437 

   438 	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */

   439 	hw->tbi_compatibility_on = false;

   440 

   441 	/* Delay to allow any outstanding PCI transactions to complete before

   442 	 * resetting the device

   443 	 */

   444 	msleep(10);

   445 

   446 	ctrl = er32(CTRL);

   447 

   448 	/* Must reset the PHY before resetting the MAC */

   449 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   450 		ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));

   451 		E1000_WRITE_FLUSH();

   452 		msleep(5);

   453 	}

   454 

   455 	/* Issue a global reset to the MAC.  This will reset the chip's

   456 	 * transmit, receive, DMA, and link units.  It will not effect

   457 	 * the current PCI configuration.  The global reset bit is self-

   458 	 * clearing, and should clear within a microsecond.

   459 	 */

   460 	e_dbg("Issuing a global reset to MAC\n");

   461 

   462 	switch (hw->mac_type) {

   463 	case e1000_82544:

   464 	case e1000_82540:

   465 	case e1000_82545:

   466 	case e1000_82546:

   467 	case e1000_82541:

   468 	case e1000_82541_rev_2:

   469 		/* These controllers can't ack the 64-bit write when issuing the

   470 		 * reset, so use IO-mapping as a workaround to issue the reset

   471 		 */

   472 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));

   473 		break;

   474 	case e1000_82545_rev_3:

   475 	case e1000_82546_rev_3:

   476 		/* Reset is performed on a shadow of the control register */

   477 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));

   478 		break;

   479 	case e1000_ce4100:

   480 	default:

   481 		ew32(CTRL, (ctrl | E1000_CTRL_RST));

   482 		break;

   483 	}

   484 

   485 	/* After MAC reset, force reload of EEPROM to restore power-on settings

   486 	 * to device.  Later controllers reload the EEPROM automatically, so

   487 	 * just wait for reload to complete.

   488 	 */

   489 	switch (hw->mac_type) {

   490 	case e1000_82542_rev2_0:

   491 	case e1000_82542_rev2_1:

   492 	case e1000_82543:

   493 	case e1000_82544:

   494 		/* Wait for reset to complete */

   495 		udelay(10);

   496 		ctrl_ext = er32(CTRL_EXT);

   497 		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

   498 		ew32(CTRL_EXT, ctrl_ext);

   499 		E1000_WRITE_FLUSH();

   500 		/* Wait for EEPROM reload */

   501 		msleep(2);

   502 		break;

   503 	case e1000_82541:

   504 	case e1000_82541_rev_2:

   505 	case e1000_82547:

   506 	case e1000_82547_rev_2:

   507 		/* Wait for EEPROM reload */

   508 		msleep(20);

   509 		break;

   510 	default:

   511 		/* Auto read done will delay 5ms or poll based on mac type */

   512 		ret_val = e1000_get_auto_rd_done(hw);

   513 		if (ret_val)

   514 			return ret_val;

   515 		break;

   516 	}

   517 

   518 	/* Disable HW ARPs on ASF enabled adapters */

   519 	if (hw->mac_type >= e1000_82540) {

   520 		manc = er32(MANC);

   521 		manc &= ~(E1000_MANC_ARP_EN);

   522 		ew32(MANC, manc);

   523 	}

   524 

   525 	if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {

   526 		e1000_phy_init_script(hw);

   527 

   528 		/* Configure activity LED after PHY reset */

   529 		led_ctrl = er32(LEDCTL);

   530 		led_ctrl &= IGP_ACTIVITY_LED_MASK;

   531 		led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

   532 		ew32(LEDCTL, led_ctrl);

   533 	}

   534 

   535 	/* Clear interrupt mask to stop board from generating interrupts */

   536 	e_dbg("Masking off all interrupts\n");

   537 	ew32(IMC, 0xffffffff);

   538 

   539 	/* Clear any pending interrupt events. */

   540 	icr = er32(ICR);

   541 

   542 	/* If MWI was previously enabled, reenable it. */

   543 	if (hw->mac_type == e1000_82542_rev2_0) {

   544 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   545 			e1000_pci_set_mwi(hw);

   546 	}

   547 

   548 	return E1000_SUCCESS;

   549 }

   550 

   551 /**

   552  * e1000_init_hw - Performs basic configuration of the adapter.

   553  * @hw: Struct containing variables accessed by shared code

   554  *

   555  * Assumes that the controller has previously been reset and is in a

   556  * post-reset uninitialized state. Initializes the receive address registers,

   557  * multicast table, and VLAN filter table. Calls routines to setup link

   558  * configuration and flow control settings. Clears all on-chip counters. Leaves

   559  * the transmit and receive units disabled and uninitialized.

   560  */

   561 s32 e1000_init_hw(struct e1000_hw *hw)

   562 {

   563 	u32 ctrl;

   564 	u32 i;

   565 	s32 ret_val;

   566 	u32 mta_size;

   567 	u32 ctrl_ext;

   568 

   569 	e_dbg("e1000_init_hw");

   570 

   571 	/* Initialize Identification LED */

   572 	ret_val = e1000_id_led_init(hw);

   573 	if (ret_val) {

   574 		e_dbg("Error Initializing Identification LED\n");

   575 		return ret_val;

   576 	}

   577 

   578 	/* Set the media type and TBI compatibility */

   579 	e1000_set_media_type(hw);

   580 

   581 	/* Disabling VLAN filtering. */

   582 	e_dbg("Initializing the IEEE VLAN\n");

   583 	if (hw->mac_type < e1000_82545_rev_3)

   584 		ew32(VET, 0);

   585 	e1000_clear_vfta(hw);

   586 

   587 	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */

   588 	if (hw->mac_type == e1000_82542_rev2_0) {

   589 		e_dbg("Disabling MWI on 82542 rev 2.0\n");

   590 		e1000_pci_clear_mwi(hw);

   591 		ew32(RCTL, E1000_RCTL_RST);

   592 		E1000_WRITE_FLUSH();

   593 		msleep(5);

   594 	}

   595 

   596 	/* Setup the receive address. This involves initializing all of the

   597 	 * Receive Address Registers (RARs 0 - 15).

   598 	 */

   599 	e1000_init_rx_addrs(hw);

   600 

   601 	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */

   602 	if (hw->mac_type == e1000_82542_rev2_0) {

   603 		ew32(RCTL, 0);

   604 		E1000_WRITE_FLUSH();

   605 		msleep(1);

   606 		if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)

   607 			e1000_pci_set_mwi(hw);

   608 	}

   609 

   610 	/* Zero out the Multicast HASH table */

   611 	e_dbg("Zeroing the MTA\n");

   612 	mta_size = E1000_MC_TBL_SIZE;

   613 	for (i = 0; i < mta_size; i++) {

   614 		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);

   615 		/* use write flush to prevent Memory Write Block (MWB) from

   616 		 * occurring when accessing our register space

   617 		 */

   618 		E1000_WRITE_FLUSH();

   619 	}

   620 

   621 	/* Set the PCI priority bit correctly in the CTRL register.  This

   622 	 * determines if the adapter gives priority to receives, or if it

   623 	 * gives equal priority to transmits and receives.  Valid only on

   624 	 * 82542 and 82543 silicon.

   625 	 */

   626 	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {

   627 		ctrl = er32(CTRL);

   628 		ew32(CTRL, ctrl | E1000_CTRL_PRIOR);

   629 	}

   630 

   631 	switch (hw->mac_type) {

   632 	case e1000_82545_rev_3:

   633 	case e1000_82546_rev_3:

   634 		break;

   635 	default:

   636 		/* Workaround for PCI-X problem when BIOS sets MMRBC

   637 		 * incorrectly.

   638 		 */

   639 		if (hw->bus_type == e1000_bus_type_pcix

   640 		    && e1000_pcix_get_mmrbc(hw) > 2048)

   641 			e1000_pcix_set_mmrbc(hw, 2048);

   642 		break;

   643 	}

   644 

   645 	/* Call a subroutine to configure the link and setup flow control. */

   646 	ret_val = e1000_setup_link(hw);

   647 

   648 	/* Set the transmit descriptor write-back policy */

   649 	if (hw->mac_type > e1000_82544) {

   650 		ctrl = er32(TXDCTL);

   651 		ctrl =

   652 		    (ctrl & ~E1000_TXDCTL_WTHRESH) |

   653 		    E1000_TXDCTL_FULL_TX_DESC_WB;

   654 		ew32(TXDCTL, ctrl);

   655 	}

   656 

   657 	/* Clear all of the statistics registers (clear on read).  It is

   658 	 * important that we do this after we have tried to establish link

   659 	 * because the symbol error count will increment wildly if there

   660 	 * is no link.

   661 	 */

   662 	e1000_clear_hw_cntrs(hw);

   663 

   664 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||

   665 	    hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {

   666 		ctrl_ext = er32(CTRL_EXT);

   667 		/* Relaxed ordering must be disabled to avoid a parity

   668 		 * error crash in a PCI slot.

   669 		 */

   670 		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;

   671 		ew32(CTRL_EXT, ctrl_ext);

   672 	}

   673 

   674 	return ret_val;

   675 }

   676 

   677 /**

   678  * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.

   679  * @hw: Struct containing variables accessed by shared code.

   680  */

   681 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)

   682 {

   683 	u16 eeprom_data;

   684 	s32 ret_val;

   685 

   686 	e_dbg("e1000_adjust_serdes_amplitude");

   687 

   688 	if (hw->media_type != e1000_media_type_internal_serdes)

   689 		return E1000_SUCCESS;

   690 

   691 	switch (hw->mac_type) {

   692 	case e1000_82545_rev_3:

   693 	case e1000_82546_rev_3:

   694 		break;

   695 	default:

   696 		return E1000_SUCCESS;

   697 	}

   698 

   699 	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,

   700 	                            &eeprom_data);

   701 	if (ret_val) {

   702 		return ret_val;

   703 	}

   704 

   705 	if (eeprom_data != EEPROM_RESERVED_WORD) {

   706 		/* Adjust SERDES output amplitude only. */

   707 		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;

   708 		ret_val =

   709 		    e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);

   710 		if (ret_val)

   711 			return ret_val;

   712 	}

   713 

   714 	return E1000_SUCCESS;

   715 }

   716 

   717 /**

   718  * e1000_setup_link - Configures flow control and link settings.

   719  * @hw: Struct containing variables accessed by shared code

   720  *

   721  * Determines which flow control settings to use. Calls the appropriate media-

   722  * specific link configuration function. Configures the flow control settings.

   723  * Assuming the adapter has a valid link partner, a valid link should be

   724  * established. Assumes the hardware has previously been reset and the

   725  * transmitter and receiver are not enabled.

   726  */

   727 s32 e1000_setup_link(struct e1000_hw *hw)

   728 {

   729 	u32 ctrl_ext;

   730 	s32 ret_val;

   731 	u16 eeprom_data;

   732 

   733 	e_dbg("e1000_setup_link");

   734 

   735 	/* Read and store word 0x0F of the EEPROM. This word contains bits

   736 	 * that determine the hardware's default PAUSE (flow control) mode,

   737 	 * a bit that determines whether the HW defaults to enabling or

   738 	 * disabling auto-negotiation, and the direction of the

   739 	 * SW defined pins. If there is no SW over-ride of the flow

   740 	 * control setting, then the variable hw->fc will

   741 	 * be initialized based on a value in the EEPROM.

   742 	 */

   743 	if (hw->fc == E1000_FC_DEFAULT) {

   744 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   745 					    1, &eeprom_data);

   746 		if (ret_val) {

   747 			e_dbg("EEPROM Read Error\n");

   748 			return -E1000_ERR_EEPROM;

   749 		}

   750 		if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)

   751 			hw->fc = E1000_FC_NONE;

   752 		else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==

   753 			 EEPROM_WORD0F_ASM_DIR)

   754 			hw->fc = E1000_FC_TX_PAUSE;

   755 		else

   756 			hw->fc = E1000_FC_FULL;

   757 	}

   758 

   759 	/* We want to save off the original Flow Control configuration just

   760 	 * in case we get disconnected and then reconnected into a different

   761 	 * hub or switch with different Flow Control capabilities.

   762 	 */

   763 	if (hw->mac_type == e1000_82542_rev2_0)

   764 		hw->fc &= (~E1000_FC_TX_PAUSE);

   765 

   766 	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))

   767 		hw->fc &= (~E1000_FC_RX_PAUSE);

   768 

   769 	hw->original_fc = hw->fc;

   770 

   771 	e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);

   772 

   773 	/* Take the 4 bits from EEPROM word 0x0F that determine the initial

   774 	 * polarity value for the SW controlled pins, and setup the

   775 	 * Extended Device Control reg with that info.

   776 	 * This is needed because one of the SW controlled pins is used for

   777 	 * signal detection.  So this should be done before e1000_setup_pcs_link()

   778 	 * or e1000_phy_setup() is called.

   779 	 */

   780 	if (hw->mac_type == e1000_82543) {

   781 		ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,

   782 					    1, &eeprom_data);

   783 		if (ret_val) {

   784 			e_dbg("EEPROM Read Error\n");

   785 			return -E1000_ERR_EEPROM;

   786 		}

   787 		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<

   788 			    SWDPIO__EXT_SHIFT);

   789 		ew32(CTRL_EXT, ctrl_ext);

   790 	}

   791 

   792 	/* Call the necessary subroutine to configure the link. */

   793 	ret_val = (hw->media_type == e1000_media_type_copper) ?

   794 	    e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);

   795 

   796 	/* Initialize the flow control address, type, and PAUSE timer

   797 	 * registers to their default values.  This is done even if flow

   798 	 * control is disabled, because it does not hurt anything to

   799 	 * initialize these registers.

   800 	 */

   801 	e_dbg("Initializing the Flow Control address, type and timer regs\n");

   802 

   803 	ew32(FCT, FLOW_CONTROL_TYPE);

   804 	ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);

   805 	ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);

   806 

   807 	ew32(FCTTV, hw->fc_pause_time);

   808 

   809 	/* Set the flow control receive threshold registers.  Normally,

   810 	 * these registers will be set to a default threshold that may be

   811 	 * adjusted later by the driver's runtime code.  However, if the

   812 	 * ability to transmit pause frames in not enabled, then these

   813 	 * registers will be set to 0.

   814 	 */

   815 	if (!(hw->fc & E1000_FC_TX_PAUSE)) {

   816 		ew32(FCRTL, 0);

   817 		ew32(FCRTH, 0);

   818 	} else {

   819 		/* We need to set up the Receive Threshold high and low water

   820 		 * marks as well as (optionally) enabling the transmission of

   821 		 * XON frames.

   822 		 */

   823 		if (hw->fc_send_xon) {

   824 			ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));

   825 			ew32(FCRTH, hw->fc_high_water);

   826 		} else {

   827 			ew32(FCRTL, hw->fc_low_water);

   828 			ew32(FCRTH, hw->fc_high_water);

   829 		}

   830 	}

   831 	return ret_val;

   832 }

   833 

   834 /**

   835  * e1000_setup_fiber_serdes_link - prepare fiber or serdes link

   836  * @hw: Struct containing variables accessed by shared code

   837  *

   838  * Manipulates Physical Coding Sublayer functions in order to configure

   839  * link. Assumes the hardware has been previously reset and the transmitter

   840  * and receiver are not enabled.

   841  */

   842 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)

   843 {

   844 	u32 ctrl;

   845 	u32 status;

   846 	u32 txcw = 0;

   847 	u32 i;

   848 	u32 signal = 0;

   849 	s32 ret_val;

   850 

   851 	e_dbg("e1000_setup_fiber_serdes_link");

   852 

   853 	/* On adapters with a MAC newer than 82544, SWDP 1 will be

   854 	 * set when the optics detect a signal. On older adapters, it will be

   855 	 * cleared when there is a signal.  This applies to fiber media only.

   856 	 * If we're on serdes media, adjust the output amplitude to value

   857 	 * set in the EEPROM.

   858 	 */

   859 	ctrl = er32(CTRL);

   860 	if (hw->media_type == e1000_media_type_fiber)

   861 		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;

   862 

   863 	ret_val = e1000_adjust_serdes_amplitude(hw);

   864 	if (ret_val)

   865 		return ret_val;

   866 

   867 	/* Take the link out of reset */

   868 	ctrl &= ~(E1000_CTRL_LRST);

   869 

   870 	/* Adjust VCO speed to improve BER performance */

   871 	ret_val = e1000_set_vco_speed(hw);

   872 	if (ret_val)

   873 		return ret_val;

   874 

   875 	e1000_config_collision_dist(hw);

   876 

   877 	/* Check for a software override of the flow control settings, and setup

   878 	 * the device accordingly.  If auto-negotiation is enabled, then

   879 	 * software will have to set the "PAUSE" bits to the correct value in

   880 	 * the Tranmsit Config Word Register (TXCW) and re-start

   881 	 * auto-negotiation.  However, if auto-negotiation is disabled, then

   882 	 * software will have to manually configure the two flow control enable

   883 	 * bits in the CTRL register.

   884 	 *

   885 	 * The possible values of the "fc" parameter are:

   886 	 *  0:  Flow control is completely disabled

   887 	 *  1:  Rx flow control is enabled (we can receive pause frames, but

   888 	 *      not send pause frames).

   889 	 *  2:  Tx flow control is enabled (we can send pause frames but we do

   890 	 *      not support receiving pause frames).

   891 	 *  3:  Both Rx and TX flow control (symmetric) are enabled.

   892 	 */

   893 	switch (hw->fc) {

   894 	case E1000_FC_NONE:

   895 		/* Flow ctrl is completely disabled by a software over-ride */

   896 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);

   897 		break;

   898 	case E1000_FC_RX_PAUSE:

   899 		/* Rx Flow control is enabled and Tx Flow control is disabled by

   900 		 * a software over-ride. Since there really isn't a way to

   901 		 * advertise that we are capable of Rx Pause ONLY, we will

   902 		 * advertise that we support both symmetric and asymmetric Rx

   903 		 * PAUSE. Later, we will disable the adapter's ability to send

   904 		 * PAUSE frames.

   905 		 */

   906 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   907 		break;

   908 	case E1000_FC_TX_PAUSE:

   909 		/* Tx Flow control is enabled, and Rx Flow control is disabled,

   910 		 * by a software over-ride.

   911 		 */

   912 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);

   913 		break;

   914 	case E1000_FC_FULL:

   915 		/* Flow control (both Rx and Tx) is enabled by a software

   916 		 * over-ride.

   917 		 */

   918 		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);

   919 		break;

   920 	default:

   921 		e_dbg("Flow control param set incorrectly\n");

   922 		return -E1000_ERR_CONFIG;

   923 		break;

   924 	}

   925 

   926 	/* Since auto-negotiation is enabled, take the link out of reset (the

   927 	 * link will be in reset, because we previously reset the chip). This

   928 	 * will restart auto-negotiation.  If auto-negotiation is successful

   929 	 * then the link-up status bit will be set and the flow control enable

   930 	 * bits (RFCE and TFCE) will be set according to their negotiated value.

   931 	 */

   932 	e_dbg("Auto-negotiation enabled\n");

   933 

   934 	ew32(TXCW, txcw);

   935 	ew32(CTRL, ctrl);

   936 	E1000_WRITE_FLUSH();

   937 

   938 	hw->txcw = txcw;

   939 	msleep(1);

   940 

   941 	/* If we have a signal (the cable is plugged in) then poll for a

   942 	 * "Link-Up" indication in the Device Status Register.  Time-out if a

   943 	 * link isn't seen in 500 milliseconds seconds (Auto-negotiation should

   944 	 * complete in less than 500 milliseconds even if the other end is doing

   945 	 * it in SW). For internal serdes, we just assume a signal is present,

   946 	 * then poll.

   947 	 */

   948 	if (hw->media_type == e1000_media_type_internal_serdes ||

   949 	    (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {

   950 		e_dbg("Looking for Link\n");

   951 		for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {

   952 			msleep(10);

   953 			status = er32(STATUS);

   954 			if (status & E1000_STATUS_LU)

   955 				break;

   956 		}

   957 		if (i == (LINK_UP_TIMEOUT / 10)) {

   958 			e_dbg("Never got a valid link from auto-neg!!!\n");

   959 			hw->autoneg_failed = 1;

   960 			/* AutoNeg failed to achieve a link, so we'll call

   961 			 * e1000_check_for_link. This routine will force the

   962 			 * link up if we detect a signal. This will allow us to

   963 			 * communicate with non-autonegotiating link partners.

   964 			 */

   965 			ret_val = e1000_check_for_link(hw);

   966 			if (ret_val) {

   967 				e_dbg("Error while checking for link\n");

   968 				return ret_val;

   969 			}

   970 			hw->autoneg_failed = 0;

   971 		} else {

   972 			hw->autoneg_failed = 0;

   973 			e_dbg("Valid Link Found\n");

   974 		}

   975 	} else {

   976 		e_dbg("No Signal Detected\n");

   977 	}

   978 	return E1000_SUCCESS;

   979 }

   980 

   981 /**

   982  * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.

   983  * @hw: Struct containing variables accessed by shared code

   984  *

   985  * Commits changes to PHY configuration by calling e1000_phy_reset().

   986  */

   987 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)

   988 {

   989 	s32 ret_val;

   990 

   991 	/* SW reset the PHY so all changes take effect */

   992 	ret_val = e1000_phy_reset(hw);

   993 	if (ret_val) {

   994 		e_dbg("Error Resetting the PHY\n");

   995 		return ret_val;

   996 	}

   997 

   998 	return E1000_SUCCESS;

   999 }

  1000 

  1001 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)

  1002 {

  1003 	s32 ret_val;

  1004 	u32 ctrl_aux;

  1005 

  1006 	switch (hw->phy_type) {

  1007 	case e1000_phy_8211:

  1008 		ret_val = e1000_copper_link_rtl_setup(hw);

  1009 		if (ret_val) {

  1010 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1011 			return ret_val;

  1012 		}

  1013 		break;

  1014 	case e1000_phy_8201:

  1015 		/* Set RMII mode */

  1016 		ctrl_aux = er32(CTL_AUX);

  1017 		ctrl_aux |= E1000_CTL_AUX_RMII;

  1018 		ew32(CTL_AUX, ctrl_aux);

  1019 		E1000_WRITE_FLUSH();

  1020 

  1021 		/* Disable the J/K bits required for receive */

  1022 		ctrl_aux = er32(CTL_AUX);

  1023 		ctrl_aux |= 0x4;

  1024 		ctrl_aux &= ~0x2;

  1025 		ew32(CTL_AUX, ctrl_aux);

  1026 		E1000_WRITE_FLUSH();

  1027 		ret_val = e1000_copper_link_rtl_setup(hw);

  1028 

  1029 		if (ret_val) {

  1030 			e_dbg("e1000_copper_link_rtl_setup failed!\n");

  1031 			return ret_val;

  1032 		}

  1033 		break;

  1034 	default:

  1035 		e_dbg("Error Resetting the PHY\n");

  1036 		return E1000_ERR_PHY_TYPE;

  1037 	}

  1038 

  1039 	return E1000_SUCCESS;

  1040 }

  1041 

  1042 /**

  1043  * e1000_copper_link_preconfig - early configuration for copper

  1044  * @hw: Struct containing variables accessed by shared code

  1045  *

  1046  * Make sure we have a valid PHY and change PHY mode before link setup.

  1047  */

  1048 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)

  1049 {

  1050 	u32 ctrl;

  1051 	s32 ret_val;

  1052 	u16 phy_data;

  1053 

  1054 	e_dbg("e1000_copper_link_preconfig");

  1055 

  1056 	ctrl = er32(CTRL);

  1057 	/* With 82543, we need to force speed and duplex on the MAC equal to

  1058 	 * what the PHY speed and duplex configuration is. In addition, we need

  1059 	 * to perform a hardware reset on the PHY to take it out of reset.

  1060 	 */

  1061 	if (hw->mac_type > e1000_82543) {

  1062 		ctrl |= E1000_CTRL_SLU;

  1063 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);

  1064 		ew32(CTRL, ctrl);

  1065 	} else {

  1066 		ctrl |=

  1067 		    (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);

  1068 		ew32(CTRL, ctrl);

  1069 		ret_val = e1000_phy_hw_reset(hw);

  1070 		if (ret_val)

  1071 			return ret_val;

  1072 	}

  1073 

  1074 	/* Make sure we have a valid PHY */

  1075 	ret_val = e1000_detect_gig_phy(hw);

  1076 	if (ret_val) {

  1077 		e_dbg("Error, did not detect valid phy.\n");

  1078 		return ret_val;

  1079 	}

  1080 	e_dbg("Phy ID = %x\n", hw->phy_id);

  1081 

  1082 	/* Set PHY to class A mode (if necessary) */

  1083 	ret_val = e1000_set_phy_mode(hw);

  1084 	if (ret_val)

  1085 		return ret_val;

  1086 

  1087 	if ((hw->mac_type == e1000_82545_rev_3) ||

  1088 	    (hw->mac_type == e1000_82546_rev_3)) {

  1089 		ret_val =

  1090 		    e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);

  1091 		phy_data |= 0x00000008;

  1092 		ret_val =

  1093 		    e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);

  1094 	}

  1095 

  1096 	if (hw->mac_type <= e1000_82543 ||

  1097 	    hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||

  1098 	    hw->mac_type == e1000_82541_rev_2

  1099 	    || hw->mac_type == e1000_82547_rev_2)

  1100 		hw->phy_reset_disable = false;

  1101 

  1102 	return E1000_SUCCESS;

  1103 }

  1104 

  1105 /**

  1106  * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.

  1107  * @hw: Struct containing variables accessed by shared code

  1108  */

  1109 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)

  1110 {

  1111 	u32 led_ctrl;

  1112 	s32 ret_val;

  1113 	u16 phy_data;

  1114 

  1115 	e_dbg("e1000_copper_link_igp_setup");

  1116 

  1117 	if (hw->phy_reset_disable)

  1118 		return E1000_SUCCESS;

  1119 

  1120 	ret_val = e1000_phy_reset(hw);

  1121 	if (ret_val) {

  1122 		e_dbg("Error Resetting the PHY\n");

  1123 		return ret_val;

  1124 	}

  1125 

  1126 	/* Wait 15ms for MAC to configure PHY from eeprom settings */

  1127 	msleep(15);

  1128 	/* Configure activity LED after PHY reset */

  1129 	led_ctrl = er32(LEDCTL);

  1130 	led_ctrl &= IGP_ACTIVITY_LED_MASK;

  1131 	led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);

  1132 	ew32(LEDCTL, led_ctrl);

  1133 

  1134 	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */

  1135 	if (hw->phy_type == e1000_phy_igp) {

  1136 		/* disable lplu d3 during driver init */