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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 */ |
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10 |
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11 #include <linux/module.h> |
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12 #include <linux/moduleparam.h> |
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13 #include <linux/pci.h> |
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14 #include <linux/netdevice.h> |
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15 #include <linux/etherdevice.h> |
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16 #include <linux/delay.h> |
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17 #include <linux/ethtool.h> |
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18 #include <linux/mii.h> |
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19 #include <linux/if_vlan.h> |
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20 #include <linux/crc32.h> |
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21 #include <linux/in.h> |
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22 #include <linux/ip.h> |
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23 #include <linux/tcp.h> |
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24 #include <linux/init.h> |
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25 #include <linux/interrupt.h> |
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26 #include <linux/dma-mapping.h> |
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27 #include <linux/pm_runtime.h> |
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28 #include <linux/firmware.h> |
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29 #include <linux/pci-aspm.h> |
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30 #include <linux/prefetch.h> |
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31 |
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32 #include <asm/io.h> |
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33 #include <asm/irq.h> |
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34 |
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35 #define RTL8169_VERSION "2.3LK-NAPI" |
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36 #define MODULENAME "r8169" |
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37 #define PFX MODULENAME ": " |
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38 |
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39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
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40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
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41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
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42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" |
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43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
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44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
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45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" |
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46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
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47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
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48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
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49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
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50 #define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw" |
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51 |
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52 #ifdef RTL8169_DEBUG |
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53 #define assert(expr) \ |
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54 if (!(expr)) { \ |
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55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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56 #expr,__FILE__,__func__,__LINE__); \ |
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57 } |
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58 #define dprintk(fmt, args...) \ |
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59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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60 #else |
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61 #define assert(expr) do {} while (0) |
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62 #define dprintk(fmt, args...) do {} while (0) |
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63 #endif /* RTL8169_DEBUG */ |
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64 |
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65 #define R8169_MSG_DEFAULT \ |
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66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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67 |
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68 #define TX_SLOTS_AVAIL(tp) \ |
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69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) |
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70 |
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71 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ |
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72 #define TX_FRAGS_READY_FOR(tp,nr_frags) \ |
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73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) |
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74 |
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75 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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77 static const int multicast_filter_limit = 32; |
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78 |
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79 #define MAX_READ_REQUEST_SHIFT 12 |
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80 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
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81 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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82 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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83 |
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84 #define R8169_REGS_SIZE 256 |
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85 #define R8169_NAPI_WEIGHT 64 |
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86 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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87 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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88 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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89 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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90 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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91 |
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92 #define RTL8169_TX_TIMEOUT (6*HZ) |
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93 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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94 |
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95 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
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96 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
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97 #define RTL_EEPROM_SIG_ADDR 0x0000 |
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98 |
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99 /* write/read MMIO register */ |
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100 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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101 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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102 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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103 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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104 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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105 #define RTL_R32(reg) readl (ioaddr + (reg)) |
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106 |
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107 enum mac_version { |
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108 RTL_GIGA_MAC_VER_01 = 0, |
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109 RTL_GIGA_MAC_VER_02, |
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110 RTL_GIGA_MAC_VER_03, |
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111 RTL_GIGA_MAC_VER_04, |
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112 RTL_GIGA_MAC_VER_05, |
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113 RTL_GIGA_MAC_VER_06, |
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114 RTL_GIGA_MAC_VER_07, |
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115 RTL_GIGA_MAC_VER_08, |
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116 RTL_GIGA_MAC_VER_09, |
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117 RTL_GIGA_MAC_VER_10, |
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118 RTL_GIGA_MAC_VER_11, |
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119 RTL_GIGA_MAC_VER_12, |
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120 RTL_GIGA_MAC_VER_13, |
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121 RTL_GIGA_MAC_VER_14, |
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122 RTL_GIGA_MAC_VER_15, |
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123 RTL_GIGA_MAC_VER_16, |
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124 RTL_GIGA_MAC_VER_17, |
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125 RTL_GIGA_MAC_VER_18, |
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126 RTL_GIGA_MAC_VER_19, |
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127 RTL_GIGA_MAC_VER_20, |
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128 RTL_GIGA_MAC_VER_21, |
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129 RTL_GIGA_MAC_VER_22, |
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130 RTL_GIGA_MAC_VER_23, |
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131 RTL_GIGA_MAC_VER_24, |
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132 RTL_GIGA_MAC_VER_25, |
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133 RTL_GIGA_MAC_VER_26, |
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134 RTL_GIGA_MAC_VER_27, |
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135 RTL_GIGA_MAC_VER_28, |
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136 RTL_GIGA_MAC_VER_29, |
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137 RTL_GIGA_MAC_VER_30, |
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138 RTL_GIGA_MAC_VER_31, |
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139 RTL_GIGA_MAC_VER_32, |
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140 RTL_GIGA_MAC_VER_33, |
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141 RTL_GIGA_MAC_VER_34, |
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142 RTL_GIGA_MAC_VER_35, |
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143 RTL_GIGA_MAC_VER_36, |
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144 RTL_GIGA_MAC_VER_37, |
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145 RTL_GIGA_MAC_VER_38, |
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146 RTL_GIGA_MAC_VER_39, |
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147 RTL_GIGA_MAC_VER_40, |
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148 RTL_GIGA_MAC_VER_41, |
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149 RTL_GIGA_MAC_NONE = 0xff, |
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150 }; |
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151 |
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152 enum rtl_tx_desc_version { |
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153 RTL_TD_0 = 0, |
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154 RTL_TD_1 = 1, |
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155 }; |
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156 |
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157 #define JUMBO_1K ETH_DATA_LEN |
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158 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) |
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159 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) |
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160 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) |
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161 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) |
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162 |
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163 #define _R(NAME,TD,FW,SZ,B) { \ |
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164 .name = NAME, \ |
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165 .txd_version = TD, \ |
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166 .fw_name = FW, \ |
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167 .jumbo_max = SZ, \ |
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168 .jumbo_tx_csum = B \ |
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169 } |
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170 |
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171 static const struct { |
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172 const char *name; |
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173 enum rtl_tx_desc_version txd_version; |
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174 const char *fw_name; |
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175 u16 jumbo_max; |
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176 bool jumbo_tx_csum; |
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177 } rtl_chip_infos[] = { |
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178 /* PCI devices. */ |
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179 [RTL_GIGA_MAC_VER_01] = |
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180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
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181 [RTL_GIGA_MAC_VER_02] = |
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182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
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183 [RTL_GIGA_MAC_VER_03] = |
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184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
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185 [RTL_GIGA_MAC_VER_04] = |
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186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
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187 [RTL_GIGA_MAC_VER_05] = |
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188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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189 [RTL_GIGA_MAC_VER_06] = |
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190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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191 /* PCI-E devices. */ |
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192 [RTL_GIGA_MAC_VER_07] = |
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193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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194 [RTL_GIGA_MAC_VER_08] = |
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195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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196 [RTL_GIGA_MAC_VER_09] = |
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197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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198 [RTL_GIGA_MAC_VER_10] = |
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199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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200 [RTL_GIGA_MAC_VER_11] = |
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201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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202 [RTL_GIGA_MAC_VER_12] = |
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203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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204 [RTL_GIGA_MAC_VER_13] = |
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205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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206 [RTL_GIGA_MAC_VER_14] = |
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207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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208 [RTL_GIGA_MAC_VER_15] = |
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209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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210 [RTL_GIGA_MAC_VER_16] = |
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211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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212 [RTL_GIGA_MAC_VER_17] = |
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213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
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214 [RTL_GIGA_MAC_VER_18] = |
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215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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216 [RTL_GIGA_MAC_VER_19] = |
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217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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218 [RTL_GIGA_MAC_VER_20] = |
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219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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220 [RTL_GIGA_MAC_VER_21] = |
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221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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222 [RTL_GIGA_MAC_VER_22] = |
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223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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224 [RTL_GIGA_MAC_VER_23] = |
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225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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226 [RTL_GIGA_MAC_VER_24] = |
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227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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228 [RTL_GIGA_MAC_VER_25] = |
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229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
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230 JUMBO_9K, false), |
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231 [RTL_GIGA_MAC_VER_26] = |
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232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
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233 JUMBO_9K, false), |
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234 [RTL_GIGA_MAC_VER_27] = |
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235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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236 [RTL_GIGA_MAC_VER_28] = |
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237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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238 [RTL_GIGA_MAC_VER_29] = |
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239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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240 JUMBO_1K, true), |
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241 [RTL_GIGA_MAC_VER_30] = |
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242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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243 JUMBO_1K, true), |
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244 [RTL_GIGA_MAC_VER_31] = |
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245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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246 [RTL_GIGA_MAC_VER_32] = |
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247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
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248 JUMBO_9K, false), |
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249 [RTL_GIGA_MAC_VER_33] = |
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250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
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251 JUMBO_9K, false), |
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252 [RTL_GIGA_MAC_VER_34] = |
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253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
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254 JUMBO_9K, false), |
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255 [RTL_GIGA_MAC_VER_35] = |
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256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
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257 JUMBO_9K, false), |
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258 [RTL_GIGA_MAC_VER_36] = |
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259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
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260 JUMBO_9K, false), |
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261 [RTL_GIGA_MAC_VER_37] = |
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262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, |
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263 JUMBO_1K, true), |
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264 [RTL_GIGA_MAC_VER_38] = |
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265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, |
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266 JUMBO_9K, false), |
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267 [RTL_GIGA_MAC_VER_39] = |
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268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, |
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269 JUMBO_1K, true), |
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270 [RTL_GIGA_MAC_VER_40] = |
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271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1, |
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272 JUMBO_9K, false), |
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273 [RTL_GIGA_MAC_VER_41] = |
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274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false), |
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275 }; |
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276 #undef _R |
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277 |
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278 enum cfg_version { |
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279 RTL_CFG_0 = 0x00, |
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280 RTL_CFG_1, |
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281 RTL_CFG_2 |
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282 }; |
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283 |
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284 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
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285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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290 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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291 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
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292 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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293 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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294 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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295 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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296 { 0x0001, 0x8168, |
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297 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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298 {0,}, |
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299 }; |
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300 |
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301 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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302 |
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303 static int rx_buf_sz = 16383; |
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304 static int use_dac; |
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305 static struct { |
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306 u32 msg_enable; |
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307 } debug = { -1 }; |
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308 |
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309 enum rtl_registers { |
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310 MAC0 = 0, /* Ethernet hardware address. */ |
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311 MAC4 = 4, |
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312 MAR0 = 8, /* Multicast filter. */ |
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313 CounterAddrLow = 0x10, |
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314 CounterAddrHigh = 0x14, |
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315 TxDescStartAddrLow = 0x20, |
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316 TxDescStartAddrHigh = 0x24, |
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317 TxHDescStartAddrLow = 0x28, |
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318 TxHDescStartAddrHigh = 0x2c, |
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319 FLASH = 0x30, |
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320 ERSR = 0x36, |
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321 ChipCmd = 0x37, |
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322 TxPoll = 0x38, |
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323 IntrMask = 0x3c, |
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324 IntrStatus = 0x3e, |
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325 |
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326 TxConfig = 0x40, |
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327 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
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328 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ |
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329 |
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330 RxConfig = 0x44, |
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331 #define RX128_INT_EN (1 << 15) /* 8111c and later */ |
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332 #define RX_MULTI_EN (1 << 14) /* 8111c only */ |
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333 #define RXCFG_FIFO_SHIFT 13 |
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334 /* No threshold before first PCI xfer */ |
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335 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) |
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336 #define RXCFG_DMA_SHIFT 8 |
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337 /* Unlimited maximum PCI burst. */ |
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338 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) |
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339 |
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340 RxMissed = 0x4c, |
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341 Cfg9346 = 0x50, |
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342 Config0 = 0x51, |
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343 Config1 = 0x52, |
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344 Config2 = 0x53, |
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345 #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
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346 |
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347 Config3 = 0x54, |
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348 Config4 = 0x55, |
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349 Config5 = 0x56, |
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350 MultiIntr = 0x5c, |
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351 PHYAR = 0x60, |
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352 PHYstatus = 0x6c, |
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353 RxMaxSize = 0xda, |
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354 CPlusCmd = 0xe0, |
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355 IntrMitigate = 0xe2, |
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356 RxDescAddrLow = 0xe4, |
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357 RxDescAddrHigh = 0xe8, |
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358 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
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359 |
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360 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ |
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361 |
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362 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ |
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363 |
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364 #define TxPacketMax (8064 >> 7) |
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365 #define EarlySize 0x27 |
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366 |
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367 FuncEvent = 0xf0, |
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368 FuncEventMask = 0xf4, |
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369 FuncPresetState = 0xf8, |
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370 FuncForceEvent = 0xfc, |
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371 }; |
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372 |
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373 enum rtl8110_registers { |
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374 TBICSR = 0x64, |
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375 TBI_ANAR = 0x68, |
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376 TBI_LPAR = 0x6a, |
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377 }; |
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378 |
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379 enum rtl8168_8101_registers { |
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380 CSIDR = 0x64, |
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381 CSIAR = 0x68, |
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382 #define CSIAR_FLAG 0x80000000 |
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383 #define CSIAR_WRITE_CMD 0x80000000 |
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384 #define CSIAR_BYTE_ENABLE 0x0f |
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385 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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386 #define CSIAR_ADDR_MASK 0x0fff |
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387 #define CSIAR_FUNC_CARD 0x00000000 |
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388 #define CSIAR_FUNC_SDIO 0x00010000 |
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389 #define CSIAR_FUNC_NIC 0x00020000 |
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390 PMCH = 0x6f, |
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391 EPHYAR = 0x80, |
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392 #define EPHYAR_FLAG 0x80000000 |
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393 #define EPHYAR_WRITE_CMD 0x80000000 |
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394 #define EPHYAR_REG_MASK 0x1f |
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395 #define EPHYAR_REG_SHIFT 16 |
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396 #define EPHYAR_DATA_MASK 0xffff |
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397 DLLPR = 0xd0, |
|
398 #define PFM_EN (1 << 6) |
|
399 DBG_REG = 0xd1, |
|
400 #define FIX_NAK_1 (1 << 4) |
|
401 #define FIX_NAK_2 (1 << 3) |
|
402 TWSI = 0xd2, |
|
403 MCU = 0xd3, |
|
404 #define NOW_IS_OOB (1 << 7) |
|
405 #define TX_EMPTY (1 << 5) |
|
406 #define RX_EMPTY (1 << 4) |
|
407 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) |
|
408 #define EN_NDP (1 << 3) |
|
409 #define EN_OOB_RESET (1 << 2) |
|
410 #define LINK_LIST_RDY (1 << 1) |
|
411 EFUSEAR = 0xdc, |
|
412 #define EFUSEAR_FLAG 0x80000000 |
|
413 #define EFUSEAR_WRITE_CMD 0x80000000 |
|
414 #define EFUSEAR_READ_CMD 0x00000000 |
|
415 #define EFUSEAR_REG_MASK 0x03ff |
|
416 #define EFUSEAR_REG_SHIFT 8 |
|
417 #define EFUSEAR_DATA_MASK 0xff |
|
418 }; |
|
419 |
|
420 enum rtl8168_registers { |
|
421 LED_FREQ = 0x1a, |
|
422 EEE_LED = 0x1b, |
|
423 ERIDR = 0x70, |
|
424 ERIAR = 0x74, |
|
425 #define ERIAR_FLAG 0x80000000 |
|
426 #define ERIAR_WRITE_CMD 0x80000000 |
|
427 #define ERIAR_READ_CMD 0x00000000 |
|
428 #define ERIAR_ADDR_BYTE_ALIGN 4 |
|
429 #define ERIAR_TYPE_SHIFT 16 |
|
430 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
|
431 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) |
|
432 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) |
|
433 #define ERIAR_MASK_SHIFT 12 |
|
434 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) |
|
435 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) |
|
436 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
|
437 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
|
438 EPHY_RXER_NUM = 0x7c, |
|
439 OCPDR = 0xb0, /* OCP GPHY access */ |
|
440 #define OCPDR_WRITE_CMD 0x80000000 |
|
441 #define OCPDR_READ_CMD 0x00000000 |
|
442 #define OCPDR_REG_MASK 0x7f |
|
443 #define OCPDR_GPHY_REG_SHIFT 16 |
|
444 #define OCPDR_DATA_MASK 0xffff |
|
445 OCPAR = 0xb4, |
|
446 #define OCPAR_FLAG 0x80000000 |
|
447 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 |
|
448 #define OCPAR_GPHY_READ_CMD 0x0000f060 |
|
449 GPHY_OCP = 0xb8, |
|
450 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
|
451 MISC = 0xf0, /* 8168e only. */ |
|
452 #define TXPLA_RST (1 << 29) |
|
453 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
|
454 #define PWM_EN (1 << 22) |
|
455 #define RXDV_GATED_EN (1 << 19) |
|
456 #define EARLY_TALLY_EN (1 << 16) |
|
457 }; |
|
458 |
|
459 enum rtl_register_content { |
|
460 /* InterruptStatusBits */ |
|
461 SYSErr = 0x8000, |
|
462 PCSTimeout = 0x4000, |
|
463 SWInt = 0x0100, |
|
464 TxDescUnavail = 0x0080, |
|
465 RxFIFOOver = 0x0040, |
|
466 LinkChg = 0x0020, |
|
467 RxOverflow = 0x0010, |
|
468 TxErr = 0x0008, |
|
469 TxOK = 0x0004, |
|
470 RxErr = 0x0002, |
|
471 RxOK = 0x0001, |
|
472 |
|
473 /* RxStatusDesc */ |
|
474 RxBOVF = (1 << 24), |
|
475 RxFOVF = (1 << 23), |
|
476 RxRWT = (1 << 22), |
|
477 RxRES = (1 << 21), |
|
478 RxRUNT = (1 << 20), |
|
479 RxCRC = (1 << 19), |
|
480 |
|
481 /* ChipCmdBits */ |
|
482 StopReq = 0x80, |
|
483 CmdReset = 0x10, |
|
484 CmdRxEnb = 0x08, |
|
485 CmdTxEnb = 0x04, |
|
486 RxBufEmpty = 0x01, |
|
487 |
|
488 /* TXPoll register p.5 */ |
|
489 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
490 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
491 FSWInt = 0x01, /* Forced software interrupt */ |
|
492 |
|
493 /* Cfg9346Bits */ |
|
494 Cfg9346_Lock = 0x00, |
|
495 Cfg9346_Unlock = 0xc0, |
|
496 |
|
497 /* rx_mode_bits */ |
|
498 AcceptErr = 0x20, |
|
499 AcceptRunt = 0x10, |
|
500 AcceptBroadcast = 0x08, |
|
501 AcceptMulticast = 0x04, |
|
502 AcceptMyPhys = 0x02, |
|
503 AcceptAllPhys = 0x01, |
|
504 #define RX_CONFIG_ACCEPT_MASK 0x3f |
|
505 |
|
506 /* TxConfigBits */ |
|
507 TxInterFrameGapShift = 24, |
|
508 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
509 |
|
510 /* Config1 register p.24 */ |
|
511 LEDS1 = (1 << 7), |
|
512 LEDS0 = (1 << 6), |
|
513 Speed_down = (1 << 4), |
|
514 MEMMAP = (1 << 3), |
|
515 IOMAP = (1 << 2), |
|
516 VPD = (1 << 1), |
|
517 PMEnable = (1 << 0), /* Power Management Enable */ |
|
518 |
|
519 /* Config2 register p. 25 */ |
|
520 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
|
521 PCI_Clock_66MHz = 0x01, |
|
522 PCI_Clock_33MHz = 0x00, |
|
523 |
|
524 /* Config3 register p.25 */ |
|
525 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
526 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
527 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
|
528 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
|
529 |
|
530 /* Config4 register */ |
|
531 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ |
|
532 |
|
533 /* Config5 register p.27 */ |
|
534 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
535 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
536 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
537 Spi_en = (1 << 3), |
|
538 LanWake = (1 << 1), /* LanWake enable/disable */ |
|
539 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
540 |
|
541 /* TBICSR p.28 */ |
|
542 TBIReset = 0x80000000, |
|
543 TBILoopback = 0x40000000, |
|
544 TBINwEnable = 0x20000000, |
|
545 TBINwRestart = 0x10000000, |
|
546 TBILinkOk = 0x02000000, |
|
547 TBINwComplete = 0x01000000, |
|
548 |
|
549 /* CPlusCmd p.31 */ |
|
550 EnableBist = (1 << 15), // 8168 8101 |
|
551 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
|
552 Normal_mode = (1 << 13), // unused |
|
553 Force_half_dup = (1 << 12), // 8168 8101 |
|
554 Force_rxflow_en = (1 << 11), // 8168 8101 |
|
555 Force_txflow_en = (1 << 10), // 8168 8101 |
|
556 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
|
557 ASF = (1 << 8), // 8168 8101 |
|
558 PktCntrDisable = (1 << 7), // 8168 8101 |
|
559 Mac_dbgo_sel = 0x001c, // 8168 |
|
560 RxVlan = (1 << 6), |
|
561 RxChkSum = (1 << 5), |
|
562 PCIDAC = (1 << 4), |
|
563 PCIMulRW = (1 << 3), |
|
564 INTT_0 = 0x0000, // 8168 |
|
565 INTT_1 = 0x0001, // 8168 |
|
566 INTT_2 = 0x0002, // 8168 |
|
567 INTT_3 = 0x0003, // 8168 |
|
568 |
|
569 /* rtl8169_PHYstatus */ |
|
570 TBI_Enable = 0x80, |
|
571 TxFlowCtrl = 0x40, |
|
572 RxFlowCtrl = 0x20, |
|
573 _1000bpsF = 0x10, |
|
574 _100bps = 0x08, |
|
575 _10bps = 0x04, |
|
576 LinkStatus = 0x02, |
|
577 FullDup = 0x01, |
|
578 |
|
579 /* _TBICSRBit */ |
|
580 TBILinkOK = 0x02000000, |
|
581 |
|
582 /* DumpCounterCommand */ |
|
583 CounterDump = 0x8, |
|
584 }; |
|
585 |
|
586 enum rtl_desc_bit { |
|
587 /* First doubleword. */ |
|
588 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
589 RingEnd = (1 << 30), /* End of descriptor ring */ |
|
590 FirstFrag = (1 << 29), /* First segment of a packet */ |
|
591 LastFrag = (1 << 28), /* Final segment of a packet */ |
|
592 }; |
|
593 |
|
594 /* Generic case. */ |
|
595 enum rtl_tx_desc_bit { |
|
596 /* First doubleword. */ |
|
597 TD_LSO = (1 << 27), /* Large Send Offload */ |
|
598 #define TD_MSS_MAX 0x07ffu /* MSS value */ |
|
599 |
|
600 /* Second doubleword. */ |
|
601 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
602 }; |
|
603 |
|
604 /* 8169, 8168b and 810x except 8102e. */ |
|
605 enum rtl_tx_desc_bit_0 { |
|
606 /* First doubleword. */ |
|
607 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ |
|
608 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
609 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
610 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ |
|
611 }; |
|
612 |
|
613 /* 8102e, 8168c and beyond. */ |
|
614 enum rtl_tx_desc_bit_1 { |
|
615 /* Second doubleword. */ |
|
616 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
|
617 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ |
|
618 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
|
619 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ |
|
620 }; |
|
621 |
|
622 static const struct rtl_tx_desc_info { |
|
623 struct { |
|
624 u32 udp; |
|
625 u32 tcp; |
|
626 } checksum; |
|
627 u16 mss_shift; |
|
628 u16 opts_offset; |
|
629 } tx_desc_info [] = { |
|
630 [RTL_TD_0] = { |
|
631 .checksum = { |
|
632 .udp = TD0_IP_CS | TD0_UDP_CS, |
|
633 .tcp = TD0_IP_CS | TD0_TCP_CS |
|
634 }, |
|
635 .mss_shift = TD0_MSS_SHIFT, |
|
636 .opts_offset = 0 |
|
637 }, |
|
638 [RTL_TD_1] = { |
|
639 .checksum = { |
|
640 .udp = TD1_IP_CS | TD1_UDP_CS, |
|
641 .tcp = TD1_IP_CS | TD1_TCP_CS |
|
642 }, |
|
643 .mss_shift = TD1_MSS_SHIFT, |
|
644 .opts_offset = 1 |
|
645 } |
|
646 }; |
|
647 |
|
648 enum rtl_rx_desc_bit { |
|
649 /* Rx private */ |
|
650 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
651 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
652 |
|
653 #define RxProtoUDP (PID1) |
|
654 #define RxProtoTCP (PID0) |
|
655 #define RxProtoIP (PID1 | PID0) |
|
656 #define RxProtoMask RxProtoIP |
|
657 |
|
658 IPFail = (1 << 16), /* IP checksum failed */ |
|
659 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
660 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
661 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
662 }; |
|
663 |
|
664 #define RsvdMask 0x3fffc000 |
|
665 |
|
666 struct TxDesc { |
|
667 __le32 opts1; |
|
668 __le32 opts2; |
|
669 __le64 addr; |
|
670 }; |
|
671 |
|
672 struct RxDesc { |
|
673 __le32 opts1; |
|
674 __le32 opts2; |
|
675 __le64 addr; |
|
676 }; |
|
677 |
|
678 struct ring_info { |
|
679 struct sk_buff *skb; |
|
680 u32 len; |
|
681 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
682 }; |
|
683 |
|
684 enum features { |
|
685 RTL_FEATURE_WOL = (1 << 0), |
|
686 RTL_FEATURE_MSI = (1 << 1), |
|
687 RTL_FEATURE_GMII = (1 << 2), |
|
688 }; |
|
689 |
|
690 struct rtl8169_counters { |
|
691 __le64 tx_packets; |
|
692 __le64 rx_packets; |
|
693 __le64 tx_errors; |
|
694 __le32 rx_errors; |
|
695 __le16 rx_missed; |
|
696 __le16 align_errors; |
|
697 __le32 tx_one_collision; |
|
698 __le32 tx_multi_collision; |
|
699 __le64 rx_unicast; |
|
700 __le64 rx_broadcast; |
|
701 __le32 rx_multicast; |
|
702 __le16 tx_aborted; |
|
703 __le16 tx_underun; |
|
704 }; |
|
705 |
|
706 enum rtl_flag { |
|
707 RTL_FLAG_TASK_ENABLED, |
|
708 RTL_FLAG_TASK_SLOW_PENDING, |
|
709 RTL_FLAG_TASK_RESET_PENDING, |
|
710 RTL_FLAG_TASK_PHY_PENDING, |
|
711 RTL_FLAG_MAX |
|
712 }; |
|
713 |
|
714 struct rtl8169_stats { |
|
715 u64 packets; |
|
716 u64 bytes; |
|
717 struct u64_stats_sync syncp; |
|
718 }; |
|
719 |
|
720 struct rtl8169_private { |
|
721 void __iomem *mmio_addr; /* memory map physical address */ |
|
722 struct pci_dev *pci_dev; |
|
723 struct net_device *dev; |
|
724 struct napi_struct napi; |
|
725 u32 msg_enable; |
|
726 u16 txd_version; |
|
727 u16 mac_version; |
|
728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
730 u32 dirty_rx; |
|
731 u32 dirty_tx; |
|
732 struct rtl8169_stats rx_stats; |
|
733 struct rtl8169_stats tx_stats; |
|
734 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
735 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
736 dma_addr_t TxPhyAddr; |
|
737 dma_addr_t RxPhyAddr; |
|
738 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
739 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
740 struct timer_list timer; |
|
741 u16 cp_cmd; |
|
742 |
|
743 u16 event_slow; |
|
744 |
|
745 struct mdio_ops { |
|
746 void (*write)(struct rtl8169_private *, int, int); |
|
747 int (*read)(struct rtl8169_private *, int); |
|
748 } mdio_ops; |
|
749 |
|
750 struct pll_power_ops { |
|
751 void (*down)(struct rtl8169_private *); |
|
752 void (*up)(struct rtl8169_private *); |
|
753 } pll_power_ops; |
|
754 |
|
755 struct jumbo_ops { |
|
756 void (*enable)(struct rtl8169_private *); |
|
757 void (*disable)(struct rtl8169_private *); |
|
758 } jumbo_ops; |
|
759 |
|
760 struct csi_ops { |
|
761 void (*write)(struct rtl8169_private *, int, int); |
|
762 u32 (*read)(struct rtl8169_private *, int); |
|
763 } csi_ops; |
|
764 |
|
765 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
|
766 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
767 void (*phy_reset_enable)(struct rtl8169_private *tp); |
|
768 void (*hw_start)(struct net_device *); |
|
769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
|
770 unsigned int (*link_ok)(void __iomem *); |
|
771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
772 |
|
773 struct { |
|
774 DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
|
775 struct mutex mutex; |
|
776 struct work_struct work; |
|
777 } wk; |
|
778 |
|
779 unsigned features; |
|
780 |
|
781 struct mii_if_info mii; |
|
782 struct rtl8169_counters counters; |
|
783 u32 saved_wolopts; |
|
784 u32 opts1_mask; |
|
785 |
|
786 struct rtl_fw { |
|
787 const struct firmware *fw; |
|
788 |
|
789 #define RTL_VER_SIZE 32 |
|
790 |
|
791 char version[RTL_VER_SIZE]; |
|
792 |
|
793 struct rtl_fw_phy_action { |
|
794 __le32 *code; |
|
795 size_t size; |
|
796 } phy_action; |
|
797 } *rtl_fw; |
|
798 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
|
799 |
|
800 u32 ocp_base; |
|
801 }; |
|
802 |
|
803 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
804 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
|
805 module_param(use_dac, int, 0); |
|
806 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
807 module_param_named(debug, debug.msg_enable, int, 0); |
|
808 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
809 MODULE_LICENSE("GPL"); |
|
810 MODULE_VERSION(RTL8169_VERSION); |
|
811 MODULE_FIRMWARE(FIRMWARE_8168D_1); |
|
812 MODULE_FIRMWARE(FIRMWARE_8168D_2); |
|
813 MODULE_FIRMWARE(FIRMWARE_8168E_1); |
|
814 MODULE_FIRMWARE(FIRMWARE_8168E_2); |
|
815 MODULE_FIRMWARE(FIRMWARE_8168E_3); |
|
816 MODULE_FIRMWARE(FIRMWARE_8105E_1); |
|
817 MODULE_FIRMWARE(FIRMWARE_8168F_1); |
|
818 MODULE_FIRMWARE(FIRMWARE_8168F_2); |
|
819 MODULE_FIRMWARE(FIRMWARE_8402_1); |
|
820 MODULE_FIRMWARE(FIRMWARE_8411_1); |
|
821 MODULE_FIRMWARE(FIRMWARE_8106E_1); |
|
822 MODULE_FIRMWARE(FIRMWARE_8168G_1); |
|
823 |
|
824 static void rtl_lock_work(struct rtl8169_private *tp) |
|
825 { |
|
826 mutex_lock(&tp->wk.mutex); |
|
827 } |
|
828 |
|
829 static void rtl_unlock_work(struct rtl8169_private *tp) |
|
830 { |
|
831 mutex_unlock(&tp->wk.mutex); |
|
832 } |
|
833 |
|
834 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
835 { |
|
836 int cap = pci_pcie_cap(pdev); |
|
837 |
|
838 if (cap) { |
|
839 u16 ctl; |
|
840 |
|
841 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
842 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
843 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
844 } |
|
845 } |
|
846 |
|
847 struct rtl_cond { |
|
848 bool (*check)(struct rtl8169_private *); |
|
849 const char *msg; |
|
850 }; |
|
851 |
|
852 static void rtl_udelay(unsigned int d) |
|
853 { |
|
854 udelay(d); |
|
855 } |
|
856 |
|
857 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, |
|
858 void (*delay)(unsigned int), unsigned int d, int n, |
|
859 bool high) |
|
860 { |
|
861 int i; |
|
862 |
|
863 for (i = 0; i < n; i++) { |
|
864 delay(d); |
|
865 if (c->check(tp) == high) |
|
866 return true; |
|
867 } |
|
868 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", |
|
869 c->msg, !high, n, d); |
|
870 return false; |
|
871 } |
|
872 |
|
873 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, |
|
874 const struct rtl_cond *c, |
|
875 unsigned int d, int n) |
|
876 { |
|
877 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); |
|
878 } |
|
879 |
|
880 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, |
|
881 const struct rtl_cond *c, |
|
882 unsigned int d, int n) |
|
883 { |
|
884 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); |
|
885 } |
|
886 |
|
887 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, |
|
888 const struct rtl_cond *c, |
|
889 unsigned int d, int n) |
|
890 { |
|
891 return rtl_loop_wait(tp, c, msleep, d, n, true); |
|
892 } |
|
893 |
|
894 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, |
|
895 const struct rtl_cond *c, |
|
896 unsigned int d, int n) |
|
897 { |
|
898 return rtl_loop_wait(tp, c, msleep, d, n, false); |
|
899 } |
|
900 |
|
901 #define DECLARE_RTL_COND(name) \ |
|
902 static bool name ## _check(struct rtl8169_private *); \ |
|
903 \ |
|
904 static const struct rtl_cond name = { \ |
|
905 .check = name ## _check, \ |
|
906 .msg = #name \ |
|
907 }; \ |
|
908 \ |
|
909 static bool name ## _check(struct rtl8169_private *tp) |
|
910 |
|
911 DECLARE_RTL_COND(rtl_ocpar_cond) |
|
912 { |
|
913 void __iomem *ioaddr = tp->mmio_addr; |
|
914 |
|
915 return RTL_R32(OCPAR) & OCPAR_FLAG; |
|
916 } |
|
917 |
|
918 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
|
919 { |
|
920 void __iomem *ioaddr = tp->mmio_addr; |
|
921 |
|
922 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
923 |
|
924 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? |
|
925 RTL_R32(OCPDR) : ~0; |
|
926 } |
|
927 |
|
928 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) |
|
929 { |
|
930 void __iomem *ioaddr = tp->mmio_addr; |
|
931 |
|
932 RTL_W32(OCPDR, data); |
|
933 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
934 |
|
935 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); |
|
936 } |
|
937 |
|
938 DECLARE_RTL_COND(rtl_eriar_cond) |
|
939 { |
|
940 void __iomem *ioaddr = tp->mmio_addr; |
|
941 |
|
942 return RTL_R32(ERIAR) & ERIAR_FLAG; |
|
943 } |
|
944 |
|
945 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
|
946 { |
|
947 void __iomem *ioaddr = tp->mmio_addr; |
|
948 |
|
949 RTL_W8(ERIDR, cmd); |
|
950 RTL_W32(ERIAR, 0x800010e8); |
|
951 msleep(2); |
|
952 |
|
953 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5)) |
|
954 return; |
|
955 |
|
956 ocp_write(tp, 0x1, 0x30, 0x00000001); |
|
957 } |
|
958 |
|
959 #define OOB_CMD_RESET 0x00 |
|
960 #define OOB_CMD_DRIVER_START 0x05 |
|
961 #define OOB_CMD_DRIVER_STOP 0x06 |
|
962 |
|
963 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
|
964 { |
|
965 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; |
|
966 } |
|
967 |
|
968 DECLARE_RTL_COND(rtl_ocp_read_cond) |
|
969 { |
|
970 u16 reg; |
|
971 |
|
972 reg = rtl8168_get_ocp_reg(tp); |
|
973 |
|
974 return ocp_read(tp, 0x0f, reg) & 0x00000800; |
|
975 } |
|
976 |
|
977 static void rtl8168_driver_start(struct rtl8169_private *tp) |
|
978 { |
|
979 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
|
980 |
|
981 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
|
982 } |
|
983 |
|
984 static void rtl8168_driver_stop(struct rtl8169_private *tp) |
|
985 { |
|
986 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); |
|
987 |
|
988 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
|
989 } |
|
990 |
|
991 static int r8168dp_check_dash(struct rtl8169_private *tp) |
|
992 { |
|
993 u16 reg = rtl8168_get_ocp_reg(tp); |
|
994 |
|
995 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
|
996 } |
|
997 |
|
998 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) |
|
999 { |
|
1000 if (reg & 0xffff0001) { |
|
1001 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); |
|
1002 return true; |
|
1003 } |
|
1004 return false; |
|
1005 } |
|
1006 |
|
1007 DECLARE_RTL_COND(rtl_ocp_gphy_cond) |
|
1008 { |
|
1009 void __iomem *ioaddr = tp->mmio_addr; |
|
1010 |
|
1011 return RTL_R32(GPHY_OCP) & OCPAR_FLAG; |
|
1012 } |
|
1013 |
|
1014 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
|
1015 { |
|
1016 void __iomem *ioaddr = tp->mmio_addr; |
|
1017 |
|
1018 if (rtl_ocp_reg_failure(tp, reg)) |
|
1019 return; |
|
1020 |
|
1021 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); |
|
1022 |
|
1023 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); |
|
1024 } |
|
1025 |
|
1026 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) |
|
1027 { |
|
1028 void __iomem *ioaddr = tp->mmio_addr; |
|
1029 |
|
1030 if (rtl_ocp_reg_failure(tp, reg)) |
|
1031 return 0; |
|
1032 |
|
1033 RTL_W32(GPHY_OCP, reg << 15); |
|
1034 |
|
1035 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? |
|
1036 (RTL_R32(GPHY_OCP) & 0xffff) : ~0; |
|
1037 } |
|
1038 |
|
1039 static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m) |
|
1040 { |
|
1041 int val; |
|
1042 |
|
1043 val = r8168_phy_ocp_read(tp, reg); |
|
1044 r8168_phy_ocp_write(tp, reg, (val | p) & ~m); |
|
1045 } |
|
1046 |
|
1047 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
|
1048 { |
|
1049 void __iomem *ioaddr = tp->mmio_addr; |
|
1050 |
|
1051 if (rtl_ocp_reg_failure(tp, reg)) |
|
1052 return; |
|
1053 |
|
1054 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data); |
|
1055 } |
|
1056 |
|
1057 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) |
|
1058 { |
|
1059 void __iomem *ioaddr = tp->mmio_addr; |
|
1060 |
|
1061 if (rtl_ocp_reg_failure(tp, reg)) |
|
1062 return 0; |
|
1063 |
|
1064 RTL_W32(OCPDR, reg << 15); |
|
1065 |
|
1066 return RTL_R32(OCPDR); |
|
1067 } |
|
1068 |
|
1069 #define OCP_STD_PHY_BASE 0xa400 |
|
1070 |
|
1071 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) |
|
1072 { |
|
1073 if (reg == 0x1f) { |
|
1074 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; |
|
1075 return; |
|
1076 } |
|
1077 |
|
1078 if (tp->ocp_base != OCP_STD_PHY_BASE) |
|
1079 reg -= 0x10; |
|
1080 |
|
1081 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); |
|
1082 } |
|
1083 |
|
1084 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) |
|
1085 { |
|
1086 if (tp->ocp_base != OCP_STD_PHY_BASE) |
|
1087 reg -= 0x10; |
|
1088 |
|
1089 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); |
|
1090 } |
|
1091 |
|
1092 DECLARE_RTL_COND(rtl_phyar_cond) |
|
1093 { |
|
1094 void __iomem *ioaddr = tp->mmio_addr; |
|
1095 |
|
1096 return RTL_R32(PHYAR) & 0x80000000; |
|
1097 } |
|
1098 |
|
1099 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
|
1100 { |
|
1101 void __iomem *ioaddr = tp->mmio_addr; |
|
1102 |
|
1103 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
|
1104 |
|
1105 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
|
1106 /* |
|
1107 * According to hardware specs a 20us delay is required after write |
|
1108 * complete indication, but before sending next command. |
|
1109 */ |
|
1110 udelay(20); |
|
1111 } |
|
1112 |
|
1113 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
|
1114 { |
|
1115 void __iomem *ioaddr = tp->mmio_addr; |
|
1116 int value; |
|
1117 |
|
1118 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16); |
|
1119 |
|
1120 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
|
1121 RTL_R32(PHYAR) & 0xffff : ~0; |
|
1122 |
|
1123 /* |
|
1124 * According to hardware specs a 20us delay is required after read |
|
1125 * complete indication, but before sending next command. |
|
1126 */ |
|
1127 udelay(20); |
|
1128 |
|
1129 return value; |
|
1130 } |
|
1131 |
|
1132 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
|
1133 { |
|
1134 void __iomem *ioaddr = tp->mmio_addr; |
|
1135 |
|
1136 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
|
1137 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
|
1138 RTL_W32(EPHY_RXER_NUM, 0); |
|
1139 |
|
1140 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
|
1141 } |
|
1142 |
|
1143 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
|
1144 { |
|
1145 r8168dp_1_mdio_access(tp, reg, |
|
1146 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); |
|
1147 } |
|
1148 |
|
1149 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
|
1150 { |
|
1151 void __iomem *ioaddr = tp->mmio_addr; |
|
1152 |
|
1153 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
|
1154 |
|
1155 mdelay(1); |
|
1156 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); |
|
1157 RTL_W32(EPHY_RXER_NUM, 0); |
|
1158 |
|
1159 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
|
1160 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0; |
|
1161 } |
|
1162 |
|
1163 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
|
1164 |
|
1165 static void r8168dp_2_mdio_start(void __iomem *ioaddr) |
|
1166 { |
|
1167 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
|
1168 } |
|
1169 |
|
1170 static void r8168dp_2_mdio_stop(void __iomem *ioaddr) |
|
1171 { |
|
1172 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
|
1173 } |
|
1174 |
|
1175 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
|
1176 { |
|
1177 void __iomem *ioaddr = tp->mmio_addr; |
|
1178 |
|
1179 r8168dp_2_mdio_start(ioaddr); |
|
1180 |
|
1181 r8169_mdio_write(tp, reg, value); |
|
1182 |
|
1183 r8168dp_2_mdio_stop(ioaddr); |
|
1184 } |
|
1185 |
|
1186 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
|
1187 { |
|
1188 void __iomem *ioaddr = tp->mmio_addr; |
|
1189 int value; |
|
1190 |
|
1191 r8168dp_2_mdio_start(ioaddr); |
|
1192 |
|
1193 value = r8169_mdio_read(tp, reg); |
|
1194 |
|
1195 r8168dp_2_mdio_stop(ioaddr); |
|
1196 |
|
1197 return value; |
|
1198 } |
|
1199 |
|
1200 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
|
1201 { |
|
1202 tp->mdio_ops.write(tp, location, val); |
|
1203 } |
|
1204 |
|
1205 static int rtl_readphy(struct rtl8169_private *tp, int location) |
|
1206 { |
|
1207 return tp->mdio_ops.read(tp, location); |
|
1208 } |
|
1209 |
|
1210 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) |
|
1211 { |
|
1212 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); |
|
1213 } |
|
1214 |
|
1215 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
|
1216 { |
|
1217 int val; |
|
1218 |
|
1219 val = rtl_readphy(tp, reg_addr); |
|
1220 rtl_writephy(tp, reg_addr, (val | p) & ~m); |
|
1221 } |
|
1222 |
|
1223 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
1224 int val) |
|
1225 { |
|
1226 struct rtl8169_private *tp = netdev_priv(dev); |
|
1227 |
|
1228 rtl_writephy(tp, location, val); |
|
1229 } |
|
1230 |
|
1231 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
1232 { |
|
1233 struct rtl8169_private *tp = netdev_priv(dev); |
|
1234 |
|
1235 return rtl_readphy(tp, location); |
|
1236 } |
|
1237 |
|
1238 DECLARE_RTL_COND(rtl_ephyar_cond) |
|
1239 { |
|
1240 void __iomem *ioaddr = tp->mmio_addr; |
|
1241 |
|
1242 return RTL_R32(EPHYAR) & EPHYAR_FLAG; |
|
1243 } |
|
1244 |
|
1245 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
|
1246 { |
|
1247 void __iomem *ioaddr = tp->mmio_addr; |
|
1248 |
|
1249 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
1250 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1251 |
|
1252 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
|
1253 |
|
1254 udelay(10); |
|
1255 } |
|
1256 |
|
1257 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
|
1258 { |
|
1259 void __iomem *ioaddr = tp->mmio_addr; |
|
1260 |
|
1261 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1262 |
|
1263 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
|
1264 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; |
|
1265 } |
|
1266 |
|
1267 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
|
1268 u32 val, int type) |
|
1269 { |
|
1270 void __iomem *ioaddr = tp->mmio_addr; |
|
1271 |
|
1272 BUG_ON((addr & 3) || (mask == 0)); |
|
1273 RTL_W32(ERIDR, val); |
|
1274 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); |
|
1275 |
|
1276 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
|
1277 } |
|
1278 |
|
1279 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
|
1280 { |
|
1281 void __iomem *ioaddr = tp->mmio_addr; |
|
1282 |
|
1283 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); |
|
1284 |
|
1285 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
|
1286 RTL_R32(ERIDR) : ~0; |
|
1287 } |
|
1288 |
|
1289 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
|
1290 u32 m, int type) |
|
1291 { |
|
1292 u32 val; |
|
1293 |
|
1294 val = rtl_eri_read(tp, addr, type); |
|
1295 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); |
|
1296 } |
|
1297 |
|
1298 struct exgmac_reg { |
|
1299 u16 addr; |
|
1300 u16 mask; |
|
1301 u32 val; |
|
1302 }; |
|
1303 |
|
1304 static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
|
1305 const struct exgmac_reg *r, int len) |
|
1306 { |
|
1307 while (len-- > 0) { |
|
1308 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
|
1309 r++; |
|
1310 } |
|
1311 } |
|
1312 |
|
1313 DECLARE_RTL_COND(rtl_efusear_cond) |
|
1314 { |
|
1315 void __iomem *ioaddr = tp->mmio_addr; |
|
1316 |
|
1317 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG; |
|
1318 } |
|
1319 |
|
1320 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
|
1321 { |
|
1322 void __iomem *ioaddr = tp->mmio_addr; |
|
1323 |
|
1324 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
1325 |
|
1326 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
|
1327 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0; |
|
1328 } |
|
1329 |
|
1330 static u16 rtl_get_events(struct rtl8169_private *tp) |
|
1331 { |
|
1332 void __iomem *ioaddr = tp->mmio_addr; |
|
1333 |
|
1334 return RTL_R16(IntrStatus); |
|
1335 } |
|
1336 |
|
1337 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) |
|
1338 { |
|
1339 void __iomem *ioaddr = tp->mmio_addr; |
|
1340 |
|
1341 RTL_W16(IntrStatus, bits); |
|
1342 mmiowb(); |
|
1343 } |
|
1344 |
|
1345 static void rtl_irq_disable(struct rtl8169_private *tp) |
|
1346 { |
|
1347 void __iomem *ioaddr = tp->mmio_addr; |
|
1348 |
|
1349 RTL_W16(IntrMask, 0); |
|
1350 mmiowb(); |
|
1351 } |
|
1352 |
|
1353 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
|
1354 { |
|
1355 void __iomem *ioaddr = tp->mmio_addr; |
|
1356 |
|
1357 RTL_W16(IntrMask, bits); |
|
1358 } |
|
1359 |
|
1360 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
|
1361 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) |
|
1362 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) |
|
1363 |
|
1364 static void rtl_irq_enable_all(struct rtl8169_private *tp) |
|
1365 { |
|
1366 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1367 } |
|
1368 |
|
1369 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
|
1370 { |
|
1371 void __iomem *ioaddr = tp->mmio_addr; |
|
1372 |
|
1373 rtl_irq_disable(tp); |
|
1374 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1375 RTL_R8(ChipCmd); |
|
1376 } |
|
1377 |
|
1378 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
|
1379 { |
|
1380 void __iomem *ioaddr = tp->mmio_addr; |
|
1381 |
|
1382 return RTL_R32(TBICSR) & TBIReset; |
|
1383 } |
|
1384 |
|
1385 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
|
1386 { |
|
1387 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
|
1388 } |
|
1389 |
|
1390 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
1391 { |
|
1392 return RTL_R32(TBICSR) & TBILinkOk; |
|
1393 } |
|
1394 |
|
1395 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
1396 { |
|
1397 return RTL_R8(PHYstatus) & LinkStatus; |
|
1398 } |
|
1399 |
|
1400 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
|
1401 { |
|
1402 void __iomem *ioaddr = tp->mmio_addr; |
|
1403 |
|
1404 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
1405 } |
|
1406 |
|
1407 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
|
1408 { |
|
1409 unsigned int val; |
|
1410 |
|
1411 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
|
1412 rtl_writephy(tp, MII_BMCR, val & 0xffff); |
|
1413 } |
|
1414 |
|
1415 static void rtl_link_chg_patch(struct rtl8169_private *tp) |
|
1416 { |
|
1417 void __iomem *ioaddr = tp->mmio_addr; |
|
1418 struct net_device *dev = tp->dev; |
|
1419 |
|
1420 if (!netif_running(dev)) |
|
1421 return; |
|
1422 |
|
1423 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
|
1424 tp->mac_version == RTL_GIGA_MAC_VER_38) { |
|
1425 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1426 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
|
1427 ERIAR_EXGMAC); |
|
1428 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, |
|
1429 ERIAR_EXGMAC); |
|
1430 } else if (RTL_R8(PHYstatus) & _100bps) { |
|
1431 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
|
1432 ERIAR_EXGMAC); |
|
1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, |
|
1434 ERIAR_EXGMAC); |
|
1435 } else { |
|
1436 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
|
1437 ERIAR_EXGMAC); |
|
1438 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, |
|
1439 ERIAR_EXGMAC); |
|
1440 } |
|
1441 /* Reset packet filter */ |
|
1442 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
|
1443 ERIAR_EXGMAC); |
|
1444 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
|
1445 ERIAR_EXGMAC); |
|
1446 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
1447 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
1448 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1449 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
|
1450 ERIAR_EXGMAC); |
|
1451 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, |
|
1452 ERIAR_EXGMAC); |
|
1453 } else { |
|
1454 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
|
1455 ERIAR_EXGMAC); |
|
1456 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, |
|
1457 ERIAR_EXGMAC); |
|
1458 } |
|
1459 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
|
1460 if (RTL_R8(PHYstatus) & _10bps) { |
|
1461 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
|
1462 ERIAR_EXGMAC); |
|
1463 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, |
|
1464 ERIAR_EXGMAC); |
|
1465 } else { |
|
1466 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
|
1467 ERIAR_EXGMAC); |
|
1468 } |
|
1469 } |
|
1470 } |
|
1471 |
|
1472 static void __rtl8169_check_link_status(struct net_device *dev, |
|
1473 struct rtl8169_private *tp, |
|
1474 void __iomem *ioaddr, bool pm) |
|
1475 { |
|
1476 if (tp->link_ok(ioaddr)) { |
|
1477 rtl_link_chg_patch(tp); |
|
1478 /* This is to cancel a scheduled suspend if there's one. */ |
|
1479 if (pm) |
|
1480 pm_request_resume(&tp->pci_dev->dev); |
|
1481 netif_carrier_on(dev); |
|
1482 if (net_ratelimit()) |
|
1483 netif_info(tp, ifup, dev, "link up\n"); |
|
1484 } else { |
|
1485 netif_carrier_off(dev); |
|
1486 netif_info(tp, ifdown, dev, "link down\n"); |
|
1487 if (pm) |
|
1488 pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
|
1489 } |
|
1490 } |
|
1491 |
|
1492 static void rtl8169_check_link_status(struct net_device *dev, |
|
1493 struct rtl8169_private *tp, |
|
1494 void __iomem *ioaddr) |
|
1495 { |
|
1496 __rtl8169_check_link_status(dev, tp, ioaddr, false); |
|
1497 } |
|
1498 |
|
1499 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
1500 |
|
1501 static u32 __rtl8169_get_wol(struct rtl8169_private *tp) |
|
1502 { |
|
1503 void __iomem *ioaddr = tp->mmio_addr; |
|
1504 u8 options; |
|
1505 u32 wolopts = 0; |
|
1506 |
|
1507 options = RTL_R8(Config1); |
|
1508 if (!(options & PMEnable)) |
|
1509 return 0; |
|
1510 |
|
1511 options = RTL_R8(Config3); |
|
1512 if (options & LinkUp) |
|
1513 wolopts |= WAKE_PHY; |
|
1514 if (options & MagicPacket) |
|
1515 wolopts |= WAKE_MAGIC; |
|
1516 |
|
1517 options = RTL_R8(Config5); |
|
1518 if (options & UWF) |
|
1519 wolopts |= WAKE_UCAST; |
|
1520 if (options & BWF) |
|
1521 wolopts |= WAKE_BCAST; |
|
1522 if (options & MWF) |
|
1523 wolopts |= WAKE_MCAST; |
|
1524 |
|
1525 return wolopts; |
|
1526 } |
|
1527 |
|
1528 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1529 { |
|
1530 struct rtl8169_private *tp = netdev_priv(dev); |
|
1531 |
|
1532 rtl_lock_work(tp); |
|
1533 |
|
1534 wol->supported = WAKE_ANY; |
|
1535 wol->wolopts = __rtl8169_get_wol(tp); |
|
1536 |
|
1537 rtl_unlock_work(tp); |
|
1538 } |
|
1539 |
|
1540 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) |
|
1541 { |
|
1542 void __iomem *ioaddr = tp->mmio_addr; |
|
1543 unsigned int i; |
|
1544 static const struct { |
|
1545 u32 opt; |
|
1546 u16 reg; |
|
1547 u8 mask; |
|
1548 } cfg[] = { |
|
1549 { WAKE_PHY, Config3, LinkUp }, |
|
1550 { WAKE_MAGIC, Config3, MagicPacket }, |
|
1551 { WAKE_UCAST, Config5, UWF }, |
|
1552 { WAKE_BCAST, Config5, BWF }, |
|
1553 { WAKE_MCAST, Config5, MWF }, |
|
1554 { WAKE_ANY, Config5, LanWake } |
|
1555 }; |
|
1556 u8 options; |
|
1557 |
|
1558 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1559 |
|
1560 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
1561 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
1562 if (wolopts & cfg[i].opt) |
|
1563 options |= cfg[i].mask; |
|
1564 RTL_W8(cfg[i].reg, options); |
|
1565 } |
|
1566 |
|
1567 switch (tp->mac_version) { |
|
1568 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: |
|
1569 options = RTL_R8(Config1) & ~PMEnable; |
|
1570 if (wolopts) |
|
1571 options |= PMEnable; |
|
1572 RTL_W8(Config1, options); |
|
1573 break; |
|
1574 default: |
|
1575 options = RTL_R8(Config2) & ~PME_SIGNAL; |
|
1576 if (wolopts) |
|
1577 options |= PME_SIGNAL; |
|
1578 RTL_W8(Config2, options); |
|
1579 break; |
|
1580 } |
|
1581 |
|
1582 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1583 } |
|
1584 |
|
1585 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1586 { |
|
1587 struct rtl8169_private *tp = netdev_priv(dev); |
|
1588 |
|
1589 rtl_lock_work(tp); |
|
1590 |
|
1591 if (wol->wolopts) |
|
1592 tp->features |= RTL_FEATURE_WOL; |
|
1593 else |
|
1594 tp->features &= ~RTL_FEATURE_WOL; |
|
1595 __rtl8169_set_wol(tp, wol->wolopts); |
|
1596 |
|
1597 rtl_unlock_work(tp); |
|
1598 |
|
1599 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
1600 |
|
1601 return 0; |
|
1602 } |
|
1603 |
|
1604 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
|
1605 { |
|
1606 return rtl_chip_infos[tp->mac_version].fw_name; |
|
1607 } |
|
1608 |
|
1609 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
1610 struct ethtool_drvinfo *info) |
|
1611 { |
|
1612 struct rtl8169_private *tp = netdev_priv(dev); |
|
1613 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
1614 |
|
1615 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
|
1616 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); |
|
1617 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
|
1618 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
|
1619 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
1620 strlcpy(info->fw_version, rtl_fw->version, |
|
1621 sizeof(info->fw_version)); |
|
1622 } |
|
1623 |
|
1624 static int rtl8169_get_regs_len(struct net_device *dev) |
|
1625 { |
|
1626 return R8169_REGS_SIZE; |
|
1627 } |
|
1628 |
|
1629 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
1630 u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
|
1631 { |
|
1632 struct rtl8169_private *tp = netdev_priv(dev); |
|
1633 void __iomem *ioaddr = tp->mmio_addr; |
|
1634 int ret = 0; |
|
1635 u32 reg; |
|
1636 |
|
1637 reg = RTL_R32(TBICSR); |
|
1638 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
1639 (duplex == DUPLEX_FULL)) { |
|
1640 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
1641 } else if (autoneg == AUTONEG_ENABLE) |
|
1642 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
1643 else { |
|
1644 netif_warn(tp, link, dev, |
|
1645 "incorrect speed setting refused in TBI mode\n"); |
|
1646 ret = -EOPNOTSUPP; |
|
1647 } |
|
1648 |
|
1649 return ret; |
|
1650 } |
|
1651 |
|
1652 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
1653 u8 autoneg, u16 speed, u8 duplex, u32 adv) |
|
1654 { |
|
1655 struct rtl8169_private *tp = netdev_priv(dev); |
|
1656 int giga_ctrl, bmcr; |
|
1657 int rc = -EINVAL; |
|
1658 |
|
1659 rtl_writephy(tp, 0x1f, 0x0000); |
|
1660 |
|
1661 if (autoneg == AUTONEG_ENABLE) { |
|
1662 int auto_nego; |
|
1663 |
|
1664 auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
|
1665 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
1666 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
1667 |
|
1668 if (adv & ADVERTISED_10baseT_Half) |
|
1669 auto_nego |= ADVERTISE_10HALF; |
|
1670 if (adv & ADVERTISED_10baseT_Full) |
|
1671 auto_nego |= ADVERTISE_10FULL; |
|
1672 if (adv & ADVERTISED_100baseT_Half) |
|
1673 auto_nego |= ADVERTISE_100HALF; |
|
1674 if (adv & ADVERTISED_100baseT_Full) |
|
1675 auto_nego |= ADVERTISE_100FULL; |
|
1676 |
|
1677 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
1678 |
|
1679 giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
|
1680 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
1681 |
|
1682 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
1683 if (tp->mii.supports_gmii) { |
|
1684 if (adv & ADVERTISED_1000baseT_Half) |
|
1685 giga_ctrl |= ADVERTISE_1000HALF; |
|
1686 if (adv & ADVERTISED_1000baseT_Full) |
|
1687 giga_ctrl |= ADVERTISE_1000FULL; |
|
1688 } else if (adv & (ADVERTISED_1000baseT_Half | |
|
1689 ADVERTISED_1000baseT_Full)) { |
|
1690 netif_info(tp, link, dev, |
|
1691 "PHY does not support 1000Mbps\n"); |
|
1692 goto out; |
|
1693 } |
|
1694 |
|
1695 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
1696 |
|
1697 rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
|
1698 rtl_writephy(tp, MII_CTRL1000, giga_ctrl); |
|
1699 } else { |
|
1700 giga_ctrl = 0; |
|
1701 |
|
1702 if (speed == SPEED_10) |
|
1703 bmcr = 0; |
|
1704 else if (speed == SPEED_100) |
|
1705 bmcr = BMCR_SPEED100; |
|
1706 else |
|
1707 goto out; |
|
1708 |
|
1709 if (duplex == DUPLEX_FULL) |
|
1710 bmcr |= BMCR_FULLDPLX; |
|
1711 } |
|
1712 |
|
1713 rtl_writephy(tp, MII_BMCR, bmcr); |
|
1714 |
|
1715 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
1716 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
1717 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
1718 rtl_writephy(tp, 0x17, 0x2138); |
|
1719 rtl_writephy(tp, 0x0e, 0x0260); |
|
1720 } else { |
|
1721 rtl_writephy(tp, 0x17, 0x2108); |
|
1722 rtl_writephy(tp, 0x0e, 0x0000); |
|
1723 } |
|
1724 } |
|
1725 |
|
1726 rc = 0; |
|
1727 out: |
|
1728 return rc; |
|
1729 } |
|
1730 |
|
1731 static int rtl8169_set_speed(struct net_device *dev, |
|
1732 u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
|
1733 { |
|
1734 struct rtl8169_private *tp = netdev_priv(dev); |
|
1735 int ret; |
|
1736 |
|
1737 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
|
1738 if (ret < 0) |
|
1739 goto out; |
|
1740 |
|
1741 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
|
1742 (advertising & ADVERTISED_1000baseT_Full)) { |
|
1743 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1744 } |
|
1745 out: |
|
1746 return ret; |
|
1747 } |
|
1748 |
|
1749 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1750 { |
|
1751 struct rtl8169_private *tp = netdev_priv(dev); |
|
1752 int ret; |
|
1753 |
|
1754 del_timer_sync(&tp->timer); |
|
1755 |
|
1756 rtl_lock_work(tp); |
|
1757 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
|
1758 cmd->duplex, cmd->advertising); |
|
1759 rtl_unlock_work(tp); |
|
1760 |
|
1761 return ret; |
|
1762 } |
|
1763 |
|
1764 static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
|
1765 netdev_features_t features) |
|
1766 { |
|
1767 struct rtl8169_private *tp = netdev_priv(dev); |
|
1768 |
|
1769 if (dev->mtu > TD_MSS_MAX) |
|
1770 features &= ~NETIF_F_ALL_TSO; |
|
1771 |
|
1772 if (dev->mtu > JUMBO_1K && |
|
1773 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) |
|
1774 features &= ~NETIF_F_IP_CSUM; |
|
1775 |
|
1776 return features; |
|
1777 } |
|
1778 |
|
1779 static void __rtl8169_set_features(struct net_device *dev, |
|
1780 netdev_features_t features) |
|
1781 { |
|
1782 struct rtl8169_private *tp = netdev_priv(dev); |
|
1783 netdev_features_t changed = features ^ dev->features; |
|
1784 void __iomem *ioaddr = tp->mmio_addr; |
|
1785 |
|
1786 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX))) |
|
1787 return; |
|
1788 |
|
1789 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) { |
|
1790 if (features & NETIF_F_RXCSUM) |
|
1791 tp->cp_cmd |= RxChkSum; |
|
1792 else |
|
1793 tp->cp_cmd &= ~RxChkSum; |
|
1794 |
|
1795 if (dev->features & NETIF_F_HW_VLAN_RX) |
|
1796 tp->cp_cmd |= RxVlan; |
|
1797 else |
|
1798 tp->cp_cmd &= ~RxVlan; |
|
1799 |
|
1800 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1801 RTL_R16(CPlusCmd); |
|
1802 } |
|
1803 if (changed & NETIF_F_RXALL) { |
|
1804 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt)); |
|
1805 if (features & NETIF_F_RXALL) |
|
1806 tmp |= (AcceptErr | AcceptRunt); |
|
1807 RTL_W32(RxConfig, tmp); |
|
1808 } |
|
1809 } |
|
1810 |
|
1811 static int rtl8169_set_features(struct net_device *dev, |
|
1812 netdev_features_t features) |
|
1813 { |
|
1814 struct rtl8169_private *tp = netdev_priv(dev); |
|
1815 |
|
1816 rtl_lock_work(tp); |
|
1817 __rtl8169_set_features(dev, features); |
|
1818 rtl_unlock_work(tp); |
|
1819 |
|
1820 return 0; |
|
1821 } |
|
1822 |
|
1823 |
|
1824 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1825 struct sk_buff *skb) |
|
1826 { |
|
1827 return (vlan_tx_tag_present(skb)) ? |
|
1828 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1829 } |
|
1830 |
|
1831 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
|
1832 { |
|
1833 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1834 |
|
1835 if (opts2 & RxVlanTag) |
|
1836 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); |
|
1837 |
|
1838 desc->opts2 = 0; |
|
1839 } |
|
1840 |
|
1841 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1842 { |
|
1843 struct rtl8169_private *tp = netdev_priv(dev); |
|
1844 void __iomem *ioaddr = tp->mmio_addr; |
|
1845 u32 status; |
|
1846 |
|
1847 cmd->supported = |
|
1848 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1849 cmd->port = PORT_FIBRE; |
|
1850 cmd->transceiver = XCVR_INTERNAL; |
|
1851 |
|
1852 status = RTL_R32(TBICSR); |
|
1853 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1854 cmd->autoneg = !!(status & TBINwEnable); |
|
1855 |
|
1856 ethtool_cmd_speed_set(cmd, SPEED_1000); |
|
1857 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1858 |
|
1859 return 0; |
|
1860 } |
|
1861 |
|
1862 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1863 { |
|
1864 struct rtl8169_private *tp = netdev_priv(dev); |
|
1865 |
|
1866 return mii_ethtool_gset(&tp->mii, cmd); |
|
1867 } |
|
1868 |
|
1869 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1870 { |
|
1871 struct rtl8169_private *tp = netdev_priv(dev); |
|
1872 int rc; |
|
1873 |
|
1874 rtl_lock_work(tp); |
|
1875 rc = tp->get_settings(dev, cmd); |
|
1876 rtl_unlock_work(tp); |
|
1877 |
|
1878 return rc; |
|
1879 } |
|
1880 |
|
1881 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1882 void *p) |
|
1883 { |
|
1884 struct rtl8169_private *tp = netdev_priv(dev); |
|
1885 |
|
1886 if (regs->len > R8169_REGS_SIZE) |
|
1887 regs->len = R8169_REGS_SIZE; |
|
1888 |
|
1889 rtl_lock_work(tp); |
|
1890 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1891 rtl_unlock_work(tp); |
|
1892 } |
|
1893 |
|
1894 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1895 { |
|
1896 struct rtl8169_private *tp = netdev_priv(dev); |
|
1897 |
|
1898 return tp->msg_enable; |
|
1899 } |
|
1900 |
|
1901 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1902 { |
|
1903 struct rtl8169_private *tp = netdev_priv(dev); |
|
1904 |
|
1905 tp->msg_enable = value; |
|
1906 } |
|
1907 |
|
1908 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1909 "tx_packets", |
|
1910 "rx_packets", |
|
1911 "tx_errors", |
|
1912 "rx_errors", |
|
1913 "rx_missed", |
|
1914 "align_errors", |
|
1915 "tx_single_collisions", |
|
1916 "tx_multi_collisions", |
|
1917 "unicast", |
|
1918 "broadcast", |
|
1919 "multicast", |
|
1920 "tx_aborted", |
|
1921 "tx_underrun", |
|
1922 }; |
|
1923 |
|
1924 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1925 { |
|
1926 switch (sset) { |
|
1927 case ETH_SS_STATS: |
|
1928 return ARRAY_SIZE(rtl8169_gstrings); |
|
1929 default: |
|
1930 return -EOPNOTSUPP; |
|
1931 } |
|
1932 } |
|
1933 |
|
1934 DECLARE_RTL_COND(rtl_counters_cond) |
|
1935 { |
|
1936 void __iomem *ioaddr = tp->mmio_addr; |
|
1937 |
|
1938 return RTL_R32(CounterAddrLow) & CounterDump; |
|
1939 } |
|
1940 |
|
1941 static void rtl8169_update_counters(struct net_device *dev) |
|
1942 { |
|
1943 struct rtl8169_private *tp = netdev_priv(dev); |
|
1944 void __iomem *ioaddr = tp->mmio_addr; |
|
1945 struct device *d = &tp->pci_dev->dev; |
|
1946 struct rtl8169_counters *counters; |
|
1947 dma_addr_t paddr; |
|
1948 u32 cmd; |
|
1949 |
|
1950 /* |
|
1951 * Some chips are unable to dump tally counters when the receiver |
|
1952 * is disabled. |
|
1953 */ |
|
1954 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1955 return; |
|
1956 |
|
1957 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
|
1958 if (!counters) |
|
1959 return; |
|
1960 |
|
1961 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1962 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1963 RTL_W32(CounterAddrLow, cmd); |
|
1964 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1965 |
|
1966 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000)) |
|
1967 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1968 |
|
1969 RTL_W32(CounterAddrLow, 0); |
|
1970 RTL_W32(CounterAddrHigh, 0); |
|
1971 |
|
1972 dma_free_coherent(d, sizeof(*counters), counters, paddr); |
|
1973 } |
|
1974 |
|
1975 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1976 struct ethtool_stats *stats, u64 *data) |
|
1977 { |
|
1978 struct rtl8169_private *tp = netdev_priv(dev); |
|
1979 |
|
1980 ASSERT_RTNL(); |
|
1981 |
|
1982 rtl8169_update_counters(dev); |
|
1983 |
|
1984 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1985 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1986 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1987 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1988 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1989 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1990 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1991 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1992 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1993 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1994 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1995 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1996 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1997 } |
|
1998 |
|
1999 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
2000 { |
|
2001 switch(stringset) { |
|
2002 case ETH_SS_STATS: |
|
2003 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
2004 break; |
|
2005 } |
|
2006 } |
|
2007 |
|
2008 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
2009 .get_drvinfo = rtl8169_get_drvinfo, |
|
2010 .get_regs_len = rtl8169_get_regs_len, |
|
2011 .get_link = ethtool_op_get_link, |
|
2012 .get_settings = rtl8169_get_settings, |
|
2013 .set_settings = rtl8169_set_settings, |
|
2014 .get_msglevel = rtl8169_get_msglevel, |
|
2015 .set_msglevel = rtl8169_set_msglevel, |
|
2016 .get_regs = rtl8169_get_regs, |
|
2017 .get_wol = rtl8169_get_wol, |
|
2018 .set_wol = rtl8169_set_wol, |
|
2019 .get_strings = rtl8169_get_strings, |
|
2020 .get_sset_count = rtl8169_get_sset_count, |
|
2021 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
2022 .get_ts_info = ethtool_op_get_ts_info, |
|
2023 }; |
|
2024 |
|
2025 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
2026 struct net_device *dev, u8 default_version) |
|
2027 { |
|
2028 void __iomem *ioaddr = tp->mmio_addr; |
|
2029 /* |
|
2030 * The driver currently handles the 8168Bf and the 8168Be identically |
|
2031 * but they can be identified more specifically through the test below |
|
2032 * if needed: |
|
2033 * |
|
2034 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
2035 * |
|
2036 * Same thing for the 8101Eb and the 8101Ec: |
|
2037 * |
|
2038 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
2039 */ |
|
2040 static const struct rtl_mac_info { |
|
2041 u32 mask; |
|
2042 u32 val; |
|
2043 int mac_version; |
|
2044 } mac_info[] = { |
|
2045 /* 8168G family. */ |
|
2046 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 }, |
|
2047 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 }, |
|
2048 |
|
2049 /* 8168F family. */ |
|
2050 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
|
2051 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
|
2052 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, |
|
2053 |
|
2054 /* 8168E family. */ |
|
2055 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
|
2056 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
|
2057 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, |
|
2058 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, |
|
2059 |
|
2060 /* 8168D family. */ |
|
2061 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
2062 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
2063 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
2064 |
|
2065 /* 8168DP family. */ |
|
2066 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
2067 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, |
|
2068 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
|
2069 |
|
2070 /* 8168C family. */ |
|
2071 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
|
2072 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
2073 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
2074 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
2075 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
2076 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
2077 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
2078 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
2079 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
2080 |
|
2081 /* 8168B family. */ |
|
2082 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
2083 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
2084 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
2085 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
2086 |
|
2087 /* 8101 family. */ |
|
2088 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 }, |
|
2089 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, |
|
2090 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
|
2091 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
|
2092 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
|
2093 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, |
|
2094 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, |
|
2095 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
2096 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
2097 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
2098 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
2099 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
2100 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
2101 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
2102 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
2103 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
2104 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
2105 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
2106 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
2107 /* FIXME: where did these entries come from ? -- FR */ |
|
2108 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
2109 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
2110 |
|
2111 /* 8110 family. */ |
|
2112 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
2113 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
2114 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
2115 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
2116 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
2117 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
2118 |
|
2119 /* Catch-all */ |
|
2120 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
2121 }; |
|
2122 const struct rtl_mac_info *p = mac_info; |
|
2123 u32 reg; |
|
2124 |
|
2125 reg = RTL_R32(TxConfig); |
|
2126 while ((reg & p->mask) != p->val) |
|
2127 p++; |
|
2128 tp->mac_version = p->mac_version; |
|
2129 |
|
2130 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
2131 netif_notice(tp, probe, dev, |
|
2132 "unknown MAC, using family default\n"); |
|
2133 tp->mac_version = default_version; |
|
2134 } |
|
2135 } |
|
2136 |
|
2137 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
2138 { |
|
2139 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
2140 } |
|
2141 |
|
2142 struct phy_reg { |
|
2143 u16 reg; |
|
2144 u16 val; |
|
2145 }; |
|
2146 |
|
2147 static void rtl_writephy_batch(struct rtl8169_private *tp, |
|
2148 const struct phy_reg *regs, int len) |
|
2149 { |
|
2150 while (len-- > 0) { |
|
2151 rtl_writephy(tp, regs->reg, regs->val); |
|
2152 regs++; |
|
2153 } |
|
2154 } |
|
2155 |
|
2156 #define PHY_READ 0x00000000 |
|
2157 #define PHY_DATA_OR 0x10000000 |
|
2158 #define PHY_DATA_AND 0x20000000 |
|
2159 #define PHY_BJMPN 0x30000000 |
|
2160 #define PHY_READ_EFUSE 0x40000000 |
|
2161 #define PHY_READ_MAC_BYTE 0x50000000 |
|
2162 #define PHY_WRITE_MAC_BYTE 0x60000000 |
|
2163 #define PHY_CLEAR_READCOUNT 0x70000000 |
|
2164 #define PHY_WRITE 0x80000000 |
|
2165 #define PHY_READCOUNT_EQ_SKIP 0x90000000 |
|
2166 #define PHY_COMP_EQ_SKIPN 0xa0000000 |
|
2167 #define PHY_COMP_NEQ_SKIPN 0xb0000000 |
|
2168 #define PHY_WRITE_PREVIOUS 0xc0000000 |
|
2169 #define PHY_SKIPN 0xd0000000 |
|
2170 #define PHY_DELAY_MS 0xe0000000 |
|
2171 #define PHY_WRITE_ERI_WORD 0xf0000000 |
|
2172 |
|
2173 struct fw_info { |
|
2174 u32 magic; |
|
2175 char version[RTL_VER_SIZE]; |
|
2176 __le32 fw_start; |
|
2177 __le32 fw_len; |
|
2178 u8 chksum; |
|
2179 } __packed; |
|
2180 |
|
2181 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
|
2182 |
|
2183 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2184 { |
|
2185 const struct firmware *fw = rtl_fw->fw; |
|
2186 struct fw_info *fw_info = (struct fw_info *)fw->data; |
|
2187 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2188 char *version = rtl_fw->version; |
|
2189 bool rc = false; |
|
2190 |
|
2191 if (fw->size < FW_OPCODE_SIZE) |
|
2192 goto out; |
|
2193 |
|
2194 if (!fw_info->magic) { |
|
2195 size_t i, size, start; |
|
2196 u8 checksum = 0; |
|
2197 |
|
2198 if (fw->size < sizeof(*fw_info)) |
|
2199 goto out; |
|
2200 |
|
2201 for (i = 0; i < fw->size; i++) |
|
2202 checksum += fw->data[i]; |
|
2203 if (checksum != 0) |
|
2204 goto out; |
|
2205 |
|
2206 start = le32_to_cpu(fw_info->fw_start); |
|
2207 if (start > fw->size) |
|
2208 goto out; |
|
2209 |
|
2210 size = le32_to_cpu(fw_info->fw_len); |
|
2211 if (size > (fw->size - start) / FW_OPCODE_SIZE) |
|
2212 goto out; |
|
2213 |
|
2214 memcpy(version, fw_info->version, RTL_VER_SIZE); |
|
2215 |
|
2216 pa->code = (__le32 *)(fw->data + start); |
|
2217 pa->size = size; |
|
2218 } else { |
|
2219 if (fw->size % FW_OPCODE_SIZE) |
|
2220 goto out; |
|
2221 |
|
2222 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); |
|
2223 |
|
2224 pa->code = (__le32 *)fw->data; |
|
2225 pa->size = fw->size / FW_OPCODE_SIZE; |
|
2226 } |
|
2227 version[RTL_VER_SIZE - 1] = 0; |
|
2228 |
|
2229 rc = true; |
|
2230 out: |
|
2231 return rc; |
|
2232 } |
|
2233 |
|
2234 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
|
2235 struct rtl_fw_phy_action *pa) |
|
2236 { |
|
2237 bool rc = false; |
|
2238 size_t index; |
|
2239 |
|
2240 for (index = 0; index < pa->size; index++) { |
|
2241 u32 action = le32_to_cpu(pa->code[index]); |
|
2242 u32 regno = (action & 0x0fff0000) >> 16; |
|
2243 |
|
2244 switch(action & 0xf0000000) { |
|
2245 case PHY_READ: |
|
2246 case PHY_DATA_OR: |
|
2247 case PHY_DATA_AND: |
|
2248 case PHY_READ_EFUSE: |
|
2249 case PHY_CLEAR_READCOUNT: |
|
2250 case PHY_WRITE: |
|
2251 case PHY_WRITE_PREVIOUS: |
|
2252 case PHY_DELAY_MS: |
|
2253 break; |
|
2254 |
|
2255 case PHY_BJMPN: |
|
2256 if (regno > index) { |
|
2257 netif_err(tp, ifup, tp->dev, |
|
2258 "Out of range of firmware\n"); |
|
2259 goto out; |
|
2260 } |
|
2261 break; |
|
2262 case PHY_READCOUNT_EQ_SKIP: |
|
2263 if (index + 2 >= pa->size) { |
|
2264 netif_err(tp, ifup, tp->dev, |
|
2265 "Out of range of firmware\n"); |
|
2266 goto out; |
|
2267 } |
|
2268 break; |
|
2269 case PHY_COMP_EQ_SKIPN: |
|
2270 case PHY_COMP_NEQ_SKIPN: |
|
2271 case PHY_SKIPN: |
|
2272 if (index + 1 + regno >= pa->size) { |
|
2273 netif_err(tp, ifup, tp->dev, |
|
2274 "Out of range of firmware\n"); |
|
2275 goto out; |
|
2276 } |
|
2277 break; |
|
2278 |
|
2279 case PHY_READ_MAC_BYTE: |
|
2280 case PHY_WRITE_MAC_BYTE: |
|
2281 case PHY_WRITE_ERI_WORD: |
|
2282 default: |
|
2283 netif_err(tp, ifup, tp->dev, |
|
2284 "Invalid action 0x%08x\n", action); |
|
2285 goto out; |
|
2286 } |
|
2287 } |
|
2288 rc = true; |
|
2289 out: |
|
2290 return rc; |
|
2291 } |
|
2292 |
|
2293 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2294 { |
|
2295 struct net_device *dev = tp->dev; |
|
2296 int rc = -EINVAL; |
|
2297 |
|
2298 if (!rtl_fw_format_ok(tp, rtl_fw)) { |
|
2299 netif_err(tp, ifup, dev, "invalid firwmare\n"); |
|
2300 goto out; |
|
2301 } |
|
2302 |
|
2303 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) |
|
2304 rc = 0; |
|
2305 out: |
|
2306 return rc; |
|
2307 } |
|
2308 |
|
2309 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2310 { |
|
2311 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2312 u32 predata, count; |
|
2313 size_t index; |
|
2314 |
|
2315 predata = count = 0; |
|
2316 |
|
2317 for (index = 0; index < pa->size; ) { |
|
2318 u32 action = le32_to_cpu(pa->code[index]); |
|
2319 u32 data = action & 0x0000ffff; |
|
2320 u32 regno = (action & 0x0fff0000) >> 16; |
|
2321 |
|
2322 if (!action) |
|
2323 break; |
|
2324 |
|
2325 switch(action & 0xf0000000) { |
|
2326 case PHY_READ: |
|
2327 predata = rtl_readphy(tp, regno); |
|
2328 count++; |
|
2329 index++; |
|
2330 break; |
|
2331 case PHY_DATA_OR: |
|
2332 predata |= data; |
|
2333 index++; |
|
2334 break; |
|
2335 case PHY_DATA_AND: |
|
2336 predata &= data; |
|
2337 index++; |
|
2338 break; |
|
2339 case PHY_BJMPN: |
|
2340 index -= regno; |
|
2341 break; |
|
2342 case PHY_READ_EFUSE: |
|
2343 predata = rtl8168d_efuse_read(tp, regno); |
|
2344 index++; |
|
2345 break; |
|
2346 case PHY_CLEAR_READCOUNT: |
|
2347 count = 0; |
|
2348 index++; |
|
2349 break; |
|
2350 case PHY_WRITE: |
|
2351 rtl_writephy(tp, regno, data); |
|
2352 index++; |
|
2353 break; |
|
2354 case PHY_READCOUNT_EQ_SKIP: |
|
2355 index += (count == data) ? 2 : 1; |
|
2356 break; |
|
2357 case PHY_COMP_EQ_SKIPN: |
|
2358 if (predata == data) |
|
2359 index += regno; |
|
2360 index++; |
|
2361 break; |
|
2362 case PHY_COMP_NEQ_SKIPN: |
|
2363 if (predata != data) |
|
2364 index += regno; |
|
2365 index++; |
|
2366 break; |
|
2367 case PHY_WRITE_PREVIOUS: |
|
2368 rtl_writephy(tp, regno, predata); |
|
2369 index++; |
|
2370 break; |
|
2371 case PHY_SKIPN: |
|
2372 index += regno + 1; |
|
2373 break; |
|
2374 case PHY_DELAY_MS: |
|
2375 mdelay(data); |
|
2376 index++; |
|
2377 break; |
|
2378 |
|
2379 case PHY_READ_MAC_BYTE: |
|
2380 case PHY_WRITE_MAC_BYTE: |
|
2381 case PHY_WRITE_ERI_WORD: |
|
2382 default: |
|
2383 BUG(); |
|
2384 } |
|
2385 } |
|
2386 } |
|
2387 |
|
2388 static void rtl_release_firmware(struct rtl8169_private *tp) |
|
2389 { |
|
2390 if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
|
2391 release_firmware(tp->rtl_fw->fw); |
|
2392 kfree(tp->rtl_fw); |
|
2393 } |
|
2394 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
2395 } |
|
2396 |
|
2397 static void rtl_apply_firmware(struct rtl8169_private *tp) |
|
2398 { |
|
2399 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
2400 |
|
2401 /* TODO: release firmware once rtl_phy_write_fw signals failures. */ |
|
2402 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
2403 rtl_phy_write_fw(tp, rtl_fw); |
|
2404 } |
|
2405 |
|
2406 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) |
|
2407 { |
|
2408 if (rtl_readphy(tp, reg) != val) |
|
2409 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); |
|
2410 else |
|
2411 rtl_apply_firmware(tp); |
|
2412 } |
|
2413 |
|
2414 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
|
2415 { |
|
2416 static const struct phy_reg phy_reg_init[] = { |
|
2417 { 0x1f, 0x0001 }, |
|
2418 { 0x06, 0x006e }, |
|
2419 { 0x08, 0x0708 }, |
|
2420 { 0x15, 0x4000 }, |
|
2421 { 0x18, 0x65c7 }, |
|
2422 |
|
2423 { 0x1f, 0x0001 }, |
|
2424 { 0x03, 0x00a1 }, |
|
2425 { 0x02, 0x0008 }, |
|
2426 { 0x01, 0x0120 }, |
|
2427 { 0x00, 0x1000 }, |
|
2428 { 0x04, 0x0800 }, |
|
2429 { 0x04, 0x0000 }, |
|
2430 |
|
2431 { 0x03, 0xff41 }, |
|
2432 { 0x02, 0xdf60 }, |
|
2433 { 0x01, 0x0140 }, |
|
2434 { 0x00, 0x0077 }, |
|
2435 { 0x04, 0x7800 }, |
|
2436 { 0x04, 0x7000 }, |
|
2437 |
|
2438 { 0x03, 0x802f }, |
|
2439 { 0x02, 0x4f02 }, |
|
2440 { 0x01, 0x0409 }, |
|
2441 { 0x00, 0xf0f9 }, |
|
2442 { 0x04, 0x9800 }, |
|
2443 { 0x04, 0x9000 }, |
|
2444 |
|
2445 { 0x03, 0xdf01 }, |
|
2446 { 0x02, 0xdf20 }, |
|
2447 { 0x01, 0xff95 }, |
|
2448 { 0x00, 0xba00 }, |
|
2449 { 0x04, 0xa800 }, |
|
2450 { 0x04, 0xa000 }, |
|
2451 |
|
2452 { 0x03, 0xff41 }, |
|
2453 { 0x02, 0xdf20 }, |
|
2454 { 0x01, 0x0140 }, |
|
2455 { 0x00, 0x00bb }, |
|
2456 { 0x04, 0xb800 }, |
|
2457 { 0x04, 0xb000 }, |
|
2458 |
|
2459 { 0x03, 0xdf41 }, |
|
2460 { 0x02, 0xdc60 }, |
|
2461 { 0x01, 0x6340 }, |
|
2462 { 0x00, 0x007d }, |
|
2463 { 0x04, 0xd800 }, |
|
2464 { 0x04, 0xd000 }, |
|
2465 |
|
2466 { 0x03, 0xdf01 }, |
|
2467 { 0x02, 0xdf20 }, |
|
2468 { 0x01, 0x100a }, |
|
2469 { 0x00, 0xa0ff }, |
|
2470 { 0x04, 0xf800 }, |
|
2471 { 0x04, 0xf000 }, |
|
2472 |
|
2473 { 0x1f, 0x0000 }, |
|
2474 { 0x0b, 0x0000 }, |
|
2475 { 0x00, 0x9200 } |
|
2476 }; |
|
2477 |
|
2478 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2479 } |
|
2480 |
|
2481 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
|
2482 { |
|
2483 static const struct phy_reg phy_reg_init[] = { |
|
2484 { 0x1f, 0x0002 }, |
|
2485 { 0x01, 0x90d0 }, |
|
2486 { 0x1f, 0x0000 } |
|
2487 }; |
|
2488 |
|
2489 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2490 } |
|
2491 |
|
2492 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
|
2493 { |
|
2494 struct pci_dev *pdev = tp->pci_dev; |
|
2495 |
|
2496 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
|
2497 (pdev->subsystem_device != 0xe000)) |
|
2498 return; |
|
2499 |
|
2500 rtl_writephy(tp, 0x1f, 0x0001); |
|
2501 rtl_writephy(tp, 0x10, 0xf01b); |
|
2502 rtl_writephy(tp, 0x1f, 0x0000); |
|
2503 } |
|
2504 |
|
2505 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
|
2506 { |
|
2507 static const struct phy_reg phy_reg_init[] = { |
|
2508 { 0x1f, 0x0001 }, |
|
2509 { 0x04, 0x0000 }, |
|
2510 { 0x03, 0x00a1 }, |
|
2511 { 0x02, 0x0008 }, |
|
2512 { 0x01, 0x0120 }, |
|
2513 { 0x00, 0x1000 }, |
|
2514 { 0x04, 0x0800 }, |
|
2515 { 0x04, 0x9000 }, |
|
2516 { 0x03, 0x802f }, |
|
2517 { 0x02, 0x4f02 }, |
|
2518 { 0x01, 0x0409 }, |
|
2519 { 0x00, 0xf099 }, |
|
2520 { 0x04, 0x9800 }, |
|
2521 { 0x04, 0xa000 }, |
|
2522 { 0x03, 0xdf01 }, |
|
2523 { 0x02, 0xdf20 }, |
|
2524 { 0x01, 0xff95 }, |
|
2525 { 0x00, 0xba00 }, |
|
2526 { 0x04, 0xa800 }, |
|
2527 { 0x04, 0xf000 }, |
|
2528 { 0x03, 0xdf01 }, |
|
2529 { 0x02, 0xdf20 }, |
|
2530 { 0x01, 0x101a }, |
|
2531 { 0x00, 0xa0ff }, |
|
2532 { 0x04, 0xf800 }, |
|
2533 { 0x04, 0x0000 }, |
|
2534 { 0x1f, 0x0000 }, |
|
2535 |
|
2536 { 0x1f, 0x0001 }, |
|
2537 { 0x10, 0xf41b }, |
|
2538 { 0x14, 0xfb54 }, |
|
2539 { 0x18, 0xf5c7 }, |
|
2540 { 0x1f, 0x0000 }, |
|
2541 |
|
2542 { 0x1f, 0x0001 }, |
|
2543 { 0x17, 0x0cc0 }, |
|
2544 { 0x1f, 0x0000 } |
|
2545 }; |
|
2546 |
|
2547 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2548 |
|
2549 rtl8169scd_hw_phy_config_quirk(tp); |
|
2550 } |
|
2551 |
|
2552 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
|
2553 { |
|
2554 static const struct phy_reg phy_reg_init[] = { |
|
2555 { 0x1f, 0x0001 }, |
|
2556 { 0x04, 0x0000 }, |
|
2557 { 0x03, 0x00a1 }, |
|
2558 { 0x02, 0x0008 }, |
|
2559 { 0x01, 0x0120 }, |
|
2560 { 0x00, 0x1000 }, |
|
2561 { 0x04, 0x0800 }, |
|
2562 { 0x04, 0x9000 }, |
|
2563 { 0x03, 0x802f }, |
|
2564 { 0x02, 0x4f02 }, |
|
2565 { 0x01, 0x0409 }, |
|
2566 { 0x00, 0xf099 }, |
|
2567 { 0x04, 0x9800 }, |
|
2568 { 0x04, 0xa000 }, |
|
2569 { 0x03, 0xdf01 }, |
|
2570 { 0x02, 0xdf20 }, |
|
2571 { 0x01, 0xff95 }, |
|
2572 { 0x00, 0xba00 }, |
|
2573 { 0x04, 0xa800 }, |
|
2574 { 0x04, 0xf000 }, |
|
2575 { 0x03, 0xdf01 }, |
|
2576 { 0x02, 0xdf20 }, |
|
2577 { 0x01, 0x101a }, |
|
2578 { 0x00, 0xa0ff }, |
|
2579 { 0x04, 0xf800 }, |
|
2580 { 0x04, 0x0000 }, |
|
2581 { 0x1f, 0x0000 }, |
|
2582 |
|
2583 { 0x1f, 0x0001 }, |
|
2584 { 0x0b, 0x8480 }, |
|
2585 { 0x1f, 0x0000 }, |
|
2586 |
|
2587 { 0x1f, 0x0001 }, |
|
2588 { 0x18, 0x67c7 }, |
|
2589 { 0x04, 0x2000 }, |
|
2590 { 0x03, 0x002f }, |
|
2591 { 0x02, 0x4360 }, |
|
2592 { 0x01, 0x0109 }, |
|
2593 { 0x00, 0x3022 }, |
|
2594 { 0x04, 0x2800 }, |
|
2595 { 0x1f, 0x0000 }, |
|
2596 |
|
2597 { 0x1f, 0x0001 }, |
|
2598 { 0x17, 0x0cc0 }, |
|
2599 { 0x1f, 0x0000 } |
|
2600 }; |
|
2601 |
|
2602 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2603 } |
|
2604 |
|
2605 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
|
2606 { |
|
2607 static const struct phy_reg phy_reg_init[] = { |
|
2608 { 0x10, 0xf41b }, |
|
2609 { 0x1f, 0x0000 } |
|
2610 }; |
|
2611 |
|
2612 rtl_writephy(tp, 0x1f, 0x0001); |
|
2613 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2614 |
|
2615 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2616 } |
|
2617 |
|
2618 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
|
2619 { |
|
2620 static const struct phy_reg phy_reg_init[] = { |
|
2621 { 0x1f, 0x0001 }, |
|
2622 { 0x10, 0xf41b }, |
|
2623 { 0x1f, 0x0000 } |
|
2624 }; |
|
2625 |
|
2626 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2627 } |
|
2628 |
|
2629 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
|
2630 { |
|
2631 static const struct phy_reg phy_reg_init[] = { |
|
2632 { 0x1f, 0x0000 }, |
|
2633 { 0x1d, 0x0f00 }, |
|
2634 { 0x1f, 0x0002 }, |
|
2635 { 0x0c, 0x1ec8 }, |
|
2636 { 0x1f, 0x0000 } |
|
2637 }; |
|
2638 |
|
2639 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2640 } |
|
2641 |
|
2642 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
|
2643 { |
|
2644 static const struct phy_reg phy_reg_init[] = { |
|
2645 { 0x1f, 0x0001 }, |
|
2646 { 0x1d, 0x3d98 }, |
|
2647 { 0x1f, 0x0000 } |
|
2648 }; |
|
2649 |
|
2650 rtl_writephy(tp, 0x1f, 0x0000); |
|
2651 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2652 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2653 |
|
2654 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2655 } |
|
2656 |
|
2657 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
|
2658 { |
|
2659 static const struct phy_reg phy_reg_init[] = { |
|
2660 { 0x1f, 0x0001 }, |
|
2661 { 0x12, 0x2300 }, |
|
2662 { 0x1f, 0x0002 }, |
|
2663 { 0x00, 0x88d4 }, |
|
2664 { 0x01, 0x82b1 }, |
|
2665 { 0x03, 0x7002 }, |
|
2666 { 0x08, 0x9e30 }, |
|
2667 { 0x09, 0x01f0 }, |
|
2668 { 0x0a, 0x5500 }, |
|
2669 { 0x0c, 0x00c8 }, |
|
2670 { 0x1f, 0x0003 }, |
|
2671 { 0x12, 0xc096 }, |
|
2672 { 0x16, 0x000a }, |
|
2673 { 0x1f, 0x0000 }, |
|
2674 { 0x1f, 0x0000 }, |
|
2675 { 0x09, 0x2000 }, |
|
2676 { 0x09, 0x0000 } |
|
2677 }; |
|
2678 |
|
2679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2680 |
|
2681 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2682 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2683 rtl_writephy(tp, 0x1f, 0x0000); |
|
2684 } |
|
2685 |
|
2686 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
|
2687 { |
|
2688 static const struct phy_reg phy_reg_init[] = { |
|
2689 { 0x1f, 0x0001 }, |
|
2690 { 0x12, 0x2300 }, |
|
2691 { 0x03, 0x802f }, |
|
2692 { 0x02, 0x4f02 }, |
|
2693 { 0x01, 0x0409 }, |
|
2694 { 0x00, 0xf099 }, |
|
2695 { 0x04, 0x9800 }, |
|
2696 { 0x04, 0x9000 }, |
|
2697 { 0x1d, 0x3d98 }, |
|
2698 { 0x1f, 0x0002 }, |
|
2699 { 0x0c, 0x7eb8 }, |
|
2700 { 0x06, 0x0761 }, |
|
2701 { 0x1f, 0x0003 }, |
|
2702 { 0x16, 0x0f0a }, |
|
2703 { 0x1f, 0x0000 } |
|
2704 }; |
|
2705 |
|
2706 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2707 |
|
2708 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2709 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2710 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2711 rtl_writephy(tp, 0x1f, 0x0000); |
|
2712 } |
|
2713 |
|
2714 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
|
2715 { |
|
2716 static const struct phy_reg phy_reg_init[] = { |
|
2717 { 0x1f, 0x0001 }, |
|
2718 { 0x12, 0x2300 }, |
|
2719 { 0x1d, 0x3d98 }, |
|
2720 { 0x1f, 0x0002 }, |
|
2721 { 0x0c, 0x7eb8 }, |
|
2722 { 0x06, 0x5461 }, |
|
2723 { 0x1f, 0x0003 }, |
|
2724 { 0x16, 0x0f0a }, |
|
2725 { 0x1f, 0x0000 } |
|
2726 }; |
|
2727 |
|
2728 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2729 |
|
2730 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2731 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2732 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2733 rtl_writephy(tp, 0x1f, 0x0000); |
|
2734 } |
|
2735 |
|
2736 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
|
2737 { |
|
2738 rtl8168c_3_hw_phy_config(tp); |
|
2739 } |
|
2740 |
|
2741 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
|
2742 { |
|
2743 static const struct phy_reg phy_reg_init_0[] = { |
|
2744 /* Channel Estimation */ |
|
2745 { 0x1f, 0x0001 }, |
|
2746 { 0x06, 0x4064 }, |
|
2747 { 0x07, 0x2863 }, |
|
2748 { 0x08, 0x059c }, |
|
2749 { 0x09, 0x26b4 }, |
|
2750 { 0x0a, 0x6a19 }, |
|
2751 { 0x0b, 0xdcc8 }, |
|
2752 { 0x10, 0xf06d }, |
|
2753 { 0x14, 0x7f68 }, |
|
2754 { 0x18, 0x7fd9 }, |
|
2755 { 0x1c, 0xf0ff }, |
|
2756 { 0x1d, 0x3d9c }, |
|
2757 { 0x1f, 0x0003 }, |
|
2758 { 0x12, 0xf49f }, |
|
2759 { 0x13, 0x070b }, |
|
2760 { 0x1a, 0x05ad }, |
|
2761 { 0x14, 0x94c0 }, |
|
2762 |
|
2763 /* |
|
2764 * Tx Error Issue |
|
2765 * Enhance line driver power |
|
2766 */ |
|
2767 { 0x1f, 0x0002 }, |
|
2768 { 0x06, 0x5561 }, |
|
2769 { 0x1f, 0x0005 }, |
|
2770 { 0x05, 0x8332 }, |
|
2771 { 0x06, 0x5561 }, |
|
2772 |
|
2773 /* |
|
2774 * Can not link to 1Gbps with bad cable |
|
2775 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2776 */ |
|
2777 { 0x1f, 0x0001 }, |
|
2778 { 0x17, 0x0cc0 }, |
|
2779 |
|
2780 { 0x1f, 0x0000 }, |
|
2781 { 0x0d, 0xf880 } |
|
2782 }; |
|
2783 |
|
2784 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2785 |
|
2786 /* |
|
2787 * Rx Error Issue |
|
2788 * Fine Tune Switching regulator parameter |
|
2789 */ |
|
2790 rtl_writephy(tp, 0x1f, 0x0002); |
|
2791 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); |
|
2792 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); |
|
2793 |
|
2794 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
|
2795 static const struct phy_reg phy_reg_init[] = { |
|
2796 { 0x1f, 0x0002 }, |
|
2797 { 0x05, 0x669a }, |
|
2798 { 0x1f, 0x0005 }, |
|
2799 { 0x05, 0x8330 }, |
|
2800 { 0x06, 0x669a }, |
|
2801 { 0x1f, 0x0002 } |
|
2802 }; |
|
2803 int val; |
|
2804 |
|
2805 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2806 |
|
2807 val = rtl_readphy(tp, 0x0d); |
|
2808 |
|
2809 if ((val & 0x00ff) != 0x006c) { |
|
2810 static const u32 set[] = { |
|
2811 0x0065, 0x0066, 0x0067, 0x0068, |
|
2812 0x0069, 0x006a, 0x006b, 0x006c |
|
2813 }; |
|
2814 int i; |
|
2815 |
|
2816 rtl_writephy(tp, 0x1f, 0x0002); |
|
2817 |
|
2818 val &= 0xff00; |
|
2819 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2820 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2821 } |
|
2822 } else { |
|
2823 static const struct phy_reg phy_reg_init[] = { |
|
2824 { 0x1f, 0x0002 }, |
|
2825 { 0x05, 0x6662 }, |
|
2826 { 0x1f, 0x0005 }, |
|
2827 { 0x05, 0x8330 }, |
|
2828 { 0x06, 0x6662 } |
|
2829 }; |
|
2830 |
|
2831 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2832 } |
|
2833 |
|
2834 /* RSET couple improve */ |
|
2835 rtl_writephy(tp, 0x1f, 0x0002); |
|
2836 rtl_patchphy(tp, 0x0d, 0x0300); |
|
2837 rtl_patchphy(tp, 0x0f, 0x0010); |
|
2838 |
|
2839 /* Fine tune PLL performance */ |
|
2840 rtl_writephy(tp, 0x1f, 0x0002); |
|
2841 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2842 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2843 |
|
2844 rtl_writephy(tp, 0x1f, 0x0005); |
|
2845 rtl_writephy(tp, 0x05, 0x001b); |
|
2846 |
|
2847 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); |
|
2848 |
|
2849 rtl_writephy(tp, 0x1f, 0x0000); |
|
2850 } |
|
2851 |
|
2852 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
|
2853 { |
|
2854 static const struct phy_reg phy_reg_init_0[] = { |
|
2855 /* Channel Estimation */ |
|
2856 { 0x1f, 0x0001 }, |
|
2857 { 0x06, 0x4064 }, |
|
2858 { 0x07, 0x2863 }, |
|
2859 { 0x08, 0x059c }, |
|
2860 { 0x09, 0x26b4 }, |
|
2861 { 0x0a, 0x6a19 }, |
|
2862 { 0x0b, 0xdcc8 }, |
|
2863 { 0x10, 0xf06d }, |
|
2864 { 0x14, 0x7f68 }, |
|
2865 { 0x18, 0x7fd9 }, |
|
2866 { 0x1c, 0xf0ff }, |
|
2867 { 0x1d, 0x3d9c }, |
|
2868 { 0x1f, 0x0003 }, |
|
2869 { 0x12, 0xf49f }, |
|
2870 { 0x13, 0x070b }, |
|
2871 { 0x1a, 0x05ad }, |
|
2872 { 0x14, 0x94c0 }, |
|
2873 |
|
2874 /* |
|
2875 * Tx Error Issue |
|
2876 * Enhance line driver power |
|
2877 */ |
|
2878 { 0x1f, 0x0002 }, |
|
2879 { 0x06, 0x5561 }, |
|
2880 { 0x1f, 0x0005 }, |
|
2881 { 0x05, 0x8332 }, |
|
2882 { 0x06, 0x5561 }, |
|
2883 |
|
2884 /* |
|
2885 * Can not link to 1Gbps with bad cable |
|
2886 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2887 */ |
|
2888 { 0x1f, 0x0001 }, |
|
2889 { 0x17, 0x0cc0 }, |
|
2890 |
|
2891 { 0x1f, 0x0000 }, |
|
2892 { 0x0d, 0xf880 } |
|
2893 }; |
|
2894 |
|
2895 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2896 |
|
2897 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
|
2898 static const struct phy_reg phy_reg_init[] = { |
|
2899 { 0x1f, 0x0002 }, |
|
2900 { 0x05, 0x669a }, |
|
2901 { 0x1f, 0x0005 }, |
|
2902 { 0x05, 0x8330 }, |
|
2903 { 0x06, 0x669a }, |
|
2904 |
|
2905 { 0x1f, 0x0002 } |
|
2906 }; |
|
2907 int val; |
|
2908 |
|
2909 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2910 |
|
2911 val = rtl_readphy(tp, 0x0d); |
|
2912 if ((val & 0x00ff) != 0x006c) { |
|
2913 static const u32 set[] = { |
|
2914 0x0065, 0x0066, 0x0067, 0x0068, |
|
2915 0x0069, 0x006a, 0x006b, 0x006c |
|
2916 }; |
|
2917 int i; |
|
2918 |
|
2919 rtl_writephy(tp, 0x1f, 0x0002); |
|
2920 |
|
2921 val &= 0xff00; |
|
2922 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2923 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2924 } |
|
2925 } else { |
|
2926 static const struct phy_reg phy_reg_init[] = { |
|
2927 { 0x1f, 0x0002 }, |
|
2928 { 0x05, 0x2642 }, |
|
2929 { 0x1f, 0x0005 }, |
|
2930 { 0x05, 0x8330 }, |
|
2931 { 0x06, 0x2642 } |
|
2932 }; |
|
2933 |
|
2934 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2935 } |
|
2936 |
|
2937 /* Fine tune PLL performance */ |
|
2938 rtl_writephy(tp, 0x1f, 0x0002); |
|
2939 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2940 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2941 |
|
2942 /* Switching regulator Slew rate */ |
|
2943 rtl_writephy(tp, 0x1f, 0x0002); |
|
2944 rtl_patchphy(tp, 0x0f, 0x0017); |
|
2945 |
|
2946 rtl_writephy(tp, 0x1f, 0x0005); |
|
2947 rtl_writephy(tp, 0x05, 0x001b); |
|
2948 |
|
2949 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); |
|
2950 |
|
2951 rtl_writephy(tp, 0x1f, 0x0000); |
|
2952 } |
|
2953 |
|
2954 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
|
2955 { |
|
2956 static const struct phy_reg phy_reg_init[] = { |
|
2957 { 0x1f, 0x0002 }, |
|
2958 { 0x10, 0x0008 }, |
|
2959 { 0x0d, 0x006c }, |
|
2960 |
|
2961 { 0x1f, 0x0000 }, |
|
2962 { 0x0d, 0xf880 }, |
|
2963 |
|
2964 { 0x1f, 0x0001 }, |
|
2965 { 0x17, 0x0cc0 }, |
|
2966 |
|
2967 { 0x1f, 0x0001 }, |
|
2968 { 0x0b, 0xa4d8 }, |
|
2969 { 0x09, 0x281c }, |
|
2970 { 0x07, 0x2883 }, |
|
2971 { 0x0a, 0x6b35 }, |
|
2972 { 0x1d, 0x3da4 }, |
|
2973 { 0x1c, 0xeffd }, |
|
2974 { 0x14, 0x7f52 }, |
|
2975 { 0x18, 0x7fc6 }, |
|
2976 { 0x08, 0x0601 }, |
|
2977 { 0x06, 0x4063 }, |
|
2978 { 0x10, 0xf074 }, |
|
2979 { 0x1f, 0x0003 }, |
|
2980 { 0x13, 0x0789 }, |
|
2981 { 0x12, 0xf4bd }, |
|
2982 { 0x1a, 0x04fd }, |
|
2983 { 0x14, 0x84b0 }, |
|
2984 { 0x1f, 0x0000 }, |
|
2985 { 0x00, 0x9200 }, |
|
2986 |
|
2987 { 0x1f, 0x0005 }, |
|
2988 { 0x01, 0x0340 }, |
|
2989 { 0x1f, 0x0001 }, |
|
2990 { 0x04, 0x4000 }, |
|
2991 { 0x03, 0x1d21 }, |
|
2992 { 0x02, 0x0c32 }, |
|
2993 { 0x01, 0x0200 }, |
|
2994 { 0x00, 0x5554 }, |
|
2995 { 0x04, 0x4800 }, |
|
2996 { 0x04, 0x4000 }, |
|
2997 { 0x04, 0xf000 }, |
|
2998 { 0x03, 0xdf01 }, |
|
2999 { 0x02, 0xdf20 }, |
|
3000 { 0x01, 0x101a }, |
|
3001 { 0x00, 0xa0ff }, |
|
3002 { 0x04, 0xf800 }, |
|
3003 { 0x04, 0xf000 }, |
|
3004 { 0x1f, 0x0000 }, |
|
3005 |
|
3006 { 0x1f, 0x0007 }, |
|
3007 { 0x1e, 0x0023 }, |
|
3008 { 0x16, 0x0000 }, |
|
3009 { 0x1f, 0x0000 } |
|
3010 }; |
|
3011 |
|
3012 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3013 } |
|
3014 |
|
3015 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
|
3016 { |
|
3017 static const struct phy_reg phy_reg_init[] = { |
|
3018 { 0x1f, 0x0001 }, |
|
3019 { 0x17, 0x0cc0 }, |
|
3020 |
|
3021 { 0x1f, 0x0007 }, |
|
3022 { 0x1e, 0x002d }, |
|
3023 { 0x18, 0x0040 }, |
|
3024 { 0x1f, 0x0000 } |
|
3025 }; |
|
3026 |
|
3027 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3028 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
3029 } |
|
3030 |
|
3031 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
|
3032 { |
|
3033 static const struct phy_reg phy_reg_init[] = { |
|
3034 /* Enable Delay cap */ |
|
3035 { 0x1f, 0x0005 }, |
|
3036 { 0x05, 0x8b80 }, |
|
3037 { 0x06, 0xc896 }, |
|
3038 { 0x1f, 0x0000 }, |
|
3039 |
|
3040 /* Channel estimation fine tune */ |
|
3041 { 0x1f, 0x0001 }, |
|
3042 { 0x0b, 0x6c20 }, |
|
3043 { 0x07, 0x2872 }, |
|
3044 { 0x1c, 0xefff }, |
|
3045 { 0x1f, 0x0003 }, |
|
3046 { 0x14, 0x6420 }, |
|
3047 { 0x1f, 0x0000 }, |
|
3048 |
|
3049 /* Update PFM & 10M TX idle timer */ |
|
3050 { 0x1f, 0x0007 }, |
|
3051 { 0x1e, 0x002f }, |
|
3052 { 0x15, 0x1919 }, |
|
3053 { 0x1f, 0x0000 }, |
|
3054 |
|
3055 { 0x1f, 0x0007 }, |
|
3056 { 0x1e, 0x00ac }, |
|
3057 { 0x18, 0x0006 }, |
|
3058 { 0x1f, 0x0000 } |
|
3059 }; |
|
3060 |
|
3061 rtl_apply_firmware(tp); |
|
3062 |
|
3063 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3064 |
|
3065 /* DCO enable for 10M IDLE Power */ |
|
3066 rtl_writephy(tp, 0x1f, 0x0007); |
|
3067 rtl_writephy(tp, 0x1e, 0x0023); |
|
3068 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
3069 rtl_writephy(tp, 0x1f, 0x0000); |
|
3070 |
|
3071 /* For impedance matching */ |
|
3072 rtl_writephy(tp, 0x1f, 0x0002); |
|
3073 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); |
|
3074 rtl_writephy(tp, 0x1f, 0x0000); |
|
3075 |
|
3076 /* PHY auto speed down */ |
|
3077 rtl_writephy(tp, 0x1f, 0x0007); |
|
3078 rtl_writephy(tp, 0x1e, 0x002d); |
|
3079 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); |
|
3080 rtl_writephy(tp, 0x1f, 0x0000); |
|
3081 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3082 |
|
3083 rtl_writephy(tp, 0x1f, 0x0005); |
|
3084 rtl_writephy(tp, 0x05, 0x8b86); |
|
3085 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3086 rtl_writephy(tp, 0x1f, 0x0000); |
|
3087 |
|
3088 rtl_writephy(tp, 0x1f, 0x0005); |
|
3089 rtl_writephy(tp, 0x05, 0x8b85); |
|
3090 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
3091 rtl_writephy(tp, 0x1f, 0x0007); |
|
3092 rtl_writephy(tp, 0x1e, 0x0020); |
|
3093 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); |
|
3094 rtl_writephy(tp, 0x1f, 0x0006); |
|
3095 rtl_writephy(tp, 0x00, 0x5a00); |
|
3096 rtl_writephy(tp, 0x1f, 0x0000); |
|
3097 rtl_writephy(tp, 0x0d, 0x0007); |
|
3098 rtl_writephy(tp, 0x0e, 0x003c); |
|
3099 rtl_writephy(tp, 0x0d, 0x4007); |
|
3100 rtl_writephy(tp, 0x0e, 0x0000); |
|
3101 rtl_writephy(tp, 0x0d, 0x0000); |
|
3102 } |
|
3103 |
|
3104 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
|
3105 { |
|
3106 static const struct phy_reg phy_reg_init[] = { |
|
3107 /* Enable Delay cap */ |
|
3108 { 0x1f, 0x0004 }, |
|
3109 { 0x1f, 0x0007 }, |
|
3110 { 0x1e, 0x00ac }, |
|
3111 { 0x18, 0x0006 }, |
|
3112 { 0x1f, 0x0002 }, |
|
3113 { 0x1f, 0x0000 }, |
|
3114 { 0x1f, 0x0000 }, |
|
3115 |
|
3116 /* Channel estimation fine tune */ |
|
3117 { 0x1f, 0x0003 }, |
|
3118 { 0x09, 0xa20f }, |
|
3119 { 0x1f, 0x0000 }, |
|
3120 { 0x1f, 0x0000 }, |
|
3121 |
|
3122 /* Green Setting */ |
|
3123 { 0x1f, 0x0005 }, |
|
3124 { 0x05, 0x8b5b }, |
|
3125 { 0x06, 0x9222 }, |
|
3126 { 0x05, 0x8b6d }, |
|
3127 { 0x06, 0x8000 }, |
|
3128 { 0x05, 0x8b76 }, |
|
3129 { 0x06, 0x8000 }, |
|
3130 { 0x1f, 0x0000 } |
|
3131 }; |
|
3132 |
|
3133 rtl_apply_firmware(tp); |
|
3134 |
|
3135 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3136 |
|
3137 /* For 4-corner performance improve */ |
|
3138 rtl_writephy(tp, 0x1f, 0x0005); |
|
3139 rtl_writephy(tp, 0x05, 0x8b80); |
|
3140 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
3141 rtl_writephy(tp, 0x1f, 0x0000); |
|
3142 |
|
3143 /* PHY auto speed down */ |
|
3144 rtl_writephy(tp, 0x1f, 0x0004); |
|
3145 rtl_writephy(tp, 0x1f, 0x0007); |
|
3146 rtl_writephy(tp, 0x1e, 0x002d); |
|
3147 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3148 rtl_writephy(tp, 0x1f, 0x0002); |
|
3149 rtl_writephy(tp, 0x1f, 0x0000); |
|
3150 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3151 |
|
3152 /* improve 10M EEE waveform */ |
|
3153 rtl_writephy(tp, 0x1f, 0x0005); |
|
3154 rtl_writephy(tp, 0x05, 0x8b86); |
|
3155 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3156 rtl_writephy(tp, 0x1f, 0x0000); |
|
3157 |
|
3158 /* Improve 2-pair detection performance */ |
|
3159 rtl_writephy(tp, 0x1f, 0x0005); |
|
3160 rtl_writephy(tp, 0x05, 0x8b85); |
|
3161 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3162 rtl_writephy(tp, 0x1f, 0x0000); |
|
3163 |
|
3164 /* EEE setting */ |
|
3165 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); |
|
3166 rtl_writephy(tp, 0x1f, 0x0005); |
|
3167 rtl_writephy(tp, 0x05, 0x8b85); |
|
3168 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
3169 rtl_writephy(tp, 0x1f, 0x0004); |
|
3170 rtl_writephy(tp, 0x1f, 0x0007); |
|
3171 rtl_writephy(tp, 0x1e, 0x0020); |
|
3172 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
|
3173 rtl_writephy(tp, 0x1f, 0x0002); |
|
3174 rtl_writephy(tp, 0x1f, 0x0000); |
|
3175 rtl_writephy(tp, 0x0d, 0x0007); |
|
3176 rtl_writephy(tp, 0x0e, 0x003c); |
|
3177 rtl_writephy(tp, 0x0d, 0x4007); |
|
3178 rtl_writephy(tp, 0x0e, 0x0000); |
|
3179 rtl_writephy(tp, 0x0d, 0x0000); |
|
3180 |
|
3181 /* Green feature */ |
|
3182 rtl_writephy(tp, 0x1f, 0x0003); |
|
3183 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); |
|
3184 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); |
|
3185 rtl_writephy(tp, 0x1f, 0x0000); |
|
3186 } |
|
3187 |
|
3188 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
|
3189 { |
|
3190 /* For 4-corner performance improve */ |
|
3191 rtl_writephy(tp, 0x1f, 0x0005); |
|
3192 rtl_writephy(tp, 0x05, 0x8b80); |
|
3193 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3194 rtl_writephy(tp, 0x1f, 0x0000); |
|
3195 |
|
3196 /* PHY auto speed down */ |
|
3197 rtl_writephy(tp, 0x1f, 0x0007); |
|
3198 rtl_writephy(tp, 0x1e, 0x002d); |
|
3199 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3200 rtl_writephy(tp, 0x1f, 0x0000); |
|
3201 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3202 |
|
3203 /* Improve 10M EEE waveform */ |
|
3204 rtl_writephy(tp, 0x1f, 0x0005); |
|
3205 rtl_writephy(tp, 0x05, 0x8b86); |
|
3206 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3207 rtl_writephy(tp, 0x1f, 0x0000); |
|
3208 } |
|
3209 |
|
3210 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
|
3211 { |
|
3212 static const struct phy_reg phy_reg_init[] = { |
|
3213 /* Channel estimation fine tune */ |
|
3214 { 0x1f, 0x0003 }, |
|
3215 { 0x09, 0xa20f }, |
|
3216 { 0x1f, 0x0000 }, |
|
3217 |
|
3218 /* Modify green table for giga & fnet */ |
|
3219 { 0x1f, 0x0005 }, |
|
3220 { 0x05, 0x8b55 }, |
|
3221 { 0x06, 0x0000 }, |
|
3222 { 0x05, 0x8b5e }, |
|
3223 { 0x06, 0x0000 }, |
|
3224 { 0x05, 0x8b67 }, |
|
3225 { 0x06, 0x0000 }, |
|
3226 { 0x05, 0x8b70 }, |
|
3227 { 0x06, 0x0000 }, |
|
3228 { 0x1f, 0x0000 }, |
|
3229 { 0x1f, 0x0007 }, |
|
3230 { 0x1e, 0x0078 }, |
|
3231 { 0x17, 0x0000 }, |
|
3232 { 0x19, 0x00fb }, |
|
3233 { 0x1f, 0x0000 }, |
|
3234 |
|
3235 /* Modify green table for 10M */ |
|
3236 { 0x1f, 0x0005 }, |
|
3237 { 0x05, 0x8b79 }, |
|
3238 { 0x06, 0xaa00 }, |
|
3239 { 0x1f, 0x0000 }, |
|
3240 |
|
3241 /* Disable hiimpedance detection (RTCT) */ |
|
3242 { 0x1f, 0x0003 }, |
|
3243 { 0x01, 0x328a }, |
|
3244 { 0x1f, 0x0000 } |
|
3245 }; |
|
3246 |
|
3247 rtl_apply_firmware(tp); |
|
3248 |
|
3249 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3250 |
|
3251 rtl8168f_hw_phy_config(tp); |
|
3252 |
|
3253 /* Improve 2-pair detection performance */ |
|
3254 rtl_writephy(tp, 0x1f, 0x0005); |
|
3255 rtl_writephy(tp, 0x05, 0x8b85); |
|
3256 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3257 rtl_writephy(tp, 0x1f, 0x0000); |
|
3258 } |
|
3259 |
|
3260 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) |
|
3261 { |
|
3262 rtl_apply_firmware(tp); |
|
3263 |
|
3264 rtl8168f_hw_phy_config(tp); |
|
3265 } |
|
3266 |
|
3267 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
|
3268 { |
|
3269 static const struct phy_reg phy_reg_init[] = { |
|
3270 /* Channel estimation fine tune */ |
|
3271 { 0x1f, 0x0003 }, |
|
3272 { 0x09, 0xa20f }, |
|
3273 { 0x1f, 0x0000 }, |
|
3274 |
|
3275 /* Modify green table for giga & fnet */ |
|
3276 { 0x1f, 0x0005 }, |
|
3277 { 0x05, 0x8b55 }, |
|
3278 { 0x06, 0x0000 }, |
|
3279 { 0x05, 0x8b5e }, |
|
3280 { 0x06, 0x0000 }, |
|
3281 { 0x05, 0x8b67 }, |
|
3282 { 0x06, 0x0000 }, |
|
3283 { 0x05, 0x8b70 }, |
|
3284 { 0x06, 0x0000 }, |
|
3285 { 0x1f, 0x0000 }, |
|
3286 { 0x1f, 0x0007 }, |
|
3287 { 0x1e, 0x0078 }, |
|
3288 { 0x17, 0x0000 }, |
|
3289 { 0x19, 0x00aa }, |
|
3290 { 0x1f, 0x0000 }, |
|
3291 |
|
3292 /* Modify green table for 10M */ |
|
3293 { 0x1f, 0x0005 }, |
|
3294 { 0x05, 0x8b79 }, |
|
3295 { 0x06, 0xaa00 }, |
|
3296 { 0x1f, 0x0000 }, |
|
3297 |
|
3298 /* Disable hiimpedance detection (RTCT) */ |
|
3299 { 0x1f, 0x0003 }, |
|
3300 { 0x01, 0x328a }, |
|
3301 { 0x1f, 0x0000 } |
|
3302 }; |
|
3303 |
|
3304 |
|
3305 rtl_apply_firmware(tp); |
|
3306 |
|
3307 rtl8168f_hw_phy_config(tp); |
|
3308 |
|
3309 /* Improve 2-pair detection performance */ |
|
3310 rtl_writephy(tp, 0x1f, 0x0005); |
|
3311 rtl_writephy(tp, 0x05, 0x8b85); |
|
3312 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3313 rtl_writephy(tp, 0x1f, 0x0000); |
|
3314 |
|
3315 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3316 |
|
3317 /* Modify green table for giga */ |
|
3318 rtl_writephy(tp, 0x1f, 0x0005); |
|
3319 rtl_writephy(tp, 0x05, 0x8b54); |
|
3320 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); |
|
3321 rtl_writephy(tp, 0x05, 0x8b5d); |
|
3322 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); |
|
3323 rtl_writephy(tp, 0x05, 0x8a7c); |
|
3324 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); |
|
3325 rtl_writephy(tp, 0x05, 0x8a7f); |
|
3326 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000); |
|
3327 rtl_writephy(tp, 0x05, 0x8a82); |
|
3328 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); |
|
3329 rtl_writephy(tp, 0x05, 0x8a85); |
|
3330 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); |
|
3331 rtl_writephy(tp, 0x05, 0x8a88); |
|
3332 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); |
|
3333 rtl_writephy(tp, 0x1f, 0x0000); |
|
3334 |
|
3335 /* uc same-seed solution */ |
|
3336 rtl_writephy(tp, 0x1f, 0x0005); |
|
3337 rtl_writephy(tp, 0x05, 0x8b85); |
|
3338 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000); |
|
3339 rtl_writephy(tp, 0x1f, 0x0000); |
|
3340 |
|
3341 /* eee setting */ |
|
3342 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
|
3343 rtl_writephy(tp, 0x1f, 0x0005); |
|
3344 rtl_writephy(tp, 0x05, 0x8b85); |
|
3345 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
3346 rtl_writephy(tp, 0x1f, 0x0004); |
|
3347 rtl_writephy(tp, 0x1f, 0x0007); |
|
3348 rtl_writephy(tp, 0x1e, 0x0020); |
|
3349 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
|
3350 rtl_writephy(tp, 0x1f, 0x0000); |
|
3351 rtl_writephy(tp, 0x0d, 0x0007); |
|
3352 rtl_writephy(tp, 0x0e, 0x003c); |
|
3353 rtl_writephy(tp, 0x0d, 0x4007); |
|
3354 rtl_writephy(tp, 0x0e, 0x0000); |
|
3355 rtl_writephy(tp, 0x0d, 0x0000); |
|
3356 |
|
3357 /* Green feature */ |
|
3358 rtl_writephy(tp, 0x1f, 0x0003); |
|
3359 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); |
|
3360 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); |
|
3361 rtl_writephy(tp, 0x1f, 0x0000); |
|
3362 } |
|
3363 |
|
3364 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) |
|
3365 { |
|
3366 static const u16 mac_ocp_patch[] = { |
|
3367 0xe008, 0xe01b, 0xe01d, 0xe01f, |
|
3368 0xe021, 0xe023, 0xe025, 0xe027, |
|
3369 0x49d2, 0xf10d, 0x766c, 0x49e2, |
|
3370 0xf00a, 0x1ec0, 0x8ee1, 0xc60a, |
|
3371 |
|
3372 0x77c0, 0x4870, 0x9fc0, 0x1ea0, |
|
3373 0xc707, 0x8ee1, 0x9d6c, 0xc603, |
|
3374 0xbe00, 0xb416, 0x0076, 0xe86c, |
|
3375 0xc602, 0xbe00, 0x0000, 0xc602, |
|
3376 |
|
3377 0xbe00, 0x0000, 0xc602, 0xbe00, |
|
3378 0x0000, 0xc602, 0xbe00, 0x0000, |
|
3379 0xc602, 0xbe00, 0x0000, 0xc602, |
|
3380 0xbe00, 0x0000, 0xc602, 0xbe00, |
|
3381 |
|
3382 0x0000, 0x0000, 0x0000, 0x0000 |
|
3383 }; |
|
3384 u32 i; |
|
3385 |
|
3386 /* Patch code for GPHY reset */ |
|
3387 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++) |
|
3388 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]); |
|
3389 r8168_mac_ocp_write(tp, 0xfc26, 0x8000); |
|
3390 r8168_mac_ocp_write(tp, 0xfc28, 0x0075); |
|
3391 |
|
3392 rtl_apply_firmware(tp); |
|
3393 |
|
3394 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100) |
|
3395 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000); |
|
3396 else |
|
3397 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000); |
|
3398 |
|
3399 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100) |
|
3400 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000); |
|
3401 else |
|
3402 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002); |
|
3403 |
|
3404 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000); |
|
3405 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000); |
|
3406 |
|
3407 r8168_phy_ocp_write(tp, 0xa436, 0x8012); |
|
3408 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000); |
|
3409 |
|
3410 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000); |
|
3411 } |
|
3412 |
|
3413 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
|
3414 { |
|
3415 static const struct phy_reg phy_reg_init[] = { |
|
3416 { 0x1f, 0x0003 }, |
|
3417 { 0x08, 0x441d }, |
|
3418 { 0x01, 0x9100 }, |
|
3419 { 0x1f, 0x0000 } |
|
3420 }; |
|
3421 |
|
3422 rtl_writephy(tp, 0x1f, 0x0000); |
|
3423 rtl_patchphy(tp, 0x11, 1 << 12); |
|
3424 rtl_patchphy(tp, 0x19, 1 << 13); |
|
3425 rtl_patchphy(tp, 0x10, 1 << 15); |
|
3426 |
|
3427 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3428 } |
|
3429 |
|
3430 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
|
3431 { |
|
3432 static const struct phy_reg phy_reg_init[] = { |
|
3433 { 0x1f, 0x0005 }, |
|
3434 { 0x1a, 0x0000 }, |
|
3435 { 0x1f, 0x0000 }, |
|
3436 |
|
3437 { 0x1f, 0x0004 }, |
|
3438 { 0x1c, 0x0000 }, |
|
3439 { 0x1f, 0x0000 }, |
|
3440 |
|
3441 { 0x1f, 0x0001 }, |
|
3442 { 0x15, 0x7701 }, |
|
3443 { 0x1f, 0x0000 } |
|
3444 }; |
|
3445 |
|
3446 /* Disable ALDPS before ram code */ |
|
3447 rtl_writephy(tp, 0x1f, 0x0000); |
|
3448 rtl_writephy(tp, 0x18, 0x0310); |
|
3449 msleep(100); |
|
3450 |
|
3451 rtl_apply_firmware(tp); |
|
3452 |
|
3453 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3454 } |
|
3455 |
|
3456 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
|
3457 { |
|
3458 /* Disable ALDPS before setting firmware */ |
|
3459 rtl_writephy(tp, 0x1f, 0x0000); |
|
3460 rtl_writephy(tp, 0x18, 0x0310); |
|
3461 msleep(20); |
|
3462 |
|
3463 rtl_apply_firmware(tp); |
|
3464 |
|
3465 /* EEE setting */ |
|
3466 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
3467 rtl_writephy(tp, 0x1f, 0x0004); |
|
3468 rtl_writephy(tp, 0x10, 0x401f); |
|
3469 rtl_writephy(tp, 0x19, 0x7030); |
|
3470 rtl_writephy(tp, 0x1f, 0x0000); |
|
3471 } |
|
3472 |
|
3473 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
|
3474 { |
|
3475 static const struct phy_reg phy_reg_init[] = { |
|
3476 { 0x1f, 0x0004 }, |
|
3477 { 0x10, 0xc07f }, |
|
3478 { 0x19, 0x7030 }, |
|
3479 { 0x1f, 0x0000 } |
|
3480 }; |
|
3481 |
|
3482 /* Disable ALDPS before ram code */ |
|
3483 rtl_writephy(tp, 0x1f, 0x0000); |
|
3484 rtl_writephy(tp, 0x18, 0x0310); |
|
3485 msleep(100); |
|
3486 |
|
3487 rtl_apply_firmware(tp); |
|
3488 |
|
3489 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
3490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3491 |
|
3492 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
3493 } |
|
3494 |
|
3495 static void rtl_hw_phy_config(struct net_device *dev) |
|
3496 { |
|
3497 struct rtl8169_private *tp = netdev_priv(dev); |
|
3498 |
|
3499 rtl8169_print_mac_version(tp); |
|
3500 |
|
3501 switch (tp->mac_version) { |
|
3502 case RTL_GIGA_MAC_VER_01: |
|
3503 break; |
|
3504 case RTL_GIGA_MAC_VER_02: |
|
3505 case RTL_GIGA_MAC_VER_03: |
|
3506 rtl8169s_hw_phy_config(tp); |
|
3507 break; |
|
3508 case RTL_GIGA_MAC_VER_04: |
|
3509 rtl8169sb_hw_phy_config(tp); |
|
3510 break; |
|
3511 case RTL_GIGA_MAC_VER_05: |
|
3512 rtl8169scd_hw_phy_config(tp); |
|
3513 break; |
|
3514 case RTL_GIGA_MAC_VER_06: |
|
3515 rtl8169sce_hw_phy_config(tp); |
|
3516 break; |
|
3517 case RTL_GIGA_MAC_VER_07: |
|
3518 case RTL_GIGA_MAC_VER_08: |
|
3519 case RTL_GIGA_MAC_VER_09: |
|
3520 rtl8102e_hw_phy_config(tp); |
|
3521 break; |
|
3522 case RTL_GIGA_MAC_VER_11: |
|
3523 rtl8168bb_hw_phy_config(tp); |
|
3524 break; |
|
3525 case RTL_GIGA_MAC_VER_12: |
|
3526 rtl8168bef_hw_phy_config(tp); |
|
3527 break; |
|
3528 case RTL_GIGA_MAC_VER_17: |
|
3529 rtl8168bef_hw_phy_config(tp); |
|
3530 break; |
|
3531 case RTL_GIGA_MAC_VER_18: |
|
3532 rtl8168cp_1_hw_phy_config(tp); |
|
3533 break; |
|
3534 case RTL_GIGA_MAC_VER_19: |
|
3535 rtl8168c_1_hw_phy_config(tp); |
|
3536 break; |
|
3537 case RTL_GIGA_MAC_VER_20: |
|
3538 rtl8168c_2_hw_phy_config(tp); |
|
3539 break; |
|
3540 case RTL_GIGA_MAC_VER_21: |
|
3541 rtl8168c_3_hw_phy_config(tp); |
|
3542 break; |
|
3543 case RTL_GIGA_MAC_VER_22: |
|
3544 rtl8168c_4_hw_phy_config(tp); |
|
3545 break; |
|
3546 case RTL_GIGA_MAC_VER_23: |
|
3547 case RTL_GIGA_MAC_VER_24: |
|
3548 rtl8168cp_2_hw_phy_config(tp); |
|
3549 break; |
|
3550 case RTL_GIGA_MAC_VER_25: |
|
3551 rtl8168d_1_hw_phy_config(tp); |
|
3552 break; |
|
3553 case RTL_GIGA_MAC_VER_26: |
|
3554 rtl8168d_2_hw_phy_config(tp); |
|
3555 break; |
|
3556 case RTL_GIGA_MAC_VER_27: |
|
3557 rtl8168d_3_hw_phy_config(tp); |
|
3558 break; |
|
3559 case RTL_GIGA_MAC_VER_28: |
|
3560 rtl8168d_4_hw_phy_config(tp); |
|
3561 break; |
|
3562 case RTL_GIGA_MAC_VER_29: |
|
3563 case RTL_GIGA_MAC_VER_30: |
|
3564 rtl8105e_hw_phy_config(tp); |
|
3565 break; |
|
3566 case RTL_GIGA_MAC_VER_31: |
|
3567 /* None. */ |
|
3568 break; |
|
3569 case RTL_GIGA_MAC_VER_32: |
|
3570 case RTL_GIGA_MAC_VER_33: |
|
3571 rtl8168e_1_hw_phy_config(tp); |
|
3572 break; |
|
3573 case RTL_GIGA_MAC_VER_34: |
|
3574 rtl8168e_2_hw_phy_config(tp); |
|
3575 break; |
|
3576 case RTL_GIGA_MAC_VER_35: |
|
3577 rtl8168f_1_hw_phy_config(tp); |
|
3578 break; |
|
3579 case RTL_GIGA_MAC_VER_36: |
|
3580 rtl8168f_2_hw_phy_config(tp); |
|
3581 break; |
|
3582 |
|
3583 case RTL_GIGA_MAC_VER_37: |
|
3584 rtl8402_hw_phy_config(tp); |
|
3585 break; |
|
3586 |
|
3587 case RTL_GIGA_MAC_VER_38: |
|
3588 rtl8411_hw_phy_config(tp); |
|
3589 break; |
|
3590 |
|
3591 case RTL_GIGA_MAC_VER_39: |
|
3592 rtl8106e_hw_phy_config(tp); |
|
3593 break; |
|
3594 |
|
3595 case RTL_GIGA_MAC_VER_40: |
|
3596 rtl8168g_1_hw_phy_config(tp); |
|
3597 break; |
|
3598 |
|
3599 case RTL_GIGA_MAC_VER_41: |
|
3600 default: |
|
3601 break; |
|
3602 } |
|
3603 } |
|
3604 |
|
3605 static void rtl_phy_work(struct rtl8169_private *tp) |
|
3606 { |
|
3607 struct timer_list *timer = &tp->timer; |
|
3608 void __iomem *ioaddr = tp->mmio_addr; |
|
3609 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
3610 |
|
3611 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
3612 |
|
3613 if (tp->phy_reset_pending(tp)) { |
|
3614 /* |
|
3615 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
3616 * Let's delay the execution of the timer for a few ticks. |
|
3617 */ |
|
3618 timeout = HZ/10; |
|
3619 goto out_mod_timer; |
|
3620 } |
|
3621 |
|
3622 if (tp->link_ok(ioaddr)) |
|
3623 return; |
|
3624 |
|
3625 netif_warn(tp, link, tp->dev, "PHY reset until link up\n"); |
|
3626 |
|
3627 tp->phy_reset_enable(tp); |
|
3628 |
|
3629 out_mod_timer: |
|
3630 mod_timer(timer, jiffies + timeout); |
|
3631 } |
|
3632 |
|
3633 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) |
|
3634 { |
|
3635 if (!test_and_set_bit(flag, tp->wk.flags)) |
|
3636 schedule_work(&tp->wk.work); |
|
3637 } |
|
3638 |
|
3639 static void rtl8169_phy_timer(unsigned long __opaque) |
|
3640 { |
|
3641 struct net_device *dev = (struct net_device *)__opaque; |
|
3642 struct rtl8169_private *tp = netdev_priv(dev); |
|
3643 |
|
3644 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
|
3645 } |
|
3646 |
|
3647 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
3648 void __iomem *ioaddr) |
|
3649 { |
|
3650 iounmap(ioaddr); |
|
3651 pci_release_regions(pdev); |
|
3652 pci_clear_mwi(pdev); |
|
3653 pci_disable_device(pdev); |
|
3654 free_netdev(dev); |
|
3655 } |
|
3656 |
|
3657 DECLARE_RTL_COND(rtl_phy_reset_cond) |
|
3658 { |
|
3659 return tp->phy_reset_pending(tp); |
|
3660 } |
|
3661 |
|
3662 static void rtl8169_phy_reset(struct net_device *dev, |
|
3663 struct rtl8169_private *tp) |
|
3664 { |
|
3665 tp->phy_reset_enable(tp); |
|
3666 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
|
3667 } |
|
3668 |
|
3669 static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
|
3670 { |
|
3671 void __iomem *ioaddr = tp->mmio_addr; |
|
3672 |
|
3673 return (tp->mac_version == RTL_GIGA_MAC_VER_01) && |
|
3674 (RTL_R8(PHYstatus) & TBI_Enable); |
|
3675 } |
|
3676 |
|
3677 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
3678 { |
|
3679 void __iomem *ioaddr = tp->mmio_addr; |
|
3680 |
|
3681 rtl_hw_phy_config(dev); |
|
3682 |
|
3683 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
3684 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3685 RTL_W8(0x82, 0x01); |
|
3686 } |
|
3687 |
|
3688 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
3689 |
|
3690 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
3691 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3692 |
|
3693 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
3694 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3695 RTL_W8(0x82, 0x01); |
|
3696 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
3697 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
3698 } |
|
3699 |
|
3700 rtl8169_phy_reset(dev, tp); |
|
3701 |
|
3702 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
|
3703 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
3704 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | |
|
3705 (tp->mii.supports_gmii ? |
|
3706 ADVERTISED_1000baseT_Half | |
|
3707 ADVERTISED_1000baseT_Full : 0)); |
|
3708 |
|
3709 if (rtl_tbi_enabled(tp)) |
|
3710 netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
|
3711 } |
|
3712 |
|
3713 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
3714 { |
|
3715 void __iomem *ioaddr = tp->mmio_addr; |
|
3716 u32 high; |
|
3717 u32 low; |
|
3718 |
|
3719 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
3720 high = addr[4] | (addr[5] << 8); |
|
3721 |
|
3722 rtl_lock_work(tp); |
|
3723 |
|
3724 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3725 |
|
3726 RTL_W32(MAC4, high); |
|
3727 RTL_R32(MAC4); |
|
3728 |
|
3729 RTL_W32(MAC0, low); |
|
3730 RTL_R32(MAC0); |
|
3731 |
|
3732 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
3733 const struct exgmac_reg e[] = { |
|
3734 { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, |
|
3735 { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, |
|
3736 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, |
|
3737 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | |
|
3738 low >> 16 }, |
|
3739 }; |
|
3740 |
|
3741 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); |
|
3742 } |
|
3743 |
|
3744 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3745 |
|
3746 rtl_unlock_work(tp); |
|
3747 } |
|
3748 |
|
3749 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
3750 { |
|
3751 struct rtl8169_private *tp = netdev_priv(dev); |
|
3752 struct sockaddr *addr = p; |
|
3753 |
|
3754 if (!is_valid_ether_addr(addr->sa_data)) |
|
3755 return -EADDRNOTAVAIL; |
|
3756 |
|
3757 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
3758 |
|
3759 rtl_rar_set(tp, dev->dev_addr); |
|
3760 |
|
3761 return 0; |
|
3762 } |
|
3763 |
|
3764 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
3765 { |
|
3766 struct rtl8169_private *tp = netdev_priv(dev); |
|
3767 struct mii_ioctl_data *data = if_mii(ifr); |
|
3768 |
|
3769 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
3770 } |
|
3771 |
|
3772 static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
|
3773 struct mii_ioctl_data *data, int cmd) |
|
3774 { |
|
3775 switch (cmd) { |
|
3776 case SIOCGMIIPHY: |
|
3777 data->phy_id = 32; /* Internal PHY */ |
|
3778 return 0; |
|
3779 |
|
3780 case SIOCGMIIREG: |
|
3781 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
|
3782 return 0; |
|
3783 |
|
3784 case SIOCSMIIREG: |
|
3785 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
|
3786 return 0; |
|
3787 } |
|
3788 return -EOPNOTSUPP; |
|
3789 } |
|
3790 |
|
3791 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
3792 { |
|
3793 return -EOPNOTSUPP; |
|
3794 } |
|
3795 |
|
3796 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
3797 { |
|
3798 if (tp->features & RTL_FEATURE_MSI) { |
|
3799 pci_disable_msi(pdev); |
|
3800 tp->features &= ~RTL_FEATURE_MSI; |
|
3801 } |
|
3802 } |
|
3803 |
|
3804 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
|
3805 { |
|
3806 struct mdio_ops *ops = &tp->mdio_ops; |
|
3807 |
|
3808 switch (tp->mac_version) { |
|
3809 case RTL_GIGA_MAC_VER_27: |
|
3810 ops->write = r8168dp_1_mdio_write; |
|
3811 ops->read = r8168dp_1_mdio_read; |
|
3812 break; |
|
3813 case RTL_GIGA_MAC_VER_28: |
|
3814 case RTL_GIGA_MAC_VER_31: |
|
3815 ops->write = r8168dp_2_mdio_write; |
|
3816 ops->read = r8168dp_2_mdio_read; |
|
3817 break; |
|
3818 case RTL_GIGA_MAC_VER_40: |
|
3819 case RTL_GIGA_MAC_VER_41: |
|
3820 ops->write = r8168g_mdio_write; |
|
3821 ops->read = r8168g_mdio_read; |
|
3822 break; |
|
3823 default: |
|
3824 ops->write = r8169_mdio_write; |
|
3825 ops->read = r8169_mdio_read; |
|
3826 break; |
|
3827 } |
|
3828 } |
|
3829 |
|
3830 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
|
3831 { |
|
3832 void __iomem *ioaddr = tp->mmio_addr; |
|
3833 |
|
3834 switch (tp->mac_version) { |
|
3835 case RTL_GIGA_MAC_VER_25: |
|
3836 case RTL_GIGA_MAC_VER_26: |
|
3837 case RTL_GIGA_MAC_VER_29: |
|
3838 case RTL_GIGA_MAC_VER_30: |
|
3839 case RTL_GIGA_MAC_VER_32: |
|
3840 case RTL_GIGA_MAC_VER_33: |
|
3841 case RTL_GIGA_MAC_VER_34: |
|
3842 case RTL_GIGA_MAC_VER_37: |
|
3843 case RTL_GIGA_MAC_VER_38: |
|
3844 case RTL_GIGA_MAC_VER_39: |
|
3845 case RTL_GIGA_MAC_VER_40: |
|
3846 case RTL_GIGA_MAC_VER_41: |
|
3847 RTL_W32(RxConfig, RTL_R32(RxConfig) | |
|
3848 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
|
3849 break; |
|
3850 default: |
|
3851 break; |
|
3852 } |
|
3853 } |
|
3854 |
|
3855 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) |
|
3856 { |
|
3857 if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) |
|
3858 return false; |
|
3859 |
|
3860 rtl_writephy(tp, 0x1f, 0x0000); |
|
3861 rtl_writephy(tp, MII_BMCR, 0x0000); |
|
3862 |
|
3863 rtl_wol_suspend_quirk(tp); |
|
3864 |
|
3865 return true; |
|
3866 } |
|
3867 |
|
3868 static void r810x_phy_power_down(struct rtl8169_private *tp) |
|
3869 { |
|
3870 rtl_writephy(tp, 0x1f, 0x0000); |
|
3871 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3872 } |
|
3873 |
|
3874 static void r810x_phy_power_up(struct rtl8169_private *tp) |
|
3875 { |
|
3876 rtl_writephy(tp, 0x1f, 0x0000); |
|
3877 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3878 } |
|
3879 |
|
3880 static void r810x_pll_power_down(struct rtl8169_private *tp) |
|
3881 { |
|
3882 void __iomem *ioaddr = tp->mmio_addr; |
|
3883 |
|
3884 if (rtl_wol_pll_power_down(tp)) |
|
3885 return; |
|
3886 |
|
3887 r810x_phy_power_down(tp); |
|
3888 |
|
3889 switch (tp->mac_version) { |
|
3890 case RTL_GIGA_MAC_VER_07: |
|
3891 case RTL_GIGA_MAC_VER_08: |
|
3892 case RTL_GIGA_MAC_VER_09: |
|
3893 case RTL_GIGA_MAC_VER_10: |
|
3894 case RTL_GIGA_MAC_VER_13: |
|
3895 case RTL_GIGA_MAC_VER_16: |
|
3896 break; |
|
3897 default: |
|
3898 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
|
3899 break; |
|
3900 } |
|
3901 } |
|
3902 |
|
3903 static void r810x_pll_power_up(struct rtl8169_private *tp) |
|
3904 { |
|
3905 void __iomem *ioaddr = tp->mmio_addr; |
|
3906 |
|
3907 r810x_phy_power_up(tp); |
|
3908 |
|
3909 switch (tp->mac_version) { |
|
3910 case RTL_GIGA_MAC_VER_07: |
|
3911 case RTL_GIGA_MAC_VER_08: |
|
3912 case RTL_GIGA_MAC_VER_09: |
|
3913 case RTL_GIGA_MAC_VER_10: |
|
3914 case RTL_GIGA_MAC_VER_13: |
|
3915 case RTL_GIGA_MAC_VER_16: |
|
3916 break; |
|
3917 default: |
|
3918 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
|
3919 break; |
|
3920 } |
|
3921 } |
|
3922 |
|
3923 static void r8168_phy_power_up(struct rtl8169_private *tp) |
|
3924 { |
|
3925 rtl_writephy(tp, 0x1f, 0x0000); |
|
3926 switch (tp->mac_version) { |
|
3927 case RTL_GIGA_MAC_VER_11: |
|
3928 case RTL_GIGA_MAC_VER_12: |
|
3929 case RTL_GIGA_MAC_VER_17: |
|
3930 case RTL_GIGA_MAC_VER_18: |
|
3931 case RTL_GIGA_MAC_VER_19: |
|
3932 case RTL_GIGA_MAC_VER_20: |
|
3933 case RTL_GIGA_MAC_VER_21: |
|
3934 case RTL_GIGA_MAC_VER_22: |
|
3935 case RTL_GIGA_MAC_VER_23: |
|
3936 case RTL_GIGA_MAC_VER_24: |
|
3937 case RTL_GIGA_MAC_VER_25: |
|
3938 case RTL_GIGA_MAC_VER_26: |
|
3939 case RTL_GIGA_MAC_VER_27: |
|
3940 case RTL_GIGA_MAC_VER_28: |
|
3941 case RTL_GIGA_MAC_VER_31: |
|
3942 rtl_writephy(tp, 0x0e, 0x0000); |
|
3943 break; |
|
3944 default: |
|
3945 break; |
|
3946 } |
|
3947 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3948 } |
|
3949 |
|
3950 static void r8168_phy_power_down(struct rtl8169_private *tp) |
|
3951 { |
|
3952 rtl_writephy(tp, 0x1f, 0x0000); |
|
3953 switch (tp->mac_version) { |
|
3954 case RTL_GIGA_MAC_VER_32: |
|
3955 case RTL_GIGA_MAC_VER_33: |
|
3956 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
|
3957 break; |
|
3958 |
|
3959 case RTL_GIGA_MAC_VER_11: |
|
3960 case RTL_GIGA_MAC_VER_12: |
|
3961 case RTL_GIGA_MAC_VER_17: |
|
3962 case RTL_GIGA_MAC_VER_18: |
|
3963 case RTL_GIGA_MAC_VER_19: |
|
3964 case RTL_GIGA_MAC_VER_20: |
|
3965 case RTL_GIGA_MAC_VER_21: |
|
3966 case RTL_GIGA_MAC_VER_22: |
|
3967 case RTL_GIGA_MAC_VER_23: |
|
3968 case RTL_GIGA_MAC_VER_24: |
|
3969 case RTL_GIGA_MAC_VER_25: |
|
3970 case RTL_GIGA_MAC_VER_26: |
|
3971 case RTL_GIGA_MAC_VER_27: |
|
3972 case RTL_GIGA_MAC_VER_28: |
|
3973 case RTL_GIGA_MAC_VER_31: |
|
3974 rtl_writephy(tp, 0x0e, 0x0200); |
|
3975 default: |
|
3976 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3977 break; |
|
3978 } |
|
3979 } |
|
3980 |
|
3981 static void r8168_pll_power_down(struct rtl8169_private *tp) |
|
3982 { |
|
3983 void __iomem *ioaddr = tp->mmio_addr; |
|
3984 |
|
3985 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3986 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3987 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3988 r8168dp_check_dash(tp)) { |
|
3989 return; |
|
3990 } |
|
3991 |
|
3992 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
|
3993 tp->mac_version == RTL_GIGA_MAC_VER_24) && |
|
3994 (RTL_R16(CPlusCmd) & ASF)) { |
|
3995 return; |
|
3996 } |
|
3997 |
|
3998 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
|
3999 tp->mac_version == RTL_GIGA_MAC_VER_33) |
|
4000 rtl_ephy_write(tp, 0x19, 0xff64); |
|
4001 |
|
4002 if (rtl_wol_pll_power_down(tp)) |
|
4003 return; |
|
4004 |
|
4005 r8168_phy_power_down(tp); |
|
4006 |
|
4007 switch (tp->mac_version) { |
|
4008 case RTL_GIGA_MAC_VER_25: |
|
4009 case RTL_GIGA_MAC_VER_26: |
|
4010 case RTL_GIGA_MAC_VER_27: |
|
4011 case RTL_GIGA_MAC_VER_28: |
|
4012 case RTL_GIGA_MAC_VER_31: |
|
4013 case RTL_GIGA_MAC_VER_32: |
|
4014 case RTL_GIGA_MAC_VER_33: |
|
4015 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
|
4016 break; |
|
4017 } |
|
4018 } |
|
4019 |
|
4020 static void r8168_pll_power_up(struct rtl8169_private *tp) |
|
4021 { |
|
4022 void __iomem *ioaddr = tp->mmio_addr; |
|
4023 |
|
4024 switch (tp->mac_version) { |
|
4025 case RTL_GIGA_MAC_VER_25: |
|
4026 case RTL_GIGA_MAC_VER_26: |
|
4027 case RTL_GIGA_MAC_VER_27: |
|
4028 case RTL_GIGA_MAC_VER_28: |
|
4029 case RTL_GIGA_MAC_VER_31: |
|
4030 case RTL_GIGA_MAC_VER_32: |
|
4031 case RTL_GIGA_MAC_VER_33: |
|
4032 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
|
4033 break; |
|
4034 } |
|
4035 |
|
4036 r8168_phy_power_up(tp); |
|
4037 } |
|
4038 |
|
4039 static void rtl_generic_op(struct rtl8169_private *tp, |
|
4040 void (*op)(struct rtl8169_private *)) |
|
4041 { |
|
4042 if (op) |
|
4043 op(tp); |
|
4044 } |
|
4045 |
|
4046 static void rtl_pll_power_down(struct rtl8169_private *tp) |
|
4047 { |
|
4048 rtl_generic_op(tp, tp->pll_power_ops.down); |
|
4049 } |
|
4050 |
|
4051 static void rtl_pll_power_up(struct rtl8169_private *tp) |
|
4052 { |
|
4053 rtl_generic_op(tp, tp->pll_power_ops.up); |
|
4054 } |
|
4055 |
|
4056 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) |
|
4057 { |
|
4058 struct pll_power_ops *ops = &tp->pll_power_ops; |
|
4059 |
|
4060 switch (tp->mac_version) { |
|
4061 case RTL_GIGA_MAC_VER_07: |
|
4062 case RTL_GIGA_MAC_VER_08: |
|
4063 case RTL_GIGA_MAC_VER_09: |
|
4064 case RTL_GIGA_MAC_VER_10: |
|
4065 case RTL_GIGA_MAC_VER_16: |
|
4066 case RTL_GIGA_MAC_VER_29: |
|
4067 case RTL_GIGA_MAC_VER_30: |
|
4068 case RTL_GIGA_MAC_VER_37: |
|
4069 case RTL_GIGA_MAC_VER_39: |
|
4070 ops->down = r810x_pll_power_down; |
|
4071 ops->up = r810x_pll_power_up; |
|
4072 break; |
|
4073 |
|
4074 case RTL_GIGA_MAC_VER_11: |
|
4075 case RTL_GIGA_MAC_VER_12: |
|
4076 case RTL_GIGA_MAC_VER_17: |
|
4077 case RTL_GIGA_MAC_VER_18: |
|
4078 case RTL_GIGA_MAC_VER_19: |
|
4079 case RTL_GIGA_MAC_VER_20: |
|
4080 case RTL_GIGA_MAC_VER_21: |
|
4081 case RTL_GIGA_MAC_VER_22: |
|
4082 case RTL_GIGA_MAC_VER_23: |
|
4083 case RTL_GIGA_MAC_VER_24: |
|
4084 case RTL_GIGA_MAC_VER_25: |
|
4085 case RTL_GIGA_MAC_VER_26: |
|
4086 case RTL_GIGA_MAC_VER_27: |
|
4087 case RTL_GIGA_MAC_VER_28: |
|
4088 case RTL_GIGA_MAC_VER_31: |
|
4089 case RTL_GIGA_MAC_VER_32: |
|
4090 case RTL_GIGA_MAC_VER_33: |
|
4091 case RTL_GIGA_MAC_VER_34: |
|
4092 case RTL_GIGA_MAC_VER_35: |
|
4093 case RTL_GIGA_MAC_VER_36: |
|
4094 case RTL_GIGA_MAC_VER_38: |
|
4095 case RTL_GIGA_MAC_VER_40: |
|
4096 case RTL_GIGA_MAC_VER_41: |
|
4097 ops->down = r8168_pll_power_down; |
|
4098 ops->up = r8168_pll_power_up; |
|
4099 break; |
|
4100 |
|
4101 default: |
|
4102 ops->down = NULL; |
|
4103 ops->up = NULL; |
|
4104 break; |
|
4105 } |
|
4106 } |
|
4107 |
|
4108 static void rtl_init_rxcfg(struct rtl8169_private *tp) |
|
4109 { |
|
4110 void __iomem *ioaddr = tp->mmio_addr; |
|
4111 |
|
4112 switch (tp->mac_version) { |
|
4113 case RTL_GIGA_MAC_VER_01: |
|
4114 case RTL_GIGA_MAC_VER_02: |
|
4115 case RTL_GIGA_MAC_VER_03: |
|
4116 case RTL_GIGA_MAC_VER_04: |
|
4117 case RTL_GIGA_MAC_VER_05: |
|
4118 case RTL_GIGA_MAC_VER_06: |
|
4119 case RTL_GIGA_MAC_VER_10: |
|
4120 case RTL_GIGA_MAC_VER_11: |
|
4121 case RTL_GIGA_MAC_VER_12: |
|
4122 case RTL_GIGA_MAC_VER_13: |
|
4123 case RTL_GIGA_MAC_VER_14: |
|
4124 case RTL_GIGA_MAC_VER_15: |
|
4125 case RTL_GIGA_MAC_VER_16: |
|
4126 case RTL_GIGA_MAC_VER_17: |
|
4127 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
|
4128 break; |
|
4129 case RTL_GIGA_MAC_VER_18: |
|
4130 case RTL_GIGA_MAC_VER_19: |
|
4131 case RTL_GIGA_MAC_VER_20: |
|
4132 case RTL_GIGA_MAC_VER_21: |
|
4133 case RTL_GIGA_MAC_VER_22: |
|
4134 case RTL_GIGA_MAC_VER_23: |
|
4135 case RTL_GIGA_MAC_VER_24: |
|
4136 case RTL_GIGA_MAC_VER_34: |
|
4137 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
|
4138 break; |
|
4139 default: |
|
4140 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); |
|
4141 break; |
|
4142 } |
|
4143 } |
|
4144 |
|
4145 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
4146 { |
|
4147 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
4148 } |
|
4149 |
|
4150 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4151 { |
|
4152 void __iomem *ioaddr = tp->mmio_addr; |
|
4153 |
|
4154 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4155 rtl_generic_op(tp, tp->jumbo_ops.enable); |
|
4156 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4157 } |
|
4158 |
|
4159 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4160 { |
|
4161 void __iomem *ioaddr = tp->mmio_addr; |
|
4162 |
|
4163 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4164 rtl_generic_op(tp, tp->jumbo_ops.disable); |
|
4165 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4166 } |
|
4167 |
|
4168 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4169 { |
|
4170 void __iomem *ioaddr = tp->mmio_addr; |
|
4171 |
|
4172 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
4173 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); |
|
4174 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
4175 } |
|
4176 |
|
4177 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4178 { |
|
4179 void __iomem *ioaddr = tp->mmio_addr; |
|
4180 |
|
4181 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
4182 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); |
|
4183 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4184 } |
|
4185 |
|
4186 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4187 { |
|
4188 void __iomem *ioaddr = tp->mmio_addr; |
|
4189 |
|
4190 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
4191 } |
|
4192 |
|
4193 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4194 { |
|
4195 void __iomem *ioaddr = tp->mmio_addr; |
|
4196 |
|
4197 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
4198 } |
|
4199 |
|
4200 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4201 { |
|
4202 void __iomem *ioaddr = tp->mmio_addr; |
|
4203 |
|
4204 RTL_W8(MaxTxPacketSize, 0x3f); |
|
4205 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
4206 RTL_W8(Config4, RTL_R8(Config4) | 0x01); |
|
4207 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
4208 } |
|
4209 |
|
4210 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4211 { |
|
4212 void __iomem *ioaddr = tp->mmio_addr; |
|
4213 |
|
4214 RTL_W8(MaxTxPacketSize, 0x0c); |
|
4215 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
4216 RTL_W8(Config4, RTL_R8(Config4) & ~0x01); |
|
4217 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4218 } |
|
4219 |
|
4220 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4221 { |
|
4222 rtl_tx_performance_tweak(tp->pci_dev, |
|
4223 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4224 } |
|
4225 |
|
4226 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4227 { |
|
4228 rtl_tx_performance_tweak(tp->pci_dev, |
|
4229 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4230 } |
|
4231 |
|
4232 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) |
|
4233 { |
|
4234 void __iomem *ioaddr = tp->mmio_addr; |
|
4235 |
|
4236 r8168b_0_hw_jumbo_enable(tp); |
|
4237 |
|
4238 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); |
|
4239 } |
|
4240 |
|
4241 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) |
|
4242 { |
|
4243 void __iomem *ioaddr = tp->mmio_addr; |
|
4244 |
|
4245 r8168b_0_hw_jumbo_disable(tp); |
|
4246 |
|
4247 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
4248 } |
|
4249 |
|
4250 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) |
|
4251 { |
|
4252 struct jumbo_ops *ops = &tp->jumbo_ops; |
|
4253 |
|
4254 switch (tp->mac_version) { |
|
4255 case RTL_GIGA_MAC_VER_11: |
|
4256 ops->disable = r8168b_0_hw_jumbo_disable; |
|
4257 ops->enable = r8168b_0_hw_jumbo_enable; |
|
4258 break; |
|
4259 case RTL_GIGA_MAC_VER_12: |
|
4260 case RTL_GIGA_MAC_VER_17: |
|
4261 ops->disable = r8168b_1_hw_jumbo_disable; |
|
4262 ops->enable = r8168b_1_hw_jumbo_enable; |
|
4263 break; |
|
4264 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ |
|
4265 case RTL_GIGA_MAC_VER_19: |
|
4266 case RTL_GIGA_MAC_VER_20: |
|
4267 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ |
|
4268 case RTL_GIGA_MAC_VER_22: |
|
4269 case RTL_GIGA_MAC_VER_23: |
|
4270 case RTL_GIGA_MAC_VER_24: |
|
4271 case RTL_GIGA_MAC_VER_25: |
|
4272 case RTL_GIGA_MAC_VER_26: |
|
4273 ops->disable = r8168c_hw_jumbo_disable; |
|
4274 ops->enable = r8168c_hw_jumbo_enable; |
|
4275 break; |
|
4276 case RTL_GIGA_MAC_VER_27: |
|
4277 case RTL_GIGA_MAC_VER_28: |
|
4278 ops->disable = r8168dp_hw_jumbo_disable; |
|
4279 ops->enable = r8168dp_hw_jumbo_enable; |
|
4280 break; |
|
4281 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ |
|
4282 case RTL_GIGA_MAC_VER_32: |
|
4283 case RTL_GIGA_MAC_VER_33: |
|
4284 case RTL_GIGA_MAC_VER_34: |
|
4285 ops->disable = r8168e_hw_jumbo_disable; |
|
4286 ops->enable = r8168e_hw_jumbo_enable; |
|
4287 break; |
|
4288 |
|
4289 /* |
|
4290 * No action needed for jumbo frames with 8169. |
|
4291 * No jumbo for 810x at all. |
|
4292 */ |
|
4293 case RTL_GIGA_MAC_VER_40: |
|
4294 case RTL_GIGA_MAC_VER_41: |
|
4295 default: |
|
4296 ops->disable = NULL; |
|
4297 ops->enable = NULL; |
|
4298 break; |
|
4299 } |
|
4300 } |
|
4301 |
|
4302 DECLARE_RTL_COND(rtl_chipcmd_cond) |
|
4303 { |
|
4304 void __iomem *ioaddr = tp->mmio_addr; |
|
4305 |
|
4306 return RTL_R8(ChipCmd) & CmdReset; |
|
4307 } |
|
4308 |
|
4309 static void rtl_hw_reset(struct rtl8169_private *tp) |
|
4310 { |
|
4311 void __iomem *ioaddr = tp->mmio_addr; |
|
4312 |
|
4313 RTL_W8(ChipCmd, CmdReset); |
|
4314 |
|
4315 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
|
4316 } |
|
4317 |
|
4318 static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
|
4319 { |
|
4320 struct rtl_fw *rtl_fw; |
|
4321 const char *name; |
|
4322 int rc = -ENOMEM; |
|
4323 |
|
4324 name = rtl_lookup_firmware_name(tp); |
|
4325 if (!name) |
|
4326 goto out_no_firmware; |
|
4327 |
|
4328 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
|
4329 if (!rtl_fw) |
|
4330 goto err_warn; |
|
4331 |
|
4332 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
|
4333 if (rc < 0) |
|
4334 goto err_free; |
|
4335 |
|
4336 rc = rtl_check_firmware(tp, rtl_fw); |
|
4337 if (rc < 0) |
|
4338 goto err_release_firmware; |
|
4339 |
|
4340 tp->rtl_fw = rtl_fw; |
|
4341 out: |
|
4342 return; |
|
4343 |
|
4344 err_release_firmware: |
|
4345 release_firmware(rtl_fw->fw); |
|
4346 err_free: |
|
4347 kfree(rtl_fw); |
|
4348 err_warn: |
|
4349 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", |
|
4350 name, rc); |
|
4351 out_no_firmware: |
|
4352 tp->rtl_fw = NULL; |
|
4353 goto out; |
|
4354 } |
|
4355 |
|
4356 static void rtl_request_firmware(struct rtl8169_private *tp) |
|
4357 { |
|
4358 if (IS_ERR(tp->rtl_fw)) |
|
4359 rtl_request_uncached_firmware(tp); |
|
4360 } |
|
4361 |
|
4362 static void rtl_rx_close(struct rtl8169_private *tp) |
|
4363 { |
|
4364 void __iomem *ioaddr = tp->mmio_addr; |
|
4365 |
|
4366 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
|
4367 } |
|
4368 |
|
4369 DECLARE_RTL_COND(rtl_npq_cond) |
|
4370 { |
|
4371 void __iomem *ioaddr = tp->mmio_addr; |
|
4372 |
|
4373 return RTL_R8(TxPoll) & NPQ; |
|
4374 } |
|
4375 |
|
4376 DECLARE_RTL_COND(rtl_txcfg_empty_cond) |
|
4377 { |
|
4378 void __iomem *ioaddr = tp->mmio_addr; |
|
4379 |
|
4380 return RTL_R32(TxConfig) & TXCFG_EMPTY; |
|
4381 } |
|
4382 |
|
4383 static void rtl8169_hw_reset(struct rtl8169_private *tp) |
|
4384 { |
|
4385 void __iomem *ioaddr = tp->mmio_addr; |
|
4386 |
|
4387 /* Disable interrupts */ |
|
4388 rtl8169_irq_mask_and_ack(tp); |
|
4389 |
|
4390 rtl_rx_close(tp); |
|
4391 |
|
4392 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4393 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4394 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4395 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
|
4396 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
|
4397 tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
4398 tp->mac_version == RTL_GIGA_MAC_VER_36 || |
|
4399 tp->mac_version == RTL_GIGA_MAC_VER_37 || |
|
4400 tp->mac_version == RTL_GIGA_MAC_VER_40 || |
|
4401 tp->mac_version == RTL_GIGA_MAC_VER_41 || |
|
4402 tp->mac_version == RTL_GIGA_MAC_VER_38) { |
|
4403 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4404 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
|
4405 } else { |
|
4406 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4407 udelay(100); |
|
4408 } |
|
4409 |
|
4410 rtl_hw_reset(tp); |
|
4411 } |
|
4412 |
|
4413 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
4414 { |
|
4415 void __iomem *ioaddr = tp->mmio_addr; |
|
4416 |
|
4417 /* Set DMA burst size and Interframe Gap Time */ |
|
4418 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4419 (InterFrameGap << TxInterFrameGapShift)); |
|
4420 } |
|
4421 |
|
4422 static void rtl_hw_start(struct net_device *dev) |
|
4423 { |
|
4424 struct rtl8169_private *tp = netdev_priv(dev); |
|
4425 |
|
4426 tp->hw_start(dev); |
|
4427 |
|
4428 rtl_irq_enable_all(tp); |
|
4429 } |
|
4430 |
|
4431 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
4432 void __iomem *ioaddr) |
|
4433 { |
|
4434 /* |
|
4435 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
4436 * register to be written before TxDescAddrLow to work. |
|
4437 * Switching from MMIO to I/O access fixes the issue as well. |
|
4438 */ |
|
4439 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
4440 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
4441 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
4442 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
4443 } |
|
4444 |
|
4445 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
4446 { |
|
4447 u16 cmd; |
|
4448 |
|
4449 cmd = RTL_R16(CPlusCmd); |
|
4450 RTL_W16(CPlusCmd, cmd); |
|
4451 return cmd; |
|
4452 } |
|
4453 |
|
4454 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
4455 { |
|
4456 /* Low hurts. Let's disable the filtering. */ |
|
4457 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
4458 } |
|
4459 |
|
4460 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
4461 { |
|
4462 static const struct rtl_cfg2_info { |
|
4463 u32 mac_version; |
|
4464 u32 clk; |
|
4465 u32 val; |
|
4466 } cfg2_info [] = { |
|
4467 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
4468 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
4469 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
4470 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
4471 }; |
|
4472 const struct rtl_cfg2_info *p = cfg2_info; |
|
4473 unsigned int i; |
|
4474 u32 clk; |
|
4475 |
|
4476 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
4477 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
4478 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
4479 RTL_W32(0x7c, p->val); |
|
4480 break; |
|
4481 } |
|
4482 } |
|
4483 } |
|
4484 |
|
4485 static void rtl_set_rx_mode(struct net_device *dev) |
|
4486 { |
|
4487 struct rtl8169_private *tp = netdev_priv(dev); |
|
4488 void __iomem *ioaddr = tp->mmio_addr; |
|
4489 u32 mc_filter[2]; /* Multicast hash filter */ |
|
4490 int rx_mode; |
|
4491 u32 tmp = 0; |
|
4492 |
|
4493 if (dev->flags & IFF_PROMISC) { |
|
4494 /* Unconditionally log net taps. */ |
|
4495 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
|
4496 rx_mode = |
|
4497 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
4498 AcceptAllPhys; |
|
4499 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4500 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
4501 (dev->flags & IFF_ALLMULTI)) { |
|
4502 /* Too many to filter perfectly -- accept all multicasts. */ |
|
4503 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
4504 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4505 } else { |
|
4506 struct netdev_hw_addr *ha; |
|
4507 |
|
4508 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
4509 mc_filter[1] = mc_filter[0] = 0; |
|
4510 netdev_for_each_mc_addr(ha, dev) { |
|
4511 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
4512 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
4513 rx_mode |= AcceptMulticast; |
|
4514 } |
|
4515 } |
|
4516 |
|
4517 if (dev->features & NETIF_F_RXALL) |
|
4518 rx_mode |= (AcceptErr | AcceptRunt); |
|
4519 |
|
4520 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
|
4521 |
|
4522 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
4523 u32 data = mc_filter[0]; |
|
4524 |
|
4525 mc_filter[0] = swab32(mc_filter[1]); |
|
4526 mc_filter[1] = swab32(data); |
|
4527 } |
|
4528 |
|
4529 if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
|
4530 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4531 |
|
4532 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
4533 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
4534 |
|
4535 RTL_W32(RxConfig, tmp); |
|
4536 } |
|
4537 |
|
4538 static void rtl_hw_start_8169(struct net_device *dev) |
|
4539 { |
|
4540 struct rtl8169_private *tp = netdev_priv(dev); |
|
4541 void __iomem *ioaddr = tp->mmio_addr; |
|
4542 struct pci_dev *pdev = tp->pci_dev; |
|
4543 |
|
4544 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
4545 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
4546 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
4547 } |
|
4548 |
|
4549 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4550 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4551 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4552 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4553 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4554 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4555 |
|
4556 rtl_init_rxcfg(tp); |
|
4557 |
|
4558 RTL_W8(EarlyTxThres, NoEarlyTx); |
|
4559 |
|
4560 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4561 |
|
4562 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4563 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4564 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4565 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4566 rtl_set_rx_tx_config_registers(tp); |
|
4567 |
|
4568 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
4569 |
|
4570 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4571 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
4572 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
4573 "Bit-3 and bit-14 MUST be 1\n"); |
|
4574 tp->cp_cmd |= (1 << 14); |
|
4575 } |
|
4576 |
|
4577 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4578 |
|
4579 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
4580 |
|
4581 /* |
|
4582 * Undocumented corner. Supposedly: |
|
4583 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
4584 */ |
|
4585 RTL_W16(IntrMitigate, 0x0000); |
|
4586 |
|
4587 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4588 |
|
4589 if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
|
4590 tp->mac_version != RTL_GIGA_MAC_VER_02 && |
|
4591 tp->mac_version != RTL_GIGA_MAC_VER_03 && |
|
4592 tp->mac_version != RTL_GIGA_MAC_VER_04) { |
|
4593 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4594 rtl_set_rx_tx_config_registers(tp); |
|
4595 } |
|
4596 |
|
4597 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4598 |
|
4599 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
4600 RTL_R8(IntrMask); |
|
4601 |
|
4602 RTL_W32(RxMissed, 0); |
|
4603 |
|
4604 rtl_set_rx_mode(dev); |
|
4605 |
|
4606 /* no early-rx interrupts */ |
|
4607 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4608 } |
|
4609 |
|
4610 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
|
4611 { |
|
4612 if (tp->csi_ops.write) |
|
4613 tp->csi_ops.write(tp, addr, value); |
|
4614 } |
|
4615 |
|
4616 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) |
|
4617 { |
|
4618 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0; |
|
4619 } |
|
4620 |
|
4621 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) |
|
4622 { |
|
4623 u32 csi; |
|
4624 |
|
4625 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; |
|
4626 rtl_csi_write(tp, 0x070c, csi | bits); |
|
4627 } |
|
4628 |
|
4629 static void rtl_csi_access_enable_1(struct rtl8169_private *tp) |
|
4630 { |
|
4631 rtl_csi_access_enable(tp, 0x17000000); |
|
4632 } |
|
4633 |
|
4634 static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
|
4635 { |
|
4636 rtl_csi_access_enable(tp, 0x27000000); |
|
4637 } |
|
4638 |
|
4639 DECLARE_RTL_COND(rtl_csiar_cond) |
|
4640 { |
|
4641 void __iomem *ioaddr = tp->mmio_addr; |
|
4642 |
|
4643 return RTL_R32(CSIAR) & CSIAR_FLAG; |
|
4644 } |
|
4645 |
|
4646 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value) |
|
4647 { |
|
4648 void __iomem *ioaddr = tp->mmio_addr; |
|
4649 |
|
4650 RTL_W32(CSIDR, value); |
|
4651 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
4652 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
4653 |
|
4654 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
|
4655 } |
|
4656 |
|
4657 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr) |
|
4658 { |
|
4659 void __iomem *ioaddr = tp->mmio_addr; |
|
4660 |
|
4661 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
4662 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
4663 |
|
4664 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
|
4665 RTL_R32(CSIDR) : ~0; |
|
4666 } |
|
4667 |
|
4668 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value) |
|
4669 { |
|
4670 void __iomem *ioaddr = tp->mmio_addr; |
|
4671 |
|
4672 RTL_W32(CSIDR, value); |
|
4673 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
4674 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | |
|
4675 CSIAR_FUNC_NIC); |
|
4676 |
|
4677 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
|
4678 } |
|
4679 |
|
4680 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr) |
|
4681 { |
|
4682 void __iomem *ioaddr = tp->mmio_addr; |
|
4683 |
|
4684 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | |
|
4685 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
4686 |
|
4687 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
|
4688 RTL_R32(CSIDR) : ~0; |
|
4689 } |
|
4690 |
|
4691 static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp) |
|
4692 { |
|
4693 struct csi_ops *ops = &tp->csi_ops; |
|
4694 |
|
4695 switch (tp->mac_version) { |
|
4696 case RTL_GIGA_MAC_VER_01: |
|
4697 case RTL_GIGA_MAC_VER_02: |
|
4698 case RTL_GIGA_MAC_VER_03: |
|
4699 case RTL_GIGA_MAC_VER_04: |
|
4700 case RTL_GIGA_MAC_VER_05: |
|
4701 case RTL_GIGA_MAC_VER_06: |
|
4702 case RTL_GIGA_MAC_VER_10: |
|
4703 case RTL_GIGA_MAC_VER_11: |
|
4704 case RTL_GIGA_MAC_VER_12: |
|
4705 case RTL_GIGA_MAC_VER_13: |
|
4706 case RTL_GIGA_MAC_VER_14: |
|
4707 case RTL_GIGA_MAC_VER_15: |
|
4708 case RTL_GIGA_MAC_VER_16: |
|
4709 case RTL_GIGA_MAC_VER_17: |
|
4710 ops->write = NULL; |
|
4711 ops->read = NULL; |
|
4712 break; |
|
4713 |
|
4714 case RTL_GIGA_MAC_VER_37: |
|
4715 case RTL_GIGA_MAC_VER_38: |
|
4716 ops->write = r8402_csi_write; |
|
4717 ops->read = r8402_csi_read; |
|
4718 break; |
|
4719 |
|
4720 default: |
|
4721 ops->write = r8169_csi_write; |
|
4722 ops->read = r8169_csi_read; |
|
4723 break; |
|
4724 } |
|
4725 } |
|
4726 |
|
4727 struct ephy_info { |
|
4728 unsigned int offset; |
|
4729 u16 mask; |
|
4730 u16 bits; |
|
4731 }; |
|
4732 |
|
4733 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
|
4734 int len) |
|
4735 { |
|
4736 u16 w; |
|
4737 |
|
4738 while (len-- > 0) { |
|
4739 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
|
4740 rtl_ephy_write(tp, e->offset, w); |
|
4741 e++; |
|
4742 } |
|
4743 } |
|
4744 |
|
4745 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
4746 { |
|
4747 int cap = pci_pcie_cap(pdev); |
|
4748 |
|
4749 if (cap) { |
|
4750 u16 ctl; |
|
4751 |
|
4752 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4753 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4754 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4755 } |
|
4756 } |
|
4757 |
|
4758 static void rtl_enable_clock_request(struct pci_dev *pdev) |
|
4759 { |
|
4760 int cap = pci_pcie_cap(pdev); |
|
4761 |
|
4762 if (cap) { |
|
4763 u16 ctl; |
|
4764 |
|
4765 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4766 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4767 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4768 } |
|
4769 } |
|
4770 |
|
4771 #define R8168_CPCMD_QUIRK_MASK (\ |
|
4772 EnableBist | \ |
|
4773 Mac_dbgo_oe | \ |
|
4774 Force_half_dup | \ |
|
4775 Force_rxflow_en | \ |
|
4776 Force_txflow_en | \ |
|
4777 Cxpl_dbg_sel | \ |
|
4778 ASF | \ |
|
4779 PktCntrDisable | \ |
|
4780 Mac_dbgo_sel) |
|
4781 |
|
4782 static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
|
4783 { |
|
4784 void __iomem *ioaddr = tp->mmio_addr; |
|
4785 struct pci_dev *pdev = tp->pci_dev; |
|
4786 |
|
4787 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4788 |
|
4789 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4790 |
|
4791 rtl_tx_performance_tweak(pdev, |
|
4792 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4793 } |
|
4794 |
|
4795 static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
|
4796 { |
|
4797 void __iomem *ioaddr = tp->mmio_addr; |
|
4798 |
|
4799 rtl_hw_start_8168bb(tp); |
|
4800 |
|
4801 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4802 |
|
4803 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
4804 } |
|
4805 |
|
4806 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
|
4807 { |
|
4808 void __iomem *ioaddr = tp->mmio_addr; |
|
4809 struct pci_dev *pdev = tp->pci_dev; |
|
4810 |
|
4811 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
4812 |
|
4813 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4814 |
|
4815 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4816 |
|
4817 rtl_disable_clock_request(pdev); |
|
4818 |
|
4819 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4820 } |
|
4821 |
|
4822 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
|
4823 { |
|
4824 static const struct ephy_info e_info_8168cp[] = { |
|
4825 { 0x01, 0, 0x0001 }, |
|
4826 { 0x02, 0x0800, 0x1000 }, |
|
4827 { 0x03, 0, 0x0042 }, |
|
4828 { 0x06, 0x0080, 0x0000 }, |
|
4829 { 0x07, 0, 0x2000 } |
|
4830 }; |
|
4831 |
|
4832 rtl_csi_access_enable_2(tp); |
|
4833 |
|
4834 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
4835 |
|
4836 __rtl_hw_start_8168cp(tp); |
|
4837 } |
|
4838 |
|
4839 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
|
4840 { |
|
4841 void __iomem *ioaddr = tp->mmio_addr; |
|
4842 struct pci_dev *pdev = tp->pci_dev; |
|
4843 |
|
4844 rtl_csi_access_enable_2(tp); |
|
4845 |
|
4846 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4847 |
|
4848 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4849 |
|
4850 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4851 } |
|
4852 |
|
4853 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
|
4854 { |
|
4855 void __iomem *ioaddr = tp->mmio_addr; |
|
4856 struct pci_dev *pdev = tp->pci_dev; |
|
4857 |
|
4858 rtl_csi_access_enable_2(tp); |
|
4859 |
|
4860 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4861 |
|
4862 /* Magic. */ |
|
4863 RTL_W8(DBG_REG, 0x20); |
|
4864 |
|
4865 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4866 |
|
4867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4868 |
|
4869 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4870 } |
|
4871 |
|
4872 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
|
4873 { |
|
4874 void __iomem *ioaddr = tp->mmio_addr; |
|
4875 static const struct ephy_info e_info_8168c_1[] = { |
|
4876 { 0x02, 0x0800, 0x1000 }, |
|
4877 { 0x03, 0, 0x0002 }, |
|
4878 { 0x06, 0x0080, 0x0000 } |
|
4879 }; |
|
4880 |
|
4881 rtl_csi_access_enable_2(tp); |
|
4882 |
|
4883 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
4884 |
|
4885 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
4886 |
|
4887 __rtl_hw_start_8168cp(tp); |
|
4888 } |
|
4889 |
|
4890 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
|
4891 { |
|
4892 static const struct ephy_info e_info_8168c_2[] = { |
|
4893 { 0x01, 0, 0x0001 }, |
|
4894 { 0x03, 0x0400, 0x0220 } |
|
4895 }; |
|
4896 |
|
4897 rtl_csi_access_enable_2(tp); |
|
4898 |
|
4899 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
4900 |
|
4901 __rtl_hw_start_8168cp(tp); |
|
4902 } |
|
4903 |
|
4904 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
|
4905 { |
|
4906 rtl_hw_start_8168c_2(tp); |
|
4907 } |
|
4908 |
|
4909 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
|
4910 { |
|
4911 rtl_csi_access_enable_2(tp); |
|
4912 |
|
4913 __rtl_hw_start_8168cp(tp); |
|
4914 } |
|
4915 |
|
4916 static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
|
4917 { |
|
4918 void __iomem *ioaddr = tp->mmio_addr; |
|
4919 struct pci_dev *pdev = tp->pci_dev; |
|
4920 |
|
4921 rtl_csi_access_enable_2(tp); |
|
4922 |
|
4923 rtl_disable_clock_request(pdev); |
|
4924 |
|
4925 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4926 |
|
4927 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4928 |
|
4929 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4930 } |
|
4931 |
|
4932 static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
|
4933 { |
|
4934 void __iomem *ioaddr = tp->mmio_addr; |
|
4935 struct pci_dev *pdev = tp->pci_dev; |
|
4936 |
|
4937 rtl_csi_access_enable_1(tp); |
|
4938 |
|
4939 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4940 |
|
4941 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4942 |
|
4943 rtl_disable_clock_request(pdev); |
|
4944 } |
|
4945 |
|
4946 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
|
4947 { |
|
4948 void __iomem *ioaddr = tp->mmio_addr; |
|
4949 struct pci_dev *pdev = tp->pci_dev; |
|
4950 static const struct ephy_info e_info_8168d_4[] = { |
|
4951 { 0x0b, ~0, 0x48 }, |
|
4952 { 0x19, 0x20, 0x50 }, |
|
4953 { 0x0c, ~0, 0x20 } |
|
4954 }; |
|
4955 int i; |
|
4956 |
|
4957 rtl_csi_access_enable_1(tp); |
|
4958 |
|
4959 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4960 |
|
4961 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4962 |
|
4963 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { |
|
4964 const struct ephy_info *e = e_info_8168d_4 + i; |
|
4965 u16 w; |
|
4966 |
|
4967 w = rtl_ephy_read(tp, e->offset); |
|
4968 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); |
|
4969 } |
|
4970 |
|
4971 rtl_enable_clock_request(pdev); |
|
4972 } |
|
4973 |
|
4974 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
|
4975 { |
|
4976 void __iomem *ioaddr = tp->mmio_addr; |
|
4977 struct pci_dev *pdev = tp->pci_dev; |
|
4978 static const struct ephy_info e_info_8168e_1[] = { |
|
4979 { 0x00, 0x0200, 0x0100 }, |
|
4980 { 0x00, 0x0000, 0x0004 }, |
|
4981 { 0x06, 0x0002, 0x0001 }, |
|
4982 { 0x06, 0x0000, 0x0030 }, |
|
4983 { 0x07, 0x0000, 0x2000 }, |
|
4984 { 0x00, 0x0000, 0x0020 }, |
|
4985 { 0x03, 0x5800, 0x2000 }, |
|
4986 { 0x03, 0x0000, 0x0001 }, |
|
4987 { 0x01, 0x0800, 0x1000 }, |
|
4988 { 0x07, 0x0000, 0x4000 }, |
|
4989 { 0x1e, 0x0000, 0x2000 }, |
|
4990 { 0x19, 0xffff, 0xfe6c }, |
|
4991 { 0x0a, 0x0000, 0x0040 } |
|
4992 }; |
|
4993 |
|
4994 rtl_csi_access_enable_2(tp); |
|
4995 |
|
4996 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
|
4997 |
|
4998 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4999 |
|
5000 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
5001 |
|
5002 rtl_disable_clock_request(pdev); |
|
5003 |
|
5004 /* Reset tx FIFO pointer */ |
|
5005 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
|
5006 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); |
|
5007 |
|
5008 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
5009 } |
|
5010 |
|
5011 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
|
5012 { |
|
5013 void __iomem *ioaddr = tp->mmio_addr; |
|
5014 struct pci_dev *pdev = tp->pci_dev; |
|
5015 static const struct ephy_info e_info_8168e_2[] = { |
|
5016 { 0x09, 0x0000, 0x0080 }, |
|
5017 { 0x19, 0x0000, 0x0224 } |
|
5018 }; |
|
5019 |
|
5020 rtl_csi_access_enable_1(tp); |
|
5021 |
|
5022 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
|
5023 |
|
5024 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5025 |
|
5026 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5027 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5028 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
5029 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
5030 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
5031 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); |
|
5032 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
5033 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
|
5034 |
|
5035 RTL_W8(MaxTxPacketSize, EarlySize); |
|
5036 |
|
5037 rtl_disable_clock_request(pdev); |
|
5038 |
|
5039 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
5040 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
5041 |
|
5042 /* Adjust EEE LED frequency */ |
|
5043 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
5044 |
|
5045 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
5046 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
5047 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
5048 } |
|
5049 |
|
5050 static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
|
5051 { |
|
5052 void __iomem *ioaddr = tp->mmio_addr; |
|
5053 struct pci_dev *pdev = tp->pci_dev; |
|
5054 |
|
5055 rtl_csi_access_enable_2(tp); |
|
5056 |
|
5057 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5058 |
|
5059 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5060 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5061 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
5062 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
5063 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
5064 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
5065 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
5066 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
5067 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
5068 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); |
|
5069 |
|
5070 RTL_W8(MaxTxPacketSize, EarlySize); |
|
5071 |
|
5072 rtl_disable_clock_request(pdev); |
|
5073 |
|
5074 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
5075 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
5076 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
5077 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
5078 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
5079 } |
|
5080 |
|
5081 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
|
5082 { |
|
5083 void __iomem *ioaddr = tp->mmio_addr; |
|
5084 static const struct ephy_info e_info_8168f_1[] = { |
|
5085 { 0x06, 0x00c0, 0x0020 }, |
|
5086 { 0x08, 0x0001, 0x0002 }, |
|
5087 { 0x09, 0x0000, 0x0080 }, |
|
5088 { 0x19, 0x0000, 0x0224 } |
|
5089 }; |
|
5090 |
|
5091 rtl_hw_start_8168f(tp); |
|
5092 |
|
5093 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
|
5094 |
|
5095 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
|
5096 |
|
5097 /* Adjust EEE LED frequency */ |
|
5098 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
5099 } |
|
5100 |
|
5101 static void rtl_hw_start_8411(struct rtl8169_private *tp) |
|
5102 { |
|
5103 static const struct ephy_info e_info_8168f_1[] = { |
|
5104 { 0x06, 0x00c0, 0x0020 }, |
|
5105 { 0x0f, 0xffff, 0x5200 }, |
|
5106 { 0x1e, 0x0000, 0x4000 }, |
|
5107 { 0x19, 0x0000, 0x0224 } |
|
5108 }; |
|
5109 |
|
5110 rtl_hw_start_8168f(tp); |
|
5111 |
|
5112 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
|
5113 |
|
5114 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
|
5115 } |
|
5116 |
|
5117 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
|
5118 { |
|
5119 void __iomem *ioaddr = tp->mmio_addr; |
|
5120 struct pci_dev *pdev = tp->pci_dev; |
|
5121 |
|
5122 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC); |
|
5123 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); |
|
5124 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); |
|
5125 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
5126 |
|
5127 rtl_csi_access_enable_1(tp); |
|
5128 |
|
5129 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5130 |
|
5131 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
5132 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
5133 |
|
5134 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
5135 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
|
5136 RTL_W8(MaxTxPacketSize, EarlySize); |
|
5137 |
|
5138 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5139 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5140 |
|
5141 /* Adjust EEE LED frequency */ |
|
5142 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
5143 |
|
5144 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC); |
|
5145 } |
|
5146 |
|
5147 static void rtl_hw_start_8168(struct net_device *dev) |
|
5148 { |
|
5149 struct rtl8169_private *tp = netdev_priv(dev); |
|
5150 void __iomem *ioaddr = tp->mmio_addr; |
|
5151 |
|
5152 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
5153 |
|
5154 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
5155 |
|
5156 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
5157 |
|
5158 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
5159 |
|
5160 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5161 |
|
5162 RTL_W16(IntrMitigate, 0x5151); |
|
5163 |
|
5164 /* Work around for RxFIFO overflow. */ |
|
5165 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
5166 tp->event_slow |= RxFIFOOver | PCSTimeout; |
|
5167 tp->event_slow &= ~RxOverflow; |
|
5168 } |
|
5169 |
|
5170 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
5171 |
|
5172 rtl_set_rx_mode(dev); |
|
5173 |
|
5174 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
5175 (InterFrameGap << TxInterFrameGapShift)); |
|
5176 |
|
5177 RTL_R8(IntrMask); |
|
5178 |
|
5179 switch (tp->mac_version) { |
|
5180 case RTL_GIGA_MAC_VER_11: |
|
5181 rtl_hw_start_8168bb(tp); |
|
5182 break; |
|
5183 |
|
5184 case RTL_GIGA_MAC_VER_12: |
|
5185 case RTL_GIGA_MAC_VER_17: |
|
5186 rtl_hw_start_8168bef(tp); |
|
5187 break; |
|
5188 |
|
5189 case RTL_GIGA_MAC_VER_18: |
|
5190 rtl_hw_start_8168cp_1(tp); |
|
5191 break; |
|
5192 |
|
5193 case RTL_GIGA_MAC_VER_19: |
|
5194 rtl_hw_start_8168c_1(tp); |
|
5195 break; |
|
5196 |
|
5197 case RTL_GIGA_MAC_VER_20: |
|
5198 rtl_hw_start_8168c_2(tp); |
|
5199 break; |
|
5200 |
|
5201 case RTL_GIGA_MAC_VER_21: |
|
5202 rtl_hw_start_8168c_3(tp); |
|
5203 break; |
|
5204 |
|
5205 case RTL_GIGA_MAC_VER_22: |
|
5206 rtl_hw_start_8168c_4(tp); |
|
5207 break; |
|
5208 |
|
5209 case RTL_GIGA_MAC_VER_23: |
|
5210 rtl_hw_start_8168cp_2(tp); |
|
5211 break; |
|
5212 |
|
5213 case RTL_GIGA_MAC_VER_24: |
|
5214 rtl_hw_start_8168cp_3(tp); |
|
5215 break; |
|
5216 |
|
5217 case RTL_GIGA_MAC_VER_25: |
|
5218 case RTL_GIGA_MAC_VER_26: |
|
5219 case RTL_GIGA_MAC_VER_27: |
|
5220 rtl_hw_start_8168d(tp); |
|
5221 break; |
|
5222 |
|
5223 case RTL_GIGA_MAC_VER_28: |
|
5224 rtl_hw_start_8168d_4(tp); |
|
5225 break; |
|
5226 |
|
5227 case RTL_GIGA_MAC_VER_31: |
|
5228 rtl_hw_start_8168dp(tp); |
|
5229 break; |
|
5230 |
|
5231 case RTL_GIGA_MAC_VER_32: |
|
5232 case RTL_GIGA_MAC_VER_33: |
|
5233 rtl_hw_start_8168e_1(tp); |
|
5234 break; |
|
5235 case RTL_GIGA_MAC_VER_34: |
|
5236 rtl_hw_start_8168e_2(tp); |
|
5237 break; |
|
5238 |
|
5239 case RTL_GIGA_MAC_VER_35: |
|
5240 case RTL_GIGA_MAC_VER_36: |
|
5241 rtl_hw_start_8168f_1(tp); |
|
5242 break; |
|
5243 |
|
5244 case RTL_GIGA_MAC_VER_38: |
|
5245 rtl_hw_start_8411(tp); |
|
5246 break; |
|
5247 |
|
5248 case RTL_GIGA_MAC_VER_40: |
|
5249 case RTL_GIGA_MAC_VER_41: |
|
5250 rtl_hw_start_8168g_1(tp); |
|
5251 break; |
|
5252 |
|
5253 default: |
|
5254 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
5255 dev->name, tp->mac_version); |
|
5256 break; |
|
5257 } |
|
5258 |
|
5259 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
5260 |
|
5261 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
5262 |
|
5263 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
5264 } |
|
5265 |
|
5266 #define R810X_CPCMD_QUIRK_MASK (\ |
|
5267 EnableBist | \ |
|
5268 Mac_dbgo_oe | \ |
|
5269 Force_half_dup | \ |
|
5270 Force_rxflow_en | \ |
|
5271 Force_txflow_en | \ |
|
5272 Cxpl_dbg_sel | \ |
|
5273 ASF | \ |
|
5274 PktCntrDisable | \ |
|
5275 Mac_dbgo_sel) |
|
5276 |
|
5277 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
|
5278 { |
|
5279 void __iomem *ioaddr = tp->mmio_addr; |
|
5280 struct pci_dev *pdev = tp->pci_dev; |
|
5281 static const struct ephy_info e_info_8102e_1[] = { |
|
5282 { 0x01, 0, 0x6e65 }, |
|
5283 { 0x02, 0, 0x091f }, |
|
5284 { 0x03, 0, 0xc2f9 }, |
|
5285 { 0x06, 0, 0xafb5 }, |
|
5286 { 0x07, 0, 0x0e00 }, |
|
5287 { 0x19, 0, 0xec80 }, |
|
5288 { 0x01, 0, 0x2e65 }, |
|
5289 { 0x01, 0, 0x6e65 } |
|
5290 }; |
|
5291 u8 cfg1; |
|
5292 |
|
5293 rtl_csi_access_enable_2(tp); |
|
5294 |
|
5295 RTL_W8(DBG_REG, FIX_NAK_1); |
|
5296 |
|
5297 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5298 |
|
5299 RTL_W8(Config1, |
|
5300 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
5301 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
5302 |
|
5303 cfg1 = RTL_R8(Config1); |
|
5304 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
5305 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
5306 |
|
5307 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
5308 } |
|
5309 |
|
5310 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
|
5311 { |
|
5312 void __iomem *ioaddr = tp->mmio_addr; |
|
5313 struct pci_dev *pdev = tp->pci_dev; |
|
5314 |
|
5315 rtl_csi_access_enable_2(tp); |
|
5316 |
|
5317 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5318 |
|
5319 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
5320 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
5321 } |
|
5322 |
|
5323 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
|
5324 { |
|
5325 rtl_hw_start_8102e_2(tp); |
|
5326 |
|
5327 rtl_ephy_write(tp, 0x03, 0xc2f9); |
|
5328 } |
|
5329 |
|
5330 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
|
5331 { |
|
5332 void __iomem *ioaddr = tp->mmio_addr; |
|
5333 static const struct ephy_info e_info_8105e_1[] = { |
|
5334 { 0x07, 0, 0x4000 }, |
|
5335 { 0x19, 0, 0x0200 }, |
|
5336 { 0x19, 0, 0x0020 }, |
|
5337 { 0x1e, 0, 0x2000 }, |
|
5338 { 0x03, 0, 0x0001 }, |
|
5339 { 0x19, 0, 0x0100 }, |
|
5340 { 0x19, 0, 0x0004 }, |
|
5341 { 0x0a, 0, 0x0020 } |
|
5342 }; |
|
5343 |
|
5344 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
5345 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
5346 |
|
5347 /* Disable Early Tally Counter */ |
|
5348 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
|
5349 |
|
5350 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
|
5351 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
5352 |
|
5353 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
|
5354 } |
|
5355 |
|
5356 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
|
5357 { |
|
5358 rtl_hw_start_8105e_1(tp); |
|
5359 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
|
5360 } |
|
5361 |
|
5362 static void rtl_hw_start_8402(struct rtl8169_private *tp) |
|
5363 { |
|
5364 void __iomem *ioaddr = tp->mmio_addr; |
|
5365 static const struct ephy_info e_info_8402[] = { |
|
5366 { 0x19, 0xffff, 0xff64 }, |
|
5367 { 0x1e, 0, 0x4000 } |
|
5368 }; |
|
5369 |
|
5370 rtl_csi_access_enable_2(tp); |
|
5371 |
|
5372 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
5373 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
5374 |
|
5375 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
5376 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
5377 |
|
5378 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
|
5379 |
|
5380 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
5381 |
|
5382 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
|
5383 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); |
|
5384 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
5385 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
5386 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5387 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
5388 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); |
|
5389 } |
|
5390 |
|
5391 static void rtl_hw_start_8106(struct rtl8169_private *tp) |
|
5392 { |
|
5393 void __iomem *ioaddr = tp->mmio_addr; |
|
5394 |
|
5395 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
5396 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
5397 |
|
5398 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
|
5399 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
|
5400 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); |
|
5401 } |
|
5402 |
|
5403 static void rtl_hw_start_8101(struct net_device *dev) |
|
5404 { |
|
5405 struct rtl8169_private *tp = netdev_priv(dev); |
|
5406 void __iomem *ioaddr = tp->mmio_addr; |
|
5407 struct pci_dev *pdev = tp->pci_dev; |
|
5408 |
|
5409 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
|
5410 tp->event_slow &= ~RxFIFOOver; |
|
5411 |
|
5412 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
|
5413 tp->mac_version == RTL_GIGA_MAC_VER_16) { |
|
5414 int cap = pci_pcie_cap(pdev); |
|
5415 |
|
5416 if (cap) { |
|
5417 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
5418 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
5419 } |
|
5420 } |
|
5421 |
|
5422 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
5423 |
|
5424 switch (tp->mac_version) { |
|
5425 case RTL_GIGA_MAC_VER_07: |
|
5426 rtl_hw_start_8102e_1(tp); |
|
5427 break; |
|
5428 |
|
5429 case RTL_GIGA_MAC_VER_08: |
|
5430 rtl_hw_start_8102e_3(tp); |
|
5431 break; |
|
5432 |
|
5433 case RTL_GIGA_MAC_VER_09: |
|
5434 rtl_hw_start_8102e_2(tp); |
|
5435 break; |
|
5436 |
|
5437 case RTL_GIGA_MAC_VER_29: |
|
5438 rtl_hw_start_8105e_1(tp); |
|
5439 break; |
|
5440 case RTL_GIGA_MAC_VER_30: |
|
5441 rtl_hw_start_8105e_2(tp); |
|
5442 break; |
|
5443 |
|
5444 case RTL_GIGA_MAC_VER_37: |
|
5445 rtl_hw_start_8402(tp); |
|
5446 break; |
|
5447 |
|
5448 case RTL_GIGA_MAC_VER_39: |
|
5449 rtl_hw_start_8106(tp); |
|
5450 break; |
|
5451 } |
|
5452 |
|
5453 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
5454 |
|
5455 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
5456 |
|
5457 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
5458 |
|
5459 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
|
5460 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5461 |
|
5462 RTL_W16(IntrMitigate, 0x0000); |
|
5463 |
|
5464 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
5465 |
|
5466 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
5467 rtl_set_rx_tx_config_registers(tp); |
|
5468 |
|
5469 RTL_R8(IntrMask); |
|
5470 |
|
5471 rtl_set_rx_mode(dev); |
|
5472 |
|
5473 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
5474 } |
|
5475 |
|
5476 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
5477 { |
|
5478 struct rtl8169_private *tp = netdev_priv(dev); |
|
5479 |
|
5480 if (new_mtu < ETH_ZLEN || |
|
5481 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) |
|
5482 return -EINVAL; |
|
5483 |
|
5484 if (new_mtu > ETH_DATA_LEN) |
|
5485 rtl_hw_jumbo_enable(tp); |
|
5486 else |
|
5487 rtl_hw_jumbo_disable(tp); |
|
5488 |
|
5489 dev->mtu = new_mtu; |
|
5490 netdev_update_features(dev); |
|
5491 |
|
5492 return 0; |
|
5493 } |
|
5494 |
|
5495 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
5496 { |
|
5497 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
5498 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
5499 } |
|
5500 |
|
5501 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
|
5502 void **data_buff, struct RxDesc *desc) |
|
5503 { |
|
5504 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
|
5505 DMA_FROM_DEVICE); |
|
5506 |
|
5507 kfree(*data_buff); |
|
5508 *data_buff = NULL; |
|
5509 rtl8169_make_unusable_by_asic(desc); |
|
5510 } |
|
5511 |
|
5512 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
5513 { |
|
5514 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
5515 |
|
5516 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
5517 } |
|
5518 |
|
5519 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
5520 u32 rx_buf_sz) |
|
5521 { |
|
5522 desc->addr = cpu_to_le64(mapping); |
|
5523 wmb(); |
|
5524 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5525 } |
|
5526 |
|
5527 static inline void *rtl8169_align(void *data) |
|
5528 { |
|
5529 return (void *)ALIGN((long)data, 16); |
|
5530 } |
|
5531 |
|
5532 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
|
5533 struct RxDesc *desc) |
|
5534 { |
|
5535 void *data; |
|
5536 dma_addr_t mapping; |
|
5537 struct device *d = &tp->pci_dev->dev; |
|
5538 struct net_device *dev = tp->dev; |
|
5539 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
|
5540 |
|
5541 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
|
5542 if (!data) |
|
5543 return NULL; |
|
5544 |
|
5545 if (rtl8169_align(data) != data) { |
|
5546 kfree(data); |
|
5547 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); |
|
5548 if (!data) |
|
5549 return NULL; |
|
5550 } |
|
5551 |
|
5552 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
|
5553 DMA_FROM_DEVICE); |
|
5554 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5555 if (net_ratelimit()) |
|
5556 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); |
|
5557 goto err_out; |
|
5558 } |
|
5559 |
|
5560 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
5561 return data; |
|
5562 |
|
5563 err_out: |
|
5564 kfree(data); |
|
5565 return NULL; |
|
5566 } |
|
5567 |
|
5568 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
5569 { |
|
5570 unsigned int i; |
|
5571 |
|
5572 for (i = 0; i < NUM_RX_DESC; i++) { |
|
5573 if (tp->Rx_databuff[i]) { |
|
5574 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, |
|
5575 tp->RxDescArray + i); |
|
5576 } |
|
5577 } |
|
5578 } |
|
5579 |
|
5580 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
5581 { |
|
5582 desc->opts1 |= cpu_to_le32(RingEnd); |
|
5583 } |
|
5584 |
|
5585 static int rtl8169_rx_fill(struct rtl8169_private *tp) |
|
5586 { |
|
5587 unsigned int i; |
|
5588 |
|
5589 for (i = 0; i < NUM_RX_DESC; i++) { |
|
5590 void *data; |
|
5591 |
|
5592 if (tp->Rx_databuff[i]) |
|
5593 continue; |
|
5594 |
|
5595 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
|
5596 if (!data) { |
|
5597 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); |
|
5598 goto err_out; |
|
5599 } |
|
5600 tp->Rx_databuff[i] = data; |
|
5601 } |
|
5602 |
|
5603 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
5604 return 0; |
|
5605 |
|
5606 err_out: |
|
5607 rtl8169_rx_clear(tp); |
|
5608 return -ENOMEM; |
|
5609 } |
|
5610 |
|
5611 static int rtl8169_init_ring(struct net_device *dev) |
|
5612 { |
|
5613 struct rtl8169_private *tp = netdev_priv(dev); |
|
5614 |
|
5615 rtl8169_init_ring_indexes(tp); |
|
5616 |
|
5617 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
5618 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
|
5619 |
|
5620 return rtl8169_rx_fill(tp); |
|
5621 } |
|
5622 |
|
5623 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
|
5624 struct TxDesc *desc) |
|
5625 { |
|
5626 unsigned int len = tx_skb->len; |
|
5627 |
|
5628 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
|
5629 |
|
5630 desc->opts1 = 0x00; |
|
5631 desc->opts2 = 0x00; |
|
5632 desc->addr = 0x00; |
|
5633 tx_skb->len = 0; |
|
5634 } |
|
5635 |
|
5636 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
|
5637 unsigned int n) |
|
5638 { |
|
5639 unsigned int i; |
|
5640 |
|
5641 for (i = 0; i < n; i++) { |
|
5642 unsigned int entry = (start + i) % NUM_TX_DESC; |
|
5643 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5644 unsigned int len = tx_skb->len; |
|
5645 |
|
5646 if (len) { |
|
5647 struct sk_buff *skb = tx_skb->skb; |
|
5648 |
|
5649 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5650 tp->TxDescArray + entry); |
|
5651 if (skb) { |
|
5652 tp->dev->stats.tx_dropped++; |
|
5653 dev_kfree_skb(skb); |
|
5654 tx_skb->skb = NULL; |
|
5655 } |
|
5656 } |
|
5657 } |
|
5658 } |
|
5659 |
|
5660 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
5661 { |
|
5662 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); |
|
5663 tp->cur_tx = tp->dirty_tx = 0; |
|
5664 } |
|
5665 |
|
5666 static void rtl_reset_work(struct rtl8169_private *tp) |
|
5667 { |
|
5668 struct net_device *dev = tp->dev; |
|
5669 int i; |
|
5670 |
|
5671 napi_disable(&tp->napi); |
|
5672 netif_stop_queue(dev); |
|
5673 synchronize_sched(); |
|
5674 |
|
5675 rtl8169_hw_reset(tp); |
|
5676 |
|
5677 for (i = 0; i < NUM_RX_DESC; i++) |
|
5678 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); |
|
5679 |
|
5680 rtl8169_tx_clear(tp); |
|
5681 rtl8169_init_ring_indexes(tp); |
|
5682 |
|
5683 napi_enable(&tp->napi); |
|
5684 rtl_hw_start(dev); |
|
5685 netif_wake_queue(dev); |
|
5686 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
5687 } |
|
5688 |
|
5689 static void rtl8169_tx_timeout(struct net_device *dev) |
|
5690 { |
|
5691 struct rtl8169_private *tp = netdev_priv(dev); |
|
5692 |
|
5693 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5694 } |
|
5695 |
|
5696 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
5697 u32 *opts) |
|
5698 { |
|
5699 struct skb_shared_info *info = skb_shinfo(skb); |
|
5700 unsigned int cur_frag, entry; |
|
5701 struct TxDesc * uninitialized_var(txd); |
|
5702 struct device *d = &tp->pci_dev->dev; |
|
5703 |
|
5704 entry = tp->cur_tx; |
|
5705 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
5706 const skb_frag_t *frag = info->frags + cur_frag; |
|
5707 dma_addr_t mapping; |
|
5708 u32 status, len; |
|
5709 void *addr; |
|
5710 |
|
5711 entry = (entry + 1) % NUM_TX_DESC; |
|
5712 |
|
5713 txd = tp->TxDescArray + entry; |
|
5714 len = skb_frag_size(frag); |
|
5715 addr = skb_frag_address(frag); |
|
5716 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
|
5717 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5718 if (net_ratelimit()) |
|
5719 netif_err(tp, drv, tp->dev, |
|
5720 "Failed to map TX fragments DMA!\n"); |
|
5721 goto err_out; |
|
5722 } |
|
5723 |
|
5724 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5725 status = opts[0] | len | |
|
5726 (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5727 |
|
5728 txd->opts1 = cpu_to_le32(status); |
|
5729 txd->opts2 = cpu_to_le32(opts[1]); |
|
5730 txd->addr = cpu_to_le64(mapping); |
|
5731 |
|
5732 tp->tx_skb[entry].len = len; |
|
5733 } |
|
5734 |
|
5735 if (cur_frag) { |
|
5736 tp->tx_skb[entry].skb = skb; |
|
5737 txd->opts1 |= cpu_to_le32(LastFrag); |
|
5738 } |
|
5739 |
|
5740 return cur_frag; |
|
5741 |
|
5742 err_out: |
|
5743 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); |
|
5744 return -EIO; |
|
5745 } |
|
5746 |
|
5747 static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
|
5748 struct sk_buff *skb, u32 *opts) |
|
5749 { |
|
5750 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
|
5751 u32 mss = skb_shinfo(skb)->gso_size; |
|
5752 int offset = info->opts_offset; |
|
5753 |
|
5754 if (mss) { |
|
5755 opts[0] |= TD_LSO; |
|
5756 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; |
|
5757 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
5758 const struct iphdr *ip = ip_hdr(skb); |
|
5759 |
|
5760 if (ip->protocol == IPPROTO_TCP) |
|
5761 opts[offset] |= info->checksum.tcp; |
|
5762 else if (ip->protocol == IPPROTO_UDP) |
|
5763 opts[offset] |= info->checksum.udp; |
|
5764 else |
|
5765 WARN_ON_ONCE(1); |
|
5766 } |
|
5767 } |
|
5768 |
|
5769 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
5770 struct net_device *dev) |
|
5771 { |
|
5772 struct rtl8169_private *tp = netdev_priv(dev); |
|
5773 unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
|
5774 struct TxDesc *txd = tp->TxDescArray + entry; |
|
5775 void __iomem *ioaddr = tp->mmio_addr; |
|
5776 struct device *d = &tp->pci_dev->dev; |
|
5777 dma_addr_t mapping; |
|
5778 u32 status, len; |
|
5779 u32 opts[2]; |
|
5780 int frags; |
|
5781 |
|
5782 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
|
5783 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
|
5784 goto err_stop_0; |
|
5785 } |
|
5786 |
|
5787 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
5788 goto err_stop_0; |
|
5789 |
|
5790 len = skb_headlen(skb); |
|
5791 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
|
5792 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5793 if (net_ratelimit()) |
|
5794 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); |
|
5795 goto err_dma_0; |
|
5796 } |
|
5797 |
|
5798 tp->tx_skb[entry].len = len; |
|
5799 txd->addr = cpu_to_le64(mapping); |
|
5800 |
|
5801 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
5802 opts[0] = DescOwn; |
|
5803 |
|
5804 rtl8169_tso_csum(tp, skb, opts); |
|
5805 |
|
5806 frags = rtl8169_xmit_frags(tp, skb, opts); |
|
5807 if (frags < 0) |
|
5808 goto err_dma_1; |
|
5809 else if (frags) |
|
5810 opts[0] |= FirstFrag; |
|
5811 else { |
|
5812 opts[0] |= FirstFrag | LastFrag; |
|
5813 tp->tx_skb[entry].skb = skb; |
|
5814 } |
|
5815 |
|
5816 txd->opts2 = cpu_to_le32(opts[1]); |
|
5817 |
|
5818 skb_tx_timestamp(skb); |
|
5819 |
|
5820 wmb(); |
|
5821 |
|
5822 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5823 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5824 txd->opts1 = cpu_to_le32(status); |
|
5825 |
|
5826 tp->cur_tx += frags + 1; |
|
5827 |
|
5828 wmb(); |
|
5829 |
|
5830 RTL_W8(TxPoll, NPQ); |
|
5831 |
|
5832 mmiowb(); |
|
5833 |
|
5834 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5835 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
|
5836 * not miss a ring update when it notices a stopped queue. |
|
5837 */ |
|
5838 smp_wmb(); |
|
5839 netif_stop_queue(dev); |
|
5840 /* Sync with rtl_tx: |
|
5841 * - publish queue status and cur_tx ring index (write barrier) |
|
5842 * - refresh dirty_tx ring index (read barrier). |
|
5843 * May the current thread have a pessimistic view of the ring |
|
5844 * status and forget to wake up queue, a racing rtl_tx thread |
|
5845 * can't. |
|
5846 */ |
|
5847 smp_mb(); |
|
5848 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
|
5849 netif_wake_queue(dev); |
|
5850 } |
|
5851 |
|
5852 return NETDEV_TX_OK; |
|
5853 |
|
5854 err_dma_1: |
|
5855 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
|
5856 err_dma_0: |
|
5857 dev_kfree_skb(skb); |
|
5858 dev->stats.tx_dropped++; |
|
5859 return NETDEV_TX_OK; |
|
5860 |
|
5861 err_stop_0: |
|
5862 netif_stop_queue(dev); |
|
5863 dev->stats.tx_dropped++; |
|
5864 return NETDEV_TX_BUSY; |
|
5865 } |
|
5866 |
|
5867 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
5868 { |
|
5869 struct rtl8169_private *tp = netdev_priv(dev); |
|
5870 struct pci_dev *pdev = tp->pci_dev; |
|
5871 u16 pci_status, pci_cmd; |
|
5872 |
|
5873 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
5874 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
5875 |
|
5876 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
|
5877 pci_cmd, pci_status); |
|
5878 |
|
5879 /* |
|
5880 * The recovery sequence below admits a very elaborated explanation: |
|
5881 * - it seems to work; |
|
5882 * - I did not see what else could be done; |
|
5883 * - it makes iop3xx happy. |
|
5884 * |
|
5885 * Feel free to adjust to your needs. |
|
5886 */ |
|
5887 if (pdev->broken_parity_status) |
|
5888 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
5889 else |
|
5890 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
5891 |
|
5892 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
5893 |
|
5894 pci_write_config_word(pdev, PCI_STATUS, |
|
5895 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
5896 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
5897 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
5898 |
|
5899 /* The infamous DAC f*ckup only happens at boot time */ |
|
5900 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
5901 void __iomem *ioaddr = tp->mmio_addr; |
|
5902 |
|
5903 netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
|
5904 tp->cp_cmd &= ~PCIDAC; |
|
5905 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5906 dev->features &= ~NETIF_F_HIGHDMA; |
|
5907 } |
|
5908 |
|
5909 rtl8169_hw_reset(tp); |
|
5910 |
|
5911 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5912 } |
|
5913 |
|
5914 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
|
5915 { |
|
5916 unsigned int dirty_tx, tx_left; |
|
5917 |
|
5918 dirty_tx = tp->dirty_tx; |
|
5919 smp_rmb(); |
|
5920 tx_left = tp->cur_tx - dirty_tx; |
|
5921 |
|
5922 while (tx_left > 0) { |
|
5923 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
5924 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5925 u32 status; |
|
5926 |
|
5927 rmb(); |
|
5928 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
5929 if (status & DescOwn) |
|
5930 break; |
|
5931 |
|
5932 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5933 tp->TxDescArray + entry); |
|
5934 if (status & LastFrag) { |
|
5935 u64_stats_update_begin(&tp->tx_stats.syncp); |
|
5936 tp->tx_stats.packets++; |
|
5937 tp->tx_stats.bytes += tx_skb->skb->len; |
|
5938 u64_stats_update_end(&tp->tx_stats.syncp); |
|
5939 dev_kfree_skb(tx_skb->skb); |
|
5940 tx_skb->skb = NULL; |
|
5941 } |
|
5942 dirty_tx++; |
|
5943 tx_left--; |
|
5944 } |
|
5945 |
|
5946 if (tp->dirty_tx != dirty_tx) { |
|
5947 tp->dirty_tx = dirty_tx; |
|
5948 /* Sync with rtl8169_start_xmit: |
|
5949 * - publish dirty_tx ring index (write barrier) |
|
5950 * - refresh cur_tx ring index and queue status (read barrier) |
|
5951 * May the current thread miss the stopped queue condition, |
|
5952 * a racing xmit thread can only have a right view of the |
|
5953 * ring status. |
|
5954 */ |
|
5955 smp_mb(); |
|
5956 if (netif_queue_stopped(dev) && |
|
5957 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5958 netif_wake_queue(dev); |
|
5959 } |
|
5960 /* |
|
5961 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
5962 * too close. Let's kick an extra TxPoll request when a burst |
|
5963 * of start_xmit activity is detected (if it is not detected, |
|
5964 * it is slow enough). -- FR |
|
5965 */ |
|
5966 if (tp->cur_tx != dirty_tx) { |
|
5967 void __iomem *ioaddr = tp->mmio_addr; |
|
5968 |
|
5969 RTL_W8(TxPoll, NPQ); |
|
5970 } |
|
5971 } |
|
5972 } |
|
5973 |
|
5974 static inline int rtl8169_fragmented_frame(u32 status) |
|
5975 { |
|
5976 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
5977 } |
|
5978 |
|
5979 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
|
5980 { |
|
5981 u32 status = opts1 & RxProtoMask; |
|
5982 |
|
5983 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
5984 ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
|
5985 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
5986 else |
|
5987 skb_checksum_none_assert(skb); |
|
5988 } |
|
5989 |
|
5990 static struct sk_buff *rtl8169_try_rx_copy(void *data, |
|
5991 struct rtl8169_private *tp, |
|
5992 int pkt_size, |
|
5993 dma_addr_t addr) |
|
5994 { |
|
5995 struct sk_buff *skb; |
|
5996 struct device *d = &tp->pci_dev->dev; |
|
5997 |
|
5998 data = rtl8169_align(data); |
|
5999 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
6000 prefetch(data); |
|
6001 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); |
|
6002 if (skb) |
|
6003 memcpy(skb->data, data, pkt_size); |
|
6004 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
6005 |
|
6006 return skb; |
|
6007 } |
|
6008 |
|
6009 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
|
6010 { |
|
6011 unsigned int cur_rx, rx_left; |
|
6012 unsigned int count; |
|
6013 |
|
6014 cur_rx = tp->cur_rx; |
|
6015 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
6016 rx_left = min(rx_left, budget); |
|
6017 |
|
6018 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
6019 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
6020 struct RxDesc *desc = tp->RxDescArray + entry; |
|
6021 u32 status; |
|
6022 |
|
6023 rmb(); |
|
6024 status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
|
6025 |
|
6026 if (status & DescOwn) |
|
6027 break; |
|
6028 if (unlikely(status & RxRES)) { |
|
6029 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
|
6030 status); |
|
6031 dev->stats.rx_errors++; |
|
6032 if (status & (RxRWT | RxRUNT)) |
|
6033 dev->stats.rx_length_errors++; |
|
6034 if (status & RxCRC) |
|
6035 dev->stats.rx_crc_errors++; |
|
6036 if (status & RxFOVF) { |
|
6037 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
6038 dev->stats.rx_fifo_errors++; |
|
6039 } |
|
6040 if ((status & (RxRUNT | RxCRC)) && |
|
6041 !(status & (RxRWT | RxFOVF)) && |
|
6042 (dev->features & NETIF_F_RXALL)) |
|
6043 goto process_pkt; |
|
6044 |
|
6045 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
6046 } else { |
|
6047 struct sk_buff *skb; |
|
6048 dma_addr_t addr; |
|
6049 int pkt_size; |
|
6050 |
|
6051 process_pkt: |
|
6052 addr = le64_to_cpu(desc->addr); |
|
6053 if (likely(!(dev->features & NETIF_F_RXFCS))) |
|
6054 pkt_size = (status & 0x00003fff) - 4; |
|
6055 else |
|
6056 pkt_size = status & 0x00003fff; |
|
6057 |
|
6058 /* |
|
6059 * The driver does not support incoming fragmented |
|
6060 * frames. They are seen as a symptom of over-mtu |
|
6061 * sized frames. |
|
6062 */ |
|
6063 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
6064 dev->stats.rx_dropped++; |
|
6065 dev->stats.rx_length_errors++; |
|
6066 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
6067 continue; |
|
6068 } |
|
6069 |
|
6070 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
|
6071 tp, pkt_size, addr); |
|
6072 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
6073 if (!skb) { |
|
6074 dev->stats.rx_dropped++; |
|
6075 continue; |
|
6076 } |
|
6077 |
|
6078 rtl8169_rx_csum(skb, status); |
|
6079 skb_put(skb, pkt_size); |
|
6080 skb->protocol = eth_type_trans(skb, dev); |
|
6081 |
|
6082 rtl8169_rx_vlan_tag(desc, skb); |
|
6083 |
|
6084 napi_gro_receive(&tp->napi, skb); |
|
6085 |
|
6086 u64_stats_update_begin(&tp->rx_stats.syncp); |
|
6087 tp->rx_stats.packets++; |
|
6088 tp->rx_stats.bytes += pkt_size; |
|
6089 u64_stats_update_end(&tp->rx_stats.syncp); |
|
6090 } |
|
6091 |
|
6092 /* Work around for AMD plateform. */ |
|
6093 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
6094 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
6095 desc->opts2 = 0; |
|
6096 cur_rx++; |
|
6097 } |
|
6098 } |
|
6099 |
|
6100 count = cur_rx - tp->cur_rx; |
|
6101 tp->cur_rx = cur_rx; |
|
6102 |
|
6103 tp->dirty_rx += count; |
|
6104 |
|
6105 return count; |
|
6106 } |
|
6107 |
|
6108 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
6109 { |
|
6110 struct net_device *dev = dev_instance; |
|
6111 struct rtl8169_private *tp = netdev_priv(dev); |
|
6112 int handled = 0; |
|
6113 u16 status; |
|
6114 |
|
6115 status = rtl_get_events(tp); |
|
6116 if (status && status != 0xffff) { |
|
6117 status &= RTL_EVENT_NAPI | tp->event_slow; |
|
6118 if (status) { |
|
6119 handled = 1; |
|
6120 |
|
6121 rtl_irq_disable(tp); |
|
6122 napi_schedule(&tp->napi); |
|
6123 } |
|
6124 } |
|
6125 return IRQ_RETVAL(handled); |
|
6126 } |
|
6127 |
|
6128 /* |
|
6129 * Workqueue context. |
|
6130 */ |
|
6131 static void rtl_slow_event_work(struct rtl8169_private *tp) |
|
6132 { |
|
6133 struct net_device *dev = tp->dev; |
|
6134 u16 status; |
|
6135 |
|
6136 status = rtl_get_events(tp) & tp->event_slow; |
|
6137 rtl_ack_events(tp, status); |
|
6138 |
|
6139 if (unlikely(status & RxFIFOOver)) { |
|
6140 switch (tp->mac_version) { |
|
6141 /* Work around for rx fifo overflow */ |
|
6142 case RTL_GIGA_MAC_VER_11: |
|
6143 netif_stop_queue(dev); |
|
6144 /* XXX - Hack alert. See rtl_task(). */ |
|
6145 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); |
|
6146 default: |
|
6147 break; |
|
6148 } |
|
6149 } |
|
6150 |
|
6151 if (unlikely(status & SYSErr)) |
|
6152 rtl8169_pcierr_interrupt(dev); |
|
6153 |
|
6154 if (status & LinkChg) |
|
6155 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); |
|
6156 |
|
6157 rtl_irq_enable_all(tp); |
|
6158 } |
|
6159 |
|
6160 static void rtl_task(struct work_struct *work) |
|
6161 { |
|
6162 static const struct { |
|
6163 int bitnr; |
|
6164 void (*action)(struct rtl8169_private *); |
|
6165 } rtl_work[] = { |
|
6166 /* XXX - keep rtl_slow_event_work() as first element. */ |
|
6167 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
|
6168 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, |
|
6169 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } |
|
6170 }; |
|
6171 struct rtl8169_private *tp = |
|
6172 container_of(work, struct rtl8169_private, wk.work); |
|
6173 struct net_device *dev = tp->dev; |
|
6174 int i; |
|
6175 |
|
6176 rtl_lock_work(tp); |
|
6177 |
|
6178 if (!netif_running(dev) || |
|
6179 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) |
|
6180 goto out_unlock; |
|
6181 |
|
6182 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { |
|
6183 bool pending; |
|
6184 |
|
6185 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
|
6186 if (pending) |
|
6187 rtl_work[i].action(tp); |
|
6188 } |
|
6189 |
|
6190 out_unlock: |
|
6191 rtl_unlock_work(tp); |
|
6192 } |
|
6193 |
|
6194 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
6195 { |
|
6196 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
6197 struct net_device *dev = tp->dev; |
|
6198 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
|
6199 int work_done= 0; |
|
6200 u16 status; |
|
6201 |
|
6202 status = rtl_get_events(tp); |
|
6203 rtl_ack_events(tp, status & ~tp->event_slow); |
|
6204 |
|
6205 if (status & RTL_EVENT_NAPI_RX) |
|
6206 work_done = rtl_rx(dev, tp, (u32) budget); |
|
6207 |
|
6208 if (status & RTL_EVENT_NAPI_TX) |
|
6209 rtl_tx(dev, tp); |
|
6210 |
|
6211 if (status & tp->event_slow) { |
|
6212 enable_mask &= ~tp->event_slow; |
|
6213 |
|
6214 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); |
|
6215 } |
|
6216 |
|
6217 if (work_done < budget) { |
|
6218 napi_complete(napi); |
|
6219 |
|
6220 rtl_irq_enable(tp, enable_mask); |
|
6221 mmiowb(); |
|
6222 } |
|
6223 |
|
6224 return work_done; |
|
6225 } |
|
6226 |
|
6227 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
6228 { |
|
6229 struct rtl8169_private *tp = netdev_priv(dev); |
|
6230 |
|
6231 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
6232 return; |
|
6233 |
|
6234 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
6235 RTL_W32(RxMissed, 0); |
|
6236 } |
|
6237 |
|
6238 static void rtl8169_down(struct net_device *dev) |
|
6239 { |
|
6240 struct rtl8169_private *tp = netdev_priv(dev); |
|
6241 void __iomem *ioaddr = tp->mmio_addr; |
|
6242 |
|
6243 del_timer_sync(&tp->timer); |
|
6244 |
|
6245 napi_disable(&tp->napi); |
|
6246 netif_stop_queue(dev); |
|
6247 |
|
6248 rtl8169_hw_reset(tp); |
|
6249 /* |
|
6250 * At this point device interrupts can not be enabled in any function, |
|
6251 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
|
6252 * and napi is disabled (rtl8169_poll). |
|
6253 */ |
|
6254 rtl8169_rx_missed(dev, ioaddr); |
|
6255 |
|
6256 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
6257 synchronize_sched(); |
|
6258 |
|
6259 rtl8169_tx_clear(tp); |
|
6260 |
|
6261 rtl8169_rx_clear(tp); |
|
6262 |
|
6263 rtl_pll_power_down(tp); |
|
6264 } |
|
6265 |
|
6266 static int rtl8169_close(struct net_device *dev) |
|
6267 { |
|
6268 struct rtl8169_private *tp = netdev_priv(dev); |
|
6269 struct pci_dev *pdev = tp->pci_dev; |
|
6270 |
|
6271 pm_runtime_get_sync(&pdev->dev); |
|
6272 |
|
6273 /* Update counters before going down */ |
|
6274 rtl8169_update_counters(dev); |
|
6275 |
|
6276 rtl_lock_work(tp); |
|
6277 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
6278 |
|
6279 rtl8169_down(dev); |
|
6280 rtl_unlock_work(tp); |
|
6281 |
|
6282 free_irq(pdev->irq, dev); |
|
6283 |
|
6284 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
6285 tp->RxPhyAddr); |
|
6286 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
6287 tp->TxPhyAddr); |
|
6288 tp->TxDescArray = NULL; |
|
6289 tp->RxDescArray = NULL; |
|
6290 |
|
6291 pm_runtime_put_sync(&pdev->dev); |
|
6292 |
|
6293 return 0; |
|
6294 } |
|
6295 |
|
6296 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
6297 static void rtl8169_netpoll(struct net_device *dev) |
|
6298 { |
|
6299 struct rtl8169_private *tp = netdev_priv(dev); |
|
6300 |
|
6301 rtl8169_interrupt(tp->pci_dev->irq, dev); |
|
6302 } |
|
6303 #endif |
|
6304 |
|
6305 static int rtl_open(struct net_device *dev) |
|
6306 { |
|
6307 struct rtl8169_private *tp = netdev_priv(dev); |
|
6308 void __iomem *ioaddr = tp->mmio_addr; |
|
6309 struct pci_dev *pdev = tp->pci_dev; |
|
6310 int retval = -ENOMEM; |
|
6311 |
|
6312 pm_runtime_get_sync(&pdev->dev); |
|
6313 |
|
6314 /* |
|
6315 * Rx and Tx descriptors needs 256 bytes alignment. |
|
6316 * dma_alloc_coherent provides more. |
|
6317 */ |
|
6318 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
|
6319 &tp->TxPhyAddr, GFP_KERNEL); |
|
6320 if (!tp->TxDescArray) |
|
6321 goto err_pm_runtime_put; |
|
6322 |
|
6323 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
|
6324 &tp->RxPhyAddr, GFP_KERNEL); |
|
6325 if (!tp->RxDescArray) |
|
6326 goto err_free_tx_0; |
|
6327 |
|
6328 retval = rtl8169_init_ring(dev); |
|
6329 if (retval < 0) |
|
6330 goto err_free_rx_1; |
|
6331 |
|
6332 INIT_WORK(&tp->wk.work, rtl_task); |
|
6333 |
|
6334 smp_mb(); |
|
6335 |
|
6336 rtl_request_firmware(tp); |
|
6337 |
|
6338 retval = request_irq(pdev->irq, rtl8169_interrupt, |
|
6339 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
6340 dev->name, dev); |
|
6341 if (retval < 0) |
|
6342 goto err_release_fw_2; |
|
6343 |
|
6344 rtl_lock_work(tp); |
|
6345 |
|
6346 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
6347 |
|
6348 napi_enable(&tp->napi); |
|
6349 |
|
6350 rtl8169_init_phy(dev, tp); |
|
6351 |
|
6352 __rtl8169_set_features(dev, dev->features); |
|
6353 |
|
6354 rtl_pll_power_up(tp); |
|
6355 |
|
6356 rtl_hw_start(dev); |
|
6357 |
|
6358 netif_start_queue(dev); |
|
6359 |
|
6360 rtl_unlock_work(tp); |
|
6361 |
|
6362 tp->saved_wolopts = 0; |
|
6363 pm_runtime_put_noidle(&pdev->dev); |
|
6364 |
|
6365 rtl8169_check_link_status(dev, tp, ioaddr); |
|
6366 out: |
|
6367 return retval; |
|
6368 |
|
6369 err_release_fw_2: |
|
6370 rtl_release_firmware(tp); |
|
6371 rtl8169_rx_clear(tp); |
|
6372 err_free_rx_1: |
|
6373 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
6374 tp->RxPhyAddr); |
|
6375 tp->RxDescArray = NULL; |
|
6376 err_free_tx_0: |
|
6377 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
6378 tp->TxPhyAddr); |
|
6379 tp->TxDescArray = NULL; |
|
6380 err_pm_runtime_put: |
|
6381 pm_runtime_put_noidle(&pdev->dev); |
|
6382 goto out; |
|
6383 } |
|
6384 |
|
6385 static struct rtnl_link_stats64 * |
|
6386 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
|
6387 { |
|
6388 struct rtl8169_private *tp = netdev_priv(dev); |
|
6389 void __iomem *ioaddr = tp->mmio_addr; |
|
6390 unsigned int start; |
|
6391 |
|
6392 if (netif_running(dev)) |
|
6393 rtl8169_rx_missed(dev, ioaddr); |
|
6394 |
|
6395 do { |
|
6396 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); |
|
6397 stats->rx_packets = tp->rx_stats.packets; |
|
6398 stats->rx_bytes = tp->rx_stats.bytes; |
|
6399 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); |
|
6400 |
|
6401 |
|
6402 do { |
|
6403 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); |
|
6404 stats->tx_packets = tp->tx_stats.packets; |
|
6405 stats->tx_bytes = tp->tx_stats.bytes; |
|
6406 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); |
|
6407 |
|
6408 stats->rx_dropped = dev->stats.rx_dropped; |
|
6409 stats->tx_dropped = dev->stats.tx_dropped; |
|
6410 stats->rx_length_errors = dev->stats.rx_length_errors; |
|
6411 stats->rx_errors = dev->stats.rx_errors; |
|
6412 stats->rx_crc_errors = dev->stats.rx_crc_errors; |
|
6413 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; |
|
6414 stats->rx_missed_errors = dev->stats.rx_missed_errors; |
|
6415 |
|
6416 return stats; |
|
6417 } |
|
6418 |
|
6419 static void rtl8169_net_suspend(struct net_device *dev) |
|
6420 { |
|
6421 struct rtl8169_private *tp = netdev_priv(dev); |
|
6422 |
|
6423 if (!netif_running(dev)) |
|
6424 return; |
|
6425 |
|
6426 netif_device_detach(dev); |
|
6427 netif_stop_queue(dev); |
|
6428 |
|
6429 rtl_lock_work(tp); |
|
6430 napi_disable(&tp->napi); |
|
6431 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
6432 rtl_unlock_work(tp); |
|
6433 |
|
6434 rtl_pll_power_down(tp); |
|
6435 } |
|
6436 |
|
6437 #ifdef CONFIG_PM |
|
6438 |
|
6439 static int rtl8169_suspend(struct device *device) |
|
6440 { |
|
6441 struct pci_dev *pdev = to_pci_dev(device); |
|
6442 struct net_device *dev = pci_get_drvdata(pdev); |
|
6443 |
|
6444 rtl8169_net_suspend(dev); |
|
6445 |
|
6446 return 0; |
|
6447 } |
|
6448 |
|
6449 static void __rtl8169_resume(struct net_device *dev) |
|
6450 { |
|
6451 struct rtl8169_private *tp = netdev_priv(dev); |
|
6452 |
|
6453 netif_device_attach(dev); |
|
6454 |
|
6455 rtl_pll_power_up(tp); |
|
6456 |
|
6457 rtl_lock_work(tp); |
|
6458 napi_enable(&tp->napi); |
|
6459 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
6460 rtl_unlock_work(tp); |
|
6461 |
|
6462 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
6463 } |
|
6464 |
|
6465 static int rtl8169_resume(struct device *device) |
|
6466 { |
|
6467 struct pci_dev *pdev = to_pci_dev(device); |
|
6468 struct net_device *dev = pci_get_drvdata(pdev); |
|
6469 struct rtl8169_private *tp = netdev_priv(dev); |
|
6470 |
|
6471 rtl8169_init_phy(dev, tp); |
|
6472 |
|
6473 if (netif_running(dev)) |
|
6474 __rtl8169_resume(dev); |
|
6475 |
|
6476 return 0; |
|
6477 } |
|
6478 |
|
6479 static int rtl8169_runtime_suspend(struct device *device) |
|
6480 { |
|
6481 struct pci_dev *pdev = to_pci_dev(device); |
|
6482 struct net_device *dev = pci_get_drvdata(pdev); |
|
6483 struct rtl8169_private *tp = netdev_priv(dev); |
|
6484 |
|
6485 if (!tp->TxDescArray) |
|
6486 return 0; |
|
6487 |
|
6488 rtl_lock_work(tp); |
|
6489 tp->saved_wolopts = __rtl8169_get_wol(tp); |
|
6490 __rtl8169_set_wol(tp, WAKE_ANY); |
|
6491 rtl_unlock_work(tp); |
|
6492 |
|
6493 rtl8169_net_suspend(dev); |
|
6494 |
|
6495 return 0; |
|
6496 } |
|
6497 |
|
6498 static int rtl8169_runtime_resume(struct device *device) |
|
6499 { |
|
6500 struct pci_dev *pdev = to_pci_dev(device); |
|
6501 struct net_device *dev = pci_get_drvdata(pdev); |
|
6502 struct rtl8169_private *tp = netdev_priv(dev); |
|
6503 |
|
6504 if (!tp->TxDescArray) |
|
6505 return 0; |
|
6506 |
|
6507 rtl_lock_work(tp); |
|
6508 __rtl8169_set_wol(tp, tp->saved_wolopts); |
|
6509 tp->saved_wolopts = 0; |
|
6510 rtl_unlock_work(tp); |
|
6511 |
|
6512 rtl8169_init_phy(dev, tp); |
|
6513 |
|
6514 __rtl8169_resume(dev); |
|
6515 |
|
6516 return 0; |
|
6517 } |
|
6518 |
|
6519 static int rtl8169_runtime_idle(struct device *device) |
|
6520 { |
|
6521 struct pci_dev *pdev = to_pci_dev(device); |
|
6522 struct net_device *dev = pci_get_drvdata(pdev); |
|
6523 struct rtl8169_private *tp = netdev_priv(dev); |
|
6524 |
|
6525 return tp->TxDescArray ? -EBUSY : 0; |
|
6526 } |
|
6527 |
|
6528 static const struct dev_pm_ops rtl8169_pm_ops = { |
|
6529 .suspend = rtl8169_suspend, |
|
6530 .resume = rtl8169_resume, |
|
6531 .freeze = rtl8169_suspend, |
|
6532 .thaw = rtl8169_resume, |
|
6533 .poweroff = rtl8169_suspend, |
|
6534 .restore = rtl8169_resume, |
|
6535 .runtime_suspend = rtl8169_runtime_suspend, |
|
6536 .runtime_resume = rtl8169_runtime_resume, |
|
6537 .runtime_idle = rtl8169_runtime_idle, |
|
6538 }; |
|
6539 |
|
6540 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
6541 |
|
6542 #else /* !CONFIG_PM */ |
|
6543 |
|
6544 #define RTL8169_PM_OPS NULL |
|
6545 |
|
6546 #endif /* !CONFIG_PM */ |
|
6547 |
|
6548 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
|
6549 { |
|
6550 void __iomem *ioaddr = tp->mmio_addr; |
|
6551 |
|
6552 /* WoL fails with 8168b when the receiver is disabled. */ |
|
6553 switch (tp->mac_version) { |
|
6554 case RTL_GIGA_MAC_VER_11: |
|
6555 case RTL_GIGA_MAC_VER_12: |
|
6556 case RTL_GIGA_MAC_VER_17: |
|
6557 pci_clear_master(tp->pci_dev); |
|
6558 |
|
6559 RTL_W8(ChipCmd, CmdRxEnb); |
|
6560 /* PCI commit */ |
|
6561 RTL_R8(ChipCmd); |
|
6562 break; |
|
6563 default: |
|
6564 break; |
|
6565 } |
|
6566 } |
|
6567 |
|
6568 static void rtl_shutdown(struct pci_dev *pdev) |
|
6569 { |
|
6570 struct net_device *dev = pci_get_drvdata(pdev); |
|
6571 struct rtl8169_private *tp = netdev_priv(dev); |
|
6572 struct device *d = &pdev->dev; |
|
6573 |
|
6574 pm_runtime_get_sync(d); |
|
6575 |
|
6576 rtl8169_net_suspend(dev); |
|
6577 |
|
6578 /* Restore original MAC address */ |
|
6579 rtl_rar_set(tp, dev->perm_addr); |
|
6580 |
|
6581 rtl8169_hw_reset(tp); |
|
6582 |
|
6583 if (system_state == SYSTEM_POWER_OFF) { |
|
6584 if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
|
6585 rtl_wol_suspend_quirk(tp); |
|
6586 rtl_wol_shutdown_quirk(tp); |
|
6587 } |
|
6588 |
|
6589 pci_wake_from_d3(pdev, true); |
|
6590 pci_set_power_state(pdev, PCI_D3hot); |
|
6591 } |
|
6592 |
|
6593 pm_runtime_put_noidle(d); |
|
6594 } |
|
6595 |
|
6596 static void __devexit rtl_remove_one(struct pci_dev *pdev) |
|
6597 { |
|
6598 struct net_device *dev = pci_get_drvdata(pdev); |
|
6599 struct rtl8169_private *tp = netdev_priv(dev); |
|
6600 |
|
6601 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6602 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6603 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6604 rtl8168_driver_stop(tp); |
|
6605 } |
|
6606 |
|
6607 cancel_work_sync(&tp->wk.work); |
|
6608 |
|
6609 netif_napi_del(&tp->napi); |
|
6610 |
|
6611 unregister_netdev(dev); |
|
6612 |
|
6613 rtl_release_firmware(tp); |
|
6614 |
|
6615 if (pci_dev_run_wake(pdev)) |
|
6616 pm_runtime_get_noresume(&pdev->dev); |
|
6617 |
|
6618 /* restore original MAC address */ |
|
6619 rtl_rar_set(tp, dev->perm_addr); |
|
6620 |
|
6621 rtl_disable_msi(pdev, tp); |
|
6622 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
6623 pci_set_drvdata(pdev, NULL); |
|
6624 } |
|
6625 |
|
6626 static const struct net_device_ops rtl_netdev_ops = { |
|
6627 .ndo_open = rtl_open, |
|
6628 .ndo_stop = rtl8169_close, |
|
6629 .ndo_get_stats64 = rtl8169_get_stats64, |
|
6630 .ndo_start_xmit = rtl8169_start_xmit, |
|
6631 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
6632 .ndo_validate_addr = eth_validate_addr, |
|
6633 .ndo_change_mtu = rtl8169_change_mtu, |
|
6634 .ndo_fix_features = rtl8169_fix_features, |
|
6635 .ndo_set_features = rtl8169_set_features, |
|
6636 .ndo_set_mac_address = rtl_set_mac_address, |
|
6637 .ndo_do_ioctl = rtl8169_ioctl, |
|
6638 .ndo_set_rx_mode = rtl_set_rx_mode, |
|
6639 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
6640 .ndo_poll_controller = rtl8169_netpoll, |
|
6641 #endif |
|
6642 |
|
6643 }; |
|
6644 |
|
6645 static const struct rtl_cfg_info { |
|
6646 void (*hw_start)(struct net_device *); |
|
6647 unsigned int region; |
|
6648 unsigned int align; |
|
6649 u16 event_slow; |
|
6650 unsigned features; |
|
6651 u8 default_ver; |
|
6652 } rtl_cfg_infos [] = { |
|
6653 [RTL_CFG_0] = { |
|
6654 .hw_start = rtl_hw_start_8169, |
|
6655 .region = 1, |
|
6656 .align = 0, |
|
6657 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, |
|
6658 .features = RTL_FEATURE_GMII, |
|
6659 .default_ver = RTL_GIGA_MAC_VER_01, |
|
6660 }, |
|
6661 [RTL_CFG_1] = { |
|
6662 .hw_start = rtl_hw_start_8168, |
|
6663 .region = 2, |
|
6664 .align = 8, |
|
6665 .event_slow = SYSErr | LinkChg | RxOverflow, |
|
6666 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
6667 .default_ver = RTL_GIGA_MAC_VER_11, |
|
6668 }, |
|
6669 [RTL_CFG_2] = { |
|
6670 .hw_start = rtl_hw_start_8101, |
|
6671 .region = 2, |
|
6672 .align = 8, |
|
6673 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | |
|
6674 PCSTimeout, |
|
6675 .features = RTL_FEATURE_MSI, |
|
6676 .default_ver = RTL_GIGA_MAC_VER_13, |
|
6677 } |
|
6678 }; |
|
6679 |
|
6680 /* Cfg9346_Unlock assumed. */ |
|
6681 static unsigned rtl_try_msi(struct rtl8169_private *tp, |
|
6682 const struct rtl_cfg_info *cfg) |
|
6683 { |
|
6684 void __iomem *ioaddr = tp->mmio_addr; |
|
6685 unsigned msi = 0; |
|
6686 u8 cfg2; |
|
6687 |
|
6688 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
6689 if (cfg->features & RTL_FEATURE_MSI) { |
|
6690 if (pci_enable_msi(tp->pci_dev)) { |
|
6691 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); |
|
6692 } else { |
|
6693 cfg2 |= MSIEnable; |
|
6694 msi = RTL_FEATURE_MSI; |
|
6695 } |
|
6696 } |
|
6697 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
6698 RTL_W8(Config2, cfg2); |
|
6699 return msi; |
|
6700 } |
|
6701 |
|
6702 DECLARE_RTL_COND(rtl_link_list_ready_cond) |
|
6703 { |
|
6704 void __iomem *ioaddr = tp->mmio_addr; |
|
6705 |
|
6706 return RTL_R8(MCU) & LINK_LIST_RDY; |
|
6707 } |
|
6708 |
|
6709 DECLARE_RTL_COND(rtl_rxtx_empty_cond) |
|
6710 { |
|
6711 void __iomem *ioaddr = tp->mmio_addr; |
|
6712 |
|
6713 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY; |
|
6714 } |
|
6715 |
|
6716 static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp) |
|
6717 { |
|
6718 void __iomem *ioaddr = tp->mmio_addr; |
|
6719 u32 data; |
|
6720 |
|
6721 tp->ocp_base = OCP_STD_PHY_BASE; |
|
6722 |
|
6723 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN); |
|
6724 |
|
6725 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) |
|
6726 return; |
|
6727 |
|
6728 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) |
|
6729 return; |
|
6730 |
|
6731 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); |
|
6732 msleep(1); |
|
6733 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
6734 |
|
6735 data = r8168_mac_ocp_read(tp, 0xe8de); |
|
6736 data &= ~(1 << 14); |
|
6737 r8168_mac_ocp_write(tp, 0xe8de, data); |
|
6738 |
|
6739 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) |
|
6740 return; |
|
6741 |
|
6742 data = r8168_mac_ocp_read(tp, 0xe8de); |
|
6743 data |= (1 << 15); |
|
6744 r8168_mac_ocp_write(tp, 0xe8de, data); |
|
6745 |
|
6746 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) |
|
6747 return; |
|
6748 } |
|
6749 |
|
6750 static void __devinit rtl_hw_initialize(struct rtl8169_private *tp) |
|
6751 { |
|
6752 switch (tp->mac_version) { |
|
6753 case RTL_GIGA_MAC_VER_40: |
|
6754 case RTL_GIGA_MAC_VER_41: |
|
6755 rtl_hw_init_8168g(tp); |
|
6756 break; |
|
6757 |
|
6758 default: |
|
6759 break; |
|
6760 } |
|
6761 } |
|
6762 |
|
6763 static int __devinit |
|
6764 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
6765 { |
|
6766 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
6767 const unsigned int region = cfg->region; |
|
6768 struct rtl8169_private *tp; |
|
6769 struct mii_if_info *mii; |
|
6770 struct net_device *dev; |
|
6771 void __iomem *ioaddr; |
|
6772 int chipset, i; |
|
6773 int rc; |
|
6774 |
|
6775 if (netif_msg_drv(&debug)) { |
|
6776 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
6777 MODULENAME, RTL8169_VERSION); |
|
6778 } |
|
6779 |
|
6780 dev = alloc_etherdev(sizeof (*tp)); |
|
6781 if (!dev) { |
|
6782 rc = -ENOMEM; |
|
6783 goto out; |
|
6784 } |
|
6785 |
|
6786 SET_NETDEV_DEV(dev, &pdev->dev); |
|
6787 dev->netdev_ops = &rtl_netdev_ops; |
|
6788 tp = netdev_priv(dev); |
|
6789 tp->dev = dev; |
|
6790 tp->pci_dev = pdev; |
|
6791 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
6792 |
|
6793 mii = &tp->mii; |
|
6794 mii->dev = dev; |
|
6795 mii->mdio_read = rtl_mdio_read; |
|
6796 mii->mdio_write = rtl_mdio_write; |
|
6797 mii->phy_id_mask = 0x1f; |
|
6798 mii->reg_num_mask = 0x1f; |
|
6799 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
6800 |
|
6801 /* disable ASPM completely as that cause random device stop working |
|
6802 * problems as well as full system hangs for some PCIe devices users */ |
|
6803 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
|
6804 PCIE_LINK_STATE_CLKPM); |
|
6805 |
|
6806 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
6807 rc = pci_enable_device(pdev); |
|
6808 if (rc < 0) { |
|
6809 netif_err(tp, probe, dev, "enable failure\n"); |
|
6810 goto err_out_free_dev_1; |
|
6811 } |
|
6812 |
|
6813 if (pci_set_mwi(pdev) < 0) |
|
6814 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
|
6815 |
|
6816 /* make sure PCI base addr 1 is MMIO */ |
|
6817 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
6818 netif_err(tp, probe, dev, |
|
6819 "region #%d not an MMIO resource, aborting\n", |
|
6820 region); |
|
6821 rc = -ENODEV; |
|
6822 goto err_out_mwi_2; |
|
6823 } |
|
6824 |
|
6825 /* check for weird/broken PCI region reporting */ |
|
6826 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
6827 netif_err(tp, probe, dev, |
|
6828 "Invalid PCI region size(s), aborting\n"); |
|
6829 rc = -ENODEV; |
|
6830 goto err_out_mwi_2; |
|
6831 } |
|
6832 |
|
6833 rc = pci_request_regions(pdev, MODULENAME); |
|
6834 if (rc < 0) { |
|
6835 netif_err(tp, probe, dev, "could not request regions\n"); |
|
6836 goto err_out_mwi_2; |
|
6837 } |
|
6838 |
|
6839 tp->cp_cmd = RxChkSum; |
|
6840 |
|
6841 if ((sizeof(dma_addr_t) > 4) && |
|
6842 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
6843 tp->cp_cmd |= PCIDAC; |
|
6844 dev->features |= NETIF_F_HIGHDMA; |
|
6845 } else { |
|
6846 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
6847 if (rc < 0) { |
|
6848 netif_err(tp, probe, dev, "DMA configuration failed\n"); |
|
6849 goto err_out_free_res_3; |
|
6850 } |
|
6851 } |
|
6852 |
|
6853 /* ioremap MMIO region */ |
|
6854 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
6855 if (!ioaddr) { |
|
6856 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
|
6857 rc = -EIO; |
|
6858 goto err_out_free_res_3; |
|
6859 } |
|
6860 tp->mmio_addr = ioaddr; |
|
6861 |
|
6862 if (!pci_is_pcie(pdev)) |
|
6863 netif_info(tp, probe, dev, "not PCI Express\n"); |
|
6864 |
|
6865 /* Identify chip attached to board */ |
|
6866 rtl8169_get_mac_version(tp, dev, cfg->default_ver); |
|
6867 |
|
6868 rtl_init_rxcfg(tp); |
|
6869 |
|
6870 rtl_irq_disable(tp); |
|
6871 |
|
6872 rtl_hw_initialize(tp); |
|
6873 |
|
6874 rtl_hw_reset(tp); |
|
6875 |
|
6876 rtl_ack_events(tp, 0xffff); |
|
6877 |
|
6878 pci_set_master(pdev); |
|
6879 |
|
6880 /* |
|
6881 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
6882 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
6883 */ |
|
6884 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6885 tp->cp_cmd |= RxVlan; |
|
6886 |
|
6887 rtl_init_mdio_ops(tp); |
|
6888 rtl_init_pll_power_ops(tp); |
|
6889 rtl_init_jumbo_ops(tp); |
|
6890 rtl_init_csi_ops(tp); |
|
6891 |
|
6892 rtl8169_print_mac_version(tp); |
|
6893 |
|
6894 chipset = tp->mac_version; |
|
6895 tp->txd_version = rtl_chip_infos[chipset].txd_version; |
|
6896 |
|
6897 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
6898 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
6899 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
6900 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
6901 tp->features |= RTL_FEATURE_WOL; |
|
6902 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
6903 tp->features |= RTL_FEATURE_WOL; |
|
6904 tp->features |= rtl_try_msi(tp, cfg); |
|
6905 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
6906 |
|
6907 if (rtl_tbi_enabled(tp)) { |
|
6908 tp->set_speed = rtl8169_set_speed_tbi; |
|
6909 tp->get_settings = rtl8169_gset_tbi; |
|
6910 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
6911 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
6912 tp->link_ok = rtl8169_tbi_link_ok; |
|
6913 tp->do_ioctl = rtl_tbi_ioctl; |
|
6914 } else { |
|
6915 tp->set_speed = rtl8169_set_speed_xmii; |
|
6916 tp->get_settings = rtl8169_gset_xmii; |
|
6917 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
6918 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
6919 tp->link_ok = rtl8169_xmii_link_ok; |
|
6920 tp->do_ioctl = rtl_xmii_ioctl; |
|
6921 } |
|
6922 |
|
6923 mutex_init(&tp->wk.mutex); |
|
6924 |
|
6925 /* Get MAC address */ |
|
6926 for (i = 0; i < ETH_ALEN; i++) |
|
6927 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
6928 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
6929 |
|
6930 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
6931 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
6932 |
|
6933 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
6934 |
|
6935 /* don't enable SG, IP_CSUM and TSO by default - it might not work |
|
6936 * properly for all devices */ |
|
6937 dev->features |= NETIF_F_RXCSUM | |
|
6938 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6939 |
|
6940 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6941 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6942 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6943 NETIF_F_HIGHDMA; |
|
6944 |
|
6945 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6946 /* 8110SCd requires hardware Rx VLAN - disallow toggling */ |
|
6947 dev->hw_features &= ~NETIF_F_HW_VLAN_RX; |
|
6948 |
|
6949 dev->hw_features |= NETIF_F_RXALL; |
|
6950 dev->hw_features |= NETIF_F_RXFCS; |
|
6951 |
|
6952 tp->hw_start = cfg->hw_start; |
|
6953 tp->event_slow = cfg->event_slow; |
|
6954 |
|
6955 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
|
6956 ~(RxBOVF | RxFOVF) : ~0; |
|
6957 |
|
6958 init_timer(&tp->timer); |
|
6959 tp->timer.data = (unsigned long) dev; |
|
6960 tp->timer.function = rtl8169_phy_timer; |
|
6961 |
|
6962 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
6963 |
|
6964 rc = register_netdev(dev); |
|
6965 if (rc < 0) |
|
6966 goto err_out_msi_4; |
|
6967 |
|
6968 pci_set_drvdata(pdev, dev); |
|
6969 |
|
6970 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
|
6971 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, |
|
6972 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); |
|
6973 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
|
6974 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " |
|
6975 "tx checksumming: %s]\n", |
|
6976 rtl_chip_infos[chipset].jumbo_max, |
|
6977 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); |
|
6978 } |
|
6979 |
|
6980 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6981 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6982 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6983 rtl8168_driver_start(tp); |
|
6984 } |
|
6985 |
|
6986 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
6987 |
|
6988 if (pci_dev_run_wake(pdev)) |
|
6989 pm_runtime_put_noidle(&pdev->dev); |
|
6990 |
|
6991 netif_carrier_off(dev); |
|
6992 |
|
6993 out: |
|
6994 return rc; |
|
6995 |
|
6996 err_out_msi_4: |
|
6997 netif_napi_del(&tp->napi); |
|
6998 rtl_disable_msi(pdev, tp); |
|
6999 iounmap(ioaddr); |
|
7000 err_out_free_res_3: |
|
7001 pci_release_regions(pdev); |
|
7002 err_out_mwi_2: |
|
7003 pci_clear_mwi(pdev); |
|
7004 pci_disable_device(pdev); |
|
7005 err_out_free_dev_1: |
|
7006 free_netdev(dev); |
|
7007 goto out; |
|
7008 } |
|
7009 |
|
7010 static struct pci_driver rtl8169_pci_driver = { |
|
7011 .name = MODULENAME, |
|
7012 .id_table = rtl8169_pci_tbl, |
|
7013 .probe = rtl_init_one, |
|
7014 .remove = __devexit_p(rtl_remove_one), |
|
7015 .shutdown = rtl_shutdown, |
|
7016 .driver.pm = RTL8169_PM_OPS, |
|
7017 }; |
|
7018 |
|
7019 static int __init rtl8169_init_module(void) |
|
7020 { |
|
7021 return pci_register_driver(&rtl8169_pci_driver); |
|
7022 } |
|
7023 |
|
7024 static void __exit rtl8169_cleanup_module(void) |
|
7025 { |
|
7026 pci_unregister_driver(&rtl8169_pci_driver); |
|
7027 } |
|
7028 |
|
7029 module_init(rtl8169_init_module); |
|
7030 module_exit(rtl8169_cleanup_module); |