devices/8139too-3.6-ethercat.c
branchstable-1.5
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     1 /******************************************************************************
       
     2  *
       
     3  *  $Id$
       
     4  *
       
     5  *  Copyright (C) 2006-2014  Florian Pose, Ingenieurgemeinschaft IgH
       
     6  *
       
     7  *  This file is part of the IgH EtherCAT Master.
       
     8  *
       
     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or
       
    10  *  modify it under the terms of the GNU General Public License version 2, as
       
    11  *  published by the Free Software Foundation.
       
    12  *
       
    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,
       
    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
       
    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
       
    16  *  Public License for more details.
       
    17  *
       
    18  *  You should have received a copy of the GNU General Public License along
       
    19  *  with the IgH EtherCAT Master; if not, write to the Free Software
       
    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
       
    21  *
       
    22  *  ---
       
    23  *
       
    24  *  The license mentioned above concerns the source code only. Using the
       
    25  *  EtherCAT technology and brand is only permitted in compliance with the
       
    26  *  industrial property and similar rights of Beckhoff Automation GmbH.
       
    27  *
       
    28  *  vim: noexpandtab
       
    29  *
       
    30  *****************************************************************************/
       
    31 
       
    32 /**
       
    33    \file
       
    34    EtherCAT driver for RTL8139-compatible NICs.
       
    35 */
       
    36 
       
    37 /*****************************************************************************/
       
    38 
       
    39 /*
       
    40   Former documentation:
       
    41 
       
    42 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
       
    43 
       
    44 	Maintained by Jeff Garzik <jgarzik@pobox.com>
       
    45 	Copyright 2000-2002 Jeff Garzik
       
    46 
       
    47 	Much code comes from Donald Becker's rtl8139.c driver,
       
    48 	versions 1.13 and older.  This driver was originally based
       
    49 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
       
    50 
       
    51 	-----<snip>-----
       
    52 
       
    53         	Written 1997-2001 by Donald Becker.
       
    54 		This software may be used and distributed according to the
       
    55 		terms of the GNU General Public License (GPL), incorporated
       
    56 		herein by reference.  Drivers based on or derived from this
       
    57 		code fall under the GPL and must retain the authorship,
       
    58 		copyright and license notice.  This file is not a complete
       
    59 		program and may only be used when the entire operating
       
    60 		system is licensed under the GPL.
       
    61 
       
    62 		This driver is for boards based on the RTL8129 and RTL8139
       
    63 		PCI ethernet chips.
       
    64 
       
    65 		The author may be reached as becker@scyld.com, or C/O Scyld
       
    66 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis
       
    67 		MD 21403
       
    68 
       
    69 		Support and updates available at
       
    70 		http://www.scyld.com/network/rtl8139.html
       
    71 
       
    72 		Twister-tuning table provided by Kinston
       
    73 		<shangh@realtek.com.tw>.
       
    74 
       
    75 	-----<snip>-----
       
    76 
       
    77 	This software may be used and distributed according to the terms
       
    78 	of the GNU General Public License, incorporated herein by reference.
       
    79 
       
    80 	Contributors:
       
    81 
       
    82 		Donald Becker - he wrote the original driver, kudos to him!
       
    83 		(but please don't e-mail him for support, this isn't his driver)
       
    84 
       
    85 		Tigran Aivazian - bug fixes, skbuff free cleanup
       
    86 
       
    87 		Martin Mares - suggestions for PCI cleanup
       
    88 
       
    89 		David S. Miller - PCI DMA and softnet updates
       
    90 
       
    91 		Ernst Gill - fixes ported from BSD driver
       
    92 
       
    93 		Daniel Kobras - identified specific locations of
       
    94 			posted MMIO write bugginess
       
    95 
       
    96 		Gerard Sharp - bug fix, testing and feedback
       
    97 
       
    98 		David Ford - Rx ring wrap fix
       
    99 
       
   100 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
       
   101 		to find and fix a crucial bug on older chipsets.
       
   102 
       
   103 		Donald Becker/Chris Butterworth/Marcus Westergren -
       
   104 		Noticed various Rx packet size-related buglets.
       
   105 
       
   106 		Santiago Garcia Mantinan - testing and feedback
       
   107 
       
   108 		Jens David - 2.2.x kernel backports
       
   109 
       
   110 		Martin Dennett - incredibly helpful insight on undocumented
       
   111 		features of the 8139 chips
       
   112 
       
   113 		Jean-Jacques Michel - bug fix
       
   114 
       
   115 		Tobias Ringström - Rx interrupt status checking suggestion
       
   116 
       
   117 		Andrew Morton - Clear blocked signals, avoid
       
   118 		buffer overrun setting current->comm.
       
   119 
       
   120 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls
       
   121 
       
   122 		Robert Kuebel - Save kernel thread from dying on any signal.
       
   123 
       
   124 	Submitting bug reports:
       
   125 
       
   126 		"rtl8139-diag -mmmaaavvveefN" output
       
   127 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
       
   128 
       
   129 */
       
   130 
       
   131 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
       
   132 
       
   133 #define DRV_NAME	"ec_8139too"
       
   134 #define DRV_VERSION	"0.9.28"
       
   135 
       
   136 
       
   137 #include <linux/module.h>
       
   138 #include <linux/kernel.h>
       
   139 #include <linux/compiler.h>
       
   140 #include <linux/pci.h>
       
   141 #include <linux/init.h>
       
   142 #include <linux/interrupt.h>
       
   143 #include <linux/netdevice.h>
       
   144 #include <linux/etherdevice.h>
       
   145 #include <linux/rtnetlink.h>
       
   146 #include <linux/delay.h>
       
   147 #include <linux/ethtool.h>
       
   148 #include <linux/mii.h>
       
   149 #include <linux/completion.h>
       
   150 #include <linux/crc32.h>
       
   151 #include <linux/io.h>
       
   152 #include <linux/uaccess.h>
       
   153 #include <linux/gfp.h>
       
   154 #include <asm/irq.h>
       
   155 
       
   156 #include "../globals.h"
       
   157 #include "ecdev.h"
       
   158 
       
   159 #define RTL8139_DRIVER_NAME DRV_NAME \
       
   160 	" EtherCAT-capable Fast Ethernet driver " \
       
   161 	DRV_VERSION ", master " EC_MASTER_VERSION
       
   162 
       
   163 #define PFX DRV_NAME ": "
       
   164 
       
   165 /* Default Message level */
       
   166 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \
       
   167                                  NETIF_MSG_PROBE  | \
       
   168                                  NETIF_MSG_LINK)
       
   169 
       
   170 
       
   171 /* define to 1, 2 or 3 to enable copious debugging info */
       
   172 #define RTL8139_DEBUG 0
       
   173 
       
   174 /* define to 1 to disable lightweight runtime debugging checks */
       
   175 #undef RTL8139_NDEBUG
       
   176 
       
   177 
       
   178 #ifdef RTL8139_NDEBUG
       
   179 #  define assert(expr) do {} while (0)
       
   180 #else
       
   181 #  define assert(expr) \
       
   182         if (unlikely(!(expr))) {				\
       
   183 		pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\
       
   184 		       #expr, __FILE__, __func__, __LINE__);	\
       
   185         }
       
   186 #endif
       
   187 
       
   188 
       
   189 /* A few user-configurable values. */
       
   190 /* media options */
       
   191 #define MAX_UNITS 8
       
   192 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
       
   193 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
       
   194 
       
   195 /* Whether to use MMIO or PIO. Default to MMIO. */
       
   196 #ifdef CONFIG_8139TOO_PIO
       
   197 static bool use_io = true;
       
   198 #else
       
   199 static bool use_io = false;
       
   200 #endif
       
   201 
       
   202 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
       
   203    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
       
   204 static int multicast_filter_limit = 32;
       
   205 
       
   206 /* bitmapped message enable number */
       
   207 static int debug = -1;
       
   208 
       
   209 /*
       
   210  * Receive ring size
       
   211  * Warning: 64K ring has hardware issues and may lock up.
       
   212  */
       
   213 #if defined(CONFIG_SH_DREAMCAST)
       
   214 #define RX_BUF_IDX 0	/* 8K ring */
       
   215 #else
       
   216 #define RX_BUF_IDX	2	/* 32K ring */
       
   217 #endif
       
   218 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)
       
   219 #define RX_BUF_PAD	16
       
   220 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
       
   221 
       
   222 #if RX_BUF_LEN == 65536
       
   223 #define RX_BUF_TOT_LEN	RX_BUF_LEN
       
   224 #else
       
   225 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
       
   226 #endif
       
   227 
       
   228 /* Number of Tx descriptor registers. */
       
   229 #define NUM_TX_DESC	4
       
   230 
       
   231 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
       
   232 #define MAX_ETH_FRAME_SIZE	1536
       
   233 
       
   234 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
       
   235 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE
       
   236 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)
       
   237 
       
   238 /* PCI Tuning Parameters
       
   239    Threshold is bytes transferred to chip before transmission starts. */
       
   240 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
       
   241 
       
   242 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
       
   243 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */
       
   244 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
       
   245 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
       
   246 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */
       
   247 
       
   248 /* Operational parameters that usually are not changed. */
       
   249 /* Time in jiffies before concluding the transmitter is hung. */
       
   250 #define TX_TIMEOUT  (6*HZ)
       
   251 
       
   252 
       
   253 enum {
       
   254 	HAS_MII_XCVR = 0x010000,
       
   255 	HAS_CHIP_XCVR = 0x020000,
       
   256 	HAS_LNK_CHNG = 0x040000,
       
   257 };
       
   258 
       
   259 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */
       
   260 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */
       
   261 #define RTL_MIN_IO_SIZE 0x80
       
   262 #define RTL8139B_IO_SIZE 256
       
   263 
       
   264 #define RTL8129_CAPS	HAS_MII_XCVR
       
   265 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)
       
   266 
       
   267 typedef enum {
       
   268 	RTL8139 = 0,
       
   269 	RTL8129,
       
   270 } board_t;
       
   271 
       
   272 
       
   273 /* indexed by board_t, above */
       
   274 static const struct {
       
   275 	const char *name;
       
   276 	u32 hw_flags;
       
   277 } board_info[] __devinitdata = {
       
   278 	{ "RealTek RTL8139", RTL8139_CAPS },
       
   279 	{ "RealTek RTL8129", RTL8129_CAPS },
       
   280 };
       
   281 
       
   282 
       
   283 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
       
   284 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   285 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   286 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   287 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   288 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   289 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   290 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   291 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   292 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   293 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   294 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   295 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   296 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   297 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   298 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   299 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   300 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   301 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   302 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   303 
       
   304 #ifdef CONFIG_SH_SECUREEDGE5410
       
   305 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */
       
   306 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
       
   307 #endif
       
   308 #ifdef CONFIG_8139TOO_8129
       
   309 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
       
   310 #endif
       
   311 
       
   312 	/* some crazy cards report invalid vendor ids like
       
   313 	 * 0x0001 here.  The other ids are valid and constant,
       
   314 	 * so we simply don't match on the main vendor id.
       
   315 	 */
       
   316 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
       
   317 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
       
   318 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
       
   319 
       
   320 	{0,}
       
   321 };
       
   322 
       
   323 /* prevent driver from being loaded automatically */
       
   324 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
       
   325 
       
   326 static struct {
       
   327 	const char str[ETH_GSTRING_LEN];
       
   328 } ethtool_stats_keys[] = {
       
   329 	{ "early_rx" },
       
   330 	{ "tx_buf_mapped" },
       
   331 	{ "tx_timeouts" },
       
   332 	{ "rx_lost_in_ring" },
       
   333 };
       
   334 
       
   335 /* The rest of these values should never change. */
       
   336 
       
   337 /* Symbolic offsets to registers. */
       
   338 enum RTL8139_registers {
       
   339 	MAC0		= 0,	 /* Ethernet hardware address. */
       
   340 	MAR0		= 8,	 /* Multicast filter. */
       
   341 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */
       
   342 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */
       
   343 	RxBuf		= 0x30,
       
   344 	ChipCmd		= 0x37,
       
   345 	RxBufPtr	= 0x38,
       
   346 	RxBufAddr	= 0x3A,
       
   347 	IntrMask	= 0x3C,
       
   348 	IntrStatus	= 0x3E,
       
   349 	TxConfig	= 0x40,
       
   350 	RxConfig	= 0x44,
       
   351 	Timer		= 0x48,	 /* A general-purpose counter. */
       
   352 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */
       
   353 	Cfg9346		= 0x50,
       
   354 	Config0		= 0x51,
       
   355 	Config1		= 0x52,
       
   356 	TimerInt	= 0x54,
       
   357 	MediaStatus	= 0x58,
       
   358 	Config3		= 0x59,
       
   359 	Config4		= 0x5A,	 /* absent on RTL-8139A */
       
   360 	HltClk		= 0x5B,
       
   361 	MultiIntr	= 0x5C,
       
   362 	TxSummary	= 0x60,
       
   363 	BasicModeCtrl	= 0x62,
       
   364 	BasicModeStatus	= 0x64,
       
   365 	NWayAdvert	= 0x66,
       
   366 	NWayLPAR	= 0x68,
       
   367 	NWayExpansion	= 0x6A,
       
   368 	/* Undocumented registers, but required for proper operation. */
       
   369 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */
       
   370 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */
       
   371 	PARA78		= 0x78,
       
   372 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */
       
   373 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */
       
   374 	Config5		= 0xD8,	 /* absent on RTL-8139A */
       
   375 };
       
   376 
       
   377 enum ClearBitMasks {
       
   378 	MultiIntrClear	= 0xF000,
       
   379 	ChipCmdClear	= 0xE2,
       
   380 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
       
   381 };
       
   382 
       
   383 enum ChipCmdBits {
       
   384 	CmdReset	= 0x10,
       
   385 	CmdRxEnb	= 0x08,
       
   386 	CmdTxEnb	= 0x04,
       
   387 	RxBufEmpty	= 0x01,
       
   388 };
       
   389 
       
   390 /* Interrupt register bits, using my own meaningful names. */
       
   391 enum IntrStatusBits {
       
   392 	PCIErr		= 0x8000,
       
   393 	PCSTimeout	= 0x4000,
       
   394 	RxFIFOOver	= 0x40,
       
   395 	RxUnderrun	= 0x20,
       
   396 	RxOverflow	= 0x10,
       
   397 	TxErr		= 0x08,
       
   398 	TxOK		= 0x04,
       
   399 	RxErr		= 0x02,
       
   400 	RxOK		= 0x01,
       
   401 
       
   402 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,
       
   403 };
       
   404 
       
   405 enum TxStatusBits {
       
   406 	TxHostOwns	= 0x2000,
       
   407 	TxUnderrun	= 0x4000,
       
   408 	TxStatOK	= 0x8000,
       
   409 	TxOutOfWindow	= 0x20000000,
       
   410 	TxAborted	= 0x40000000,
       
   411 	TxCarrierLost	= 0x80000000,
       
   412 };
       
   413 enum RxStatusBits {
       
   414 	RxMulticast	= 0x8000,
       
   415 	RxPhysical	= 0x4000,
       
   416 	RxBroadcast	= 0x2000,
       
   417 	RxBadSymbol	= 0x0020,
       
   418 	RxRunt		= 0x0010,
       
   419 	RxTooLong	= 0x0008,
       
   420 	RxCRCErr	= 0x0004,
       
   421 	RxBadAlign	= 0x0002,
       
   422 	RxStatusOK	= 0x0001,
       
   423 };
       
   424 
       
   425 /* Bits in RxConfig. */
       
   426 enum rx_mode_bits {
       
   427 	AcceptErr	= 0x20,
       
   428 	AcceptRunt	= 0x10,
       
   429 	AcceptBroadcast	= 0x08,
       
   430 	AcceptMulticast	= 0x04,
       
   431 	AcceptMyPhys	= 0x02,
       
   432 	AcceptAllPhys	= 0x01,
       
   433 };
       
   434 
       
   435 /* Bits in TxConfig. */
       
   436 enum tx_config_bits {
       
   437         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
       
   438         TxIFGShift	= 24,
       
   439         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
       
   440         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
       
   441         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
       
   442         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
       
   443 
       
   444 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */
       
   445 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */
       
   446 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */
       
   447 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */
       
   448 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */
       
   449 
       
   450 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */
       
   451 };
       
   452 
       
   453 /* Bits in Config1 */
       
   454 enum Config1Bits {
       
   455 	Cfg1_PM_Enable	= 0x01,
       
   456 	Cfg1_VPD_Enable	= 0x02,
       
   457 	Cfg1_PIO	= 0x04,
       
   458 	Cfg1_MMIO	= 0x08,
       
   459 	LWAKE		= 0x10,		/* not on 8139, 8139A */
       
   460 	Cfg1_Driver_Load = 0x20,
       
   461 	Cfg1_LED0	= 0x40,
       
   462 	Cfg1_LED1	= 0x80,
       
   463 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */
       
   464 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */
       
   465 };
       
   466 
       
   467 /* Bits in Config3 */
       
   468 enum Config3Bits {
       
   469 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */
       
   470 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */
       
   471 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */
       
   472 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */
       
   473 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */
       
   474 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */
       
   475 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */
       
   476 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */
       
   477 };
       
   478 
       
   479 /* Bits in Config4 */
       
   480 enum Config4Bits {
       
   481 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */
       
   482 };
       
   483 
       
   484 /* Bits in Config5 */
       
   485 enum Config5Bits {
       
   486 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */
       
   487 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */
       
   488 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */
       
   489 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
       
   490 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */
       
   491 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */
       
   492 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */
       
   493 };
       
   494 
       
   495 enum RxConfigBits {
       
   496 	/* rx fifo threshold */
       
   497 	RxCfgFIFOShift	= 13,
       
   498 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),
       
   499 
       
   500 	/* Max DMA burst */
       
   501 	RxCfgDMAShift	= 8,
       
   502 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
       
   503 
       
   504 	/* rx ring buffer length */
       
   505 	RxCfgRcv8K	= 0,
       
   506 	RxCfgRcv16K	= (1 << 11),
       
   507 	RxCfgRcv32K	= (1 << 12),
       
   508 	RxCfgRcv64K	= (1 << 11) | (1 << 12),
       
   509 
       
   510 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
       
   511 	RxNoWrap	= (1 << 7),
       
   512 };
       
   513 
       
   514 /* Twister tuning parameters from RealTek.
       
   515    Completely undocumented, but required to tune bad links on some boards. */
       
   516 enum CSCRBits {
       
   517 	CSCR_LinkOKBit		= 0x0400,
       
   518 	CSCR_LinkChangeBit	= 0x0800,
       
   519 	CSCR_LinkStatusBits	= 0x0f000,
       
   520 	CSCR_LinkDownOffCmd	= 0x003c0,
       
   521 	CSCR_LinkDownCmd	= 0x0f3c0,
       
   522 };
       
   523 
       
   524 enum Cfg9346Bits {
       
   525 	Cfg9346_Lock	= 0x00,
       
   526 	Cfg9346_Unlock	= 0xC0,
       
   527 };
       
   528 
       
   529 typedef enum {
       
   530 	CH_8139	= 0,
       
   531 	CH_8139_K,
       
   532 	CH_8139A,
       
   533 	CH_8139A_G,
       
   534 	CH_8139B,
       
   535 	CH_8130,
       
   536 	CH_8139C,
       
   537 	CH_8100,
       
   538 	CH_8100B_8139D,
       
   539 	CH_8101,
       
   540 } chip_t;
       
   541 
       
   542 enum chip_flags {
       
   543 	HasHltClk	= (1 << 0),
       
   544 	HasLWake	= (1 << 1),
       
   545 };
       
   546 
       
   547 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
       
   548 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
       
   549 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)
       
   550 
       
   551 /* directly indexed by chip_t, above */
       
   552 static const struct {
       
   553 	const char *name;
       
   554 	u32 version; /* from RTL8139C/RTL8139D docs */
       
   555 	u32 flags;
       
   556 } rtl_chip_info[] = {
       
   557 	{ "RTL-8139",
       
   558 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),
       
   559 	  HasHltClk,
       
   560 	},
       
   561 
       
   562 	{ "RTL-8139 rev K",
       
   563 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),
       
   564 	  HasHltClk,
       
   565 	},
       
   566 
       
   567 	{ "RTL-8139A",
       
   568 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),
       
   569 	  HasHltClk, /* XXX undocumented? */
       
   570 	},
       
   571 
       
   572 	{ "RTL-8139A rev G",
       
   573 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),
       
   574 	  HasHltClk, /* XXX undocumented? */
       
   575 	},
       
   576 
       
   577 	{ "RTL-8139B",
       
   578 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),
       
   579 	  HasLWake,
       
   580 	},
       
   581 
       
   582 	{ "RTL-8130",
       
   583 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),
       
   584 	  HasLWake,
       
   585 	},
       
   586 
       
   587 	{ "RTL-8139C",
       
   588 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),
       
   589 	  HasLWake,
       
   590 	},
       
   591 
       
   592 	{ "RTL-8100",
       
   593 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),
       
   594  	  HasLWake,
       
   595  	},
       
   596 
       
   597 	{ "RTL-8100B/8139D",
       
   598 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),
       
   599 	  HasHltClk /* XXX undocumented? */
       
   600 	| HasLWake,
       
   601 	},
       
   602 
       
   603 	{ "RTL-8101",
       
   604 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),
       
   605 	  HasLWake,
       
   606 	},
       
   607 };
       
   608 
       
   609 struct rtl_extra_stats {
       
   610 	unsigned long early_rx;
       
   611 	unsigned long tx_buf_mapped;
       
   612 	unsigned long tx_timeouts;
       
   613 	unsigned long rx_lost_in_ring;
       
   614 };
       
   615 
       
   616 struct rtl8139_stats {
       
   617 	u64	packets;
       
   618 	u64	bytes;
       
   619 	struct u64_stats_sync	syncp;
       
   620 };
       
   621 
       
   622 struct rtl8139_private {
       
   623 	void __iomem		*mmio_addr;
       
   624 	int			drv_flags;
       
   625 	struct pci_dev		*pci_dev;
       
   626 	u32			msg_enable;
       
   627 	struct napi_struct	napi;
       
   628 	struct net_device	*dev;
       
   629 
       
   630 	unsigned char		*rx_ring;
       
   631 	unsigned int		cur_rx;	/* RX buf index of next pkt */
       
   632 	struct rtl8139_stats	rx_stats;
       
   633 	dma_addr_t		rx_ring_dma;
       
   634 
       
   635 	unsigned int		tx_flag;
       
   636 	unsigned long		cur_tx;
       
   637 	unsigned long		dirty_tx;
       
   638 	struct rtl8139_stats	tx_stats;
       
   639 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */
       
   640 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */
       
   641 	dma_addr_t		tx_bufs_dma;
       
   642 
       
   643 	signed char		phys[4];	/* MII device addresses. */
       
   644 
       
   645 				/* Twister tune state. */
       
   646 	char			twistie, twist_row, twist_col;
       
   647 
       
   648 	unsigned int		watchdog_fired : 1;
       
   649 	unsigned int		default_port : 4; /* Last dev->if_port value. */
       
   650 	unsigned int		have_thread : 1;
       
   651 
       
   652 	spinlock_t		lock;
       
   653 	spinlock_t		rx_lock;
       
   654 
       
   655 	chip_t			chipset;
       
   656 	u32			rx_config;
       
   657 	struct rtl_extra_stats	xstats;
       
   658 
       
   659 	struct delayed_work	thread;
       
   660 
       
   661 	struct mii_if_info	mii;
       
   662 	unsigned int		regs_len;
       
   663 	unsigned long		fifo_copy_timeout;
       
   664 
       
   665 	ec_device_t *ecdev;
       
   666 };
       
   667 
       
   668 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");
       
   669 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");
       
   670 MODULE_LICENSE("GPL");
       
   671 MODULE_VERSION(EC_MASTER_VERSION);
       
   672 
       
   673 module_param(use_io, bool, 0);
       
   674 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
       
   675 module_param(multicast_filter_limit, int, 0);
       
   676 module_param_array(media, int, NULL, 0);
       
   677 module_param_array(full_duplex, int, NULL, 0);
       
   678 module_param(debug, int, 0);
       
   679 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
       
   680 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
       
   681 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
       
   682 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
       
   683 
       
   684 void ec_poll(struct net_device *);
       
   685 
       
   686 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
       
   687 static int rtl8139_open (struct net_device *dev);
       
   688 static int mdio_read (struct net_device *dev, int phy_id, int location);
       
   689 static void mdio_write (struct net_device *dev, int phy_id, int location,
       
   690 			int val);
       
   691 static void rtl8139_start_thread(struct rtl8139_private *tp);
       
   692 static void rtl8139_tx_timeout (struct net_device *dev);
       
   693 static void rtl8139_init_ring (struct net_device *dev);
       
   694 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
       
   695 				       struct net_device *dev);
       
   696 #ifdef CONFIG_NET_POLL_CONTROLLER
       
   697 static void rtl8139_poll_controller(struct net_device *dev);
       
   698 #endif
       
   699 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
       
   700 static int rtl8139_poll(struct napi_struct *napi, int budget);
       
   701 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
       
   702 static int rtl8139_close (struct net_device *dev);
       
   703 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
       
   704 static struct rtnl_link_stats64 *rtl8139_get_stats64(struct net_device *dev,
       
   705 						    struct rtnl_link_stats64
       
   706 						    *stats);
       
   707 static void rtl8139_set_rx_mode (struct net_device *dev);
       
   708 static void __set_rx_mode (struct net_device *dev);
       
   709 static void rtl8139_hw_start (struct net_device *dev);
       
   710 static void rtl8139_thread (struct work_struct *work);
       
   711 static void rtl8139_tx_timeout_task(struct work_struct *work);
       
   712 static const struct ethtool_ops rtl8139_ethtool_ops;
       
   713 
       
   714 /* write MMIO register, with flush */
       
   715 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
       
   716 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
       
   717 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
       
   718 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
       
   719 
       
   720 /* write MMIO register */
       
   721 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))
       
   722 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))
       
   723 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))
       
   724 
       
   725 /* read MMIO register */
       
   726 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))
       
   727 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))
       
   728 #define RTL_R32(reg)		ioread32 (ioaddr + (reg))
       
   729 
       
   730 
       
   731 static const u16 rtl8139_intr_mask =
       
   732 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
       
   733 	TxErr | TxOK | RxErr | RxOK;
       
   734 
       
   735 static const u16 rtl8139_norx_intr_mask =
       
   736 	PCIErr | PCSTimeout | RxUnderrun |
       
   737 	TxErr | TxOK | RxErr ;
       
   738 
       
   739 #if RX_BUF_IDX == 0
       
   740 static const unsigned int rtl8139_rx_config =
       
   741 	RxCfgRcv8K | RxNoWrap |
       
   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   743 	(RX_DMA_BURST << RxCfgDMAShift);
       
   744 #elif RX_BUF_IDX == 1
       
   745 static const unsigned int rtl8139_rx_config =
       
   746 	RxCfgRcv16K | RxNoWrap |
       
   747 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   748 	(RX_DMA_BURST << RxCfgDMAShift);
       
   749 #elif RX_BUF_IDX == 2
       
   750 static const unsigned int rtl8139_rx_config =
       
   751 	RxCfgRcv32K | RxNoWrap |
       
   752 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   753 	(RX_DMA_BURST << RxCfgDMAShift);
       
   754 #elif RX_BUF_IDX == 3
       
   755 static const unsigned int rtl8139_rx_config =
       
   756 	RxCfgRcv64K |
       
   757 	(RX_FIFO_THRESH << RxCfgFIFOShift) |
       
   758 	(RX_DMA_BURST << RxCfgDMAShift);
       
   759 #else
       
   760 #error "Invalid configuration for 8139_RXBUF_IDX"
       
   761 #endif
       
   762 
       
   763 static const unsigned int rtl8139_tx_config =
       
   764 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
       
   765 
       
   766 static void __rtl8139_cleanup_dev (struct net_device *dev)
       
   767 {
       
   768 	struct rtl8139_private *tp = netdev_priv(dev);
       
   769 	struct pci_dev *pdev;
       
   770 
       
   771 	assert (dev != NULL);
       
   772 	assert (tp->pci_dev != NULL);
       
   773 	pdev = tp->pci_dev;
       
   774 
       
   775 	if (tp->mmio_addr)
       
   776 		pci_iounmap (pdev, tp->mmio_addr);
       
   777 
       
   778 	/* it's ok to call this even if we have no regions to free */
       
   779 	pci_release_regions (pdev);
       
   780 
       
   781 	free_netdev(dev);
       
   782 	pci_set_drvdata (pdev, NULL);
       
   783 }
       
   784 
       
   785 
       
   786 static void rtl8139_chip_reset (void __iomem *ioaddr)
       
   787 {
       
   788 	int i;
       
   789 
       
   790 	/* Soft reset the chip. */
       
   791 	RTL_W8 (ChipCmd, CmdReset);
       
   792 
       
   793 	/* Check that the chip has finished the reset. */
       
   794 	for (i = 1000; i > 0; i--) {
       
   795 		barrier();
       
   796 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
       
   797 			break;
       
   798 		udelay (10);
       
   799 	}
       
   800 }
       
   801 
       
   802 
       
   803 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
       
   804 {
       
   805 	struct device *d = &pdev->dev;
       
   806 	void __iomem *ioaddr;
       
   807 	struct net_device *dev;
       
   808 	struct rtl8139_private *tp;
       
   809 	u8 tmp8;
       
   810 	int rc, disable_dev_on_err = 0;
       
   811 	unsigned int i, bar;
       
   812 	unsigned long io_len;
       
   813 	u32 version;
       
   814 	static const struct {
       
   815 		unsigned long mask;
       
   816 		char *type;
       
   817 	} res[] = {
       
   818 		{ IORESOURCE_IO,  "PIO" },
       
   819 		{ IORESOURCE_MEM, "MMIO" }
       
   820 	};
       
   821 
       
   822 	assert (pdev != NULL);
       
   823 
       
   824 	/* dev and priv zeroed in alloc_etherdev */
       
   825 	dev = alloc_etherdev (sizeof (*tp));
       
   826 	if (dev == NULL)
       
   827 		return ERR_PTR(-ENOMEM);
       
   828 
       
   829 	SET_NETDEV_DEV(dev, &pdev->dev);
       
   830 
       
   831 	tp = netdev_priv(dev);
       
   832 	tp->pci_dev = pdev;
       
   833 
       
   834 	/* enable device (incl. PCI PM wakeup and hotplug setup) */
       
   835 	rc = pci_enable_device (pdev);
       
   836 	if (rc)
       
   837 		goto err_out;
       
   838 
       
   839 	rc = pci_request_regions (pdev, DRV_NAME);
       
   840 	if (rc)
       
   841 		goto err_out;
       
   842 	disable_dev_on_err = 1;
       
   843 
       
   844 	pci_set_master (pdev);
       
   845 
       
   846 retry:
       
   847 	/* PIO bar register comes first. */
       
   848 	bar = !use_io;
       
   849 
       
   850 	io_len = pci_resource_len(pdev, bar);
       
   851 
       
   852 	dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
       
   853 
       
   854 	if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
       
   855 		dev_err(d, "region #%d not a %s resource, aborting\n", bar,
       
   856 			res[bar].type);
       
   857 		rc = -ENODEV;
       
   858 		goto err_out;
       
   859 	}
       
   860 	if (io_len < RTL_MIN_IO_SIZE) {
       
   861 		dev_err(d, "Invalid PCI %s region size(s), aborting\n",
       
   862 			res[bar].type);
       
   863 		rc = -ENODEV;
       
   864 		goto err_out;
       
   865 	}
       
   866 
       
   867 	ioaddr = pci_iomap(pdev, bar, 0);
       
   868 	if (!ioaddr) {
       
   869 		dev_err(d, "cannot map %s\n", res[bar].type);
       
   870 		if (!use_io) {
       
   871 			use_io = true;
       
   872 			goto retry;
       
   873 		}
       
   874 		rc = -ENODEV;
       
   875 		goto err_out;
       
   876 	}
       
   877 	tp->regs_len = io_len;
       
   878 	tp->mmio_addr = ioaddr;
       
   879 
       
   880 	/* Bring old chips out of low-power mode. */
       
   881 	RTL_W8 (HltClk, 'R');
       
   882 
       
   883 	/* check for missing/broken hardware */
       
   884 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
       
   885 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
       
   886 		rc = -EIO;
       
   887 		goto err_out;
       
   888 	}
       
   889 
       
   890 	/* identify chip attached to board */
       
   891 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;
       
   892 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
       
   893 		if (version == rtl_chip_info[i].version) {
       
   894 			tp->chipset = i;
       
   895 			goto match;
       
   896 		}
       
   897 
       
   898 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */
       
   899 	i = 0;
       
   900 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
       
   901 	dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
       
   902 	tp->chipset = 0;
       
   903 
       
   904 match:
       
   905 	pr_debug("chipset id (%d) == index %d, '%s'\n",
       
   906 		 version, i, rtl_chip_info[i].name);
       
   907 
       
   908 	if (tp->chipset >= CH_8139B) {
       
   909 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
       
   910 		pr_debug("PCI PM wakeup\n");
       
   911 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
       
   912 		    (tmp8 & LWAKE))
       
   913 			new_tmp8 &= ~LWAKE;
       
   914 		new_tmp8 |= Cfg1_PM_Enable;
       
   915 		if (new_tmp8 != tmp8) {
       
   916 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
   917 			RTL_W8 (Config1, tmp8);
       
   918 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
   919 		}
       
   920 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {
       
   921 			tmp8 = RTL_R8 (Config4);
       
   922 			if (tmp8 & LWPTN) {
       
   923 				RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
   924 				RTL_W8 (Config4, tmp8 & ~LWPTN);
       
   925 				RTL_W8 (Cfg9346, Cfg9346_Lock);
       
   926 			}
       
   927 		}
       
   928 	} else {
       
   929 		pr_debug("Old chip wakeup\n");
       
   930 		tmp8 = RTL_R8 (Config1);
       
   931 		tmp8 &= ~(SLEEP | PWRDN);
       
   932 		RTL_W8 (Config1, tmp8);
       
   933 	}
       
   934 
       
   935 	rtl8139_chip_reset (ioaddr);
       
   936 
       
   937 	return dev;
       
   938 
       
   939 err_out:
       
   940 	__rtl8139_cleanup_dev (dev);
       
   941 	if (disable_dev_on_err)
       
   942 		pci_disable_device (pdev);
       
   943 	return ERR_PTR(rc);
       
   944 }
       
   945 
       
   946 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
       
   947 {
       
   948 	struct rtl8139_private *tp = netdev_priv(dev);
       
   949 	unsigned long flags;
       
   950 	netdev_features_t changed = features ^ dev->features;
       
   951 	void __iomem *ioaddr = tp->mmio_addr;
       
   952 
       
   953 	if (!(changed & (NETIF_F_RXALL)))
       
   954 		return 0;
       
   955 
       
   956 	spin_lock_irqsave(&tp->lock, flags);
       
   957 
       
   958 	if (changed & NETIF_F_RXALL) {
       
   959 		int rx_mode = tp->rx_config;
       
   960 		if (features & NETIF_F_RXALL)
       
   961 			rx_mode |= (AcceptErr | AcceptRunt);
       
   962 		else
       
   963 			rx_mode &= ~(AcceptErr | AcceptRunt);
       
   964 		tp->rx_config = rtl8139_rx_config | rx_mode;
       
   965 		RTL_W32_F(RxConfig, tp->rx_config);
       
   966 	}
       
   967 
       
   968 	spin_unlock_irqrestore(&tp->lock, flags);
       
   969 
       
   970 	return 0;
       
   971 }
       
   972 
       
   973 static const struct net_device_ops rtl8139_netdev_ops = {
       
   974 	.ndo_open		= rtl8139_open,
       
   975 	.ndo_stop		= rtl8139_close,
       
   976 	.ndo_get_stats64	= rtl8139_get_stats64,
       
   977 	.ndo_change_mtu		= eth_change_mtu,
       
   978 	.ndo_validate_addr	= eth_validate_addr,
       
   979 	.ndo_set_mac_address 	= rtl8139_set_mac_address,
       
   980 	.ndo_start_xmit		= rtl8139_start_xmit,
       
   981 	.ndo_set_rx_mode	= rtl8139_set_rx_mode,
       
   982 	.ndo_do_ioctl		= netdev_ioctl,
       
   983 	.ndo_tx_timeout		= rtl8139_tx_timeout,
       
   984 #ifdef CONFIG_NET_POLL_CONTROLLER
       
   985 	.ndo_poll_controller	= rtl8139_poll_controller,
       
   986 #endif
       
   987 	.ndo_set_features	= rtl8139_set_features,
       
   988 };
       
   989 
       
   990 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
       
   991 				       const struct pci_device_id *ent)
       
   992 {
       
   993 	struct net_device *dev = NULL;
       
   994 	struct rtl8139_private *tp;
       
   995 	int i, addr_len, option;
       
   996 	void __iomem *ioaddr;
       
   997 	static int board_idx = -1;
       
   998 
       
   999 	assert (pdev != NULL);
       
  1000 	assert (ent != NULL);
       
  1001 
       
  1002 	board_idx++;
       
  1003 
       
  1004 	/* when we're built into the kernel, the driver version message
       
  1005 	 * is only printed if at least one 8139 board has been found
       
  1006 	 */
       
  1007 #ifndef MODULE
       
  1008 	{
       
  1009 		static int printed_version;
       
  1010 		if (!printed_version++)
       
  1011 			pr_info(RTL8139_DRIVER_NAME "\n");
       
  1012 	}
       
  1013 #endif
       
  1014 
       
  1015 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
       
  1016 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
       
  1017 		dev_info(&pdev->dev,
       
  1018 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
       
  1019 		       	   pdev->vendor, pdev->device, pdev->revision);
       
  1020 		return -ENODEV;
       
  1021 	}
       
  1022 
       
  1023 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
       
  1024 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
       
  1025 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
       
  1026 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
       
  1027 		pr_info("OQO Model 2 detected. Forcing PIO\n");
       
  1028 		use_io = 1;
       
  1029 	}
       
  1030 
       
  1031 	dev = rtl8139_init_board (pdev);
       
  1032 	if (IS_ERR(dev))
       
  1033 		return PTR_ERR(dev);
       
  1034 
       
  1035 	assert (dev != NULL);
       
  1036 	tp = netdev_priv(dev);
       
  1037 	tp->dev = dev;
       
  1038 
       
  1039 	ioaddr = tp->mmio_addr;
       
  1040 	assert (ioaddr != NULL);
       
  1041 
       
  1042 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
       
  1043 	for (i = 0; i < 3; i++)
       
  1044 		((__le16 *) (dev->dev_addr))[i] =
       
  1045 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
       
  1046 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
       
  1047 
       
  1048 	/* The Rtl8139-specific entries in the device structure. */
       
  1049 	dev->netdev_ops = &rtl8139_netdev_ops;
       
  1050 	dev->ethtool_ops = &rtl8139_ethtool_ops;
       
  1051 	dev->watchdog_timeo = TX_TIMEOUT;
       
  1052 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
       
  1053 
       
  1054 	/* note: the hardware is not capable of sg/csum/highdma, however
       
  1055 	 * through the use of skb_copy_and_csum_dev we enable these
       
  1056 	 * features
       
  1057 	 */
       
  1058 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
       
  1059 	dev->vlan_features = dev->features;
       
  1060 
       
  1061 	dev->hw_features |= NETIF_F_RXALL;
       
  1062 	dev->hw_features |= NETIF_F_RXFCS;
       
  1063 
       
  1064 	/* tp zeroed and aligned in alloc_etherdev */
       
  1065 	tp = netdev_priv(dev);
       
  1066 
       
  1067 	/* note: tp->chipset set in rtl8139_init_board */
       
  1068 	tp->drv_flags = board_info[ent->driver_data].hw_flags;
       
  1069 	tp->mmio_addr = ioaddr;
       
  1070 	tp->msg_enable =
       
  1071 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
       
  1072 	spin_lock_init (&tp->lock);
       
  1073 	spin_lock_init (&tp->rx_lock);
       
  1074 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
       
  1075 	tp->mii.dev = dev;
       
  1076 	tp->mii.mdio_read = mdio_read;
       
  1077 	tp->mii.mdio_write = mdio_write;
       
  1078 	tp->mii.phy_id_mask = 0x3f;
       
  1079 	tp->mii.reg_num_mask = 0x1f;
       
  1080 
       
  1081 	/* dev is fully set up and ready to use now */
       
  1082 
       
  1083 	// offer device to EtherCAT master module
       
  1084 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);
       
  1085 
       
  1086 	if (!tp->ecdev) {
       
  1087 		pr_debug("about to register device named %s (%p)...\n",
       
  1088 				dev->name, dev);
       
  1089 		i = register_netdev (dev);
       
  1090 		if (i) goto err_out;
       
  1091 	}
       
  1092 
       
  1093 	pci_set_drvdata (pdev, dev);
       
  1094 
       
  1095 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",
       
  1096 		dev->name,
       
  1097 		board_info[ent->driver_data].name,
       
  1098 		dev->base_addr,
       
  1099 		dev->dev_addr,
       
  1100 		dev->irq);
       
  1101 
       
  1102 	pr_debug("%s:  Identified 8139 chip type '%s'\n",
       
  1103 		dev->name, rtl_chip_info[tp->chipset].name);
       
  1104 
       
  1105 	/* Find the connected MII xcvrs.
       
  1106 	   Doing this in open() would allow detecting external xcvrs later, but
       
  1107 	   takes too much time. */
       
  1108 #ifdef CONFIG_8139TOO_8129
       
  1109 	if (tp->drv_flags & HAS_MII_XCVR) {
       
  1110 		int phy, phy_idx = 0;
       
  1111 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
       
  1112 			int mii_status = mdio_read(dev, phy, 1);
       
  1113 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {
       
  1114 				u16 advertising = mdio_read(dev, phy, 4);
       
  1115 				tp->phys[phy_idx++] = phy;
       
  1116 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",
       
  1117 					   dev->name, phy, mii_status, advertising);
       
  1118 			}
       
  1119 		}
       
  1120 		if (phy_idx == 0) {
       
  1121 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",
       
  1122 				   dev->name);
       
  1123 			tp->phys[0] = 32;
       
  1124 		}
       
  1125 	} else
       
  1126 #endif
       
  1127 		tp->phys[0] = 32;
       
  1128 	tp->mii.phy_id = tp->phys[0];
       
  1129 
       
  1130 	/* The lower four bits are the media type. */
       
  1131 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
       
  1132 	if (option > 0) {
       
  1133 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
       
  1134 		tp->default_port = option & 0xFF;
       
  1135 		if (tp->default_port)
       
  1136 			tp->mii.force_media = 1;
       
  1137 	}
       
  1138 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)
       
  1139 		tp->mii.full_duplex = full_duplex[board_idx];
       
  1140 	if (tp->mii.full_duplex) {
       
  1141 		pr_info("%s: Media type forced to Full Duplex.\n", dev->name);
       
  1142 		/* Changing the MII-advertised media because might prevent
       
  1143 		   re-connection. */
       
  1144 		tp->mii.force_media = 1;
       
  1145 	}
       
  1146 	if (tp->default_port) {
       
  1147 		pr_info("  Forcing %dMbps %s-duplex operation.\n",
       
  1148 			   (option & 0x20 ? 100 : 10),
       
  1149 			   (option & 0x10 ? "full" : "half"));
       
  1150 		mdio_write(dev, tp->phys[0], 0,
       
  1151 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */
       
  1152 				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
       
  1153 	}
       
  1154 
       
  1155 	/* Put the chip into low-power mode. */
       
  1156 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  1157 		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
       
  1158 
       
  1159 	if (tp->ecdev && ecdev_open(tp->ecdev)) {
       
  1160 		ecdev_withdraw(tp->ecdev);
       
  1161 		goto err_out;
       
  1162 	}
       
  1163 
       
  1164 	return 0;
       
  1165 
       
  1166 err_out:
       
  1167 	__rtl8139_cleanup_dev (dev);
       
  1168 	pci_disable_device (pdev);
       
  1169 	return i;
       
  1170 }
       
  1171 
       
  1172 
       
  1173 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
       
  1174 {
       
  1175 	struct net_device *dev = pci_get_drvdata (pdev);
       
  1176 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1177 
       
  1178 	assert (dev != NULL);
       
  1179 
       
  1180 	if (tp->ecdev) {
       
  1181 		ecdev_close(tp->ecdev);
       
  1182 		ecdev_withdraw(tp->ecdev);
       
  1183 	}
       
  1184 	else {
       
  1185 		cancel_delayed_work_sync(&tp->thread);
       
  1186 
       
  1187 		unregister_netdev (dev);
       
  1188 	}
       
  1189 
       
  1190 	__rtl8139_cleanup_dev (dev);
       
  1191 	pci_disable_device (pdev);
       
  1192 }
       
  1193 
       
  1194 
       
  1195 /* Serial EEPROM section. */
       
  1196 
       
  1197 /*  EEPROM_Ctrl bits. */
       
  1198 #define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
       
  1199 #define EE_CS			0x08	/* EEPROM chip select. */
       
  1200 #define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
       
  1201 #define EE_WRITE_0		0x00
       
  1202 #define EE_WRITE_1		0x02
       
  1203 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
       
  1204 #define EE_ENB			(0x80 | EE_CS)
       
  1205 
       
  1206 /* Delay between EEPROM clock transitions.
       
  1207    No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
       
  1208  */
       
  1209 
       
  1210 #define eeprom_delay()	(void)RTL_R8(Cfg9346)
       
  1211 
       
  1212 /* The EEPROM commands include the alway-set leading bit. */
       
  1213 #define EE_WRITE_CMD	(5)
       
  1214 #define EE_READ_CMD		(6)
       
  1215 #define EE_ERASE_CMD	(7)
       
  1216 
       
  1217 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
       
  1218 {
       
  1219 	int i;
       
  1220 	unsigned retval = 0;
       
  1221 	int read_cmd = location | (EE_READ_CMD << addr_len);
       
  1222 
       
  1223 	RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
       
  1224 	RTL_W8 (Cfg9346, EE_ENB);
       
  1225 	eeprom_delay ();
       
  1226 
       
  1227 	/* Shift the read command bits out. */
       
  1228 	for (i = 4 + addr_len; i >= 0; i--) {
       
  1229 		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
       
  1230 		RTL_W8 (Cfg9346, EE_ENB | dataval);
       
  1231 		eeprom_delay ();
       
  1232 		RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
       
  1233 		eeprom_delay ();
       
  1234 	}
       
  1235 	RTL_W8 (Cfg9346, EE_ENB);
       
  1236 	eeprom_delay ();
       
  1237 
       
  1238 	for (i = 16; i > 0; i--) {
       
  1239 		RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
       
  1240 		eeprom_delay ();
       
  1241 		retval =
       
  1242 		    (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
       
  1243 				     0);
       
  1244 		RTL_W8 (Cfg9346, EE_ENB);
       
  1245 		eeprom_delay ();
       
  1246 	}
       
  1247 
       
  1248 	/* Terminate the EEPROM access. */
       
  1249 	RTL_W8(Cfg9346, 0);
       
  1250 	eeprom_delay ();
       
  1251 
       
  1252 	return retval;
       
  1253 }
       
  1254 
       
  1255 /* MII serial management: mostly bogus for now. */
       
  1256 /* Read and write the MII management registers using software-generated
       
  1257    serial MDIO protocol.
       
  1258    The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
       
  1259    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
       
  1260    "overclocking" issues. */
       
  1261 #define MDIO_DIR		0x80
       
  1262 #define MDIO_DATA_OUT	0x04
       
  1263 #define MDIO_DATA_IN	0x02
       
  1264 #define MDIO_CLK		0x01
       
  1265 #define MDIO_WRITE0 (MDIO_DIR)
       
  1266 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
       
  1267 
       
  1268 #define mdio_delay()	RTL_R8(Config4)
       
  1269 
       
  1270 
       
  1271 static const char mii_2_8139_map[8] = {
       
  1272 	BasicModeCtrl,
       
  1273 	BasicModeStatus,
       
  1274 	0,
       
  1275 	0,
       
  1276 	NWayAdvert,
       
  1277 	NWayLPAR,
       
  1278 	NWayExpansion,
       
  1279 	0
       
  1280 };
       
  1281 
       
  1282 
       
  1283 #ifdef CONFIG_8139TOO_8129
       
  1284 /* Syncronize the MII management interface by shifting 32 one bits out. */
       
  1285 static void mdio_sync (void __iomem *ioaddr)
       
  1286 {
       
  1287 	int i;
       
  1288 
       
  1289 	for (i = 32; i >= 0; i--) {
       
  1290 		RTL_W8 (Config4, MDIO_WRITE1);
       
  1291 		mdio_delay ();
       
  1292 		RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
       
  1293 		mdio_delay ();
       
  1294 	}
       
  1295 }
       
  1296 #endif
       
  1297 
       
  1298 static int mdio_read (struct net_device *dev, int phy_id, int location)
       
  1299 {
       
  1300 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1301 	int retval = 0;
       
  1302 #ifdef CONFIG_8139TOO_8129
       
  1303 	void __iomem *ioaddr = tp->mmio_addr;
       
  1304 	int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
       
  1305 	int i;
       
  1306 #endif
       
  1307 
       
  1308 	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
       
  1309 		void __iomem *ioaddr = tp->mmio_addr;
       
  1310 		return location < 8 && mii_2_8139_map[location] ?
       
  1311 		    RTL_R16 (mii_2_8139_map[location]) : 0;
       
  1312 	}
       
  1313 
       
  1314 #ifdef CONFIG_8139TOO_8129
       
  1315 	mdio_sync (ioaddr);
       
  1316 	/* Shift the read command bits out. */
       
  1317 	for (i = 15; i >= 0; i--) {
       
  1318 		int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
       
  1319 
       
  1320 		RTL_W8 (Config4, MDIO_DIR | dataval);
       
  1321 		mdio_delay ();
       
  1322 		RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
       
  1323 		mdio_delay ();
       
  1324 	}
       
  1325 
       
  1326 	/* Read the two transition, 16 data, and wire-idle bits. */
       
  1327 	for (i = 19; i > 0; i--) {
       
  1328 		RTL_W8 (Config4, 0);
       
  1329 		mdio_delay ();
       
  1330 		retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
       
  1331 		RTL_W8 (Config4, MDIO_CLK);
       
  1332 		mdio_delay ();
       
  1333 	}
       
  1334 #endif
       
  1335 
       
  1336 	return (retval >> 1) & 0xffff;
       
  1337 }
       
  1338 
       
  1339 
       
  1340 static void mdio_write (struct net_device *dev, int phy_id, int location,
       
  1341 			int value)
       
  1342 {
       
  1343 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1344 #ifdef CONFIG_8139TOO_8129
       
  1345 	void __iomem *ioaddr = tp->mmio_addr;
       
  1346 	int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
       
  1347 	int i;
       
  1348 #endif
       
  1349 
       
  1350 	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
       
  1351 		void __iomem *ioaddr = tp->mmio_addr;
       
  1352 		if (location == 0) {
       
  1353 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  1354 			RTL_W16 (BasicModeCtrl, value);
       
  1355 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1356 		} else if (location < 8 && mii_2_8139_map[location])
       
  1357 			RTL_W16 (mii_2_8139_map[location], value);
       
  1358 		return;
       
  1359 	}
       
  1360 
       
  1361 #ifdef CONFIG_8139TOO_8129
       
  1362 	mdio_sync (ioaddr);
       
  1363 
       
  1364 	/* Shift the command bits out. */
       
  1365 	for (i = 31; i >= 0; i--) {
       
  1366 		int dataval =
       
  1367 		    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
       
  1368 		RTL_W8 (Config4, dataval);
       
  1369 		mdio_delay ();
       
  1370 		RTL_W8 (Config4, dataval | MDIO_CLK);
       
  1371 		mdio_delay ();
       
  1372 	}
       
  1373 	/* Clear out extra bits. */
       
  1374 	for (i = 2; i > 0; i--) {
       
  1375 		RTL_W8 (Config4, 0);
       
  1376 		mdio_delay ();
       
  1377 		RTL_W8 (Config4, MDIO_CLK);
       
  1378 		mdio_delay ();
       
  1379 	}
       
  1380 #endif
       
  1381 }
       
  1382 
       
  1383 
       
  1384 static int rtl8139_open (struct net_device *dev)
       
  1385 {
       
  1386 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1387 	void __iomem *ioaddr = tp->mmio_addr;
       
  1388 	const int irq = tp->pci_dev->irq;
       
  1389 	int retval;
       
  1390 
       
  1391 	if (!tp->ecdev) {
       
  1392 		retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
       
  1393 		if (retval)
       
  1394 			return retval;
       
  1395 	}
       
  1396 
       
  1397 	tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  1398 					   &tp->tx_bufs_dma, GFP_KERNEL);
       
  1399 	tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  1400 					   &tp->rx_ring_dma, GFP_KERNEL);
       
  1401 	if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
       
  1402 		if (!tp->ecdev) {
       
  1403 			free_irq(irq, dev);
       
  1404 		}
       
  1405 
       
  1406 		if (tp->tx_bufs)
       
  1407 			dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  1408 					    tp->tx_bufs, tp->tx_bufs_dma);
       
  1409 		if (tp->rx_ring)
       
  1410 			dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  1411 					    tp->rx_ring, tp->rx_ring_dma);
       
  1412 
       
  1413 		return -ENOMEM;
       
  1414 
       
  1415 	}
       
  1416 
       
  1417 	napi_enable(&tp->napi);
       
  1418 
       
  1419 	tp->mii.full_duplex = tp->mii.force_media;
       
  1420 	tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
       
  1421 
       
  1422 	rtl8139_init_ring (dev);
       
  1423 	rtl8139_hw_start (dev);
       
  1424 	if (!tp->ecdev) {
       
  1425 		netif_start_queue (dev);
       
  1426 	}
       
  1427 
       
  1428 	netif_dbg(tp, ifup, dev,
       
  1429 		  "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
       
  1430 		  __func__,
       
  1431 		  (unsigned long long)pci_resource_start (tp->pci_dev, 1),
       
  1432 		  irq, RTL_R8 (MediaStatus),
       
  1433 		  tp->mii.full_duplex ? "full" : "half");
       
  1434 
       
  1435 	if (!tp->ecdev) {
       
  1436 		rtl8139_start_thread(tp);
       
  1437 	}
       
  1438 
       
  1439 	return 0;
       
  1440 }
       
  1441 
       
  1442 
       
  1443 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
       
  1444 {
       
  1445 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1446 
       
  1447 	if (tp->ecdev) {
       
  1448 		void __iomem *ioaddr = tp->mmio_addr;
       
  1449 		u16 state = RTL_R16(BasicModeStatus) & BMSR_LSTATUS;
       
  1450 		ecdev_set_link(tp->ecdev, state ? 1 : 0);
       
  1451 	}
       
  1452 	else {
       
  1453 		if (tp->phys[0] >= 0) {
       
  1454 			mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
       
  1455 		}
       
  1456 	}
       
  1457 }
       
  1458 
       
  1459 /* Start the hardware at open or resume. */
       
  1460 static void rtl8139_hw_start (struct net_device *dev)
       
  1461 {
       
  1462 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1463 	void __iomem *ioaddr = tp->mmio_addr;
       
  1464 	u32 i;
       
  1465 	u8 tmp;
       
  1466 
       
  1467 	/* Bring old chips out of low-power mode. */
       
  1468 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  1469 		RTL_W8 (HltClk, 'R');
       
  1470 
       
  1471 	rtl8139_chip_reset (ioaddr);
       
  1472 
       
  1473 	/* unlock Config[01234] and BMCR register writes */
       
  1474 	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
       
  1475 	/* Restore our idea of the MAC address. */
       
  1476 	RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
       
  1477 	RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
       
  1478 
       
  1479 	tp->cur_rx = 0;
       
  1480 
       
  1481 	/* init Rx ring buffer DMA address */
       
  1482 	RTL_W32_F (RxBuf, tp->rx_ring_dma);
       
  1483 
       
  1484 	/* Must enable Tx/Rx before setting transfer thresholds! */
       
  1485 	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1486 
       
  1487 	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
       
  1488 	RTL_W32 (RxConfig, tp->rx_config);
       
  1489 	RTL_W32 (TxConfig, rtl8139_tx_config);
       
  1490 
       
  1491 	rtl_check_media (dev, 1);
       
  1492 
       
  1493 	if (tp->chipset >= CH_8139B) {
       
  1494 		/* Disable magic packet scanning, which is enabled
       
  1495 		 * when PM is enabled in Config1.  It can be reenabled
       
  1496 		 * via ETHTOOL_SWOL if desired.  */
       
  1497 		RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
       
  1498 	}
       
  1499 
       
  1500 	netdev_dbg(dev, "init buffer addresses\n");
       
  1501 
       
  1502 	/* Lock Config[01234] and BMCR register writes */
       
  1503 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1504 
       
  1505 	/* init Tx buffer DMA addresses */
       
  1506 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1507 		RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
       
  1508 
       
  1509 	RTL_W32 (RxMissed, 0);
       
  1510 
       
  1511 	rtl8139_set_rx_mode (dev);
       
  1512 
       
  1513 	/* no early-rx interrupts */
       
  1514 	RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
       
  1515 
       
  1516 	/* make sure RxTx has started */
       
  1517 	tmp = RTL_R8 (ChipCmd);
       
  1518 	if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
       
  1519 		RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1520 
       
  1521 	if (!tp->ecdev) {
       
  1522 		/* Enable all known interrupts by setting the interrupt mask. */
       
  1523 		RTL_W16 (IntrMask, rtl8139_intr_mask);
       
  1524 	}
       
  1525 }
       
  1526 
       
  1527 
       
  1528 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
       
  1529 static void rtl8139_init_ring (struct net_device *dev)
       
  1530 {
       
  1531 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1532 	int i;
       
  1533 
       
  1534 	tp->cur_rx = 0;
       
  1535 	tp->cur_tx = 0;
       
  1536 	tp->dirty_tx = 0;
       
  1537 
       
  1538 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1539 		tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
       
  1540 }
       
  1541 
       
  1542 
       
  1543 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
       
  1544 static int next_tick = 3 * HZ;
       
  1545 
       
  1546 #ifndef CONFIG_8139TOO_TUNE_TWISTER
       
  1547 static inline void rtl8139_tune_twister (struct net_device *dev,
       
  1548 				  struct rtl8139_private *tp) {}
       
  1549 #else
       
  1550 enum TwisterParamVals {
       
  1551 	PARA78_default	= 0x78fa8388,
       
  1552 	PARA7c_default	= 0xcb38de43,	/* param[0][3] */
       
  1553 	PARA7c_xxx	= 0xcb38de43,
       
  1554 };
       
  1555 
       
  1556 static const unsigned long param[4][4] = {
       
  1557 	{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
       
  1558 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
       
  1559 	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
       
  1560 	{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
       
  1561 };
       
  1562 
       
  1563 static void rtl8139_tune_twister (struct net_device *dev,
       
  1564 				  struct rtl8139_private *tp)
       
  1565 {
       
  1566 	int linkcase;
       
  1567 	void __iomem *ioaddr = tp->mmio_addr;
       
  1568 
       
  1569 	/* This is a complicated state machine to configure the "twister" for
       
  1570 	   impedance/echos based on the cable length.
       
  1571 	   All of this is magic and undocumented.
       
  1572 	 */
       
  1573 	switch (tp->twistie) {
       
  1574 	case 1:
       
  1575 		if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
       
  1576 			/* We have link beat, let us tune the twister. */
       
  1577 			RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
       
  1578 			tp->twistie = 2;	/* Change to state 2. */
       
  1579 			next_tick = HZ / 10;
       
  1580 		} else {
       
  1581 			/* Just put in some reasonable defaults for when beat returns. */
       
  1582 			RTL_W16 (CSCR, CSCR_LinkDownCmd);
       
  1583 			RTL_W32 (FIFOTMS, 0x20);	/* Turn on cable test mode. */
       
  1584 			RTL_W32 (PARA78, PARA78_default);
       
  1585 			RTL_W32 (PARA7c, PARA7c_default);
       
  1586 			tp->twistie = 0;	/* Bail from future actions. */
       
  1587 		}
       
  1588 		break;
       
  1589 	case 2:
       
  1590 		/* Read how long it took to hear the echo. */
       
  1591 		linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
       
  1592 		if (linkcase == 0x7000)
       
  1593 			tp->twist_row = 3;
       
  1594 		else if (linkcase == 0x3000)
       
  1595 			tp->twist_row = 2;
       
  1596 		else if (linkcase == 0x1000)
       
  1597 			tp->twist_row = 1;
       
  1598 		else
       
  1599 			tp->twist_row = 0;
       
  1600 		tp->twist_col = 0;
       
  1601 		tp->twistie = 3;	/* Change to state 2. */
       
  1602 		next_tick = HZ / 10;
       
  1603 		break;
       
  1604 	case 3:
       
  1605 		/* Put out four tuning parameters, one per 100msec. */
       
  1606 		if (tp->twist_col == 0)
       
  1607 			RTL_W16 (FIFOTMS, 0);
       
  1608 		RTL_W32 (PARA7c, param[(int) tp->twist_row]
       
  1609 			 [(int) tp->twist_col]);
       
  1610 		next_tick = HZ / 10;
       
  1611 		if (++tp->twist_col >= 4) {
       
  1612 			/* For short cables we are done.
       
  1613 			   For long cables (row == 3) check for mistune. */
       
  1614 			tp->twistie =
       
  1615 			    (tp->twist_row == 3) ? 4 : 0;
       
  1616 		}
       
  1617 		break;
       
  1618 	case 4:
       
  1619 		/* Special case for long cables: check for mistune. */
       
  1620 		if ((RTL_R16 (CSCR) &
       
  1621 		     CSCR_LinkStatusBits) == 0x7000) {
       
  1622 			tp->twistie = 0;
       
  1623 			break;
       
  1624 		} else {
       
  1625 			RTL_W32 (PARA7c, 0xfb38de03);
       
  1626 			tp->twistie = 5;
       
  1627 			next_tick = HZ / 10;
       
  1628 		}
       
  1629 		break;
       
  1630 	case 5:
       
  1631 		/* Retune for shorter cable (column 2). */
       
  1632 		RTL_W32 (FIFOTMS, 0x20);
       
  1633 		RTL_W32 (PARA78, PARA78_default);
       
  1634 		RTL_W32 (PARA7c, PARA7c_default);
       
  1635 		RTL_W32 (FIFOTMS, 0x00);
       
  1636 		tp->twist_row = 2;
       
  1637 		tp->twist_col = 0;
       
  1638 		tp->twistie = 3;
       
  1639 		next_tick = HZ / 10;
       
  1640 		break;
       
  1641 
       
  1642 	default:
       
  1643 		/* do nothing */
       
  1644 		break;
       
  1645 	}
       
  1646 }
       
  1647 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
       
  1648 
       
  1649 static inline void rtl8139_thread_iter (struct net_device *dev,
       
  1650 				 struct rtl8139_private *tp,
       
  1651 				 void __iomem *ioaddr)
       
  1652 {
       
  1653 	int mii_lpa;
       
  1654 
       
  1655 	mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
       
  1656 
       
  1657 	if (!tp->mii.force_media && mii_lpa != 0xffff) {
       
  1658 		int duplex = ((mii_lpa & LPA_100FULL) ||
       
  1659 			      (mii_lpa & 0x01C0) == 0x0040);
       
  1660 		if (tp->mii.full_duplex != duplex) {
       
  1661 			tp->mii.full_duplex = duplex;
       
  1662 
       
  1663 			if (mii_lpa) {
       
  1664 				netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
       
  1665 					    tp->mii.full_duplex ? "full" : "half",
       
  1666 					    tp->phys[0], mii_lpa);
       
  1667 			} else {
       
  1668 				netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
       
  1669 			}
       
  1670 #if 0
       
  1671 			RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  1672 			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
       
  1673 			RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  1674 #endif
       
  1675 		}
       
  1676 	}
       
  1677 
       
  1678 	next_tick = HZ * 60;
       
  1679 
       
  1680 	rtl8139_tune_twister (dev, tp);
       
  1681 
       
  1682 	netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
       
  1683 		   RTL_R16(NWayLPAR));
       
  1684 	netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
       
  1685 		   RTL_R16(IntrMask), RTL_R16(IntrStatus));
       
  1686 	netdev_dbg(dev, "Chip config %02x %02x\n",
       
  1687 		   RTL_R8(Config0), RTL_R8(Config1));
       
  1688 }
       
  1689 
       
  1690 static void rtl8139_thread (struct work_struct *work)
       
  1691 {
       
  1692 	struct rtl8139_private *tp =
       
  1693 		container_of(work, struct rtl8139_private, thread.work);
       
  1694 	struct net_device *dev = tp->mii.dev;
       
  1695 	unsigned long thr_delay = next_tick;
       
  1696 
       
  1697 	rtnl_lock();
       
  1698 
       
  1699 	if (!netif_running(dev))
       
  1700 		goto out_unlock;
       
  1701 
       
  1702 	if (tp->watchdog_fired) {
       
  1703 		tp->watchdog_fired = 0;
       
  1704 		rtl8139_tx_timeout_task(work);
       
  1705 	} else
       
  1706 		rtl8139_thread_iter(dev, tp, tp->mmio_addr);
       
  1707 
       
  1708 	if (tp->have_thread)
       
  1709 		schedule_delayed_work(&tp->thread, thr_delay);
       
  1710 out_unlock:
       
  1711 	rtnl_unlock ();
       
  1712 }
       
  1713 
       
  1714 static void rtl8139_start_thread(struct rtl8139_private *tp)
       
  1715 {
       
  1716 	tp->twistie = 0;
       
  1717 	if (tp->chipset == CH_8139_K)
       
  1718 		tp->twistie = 1;
       
  1719 	else if (tp->drv_flags & HAS_LNK_CHNG)
       
  1720 		return;
       
  1721 
       
  1722 	tp->have_thread = 1;
       
  1723 	tp->watchdog_fired = 0;
       
  1724 
       
  1725 	schedule_delayed_work(&tp->thread, next_tick);
       
  1726 }
       
  1727 
       
  1728 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
       
  1729 {
       
  1730 	tp->cur_tx = 0;
       
  1731 	tp->dirty_tx = 0;
       
  1732 
       
  1733 	/* XXX account for unsent Tx packets in tp->stats.tx_dropped */
       
  1734 }
       
  1735 
       
  1736 static void rtl8139_tx_timeout_task (struct work_struct *work)
       
  1737 {
       
  1738 	struct rtl8139_private *tp =
       
  1739 		container_of(work, struct rtl8139_private, thread.work);
       
  1740 	struct net_device *dev = tp->mii.dev;
       
  1741 	void __iomem *ioaddr = tp->mmio_addr;
       
  1742 	int i;
       
  1743 	u8 tmp8;
       
  1744 
       
  1745 	netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
       
  1746 		   RTL_R8(ChipCmd), RTL_R16(IntrStatus),
       
  1747 		   RTL_R16(IntrMask), RTL_R8(MediaStatus));
       
  1748 	/* Emit info to figure out what went wrong. */
       
  1749 	netdev_dbg(dev, "Tx queue start entry %ld  dirty entry %ld\n",
       
  1750 		   tp->cur_tx, tp->dirty_tx);
       
  1751 	for (i = 0; i < NUM_TX_DESC; i++)
       
  1752 		netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
       
  1753 			   i, RTL_R32(TxStatus0 + (i * 4)),
       
  1754 			   i == tp->dirty_tx % NUM_TX_DESC ?
       
  1755 			   " (queue head)" : "");
       
  1756 
       
  1757 	tp->xstats.tx_timeouts++;
       
  1758 
       
  1759 	/* disable Tx ASAP, if not already */
       
  1760 	tmp8 = RTL_R8 (ChipCmd);
       
  1761 	if (tmp8 & CmdTxEnb)
       
  1762 		RTL_W8 (ChipCmd, CmdRxEnb);
       
  1763 
       
  1764 	if (tp->ecdev) {
       
  1765 		rtl8139_tx_clear (tp);
       
  1766 		rtl8139_hw_start (dev);
       
  1767 	}
       
  1768 	else {
       
  1769 		spin_lock_bh(&tp->rx_lock);
       
  1770 
       
  1771 		/* Disable interrupts by clearing the interrupt mask. */
       
  1772 		RTL_W16 (IntrMask, 0x0000);
       
  1773 
       
  1774 		/* Stop a shared interrupt from scavenging while we are. */
       
  1775 		spin_lock_irq(&tp->lock);
       
  1776 		rtl8139_tx_clear (tp);
       
  1777 		spin_unlock_irq(&tp->lock);
       
  1778 
       
  1779 		/* ...and finally, reset everything */
       
  1780 		if (netif_running(dev)) {
       
  1781 			rtl8139_hw_start (dev);
       
  1782 			netif_wake_queue (dev);
       
  1783 		}
       
  1784 
       
  1785 		spin_unlock_bh(&tp->rx_lock);
       
  1786 	}
       
  1787 }
       
  1788 
       
  1789 static void rtl8139_tx_timeout (struct net_device *dev)
       
  1790 {
       
  1791 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1792 
       
  1793 	tp->watchdog_fired = 1;
       
  1794 	if (!tp->ecdev && !tp->have_thread) {
       
  1795 		INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
       
  1796 		schedule_delayed_work(&tp->thread, next_tick);
       
  1797 	}
       
  1798 }
       
  1799 
       
  1800 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
       
  1801 					     struct net_device *dev)
       
  1802 {
       
  1803 	struct rtl8139_private *tp = netdev_priv(dev);
       
  1804 	void __iomem *ioaddr = tp->mmio_addr;
       
  1805 	unsigned int entry;
       
  1806 	unsigned int len = skb->len;
       
  1807 	unsigned long flags = 0;
       
  1808 
       
  1809 	/* Calculate the next Tx descriptor entry. */
       
  1810 	entry = tp->cur_tx % NUM_TX_DESC;
       
  1811 
       
  1812 	/* Note: the chip doesn't have auto-pad! */
       
  1813 	if (likely(len < TX_BUF_SIZE)) {
       
  1814 		if (len < ETH_ZLEN)
       
  1815 			memset(tp->tx_buf[entry], 0, ETH_ZLEN);
       
  1816 		skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
       
  1817 		if (!tp->ecdev) {
       
  1818 			dev_kfree_skb(skb);
       
  1819 		}
       
  1820 	} else {
       
  1821 		if (!tp->ecdev) {
       
  1822 			dev_kfree_skb(skb);
       
  1823 		}
       
  1824 		dev->stats.tx_dropped++;
       
  1825 		return NETDEV_TX_OK;
       
  1826 	}
       
  1827 
       
  1828 	if (!tp->ecdev) {
       
  1829 		spin_lock_irqsave(&tp->lock, flags);
       
  1830 	}
       
  1831 	/*
       
  1832 	 * Writing to TxStatus triggers a DMA transfer of the data
       
  1833 	 * copied to tp->tx_buf[entry] above. Use a memory barrier
       
  1834 	 * to make sure that the device sees the updated data.
       
  1835 	 */
       
  1836 	wmb();
       
  1837 	RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
       
  1838 		   tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
       
  1839 
       
  1840 	tp->cur_tx++;
       
  1841 
       
  1842 	if (!tp->ecdev) {
       
  1843 		if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
       
  1844 			netif_stop_queue (dev);
       
  1845 		spin_unlock_irqrestore(&tp->lock, flags);
       
  1846 	}
       
  1847 
       
  1848 	netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
       
  1849 		  len, entry);
       
  1850 
       
  1851 	return NETDEV_TX_OK;
       
  1852 }
       
  1853 
       
  1854 
       
  1855 static void rtl8139_tx_interrupt (struct net_device *dev,
       
  1856 				  struct rtl8139_private *tp,
       
  1857 				  void __iomem *ioaddr)
       
  1858 {
       
  1859 	unsigned long dirty_tx, tx_left;
       
  1860 
       
  1861 	assert (dev != NULL);
       
  1862 	assert (ioaddr != NULL);
       
  1863 
       
  1864 	dirty_tx = tp->dirty_tx;
       
  1865 	tx_left = tp->cur_tx - dirty_tx;
       
  1866 	while (tx_left > 0) {
       
  1867 		int entry = dirty_tx % NUM_TX_DESC;
       
  1868 		int txstatus;
       
  1869 
       
  1870 		txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
       
  1871 
       
  1872 		if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
       
  1873 			break;	/* It still hasn't been Txed */
       
  1874 
       
  1875 		/* Note: TxCarrierLost is always asserted at 100mbps. */
       
  1876 		if (txstatus & (TxOutOfWindow | TxAborted)) {
       
  1877 			/* There was an major error, log it. */
       
  1878 			netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
       
  1879 				  txstatus);
       
  1880 			dev->stats.tx_errors++;
       
  1881 			if (txstatus & TxAborted) {
       
  1882 				dev->stats.tx_aborted_errors++;
       
  1883 				RTL_W32 (TxConfig, TxClearAbt);
       
  1884 				RTL_W16 (IntrStatus, TxErr);
       
  1885 				wmb();
       
  1886 			}
       
  1887 			if (txstatus & TxCarrierLost)
       
  1888 				dev->stats.tx_carrier_errors++;
       
  1889 			if (txstatus & TxOutOfWindow)
       
  1890 				dev->stats.tx_window_errors++;
       
  1891 		} else {
       
  1892 			if (txstatus & TxUnderrun) {
       
  1893 				/* Add 64 to the Tx FIFO threshold. */
       
  1894 				if (tp->tx_flag < 0x00300000)
       
  1895 					tp->tx_flag += 0x00020000;
       
  1896 				dev->stats.tx_fifo_errors++;
       
  1897 			}
       
  1898 			dev->stats.collisions += (txstatus >> 24) & 15;
       
  1899 			u64_stats_update_begin(&tp->tx_stats.syncp);
       
  1900 			tp->tx_stats.packets++;
       
  1901 			tp->tx_stats.bytes += txstatus & 0x7ff;
       
  1902 			u64_stats_update_end(&tp->tx_stats.syncp);
       
  1903 		}
       
  1904 
       
  1905 		dirty_tx++;
       
  1906 		tx_left--;
       
  1907 	}
       
  1908 
       
  1909 #ifndef RTL8139_NDEBUG
       
  1910 	if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
       
  1911 		pr_err("%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
       
  1912 		        dev->name, dirty_tx, tp->cur_tx);
       
  1913 		dirty_tx += NUM_TX_DESC;
       
  1914 	}
       
  1915 #endif /* RTL8139_NDEBUG */
       
  1916 
       
  1917 	/* only wake the queue if we did work, and the queue is stopped */
       
  1918 	if (tp->dirty_tx != dirty_tx) {
       
  1919 		tp->dirty_tx = dirty_tx;
       
  1920 		mb();
       
  1921 		if (!tp->ecdev) {
       
  1922 			netif_wake_queue (dev);
       
  1923 		}
       
  1924 	}
       
  1925 }
       
  1926 
       
  1927 
       
  1928 /* TODO: clean this up!  Rx reset need not be this intensive */
       
  1929 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
       
  1930 			    struct rtl8139_private *tp, void __iomem *ioaddr)
       
  1931 {
       
  1932 	u8 tmp8;
       
  1933 #ifdef CONFIG_8139_OLD_RX_RESET
       
  1934 	int tmp_work;
       
  1935 #endif
       
  1936 
       
  1937 	if (netif_msg_rx_err (tp))
       
  1938 		pr_debug("%s: Ethernet frame had errors, status %8.8x.\n",
       
  1939 			dev->name, rx_status);
       
  1940 	dev->stats.rx_errors++;
       
  1941 	if (!(rx_status & RxStatusOK)) {
       
  1942 		if (rx_status & RxTooLong) {
       
  1943 			pr_debug("%s: Oversized Ethernet frame, status %4.4x!\n",
       
  1944 			 	dev->name, rx_status);
       
  1945 			/* A.C.: The chip hangs here. */
       
  1946 		}
       
  1947 		if (rx_status & (RxBadSymbol | RxBadAlign))
       
  1948 			dev->stats.rx_frame_errors++;
       
  1949 		if (rx_status & (RxRunt | RxTooLong))
       
  1950 			dev->stats.rx_length_errors++;
       
  1951 		if (rx_status & RxCRCErr)
       
  1952 			dev->stats.rx_crc_errors++;
       
  1953 	} else {
       
  1954 		tp->xstats.rx_lost_in_ring++;
       
  1955 	}
       
  1956 
       
  1957 #ifndef CONFIG_8139_OLD_RX_RESET
       
  1958 	tmp8 = RTL_R8 (ChipCmd);
       
  1959 	RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
       
  1960 	RTL_W8 (ChipCmd, tmp8);
       
  1961 	RTL_W32 (RxConfig, tp->rx_config);
       
  1962 	tp->cur_rx = 0;
       
  1963 #else
       
  1964 	/* Reset the receiver, based on RealTek recommendation. (Bug?) */
       
  1965 
       
  1966 	/* disable receive */
       
  1967 	RTL_W8_F (ChipCmd, CmdTxEnb);
       
  1968 	tmp_work = 200;
       
  1969 	while (--tmp_work > 0) {
       
  1970 		udelay(1);
       
  1971 		tmp8 = RTL_R8 (ChipCmd);
       
  1972 		if (!(tmp8 & CmdRxEnb))
       
  1973 			break;
       
  1974 	}
       
  1975 	if (tmp_work <= 0)
       
  1976 		pr_warning(PFX "rx stop wait too long\n");
       
  1977 	/* restart receive */
       
  1978 	tmp_work = 200;
       
  1979 	while (--tmp_work > 0) {
       
  1980 		RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1981 		udelay(1);
       
  1982 		tmp8 = RTL_R8 (ChipCmd);
       
  1983 		if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
       
  1984 			break;
       
  1985 	}
       
  1986 	if (tmp_work <= 0)
       
  1987 		pr_warning(PFX "tx/rx enable wait too long\n");
       
  1988 
       
  1989 	/* and reinitialize all rx related registers */
       
  1990 	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
       
  1991 	/* Must enable Tx/Rx before setting transfer thresholds! */
       
  1992 	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
       
  1993 
       
  1994 	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
       
  1995 	RTL_W32 (RxConfig, tp->rx_config);
       
  1996 	tp->cur_rx = 0;
       
  1997 
       
  1998 	pr_debug("init buffer addresses\n");
       
  1999 
       
  2000 	/* Lock Config[01234] and BMCR register writes */
       
  2001 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  2002 
       
  2003 	/* init Rx ring buffer DMA address */
       
  2004 	RTL_W32_F (RxBuf, tp->rx_ring_dma);
       
  2005 
       
  2006 	/* A.C.: Reset the multicast list. */
       
  2007 	__set_rx_mode (dev);
       
  2008 #endif
       
  2009 }
       
  2010 
       
  2011 #if RX_BUF_IDX == 3
       
  2012 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
       
  2013 				 u32 offset, unsigned int size)
       
  2014 {
       
  2015 	u32 left = RX_BUF_LEN - offset;
       
  2016 
       
  2017 	if (size > left) {
       
  2018 		skb_copy_to_linear_data(skb, ring + offset, left);
       
  2019 		skb_copy_to_linear_data_offset(skb, left, ring, size - left);
       
  2020 	} else
       
  2021 		skb_copy_to_linear_data(skb, ring + offset, size);
       
  2022 }
       
  2023 #endif
       
  2024 
       
  2025 static void rtl8139_isr_ack(struct rtl8139_private *tp)
       
  2026 {
       
  2027 	void __iomem *ioaddr = tp->mmio_addr;
       
  2028 	u16 status;
       
  2029 
       
  2030 	status = RTL_R16 (IntrStatus) & RxAckBits;
       
  2031 
       
  2032 	/* Clear out errors and receive interrupts */
       
  2033 	if (likely(status != 0)) {
       
  2034 		if (unlikely(status & (RxFIFOOver | RxOverflow))) {
       
  2035 			tp->dev->stats.rx_errors++;
       
  2036 			if (status & RxFIFOOver)
       
  2037 				tp->dev->stats.rx_fifo_errors++;
       
  2038 		}
       
  2039 		RTL_W16_F (IntrStatus, RxAckBits);
       
  2040 	}
       
  2041 }
       
  2042 
       
  2043 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
       
  2044 		      int budget)
       
  2045 {
       
  2046 	void __iomem *ioaddr = tp->mmio_addr;
       
  2047 	int received = 0;
       
  2048 	unsigned char *rx_ring = tp->rx_ring;
       
  2049 	unsigned int cur_rx = tp->cur_rx;
       
  2050 	unsigned int rx_size = 0;
       
  2051 
       
  2052 	pr_debug("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
       
  2053 		 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
       
  2054 		 RTL_R16 (RxBufAddr),
       
  2055 		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
       
  2056 
       
  2057 	while ((tp->ecdev || netif_running(dev))
       
  2058 			&& received < budget
       
  2059 			&& (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
       
  2060 		u32 ring_offset = cur_rx % RX_BUF_LEN;
       
  2061 		u32 rx_status;
       
  2062 		unsigned int pkt_size;
       
  2063 		struct sk_buff *skb;
       
  2064 
       
  2065 		rmb();
       
  2066 
       
  2067 		/* read size+status of next frame from DMA ring buffer */
       
  2068 		rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
       
  2069 		rx_size = rx_status >> 16;
       
  2070 		if (likely(!(dev->features & NETIF_F_RXFCS)))
       
  2071 			pkt_size = rx_size - 4;
       
  2072 		else
       
  2073 			pkt_size = rx_size;
       
  2074 
       
  2075 		if (!tp->ecdev) {
       
  2076 			if (netif_msg_rx_status(tp))
       
  2077 				pr_debug("%s:  rtl8139_rx() status %4.4x, size %4.4x,"
       
  2078 					" cur %4.4x.\n", dev->name, rx_status,
       
  2079 				 rx_size, cur_rx);
       
  2080 		}
       
  2081 #if RTL8139_DEBUG > 2
       
  2082 		{
       
  2083 			int i;
       
  2084 			pr_debug("%s: Frame contents ", dev->name);
       
  2085 			for (i = 0; i < 70; i++)
       
  2086 				pr_cont(" %2.2x",
       
  2087 					rx_ring[ring_offset + i]);
       
  2088 			pr_cont(".\n");
       
  2089 		}
       
  2090 #endif
       
  2091 
       
  2092 		/* Packet copy from FIFO still in progress.
       
  2093 		 * Theoretically, this should never happen
       
  2094 		 * since EarlyRx is disabled.
       
  2095 		 */
       
  2096 		if (unlikely(rx_size == 0xfff0)) {
       
  2097 			if (!tp->fifo_copy_timeout)
       
  2098 				tp->fifo_copy_timeout = jiffies + 2;
       
  2099 			else if (time_after(jiffies, tp->fifo_copy_timeout)) {
       
  2100 				pr_debug("%s: hung FIFO. Reset.", dev->name);
       
  2101 				rx_size = 0;
       
  2102 				goto no_early_rx;
       
  2103 			}
       
  2104 			if (netif_msg_intr(tp)) {
       
  2105 				pr_debug("%s: fifo copy in progress.",
       
  2106 				       dev->name);
       
  2107 			}
       
  2108 			tp->xstats.early_rx++;
       
  2109 			break;
       
  2110 		}
       
  2111 
       
  2112 no_early_rx:
       
  2113 		tp->fifo_copy_timeout = 0;
       
  2114 
       
  2115 		/* If Rx err or invalid rx_size/rx_status received
       
  2116 		 * (which happens if we get lost in the ring),
       
  2117 		 * Rx process gets reset, so we abort any further
       
  2118 		 * Rx processing.
       
  2119 		 */
       
  2120 		if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
       
  2121 			     (rx_size < 8) ||
       
  2122 			     (!(rx_status & RxStatusOK)))) {
       
  2123 			if ((dev->features & NETIF_F_RXALL) &&
       
  2124 			    (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
       
  2125 			    (rx_size >= 8) &&
       
  2126 			    (!(rx_status & RxStatusOK))) {
       
  2127 				/* Length is at least mostly OK, but pkt has
       
  2128 				 * error.  I'm hoping we can handle some of these
       
  2129 				 * errors without resetting the chip. --Ben
       
  2130 				 */
       
  2131 				dev->stats.rx_errors++;
       
  2132 				if (rx_status & RxCRCErr) {
       
  2133 					dev->stats.rx_crc_errors++;
       
  2134 					goto keep_pkt;
       
  2135 				}
       
  2136 				if (rx_status & RxRunt) {
       
  2137 					dev->stats.rx_length_errors++;
       
  2138 					goto keep_pkt;
       
  2139 				}
       
  2140 			}
       
  2141 			rtl8139_rx_err (rx_status, dev, tp, ioaddr);
       
  2142 			received = -1;
       
  2143 			goto out;
       
  2144 		}
       
  2145 
       
  2146 keep_pkt:
       
  2147 		if (tp->ecdev) {
       
  2148 			ecdev_receive(tp->ecdev,
       
  2149 					&rx_ring[ring_offset + 4], pkt_size);
       
  2150 					dev->last_rx = jiffies;
       
  2151 					dev->stats.rx_bytes += pkt_size;
       
  2152 					dev->stats.rx_packets++;
       
  2153 		} else {
       
  2154 			/* Malloc up new buffer, compatible with net-2e. */
       
  2155 			/* Omit the four octet CRC from the length. */
       
  2156 
       
  2157 			skb = netdev_alloc_skb_ip_align(dev, pkt_size);
       
  2158 			if (likely(skb)) {
       
  2159 #if RX_BUF_IDX == 3
       
  2160 				wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
       
  2161 #else
       
  2162 				skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4],
       
  2163 						pkt_size);
       
  2164 #endif
       
  2165 				skb_put (skb, pkt_size);
       
  2166 
       
  2167 				skb->protocol = eth_type_trans (skb, dev);
       
  2168 
       
  2169 				u64_stats_update_begin(&tp->rx_stats.syncp);
       
  2170 				tp->rx_stats.packets++;
       
  2171 				tp->rx_stats.bytes += pkt_size;
       
  2172 				u64_stats_update_end(&tp->rx_stats.syncp);
       
  2173 
       
  2174 				netif_receive_skb (skb);
       
  2175 			} else {
       
  2176 				if (net_ratelimit())
       
  2177 					netdev_warn(dev, "Memory squeeze, dropping packet\n");
       
  2178 				dev->stats.rx_dropped++;
       
  2179 			}
       
  2180 		}
       
  2181 		received++;
       
  2182 
       
  2183 		cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
       
  2184 		RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
       
  2185 
       
  2186 		rtl8139_isr_ack(tp);
       
  2187 	}
       
  2188 
       
  2189 	if (unlikely(!received || rx_size == 0xfff0))
       
  2190 		rtl8139_isr_ack(tp);
       
  2191 
       
  2192 	pr_debug("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
       
  2193 		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
       
  2194 		 RTL_R16 (RxBufAddr),
       
  2195 		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
       
  2196 
       
  2197 	tp->cur_rx = cur_rx;
       
  2198 
       
  2199 	/*
       
  2200 	 * The receive buffer should be mostly empty.
       
  2201 	 * Tell NAPI to reenable the Rx irq.
       
  2202 	 */
       
  2203 	if (tp->fifo_copy_timeout)
       
  2204 		received = budget;
       
  2205 
       
  2206 out:
       
  2207 	return received;
       
  2208 }
       
  2209 
       
  2210 
       
  2211 static void rtl8139_weird_interrupt (struct net_device *dev,
       
  2212 				     struct rtl8139_private *tp,
       
  2213 				     void __iomem *ioaddr,
       
  2214 				     int status, int link_changed)
       
  2215 {
       
  2216 	pr_debug("%s: Abnormal interrupt, status %8.8x.\n",
       
  2217 		 dev->name, status);
       
  2218 
       
  2219 	assert (dev != NULL);
       
  2220 	assert (tp != NULL);
       
  2221 	assert (ioaddr != NULL);
       
  2222 
       
  2223 	/* Update the error count. */
       
  2224 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2225 	RTL_W32 (RxMissed, 0);
       
  2226 
       
  2227 	if ((status & RxUnderrun) && link_changed &&
       
  2228 	    (tp->drv_flags & HAS_LNK_CHNG)) {
       
  2229 		rtl_check_media(dev, 0);
       
  2230 		status &= ~RxUnderrun;
       
  2231 	}
       
  2232 
       
  2233 	if (status & (RxUnderrun | RxErr))
       
  2234 		dev->stats.rx_errors++;
       
  2235 
       
  2236 	if (status & PCSTimeout)
       
  2237 		dev->stats.rx_length_errors++;
       
  2238 	if (status & RxUnderrun)
       
  2239 		dev->stats.rx_fifo_errors++;
       
  2240 	if (status & PCIErr) {
       
  2241 		u16 pci_cmd_status;
       
  2242 		pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
       
  2243 		pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
       
  2244 
       
  2245 		pr_err("%s: PCI Bus error %4.4x.\n",
       
  2246 			dev->name, pci_cmd_status);
       
  2247 	}
       
  2248 }
       
  2249 
       
  2250 static int rtl8139_poll(struct napi_struct *napi, int budget)
       
  2251 {
       
  2252 	struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
       
  2253 	struct net_device *dev = tp->dev;
       
  2254 	void __iomem *ioaddr = tp->mmio_addr;
       
  2255 	int work_done;
       
  2256 
       
  2257 	spin_lock(&tp->rx_lock);
       
  2258 	work_done = 0;
       
  2259 	if (likely(RTL_R16(IntrStatus) & RxAckBits))
       
  2260 		work_done += rtl8139_rx(dev, tp, budget);
       
  2261 
       
  2262 	if (work_done < budget) {
       
  2263 		unsigned long flags;
       
  2264 		/*
       
  2265 		 * Order is important since data can get interrupted
       
  2266 		 * again when we think we are done.
       
  2267 		 */
       
  2268 		spin_lock_irqsave(&tp->lock, flags);
       
  2269 		__napi_complete(napi);
       
  2270 		RTL_W16_F(IntrMask, rtl8139_intr_mask);
       
  2271 		spin_unlock_irqrestore(&tp->lock, flags);
       
  2272 	}
       
  2273 	spin_unlock(&tp->rx_lock);
       
  2274 
       
  2275 	return work_done;
       
  2276 }
       
  2277 
       
  2278 void ec_poll(struct net_device *dev)
       
  2279 {
       
  2280 	rtl8139_interrupt(0, dev);
       
  2281 }
       
  2282 
       
  2283 /* The interrupt handler does all of the Rx thread work and cleans up
       
  2284    after the Tx thread. */
       
  2285 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
       
  2286 {
       
  2287 	struct net_device *dev = (struct net_device *) dev_instance;
       
  2288 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2289 	void __iomem *ioaddr = tp->mmio_addr;
       
  2290 	u16 status, ackstat;
       
  2291 	int link_changed = 0; /* avoid bogus "uninit" warning */
       
  2292 	int handled = 0;
       
  2293 
       
  2294 	if (tp->ecdev) {
       
  2295 		status = RTL_R16 (IntrStatus);
       
  2296 	}
       
  2297 	else {
       
  2298 		spin_lock (&tp->lock);
       
  2299 		status = RTL_R16 (IntrStatus);
       
  2300 
       
  2301 		/* shared irq? */
       
  2302 		if (unlikely((status & rtl8139_intr_mask) == 0))
       
  2303 			goto out;
       
  2304 	}
       
  2305 
       
  2306 	handled = 1;
       
  2307 
       
  2308 	/* h/w no longer present (hotplug?) or major error, bail */
       
  2309 	if (unlikely(status == 0xFFFF))
       
  2310 		goto out;
       
  2311 
       
  2312 	if (!tp->ecdev) {
       
  2313 		/* close possible race's with dev_close */
       
  2314 		if (unlikely(!netif_running(dev))) {
       
  2315 			RTL_W16 (IntrMask, 0);
       
  2316 			goto out;
       
  2317 		}
       
  2318 	}
       
  2319 
       
  2320 	/* Acknowledge all of the current interrupt sources ASAP, but
       
  2321 	   an first get an additional status bit from CSCR. */
       
  2322 	if (unlikely(status & RxUnderrun))
       
  2323 		link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
       
  2324 
       
  2325 	ackstat = status & ~(RxAckBits | TxErr);
       
  2326 	if (ackstat)
       
  2327 		RTL_W16 (IntrStatus, ackstat);
       
  2328 
       
  2329 	/* Receive packets are processed by poll routine.
       
  2330 	   If not running start it now. */
       
  2331 	if (status & RxAckBits){
       
  2332 		if (tp->ecdev) {
       
  2333 			/* EtherCAT device: Just receive all frames */
       
  2334 			rtl8139_rx(dev, tp, 100); // FIXME
       
  2335 		} else {
       
  2336 			/* Mark for polling */
       
  2337 			if (napi_schedule_prep(&tp->napi)) {
       
  2338 				RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
       
  2339 				__napi_schedule(&tp->napi);
       
  2340 			}
       
  2341 		}
       
  2342 	}
       
  2343 
       
  2344 	/* Check uncommon events with one test. */
       
  2345 	if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
       
  2346 		rtl8139_weird_interrupt (dev, tp, ioaddr,
       
  2347 					 status, link_changed);
       
  2348 
       
  2349 	if (status & (TxOK | TxErr)) {
       
  2350 		rtl8139_tx_interrupt (dev, tp, ioaddr);
       
  2351 		if (status & TxErr)
       
  2352 			RTL_W16 (IntrStatus, TxErr);
       
  2353 	}
       
  2354 out:
       
  2355 	if (!tp->ecdev) {
       
  2356 		spin_unlock (&tp->lock);
       
  2357 	}
       
  2358 
       
  2359 	pr_debug("%s: exiting interrupt, intr_status=%#4.4x.\n",
       
  2360 		 dev->name, RTL_R16 (IntrStatus));
       
  2361 	return IRQ_RETVAL(handled);
       
  2362 }
       
  2363 
       
  2364 #ifdef CONFIG_NET_POLL_CONTROLLER
       
  2365 /*
       
  2366  * Polling receive - used by netconsole and other diagnostic tools
       
  2367  * to allow network i/o with interrupts disabled.
       
  2368  */
       
  2369 static void rtl8139_poll_controller(struct net_device *dev)
       
  2370 {
       
  2371 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2372 	const int irq = tp->pci_dev->irq;
       
  2373 
       
  2374 	disable_irq(irq);
       
  2375 	rtl8139_interrupt(irq, dev);
       
  2376 	enable_irq(irq);
       
  2377 }
       
  2378 #endif
       
  2379 
       
  2380 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
       
  2381 {
       
  2382 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2383 	void __iomem *ioaddr = tp->mmio_addr;
       
  2384 	struct sockaddr *addr = p;
       
  2385 
       
  2386 	if (!is_valid_ether_addr(addr->sa_data))
       
  2387 		return -EADDRNOTAVAIL;
       
  2388 
       
  2389 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
       
  2390 
       
  2391 	spin_lock_irq(&tp->lock);
       
  2392 
       
  2393 	RTL_W8_F(Cfg9346, Cfg9346_Unlock);
       
  2394 	RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
       
  2395 	RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
       
  2396 	RTL_W8_F(Cfg9346, Cfg9346_Lock);
       
  2397 
       
  2398 	spin_unlock_irq(&tp->lock);
       
  2399 
       
  2400 	return 0;
       
  2401 }
       
  2402 
       
  2403 static int rtl8139_close (struct net_device *dev)
       
  2404 {
       
  2405 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2406 	void __iomem *ioaddr = tp->mmio_addr;
       
  2407 	unsigned long flags = 0;
       
  2408 
       
  2409 	if (!tp->ecdev) {
       
  2410 		netif_stop_queue(dev);
       
  2411 		napi_disable(&tp->napi);
       
  2412 
       
  2413 		netif_dbg(tp, ifdown, dev,
       
  2414 				"Shutting down ethercard, status was 0x%04x\n",
       
  2415 				RTL_R16(IntrStatus));
       
  2416 
       
  2417 		spin_lock_irqsave (&tp->lock, flags);
       
  2418 	}
       
  2419 
       
  2420 	/* Stop the chip's Tx and Rx DMA processes. */
       
  2421 	RTL_W8 (ChipCmd, 0);
       
  2422 
       
  2423 	/* Disable interrupts by clearing the interrupt mask. */
       
  2424 	RTL_W16 (IntrMask, 0);
       
  2425 
       
  2426 	/* Update the error counts. */
       
  2427 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2428 	RTL_W32 (RxMissed, 0);
       
  2429 
       
  2430 	if (!tp->ecdev) {
       
  2431 		spin_unlock_irqrestore (&tp->lock, flags);
       
  2432 
       
  2433 		free_irq(tp->pci_dev->irq, dev);
       
  2434 	}
       
  2435 
       
  2436 	rtl8139_tx_clear (tp);
       
  2437 
       
  2438 	dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
       
  2439 			  tp->rx_ring, tp->rx_ring_dma);
       
  2440 	dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
       
  2441 			  tp->tx_bufs, tp->tx_bufs_dma);
       
  2442 	tp->rx_ring = NULL;
       
  2443 	tp->tx_bufs = NULL;
       
  2444 
       
  2445 	/* Green! Put the chip in low-power mode. */
       
  2446 	RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  2447 
       
  2448 	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
       
  2449 		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
       
  2450 
       
  2451 	return 0;
       
  2452 }
       
  2453 
       
  2454 
       
  2455 /* Get the ethtool Wake-on-LAN settings.  Assumes that wol points to
       
  2456    kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
       
  2457    other threads or interrupts aren't messing with the 8139.  */
       
  2458 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  2459 {
       
  2460 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2461 	void __iomem *ioaddr = tp->mmio_addr;
       
  2462 
       
  2463 	spin_lock_irq(&tp->lock);
       
  2464 	if (rtl_chip_info[tp->chipset].flags & HasLWake) {
       
  2465 		u8 cfg3 = RTL_R8 (Config3);
       
  2466 		u8 cfg5 = RTL_R8 (Config5);
       
  2467 
       
  2468 		wol->supported = WAKE_PHY | WAKE_MAGIC
       
  2469 			| WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
       
  2470 
       
  2471 		wol->wolopts = 0;
       
  2472 		if (cfg3 & Cfg3_LinkUp)
       
  2473 			wol->wolopts |= WAKE_PHY;
       
  2474 		if (cfg3 & Cfg3_Magic)
       
  2475 			wol->wolopts |= WAKE_MAGIC;
       
  2476 		/* (KON)FIXME: See how netdev_set_wol() handles the
       
  2477 		   following constants.  */
       
  2478 		if (cfg5 & Cfg5_UWF)
       
  2479 			wol->wolopts |= WAKE_UCAST;
       
  2480 		if (cfg5 & Cfg5_MWF)
       
  2481 			wol->wolopts |= WAKE_MCAST;
       
  2482 		if (cfg5 & Cfg5_BWF)
       
  2483 			wol->wolopts |= WAKE_BCAST;
       
  2484 	}
       
  2485 	spin_unlock_irq(&tp->lock);
       
  2486 }
       
  2487 
       
  2488 
       
  2489 /* Set the ethtool Wake-on-LAN settings.  Return 0 or -errno.  Assumes
       
  2490    that wol points to kernel memory and other threads or interrupts
       
  2491    aren't messing with the 8139.  */
       
  2492 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
       
  2493 {
       
  2494 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2495 	void __iomem *ioaddr = tp->mmio_addr;
       
  2496 	u32 support;
       
  2497 	u8 cfg3, cfg5;
       
  2498 
       
  2499 	support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
       
  2500 		   ? (WAKE_PHY | WAKE_MAGIC
       
  2501 		      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
       
  2502 		   : 0);
       
  2503 	if (wol->wolopts & ~support)
       
  2504 		return -EINVAL;
       
  2505 
       
  2506 	spin_lock_irq(&tp->lock);
       
  2507 	cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
       
  2508 	if (wol->wolopts & WAKE_PHY)
       
  2509 		cfg3 |= Cfg3_LinkUp;
       
  2510 	if (wol->wolopts & WAKE_MAGIC)
       
  2511 		cfg3 |= Cfg3_Magic;
       
  2512 	RTL_W8 (Cfg9346, Cfg9346_Unlock);
       
  2513 	RTL_W8 (Config3, cfg3);
       
  2514 	RTL_W8 (Cfg9346, Cfg9346_Lock);
       
  2515 
       
  2516 	cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
       
  2517 	/* (KON)FIXME: These are untested.  We may have to set the
       
  2518 	   CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
       
  2519 	   documentation.  */
       
  2520 	if (wol->wolopts & WAKE_UCAST)
       
  2521 		cfg5 |= Cfg5_UWF;
       
  2522 	if (wol->wolopts & WAKE_MCAST)
       
  2523 		cfg5 |= Cfg5_MWF;
       
  2524 	if (wol->wolopts & WAKE_BCAST)
       
  2525 		cfg5 |= Cfg5_BWF;
       
  2526 	RTL_W8 (Config5, cfg5);	/* need not unlock via Cfg9346 */
       
  2527 	spin_unlock_irq(&tp->lock);
       
  2528 
       
  2529 	return 0;
       
  2530 }
       
  2531 
       
  2532 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
       
  2533 {
       
  2534 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2535 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
       
  2536 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
       
  2537 	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
       
  2538 	info->regdump_len = tp->regs_len;
       
  2539 }
       
  2540 
       
  2541 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  2542 {
       
  2543 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2544 	spin_lock_irq(&tp->lock);
       
  2545 	mii_ethtool_gset(&tp->mii, cmd);
       
  2546 	spin_unlock_irq(&tp->lock);
       
  2547 	return 0;
       
  2548 }
       
  2549 
       
  2550 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
       
  2551 {
       
  2552 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2553 	int rc;
       
  2554 	spin_lock_irq(&tp->lock);
       
  2555 	rc = mii_ethtool_sset(&tp->mii, cmd);
       
  2556 	spin_unlock_irq(&tp->lock);
       
  2557 	return rc;
       
  2558 }
       
  2559 
       
  2560 static int rtl8139_nway_reset(struct net_device *dev)
       
  2561 {
       
  2562 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2563 	return mii_nway_restart(&tp->mii);
       
  2564 }
       
  2565 
       
  2566 static u32 rtl8139_get_link(struct net_device *dev)
       
  2567 {
       
  2568 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2569 	return mii_link_ok(&tp->mii);
       
  2570 }
       
  2571 
       
  2572 static u32 rtl8139_get_msglevel(struct net_device *dev)
       
  2573 {
       
  2574 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2575 	return tp->msg_enable;
       
  2576 }
       
  2577 
       
  2578 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
       
  2579 {
       
  2580 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2581 	tp->msg_enable = datum;
       
  2582 }
       
  2583 
       
  2584 static int rtl8139_get_regs_len(struct net_device *dev)
       
  2585 {
       
  2586 	struct rtl8139_private *tp;
       
  2587 	/* TODO: we are too slack to do reg dumping for pio, for now */
       
  2588 	if (use_io)
       
  2589 		return 0;
       
  2590 	tp = netdev_priv(dev);
       
  2591 	return tp->regs_len;
       
  2592 }
       
  2593 
       
  2594 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
       
  2595 {
       
  2596 	struct rtl8139_private *tp;
       
  2597 
       
  2598 	/* TODO: we are too slack to do reg dumping for pio, for now */
       
  2599 	if (use_io)
       
  2600 		return;
       
  2601 	tp = netdev_priv(dev);
       
  2602 
       
  2603 	regs->version = RTL_REGS_VER;
       
  2604 
       
  2605 	spin_lock_irq(&tp->lock);
       
  2606 	memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
       
  2607 	spin_unlock_irq(&tp->lock);
       
  2608 }
       
  2609 
       
  2610 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
       
  2611 {
       
  2612 	switch (sset) {
       
  2613 	case ETH_SS_STATS:
       
  2614 		return RTL_NUM_STATS;
       
  2615 	default:
       
  2616 		return -EOPNOTSUPP;
       
  2617 	}
       
  2618 }
       
  2619 
       
  2620 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
       
  2621 {
       
  2622 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2623 
       
  2624 	data[0] = tp->xstats.early_rx;
       
  2625 	data[1] = tp->xstats.tx_buf_mapped;
       
  2626 	data[2] = tp->xstats.tx_timeouts;
       
  2627 	data[3] = tp->xstats.rx_lost_in_ring;
       
  2628 }
       
  2629 
       
  2630 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
       
  2631 {
       
  2632 	memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
       
  2633 }
       
  2634 
       
  2635 static const struct ethtool_ops rtl8139_ethtool_ops = {
       
  2636 	.get_drvinfo		= rtl8139_get_drvinfo,
       
  2637 	.get_settings		= rtl8139_get_settings,
       
  2638 	.set_settings		= rtl8139_set_settings,
       
  2639 	.get_regs_len		= rtl8139_get_regs_len,
       
  2640 	.get_regs		= rtl8139_get_regs,
       
  2641 	.nway_reset		= rtl8139_nway_reset,
       
  2642 	.get_link		= rtl8139_get_link,
       
  2643 	.get_msglevel		= rtl8139_get_msglevel,
       
  2644 	.set_msglevel		= rtl8139_set_msglevel,
       
  2645 	.get_wol		= rtl8139_get_wol,
       
  2646 	.set_wol		= rtl8139_set_wol,
       
  2647 	.get_strings		= rtl8139_get_strings,
       
  2648 	.get_sset_count		= rtl8139_get_sset_count,
       
  2649 	.get_ethtool_stats	= rtl8139_get_ethtool_stats,
       
  2650 };
       
  2651 
       
  2652 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
       
  2653 {
       
  2654 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2655 	int rc;
       
  2656 
       
  2657 	if (tp->ecdev || !netif_running(dev))
       
  2658 		return -EINVAL;
       
  2659 
       
  2660 	spin_lock_irq(&tp->lock);
       
  2661 	rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
       
  2662 	spin_unlock_irq(&tp->lock);
       
  2663 
       
  2664 	return rc;
       
  2665 }
       
  2666 
       
  2667 
       
  2668 static struct rtnl_link_stats64 *
       
  2669 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
       
  2670 {
       
  2671 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2672 	void __iomem *ioaddr = tp->mmio_addr;
       
  2673 	unsigned long flags;
       
  2674 	unsigned int start;
       
  2675 
       
  2676 	if (tp->ecdev || netif_running(dev)) {
       
  2677 		spin_lock_irqsave (&tp->lock, flags);
       
  2678 		dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2679 		RTL_W32 (RxMissed, 0);
       
  2680 		spin_unlock_irqrestore (&tp->lock, flags);
       
  2681 	}
       
  2682 
       
  2683 	netdev_stats_to_stats64(stats, &dev->stats);
       
  2684 
       
  2685 	do {
       
  2686 		start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
       
  2687 		stats->rx_packets = tp->rx_stats.packets;
       
  2688 		stats->rx_bytes = tp->rx_stats.bytes;
       
  2689 	} while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
       
  2690 
       
  2691 	do {
       
  2692 		start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
       
  2693 		stats->tx_packets = tp->tx_stats.packets;
       
  2694 		stats->tx_bytes = tp->tx_stats.bytes;
       
  2695 	} while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
       
  2696 
       
  2697 	return stats;
       
  2698 }
       
  2699 
       
  2700 /* Set or clear the multicast filter for this adaptor.
       
  2701    This routine is not state sensitive and need not be SMP locked. */
       
  2702 
       
  2703 static void __set_rx_mode (struct net_device *dev)
       
  2704 {
       
  2705 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2706 	void __iomem *ioaddr = tp->mmio_addr;
       
  2707 	u32 mc_filter[2];	/* Multicast hash filter */
       
  2708 	int rx_mode;
       
  2709 	u32 tmp;
       
  2710 
       
  2711 	netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
       
  2712 		   dev->flags, RTL_R32(RxConfig));
       
  2713 
       
  2714 	/* Note: do not reorder, GCC is clever about common statements. */
       
  2715 	if (dev->flags & IFF_PROMISC) {
       
  2716 		rx_mode =
       
  2717 		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
       
  2718 		    AcceptAllPhys;
       
  2719 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  2720 	} else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
       
  2721 		   (dev->flags & IFF_ALLMULTI)) {
       
  2722 		/* Too many to filter perfectly -- accept all multicasts. */
       
  2723 		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
       
  2724 		mc_filter[1] = mc_filter[0] = 0xffffffff;
       
  2725 	} else {
       
  2726 		struct netdev_hw_addr *ha;
       
  2727 		rx_mode = AcceptBroadcast | AcceptMyPhys;
       
  2728 		mc_filter[1] = mc_filter[0] = 0;
       
  2729 		netdev_for_each_mc_addr(ha, dev) {
       
  2730 			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
       
  2731 
       
  2732 			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
       
  2733 			rx_mode |= AcceptMulticast;
       
  2734 		}
       
  2735 	}
       
  2736 
       
  2737 	if (dev->features & NETIF_F_RXALL)
       
  2738 		rx_mode |= (AcceptErr | AcceptRunt);
       
  2739 
       
  2740 	/* We can safely update without stopping the chip. */
       
  2741 	tmp = rtl8139_rx_config | rx_mode;
       
  2742 	if (tp->rx_config != tmp) {
       
  2743 		RTL_W32_F (RxConfig, tmp);
       
  2744 		tp->rx_config = tmp;
       
  2745 	}
       
  2746 	RTL_W32_F (MAR0 + 0, mc_filter[0]);
       
  2747 	RTL_W32_F (MAR0 + 4, mc_filter[1]);
       
  2748 }
       
  2749 
       
  2750 static void rtl8139_set_rx_mode (struct net_device *dev)
       
  2751 {
       
  2752 	unsigned long flags;
       
  2753 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2754 
       
  2755 	spin_lock_irqsave (&tp->lock, flags);
       
  2756 	__set_rx_mode(dev);
       
  2757 	spin_unlock_irqrestore (&tp->lock, flags);
       
  2758 }
       
  2759 
       
  2760 #ifdef CONFIG_PM
       
  2761 
       
  2762 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
       
  2763 {
       
  2764 	struct net_device *dev = pci_get_drvdata (pdev);
       
  2765 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2766 	void __iomem *ioaddr = tp->mmio_addr;
       
  2767 	unsigned long flags;
       
  2768 
       
  2769 	pci_save_state (pdev);
       
  2770 
       
  2771 	if (tp->ecdev || !netif_running (dev))
       
  2772 		return 0;
       
  2773 
       
  2774 	netif_device_detach (dev);
       
  2775 
       
  2776 	spin_lock_irqsave (&tp->lock, flags);
       
  2777 
       
  2778 	/* Disable interrupts, stop Tx and Rx. */
       
  2779 	RTL_W16 (IntrMask, 0);
       
  2780 	RTL_W8 (ChipCmd, 0);
       
  2781 
       
  2782 	/* Update the error counts. */
       
  2783 	dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
       
  2784 	RTL_W32 (RxMissed, 0);
       
  2785 
       
  2786 	spin_unlock_irqrestore (&tp->lock, flags);
       
  2787 
       
  2788 	pci_set_power_state (pdev, PCI_D3hot);
       
  2789 
       
  2790 	return 0;
       
  2791 }
       
  2792 
       
  2793 
       
  2794 static int rtl8139_resume (struct pci_dev *pdev)
       
  2795 {
       
  2796 	struct net_device *dev = pci_get_drvdata (pdev);
       
  2797 	struct rtl8139_private *tp = netdev_priv(dev);
       
  2798 
       
  2799 	pci_restore_state (pdev);
       
  2800 	if (tp->ecdev || !netif_running (dev))
       
  2801 		return 0;
       
  2802 	pci_set_power_state (pdev, PCI_D0);
       
  2803 	rtl8139_init_ring (dev);
       
  2804 	rtl8139_hw_start (dev);
       
  2805 	netif_device_attach (dev);
       
  2806 	return 0;
       
  2807 }
       
  2808 
       
  2809 #endif /* CONFIG_PM */
       
  2810 
       
  2811 
       
  2812 static struct pci_driver rtl8139_pci_driver = {
       
  2813 	.name		= DRV_NAME,
       
  2814 	.id_table	= rtl8139_pci_tbl,
       
  2815 	.probe		= rtl8139_init_one,
       
  2816 	.remove		= __devexit_p(rtl8139_remove_one),
       
  2817 #ifdef CONFIG_PM
       
  2818 	.suspend	= rtl8139_suspend,
       
  2819 	.resume		= rtl8139_resume,
       
  2820 #endif /* CONFIG_PM */
       
  2821 };
       
  2822 
       
  2823 
       
  2824 static int __init rtl8139_init_module (void)
       
  2825 {
       
  2826 	/* when we're a module, we always print a version message,
       
  2827 	 * even if no 8139 board is found.
       
  2828 	 */
       
  2829 #ifdef MODULE
       
  2830 	pr_info(RTL8139_DRIVER_NAME "\n");
       
  2831 #endif
       
  2832 
       
  2833 	return pci_register_driver(&rtl8139_pci_driver);
       
  2834 }
       
  2835 
       
  2836 
       
  2837 static void __exit rtl8139_cleanup_module (void)
       
  2838 {
       
  2839 	pci_unregister_driver (&rtl8139_pci_driver);
       
  2840 }
       
  2841 
       
  2842 
       
  2843 module_init(rtl8139_init_module);
       
  2844 module_exit(rtl8139_cleanup_module);