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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 */ |
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10 |
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11 #include <linux/module.h> |
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12 #include <linux/moduleparam.h> |
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13 #include <linux/pci.h> |
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14 #include <linux/netdevice.h> |
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15 #include <linux/etherdevice.h> |
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16 #include <linux/delay.h> |
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17 #include <linux/ethtool.h> |
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18 #include <linux/mii.h> |
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19 #include <linux/if_vlan.h> |
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20 #include <linux/crc32.h> |
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21 #include <linux/in.h> |
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22 #include <linux/ip.h> |
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23 #include <linux/tcp.h> |
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24 #include <linux/init.h> |
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25 #include <linux/dma-mapping.h> |
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26 #include <linux/pm_runtime.h> |
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27 #include <linux/pci-aspm.h> |
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28 |
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29 #include <asm/system.h> |
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30 #include <asm/io.h> |
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31 #include <asm/irq.h> |
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32 |
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33 #define RTL8169_VERSION "2.3LK-NAPI" |
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34 #define MODULENAME "r8169" |
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35 #define PFX MODULENAME ": " |
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36 |
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37 #ifdef RTL8169_DEBUG |
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38 #define assert(expr) \ |
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39 if (!(expr)) { \ |
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40 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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41 #expr,__FILE__,__func__,__LINE__); \ |
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42 } |
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43 #define dprintk(fmt, args...) \ |
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44 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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45 #else |
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46 #define assert(expr) do {} while (0) |
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47 #define dprintk(fmt, args...) do {} while (0) |
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48 #endif /* RTL8169_DEBUG */ |
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49 |
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50 #define R8169_MSG_DEFAULT \ |
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51 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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52 |
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53 #define TX_BUFFS_AVAIL(tp) \ |
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54 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
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55 |
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56 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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57 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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58 static const int multicast_filter_limit = 32; |
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59 |
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60 /* MAC address length */ |
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61 #define MAC_ADDR_LEN 6 |
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62 |
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63 #define MAX_READ_REQUEST_SHIFT 12 |
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64 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
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65 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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66 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
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67 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
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68 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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70 |
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71 #define R8169_REGS_SIZE 256 |
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72 #define R8169_NAPI_WEIGHT 64 |
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73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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74 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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75 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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76 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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77 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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78 |
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79 #define RTL8169_TX_TIMEOUT (6*HZ) |
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80 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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81 |
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82 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
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83 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
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84 #define RTL_EEPROM_SIG_ADDR 0x0000 |
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85 |
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86 /* write/read MMIO register */ |
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87 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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88 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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89 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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90 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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91 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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92 #define RTL_R32(reg) readl (ioaddr + (reg)) |
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93 |
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94 enum mac_version { |
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95 RTL_GIGA_MAC_NONE = 0x00, |
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96 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
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97 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
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98 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
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99 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
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100 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
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101 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
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102 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
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103 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e |
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104 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e |
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105 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e |
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106 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
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107 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
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108 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb |
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109 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? |
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110 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? |
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111 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec |
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112 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
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113 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
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114 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
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115 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
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116 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
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117 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
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118 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
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119 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
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120 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D |
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121 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D |
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122 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP |
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123 }; |
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124 |
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125 #define _R(NAME,MAC,MASK) \ |
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126 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
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127 |
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128 static const struct { |
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129 const char *name; |
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130 u8 mac_version; |
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131 u32 RxConfigMask; /* Clears the bits supported by this chip */ |
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132 } rtl_chip_info[] = { |
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133 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
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134 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S |
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135 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S |
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136 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB |
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137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd |
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138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
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139 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
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140 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E |
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141 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E |
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142 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E |
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143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
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144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
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145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
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146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
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147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
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148 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E |
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149 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E |
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150 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E |
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151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
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152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
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153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
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154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
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155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
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156 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
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157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E |
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158 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E |
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159 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E |
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160 }; |
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161 #undef _R |
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162 |
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163 enum cfg_version { |
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164 RTL_CFG_0 = 0x00, |
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165 RTL_CFG_1, |
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166 RTL_CFG_2 |
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167 }; |
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168 |
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169 static void rtl_hw_start_8169(struct net_device *); |
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170 static void rtl_hw_start_8168(struct net_device *); |
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171 static void rtl_hw_start_8101(struct net_device *); |
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172 |
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173 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
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174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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179 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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180 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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181 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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182 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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183 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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184 { 0x0001, 0x8168, |
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185 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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186 {0,}, |
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187 }; |
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188 |
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189 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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190 |
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191 static int rx_buf_sz = 16383; |
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192 static int use_dac; |
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193 static struct { |
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194 u32 msg_enable; |
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195 } debug = { -1 }; |
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196 |
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197 enum rtl_registers { |
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198 MAC0 = 0, /* Ethernet hardware address. */ |
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199 MAC4 = 4, |
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200 MAR0 = 8, /* Multicast filter. */ |
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201 CounterAddrLow = 0x10, |
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202 CounterAddrHigh = 0x14, |
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203 TxDescStartAddrLow = 0x20, |
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204 TxDescStartAddrHigh = 0x24, |
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205 TxHDescStartAddrLow = 0x28, |
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206 TxHDescStartAddrHigh = 0x2c, |
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207 FLASH = 0x30, |
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208 ERSR = 0x36, |
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209 ChipCmd = 0x37, |
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210 TxPoll = 0x38, |
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211 IntrMask = 0x3c, |
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212 IntrStatus = 0x3e, |
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213 TxConfig = 0x40, |
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214 RxConfig = 0x44, |
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215 RxMissed = 0x4c, |
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216 Cfg9346 = 0x50, |
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217 Config0 = 0x51, |
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218 Config1 = 0x52, |
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219 Config2 = 0x53, |
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220 Config3 = 0x54, |
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221 Config4 = 0x55, |
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222 Config5 = 0x56, |
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223 MultiIntr = 0x5c, |
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224 PHYAR = 0x60, |
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225 PHYstatus = 0x6c, |
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226 RxMaxSize = 0xda, |
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227 CPlusCmd = 0xe0, |
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228 IntrMitigate = 0xe2, |
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229 RxDescAddrLow = 0xe4, |
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230 RxDescAddrHigh = 0xe8, |
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231 EarlyTxThres = 0xec, |
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232 FuncEvent = 0xf0, |
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233 FuncEventMask = 0xf4, |
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234 FuncPresetState = 0xf8, |
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235 FuncForceEvent = 0xfc, |
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236 }; |
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237 |
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238 enum rtl8110_registers { |
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239 TBICSR = 0x64, |
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240 TBI_ANAR = 0x68, |
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241 TBI_LPAR = 0x6a, |
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242 }; |
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243 |
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244 enum rtl8168_8101_registers { |
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245 CSIDR = 0x64, |
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246 CSIAR = 0x68, |
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247 #define CSIAR_FLAG 0x80000000 |
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248 #define CSIAR_WRITE_CMD 0x80000000 |
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249 #define CSIAR_BYTE_ENABLE 0x0f |
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250 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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251 #define CSIAR_ADDR_MASK 0x0fff |
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252 |
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253 EPHYAR = 0x80, |
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254 #define EPHYAR_FLAG 0x80000000 |
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255 #define EPHYAR_WRITE_CMD 0x80000000 |
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256 #define EPHYAR_REG_MASK 0x1f |
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257 #define EPHYAR_REG_SHIFT 16 |
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258 #define EPHYAR_DATA_MASK 0xffff |
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259 DBG_REG = 0xd1, |
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260 #define FIX_NAK_1 (1 << 4) |
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261 #define FIX_NAK_2 (1 << 3) |
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262 EFUSEAR = 0xdc, |
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263 #define EFUSEAR_FLAG 0x80000000 |
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264 #define EFUSEAR_WRITE_CMD 0x80000000 |
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265 #define EFUSEAR_READ_CMD 0x00000000 |
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266 #define EFUSEAR_REG_MASK 0x03ff |
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267 #define EFUSEAR_REG_SHIFT 8 |
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268 #define EFUSEAR_DATA_MASK 0xff |
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269 }; |
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270 |
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271 enum rtl_register_content { |
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272 /* InterruptStatusBits */ |
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273 SYSErr = 0x8000, |
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274 PCSTimeout = 0x4000, |
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275 SWInt = 0x0100, |
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276 TxDescUnavail = 0x0080, |
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277 RxFIFOOver = 0x0040, |
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278 LinkChg = 0x0020, |
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279 RxOverflow = 0x0010, |
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280 TxErr = 0x0008, |
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281 TxOK = 0x0004, |
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282 RxErr = 0x0002, |
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283 RxOK = 0x0001, |
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284 |
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285 /* RxStatusDesc */ |
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286 RxFOVF = (1 << 23), |
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287 RxRWT = (1 << 22), |
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288 RxRES = (1 << 21), |
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289 RxRUNT = (1 << 20), |
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290 RxCRC = (1 << 19), |
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291 |
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292 /* ChipCmdBits */ |
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293 CmdReset = 0x10, |
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294 CmdRxEnb = 0x08, |
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295 CmdTxEnb = 0x04, |
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296 RxBufEmpty = 0x01, |
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297 |
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298 /* TXPoll register p.5 */ |
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299 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
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300 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
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301 FSWInt = 0x01, /* Forced software interrupt */ |
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302 |
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303 /* Cfg9346Bits */ |
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304 Cfg9346_Lock = 0x00, |
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305 Cfg9346_Unlock = 0xc0, |
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306 |
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307 /* rx_mode_bits */ |
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308 AcceptErr = 0x20, |
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309 AcceptRunt = 0x10, |
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310 AcceptBroadcast = 0x08, |
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311 AcceptMulticast = 0x04, |
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312 AcceptMyPhys = 0x02, |
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313 AcceptAllPhys = 0x01, |
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314 |
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315 /* RxConfigBits */ |
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316 RxCfgFIFOShift = 13, |
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317 RxCfgDMAShift = 8, |
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318 |
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319 /* TxConfigBits */ |
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320 TxInterFrameGapShift = 24, |
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321 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
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322 |
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323 /* Config1 register p.24 */ |
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324 LEDS1 = (1 << 7), |
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325 LEDS0 = (1 << 6), |
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326 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
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327 Speed_down = (1 << 4), |
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328 MEMMAP = (1 << 3), |
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329 IOMAP = (1 << 2), |
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330 VPD = (1 << 1), |
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331 PMEnable = (1 << 0), /* Power Management Enable */ |
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332 |
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333 /* Config2 register p. 25 */ |
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334 PCI_Clock_66MHz = 0x01, |
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335 PCI_Clock_33MHz = 0x00, |
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336 |
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337 /* Config3 register p.25 */ |
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338 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
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339 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
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340 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
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341 |
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342 /* Config5 register p.27 */ |
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343 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
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344 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
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345 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
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346 LanWake = (1 << 1), /* LanWake enable/disable */ |
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347 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
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348 |
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349 /* TBICSR p.28 */ |
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350 TBIReset = 0x80000000, |
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351 TBILoopback = 0x40000000, |
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352 TBINwEnable = 0x20000000, |
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353 TBINwRestart = 0x10000000, |
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354 TBILinkOk = 0x02000000, |
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355 TBINwComplete = 0x01000000, |
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356 |
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357 /* CPlusCmd p.31 */ |
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358 EnableBist = (1 << 15), // 8168 8101 |
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359 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
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360 Normal_mode = (1 << 13), // unused |
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361 Force_half_dup = (1 << 12), // 8168 8101 |
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362 Force_rxflow_en = (1 << 11), // 8168 8101 |
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363 Force_txflow_en = (1 << 10), // 8168 8101 |
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364 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
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365 ASF = (1 << 8), // 8168 8101 |
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366 PktCntrDisable = (1 << 7), // 8168 8101 |
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367 Mac_dbgo_sel = 0x001c, // 8168 |
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368 RxVlan = (1 << 6), |
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369 RxChkSum = (1 << 5), |
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370 PCIDAC = (1 << 4), |
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371 PCIMulRW = (1 << 3), |
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372 INTT_0 = 0x0000, // 8168 |
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373 INTT_1 = 0x0001, // 8168 |
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374 INTT_2 = 0x0002, // 8168 |
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375 INTT_3 = 0x0003, // 8168 |
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376 |
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377 /* rtl8169_PHYstatus */ |
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378 TBI_Enable = 0x80, |
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379 TxFlowCtrl = 0x40, |
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380 RxFlowCtrl = 0x20, |
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381 _1000bpsF = 0x10, |
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382 _100bps = 0x08, |
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383 _10bps = 0x04, |
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384 LinkStatus = 0x02, |
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385 FullDup = 0x01, |
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386 |
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387 /* _TBICSRBit */ |
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388 TBILinkOK = 0x02000000, |
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389 |
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390 /* DumpCounterCommand */ |
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391 CounterDump = 0x8, |
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392 }; |
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393 |
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394 enum desc_status_bit { |
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395 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
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396 RingEnd = (1 << 30), /* End of descriptor ring */ |
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397 FirstFrag = (1 << 29), /* First segment of a packet */ |
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398 LastFrag = (1 << 28), /* Final segment of a packet */ |
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399 |
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400 /* Tx private */ |
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401 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
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402 MSSShift = 16, /* MSS value position */ |
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403 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
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404 IPCS = (1 << 18), /* Calculate IP checksum */ |
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405 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
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406 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
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407 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
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408 |
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409 /* Rx private */ |
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410 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
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411 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
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412 |
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413 #define RxProtoUDP (PID1) |
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414 #define RxProtoTCP (PID0) |
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415 #define RxProtoIP (PID1 | PID0) |
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416 #define RxProtoMask RxProtoIP |
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417 |
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418 IPFail = (1 << 16), /* IP checksum failed */ |
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419 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
420 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
421 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
422 }; |
|
423 |
|
424 #define RsvdMask 0x3fffc000 |
|
425 |
|
426 struct TxDesc { |
|
427 __le32 opts1; |
|
428 __le32 opts2; |
|
429 __le64 addr; |
|
430 }; |
|
431 |
|
432 struct RxDesc { |
|
433 __le32 opts1; |
|
434 __le32 opts2; |
|
435 __le64 addr; |
|
436 }; |
|
437 |
|
438 struct ring_info { |
|
439 struct sk_buff *skb; |
|
440 u32 len; |
|
441 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
442 }; |
|
443 |
|
444 enum features { |
|
445 RTL_FEATURE_WOL = (1 << 0), |
|
446 RTL_FEATURE_MSI = (1 << 1), |
|
447 RTL_FEATURE_GMII = (1 << 2), |
|
448 }; |
|
449 |
|
450 struct rtl8169_counters { |
|
451 __le64 tx_packets; |
|
452 __le64 rx_packets; |
|
453 __le64 tx_errors; |
|
454 __le32 rx_errors; |
|
455 __le16 rx_missed; |
|
456 __le16 align_errors; |
|
457 __le32 tx_one_collision; |
|
458 __le32 tx_multi_collision; |
|
459 __le64 rx_unicast; |
|
460 __le64 rx_broadcast; |
|
461 __le32 rx_multicast; |
|
462 __le16 tx_aborted; |
|
463 __le16 tx_underun; |
|
464 }; |
|
465 |
|
466 struct rtl8169_private { |
|
467 void __iomem *mmio_addr; /* memory map physical address */ |
|
468 struct pci_dev *pci_dev; /* Index of PCI device */ |
|
469 struct net_device *dev; |
|
470 struct napi_struct napi; |
|
471 spinlock_t lock; /* spin lock flag */ |
|
472 u32 msg_enable; |
|
473 int chipset; |
|
474 int mac_version; |
|
475 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
476 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
477 u32 dirty_rx; |
|
478 u32 dirty_tx; |
|
479 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
480 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
481 dma_addr_t TxPhyAddr; |
|
482 dma_addr_t RxPhyAddr; |
|
483 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
484 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
485 struct timer_list timer; |
|
486 u16 cp_cmd; |
|
487 u16 intr_event; |
|
488 u16 napi_event; |
|
489 u16 intr_mask; |
|
490 int phy_1000_ctrl_reg; |
|
491 #ifdef CONFIG_R8169_VLAN |
|
492 struct vlan_group *vlgrp; |
|
493 #endif |
|
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
|
495 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
496 void (*phy_reset_enable)(void __iomem *); |
|
497 void (*hw_start)(struct net_device *); |
|
498 unsigned int (*phy_reset_pending)(void __iomem *); |
|
499 unsigned int (*link_ok)(void __iomem *); |
|
500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
501 int pcie_cap; |
|
502 struct delayed_work task; |
|
503 unsigned features; |
|
504 |
|
505 struct mii_if_info mii; |
|
506 struct rtl8169_counters counters; |
|
507 u32 saved_wolopts; |
|
508 }; |
|
509 |
|
510 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
511 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
|
512 module_param(use_dac, int, 0); |
|
513 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
514 module_param_named(debug, debug.msg_enable, int, 0); |
|
515 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
516 MODULE_LICENSE("GPL"); |
|
517 MODULE_VERSION(RTL8169_VERSION); |
|
518 |
|
519 static int rtl8169_open(struct net_device *dev); |
|
520 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
521 struct net_device *dev); |
|
522 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
523 static int rtl8169_init_ring(struct net_device *dev); |
|
524 static void rtl_hw_start(struct net_device *dev); |
|
525 static int rtl8169_close(struct net_device *dev); |
|
526 static void rtl_set_rx_mode(struct net_device *dev); |
|
527 static void rtl8169_tx_timeout(struct net_device *dev); |
|
528 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
529 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
530 void __iomem *, u32 budget); |
|
531 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
532 static void rtl8169_down(struct net_device *dev); |
|
533 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
534 static int rtl8169_poll(struct napi_struct *napi, int budget); |
|
535 |
|
536 static const unsigned int rtl8169_rx_config = |
|
537 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
538 |
|
539 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
540 { |
|
541 int i; |
|
542 |
|
543 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
544 |
|
545 for (i = 20; i > 0; i--) { |
|
546 /* |
|
547 * Check if the RTL8169 has completed writing to the specified |
|
548 * MII register. |
|
549 */ |
|
550 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
551 break; |
|
552 udelay(25); |
|
553 } |
|
554 /* |
|
555 * According to hardware specs a 20us delay is required after write |
|
556 * complete indication, but before sending next command. |
|
557 */ |
|
558 udelay(20); |
|
559 } |
|
560 |
|
561 static int mdio_read(void __iomem *ioaddr, int reg_addr) |
|
562 { |
|
563 int i, value = -1; |
|
564 |
|
565 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
566 |
|
567 for (i = 20; i > 0; i--) { |
|
568 /* |
|
569 * Check if the RTL8169 has completed retrieving data from |
|
570 * the specified MII register. |
|
571 */ |
|
572 if (RTL_R32(PHYAR) & 0x80000000) { |
|
573 value = RTL_R32(PHYAR) & 0xffff; |
|
574 break; |
|
575 } |
|
576 udelay(25); |
|
577 } |
|
578 /* |
|
579 * According to hardware specs a 20us delay is required after read |
|
580 * complete indication, but before sending next command. |
|
581 */ |
|
582 udelay(20); |
|
583 |
|
584 return value; |
|
585 } |
|
586 |
|
587 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
|
588 { |
|
589 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); |
|
590 } |
|
591 |
|
592 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m) |
|
593 { |
|
594 int val; |
|
595 |
|
596 val = mdio_read(ioaddr, reg_addr); |
|
597 mdio_write(ioaddr, reg_addr, (val | p) & ~m); |
|
598 } |
|
599 |
|
600 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
601 int val) |
|
602 { |
|
603 struct rtl8169_private *tp = netdev_priv(dev); |
|
604 void __iomem *ioaddr = tp->mmio_addr; |
|
605 |
|
606 mdio_write(ioaddr, location, val); |
|
607 } |
|
608 |
|
609 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
610 { |
|
611 struct rtl8169_private *tp = netdev_priv(dev); |
|
612 void __iomem *ioaddr = tp->mmio_addr; |
|
613 |
|
614 return mdio_read(ioaddr, location); |
|
615 } |
|
616 |
|
617 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
618 { |
|
619 unsigned int i; |
|
620 |
|
621 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
622 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
623 |
|
624 for (i = 0; i < 100; i++) { |
|
625 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
626 break; |
|
627 udelay(10); |
|
628 } |
|
629 } |
|
630 |
|
631 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
632 { |
|
633 u16 value = 0xffff; |
|
634 unsigned int i; |
|
635 |
|
636 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
637 |
|
638 for (i = 0; i < 100; i++) { |
|
639 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
640 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
641 break; |
|
642 } |
|
643 udelay(10); |
|
644 } |
|
645 |
|
646 return value; |
|
647 } |
|
648 |
|
649 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
650 { |
|
651 unsigned int i; |
|
652 |
|
653 RTL_W32(CSIDR, value); |
|
654 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
655 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
656 |
|
657 for (i = 0; i < 100; i++) { |
|
658 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
659 break; |
|
660 udelay(10); |
|
661 } |
|
662 } |
|
663 |
|
664 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
665 { |
|
666 u32 value = ~0x00; |
|
667 unsigned int i; |
|
668 |
|
669 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
670 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
671 |
|
672 for (i = 0; i < 100; i++) { |
|
673 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
674 value = RTL_R32(CSIDR); |
|
675 break; |
|
676 } |
|
677 udelay(10); |
|
678 } |
|
679 |
|
680 return value; |
|
681 } |
|
682 |
|
683 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
|
684 { |
|
685 u8 value = 0xff; |
|
686 unsigned int i; |
|
687 |
|
688 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
689 |
|
690 for (i = 0; i < 300; i++) { |
|
691 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { |
|
692 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; |
|
693 break; |
|
694 } |
|
695 udelay(100); |
|
696 } |
|
697 |
|
698 return value; |
|
699 } |
|
700 |
|
701 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
702 { |
|
703 RTL_W16(IntrMask, 0x0000); |
|
704 |
|
705 RTL_W16(IntrStatus, 0xffff); |
|
706 } |
|
707 |
|
708 static void rtl8169_asic_down(void __iomem *ioaddr) |
|
709 { |
|
710 RTL_W8(ChipCmd, 0x00); |
|
711 rtl8169_irq_mask_and_ack(ioaddr); |
|
712 RTL_R16(CPlusCmd); |
|
713 } |
|
714 |
|
715 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
716 { |
|
717 return RTL_R32(TBICSR) & TBIReset; |
|
718 } |
|
719 |
|
720 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
721 { |
|
722 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
723 } |
|
724 |
|
725 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
726 { |
|
727 return RTL_R32(TBICSR) & TBILinkOk; |
|
728 } |
|
729 |
|
730 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
731 { |
|
732 return RTL_R8(PHYstatus) & LinkStatus; |
|
733 } |
|
734 |
|
735 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
736 { |
|
737 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
738 } |
|
739 |
|
740 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
741 { |
|
742 unsigned int val; |
|
743 |
|
744 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
745 mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
746 } |
|
747 |
|
748 static void __rtl8169_check_link_status(struct net_device *dev, |
|
749 struct rtl8169_private *tp, |
|
750 void __iomem *ioaddr, |
|
751 bool pm) |
|
752 { |
|
753 unsigned long flags; |
|
754 |
|
755 spin_lock_irqsave(&tp->lock, flags); |
|
756 if (tp->link_ok(ioaddr)) { |
|
757 /* This is to cancel a scheduled suspend if there's one. */ |
|
758 if (pm) |
|
759 pm_request_resume(&tp->pci_dev->dev); |
|
760 netif_carrier_on(dev); |
|
761 if (net_ratelimit()) |
|
762 netif_info(tp, ifup, dev, "link up\n"); |
|
763 } else { |
|
764 netif_carrier_off(dev); |
|
765 netif_info(tp, ifdown, dev, "link down\n"); |
|
766 if (pm) |
|
767 pm_schedule_suspend(&tp->pci_dev->dev, 100); |
|
768 } |
|
769 spin_unlock_irqrestore(&tp->lock, flags); |
|
770 } |
|
771 |
|
772 static void rtl8169_check_link_status(struct net_device *dev, |
|
773 struct rtl8169_private *tp, |
|
774 void __iomem *ioaddr) |
|
775 { |
|
776 __rtl8169_check_link_status(dev, tp, ioaddr, false); |
|
777 } |
|
778 |
|
779 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
780 |
|
781 static u32 __rtl8169_get_wol(struct rtl8169_private *tp) |
|
782 { |
|
783 void __iomem *ioaddr = tp->mmio_addr; |
|
784 u8 options; |
|
785 u32 wolopts = 0; |
|
786 |
|
787 options = RTL_R8(Config1); |
|
788 if (!(options & PMEnable)) |
|
789 return 0; |
|
790 |
|
791 options = RTL_R8(Config3); |
|
792 if (options & LinkUp) |
|
793 wolopts |= WAKE_PHY; |
|
794 if (options & MagicPacket) |
|
795 wolopts |= WAKE_MAGIC; |
|
796 |
|
797 options = RTL_R8(Config5); |
|
798 if (options & UWF) |
|
799 wolopts |= WAKE_UCAST; |
|
800 if (options & BWF) |
|
801 wolopts |= WAKE_BCAST; |
|
802 if (options & MWF) |
|
803 wolopts |= WAKE_MCAST; |
|
804 |
|
805 return wolopts; |
|
806 } |
|
807 |
|
808 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
809 { |
|
810 struct rtl8169_private *tp = netdev_priv(dev); |
|
811 |
|
812 spin_lock_irq(&tp->lock); |
|
813 |
|
814 wol->supported = WAKE_ANY; |
|
815 wol->wolopts = __rtl8169_get_wol(tp); |
|
816 |
|
817 spin_unlock_irq(&tp->lock); |
|
818 } |
|
819 |
|
820 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) |
|
821 { |
|
822 void __iomem *ioaddr = tp->mmio_addr; |
|
823 unsigned int i; |
|
824 static const struct { |
|
825 u32 opt; |
|
826 u16 reg; |
|
827 u8 mask; |
|
828 } cfg[] = { |
|
829 { WAKE_ANY, Config1, PMEnable }, |
|
830 { WAKE_PHY, Config3, LinkUp }, |
|
831 { WAKE_MAGIC, Config3, MagicPacket }, |
|
832 { WAKE_UCAST, Config5, UWF }, |
|
833 { WAKE_BCAST, Config5, BWF }, |
|
834 { WAKE_MCAST, Config5, MWF }, |
|
835 { WAKE_ANY, Config5, LanWake } |
|
836 }; |
|
837 |
|
838 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
839 |
|
840 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
841 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
842 if (wolopts & cfg[i].opt) |
|
843 options |= cfg[i].mask; |
|
844 RTL_W8(cfg[i].reg, options); |
|
845 } |
|
846 |
|
847 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
848 } |
|
849 |
|
850 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
851 { |
|
852 struct rtl8169_private *tp = netdev_priv(dev); |
|
853 |
|
854 spin_lock_irq(&tp->lock); |
|
855 |
|
856 if (wol->wolopts) |
|
857 tp->features |= RTL_FEATURE_WOL; |
|
858 else |
|
859 tp->features &= ~RTL_FEATURE_WOL; |
|
860 __rtl8169_set_wol(tp, wol->wolopts); |
|
861 spin_unlock_irq(&tp->lock); |
|
862 |
|
863 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
864 |
|
865 return 0; |
|
866 } |
|
867 |
|
868 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
869 struct ethtool_drvinfo *info) |
|
870 { |
|
871 struct rtl8169_private *tp = netdev_priv(dev); |
|
872 |
|
873 strcpy(info->driver, MODULENAME); |
|
874 strcpy(info->version, RTL8169_VERSION); |
|
875 strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
876 } |
|
877 |
|
878 static int rtl8169_get_regs_len(struct net_device *dev) |
|
879 { |
|
880 return R8169_REGS_SIZE; |
|
881 } |
|
882 |
|
883 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
884 u8 autoneg, u16 speed, u8 duplex) |
|
885 { |
|
886 struct rtl8169_private *tp = netdev_priv(dev); |
|
887 void __iomem *ioaddr = tp->mmio_addr; |
|
888 int ret = 0; |
|
889 u32 reg; |
|
890 |
|
891 reg = RTL_R32(TBICSR); |
|
892 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
893 (duplex == DUPLEX_FULL)) { |
|
894 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
895 } else if (autoneg == AUTONEG_ENABLE) |
|
896 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
897 else { |
|
898 netif_warn(tp, link, dev, |
|
899 "incorrect speed setting refused in TBI mode\n"); |
|
900 ret = -EOPNOTSUPP; |
|
901 } |
|
902 |
|
903 return ret; |
|
904 } |
|
905 |
|
906 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
907 u8 autoneg, u16 speed, u8 duplex) |
|
908 { |
|
909 struct rtl8169_private *tp = netdev_priv(dev); |
|
910 void __iomem *ioaddr = tp->mmio_addr; |
|
911 int giga_ctrl, bmcr; |
|
912 |
|
913 if (autoneg == AUTONEG_ENABLE) { |
|
914 int auto_nego; |
|
915 |
|
916 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
917 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
918 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
919 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
920 |
|
921 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
922 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
923 |
|
924 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
925 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && |
|
926 (tp->mac_version != RTL_GIGA_MAC_VER_08) && |
|
927 (tp->mac_version != RTL_GIGA_MAC_VER_09) && |
|
928 (tp->mac_version != RTL_GIGA_MAC_VER_10) && |
|
929 (tp->mac_version != RTL_GIGA_MAC_VER_13) && |
|
930 (tp->mac_version != RTL_GIGA_MAC_VER_14) && |
|
931 (tp->mac_version != RTL_GIGA_MAC_VER_15) && |
|
932 (tp->mac_version != RTL_GIGA_MAC_VER_16)) { |
|
933 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
934 } else { |
|
935 netif_info(tp, link, dev, |
|
936 "PHY does not support 1000Mbps\n"); |
|
937 } |
|
938 |
|
939 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
940 |
|
941 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
942 (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
943 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { |
|
944 /* |
|
945 * Wake up the PHY. |
|
946 * Vendor specific (0x1f) and reserved (0x0e) MII |
|
947 * registers. |
|
948 */ |
|
949 mdio_write(ioaddr, 0x1f, 0x0000); |
|
950 mdio_write(ioaddr, 0x0e, 0x0000); |
|
951 } |
|
952 |
|
953 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
954 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
955 } else { |
|
956 giga_ctrl = 0; |
|
957 |
|
958 if (speed == SPEED_10) |
|
959 bmcr = 0; |
|
960 else if (speed == SPEED_100) |
|
961 bmcr = BMCR_SPEED100; |
|
962 else |
|
963 return -EINVAL; |
|
964 |
|
965 if (duplex == DUPLEX_FULL) |
|
966 bmcr |= BMCR_FULLDPLX; |
|
967 |
|
968 mdio_write(ioaddr, 0x1f, 0x0000); |
|
969 } |
|
970 |
|
971 tp->phy_1000_ctrl_reg = giga_ctrl; |
|
972 |
|
973 mdio_write(ioaddr, MII_BMCR, bmcr); |
|
974 |
|
975 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
976 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
977 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
978 mdio_write(ioaddr, 0x17, 0x2138); |
|
979 mdio_write(ioaddr, 0x0e, 0x0260); |
|
980 } else { |
|
981 mdio_write(ioaddr, 0x17, 0x2108); |
|
982 mdio_write(ioaddr, 0x0e, 0x0000); |
|
983 } |
|
984 } |
|
985 |
|
986 return 0; |
|
987 } |
|
988 |
|
989 static int rtl8169_set_speed(struct net_device *dev, |
|
990 u8 autoneg, u16 speed, u8 duplex) |
|
991 { |
|
992 struct rtl8169_private *tp = netdev_priv(dev); |
|
993 int ret; |
|
994 |
|
995 ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
996 |
|
997 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
998 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
999 |
|
1000 return ret; |
|
1001 } |
|
1002 |
|
1003 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1004 { |
|
1005 struct rtl8169_private *tp = netdev_priv(dev); |
|
1006 unsigned long flags; |
|
1007 int ret; |
|
1008 |
|
1009 spin_lock_irqsave(&tp->lock, flags); |
|
1010 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
1011 spin_unlock_irqrestore(&tp->lock, flags); |
|
1012 |
|
1013 return ret; |
|
1014 } |
|
1015 |
|
1016 static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
1017 { |
|
1018 struct rtl8169_private *tp = netdev_priv(dev); |
|
1019 |
|
1020 return tp->cp_cmd & RxChkSum; |
|
1021 } |
|
1022 |
|
1023 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
1024 { |
|
1025 struct rtl8169_private *tp = netdev_priv(dev); |
|
1026 void __iomem *ioaddr = tp->mmio_addr; |
|
1027 unsigned long flags; |
|
1028 |
|
1029 spin_lock_irqsave(&tp->lock, flags); |
|
1030 |
|
1031 if (data) |
|
1032 tp->cp_cmd |= RxChkSum; |
|
1033 else |
|
1034 tp->cp_cmd &= ~RxChkSum; |
|
1035 |
|
1036 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1037 RTL_R16(CPlusCmd); |
|
1038 |
|
1039 spin_unlock_irqrestore(&tp->lock, flags); |
|
1040 |
|
1041 return 0; |
|
1042 } |
|
1043 |
|
1044 #ifdef CONFIG_R8169_VLAN |
|
1045 |
|
1046 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1047 struct sk_buff *skb) |
|
1048 { |
|
1049 return (vlan_tx_tag_present(skb)) ? |
|
1050 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1051 } |
|
1052 |
|
1053 static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
1054 struct vlan_group *grp) |
|
1055 { |
|
1056 struct rtl8169_private *tp = netdev_priv(dev); |
|
1057 void __iomem *ioaddr = tp->mmio_addr; |
|
1058 unsigned long flags; |
|
1059 |
|
1060 spin_lock_irqsave(&tp->lock, flags); |
|
1061 tp->vlgrp = grp; |
|
1062 /* |
|
1063 * Do not disable RxVlan on 8110SCd. |
|
1064 */ |
|
1065 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05)) |
|
1066 tp->cp_cmd |= RxVlan; |
|
1067 else |
|
1068 tp->cp_cmd &= ~RxVlan; |
|
1069 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1070 RTL_R16(CPlusCmd); |
|
1071 spin_unlock_irqrestore(&tp->lock, flags); |
|
1072 } |
|
1073 |
|
1074 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1075 struct sk_buff *skb, int polling) |
|
1076 { |
|
1077 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1078 struct vlan_group *vlgrp = tp->vlgrp; |
|
1079 int ret; |
|
1080 |
|
1081 if (vlgrp && (opts2 & RxVlanTag)) { |
|
1082 u16 vtag = swab16(opts2 & 0xffff); |
|
1083 |
|
1084 if (likely(polling)) |
|
1085 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb); |
|
1086 else |
|
1087 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling); |
|
1088 ret = 0; |
|
1089 } else |
|
1090 ret = -1; |
|
1091 desc->opts2 = 0; |
|
1092 return ret; |
|
1093 } |
|
1094 |
|
1095 #else /* !CONFIG_R8169_VLAN */ |
|
1096 |
|
1097 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1098 struct sk_buff *skb) |
|
1099 { |
|
1100 return 0; |
|
1101 } |
|
1102 |
|
1103 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1104 struct sk_buff *skb, int polling) |
|
1105 { |
|
1106 return -1; |
|
1107 } |
|
1108 |
|
1109 #endif |
|
1110 |
|
1111 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1112 { |
|
1113 struct rtl8169_private *tp = netdev_priv(dev); |
|
1114 void __iomem *ioaddr = tp->mmio_addr; |
|
1115 u32 status; |
|
1116 |
|
1117 cmd->supported = |
|
1118 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1119 cmd->port = PORT_FIBRE; |
|
1120 cmd->transceiver = XCVR_INTERNAL; |
|
1121 |
|
1122 status = RTL_R32(TBICSR); |
|
1123 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1124 cmd->autoneg = !!(status & TBINwEnable); |
|
1125 |
|
1126 cmd->speed = SPEED_1000; |
|
1127 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1128 |
|
1129 return 0; |
|
1130 } |
|
1131 |
|
1132 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1133 { |
|
1134 struct rtl8169_private *tp = netdev_priv(dev); |
|
1135 |
|
1136 return mii_ethtool_gset(&tp->mii, cmd); |
|
1137 } |
|
1138 |
|
1139 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1140 { |
|
1141 struct rtl8169_private *tp = netdev_priv(dev); |
|
1142 unsigned long flags; |
|
1143 int rc; |
|
1144 |
|
1145 spin_lock_irqsave(&tp->lock, flags); |
|
1146 |
|
1147 rc = tp->get_settings(dev, cmd); |
|
1148 |
|
1149 spin_unlock_irqrestore(&tp->lock, flags); |
|
1150 return rc; |
|
1151 } |
|
1152 |
|
1153 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1154 void *p) |
|
1155 { |
|
1156 struct rtl8169_private *tp = netdev_priv(dev); |
|
1157 unsigned long flags; |
|
1158 |
|
1159 if (regs->len > R8169_REGS_SIZE) |
|
1160 regs->len = R8169_REGS_SIZE; |
|
1161 |
|
1162 spin_lock_irqsave(&tp->lock, flags); |
|
1163 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1164 spin_unlock_irqrestore(&tp->lock, flags); |
|
1165 } |
|
1166 |
|
1167 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1168 { |
|
1169 struct rtl8169_private *tp = netdev_priv(dev); |
|
1170 |
|
1171 return tp->msg_enable; |
|
1172 } |
|
1173 |
|
1174 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1175 { |
|
1176 struct rtl8169_private *tp = netdev_priv(dev); |
|
1177 |
|
1178 tp->msg_enable = value; |
|
1179 } |
|
1180 |
|
1181 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1182 "tx_packets", |
|
1183 "rx_packets", |
|
1184 "tx_errors", |
|
1185 "rx_errors", |
|
1186 "rx_missed", |
|
1187 "align_errors", |
|
1188 "tx_single_collisions", |
|
1189 "tx_multi_collisions", |
|
1190 "unicast", |
|
1191 "broadcast", |
|
1192 "multicast", |
|
1193 "tx_aborted", |
|
1194 "tx_underrun", |
|
1195 }; |
|
1196 |
|
1197 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1198 { |
|
1199 switch (sset) { |
|
1200 case ETH_SS_STATS: |
|
1201 return ARRAY_SIZE(rtl8169_gstrings); |
|
1202 default: |
|
1203 return -EOPNOTSUPP; |
|
1204 } |
|
1205 } |
|
1206 |
|
1207 static void rtl8169_update_counters(struct net_device *dev) |
|
1208 { |
|
1209 struct rtl8169_private *tp = netdev_priv(dev); |
|
1210 void __iomem *ioaddr = tp->mmio_addr; |
|
1211 struct rtl8169_counters *counters; |
|
1212 dma_addr_t paddr; |
|
1213 u32 cmd; |
|
1214 int wait = 1000; |
|
1215 struct device *d = &tp->pci_dev->dev; |
|
1216 |
|
1217 /* |
|
1218 * Some chips are unable to dump tally counters when the receiver |
|
1219 * is disabled. |
|
1220 */ |
|
1221 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1222 return; |
|
1223 |
|
1224 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
|
1225 if (!counters) |
|
1226 return; |
|
1227 |
|
1228 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1229 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1230 RTL_W32(CounterAddrLow, cmd); |
|
1231 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1232 |
|
1233 while (wait--) { |
|
1234 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1235 /* copy updated counters */ |
|
1236 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1237 break; |
|
1238 } |
|
1239 udelay(10); |
|
1240 } |
|
1241 |
|
1242 RTL_W32(CounterAddrLow, 0); |
|
1243 RTL_W32(CounterAddrHigh, 0); |
|
1244 |
|
1245 dma_free_coherent(d, sizeof(*counters), counters, paddr); |
|
1246 } |
|
1247 |
|
1248 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1249 struct ethtool_stats *stats, u64 *data) |
|
1250 { |
|
1251 struct rtl8169_private *tp = netdev_priv(dev); |
|
1252 |
|
1253 ASSERT_RTNL(); |
|
1254 |
|
1255 rtl8169_update_counters(dev); |
|
1256 |
|
1257 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1258 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1259 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1260 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1261 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1262 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1263 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1264 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1265 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1266 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1267 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1268 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1269 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1270 } |
|
1271 |
|
1272 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1273 { |
|
1274 switch(stringset) { |
|
1275 case ETH_SS_STATS: |
|
1276 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1277 break; |
|
1278 } |
|
1279 } |
|
1280 |
|
1281 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1282 .get_drvinfo = rtl8169_get_drvinfo, |
|
1283 .get_regs_len = rtl8169_get_regs_len, |
|
1284 .get_link = ethtool_op_get_link, |
|
1285 .get_settings = rtl8169_get_settings, |
|
1286 .set_settings = rtl8169_set_settings, |
|
1287 .get_msglevel = rtl8169_get_msglevel, |
|
1288 .set_msglevel = rtl8169_set_msglevel, |
|
1289 .get_rx_csum = rtl8169_get_rx_csum, |
|
1290 .set_rx_csum = rtl8169_set_rx_csum, |
|
1291 .set_tx_csum = ethtool_op_set_tx_csum, |
|
1292 .set_sg = ethtool_op_set_sg, |
|
1293 .set_tso = ethtool_op_set_tso, |
|
1294 .get_regs = rtl8169_get_regs, |
|
1295 .get_wol = rtl8169_get_wol, |
|
1296 .set_wol = rtl8169_set_wol, |
|
1297 .get_strings = rtl8169_get_strings, |
|
1298 .get_sset_count = rtl8169_get_sset_count, |
|
1299 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1300 }; |
|
1301 |
|
1302 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1303 void __iomem *ioaddr) |
|
1304 { |
|
1305 /* |
|
1306 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1307 * but they can be identified more specifically through the test below |
|
1308 * if needed: |
|
1309 * |
|
1310 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1311 * |
|
1312 * Same thing for the 8101Eb and the 8101Ec: |
|
1313 * |
|
1314 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1315 */ |
|
1316 static const struct { |
|
1317 u32 mask; |
|
1318 u32 val; |
|
1319 int mac_version; |
|
1320 } mac_info[] = { |
|
1321 /* 8168D family. */ |
|
1322 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
1323 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
1324 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
1325 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
1326 |
|
1327 /* 8168C family. */ |
|
1328 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
|
1329 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1330 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1331 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1332 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1333 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1334 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1335 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1336 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1337 |
|
1338 /* 8168B family. */ |
|
1339 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1340 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1341 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1342 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1343 |
|
1344 /* 8101 family. */ |
|
1345 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1346 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1347 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1348 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1349 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1350 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1351 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1352 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1353 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1354 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1355 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1356 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1357 /* FIXME: where did these entries come from ? -- FR */ |
|
1358 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1359 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1360 |
|
1361 /* 8110 family. */ |
|
1362 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1363 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1364 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1365 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1366 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1367 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1368 |
|
1369 /* Catch-all */ |
|
1370 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1371 }, *p = mac_info; |
|
1372 u32 reg; |
|
1373 |
|
1374 reg = RTL_R32(TxConfig); |
|
1375 while ((reg & p->mask) != p->val) |
|
1376 p++; |
|
1377 tp->mac_version = p->mac_version; |
|
1378 } |
|
1379 |
|
1380 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1381 { |
|
1382 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1383 } |
|
1384 |
|
1385 struct phy_reg { |
|
1386 u16 reg; |
|
1387 u16 val; |
|
1388 }; |
|
1389 |
|
1390 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len) |
|
1391 { |
|
1392 while (len-- > 0) { |
|
1393 mdio_write(ioaddr, regs->reg, regs->val); |
|
1394 regs++; |
|
1395 } |
|
1396 } |
|
1397 |
|
1398 static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
|
1399 { |
|
1400 static const struct phy_reg phy_reg_init[] = { |
|
1401 { 0x1f, 0x0001 }, |
|
1402 { 0x06, 0x006e }, |
|
1403 { 0x08, 0x0708 }, |
|
1404 { 0x15, 0x4000 }, |
|
1405 { 0x18, 0x65c7 }, |
|
1406 |
|
1407 { 0x1f, 0x0001 }, |
|
1408 { 0x03, 0x00a1 }, |
|
1409 { 0x02, 0x0008 }, |
|
1410 { 0x01, 0x0120 }, |
|
1411 { 0x00, 0x1000 }, |
|
1412 { 0x04, 0x0800 }, |
|
1413 { 0x04, 0x0000 }, |
|
1414 |
|
1415 { 0x03, 0xff41 }, |
|
1416 { 0x02, 0xdf60 }, |
|
1417 { 0x01, 0x0140 }, |
|
1418 { 0x00, 0x0077 }, |
|
1419 { 0x04, 0x7800 }, |
|
1420 { 0x04, 0x7000 }, |
|
1421 |
|
1422 { 0x03, 0x802f }, |
|
1423 { 0x02, 0x4f02 }, |
|
1424 { 0x01, 0x0409 }, |
|
1425 { 0x00, 0xf0f9 }, |
|
1426 { 0x04, 0x9800 }, |
|
1427 { 0x04, 0x9000 }, |
|
1428 |
|
1429 { 0x03, 0xdf01 }, |
|
1430 { 0x02, 0xdf20 }, |
|
1431 { 0x01, 0xff95 }, |
|
1432 { 0x00, 0xba00 }, |
|
1433 { 0x04, 0xa800 }, |
|
1434 { 0x04, 0xa000 }, |
|
1435 |
|
1436 { 0x03, 0xff41 }, |
|
1437 { 0x02, 0xdf20 }, |
|
1438 { 0x01, 0x0140 }, |
|
1439 { 0x00, 0x00bb }, |
|
1440 { 0x04, 0xb800 }, |
|
1441 { 0x04, 0xb000 }, |
|
1442 |
|
1443 { 0x03, 0xdf41 }, |
|
1444 { 0x02, 0xdc60 }, |
|
1445 { 0x01, 0x6340 }, |
|
1446 { 0x00, 0x007d }, |
|
1447 { 0x04, 0xd800 }, |
|
1448 { 0x04, 0xd000 }, |
|
1449 |
|
1450 { 0x03, 0xdf01 }, |
|
1451 { 0x02, 0xdf20 }, |
|
1452 { 0x01, 0x100a }, |
|
1453 { 0x00, 0xa0ff }, |
|
1454 { 0x04, 0xf800 }, |
|
1455 { 0x04, 0xf000 }, |
|
1456 |
|
1457 { 0x1f, 0x0000 }, |
|
1458 { 0x0b, 0x0000 }, |
|
1459 { 0x00, 0x9200 } |
|
1460 }; |
|
1461 |
|
1462 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1463 } |
|
1464 |
|
1465 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
|
1466 { |
|
1467 static const struct phy_reg phy_reg_init[] = { |
|
1468 { 0x1f, 0x0002 }, |
|
1469 { 0x01, 0x90d0 }, |
|
1470 { 0x1f, 0x0000 } |
|
1471 }; |
|
1472 |
|
1473 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1474 } |
|
1475 |
|
1476 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, |
|
1477 void __iomem *ioaddr) |
|
1478 { |
|
1479 struct pci_dev *pdev = tp->pci_dev; |
|
1480 u16 vendor_id, device_id; |
|
1481 |
|
1482 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); |
|
1483 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); |
|
1484 |
|
1485 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) |
|
1486 return; |
|
1487 |
|
1488 mdio_write(ioaddr, 0x1f, 0x0001); |
|
1489 mdio_write(ioaddr, 0x10, 0xf01b); |
|
1490 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1491 } |
|
1492 |
|
1493 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, |
|
1494 void __iomem *ioaddr) |
|
1495 { |
|
1496 static const struct phy_reg phy_reg_init[] = { |
|
1497 { 0x1f, 0x0001 }, |
|
1498 { 0x04, 0x0000 }, |
|
1499 { 0x03, 0x00a1 }, |
|
1500 { 0x02, 0x0008 }, |
|
1501 { 0x01, 0x0120 }, |
|
1502 { 0x00, 0x1000 }, |
|
1503 { 0x04, 0x0800 }, |
|
1504 { 0x04, 0x9000 }, |
|
1505 { 0x03, 0x802f }, |
|
1506 { 0x02, 0x4f02 }, |
|
1507 { 0x01, 0x0409 }, |
|
1508 { 0x00, 0xf099 }, |
|
1509 { 0x04, 0x9800 }, |
|
1510 { 0x04, 0xa000 }, |
|
1511 { 0x03, 0xdf01 }, |
|
1512 { 0x02, 0xdf20 }, |
|
1513 { 0x01, 0xff95 }, |
|
1514 { 0x00, 0xba00 }, |
|
1515 { 0x04, 0xa800 }, |
|
1516 { 0x04, 0xf000 }, |
|
1517 { 0x03, 0xdf01 }, |
|
1518 { 0x02, 0xdf20 }, |
|
1519 { 0x01, 0x101a }, |
|
1520 { 0x00, 0xa0ff }, |
|
1521 { 0x04, 0xf800 }, |
|
1522 { 0x04, 0x0000 }, |
|
1523 { 0x1f, 0x0000 }, |
|
1524 |
|
1525 { 0x1f, 0x0001 }, |
|
1526 { 0x10, 0xf41b }, |
|
1527 { 0x14, 0xfb54 }, |
|
1528 { 0x18, 0xf5c7 }, |
|
1529 { 0x1f, 0x0000 }, |
|
1530 |
|
1531 { 0x1f, 0x0001 }, |
|
1532 { 0x17, 0x0cc0 }, |
|
1533 { 0x1f, 0x0000 } |
|
1534 }; |
|
1535 |
|
1536 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1537 |
|
1538 rtl8169scd_hw_phy_config_quirk(tp, ioaddr); |
|
1539 } |
|
1540 |
|
1541 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) |
|
1542 { |
|
1543 static const struct phy_reg phy_reg_init[] = { |
|
1544 { 0x1f, 0x0001 }, |
|
1545 { 0x04, 0x0000 }, |
|
1546 { 0x03, 0x00a1 }, |
|
1547 { 0x02, 0x0008 }, |
|
1548 { 0x01, 0x0120 }, |
|
1549 { 0x00, 0x1000 }, |
|
1550 { 0x04, 0x0800 }, |
|
1551 { 0x04, 0x9000 }, |
|
1552 { 0x03, 0x802f }, |
|
1553 { 0x02, 0x4f02 }, |
|
1554 { 0x01, 0x0409 }, |
|
1555 { 0x00, 0xf099 }, |
|
1556 { 0x04, 0x9800 }, |
|
1557 { 0x04, 0xa000 }, |
|
1558 { 0x03, 0xdf01 }, |
|
1559 { 0x02, 0xdf20 }, |
|
1560 { 0x01, 0xff95 }, |
|
1561 { 0x00, 0xba00 }, |
|
1562 { 0x04, 0xa800 }, |
|
1563 { 0x04, 0xf000 }, |
|
1564 { 0x03, 0xdf01 }, |
|
1565 { 0x02, 0xdf20 }, |
|
1566 { 0x01, 0x101a }, |
|
1567 { 0x00, 0xa0ff }, |
|
1568 { 0x04, 0xf800 }, |
|
1569 { 0x04, 0x0000 }, |
|
1570 { 0x1f, 0x0000 }, |
|
1571 |
|
1572 { 0x1f, 0x0001 }, |
|
1573 { 0x0b, 0x8480 }, |
|
1574 { 0x1f, 0x0000 }, |
|
1575 |
|
1576 { 0x1f, 0x0001 }, |
|
1577 { 0x18, 0x67c7 }, |
|
1578 { 0x04, 0x2000 }, |
|
1579 { 0x03, 0x002f }, |
|
1580 { 0x02, 0x4360 }, |
|
1581 { 0x01, 0x0109 }, |
|
1582 { 0x00, 0x3022 }, |
|
1583 { 0x04, 0x2800 }, |
|
1584 { 0x1f, 0x0000 }, |
|
1585 |
|
1586 { 0x1f, 0x0001 }, |
|
1587 { 0x17, 0x0cc0 }, |
|
1588 { 0x1f, 0x0000 } |
|
1589 }; |
|
1590 |
|
1591 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1592 } |
|
1593 |
|
1594 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
|
1595 { |
|
1596 static const struct phy_reg phy_reg_init[] = { |
|
1597 { 0x10, 0xf41b }, |
|
1598 { 0x1f, 0x0000 } |
|
1599 }; |
|
1600 |
|
1601 mdio_write(ioaddr, 0x1f, 0x0001); |
|
1602 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1603 |
|
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1605 } |
|
1606 |
|
1607 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) |
|
1608 { |
|
1609 static const struct phy_reg phy_reg_init[] = { |
|
1610 { 0x1f, 0x0001 }, |
|
1611 { 0x10, 0xf41b }, |
|
1612 { 0x1f, 0x0000 } |
|
1613 }; |
|
1614 |
|
1615 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1616 } |
|
1617 |
|
1618 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
|
1619 { |
|
1620 static const struct phy_reg phy_reg_init[] = { |
|
1621 { 0x1f, 0x0000 }, |
|
1622 { 0x1d, 0x0f00 }, |
|
1623 { 0x1f, 0x0002 }, |
|
1624 { 0x0c, 0x1ec8 }, |
|
1625 { 0x1f, 0x0000 } |
|
1626 }; |
|
1627 |
|
1628 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1629 } |
|
1630 |
|
1631 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
|
1632 { |
|
1633 static const struct phy_reg phy_reg_init[] = { |
|
1634 { 0x1f, 0x0001 }, |
|
1635 { 0x1d, 0x3d98 }, |
|
1636 { 0x1f, 0x0000 } |
|
1637 }; |
|
1638 |
|
1639 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1640 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1641 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1642 |
|
1643 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1644 } |
|
1645 |
|
1646 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
|
1647 { |
|
1648 static const struct phy_reg phy_reg_init[] = { |
|
1649 { 0x1f, 0x0001 }, |
|
1650 { 0x12, 0x2300 }, |
|
1651 { 0x1f, 0x0002 }, |
|
1652 { 0x00, 0x88d4 }, |
|
1653 { 0x01, 0x82b1 }, |
|
1654 { 0x03, 0x7002 }, |
|
1655 { 0x08, 0x9e30 }, |
|
1656 { 0x09, 0x01f0 }, |
|
1657 { 0x0a, 0x5500 }, |
|
1658 { 0x0c, 0x00c8 }, |
|
1659 { 0x1f, 0x0003 }, |
|
1660 { 0x12, 0xc096 }, |
|
1661 { 0x16, 0x000a }, |
|
1662 { 0x1f, 0x0000 }, |
|
1663 { 0x1f, 0x0000 }, |
|
1664 { 0x09, 0x2000 }, |
|
1665 { 0x09, 0x0000 } |
|
1666 }; |
|
1667 |
|
1668 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1669 |
|
1670 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1671 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1672 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1673 } |
|
1674 |
|
1675 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
|
1676 { |
|
1677 static const struct phy_reg phy_reg_init[] = { |
|
1678 { 0x1f, 0x0001 }, |
|
1679 { 0x12, 0x2300 }, |
|
1680 { 0x03, 0x802f }, |
|
1681 { 0x02, 0x4f02 }, |
|
1682 { 0x01, 0x0409 }, |
|
1683 { 0x00, 0xf099 }, |
|
1684 { 0x04, 0x9800 }, |
|
1685 { 0x04, 0x9000 }, |
|
1686 { 0x1d, 0x3d98 }, |
|
1687 { 0x1f, 0x0002 }, |
|
1688 { 0x0c, 0x7eb8 }, |
|
1689 { 0x06, 0x0761 }, |
|
1690 { 0x1f, 0x0003 }, |
|
1691 { 0x16, 0x0f0a }, |
|
1692 { 0x1f, 0x0000 } |
|
1693 }; |
|
1694 |
|
1695 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1696 |
|
1697 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1698 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1699 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1700 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1701 } |
|
1702 |
|
1703 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
|
1704 { |
|
1705 static const struct phy_reg phy_reg_init[] = { |
|
1706 { 0x1f, 0x0001 }, |
|
1707 { 0x12, 0x2300 }, |
|
1708 { 0x1d, 0x3d98 }, |
|
1709 { 0x1f, 0x0002 }, |
|
1710 { 0x0c, 0x7eb8 }, |
|
1711 { 0x06, 0x5461 }, |
|
1712 { 0x1f, 0x0003 }, |
|
1713 { 0x16, 0x0f0a }, |
|
1714 { 0x1f, 0x0000 } |
|
1715 }; |
|
1716 |
|
1717 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1718 |
|
1719 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1720 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1721 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1722 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1723 } |
|
1724 |
|
1725 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
|
1726 { |
|
1727 rtl8168c_3_hw_phy_config(ioaddr); |
|
1728 } |
|
1729 |
|
1730 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) |
|
1731 { |
|
1732 static const struct phy_reg phy_reg_init_0[] = { |
|
1733 { 0x1f, 0x0001 }, |
|
1734 { 0x06, 0x4064 }, |
|
1735 { 0x07, 0x2863 }, |
|
1736 { 0x08, 0x059c }, |
|
1737 { 0x09, 0x26b4 }, |
|
1738 { 0x0a, 0x6a19 }, |
|
1739 { 0x0b, 0xdcc8 }, |
|
1740 { 0x10, 0xf06d }, |
|
1741 { 0x14, 0x7f68 }, |
|
1742 { 0x18, 0x7fd9 }, |
|
1743 { 0x1c, 0xf0ff }, |
|
1744 { 0x1d, 0x3d9c }, |
|
1745 { 0x1f, 0x0003 }, |
|
1746 { 0x12, 0xf49f }, |
|
1747 { 0x13, 0x070b }, |
|
1748 { 0x1a, 0x05ad }, |
|
1749 { 0x14, 0x94c0 } |
|
1750 }; |
|
1751 static const struct phy_reg phy_reg_init_1[] = { |
|
1752 { 0x1f, 0x0002 }, |
|
1753 { 0x06, 0x5561 }, |
|
1754 { 0x1f, 0x0005 }, |
|
1755 { 0x05, 0x8332 }, |
|
1756 { 0x06, 0x5561 } |
|
1757 }; |
|
1758 static const struct phy_reg phy_reg_init_2[] = { |
|
1759 { 0x1f, 0x0005 }, |
|
1760 { 0x05, 0xffc2 }, |
|
1761 { 0x1f, 0x0005 }, |
|
1762 { 0x05, 0x8000 }, |
|
1763 { 0x06, 0xf8f9 }, |
|
1764 { 0x06, 0xfaef }, |
|
1765 { 0x06, 0x59ee }, |
|
1766 { 0x06, 0xf8ea }, |
|
1767 { 0x06, 0x00ee }, |
|
1768 { 0x06, 0xf8eb }, |
|
1769 { 0x06, 0x00e0 }, |
|
1770 { 0x06, 0xf87c }, |
|
1771 { 0x06, 0xe1f8 }, |
|
1772 { 0x06, 0x7d59 }, |
|
1773 { 0x06, 0x0fef }, |
|
1774 { 0x06, 0x0139 }, |
|
1775 { 0x06, 0x029e }, |
|
1776 { 0x06, 0x06ef }, |
|
1777 { 0x06, 0x1039 }, |
|
1778 { 0x06, 0x089f }, |
|
1779 { 0x06, 0x2aee }, |
|
1780 { 0x06, 0xf8ea }, |
|
1781 { 0x06, 0x00ee }, |
|
1782 { 0x06, 0xf8eb }, |
|
1783 { 0x06, 0x01e0 }, |
|
1784 { 0x06, 0xf87c }, |
|
1785 { 0x06, 0xe1f8 }, |
|
1786 { 0x06, 0x7d58 }, |
|
1787 { 0x06, 0x409e }, |
|
1788 { 0x06, 0x0f39 }, |
|
1789 { 0x06, 0x46aa }, |
|
1790 { 0x06, 0x0bbf }, |
|
1791 { 0x06, 0x8290 }, |
|
1792 { 0x06, 0xd682 }, |
|
1793 { 0x06, 0x9802 }, |
|
1794 { 0x06, 0x014f }, |
|
1795 { 0x06, 0xae09 }, |
|
1796 { 0x06, 0xbf82 }, |
|
1797 { 0x06, 0x98d6 }, |
|
1798 { 0x06, 0x82a0 }, |
|
1799 { 0x06, 0x0201 }, |
|
1800 { 0x06, 0x4fef }, |
|
1801 { 0x06, 0x95fe }, |
|
1802 { 0x06, 0xfdfc }, |
|
1803 { 0x06, 0x05f8 }, |
|
1804 { 0x06, 0xf9fa }, |
|
1805 { 0x06, 0xeef8 }, |
|
1806 { 0x06, 0xea00 }, |
|
1807 { 0x06, 0xeef8 }, |
|
1808 { 0x06, 0xeb00 }, |
|
1809 { 0x06, 0xe2f8 }, |
|
1810 { 0x06, 0x7ce3 }, |
|
1811 { 0x06, 0xf87d }, |
|
1812 { 0x06, 0xa511 }, |
|
1813 { 0x06, 0x1112 }, |
|
1814 { 0x06, 0xd240 }, |
|
1815 { 0x06, 0xd644 }, |
|
1816 { 0x06, 0x4402 }, |
|
1817 { 0x06, 0x8217 }, |
|
1818 { 0x06, 0xd2a0 }, |
|
1819 { 0x06, 0xd6aa }, |
|
1820 { 0x06, 0xaa02 }, |
|
1821 { 0x06, 0x8217 }, |
|
1822 { 0x06, 0xae0f }, |
|
1823 { 0x06, 0xa544 }, |
|
1824 { 0x06, 0x4402 }, |
|
1825 { 0x06, 0xae4d }, |
|
1826 { 0x06, 0xa5aa }, |
|
1827 { 0x06, 0xaa02 }, |
|
1828 { 0x06, 0xae47 }, |
|
1829 { 0x06, 0xaf82 }, |
|
1830 { 0x06, 0x13ee }, |
|
1831 { 0x06, 0x834e }, |
|
1832 { 0x06, 0x00ee }, |
|
1833 { 0x06, 0x834d }, |
|
1834 { 0x06, 0x0fee }, |
|
1835 { 0x06, 0x834c }, |
|
1836 { 0x06, 0x0fee }, |
|
1837 { 0x06, 0x834f }, |
|
1838 { 0x06, 0x00ee }, |
|
1839 { 0x06, 0x8351 }, |
|
1840 { 0x06, 0x00ee }, |
|
1841 { 0x06, 0x834a }, |
|
1842 { 0x06, 0xffee }, |
|
1843 { 0x06, 0x834b }, |
|
1844 { 0x06, 0xffe0 }, |
|
1845 { 0x06, 0x8330 }, |
|
1846 { 0x06, 0xe183 }, |
|
1847 { 0x06, 0x3158 }, |
|
1848 { 0x06, 0xfee4 }, |
|
1849 { 0x06, 0xf88a }, |
|
1850 { 0x06, 0xe5f8 }, |
|
1851 { 0x06, 0x8be0 }, |
|
1852 { 0x06, 0x8332 }, |
|
1853 { 0x06, 0xe183 }, |
|
1854 { 0x06, 0x3359 }, |
|
1855 { 0x06, 0x0fe2 }, |
|
1856 { 0x06, 0x834d }, |
|
1857 { 0x06, 0x0c24 }, |
|
1858 { 0x06, 0x5af0 }, |
|
1859 { 0x06, 0x1e12 }, |
|
1860 { 0x06, 0xe4f8 }, |
|
1861 { 0x06, 0x8ce5 }, |
|
1862 { 0x06, 0xf88d }, |
|
1863 { 0x06, 0xaf82 }, |
|
1864 { 0x06, 0x13e0 }, |
|
1865 { 0x06, 0x834f }, |
|
1866 { 0x06, 0x10e4 }, |
|
1867 { 0x06, 0x834f }, |
|
1868 { 0x06, 0xe083 }, |
|
1869 { 0x06, 0x4e78 }, |
|
1870 { 0x06, 0x009f }, |
|
1871 { 0x06, 0x0ae0 }, |
|
1872 { 0x06, 0x834f }, |
|
1873 { 0x06, 0xa010 }, |
|
1874 { 0x06, 0xa5ee }, |
|
1875 { 0x06, 0x834e }, |
|
1876 { 0x06, 0x01e0 }, |
|
1877 { 0x06, 0x834e }, |
|
1878 { 0x06, 0x7805 }, |
|
1879 { 0x06, 0x9e9a }, |
|
1880 { 0x06, 0xe083 }, |
|
1881 { 0x06, 0x4e78 }, |
|
1882 { 0x06, 0x049e }, |
|
1883 { 0x06, 0x10e0 }, |
|
1884 { 0x06, 0x834e }, |
|
1885 { 0x06, 0x7803 }, |
|
1886 { 0x06, 0x9e0f }, |
|
1887 { 0x06, 0xe083 }, |
|
1888 { 0x06, 0x4e78 }, |
|
1889 { 0x06, 0x019e }, |
|
1890 { 0x06, 0x05ae }, |
|
1891 { 0x06, 0x0caf }, |
|
1892 { 0x06, 0x81f8 }, |
|
1893 { 0x06, 0xaf81 }, |
|
1894 { 0x06, 0xa3af }, |
|
1895 { 0x06, 0x81dc }, |
|
1896 { 0x06, 0xaf82 }, |
|
1897 { 0x06, 0x13ee }, |
|
1898 { 0x06, 0x8348 }, |
|
1899 { 0x06, 0x00ee }, |
|
1900 { 0x06, 0x8349 }, |
|
1901 { 0x06, 0x00e0 }, |
|
1902 { 0x06, 0x8351 }, |
|
1903 { 0x06, 0x10e4 }, |
|
1904 { 0x06, 0x8351 }, |
|
1905 { 0x06, 0x5801 }, |
|
1906 { 0x06, 0x9fea }, |
|
1907 { 0x06, 0xd000 }, |
|
1908 { 0x06, 0xd180 }, |
|
1909 { 0x06, 0x1f66 }, |
|
1910 { 0x06, 0xe2f8 }, |
|
1911 { 0x06, 0xeae3 }, |
|
1912 { 0x06, 0xf8eb }, |
|
1913 { 0x06, 0x5af8 }, |
|
1914 { 0x06, 0x1e20 }, |
|
1915 { 0x06, 0xe6f8 }, |
|
1916 { 0x06, 0xeae5 }, |
|
1917 { 0x06, 0xf8eb }, |
|
1918 { 0x06, 0xd302 }, |
|
1919 { 0x06, 0xb3fe }, |
|
1920 { 0x06, 0xe2f8 }, |
|
1921 { 0x06, 0x7cef }, |
|
1922 { 0x06, 0x325b }, |
|
1923 { 0x06, 0x80e3 }, |
|
1924 { 0x06, 0xf87d }, |
|
1925 { 0x06, 0x9e03 }, |
|
1926 { 0x06, 0x7dff }, |
|
1927 { 0x06, 0xff0d }, |
|
1928 { 0x06, 0x581c }, |
|
1929 { 0x06, 0x551a }, |
|
1930 { 0x06, 0x6511 }, |
|
1931 { 0x06, 0xa190 }, |
|
1932 { 0x06, 0xd3e2 }, |
|
1933 { 0x06, 0x8348 }, |
|
1934 { 0x06, 0xe383 }, |
|
1935 { 0x06, 0x491b }, |
|
1936 { 0x06, 0x56ab }, |
|
1937 { 0x06, 0x08ef }, |
|
1938 { 0x06, 0x56e6 }, |
|
1939 { 0x06, 0x8348 }, |
|
1940 { 0x06, 0xe783 }, |
|
1941 { 0x06, 0x4910 }, |
|
1942 { 0x06, 0xd180 }, |
|
1943 { 0x06, 0x1f66 }, |
|
1944 { 0x06, 0xa004 }, |
|
1945 { 0x06, 0xb9e2 }, |
|
1946 { 0x06, 0x8348 }, |
|
1947 { 0x06, 0xe383 }, |
|
1948 { 0x06, 0x49ef }, |
|
1949 { 0x06, 0x65e2 }, |
|
1950 { 0x06, 0x834a }, |
|
1951 { 0x06, 0xe383 }, |
|
1952 { 0x06, 0x4b1b }, |
|
1953 { 0x06, 0x56aa }, |
|
1954 { 0x06, 0x0eef }, |
|
1955 { 0x06, 0x56e6 }, |
|
1956 { 0x06, 0x834a }, |
|
1957 { 0x06, 0xe783 }, |
|
1958 { 0x06, 0x4be2 }, |
|
1959 { 0x06, 0x834d }, |
|
1960 { 0x06, 0xe683 }, |
|
1961 { 0x06, 0x4ce0 }, |
|
1962 { 0x06, 0x834d }, |
|
1963 { 0x06, 0xa000 }, |
|
1964 { 0x06, 0x0caf }, |
|
1965 { 0x06, 0x81dc }, |
|
1966 { 0x06, 0xe083 }, |
|
1967 { 0x06, 0x4d10 }, |
|
1968 { 0x06, 0xe483 }, |
|
1969 { 0x06, 0x4dae }, |
|
1970 { 0x06, 0x0480 }, |
|
1971 { 0x06, 0xe483 }, |
|
1972 { 0x06, 0x4de0 }, |
|
1973 { 0x06, 0x834e }, |
|
1974 { 0x06, 0x7803 }, |
|
1975 { 0x06, 0x9e0b }, |
|
1976 { 0x06, 0xe083 }, |
|
1977 { 0x06, 0x4e78 }, |
|
1978 { 0x06, 0x049e }, |
|
1979 { 0x06, 0x04ee }, |
|
1980 { 0x06, 0x834e }, |
|
1981 { 0x06, 0x02e0 }, |
|
1982 { 0x06, 0x8332 }, |
|
1983 { 0x06, 0xe183 }, |
|
1984 { 0x06, 0x3359 }, |
|
1985 { 0x06, 0x0fe2 }, |
|
1986 { 0x06, 0x834d }, |
|
1987 { 0x06, 0x0c24 }, |
|
1988 { 0x06, 0x5af0 }, |
|
1989 { 0x06, 0x1e12 }, |
|
1990 { 0x06, 0xe4f8 }, |
|
1991 { 0x06, 0x8ce5 }, |
|
1992 { 0x06, 0xf88d }, |
|
1993 { 0x06, 0xe083 }, |
|
1994 { 0x06, 0x30e1 }, |
|
1995 { 0x06, 0x8331 }, |
|
1996 { 0x06, 0x6801 }, |
|
1997 { 0x06, 0xe4f8 }, |
|
1998 { 0x06, 0x8ae5 }, |
|
1999 { 0x06, 0xf88b }, |
|
2000 { 0x06, 0xae37 }, |
|
2001 { 0x06, 0xee83 }, |
|
2002 { 0x06, 0x4e03 }, |
|
2003 { 0x06, 0xe083 }, |
|
2004 { 0x06, 0x4ce1 }, |
|
2005 { 0x06, 0x834d }, |
|
2006 { 0x06, 0x1b01 }, |
|
2007 { 0x06, 0x9e04 }, |
|
2008 { 0x06, 0xaaa1 }, |
|
2009 { 0x06, 0xaea8 }, |
|
2010 { 0x06, 0xee83 }, |
|
2011 { 0x06, 0x4e04 }, |
|
2012 { 0x06, 0xee83 }, |
|
2013 { 0x06, 0x4f00 }, |
|
2014 { 0x06, 0xaeab }, |
|
2015 { 0x06, 0xe083 }, |
|
2016 { 0x06, 0x4f78 }, |
|
2017 { 0x06, 0x039f }, |
|
2018 { 0x06, 0x14ee }, |
|
2019 { 0x06, 0x834e }, |
|
2020 { 0x06, 0x05d2 }, |
|
2021 { 0x06, 0x40d6 }, |
|
2022 { 0x06, 0x5554 }, |
|
2023 { 0x06, 0x0282 }, |
|
2024 { 0x06, 0x17d2 }, |
|
2025 { 0x06, 0xa0d6 }, |
|
2026 { 0x06, 0xba00 }, |
|
2027 { 0x06, 0x0282 }, |
|
2028 { 0x06, 0x17fe }, |
|
2029 { 0x06, 0xfdfc }, |
|
2030 { 0x06, 0x05f8 }, |
|
2031 { 0x06, 0xe0f8 }, |
|
2032 { 0x06, 0x60e1 }, |
|
2033 { 0x06, 0xf861 }, |
|
2034 { 0x06, 0x6802 }, |
|
2035 { 0x06, 0xe4f8 }, |
|
2036 { 0x06, 0x60e5 }, |
|
2037 { 0x06, 0xf861 }, |
|
2038 { 0x06, 0xe0f8 }, |
|
2039 { 0x06, 0x48e1 }, |
|
2040 { 0x06, 0xf849 }, |
|
2041 { 0x06, 0x580f }, |
|
2042 { 0x06, 0x1e02 }, |
|
2043 { 0x06, 0xe4f8 }, |
|
2044 { 0x06, 0x48e5 }, |
|
2045 { 0x06, 0xf849 }, |
|
2046 { 0x06, 0xd000 }, |
|
2047 { 0x06, 0x0282 }, |
|
2048 { 0x06, 0x5bbf }, |
|
2049 { 0x06, 0x8350 }, |
|
2050 { 0x06, 0xef46 }, |
|
2051 { 0x06, 0xdc19 }, |
|
2052 { 0x06, 0xddd0 }, |
|
2053 { 0x06, 0x0102 }, |
|
2054 { 0x06, 0x825b }, |
|
2055 { 0x06, 0x0282 }, |
|
2056 { 0x06, 0x77e0 }, |
|
2057 { 0x06, 0xf860 }, |
|
2058 { 0x06, 0xe1f8 }, |
|
2059 { 0x06, 0x6158 }, |
|
2060 { 0x06, 0xfde4 }, |
|
2061 { 0x06, 0xf860 }, |
|
2062 { 0x06, 0xe5f8 }, |
|
2063 { 0x06, 0x61fc }, |
|
2064 { 0x06, 0x04f9 }, |
|
2065 { 0x06, 0xfafb }, |
|
2066 { 0x06, 0xc6bf }, |
|
2067 { 0x06, 0xf840 }, |
|
2068 { 0x06, 0xbe83 }, |
|
2069 { 0x06, 0x50a0 }, |
|
2070 { 0x06, 0x0101 }, |
|
2071 { 0x06, 0x071b }, |
|
2072 { 0x06, 0x89cf }, |
|
2073 { 0x06, 0xd208 }, |
|
2074 { 0x06, 0xebdb }, |
|
2075 { 0x06, 0x19b2 }, |
|
2076 { 0x06, 0xfbff }, |
|
2077 { 0x06, 0xfefd }, |
|
2078 { 0x06, 0x04f8 }, |
|
2079 { 0x06, 0xe0f8 }, |
|
2080 { 0x06, 0x48e1 }, |
|
2081 { 0x06, 0xf849 }, |
|
2082 { 0x06, 0x6808 }, |
|
2083 { 0x06, 0xe4f8 }, |
|
2084 { 0x06, 0x48e5 }, |
|
2085 { 0x06, 0xf849 }, |
|
2086 { 0x06, 0x58f7 }, |
|
2087 { 0x06, 0xe4f8 }, |
|
2088 { 0x06, 0x48e5 }, |
|
2089 { 0x06, 0xf849 }, |
|
2090 { 0x06, 0xfc04 }, |
|
2091 { 0x06, 0x4d20 }, |
|
2092 { 0x06, 0x0002 }, |
|
2093 { 0x06, 0x4e22 }, |
|
2094 { 0x06, 0x0002 }, |
|
2095 { 0x06, 0x4ddf }, |
|
2096 { 0x06, 0xff01 }, |
|
2097 { 0x06, 0x4edd }, |
|
2098 { 0x06, 0xff01 }, |
|
2099 { 0x05, 0x83d4 }, |
|
2100 { 0x06, 0x8000 }, |
|
2101 { 0x05, 0x83d8 }, |
|
2102 { 0x06, 0x8051 }, |
|
2103 { 0x02, 0x6010 }, |
|
2104 { 0x03, 0xdc00 }, |
|
2105 { 0x05, 0xfff6 }, |
|
2106 { 0x06, 0x00fc }, |
|
2107 { 0x1f, 0x0000 }, |
|
2108 |
|
2109 { 0x1f, 0x0000 }, |
|
2110 { 0x0d, 0xf880 }, |
|
2111 { 0x1f, 0x0000 } |
|
2112 }; |
|
2113 |
|
2114 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2115 |
|
2116 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2117 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef); |
|
2118 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00); |
|
2119 |
|
2120 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); |
|
2121 |
|
2122 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2123 static const struct phy_reg phy_reg_init[] = { |
|
2124 { 0x1f, 0x0002 }, |
|
2125 { 0x05, 0x669a }, |
|
2126 { 0x1f, 0x0005 }, |
|
2127 { 0x05, 0x8330 }, |
|
2128 { 0x06, 0x669a }, |
|
2129 { 0x1f, 0x0002 } |
|
2130 }; |
|
2131 int val; |
|
2132 |
|
2133 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2134 |
|
2135 val = mdio_read(ioaddr, 0x0d); |
|
2136 |
|
2137 if ((val & 0x00ff) != 0x006c) { |
|
2138 static const u32 set[] = { |
|
2139 0x0065, 0x0066, 0x0067, 0x0068, |
|
2140 0x0069, 0x006a, 0x006b, 0x006c |
|
2141 }; |
|
2142 int i; |
|
2143 |
|
2144 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2145 |
|
2146 val &= 0xff00; |
|
2147 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2148 mdio_write(ioaddr, 0x0d, val | set[i]); |
|
2149 } |
|
2150 } else { |
|
2151 static const struct phy_reg phy_reg_init[] = { |
|
2152 { 0x1f, 0x0002 }, |
|
2153 { 0x05, 0x6662 }, |
|
2154 { 0x1f, 0x0005 }, |
|
2155 { 0x05, 0x8330 }, |
|
2156 { 0x06, 0x6662 } |
|
2157 }; |
|
2158 |
|
2159 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2160 } |
|
2161 |
|
2162 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2163 mdio_patch(ioaddr, 0x0d, 0x0300); |
|
2164 mdio_patch(ioaddr, 0x0f, 0x0010); |
|
2165 |
|
2166 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2167 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); |
|
2168 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); |
|
2169 |
|
2170 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); |
|
2171 } |
|
2172 |
|
2173 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) |
|
2174 { |
|
2175 static const struct phy_reg phy_reg_init_0[] = { |
|
2176 { 0x1f, 0x0001 }, |
|
2177 { 0x06, 0x4064 }, |
|
2178 { 0x07, 0x2863 }, |
|
2179 { 0x08, 0x059c }, |
|
2180 { 0x09, 0x26b4 }, |
|
2181 { 0x0a, 0x6a19 }, |
|
2182 { 0x0b, 0xdcc8 }, |
|
2183 { 0x10, 0xf06d }, |
|
2184 { 0x14, 0x7f68 }, |
|
2185 { 0x18, 0x7fd9 }, |
|
2186 { 0x1c, 0xf0ff }, |
|
2187 { 0x1d, 0x3d9c }, |
|
2188 { 0x1f, 0x0003 }, |
|
2189 { 0x12, 0xf49f }, |
|
2190 { 0x13, 0x070b }, |
|
2191 { 0x1a, 0x05ad }, |
|
2192 { 0x14, 0x94c0 }, |
|
2193 |
|
2194 { 0x1f, 0x0002 }, |
|
2195 { 0x06, 0x5561 }, |
|
2196 { 0x1f, 0x0005 }, |
|
2197 { 0x05, 0x8332 }, |
|
2198 { 0x06, 0x5561 } |
|
2199 }; |
|
2200 static const struct phy_reg phy_reg_init_1[] = { |
|
2201 { 0x1f, 0x0005 }, |
|
2202 { 0x05, 0xffc2 }, |
|
2203 { 0x1f, 0x0005 }, |
|
2204 { 0x05, 0x8000 }, |
|
2205 { 0x06, 0xf8f9 }, |
|
2206 { 0x06, 0xfaee }, |
|
2207 { 0x06, 0xf8ea }, |
|
2208 { 0x06, 0x00ee }, |
|
2209 { 0x06, 0xf8eb }, |
|
2210 { 0x06, 0x00e2 }, |
|
2211 { 0x06, 0xf87c }, |
|
2212 { 0x06, 0xe3f8 }, |
|
2213 { 0x06, 0x7da5 }, |
|
2214 { 0x06, 0x1111 }, |
|
2215 { 0x06, 0x12d2 }, |
|
2216 { 0x06, 0x40d6 }, |
|
2217 { 0x06, 0x4444 }, |
|
2218 { 0x06, 0x0281 }, |
|
2219 { 0x06, 0xc6d2 }, |
|
2220 { 0x06, 0xa0d6 }, |
|
2221 { 0x06, 0xaaaa }, |
|
2222 { 0x06, 0x0281 }, |
|
2223 { 0x06, 0xc6ae }, |
|
2224 { 0x06, 0x0fa5 }, |
|
2225 { 0x06, 0x4444 }, |
|
2226 { 0x06, 0x02ae }, |
|
2227 { 0x06, 0x4da5 }, |
|
2228 { 0x06, 0xaaaa }, |
|
2229 { 0x06, 0x02ae }, |
|
2230 { 0x06, 0x47af }, |
|
2231 { 0x06, 0x81c2 }, |
|
2232 { 0x06, 0xee83 }, |
|
2233 { 0x06, 0x4e00 }, |
|
2234 { 0x06, 0xee83 }, |
|
2235 { 0x06, 0x4d0f }, |
|
2236 { 0x06, 0xee83 }, |
|
2237 { 0x06, 0x4c0f }, |
|
2238 { 0x06, 0xee83 }, |
|
2239 { 0x06, 0x4f00 }, |
|
2240 { 0x06, 0xee83 }, |
|
2241 { 0x06, 0x5100 }, |
|
2242 { 0x06, 0xee83 }, |
|
2243 { 0x06, 0x4aff }, |
|
2244 { 0x06, 0xee83 }, |
|
2245 { 0x06, 0x4bff }, |
|
2246 { 0x06, 0xe083 }, |
|
2247 { 0x06, 0x30e1 }, |
|
2248 { 0x06, 0x8331 }, |
|
2249 { 0x06, 0x58fe }, |
|
2250 { 0x06, 0xe4f8 }, |
|
2251 { 0x06, 0x8ae5 }, |
|
2252 { 0x06, 0xf88b }, |
|
2253 { 0x06, 0xe083 }, |
|
2254 { 0x06, 0x32e1 }, |
|
2255 { 0x06, 0x8333 }, |
|
2256 { 0x06, 0x590f }, |
|
2257 { 0x06, 0xe283 }, |
|
2258 { 0x06, 0x4d0c }, |
|
2259 { 0x06, 0x245a }, |
|
2260 { 0x06, 0xf01e }, |
|
2261 { 0x06, 0x12e4 }, |
|
2262 { 0x06, 0xf88c }, |
|
2263 { 0x06, 0xe5f8 }, |
|
2264 { 0x06, 0x8daf }, |
|
2265 { 0x06, 0x81c2 }, |
|
2266 { 0x06, 0xe083 }, |
|
2267 { 0x06, 0x4f10 }, |
|
2268 { 0x06, 0xe483 }, |
|
2269 { 0x06, 0x4fe0 }, |
|
2270 { 0x06, 0x834e }, |
|
2271 { 0x06, 0x7800 }, |
|
2272 { 0x06, 0x9f0a }, |
|
2273 { 0x06, 0xe083 }, |
|
2274 { 0x06, 0x4fa0 }, |
|
2275 { 0x06, 0x10a5 }, |
|
2276 { 0x06, 0xee83 }, |
|
2277 { 0x06, 0x4e01 }, |
|
2278 { 0x06, 0xe083 }, |
|
2279 { 0x06, 0x4e78 }, |
|
2280 { 0x06, 0x059e }, |
|
2281 { 0x06, 0x9ae0 }, |
|
2282 { 0x06, 0x834e }, |
|
2283 { 0x06, 0x7804 }, |
|
2284 { 0x06, 0x9e10 }, |
|
2285 { 0x06, 0xe083 }, |
|
2286 { 0x06, 0x4e78 }, |
|
2287 { 0x06, 0x039e }, |
|
2288 { 0x06, 0x0fe0 }, |
|
2289 { 0x06, 0x834e }, |
|
2290 { 0x06, 0x7801 }, |
|
2291 { 0x06, 0x9e05 }, |
|
2292 { 0x06, 0xae0c }, |
|
2293 { 0x06, 0xaf81 }, |
|
2294 { 0x06, 0xa7af }, |
|
2295 { 0x06, 0x8152 }, |
|
2296 { 0x06, 0xaf81 }, |
|
2297 { 0x06, 0x8baf }, |
|
2298 { 0x06, 0x81c2 }, |
|
2299 { 0x06, 0xee83 }, |
|
2300 { 0x06, 0x4800 }, |
|
2301 { 0x06, 0xee83 }, |
|
2302 { 0x06, 0x4900 }, |
|
2303 { 0x06, 0xe083 }, |
|
2304 { 0x06, 0x5110 }, |
|
2305 { 0x06, 0xe483 }, |
|
2306 { 0x06, 0x5158 }, |
|
2307 { 0x06, 0x019f }, |
|
2308 { 0x06, 0xead0 }, |
|
2309 { 0x06, 0x00d1 }, |
|
2310 { 0x06, 0x801f }, |
|
2311 { 0x06, 0x66e2 }, |
|
2312 { 0x06, 0xf8ea }, |
|
2313 { 0x06, 0xe3f8 }, |
|
2314 { 0x06, 0xeb5a }, |
|
2315 { 0x06, 0xf81e }, |
|
2316 { 0x06, 0x20e6 }, |
|
2317 { 0x06, 0xf8ea }, |
|
2318 { 0x06, 0xe5f8 }, |
|
2319 { 0x06, 0xebd3 }, |
|
2320 { 0x06, 0x02b3 }, |
|
2321 { 0x06, 0xfee2 }, |
|
2322 { 0x06, 0xf87c }, |
|
2323 { 0x06, 0xef32 }, |
|
2324 { 0x06, 0x5b80 }, |
|
2325 { 0x06, 0xe3f8 }, |
|
2326 { 0x06, 0x7d9e }, |
|
2327 { 0x06, 0x037d }, |
|
2328 { 0x06, 0xffff }, |
|
2329 { 0x06, 0x0d58 }, |
|
2330 { 0x06, 0x1c55 }, |
|
2331 { 0x06, 0x1a65 }, |
|
2332 { 0x06, 0x11a1 }, |
|
2333 { 0x06, 0x90d3 }, |
|
2334 { 0x06, 0xe283 }, |
|
2335 { 0x06, 0x48e3 }, |
|
2336 { 0x06, 0x8349 }, |
|
2337 { 0x06, 0x1b56 }, |
|
2338 { 0x06, 0xab08 }, |
|
2339 { 0x06, 0xef56 }, |
|
2340 { 0x06, 0xe683 }, |
|
2341 { 0x06, 0x48e7 }, |
|
2342 { 0x06, 0x8349 }, |
|
2343 { 0x06, 0x10d1 }, |
|
2344 { 0x06, 0x801f }, |
|
2345 { 0x06, 0x66a0 }, |
|
2346 { 0x06, 0x04b9 }, |
|
2347 { 0x06, 0xe283 }, |
|
2348 { 0x06, 0x48e3 }, |
|
2349 { 0x06, 0x8349 }, |
|
2350 { 0x06, 0xef65 }, |
|
2351 { 0x06, 0xe283 }, |
|
2352 { 0x06, 0x4ae3 }, |
|
2353 { 0x06, 0x834b }, |
|
2354 { 0x06, 0x1b56 }, |
|
2355 { 0x06, 0xaa0e }, |
|
2356 { 0x06, 0xef56 }, |
|
2357 { 0x06, 0xe683 }, |
|
2358 { 0x06, 0x4ae7 }, |
|
2359 { 0x06, 0x834b }, |
|
2360 { 0x06, 0xe283 }, |
|
2361 { 0x06, 0x4de6 }, |
|
2362 { 0x06, 0x834c }, |
|
2363 { 0x06, 0xe083 }, |
|
2364 { 0x06, 0x4da0 }, |
|
2365 { 0x06, 0x000c }, |
|
2366 { 0x06, 0xaf81 }, |
|
2367 { 0x06, 0x8be0 }, |
|
2368 { 0x06, 0x834d }, |
|
2369 { 0x06, 0x10e4 }, |
|
2370 { 0x06, 0x834d }, |
|
2371 { 0x06, 0xae04 }, |
|
2372 { 0x06, 0x80e4 }, |
|
2373 { 0x06, 0x834d }, |
|
2374 { 0x06, 0xe083 }, |
|
2375 { 0x06, 0x4e78 }, |
|
2376 { 0x06, 0x039e }, |
|
2377 { 0x06, 0x0be0 }, |
|
2378 { 0x06, 0x834e }, |
|
2379 { 0x06, 0x7804 }, |
|
2380 { 0x06, 0x9e04 }, |
|
2381 { 0x06, 0xee83 }, |
|
2382 { 0x06, 0x4e02 }, |
|
2383 { 0x06, 0xe083 }, |
|
2384 { 0x06, 0x32e1 }, |
|
2385 { 0x06, 0x8333 }, |
|
2386 { 0x06, 0x590f }, |
|
2387 { 0x06, 0xe283 }, |
|
2388 { 0x06, 0x4d0c }, |
|
2389 { 0x06, 0x245a }, |
|
2390 { 0x06, 0xf01e }, |
|
2391 { 0x06, 0x12e4 }, |
|
2392 { 0x06, 0xf88c }, |
|
2393 { 0x06, 0xe5f8 }, |
|
2394 { 0x06, 0x8de0 }, |
|
2395 { 0x06, 0x8330 }, |
|
2396 { 0x06, 0xe183 }, |
|
2397 { 0x06, 0x3168 }, |
|
2398 { 0x06, 0x01e4 }, |
|
2399 { 0x06, 0xf88a }, |
|
2400 { 0x06, 0xe5f8 }, |
|
2401 { 0x06, 0x8bae }, |
|
2402 { 0x06, 0x37ee }, |
|
2403 { 0x06, 0x834e }, |
|
2404 { 0x06, 0x03e0 }, |
|
2405 { 0x06, 0x834c }, |
|
2406 { 0x06, 0xe183 }, |
|
2407 { 0x06, 0x4d1b }, |
|
2408 { 0x06, 0x019e }, |
|
2409 { 0x06, 0x04aa }, |
|
2410 { 0x06, 0xa1ae }, |
|
2411 { 0x06, 0xa8ee }, |
|
2412 { 0x06, 0x834e }, |
|
2413 { 0x06, 0x04ee }, |
|
2414 { 0x06, 0x834f }, |
|
2415 { 0x06, 0x00ae }, |
|
2416 { 0x06, 0xabe0 }, |
|
2417 { 0x06, 0x834f }, |
|
2418 { 0x06, 0x7803 }, |
|
2419 { 0x06, 0x9f14 }, |
|
2420 { 0x06, 0xee83 }, |
|
2421 { 0x06, 0x4e05 }, |
|
2422 { 0x06, 0xd240 }, |
|
2423 { 0x06, 0xd655 }, |
|
2424 { 0x06, 0x5402 }, |
|
2425 { 0x06, 0x81c6 }, |
|
2426 { 0x06, 0xd2a0 }, |
|
2427 { 0x06, 0xd6ba }, |
|
2428 { 0x06, 0x0002 }, |
|
2429 { 0x06, 0x81c6 }, |
|
2430 { 0x06, 0xfefd }, |
|
2431 { 0x06, 0xfc05 }, |
|
2432 { 0x06, 0xf8e0 }, |
|
2433 { 0x06, 0xf860 }, |
|
2434 { 0x06, 0xe1f8 }, |
|
2435 { 0x06, 0x6168 }, |
|
2436 { 0x06, 0x02e4 }, |
|
2437 { 0x06, 0xf860 }, |
|
2438 { 0x06, 0xe5f8 }, |
|
2439 { 0x06, 0x61e0 }, |
|
2440 { 0x06, 0xf848 }, |
|
2441 { 0x06, 0xe1f8 }, |
|
2442 { 0x06, 0x4958 }, |
|
2443 { 0x06, 0x0f1e }, |
|
2444 { 0x06, 0x02e4 }, |
|
2445 { 0x06, 0xf848 }, |
|
2446 { 0x06, 0xe5f8 }, |
|
2447 { 0x06, 0x49d0 }, |
|
2448 { 0x06, 0x0002 }, |
|
2449 { 0x06, 0x820a }, |
|
2450 { 0x06, 0xbf83 }, |
|
2451 { 0x06, 0x50ef }, |
|
2452 { 0x06, 0x46dc }, |
|
2453 { 0x06, 0x19dd }, |
|
2454 { 0x06, 0xd001 }, |
|
2455 { 0x06, 0x0282 }, |
|
2456 { 0x06, 0x0a02 }, |
|
2457 { 0x06, 0x8226 }, |
|
2458 { 0x06, 0xe0f8 }, |
|
2459 { 0x06, 0x60e1 }, |
|
2460 { 0x06, 0xf861 }, |
|
2461 { 0x06, 0x58fd }, |
|
2462 { 0x06, 0xe4f8 }, |
|
2463 { 0x06, 0x60e5 }, |
|
2464 { 0x06, 0xf861 }, |
|
2465 { 0x06, 0xfc04 }, |
|
2466 { 0x06, 0xf9fa }, |
|
2467 { 0x06, 0xfbc6 }, |
|
2468 { 0x06, 0xbff8 }, |
|
2469 { 0x06, 0x40be }, |
|
2470 { 0x06, 0x8350 }, |
|
2471 { 0x06, 0xa001 }, |
|
2472 { 0x06, 0x0107 }, |
|
2473 { 0x06, 0x1b89 }, |
|
2474 { 0x06, 0xcfd2 }, |
|
2475 { 0x06, 0x08eb }, |
|
2476 { 0x06, 0xdb19 }, |
|
2477 { 0x06, 0xb2fb }, |
|
2478 { 0x06, 0xfffe }, |
|
2479 { 0x06, 0xfd04 }, |
|
2480 { 0x06, 0xf8e0 }, |
|
2481 { 0x06, 0xf848 }, |
|
2482 { 0x06, 0xe1f8 }, |
|
2483 { 0x06, 0x4968 }, |
|
2484 { 0x06, 0x08e4 }, |
|
2485 { 0x06, 0xf848 }, |
|
2486 { 0x06, 0xe5f8 }, |
|
2487 { 0x06, 0x4958 }, |
|
2488 { 0x06, 0xf7e4 }, |
|
2489 { 0x06, 0xf848 }, |
|
2490 { 0x06, 0xe5f8 }, |
|
2491 { 0x06, 0x49fc }, |
|
2492 { 0x06, 0x044d }, |
|
2493 { 0x06, 0x2000 }, |
|
2494 { 0x06, 0x024e }, |
|
2495 { 0x06, 0x2200 }, |
|
2496 { 0x06, 0x024d }, |
|
2497 { 0x06, 0xdfff }, |
|
2498 { 0x06, 0x014e }, |
|
2499 { 0x06, 0xddff }, |
|
2500 { 0x06, 0x0100 }, |
|
2501 { 0x05, 0x83d8 }, |
|
2502 { 0x06, 0x8000 }, |
|
2503 { 0x03, 0xdc00 }, |
|
2504 { 0x05, 0xfff6 }, |
|
2505 { 0x06, 0x00fc }, |
|
2506 { 0x1f, 0x0000 }, |
|
2507 |
|
2508 { 0x1f, 0x0000 }, |
|
2509 { 0x0d, 0xf880 }, |
|
2510 { 0x1f, 0x0000 } |
|
2511 }; |
|
2512 |
|
2513 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2514 |
|
2515 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2516 static const struct phy_reg phy_reg_init[] = { |
|
2517 { 0x1f, 0x0002 }, |
|
2518 { 0x05, 0x669a }, |
|
2519 { 0x1f, 0x0005 }, |
|
2520 { 0x05, 0x8330 }, |
|
2521 { 0x06, 0x669a }, |
|
2522 |
|
2523 { 0x1f, 0x0002 } |
|
2524 }; |
|
2525 int val; |
|
2526 |
|
2527 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2528 |
|
2529 val = mdio_read(ioaddr, 0x0d); |
|
2530 if ((val & 0x00ff) != 0x006c) { |
|
2531 u32 set[] = { |
|
2532 0x0065, 0x0066, 0x0067, 0x0068, |
|
2533 0x0069, 0x006a, 0x006b, 0x006c |
|
2534 }; |
|
2535 int i; |
|
2536 |
|
2537 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2538 |
|
2539 val &= 0xff00; |
|
2540 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2541 mdio_write(ioaddr, 0x0d, val | set[i]); |
|
2542 } |
|
2543 } else { |
|
2544 static const struct phy_reg phy_reg_init[] = { |
|
2545 { 0x1f, 0x0002 }, |
|
2546 { 0x05, 0x2642 }, |
|
2547 { 0x1f, 0x0005 }, |
|
2548 { 0x05, 0x8330 }, |
|
2549 { 0x06, 0x2642 } |
|
2550 }; |
|
2551 |
|
2552 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2553 } |
|
2554 |
|
2555 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2556 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); |
|
2557 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); |
|
2558 |
|
2559 mdio_write(ioaddr, 0x1f, 0x0001); |
|
2560 mdio_write(ioaddr, 0x17, 0x0cc0); |
|
2561 |
|
2562 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2563 mdio_patch(ioaddr, 0x0f, 0x0017); |
|
2564 |
|
2565 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); |
|
2566 } |
|
2567 |
|
2568 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) |
|
2569 { |
|
2570 static const struct phy_reg phy_reg_init[] = { |
|
2571 { 0x1f, 0x0002 }, |
|
2572 { 0x10, 0x0008 }, |
|
2573 { 0x0d, 0x006c }, |
|
2574 |
|
2575 { 0x1f, 0x0000 }, |
|
2576 { 0x0d, 0xf880 }, |
|
2577 |
|
2578 { 0x1f, 0x0001 }, |
|
2579 { 0x17, 0x0cc0 }, |
|
2580 |
|
2581 { 0x1f, 0x0001 }, |
|
2582 { 0x0b, 0xa4d8 }, |
|
2583 { 0x09, 0x281c }, |
|
2584 { 0x07, 0x2883 }, |
|
2585 { 0x0a, 0x6b35 }, |
|
2586 { 0x1d, 0x3da4 }, |
|
2587 { 0x1c, 0xeffd }, |
|
2588 { 0x14, 0x7f52 }, |
|
2589 { 0x18, 0x7fc6 }, |
|
2590 { 0x08, 0x0601 }, |
|
2591 { 0x06, 0x4063 }, |
|
2592 { 0x10, 0xf074 }, |
|
2593 { 0x1f, 0x0003 }, |
|
2594 { 0x13, 0x0789 }, |
|
2595 { 0x12, 0xf4bd }, |
|
2596 { 0x1a, 0x04fd }, |
|
2597 { 0x14, 0x84b0 }, |
|
2598 { 0x1f, 0x0000 }, |
|
2599 { 0x00, 0x9200 }, |
|
2600 |
|
2601 { 0x1f, 0x0005 }, |
|
2602 { 0x01, 0x0340 }, |
|
2603 { 0x1f, 0x0001 }, |
|
2604 { 0x04, 0x4000 }, |
|
2605 { 0x03, 0x1d21 }, |
|
2606 { 0x02, 0x0c32 }, |
|
2607 { 0x01, 0x0200 }, |
|
2608 { 0x00, 0x5554 }, |
|
2609 { 0x04, 0x4800 }, |
|
2610 { 0x04, 0x4000 }, |
|
2611 { 0x04, 0xf000 }, |
|
2612 { 0x03, 0xdf01 }, |
|
2613 { 0x02, 0xdf20 }, |
|
2614 { 0x01, 0x101a }, |
|
2615 { 0x00, 0xa0ff }, |
|
2616 { 0x04, 0xf800 }, |
|
2617 { 0x04, 0xf000 }, |
|
2618 { 0x1f, 0x0000 }, |
|
2619 |
|
2620 { 0x1f, 0x0007 }, |
|
2621 { 0x1e, 0x0023 }, |
|
2622 { 0x16, 0x0000 }, |
|
2623 { 0x1f, 0x0000 } |
|
2624 }; |
|
2625 |
|
2626 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2627 } |
|
2628 |
|
2629 static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
|
2630 { |
|
2631 static const struct phy_reg phy_reg_init[] = { |
|
2632 { 0x1f, 0x0003 }, |
|
2633 { 0x08, 0x441d }, |
|
2634 { 0x01, 0x9100 }, |
|
2635 { 0x1f, 0x0000 } |
|
2636 }; |
|
2637 |
|
2638 mdio_write(ioaddr, 0x1f, 0x0000); |
|
2639 mdio_patch(ioaddr, 0x11, 1 << 12); |
|
2640 mdio_patch(ioaddr, 0x19, 1 << 13); |
|
2641 mdio_patch(ioaddr, 0x10, 1 << 15); |
|
2642 |
|
2643 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2644 } |
|
2645 |
|
2646 static void rtl_hw_phy_config(struct net_device *dev) |
|
2647 { |
|
2648 struct rtl8169_private *tp = netdev_priv(dev); |
|
2649 void __iomem *ioaddr = tp->mmio_addr; |
|
2650 |
|
2651 rtl8169_print_mac_version(tp); |
|
2652 |
|
2653 switch (tp->mac_version) { |
|
2654 case RTL_GIGA_MAC_VER_01: |
|
2655 break; |
|
2656 case RTL_GIGA_MAC_VER_02: |
|
2657 case RTL_GIGA_MAC_VER_03: |
|
2658 rtl8169s_hw_phy_config(ioaddr); |
|
2659 break; |
|
2660 case RTL_GIGA_MAC_VER_04: |
|
2661 rtl8169sb_hw_phy_config(ioaddr); |
|
2662 break; |
|
2663 case RTL_GIGA_MAC_VER_05: |
|
2664 rtl8169scd_hw_phy_config(tp, ioaddr); |
|
2665 break; |
|
2666 case RTL_GIGA_MAC_VER_06: |
|
2667 rtl8169sce_hw_phy_config(ioaddr); |
|
2668 break; |
|
2669 case RTL_GIGA_MAC_VER_07: |
|
2670 case RTL_GIGA_MAC_VER_08: |
|
2671 case RTL_GIGA_MAC_VER_09: |
|
2672 rtl8102e_hw_phy_config(ioaddr); |
|
2673 break; |
|
2674 case RTL_GIGA_MAC_VER_11: |
|
2675 rtl8168bb_hw_phy_config(ioaddr); |
|
2676 break; |
|
2677 case RTL_GIGA_MAC_VER_12: |
|
2678 rtl8168bef_hw_phy_config(ioaddr); |
|
2679 break; |
|
2680 case RTL_GIGA_MAC_VER_17: |
|
2681 rtl8168bef_hw_phy_config(ioaddr); |
|
2682 break; |
|
2683 case RTL_GIGA_MAC_VER_18: |
|
2684 rtl8168cp_1_hw_phy_config(ioaddr); |
|
2685 break; |
|
2686 case RTL_GIGA_MAC_VER_19: |
|
2687 rtl8168c_1_hw_phy_config(ioaddr); |
|
2688 break; |
|
2689 case RTL_GIGA_MAC_VER_20: |
|
2690 rtl8168c_2_hw_phy_config(ioaddr); |
|
2691 break; |
|
2692 case RTL_GIGA_MAC_VER_21: |
|
2693 rtl8168c_3_hw_phy_config(ioaddr); |
|
2694 break; |
|
2695 case RTL_GIGA_MAC_VER_22: |
|
2696 rtl8168c_4_hw_phy_config(ioaddr); |
|
2697 break; |
|
2698 case RTL_GIGA_MAC_VER_23: |
|
2699 case RTL_GIGA_MAC_VER_24: |
|
2700 rtl8168cp_2_hw_phy_config(ioaddr); |
|
2701 break; |
|
2702 case RTL_GIGA_MAC_VER_25: |
|
2703 rtl8168d_1_hw_phy_config(ioaddr); |
|
2704 break; |
|
2705 case RTL_GIGA_MAC_VER_26: |
|
2706 rtl8168d_2_hw_phy_config(ioaddr); |
|
2707 break; |
|
2708 case RTL_GIGA_MAC_VER_27: |
|
2709 rtl8168d_3_hw_phy_config(ioaddr); |
|
2710 break; |
|
2711 |
|
2712 default: |
|
2713 break; |
|
2714 } |
|
2715 } |
|
2716 |
|
2717 static void rtl8169_phy_timer(unsigned long __opaque) |
|
2718 { |
|
2719 struct net_device *dev = (struct net_device *)__opaque; |
|
2720 struct rtl8169_private *tp = netdev_priv(dev); |
|
2721 struct timer_list *timer = &tp->timer; |
|
2722 void __iomem *ioaddr = tp->mmio_addr; |
|
2723 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
2724 |
|
2725 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
2726 |
|
2727 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
2728 return; |
|
2729 |
|
2730 spin_lock_irq(&tp->lock); |
|
2731 |
|
2732 if (tp->phy_reset_pending(ioaddr)) { |
|
2733 /* |
|
2734 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
2735 * Let's delay the execution of the timer for a few ticks. |
|
2736 */ |
|
2737 timeout = HZ/10; |
|
2738 goto out_mod_timer; |
|
2739 } |
|
2740 |
|
2741 if (tp->link_ok(ioaddr)) |
|
2742 goto out_unlock; |
|
2743 |
|
2744 netif_warn(tp, link, dev, "PHY reset until link up\n"); |
|
2745 |
|
2746 tp->phy_reset_enable(ioaddr); |
|
2747 |
|
2748 out_mod_timer: |
|
2749 mod_timer(timer, jiffies + timeout); |
|
2750 out_unlock: |
|
2751 spin_unlock_irq(&tp->lock); |
|
2752 } |
|
2753 |
|
2754 static inline void rtl8169_delete_timer(struct net_device *dev) |
|
2755 { |
|
2756 struct rtl8169_private *tp = netdev_priv(dev); |
|
2757 struct timer_list *timer = &tp->timer; |
|
2758 |
|
2759 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
2760 return; |
|
2761 |
|
2762 del_timer_sync(timer); |
|
2763 } |
|
2764 |
|
2765 static inline void rtl8169_request_timer(struct net_device *dev) |
|
2766 { |
|
2767 struct rtl8169_private *tp = netdev_priv(dev); |
|
2768 struct timer_list *timer = &tp->timer; |
|
2769 |
|
2770 if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
2771 return; |
|
2772 |
|
2773 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
2774 } |
|
2775 |
|
2776 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2777 /* |
|
2778 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
2779 * without having to re-enable interrupts. It's not called while |
|
2780 * the interrupt routine is executing. |
|
2781 */ |
|
2782 static void rtl8169_netpoll(struct net_device *dev) |
|
2783 { |
|
2784 struct rtl8169_private *tp = netdev_priv(dev); |
|
2785 struct pci_dev *pdev = tp->pci_dev; |
|
2786 |
|
2787 disable_irq(pdev->irq); |
|
2788 rtl8169_interrupt(pdev->irq, dev); |
|
2789 enable_irq(pdev->irq); |
|
2790 } |
|
2791 #endif |
|
2792 |
|
2793 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
2794 void __iomem *ioaddr) |
|
2795 { |
|
2796 iounmap(ioaddr); |
|
2797 pci_release_regions(pdev); |
|
2798 pci_clear_mwi(pdev); |
|
2799 pci_disable_device(pdev); |
|
2800 free_netdev(dev); |
|
2801 } |
|
2802 |
|
2803 static void rtl8169_phy_reset(struct net_device *dev, |
|
2804 struct rtl8169_private *tp) |
|
2805 { |
|
2806 void __iomem *ioaddr = tp->mmio_addr; |
|
2807 unsigned int i; |
|
2808 |
|
2809 tp->phy_reset_enable(ioaddr); |
|
2810 for (i = 0; i < 100; i++) { |
|
2811 if (!tp->phy_reset_pending(ioaddr)) |
|
2812 return; |
|
2813 msleep(1); |
|
2814 } |
|
2815 netif_err(tp, link, dev, "PHY reset failed\n"); |
|
2816 } |
|
2817 |
|
2818 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
2819 { |
|
2820 void __iomem *ioaddr = tp->mmio_addr; |
|
2821 |
|
2822 rtl_hw_phy_config(dev); |
|
2823 |
|
2824 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
2825 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
2826 RTL_W8(0x82, 0x01); |
|
2827 } |
|
2828 |
|
2829 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
2830 |
|
2831 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
2832 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
2833 |
|
2834 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
2835 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
2836 RTL_W8(0x82, 0x01); |
|
2837 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
2838 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
2839 } |
|
2840 |
|
2841 rtl8169_phy_reset(dev, tp); |
|
2842 |
|
2843 /* |
|
2844 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
2845 * only 8101. Don't panic. |
|
2846 */ |
|
2847 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
2848 |
|
2849 if (RTL_R8(PHYstatus) & TBI_Enable) |
|
2850 netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
|
2851 } |
|
2852 |
|
2853 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
2854 { |
|
2855 void __iomem *ioaddr = tp->mmio_addr; |
|
2856 u32 high; |
|
2857 u32 low; |
|
2858 |
|
2859 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
2860 high = addr[4] | (addr[5] << 8); |
|
2861 |
|
2862 spin_lock_irq(&tp->lock); |
|
2863 |
|
2864 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2865 |
|
2866 RTL_W32(MAC4, high); |
|
2867 RTL_R32(MAC4); |
|
2868 |
|
2869 RTL_W32(MAC0, low); |
|
2870 RTL_R32(MAC0); |
|
2871 |
|
2872 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2873 |
|
2874 spin_unlock_irq(&tp->lock); |
|
2875 } |
|
2876 |
|
2877 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
2878 { |
|
2879 struct rtl8169_private *tp = netdev_priv(dev); |
|
2880 struct sockaddr *addr = p; |
|
2881 |
|
2882 if (!is_valid_ether_addr(addr->sa_data)) |
|
2883 return -EADDRNOTAVAIL; |
|
2884 |
|
2885 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
2886 |
|
2887 rtl_rar_set(tp, dev->dev_addr); |
|
2888 |
|
2889 return 0; |
|
2890 } |
|
2891 |
|
2892 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
2893 { |
|
2894 struct rtl8169_private *tp = netdev_priv(dev); |
|
2895 struct mii_ioctl_data *data = if_mii(ifr); |
|
2896 |
|
2897 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
2898 } |
|
2899 |
|
2900 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
2901 { |
|
2902 switch (cmd) { |
|
2903 case SIOCGMIIPHY: |
|
2904 data->phy_id = 32; /* Internal PHY */ |
|
2905 return 0; |
|
2906 |
|
2907 case SIOCGMIIREG: |
|
2908 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
2909 return 0; |
|
2910 |
|
2911 case SIOCSMIIREG: |
|
2912 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
2913 return 0; |
|
2914 } |
|
2915 return -EOPNOTSUPP; |
|
2916 } |
|
2917 |
|
2918 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
2919 { |
|
2920 return -EOPNOTSUPP; |
|
2921 } |
|
2922 |
|
2923 static const struct rtl_cfg_info { |
|
2924 void (*hw_start)(struct net_device *); |
|
2925 unsigned int region; |
|
2926 unsigned int align; |
|
2927 u16 intr_event; |
|
2928 u16 napi_event; |
|
2929 unsigned features; |
|
2930 u8 default_ver; |
|
2931 } rtl_cfg_infos [] = { |
|
2932 [RTL_CFG_0] = { |
|
2933 .hw_start = rtl_hw_start_8169, |
|
2934 .region = 1, |
|
2935 .align = 0, |
|
2936 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
2937 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
2938 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
2939 .features = RTL_FEATURE_GMII, |
|
2940 .default_ver = RTL_GIGA_MAC_VER_01, |
|
2941 }, |
|
2942 [RTL_CFG_1] = { |
|
2943 .hw_start = rtl_hw_start_8168, |
|
2944 .region = 2, |
|
2945 .align = 8, |
|
2946 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
2947 TxErr | TxOK | RxOK | RxErr, |
|
2948 .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
2949 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
2950 .default_ver = RTL_GIGA_MAC_VER_11, |
|
2951 }, |
|
2952 [RTL_CFG_2] = { |
|
2953 .hw_start = rtl_hw_start_8101, |
|
2954 .region = 2, |
|
2955 .align = 8, |
|
2956 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
2957 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
2958 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
2959 .features = RTL_FEATURE_MSI, |
|
2960 .default_ver = RTL_GIGA_MAC_VER_13, |
|
2961 } |
|
2962 }; |
|
2963 |
|
2964 /* Cfg9346_Unlock assumed. */ |
|
2965 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, |
|
2966 const struct rtl_cfg_info *cfg) |
|
2967 { |
|
2968 unsigned msi = 0; |
|
2969 u8 cfg2; |
|
2970 |
|
2971 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
2972 if (cfg->features & RTL_FEATURE_MSI) { |
|
2973 if (pci_enable_msi(pdev)) { |
|
2974 dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); |
|
2975 } else { |
|
2976 cfg2 |= MSIEnable; |
|
2977 msi = RTL_FEATURE_MSI; |
|
2978 } |
|
2979 } |
|
2980 RTL_W8(Config2, cfg2); |
|
2981 return msi; |
|
2982 } |
|
2983 |
|
2984 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
2985 { |
|
2986 if (tp->features & RTL_FEATURE_MSI) { |
|
2987 pci_disable_msi(pdev); |
|
2988 tp->features &= ~RTL_FEATURE_MSI; |
|
2989 } |
|
2990 } |
|
2991 |
|
2992 static const struct net_device_ops rtl8169_netdev_ops = { |
|
2993 .ndo_open = rtl8169_open, |
|
2994 .ndo_stop = rtl8169_close, |
|
2995 .ndo_get_stats = rtl8169_get_stats, |
|
2996 .ndo_start_xmit = rtl8169_start_xmit, |
|
2997 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
2998 .ndo_validate_addr = eth_validate_addr, |
|
2999 .ndo_change_mtu = rtl8169_change_mtu, |
|
3000 .ndo_set_mac_address = rtl_set_mac_address, |
|
3001 .ndo_do_ioctl = rtl8169_ioctl, |
|
3002 .ndo_set_multicast_list = rtl_set_rx_mode, |
|
3003 #ifdef CONFIG_R8169_VLAN |
|
3004 .ndo_vlan_rx_register = rtl8169_vlan_rx_register, |
|
3005 #endif |
|
3006 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
3007 .ndo_poll_controller = rtl8169_netpoll, |
|
3008 #endif |
|
3009 |
|
3010 }; |
|
3011 |
|
3012 static int __devinit |
|
3013 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
3014 { |
|
3015 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
3016 const unsigned int region = cfg->region; |
|
3017 struct rtl8169_private *tp; |
|
3018 struct mii_if_info *mii; |
|
3019 struct net_device *dev; |
|
3020 void __iomem *ioaddr; |
|
3021 unsigned int i; |
|
3022 int rc; |
|
3023 |
|
3024 if (netif_msg_drv(&debug)) { |
|
3025 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
3026 MODULENAME, RTL8169_VERSION); |
|
3027 } |
|
3028 |
|
3029 dev = alloc_etherdev(sizeof (*tp)); |
|
3030 if (!dev) { |
|
3031 if (netif_msg_drv(&debug)) |
|
3032 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
3033 rc = -ENOMEM; |
|
3034 goto out; |
|
3035 } |
|
3036 |
|
3037 SET_NETDEV_DEV(dev, &pdev->dev); |
|
3038 dev->netdev_ops = &rtl8169_netdev_ops; |
|
3039 tp = netdev_priv(dev); |
|
3040 tp->dev = dev; |
|
3041 tp->pci_dev = pdev; |
|
3042 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
3043 |
|
3044 mii = &tp->mii; |
|
3045 mii->dev = dev; |
|
3046 mii->mdio_read = rtl_mdio_read; |
|
3047 mii->mdio_write = rtl_mdio_write; |
|
3048 mii->phy_id_mask = 0x1f; |
|
3049 mii->reg_num_mask = 0x1f; |
|
3050 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
3051 |
|
3052 /* disable ASPM completely as that cause random device stop working |
|
3053 * problems as well as full system hangs for some PCIe devices users */ |
|
3054 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
|
3055 PCIE_LINK_STATE_CLKPM); |
|
3056 |
|
3057 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
3058 rc = pci_enable_device(pdev); |
|
3059 if (rc < 0) { |
|
3060 netif_err(tp, probe, dev, "enable failure\n"); |
|
3061 goto err_out_free_dev_1; |
|
3062 } |
|
3063 |
|
3064 if (pci_set_mwi(pdev) < 0) |
|
3065 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
|
3066 |
|
3067 /* make sure PCI base addr 1 is MMIO */ |
|
3068 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
3069 netif_err(tp, probe, dev, |
|
3070 "region #%d not an MMIO resource, aborting\n", |
|
3071 region); |
|
3072 rc = -ENODEV; |
|
3073 goto err_out_mwi_2; |
|
3074 } |
|
3075 |
|
3076 /* check for weird/broken PCI region reporting */ |
|
3077 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
3078 netif_err(tp, probe, dev, |
|
3079 "Invalid PCI region size(s), aborting\n"); |
|
3080 rc = -ENODEV; |
|
3081 goto err_out_mwi_2; |
|
3082 } |
|
3083 |
|
3084 rc = pci_request_regions(pdev, MODULENAME); |
|
3085 if (rc < 0) { |
|
3086 netif_err(tp, probe, dev, "could not request regions\n"); |
|
3087 goto err_out_mwi_2; |
|
3088 } |
|
3089 |
|
3090 tp->cp_cmd = PCIMulRW | RxChkSum; |
|
3091 |
|
3092 if ((sizeof(dma_addr_t) > 4) && |
|
3093 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
3094 tp->cp_cmd |= PCIDAC; |
|
3095 dev->features |= NETIF_F_HIGHDMA; |
|
3096 } else { |
|
3097 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
3098 if (rc < 0) { |
|
3099 netif_err(tp, probe, dev, "DMA configuration failed\n"); |
|
3100 goto err_out_free_res_3; |
|
3101 } |
|
3102 } |
|
3103 |
|
3104 /* ioremap MMIO region */ |
|
3105 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
3106 if (!ioaddr) { |
|
3107 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
|
3108 rc = -EIO; |
|
3109 goto err_out_free_res_3; |
|
3110 } |
|
3111 |
|
3112 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
|
3113 if (!tp->pcie_cap) |
|
3114 netif_info(tp, probe, dev, "no PCI Express capability\n"); |
|
3115 |
|
3116 RTL_W16(IntrMask, 0x0000); |
|
3117 |
|
3118 /* Soft reset the chip. */ |
|
3119 RTL_W8(ChipCmd, CmdReset); |
|
3120 |
|
3121 /* Check that the chip has finished the reset. */ |
|
3122 for (i = 0; i < 100; i++) { |
|
3123 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3124 break; |
|
3125 msleep_interruptible(1); |
|
3126 } |
|
3127 |
|
3128 RTL_W16(IntrStatus, 0xffff); |
|
3129 |
|
3130 pci_set_master(pdev); |
|
3131 |
|
3132 /* Identify chip attached to board */ |
|
3133 rtl8169_get_mac_version(tp, ioaddr); |
|
3134 |
|
3135 /* Use appropriate default if unknown */ |
|
3136 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
3137 netif_notice(tp, probe, dev, |
|
3138 "unknown MAC, using family default\n"); |
|
3139 tp->mac_version = cfg->default_ver; |
|
3140 } |
|
3141 |
|
3142 rtl8169_print_mac_version(tp); |
|
3143 |
|
3144 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
|
3145 if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
3146 break; |
|
3147 } |
|
3148 if (i == ARRAY_SIZE(rtl_chip_info)) { |
|
3149 dev_err(&pdev->dev, |
|
3150 "driver bug, MAC version not found in rtl_chip_info\n"); |
|
3151 goto err_out_msi_4; |
|
3152 } |
|
3153 tp->chipset = i; |
|
3154 |
|
3155 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3156 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
3157 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
3158 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
3159 tp->features |= RTL_FEATURE_WOL; |
|
3160 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
3161 tp->features |= RTL_FEATURE_WOL; |
|
3162 tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
|
3163 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3164 |
|
3165 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
|
3166 (RTL_R8(PHYstatus) & TBI_Enable)) { |
|
3167 tp->set_speed = rtl8169_set_speed_tbi; |
|
3168 tp->get_settings = rtl8169_gset_tbi; |
|
3169 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
3170 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
3171 tp->link_ok = rtl8169_tbi_link_ok; |
|
3172 tp->do_ioctl = rtl_tbi_ioctl; |
|
3173 |
|
3174 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
3175 } else { |
|
3176 tp->set_speed = rtl8169_set_speed_xmii; |
|
3177 tp->get_settings = rtl8169_gset_xmii; |
|
3178 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
3179 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
3180 tp->link_ok = rtl8169_xmii_link_ok; |
|
3181 tp->do_ioctl = rtl_xmii_ioctl; |
|
3182 } |
|
3183 |
|
3184 spin_lock_init(&tp->lock); |
|
3185 |
|
3186 tp->mmio_addr = ioaddr; |
|
3187 |
|
3188 /* Get MAC address */ |
|
3189 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
3190 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
3191 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
3192 |
|
3193 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
3194 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
3195 dev->irq = pdev->irq; |
|
3196 dev->base_addr = (unsigned long) ioaddr; |
|
3197 |
|
3198 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
3199 |
|
3200 #ifdef CONFIG_R8169_VLAN |
|
3201 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
3202 #endif |
|
3203 dev->features |= NETIF_F_GRO; |
|
3204 |
|
3205 tp->intr_mask = 0xffff; |
|
3206 tp->hw_start = cfg->hw_start; |
|
3207 tp->intr_event = cfg->intr_event; |
|
3208 tp->napi_event = cfg->napi_event; |
|
3209 |
|
3210 init_timer(&tp->timer); |
|
3211 tp->timer.data = (unsigned long) dev; |
|
3212 tp->timer.function = rtl8169_phy_timer; |
|
3213 |
|
3214 rc = register_netdev(dev); |
|
3215 if (rc < 0) |
|
3216 goto err_out_msi_4; |
|
3217 |
|
3218 pci_set_drvdata(pdev, dev); |
|
3219 |
|
3220 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
|
3221 rtl_chip_info[tp->chipset].name, |
|
3222 dev->base_addr, dev->dev_addr, |
|
3223 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); |
|
3224 |
|
3225 rtl8169_init_phy(dev, tp); |
|
3226 |
|
3227 /* |
|
3228 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
3229 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
3230 */ |
|
3231 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
3232 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan); |
|
3233 |
|
3234 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
3235 |
|
3236 if (pci_dev_run_wake(pdev)) |
|
3237 pm_runtime_put_noidle(&pdev->dev); |
|
3238 |
|
3239 netif_carrier_off(dev); |
|
3240 |
|
3241 out: |
|
3242 return rc; |
|
3243 |
|
3244 err_out_msi_4: |
|
3245 rtl_disable_msi(pdev, tp); |
|
3246 iounmap(ioaddr); |
|
3247 err_out_free_res_3: |
|
3248 pci_release_regions(pdev); |
|
3249 err_out_mwi_2: |
|
3250 pci_clear_mwi(pdev); |
|
3251 pci_disable_device(pdev); |
|
3252 err_out_free_dev_1: |
|
3253 free_netdev(dev); |
|
3254 goto out; |
|
3255 } |
|
3256 |
|
3257 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
3258 { |
|
3259 struct net_device *dev = pci_get_drvdata(pdev); |
|
3260 struct rtl8169_private *tp = netdev_priv(dev); |
|
3261 |
|
3262 flush_scheduled_work(); |
|
3263 |
|
3264 unregister_netdev(dev); |
|
3265 |
|
3266 if (pci_dev_run_wake(pdev)) |
|
3267 pm_runtime_get_noresume(&pdev->dev); |
|
3268 |
|
3269 /* restore original MAC address */ |
|
3270 rtl_rar_set(tp, dev->perm_addr); |
|
3271 |
|
3272 rtl_disable_msi(pdev, tp); |
|
3273 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
3274 pci_set_drvdata(pdev, NULL); |
|
3275 } |
|
3276 |
|
3277 static int rtl8169_open(struct net_device *dev) |
|
3278 { |
|
3279 struct rtl8169_private *tp = netdev_priv(dev); |
|
3280 struct pci_dev *pdev = tp->pci_dev; |
|
3281 int retval = -ENOMEM; |
|
3282 |
|
3283 pm_runtime_get_sync(&pdev->dev); |
|
3284 |
|
3285 /* |
|
3286 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
3287 * dma_alloc_coherent provides more. |
|
3288 */ |
|
3289 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
|
3290 &tp->TxPhyAddr, GFP_KERNEL); |
|
3291 if (!tp->TxDescArray) |
|
3292 goto err_pm_runtime_put; |
|
3293 |
|
3294 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
|
3295 &tp->RxPhyAddr, GFP_KERNEL); |
|
3296 if (!tp->RxDescArray) |
|
3297 goto err_free_tx_0; |
|
3298 |
|
3299 retval = rtl8169_init_ring(dev); |
|
3300 if (retval < 0) |
|
3301 goto err_free_rx_1; |
|
3302 |
|
3303 INIT_DELAYED_WORK(&tp->task, NULL); |
|
3304 |
|
3305 smp_mb(); |
|
3306 |
|
3307 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
3308 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
3309 dev->name, dev); |
|
3310 if (retval < 0) |
|
3311 goto err_release_ring_2; |
|
3312 |
|
3313 napi_enable(&tp->napi); |
|
3314 |
|
3315 rtl_hw_start(dev); |
|
3316 |
|
3317 rtl8169_request_timer(dev); |
|
3318 |
|
3319 tp->saved_wolopts = 0; |
|
3320 pm_runtime_put_noidle(&pdev->dev); |
|
3321 |
|
3322 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
3323 out: |
|
3324 return retval; |
|
3325 |
|
3326 err_release_ring_2: |
|
3327 rtl8169_rx_clear(tp); |
|
3328 err_free_rx_1: |
|
3329 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3330 tp->RxPhyAddr); |
|
3331 tp->RxDescArray = NULL; |
|
3332 err_free_tx_0: |
|
3333 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3334 tp->TxPhyAddr); |
|
3335 tp->TxDescArray = NULL; |
|
3336 err_pm_runtime_put: |
|
3337 pm_runtime_put_noidle(&pdev->dev); |
|
3338 goto out; |
|
3339 } |
|
3340 |
|
3341 static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
3342 { |
|
3343 /* Disable interrupts */ |
|
3344 rtl8169_irq_mask_and_ack(ioaddr); |
|
3345 |
|
3346 /* Reset the chipset */ |
|
3347 RTL_W8(ChipCmd, CmdReset); |
|
3348 |
|
3349 /* PCI commit */ |
|
3350 RTL_R8(ChipCmd); |
|
3351 } |
|
3352 |
|
3353 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
3354 { |
|
3355 void __iomem *ioaddr = tp->mmio_addr; |
|
3356 u32 cfg = rtl8169_rx_config; |
|
3357 |
|
3358 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3359 RTL_W32(RxConfig, cfg); |
|
3360 |
|
3361 /* Set DMA burst size and Interframe Gap Time */ |
|
3362 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
3363 (InterFrameGap << TxInterFrameGapShift)); |
|
3364 } |
|
3365 |
|
3366 static void rtl_hw_start(struct net_device *dev) |
|
3367 { |
|
3368 struct rtl8169_private *tp = netdev_priv(dev); |
|
3369 void __iomem *ioaddr = tp->mmio_addr; |
|
3370 unsigned int i; |
|
3371 |
|
3372 /* Soft reset the chip. */ |
|
3373 RTL_W8(ChipCmd, CmdReset); |
|
3374 |
|
3375 /* Check that the chip has finished the reset. */ |
|
3376 for (i = 0; i < 100; i++) { |
|
3377 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3378 break; |
|
3379 msleep_interruptible(1); |
|
3380 } |
|
3381 |
|
3382 tp->hw_start(dev); |
|
3383 |
|
3384 netif_start_queue(dev); |
|
3385 } |
|
3386 |
|
3387 |
|
3388 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
3389 void __iomem *ioaddr) |
|
3390 { |
|
3391 /* |
|
3392 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
3393 * register to be written before TxDescAddrLow to work. |
|
3394 * Switching from MMIO to I/O access fixes the issue as well. |
|
3395 */ |
|
3396 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
3397 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
3398 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
3399 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
3400 } |
|
3401 |
|
3402 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
3403 { |
|
3404 u16 cmd; |
|
3405 |
|
3406 cmd = RTL_R16(CPlusCmd); |
|
3407 RTL_W16(CPlusCmd, cmd); |
|
3408 return cmd; |
|
3409 } |
|
3410 |
|
3411 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
3412 { |
|
3413 /* Low hurts. Let's disable the filtering. */ |
|
3414 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
3415 } |
|
3416 |
|
3417 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
3418 { |
|
3419 static const struct { |
|
3420 u32 mac_version; |
|
3421 u32 clk; |
|
3422 u32 val; |
|
3423 } cfg2_info [] = { |
|
3424 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
3425 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
3426 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
3427 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
3428 }, *p = cfg2_info; |
|
3429 unsigned int i; |
|
3430 u32 clk; |
|
3431 |
|
3432 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
3433 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
3434 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
3435 RTL_W32(0x7c, p->val); |
|
3436 break; |
|
3437 } |
|
3438 } |
|
3439 } |
|
3440 |
|
3441 static void rtl_hw_start_8169(struct net_device *dev) |
|
3442 { |
|
3443 struct rtl8169_private *tp = netdev_priv(dev); |
|
3444 void __iomem *ioaddr = tp->mmio_addr; |
|
3445 struct pci_dev *pdev = tp->pci_dev; |
|
3446 |
|
3447 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
3448 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
3449 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3450 } |
|
3451 |
|
3452 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3453 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
3454 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3455 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
3456 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
3457 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3458 |
|
3459 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3460 |
|
3461 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
3462 |
|
3463 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
3464 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3465 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
3466 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
3467 rtl_set_rx_tx_config_registers(tp); |
|
3468 |
|
3469 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
3470 |
|
3471 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3472 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
3473 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
3474 "Bit-3 and bit-14 MUST be 1\n"); |
|
3475 tp->cp_cmd |= (1 << 14); |
|
3476 } |
|
3477 |
|
3478 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3479 |
|
3480 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
3481 |
|
3482 /* |
|
3483 * Undocumented corner. Supposedly: |
|
3484 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
3485 */ |
|
3486 RTL_W16(IntrMitigate, 0x0000); |
|
3487 |
|
3488 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3489 |
|
3490 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
|
3491 (tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
3492 (tp->mac_version != RTL_GIGA_MAC_VER_03) && |
|
3493 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { |
|
3494 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3495 rtl_set_rx_tx_config_registers(tp); |
|
3496 } |
|
3497 |
|
3498 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3499 |
|
3500 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
3501 RTL_R8(IntrMask); |
|
3502 |
|
3503 RTL_W32(RxMissed, 0); |
|
3504 |
|
3505 rtl_set_rx_mode(dev); |
|
3506 |
|
3507 /* no early-rx interrupts */ |
|
3508 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
3509 |
|
3510 /* Enable all known interrupts by setting the interrupt mask. */ |
|
3511 RTL_W16(IntrMask, tp->intr_event); |
|
3512 } |
|
3513 |
|
3514 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
3515 { |
|
3516 struct net_device *dev = pci_get_drvdata(pdev); |
|
3517 struct rtl8169_private *tp = netdev_priv(dev); |
|
3518 int cap = tp->pcie_cap; |
|
3519 |
|
3520 if (cap) { |
|
3521 u16 ctl; |
|
3522 |
|
3523 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
3524 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
3525 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
3526 } |
|
3527 } |
|
3528 |
|
3529 static void rtl_csi_access_enable(void __iomem *ioaddr) |
|
3530 { |
|
3531 u32 csi; |
|
3532 |
|
3533 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
3534 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); |
|
3535 } |
|
3536 |
|
3537 struct ephy_info { |
|
3538 unsigned int offset; |
|
3539 u16 mask; |
|
3540 u16 bits; |
|
3541 }; |
|
3542 |
|
3543 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
|
3544 { |
|
3545 u16 w; |
|
3546 |
|
3547 while (len-- > 0) { |
|
3548 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
3549 rtl_ephy_write(ioaddr, e->offset, w); |
|
3550 e++; |
|
3551 } |
|
3552 } |
|
3553 |
|
3554 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
3555 { |
|
3556 struct net_device *dev = pci_get_drvdata(pdev); |
|
3557 struct rtl8169_private *tp = netdev_priv(dev); |
|
3558 int cap = tp->pcie_cap; |
|
3559 |
|
3560 if (cap) { |
|
3561 u16 ctl; |
|
3562 |
|
3563 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
3564 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
3565 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
3566 } |
|
3567 } |
|
3568 |
|
3569 #define R8168_CPCMD_QUIRK_MASK (\ |
|
3570 EnableBist | \ |
|
3571 Mac_dbgo_oe | \ |
|
3572 Force_half_dup | \ |
|
3573 Force_rxflow_en | \ |
|
3574 Force_txflow_en | \ |
|
3575 Cxpl_dbg_sel | \ |
|
3576 ASF | \ |
|
3577 PktCntrDisable | \ |
|
3578 Mac_dbgo_sel) |
|
3579 |
|
3580 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3581 { |
|
3582 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3583 |
|
3584 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3585 |
|
3586 rtl_tx_performance_tweak(pdev, |
|
3587 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3588 } |
|
3589 |
|
3590 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3591 { |
|
3592 rtl_hw_start_8168bb(ioaddr, pdev); |
|
3593 |
|
3594 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3595 |
|
3596 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
3597 } |
|
3598 |
|
3599 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3600 { |
|
3601 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
3602 |
|
3603 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3604 |
|
3605 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3606 |
|
3607 rtl_disable_clock_request(pdev); |
|
3608 |
|
3609 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3610 } |
|
3611 |
|
3612 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3613 { |
|
3614 static const struct ephy_info e_info_8168cp[] = { |
|
3615 { 0x01, 0, 0x0001 }, |
|
3616 { 0x02, 0x0800, 0x1000 }, |
|
3617 { 0x03, 0, 0x0042 }, |
|
3618 { 0x06, 0x0080, 0x0000 }, |
|
3619 { 0x07, 0, 0x2000 } |
|
3620 }; |
|
3621 |
|
3622 rtl_csi_access_enable(ioaddr); |
|
3623 |
|
3624 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
3625 |
|
3626 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3627 } |
|
3628 |
|
3629 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3630 { |
|
3631 rtl_csi_access_enable(ioaddr); |
|
3632 |
|
3633 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3634 |
|
3635 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3636 |
|
3637 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3638 } |
|
3639 |
|
3640 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3641 { |
|
3642 rtl_csi_access_enable(ioaddr); |
|
3643 |
|
3644 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3645 |
|
3646 /* Magic. */ |
|
3647 RTL_W8(DBG_REG, 0x20); |
|
3648 |
|
3649 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3650 |
|
3651 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3652 |
|
3653 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3654 } |
|
3655 |
|
3656 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3657 { |
|
3658 static const struct ephy_info e_info_8168c_1[] = { |
|
3659 { 0x02, 0x0800, 0x1000 }, |
|
3660 { 0x03, 0, 0x0002 }, |
|
3661 { 0x06, 0x0080, 0x0000 } |
|
3662 }; |
|
3663 |
|
3664 rtl_csi_access_enable(ioaddr); |
|
3665 |
|
3666 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
3667 |
|
3668 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
3669 |
|
3670 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3671 } |
|
3672 |
|
3673 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3674 { |
|
3675 static const struct ephy_info e_info_8168c_2[] = { |
|
3676 { 0x01, 0, 0x0001 }, |
|
3677 { 0x03, 0x0400, 0x0220 } |
|
3678 }; |
|
3679 |
|
3680 rtl_csi_access_enable(ioaddr); |
|
3681 |
|
3682 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
3683 |
|
3684 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3685 } |
|
3686 |
|
3687 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3688 { |
|
3689 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
3690 } |
|
3691 |
|
3692 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3693 { |
|
3694 rtl_csi_access_enable(ioaddr); |
|
3695 |
|
3696 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3697 } |
|
3698 |
|
3699 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3700 { |
|
3701 rtl_csi_access_enable(ioaddr); |
|
3702 |
|
3703 rtl_disable_clock_request(pdev); |
|
3704 |
|
3705 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3706 |
|
3707 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3708 |
|
3709 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3710 } |
|
3711 |
|
3712 static void rtl_hw_start_8168(struct net_device *dev) |
|
3713 { |
|
3714 struct rtl8169_private *tp = netdev_priv(dev); |
|
3715 void __iomem *ioaddr = tp->mmio_addr; |
|
3716 struct pci_dev *pdev = tp->pci_dev; |
|
3717 |
|
3718 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3719 |
|
3720 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3721 |
|
3722 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
3723 |
|
3724 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
3725 |
|
3726 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3727 |
|
3728 RTL_W16(IntrMitigate, 0x5151); |
|
3729 |
|
3730 /* Work around for RxFIFO overflow. */ |
|
3731 if (tp->mac_version == RTL_GIGA_MAC_VER_11 || |
|
3732 tp->mac_version == RTL_GIGA_MAC_VER_22) { |
|
3733 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
3734 tp->intr_event &= ~RxOverflow; |
|
3735 } |
|
3736 |
|
3737 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3738 |
|
3739 rtl_set_rx_mode(dev); |
|
3740 |
|
3741 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
3742 (InterFrameGap << TxInterFrameGapShift)); |
|
3743 |
|
3744 RTL_R8(IntrMask); |
|
3745 |
|
3746 switch (tp->mac_version) { |
|
3747 case RTL_GIGA_MAC_VER_11: |
|
3748 rtl_hw_start_8168bb(ioaddr, pdev); |
|
3749 break; |
|
3750 |
|
3751 case RTL_GIGA_MAC_VER_12: |
|
3752 case RTL_GIGA_MAC_VER_17: |
|
3753 rtl_hw_start_8168bef(ioaddr, pdev); |
|
3754 break; |
|
3755 |
|
3756 case RTL_GIGA_MAC_VER_18: |
|
3757 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
3758 break; |
|
3759 |
|
3760 case RTL_GIGA_MAC_VER_19: |
|
3761 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
3762 break; |
|
3763 |
|
3764 case RTL_GIGA_MAC_VER_20: |
|
3765 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
3766 break; |
|
3767 |
|
3768 case RTL_GIGA_MAC_VER_21: |
|
3769 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
3770 break; |
|
3771 |
|
3772 case RTL_GIGA_MAC_VER_22: |
|
3773 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
3774 break; |
|
3775 |
|
3776 case RTL_GIGA_MAC_VER_23: |
|
3777 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
3778 break; |
|
3779 |
|
3780 case RTL_GIGA_MAC_VER_24: |
|
3781 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
3782 break; |
|
3783 |
|
3784 case RTL_GIGA_MAC_VER_25: |
|
3785 case RTL_GIGA_MAC_VER_26: |
|
3786 case RTL_GIGA_MAC_VER_27: |
|
3787 rtl_hw_start_8168d(ioaddr, pdev); |
|
3788 break; |
|
3789 |
|
3790 default: |
|
3791 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
3792 dev->name, tp->mac_version); |
|
3793 break; |
|
3794 } |
|
3795 |
|
3796 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3797 |
|
3798 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3799 |
|
3800 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
3801 |
|
3802 RTL_W16(IntrMask, tp->intr_event); |
|
3803 } |
|
3804 |
|
3805 #define R810X_CPCMD_QUIRK_MASK (\ |
|
3806 EnableBist | \ |
|
3807 Mac_dbgo_oe | \ |
|
3808 Force_half_dup | \ |
|
3809 Force_rxflow_en | \ |
|
3810 Force_txflow_en | \ |
|
3811 Cxpl_dbg_sel | \ |
|
3812 ASF | \ |
|
3813 PktCntrDisable | \ |
|
3814 PCIDAC | \ |
|
3815 PCIMulRW) |
|
3816 |
|
3817 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3818 { |
|
3819 static const struct ephy_info e_info_8102e_1[] = { |
|
3820 { 0x01, 0, 0x6e65 }, |
|
3821 { 0x02, 0, 0x091f }, |
|
3822 { 0x03, 0, 0xc2f9 }, |
|
3823 { 0x06, 0, 0xafb5 }, |
|
3824 { 0x07, 0, 0x0e00 }, |
|
3825 { 0x19, 0, 0xec80 }, |
|
3826 { 0x01, 0, 0x2e65 }, |
|
3827 { 0x01, 0, 0x6e65 } |
|
3828 }; |
|
3829 u8 cfg1; |
|
3830 |
|
3831 rtl_csi_access_enable(ioaddr); |
|
3832 |
|
3833 RTL_W8(DBG_REG, FIX_NAK_1); |
|
3834 |
|
3835 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3836 |
|
3837 RTL_W8(Config1, |
|
3838 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
3839 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3840 |
|
3841 cfg1 = RTL_R8(Config1); |
|
3842 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
3843 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
3844 |
|
3845 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
3846 |
|
3847 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
3848 } |
|
3849 |
|
3850 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3851 { |
|
3852 rtl_csi_access_enable(ioaddr); |
|
3853 |
|
3854 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3855 |
|
3856 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
3857 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3858 |
|
3859 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
3860 } |
|
3861 |
|
3862 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3863 { |
|
3864 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
3865 |
|
3866 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
3867 } |
|
3868 |
|
3869 static void rtl_hw_start_8101(struct net_device *dev) |
|
3870 { |
|
3871 struct rtl8169_private *tp = netdev_priv(dev); |
|
3872 void __iomem *ioaddr = tp->mmio_addr; |
|
3873 struct pci_dev *pdev = tp->pci_dev; |
|
3874 |
|
3875 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
3876 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { |
|
3877 int cap = tp->pcie_cap; |
|
3878 |
|
3879 if (cap) { |
|
3880 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
3881 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3882 } |
|
3883 } |
|
3884 |
|
3885 switch (tp->mac_version) { |
|
3886 case RTL_GIGA_MAC_VER_07: |
|
3887 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
3888 break; |
|
3889 |
|
3890 case RTL_GIGA_MAC_VER_08: |
|
3891 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
3892 break; |
|
3893 |
|
3894 case RTL_GIGA_MAC_VER_09: |
|
3895 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
3896 break; |
|
3897 } |
|
3898 |
|
3899 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3900 |
|
3901 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3902 |
|
3903 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
3904 |
|
3905 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
3906 |
|
3907 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3908 |
|
3909 RTL_W16(IntrMitigate, 0x0000); |
|
3910 |
|
3911 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3912 |
|
3913 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3914 rtl_set_rx_tx_config_registers(tp); |
|
3915 |
|
3916 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3917 |
|
3918 RTL_R8(IntrMask); |
|
3919 |
|
3920 rtl_set_rx_mode(dev); |
|
3921 |
|
3922 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3923 |
|
3924 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
3925 |
|
3926 RTL_W16(IntrMask, tp->intr_event); |
|
3927 } |
|
3928 |
|
3929 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
3930 { |
|
3931 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
3932 return -EINVAL; |
|
3933 |
|
3934 dev->mtu = new_mtu; |
|
3935 return 0; |
|
3936 } |
|
3937 |
|
3938 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
3939 { |
|
3940 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
3941 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
3942 } |
|
3943 |
|
3944 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
|
3945 void **data_buff, struct RxDesc *desc) |
|
3946 { |
|
3947 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
|
3948 DMA_FROM_DEVICE); |
|
3949 |
|
3950 kfree(*data_buff); |
|
3951 *data_buff = NULL; |
|
3952 rtl8169_make_unusable_by_asic(desc); |
|
3953 } |
|
3954 |
|
3955 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
3956 { |
|
3957 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
3958 |
|
3959 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
3960 } |
|
3961 |
|
3962 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
3963 u32 rx_buf_sz) |
|
3964 { |
|
3965 desc->addr = cpu_to_le64(mapping); |
|
3966 wmb(); |
|
3967 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
3968 } |
|
3969 |
|
3970 static inline void *rtl8169_align(void *data) |
|
3971 { |
|
3972 return (void *)ALIGN((long)data, 16); |
|
3973 } |
|
3974 |
|
3975 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
|
3976 struct RxDesc *desc) |
|
3977 { |
|
3978 void *data; |
|
3979 dma_addr_t mapping; |
|
3980 struct device *d = &tp->pci_dev->dev; |
|
3981 struct net_device *dev = tp->dev; |
|
3982 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
|
3983 |
|
3984 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
|
3985 if (!data) |
|
3986 return NULL; |
|
3987 |
|
3988 if (rtl8169_align(data) != data) { |
|
3989 kfree(data); |
|
3990 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); |
|
3991 if (!data) |
|
3992 return NULL; |
|
3993 } |
|
3994 |
|
3995 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
|
3996 DMA_FROM_DEVICE); |
|
3997 if (unlikely(dma_mapping_error(d, mapping))) { |
|
3998 if (net_ratelimit()) |
|
3999 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); |
|
4000 goto err_out; |
|
4001 } |
|
4002 |
|
4003 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
4004 return data; |
|
4005 |
|
4006 err_out: |
|
4007 kfree(data); |
|
4008 return NULL; |
|
4009 } |
|
4010 |
|
4011 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
4012 { |
|
4013 unsigned int i; |
|
4014 |
|
4015 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4016 if (tp->Rx_databuff[i]) { |
|
4017 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, |
|
4018 tp->RxDescArray + i); |
|
4019 } |
|
4020 } |
|
4021 } |
|
4022 |
|
4023 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
4024 { |
|
4025 desc->opts1 |= cpu_to_le32(RingEnd); |
|
4026 } |
|
4027 |
|
4028 static int rtl8169_rx_fill(struct rtl8169_private *tp) |
|
4029 { |
|
4030 unsigned int i; |
|
4031 |
|
4032 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4033 void *data; |
|
4034 |
|
4035 if (tp->Rx_databuff[i]) |
|
4036 continue; |
|
4037 |
|
4038 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
|
4039 if (!data) { |
|
4040 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); |
|
4041 goto err_out; |
|
4042 } |
|
4043 tp->Rx_databuff[i] = data; |
|
4044 } |
|
4045 |
|
4046 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
4047 return 0; |
|
4048 |
|
4049 err_out: |
|
4050 rtl8169_rx_clear(tp); |
|
4051 return -ENOMEM; |
|
4052 } |
|
4053 |
|
4054 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
4055 { |
|
4056 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
4057 } |
|
4058 |
|
4059 static int rtl8169_init_ring(struct net_device *dev) |
|
4060 { |
|
4061 struct rtl8169_private *tp = netdev_priv(dev); |
|
4062 |
|
4063 rtl8169_init_ring_indexes(tp); |
|
4064 |
|
4065 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
4066 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
|
4067 |
|
4068 return rtl8169_rx_fill(tp); |
|
4069 } |
|
4070 |
|
4071 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
|
4072 struct TxDesc *desc) |
|
4073 { |
|
4074 unsigned int len = tx_skb->len; |
|
4075 |
|
4076 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
|
4077 |
|
4078 desc->opts1 = 0x00; |
|
4079 desc->opts2 = 0x00; |
|
4080 desc->addr = 0x00; |
|
4081 tx_skb->len = 0; |
|
4082 } |
|
4083 |
|
4084 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
|
4085 unsigned int n) |
|
4086 { |
|
4087 unsigned int i; |
|
4088 |
|
4089 for (i = 0; i < n; i++) { |
|
4090 unsigned int entry = (start + i) % NUM_TX_DESC; |
|
4091 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
4092 unsigned int len = tx_skb->len; |
|
4093 |
|
4094 if (len) { |
|
4095 struct sk_buff *skb = tx_skb->skb; |
|
4096 |
|
4097 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
4098 tp->TxDescArray + entry); |
|
4099 if (skb) { |
|
4100 tp->dev->stats.tx_dropped++; |
|
4101 dev_kfree_skb(skb); |
|
4102 tx_skb->skb = NULL; |
|
4103 } |
|
4104 } |
|
4105 } |
|
4106 } |
|
4107 |
|
4108 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
4109 { |
|
4110 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); |
|
4111 tp->cur_tx = tp->dirty_tx = 0; |
|
4112 } |
|
4113 |
|
4114 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
4115 { |
|
4116 struct rtl8169_private *tp = netdev_priv(dev); |
|
4117 |
|
4118 PREPARE_DELAYED_WORK(&tp->task, task); |
|
4119 schedule_delayed_work(&tp->task, 4); |
|
4120 } |
|
4121 |
|
4122 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
4123 { |
|
4124 struct rtl8169_private *tp = netdev_priv(dev); |
|
4125 void __iomem *ioaddr = tp->mmio_addr; |
|
4126 |
|
4127 synchronize_irq(dev->irq); |
|
4128 |
|
4129 /* Wait for any pending NAPI task to complete */ |
|
4130 napi_disable(&tp->napi); |
|
4131 |
|
4132 rtl8169_irq_mask_and_ack(ioaddr); |
|
4133 |
|
4134 tp->intr_mask = 0xffff; |
|
4135 RTL_W16(IntrMask, tp->intr_event); |
|
4136 napi_enable(&tp->napi); |
|
4137 } |
|
4138 |
|
4139 static void rtl8169_reinit_task(struct work_struct *work) |
|
4140 { |
|
4141 struct rtl8169_private *tp = |
|
4142 container_of(work, struct rtl8169_private, task.work); |
|
4143 struct net_device *dev = tp->dev; |
|
4144 int ret; |
|
4145 |
|
4146 rtnl_lock(); |
|
4147 |
|
4148 if (!netif_running(dev)) |
|
4149 goto out_unlock; |
|
4150 |
|
4151 rtl8169_wait_for_quiescence(dev); |
|
4152 rtl8169_close(dev); |
|
4153 |
|
4154 ret = rtl8169_open(dev); |
|
4155 if (unlikely(ret < 0)) { |
|
4156 if (net_ratelimit()) |
|
4157 netif_err(tp, drv, dev, |
|
4158 "reinit failure (status = %d). Rescheduling\n", |
|
4159 ret); |
|
4160 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
4161 } |
|
4162 |
|
4163 out_unlock: |
|
4164 rtnl_unlock(); |
|
4165 } |
|
4166 |
|
4167 static void rtl8169_reset_task(struct work_struct *work) |
|
4168 { |
|
4169 struct rtl8169_private *tp = |
|
4170 container_of(work, struct rtl8169_private, task.work); |
|
4171 struct net_device *dev = tp->dev; |
|
4172 |
|
4173 rtnl_lock(); |
|
4174 |
|
4175 if (!netif_running(dev)) |
|
4176 goto out_unlock; |
|
4177 |
|
4178 rtl8169_wait_for_quiescence(dev); |
|
4179 |
|
4180 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
|
4181 rtl8169_tx_clear(tp); |
|
4182 |
|
4183 if (tp->dirty_rx == tp->cur_rx) { |
|
4184 rtl8169_init_ring_indexes(tp); |
|
4185 rtl_hw_start(dev); |
|
4186 netif_wake_queue(dev); |
|
4187 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
4188 } else { |
|
4189 if (net_ratelimit()) |
|
4190 netif_emerg(tp, intr, dev, "Rx buffers shortage\n"); |
|
4191 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4192 } |
|
4193 |
|
4194 out_unlock: |
|
4195 rtnl_unlock(); |
|
4196 } |
|
4197 |
|
4198 static void rtl8169_tx_timeout(struct net_device *dev) |
|
4199 { |
|
4200 struct rtl8169_private *tp = netdev_priv(dev); |
|
4201 |
|
4202 rtl8169_hw_reset(tp->mmio_addr); |
|
4203 |
|
4204 /* Let's wait a bit while any (async) irq lands on */ |
|
4205 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4206 } |
|
4207 |
|
4208 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
4209 u32 opts1) |
|
4210 { |
|
4211 struct skb_shared_info *info = skb_shinfo(skb); |
|
4212 unsigned int cur_frag, entry; |
|
4213 struct TxDesc * uninitialized_var(txd); |
|
4214 struct device *d = &tp->pci_dev->dev; |
|
4215 |
|
4216 entry = tp->cur_tx; |
|
4217 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
4218 skb_frag_t *frag = info->frags + cur_frag; |
|
4219 dma_addr_t mapping; |
|
4220 u32 status, len; |
|
4221 void *addr; |
|
4222 |
|
4223 entry = (entry + 1) % NUM_TX_DESC; |
|
4224 |
|
4225 txd = tp->TxDescArray + entry; |
|
4226 len = frag->size; |
|
4227 addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
4228 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
|
4229 if (unlikely(dma_mapping_error(d, mapping))) { |
|
4230 if (net_ratelimit()) |
|
4231 netif_err(tp, drv, tp->dev, |
|
4232 "Failed to map TX fragments DMA!\n"); |
|
4233 goto err_out; |
|
4234 } |
|
4235 |
|
4236 /* anti gcc 2.95.3 bugware (sic) */ |
|
4237 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
4238 |
|
4239 txd->opts1 = cpu_to_le32(status); |
|
4240 txd->addr = cpu_to_le64(mapping); |
|
4241 |
|
4242 tp->tx_skb[entry].len = len; |
|
4243 } |
|
4244 |
|
4245 if (cur_frag) { |
|
4246 tp->tx_skb[entry].skb = skb; |
|
4247 txd->opts1 |= cpu_to_le32(LastFrag); |
|
4248 } |
|
4249 |
|
4250 return cur_frag; |
|
4251 |
|
4252 err_out: |
|
4253 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); |
|
4254 return -EIO; |
|
4255 } |
|
4256 |
|
4257 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
4258 { |
|
4259 if (dev->features & NETIF_F_TSO) { |
|
4260 u32 mss = skb_shinfo(skb)->gso_size; |
|
4261 |
|
4262 if (mss) |
|
4263 return LargeSend | ((mss & MSSMask) << MSSShift); |
|
4264 } |
|
4265 if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
4266 const struct iphdr *ip = ip_hdr(skb); |
|
4267 |
|
4268 if (ip->protocol == IPPROTO_TCP) |
|
4269 return IPCS | TCPCS; |
|
4270 else if (ip->protocol == IPPROTO_UDP) |
|
4271 return IPCS | UDPCS; |
|
4272 WARN_ON(1); /* we need a WARN() */ |
|
4273 } |
|
4274 return 0; |
|
4275 } |
|
4276 |
|
4277 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
4278 struct net_device *dev) |
|
4279 { |
|
4280 struct rtl8169_private *tp = netdev_priv(dev); |
|
4281 unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
|
4282 struct TxDesc *txd = tp->TxDescArray + entry; |
|
4283 void __iomem *ioaddr = tp->mmio_addr; |
|
4284 struct device *d = &tp->pci_dev->dev; |
|
4285 dma_addr_t mapping; |
|
4286 u32 status, len; |
|
4287 u32 opts1; |
|
4288 int frags; |
|
4289 |
|
4290 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
4291 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
|
4292 goto err_stop_0; |
|
4293 } |
|
4294 |
|
4295 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
4296 goto err_stop_0; |
|
4297 |
|
4298 len = skb_headlen(skb); |
|
4299 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
|
4300 if (unlikely(dma_mapping_error(d, mapping))) { |
|
4301 if (net_ratelimit()) |
|
4302 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); |
|
4303 goto err_dma_0; |
|
4304 } |
|
4305 |
|
4306 tp->tx_skb[entry].len = len; |
|
4307 txd->addr = cpu_to_le64(mapping); |
|
4308 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
4309 |
|
4310 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
4311 |
|
4312 frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
4313 if (frags < 0) |
|
4314 goto err_dma_1; |
|
4315 else if (frags) |
|
4316 opts1 |= FirstFrag; |
|
4317 else { |
|
4318 opts1 |= FirstFrag | LastFrag; |
|
4319 tp->tx_skb[entry].skb = skb; |
|
4320 } |
|
4321 |
|
4322 wmb(); |
|
4323 |
|
4324 /* anti gcc 2.95.3 bugware (sic) */ |
|
4325 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
4326 txd->opts1 = cpu_to_le32(status); |
|
4327 |
|
4328 tp->cur_tx += frags + 1; |
|
4329 |
|
4330 wmb(); |
|
4331 |
|
4332 RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
4333 |
|
4334 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
4335 netif_stop_queue(dev); |
|
4336 smp_rmb(); |
|
4337 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
4338 netif_wake_queue(dev); |
|
4339 } |
|
4340 |
|
4341 return NETDEV_TX_OK; |
|
4342 |
|
4343 err_dma_1: |
|
4344 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
|
4345 err_dma_0: |
|
4346 dev_kfree_skb(skb); |
|
4347 dev->stats.tx_dropped++; |
|
4348 return NETDEV_TX_OK; |
|
4349 |
|
4350 err_stop_0: |
|
4351 netif_stop_queue(dev); |
|
4352 dev->stats.tx_dropped++; |
|
4353 return NETDEV_TX_BUSY; |
|
4354 } |
|
4355 |
|
4356 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
4357 { |
|
4358 struct rtl8169_private *tp = netdev_priv(dev); |
|
4359 struct pci_dev *pdev = tp->pci_dev; |
|
4360 void __iomem *ioaddr = tp->mmio_addr; |
|
4361 u16 pci_status, pci_cmd; |
|
4362 |
|
4363 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
4364 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
4365 |
|
4366 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
|
4367 pci_cmd, pci_status); |
|
4368 |
|
4369 /* |
|
4370 * The recovery sequence below admits a very elaborated explanation: |
|
4371 * - it seems to work; |
|
4372 * - I did not see what else could be done; |
|
4373 * - it makes iop3xx happy. |
|
4374 * |
|
4375 * Feel free to adjust to your needs. |
|
4376 */ |
|
4377 if (pdev->broken_parity_status) |
|
4378 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
4379 else |
|
4380 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
4381 |
|
4382 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
4383 |
|
4384 pci_write_config_word(pdev, PCI_STATUS, |
|
4385 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
4386 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
4387 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
4388 |
|
4389 /* The infamous DAC f*ckup only happens at boot time */ |
|
4390 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
4391 netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
|
4392 tp->cp_cmd &= ~PCIDAC; |
|
4393 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4394 dev->features &= ~NETIF_F_HIGHDMA; |
|
4395 } |
|
4396 |
|
4397 rtl8169_hw_reset(ioaddr); |
|
4398 |
|
4399 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
4400 } |
|
4401 |
|
4402 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
4403 struct rtl8169_private *tp, |
|
4404 void __iomem *ioaddr) |
|
4405 { |
|
4406 unsigned int dirty_tx, tx_left; |
|
4407 |
|
4408 dirty_tx = tp->dirty_tx; |
|
4409 smp_rmb(); |
|
4410 tx_left = tp->cur_tx - dirty_tx; |
|
4411 |
|
4412 while (tx_left > 0) { |
|
4413 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
4414 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
4415 u32 status; |
|
4416 |
|
4417 rmb(); |
|
4418 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
4419 if (status & DescOwn) |
|
4420 break; |
|
4421 |
|
4422 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
4423 tp->TxDescArray + entry); |
|
4424 if (status & LastFrag) { |
|
4425 dev->stats.tx_packets++; |
|
4426 dev->stats.tx_bytes += tx_skb->skb->len; |
|
4427 dev_kfree_skb(tx_skb->skb); |
|
4428 tx_skb->skb = NULL; |
|
4429 } |
|
4430 dirty_tx++; |
|
4431 tx_left--; |
|
4432 } |
|
4433 |
|
4434 if (tp->dirty_tx != dirty_tx) { |
|
4435 tp->dirty_tx = dirty_tx; |
|
4436 smp_wmb(); |
|
4437 if (netif_queue_stopped(dev) && |
|
4438 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
4439 netif_wake_queue(dev); |
|
4440 } |
|
4441 /* |
|
4442 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
4443 * too close. Let's kick an extra TxPoll request when a burst |
|
4444 * of start_xmit activity is detected (if it is not detected, |
|
4445 * it is slow enough). -- FR |
|
4446 */ |
|
4447 smp_rmb(); |
|
4448 if (tp->cur_tx != dirty_tx) |
|
4449 RTL_W8(TxPoll, NPQ); |
|
4450 } |
|
4451 } |
|
4452 |
|
4453 static inline int rtl8169_fragmented_frame(u32 status) |
|
4454 { |
|
4455 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
4456 } |
|
4457 |
|
4458 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
|
4459 { |
|
4460 u32 status = opts1 & RxProtoMask; |
|
4461 |
|
4462 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
4463 ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
|
4464 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
4465 else |
|
4466 skb_checksum_none_assert(skb); |
|
4467 } |
|
4468 |
|
4469 static struct sk_buff *rtl8169_try_rx_copy(void *data, |
|
4470 struct rtl8169_private *tp, |
|
4471 int pkt_size, |
|
4472 dma_addr_t addr) |
|
4473 { |
|
4474 struct sk_buff *skb; |
|
4475 struct device *d = &tp->pci_dev->dev; |
|
4476 |
|
4477 data = rtl8169_align(data); |
|
4478 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
4479 prefetch(data); |
|
4480 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); |
|
4481 if (skb) |
|
4482 memcpy(skb->data, data, pkt_size); |
|
4483 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
4484 |
|
4485 return skb; |
|
4486 } |
|
4487 |
|
4488 /* |
|
4489 * Warning : rtl8169_rx_interrupt() might be called : |
|
4490 * 1) from NAPI (softirq) context |
|
4491 * (polling = 1 : we should call netif_receive_skb()) |
|
4492 * 2) from process context (rtl8169_reset_task()) |
|
4493 * (polling = 0 : we must call netif_rx() instead) |
|
4494 */ |
|
4495 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
4496 struct rtl8169_private *tp, |
|
4497 void __iomem *ioaddr, u32 budget) |
|
4498 { |
|
4499 unsigned int cur_rx, rx_left; |
|
4500 unsigned int count; |
|
4501 int polling = (budget != ~(u32)0) ? 1 : 0; |
|
4502 |
|
4503 cur_rx = tp->cur_rx; |
|
4504 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
4505 rx_left = min(rx_left, budget); |
|
4506 |
|
4507 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
4508 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
4509 struct RxDesc *desc = tp->RxDescArray + entry; |
|
4510 u32 status; |
|
4511 |
|
4512 rmb(); |
|
4513 status = le32_to_cpu(desc->opts1); |
|
4514 |
|
4515 if (status & DescOwn) |
|
4516 break; |
|
4517 if (unlikely(status & RxRES)) { |
|
4518 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
|
4519 status); |
|
4520 dev->stats.rx_errors++; |
|
4521 if (status & (RxRWT | RxRUNT)) |
|
4522 dev->stats.rx_length_errors++; |
|
4523 if (status & RxCRC) |
|
4524 dev->stats.rx_crc_errors++; |
|
4525 if (status & RxFOVF) { |
|
4526 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4527 dev->stats.rx_fifo_errors++; |
|
4528 } |
|
4529 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
4530 } else { |
|
4531 struct sk_buff *skb; |
|
4532 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
4533 int pkt_size = (status & 0x00001FFF) - 4; |
|
4534 |
|
4535 /* |
|
4536 * The driver does not support incoming fragmented |
|
4537 * frames. They are seen as a symptom of over-mtu |
|
4538 * sized frames. |
|
4539 */ |
|
4540 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
4541 dev->stats.rx_dropped++; |
|
4542 dev->stats.rx_length_errors++; |
|
4543 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
4544 continue; |
|
4545 } |
|
4546 |
|
4547 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
|
4548 tp, pkt_size, addr); |
|
4549 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
4550 if (!skb) { |
|
4551 dev->stats.rx_dropped++; |
|
4552 continue; |
|
4553 } |
|
4554 |
|
4555 rtl8169_rx_csum(skb, status); |
|
4556 skb_put(skb, pkt_size); |
|
4557 skb->protocol = eth_type_trans(skb, dev); |
|
4558 |
|
4559 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) { |
|
4560 if (likely(polling)) |
|
4561 napi_gro_receive(&tp->napi, skb); |
|
4562 else |
|
4563 netif_rx(skb); |
|
4564 } |
|
4565 |
|
4566 dev->stats.rx_bytes += pkt_size; |
|
4567 dev->stats.rx_packets++; |
|
4568 } |
|
4569 |
|
4570 /* Work around for AMD plateform. */ |
|
4571 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
4572 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
4573 desc->opts2 = 0; |
|
4574 cur_rx++; |
|
4575 } |
|
4576 } |
|
4577 |
|
4578 count = cur_rx - tp->cur_rx; |
|
4579 tp->cur_rx = cur_rx; |
|
4580 |
|
4581 tp->dirty_rx += count; |
|
4582 |
|
4583 return count; |
|
4584 } |
|
4585 |
|
4586 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
4587 { |
|
4588 struct net_device *dev = dev_instance; |
|
4589 struct rtl8169_private *tp = netdev_priv(dev); |
|
4590 void __iomem *ioaddr = tp->mmio_addr; |
|
4591 int handled = 0; |
|
4592 int status; |
|
4593 |
|
4594 /* loop handling interrupts until we have no new ones or |
|
4595 * we hit a invalid/hotplug case. |
|
4596 */ |
|
4597 status = RTL_R16(IntrStatus); |
|
4598 while (status && status != 0xffff) { |
|
4599 handled = 1; |
|
4600 |
|
4601 /* Handle all of the error cases first. These will reset |
|
4602 * the chip, so just exit the loop. |
|
4603 */ |
|
4604 if (unlikely(!netif_running(dev))) { |
|
4605 rtl8169_asic_down(ioaddr); |
|
4606 break; |
|
4607 } |
|
4608 |
|
4609 if (unlikely(status & RxFIFOOver)) { |
|
4610 switch (tp->mac_version) { |
|
4611 /* Work around for rx fifo overflow */ |
|
4612 case RTL_GIGA_MAC_VER_11: |
|
4613 case RTL_GIGA_MAC_VER_22: |
|
4614 case RTL_GIGA_MAC_VER_26: |
|
4615 netif_stop_queue(dev); |
|
4616 rtl8169_tx_timeout(dev); |
|
4617 goto done; |
|
4618 /* Testers needed. */ |
|
4619 case RTL_GIGA_MAC_VER_17: |
|
4620 case RTL_GIGA_MAC_VER_19: |
|
4621 case RTL_GIGA_MAC_VER_20: |
|
4622 case RTL_GIGA_MAC_VER_21: |
|
4623 case RTL_GIGA_MAC_VER_23: |
|
4624 case RTL_GIGA_MAC_VER_24: |
|
4625 case RTL_GIGA_MAC_VER_27: |
|
4626 /* Experimental science. Pktgen proof. */ |
|
4627 case RTL_GIGA_MAC_VER_12: |
|
4628 case RTL_GIGA_MAC_VER_25: |
|
4629 if (status == RxFIFOOver) |
|
4630 goto done; |
|
4631 break; |
|
4632 default: |
|
4633 break; |
|
4634 } |
|
4635 } |
|
4636 |
|
4637 if (unlikely(status & SYSErr)) { |
|
4638 rtl8169_pcierr_interrupt(dev); |
|
4639 break; |
|
4640 } |
|
4641 |
|
4642 if (status & LinkChg) |
|
4643 __rtl8169_check_link_status(dev, tp, ioaddr, true); |
|
4644 |
|
4645 /* We need to see the lastest version of tp->intr_mask to |
|
4646 * avoid ignoring an MSI interrupt and having to wait for |
|
4647 * another event which may never come. |
|
4648 */ |
|
4649 smp_rmb(); |
|
4650 if (status & tp->intr_mask & tp->napi_event) { |
|
4651 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
4652 tp->intr_mask = ~tp->napi_event; |
|
4653 |
|
4654 if (likely(napi_schedule_prep(&tp->napi))) |
|
4655 __napi_schedule(&tp->napi); |
|
4656 else |
|
4657 netif_info(tp, intr, dev, |
|
4658 "interrupt %04x in poll\n", status); |
|
4659 } |
|
4660 |
|
4661 /* We only get a new MSI interrupt when all active irq |
|
4662 * sources on the chip have been acknowledged. So, ack |
|
4663 * everything we've seen and check if new sources have become |
|
4664 * active to avoid blocking all interrupts from the chip. |
|
4665 */ |
|
4666 RTL_W16(IntrStatus, |
|
4667 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
4668 status = RTL_R16(IntrStatus); |
|
4669 } |
|
4670 done: |
|
4671 return IRQ_RETVAL(handled); |
|
4672 } |
|
4673 |
|
4674 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
4675 { |
|
4676 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
4677 struct net_device *dev = tp->dev; |
|
4678 void __iomem *ioaddr = tp->mmio_addr; |
|
4679 int work_done; |
|
4680 |
|
4681 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
4682 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
4683 |
|
4684 if (work_done < budget) { |
|
4685 napi_complete(napi); |
|
4686 |
|
4687 /* We need for force the visibility of tp->intr_mask |
|
4688 * for other CPUs, as we can loose an MSI interrupt |
|
4689 * and potentially wait for a retransmit timeout if we don't. |
|
4690 * The posted write to IntrMask is safe, as it will |
|
4691 * eventually make it to the chip and we won't loose anything |
|
4692 * until it does. |
|
4693 */ |
|
4694 tp->intr_mask = 0xffff; |
|
4695 wmb(); |
|
4696 RTL_W16(IntrMask, tp->intr_event); |
|
4697 } |
|
4698 |
|
4699 return work_done; |
|
4700 } |
|
4701 |
|
4702 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
4703 { |
|
4704 struct rtl8169_private *tp = netdev_priv(dev); |
|
4705 |
|
4706 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
4707 return; |
|
4708 |
|
4709 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
4710 RTL_W32(RxMissed, 0); |
|
4711 } |
|
4712 |
|
4713 static void rtl8169_down(struct net_device *dev) |
|
4714 { |
|
4715 struct rtl8169_private *tp = netdev_priv(dev); |
|
4716 void __iomem *ioaddr = tp->mmio_addr; |
|
4717 |
|
4718 rtl8169_delete_timer(dev); |
|
4719 |
|
4720 netif_stop_queue(dev); |
|
4721 |
|
4722 napi_disable(&tp->napi); |
|
4723 |
|
4724 spin_lock_irq(&tp->lock); |
|
4725 |
|
4726 rtl8169_asic_down(ioaddr); |
|
4727 /* |
|
4728 * At this point device interrupts can not be enabled in any function, |
|
4729 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, |
|
4730 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). |
|
4731 */ |
|
4732 rtl8169_rx_missed(dev, ioaddr); |
|
4733 |
|
4734 spin_unlock_irq(&tp->lock); |
|
4735 |
|
4736 synchronize_irq(dev->irq); |
|
4737 |
|
4738 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
4739 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
4740 |
|
4741 rtl8169_tx_clear(tp); |
|
4742 |
|
4743 rtl8169_rx_clear(tp); |
|
4744 } |
|
4745 |
|
4746 static int rtl8169_close(struct net_device *dev) |
|
4747 { |
|
4748 struct rtl8169_private *tp = netdev_priv(dev); |
|
4749 struct pci_dev *pdev = tp->pci_dev; |
|
4750 |
|
4751 pm_runtime_get_sync(&pdev->dev); |
|
4752 |
|
4753 /* update counters before going down */ |
|
4754 rtl8169_update_counters(dev); |
|
4755 |
|
4756 rtl8169_down(dev); |
|
4757 |
|
4758 free_irq(dev->irq, dev); |
|
4759 |
|
4760 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
4761 tp->RxPhyAddr); |
|
4762 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
4763 tp->TxPhyAddr); |
|
4764 tp->TxDescArray = NULL; |
|
4765 tp->RxDescArray = NULL; |
|
4766 |
|
4767 pm_runtime_put_sync(&pdev->dev); |
|
4768 |
|
4769 return 0; |
|
4770 } |
|
4771 |
|
4772 static void rtl_set_rx_mode(struct net_device *dev) |
|
4773 { |
|
4774 struct rtl8169_private *tp = netdev_priv(dev); |
|
4775 void __iomem *ioaddr = tp->mmio_addr; |
|
4776 unsigned long flags; |
|
4777 u32 mc_filter[2]; /* Multicast hash filter */ |
|
4778 int rx_mode; |
|
4779 u32 tmp = 0; |
|
4780 |
|
4781 if (dev->flags & IFF_PROMISC) { |
|
4782 /* Unconditionally log net taps. */ |
|
4783 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
|
4784 rx_mode = |
|
4785 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
4786 AcceptAllPhys; |
|
4787 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4788 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
4789 (dev->flags & IFF_ALLMULTI)) { |
|
4790 /* Too many to filter perfectly -- accept all multicasts. */ |
|
4791 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
4792 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4793 } else { |
|
4794 struct netdev_hw_addr *ha; |
|
4795 |
|
4796 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
4797 mc_filter[1] = mc_filter[0] = 0; |
|
4798 netdev_for_each_mc_addr(ha, dev) { |
|
4799 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
4800 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
4801 rx_mode |= AcceptMulticast; |
|
4802 } |
|
4803 } |
|
4804 |
|
4805 spin_lock_irqsave(&tp->lock, flags); |
|
4806 |
|
4807 tmp = rtl8169_rx_config | rx_mode | |
|
4808 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
4809 |
|
4810 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
4811 u32 data = mc_filter[0]; |
|
4812 |
|
4813 mc_filter[0] = swab32(mc_filter[1]); |
|
4814 mc_filter[1] = swab32(data); |
|
4815 } |
|
4816 |
|
4817 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
4818 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
4819 |
|
4820 RTL_W32(RxConfig, tmp); |
|
4821 |
|
4822 spin_unlock_irqrestore(&tp->lock, flags); |
|
4823 } |
|
4824 |
|
4825 /** |
|
4826 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
4827 * @dev: The Ethernet Device to get statistics for |
|
4828 * |
|
4829 * Get TX/RX statistics for rtl8169 |
|
4830 */ |
|
4831 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
4832 { |
|
4833 struct rtl8169_private *tp = netdev_priv(dev); |
|
4834 void __iomem *ioaddr = tp->mmio_addr; |
|
4835 unsigned long flags; |
|
4836 |
|
4837 if (netif_running(dev)) { |
|
4838 spin_lock_irqsave(&tp->lock, flags); |
|
4839 rtl8169_rx_missed(dev, ioaddr); |
|
4840 spin_unlock_irqrestore(&tp->lock, flags); |
|
4841 } |
|
4842 |
|
4843 return &dev->stats; |
|
4844 } |
|
4845 |
|
4846 static void rtl8169_net_suspend(struct net_device *dev) |
|
4847 { |
|
4848 if (!netif_running(dev)) |
|
4849 return; |
|
4850 |
|
4851 netif_device_detach(dev); |
|
4852 netif_stop_queue(dev); |
|
4853 } |
|
4854 |
|
4855 #ifdef CONFIG_PM |
|
4856 |
|
4857 static int rtl8169_suspend(struct device *device) |
|
4858 { |
|
4859 struct pci_dev *pdev = to_pci_dev(device); |
|
4860 struct net_device *dev = pci_get_drvdata(pdev); |
|
4861 |
|
4862 rtl8169_net_suspend(dev); |
|
4863 |
|
4864 return 0; |
|
4865 } |
|
4866 |
|
4867 static void __rtl8169_resume(struct net_device *dev) |
|
4868 { |
|
4869 netif_device_attach(dev); |
|
4870 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4871 } |
|
4872 |
|
4873 static int rtl8169_resume(struct device *device) |
|
4874 { |
|
4875 struct pci_dev *pdev = to_pci_dev(device); |
|
4876 struct net_device *dev = pci_get_drvdata(pdev); |
|
4877 struct rtl8169_private *tp = netdev_priv(dev); |
|
4878 |
|
4879 rtl8169_init_phy(dev, tp); |
|
4880 |
|
4881 if (netif_running(dev)) |
|
4882 __rtl8169_resume(dev); |
|
4883 |
|
4884 return 0; |
|
4885 } |
|
4886 |
|
4887 static int rtl8169_runtime_suspend(struct device *device) |
|
4888 { |
|
4889 struct pci_dev *pdev = to_pci_dev(device); |
|
4890 struct net_device *dev = pci_get_drvdata(pdev); |
|
4891 struct rtl8169_private *tp = netdev_priv(dev); |
|
4892 |
|
4893 if (!tp->TxDescArray) |
|
4894 return 0; |
|
4895 |
|
4896 spin_lock_irq(&tp->lock); |
|
4897 tp->saved_wolopts = __rtl8169_get_wol(tp); |
|
4898 __rtl8169_set_wol(tp, WAKE_ANY); |
|
4899 spin_unlock_irq(&tp->lock); |
|
4900 |
|
4901 rtl8169_net_suspend(dev); |
|
4902 |
|
4903 return 0; |
|
4904 } |
|
4905 |
|
4906 static int rtl8169_runtime_resume(struct device *device) |
|
4907 { |
|
4908 struct pci_dev *pdev = to_pci_dev(device); |
|
4909 struct net_device *dev = pci_get_drvdata(pdev); |
|
4910 struct rtl8169_private *tp = netdev_priv(dev); |
|
4911 |
|
4912 if (!tp->TxDescArray) |
|
4913 return 0; |
|
4914 |
|
4915 spin_lock_irq(&tp->lock); |
|
4916 __rtl8169_set_wol(tp, tp->saved_wolopts); |
|
4917 tp->saved_wolopts = 0; |
|
4918 spin_unlock_irq(&tp->lock); |
|
4919 |
|
4920 rtl8169_init_phy(dev, tp); |
|
4921 |
|
4922 __rtl8169_resume(dev); |
|
4923 |
|
4924 return 0; |
|
4925 } |
|
4926 |
|
4927 static int rtl8169_runtime_idle(struct device *device) |
|
4928 { |
|
4929 struct pci_dev *pdev = to_pci_dev(device); |
|
4930 struct net_device *dev = pci_get_drvdata(pdev); |
|
4931 struct rtl8169_private *tp = netdev_priv(dev); |
|
4932 |
|
4933 return tp->TxDescArray ? -EBUSY : 0; |
|
4934 } |
|
4935 |
|
4936 static const struct dev_pm_ops rtl8169_pm_ops = { |
|
4937 .suspend = rtl8169_suspend, |
|
4938 .resume = rtl8169_resume, |
|
4939 .freeze = rtl8169_suspend, |
|
4940 .thaw = rtl8169_resume, |
|
4941 .poweroff = rtl8169_suspend, |
|
4942 .restore = rtl8169_resume, |
|
4943 .runtime_suspend = rtl8169_runtime_suspend, |
|
4944 .runtime_resume = rtl8169_runtime_resume, |
|
4945 .runtime_idle = rtl8169_runtime_idle, |
|
4946 }; |
|
4947 |
|
4948 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
4949 |
|
4950 #else /* !CONFIG_PM */ |
|
4951 |
|
4952 #define RTL8169_PM_OPS NULL |
|
4953 |
|
4954 #endif /* !CONFIG_PM */ |
|
4955 |
|
4956 static void rtl_shutdown(struct pci_dev *pdev) |
|
4957 { |
|
4958 struct net_device *dev = pci_get_drvdata(pdev); |
|
4959 struct rtl8169_private *tp = netdev_priv(dev); |
|
4960 void __iomem *ioaddr = tp->mmio_addr; |
|
4961 |
|
4962 rtl8169_net_suspend(dev); |
|
4963 |
|
4964 /* restore original MAC address */ |
|
4965 rtl_rar_set(tp, dev->perm_addr); |
|
4966 |
|
4967 spin_lock_irq(&tp->lock); |
|
4968 |
|
4969 rtl8169_asic_down(ioaddr); |
|
4970 |
|
4971 spin_unlock_irq(&tp->lock); |
|
4972 |
|
4973 if (system_state == SYSTEM_POWER_OFF) { |
|
4974 /* WoL fails with some 8168 when the receiver is disabled. */ |
|
4975 if (tp->features & RTL_FEATURE_WOL) { |
|
4976 pci_clear_master(pdev); |
|
4977 |
|
4978 RTL_W8(ChipCmd, CmdRxEnb); |
|
4979 /* PCI commit */ |
|
4980 RTL_R8(ChipCmd); |
|
4981 } |
|
4982 |
|
4983 pci_wake_from_d3(pdev, true); |
|
4984 pci_set_power_state(pdev, PCI_D3hot); |
|
4985 } |
|
4986 } |
|
4987 |
|
4988 static struct pci_driver rtl8169_pci_driver = { |
|
4989 .name = MODULENAME, |
|
4990 .id_table = rtl8169_pci_tbl, |
|
4991 .probe = rtl8169_init_one, |
|
4992 .remove = __devexit_p(rtl8169_remove_one), |
|
4993 .shutdown = rtl_shutdown, |
|
4994 .driver.pm = RTL8169_PM_OPS, |
|
4995 }; |
|
4996 |
|
4997 static int __init rtl8169_init_module(void) |
|
4998 { |
|
4999 return pci_register_driver(&rtl8169_pci_driver); |
|
5000 } |
|
5001 |
|
5002 static void __exit rtl8169_cleanup_module(void) |
|
5003 { |
|
5004 pci_unregister_driver(&rtl8169_pci_driver); |
|
5005 } |
|
5006 |
|
5007 module_init(rtl8169_init_module); |
|
5008 module_exit(rtl8169_cleanup_module); |