|
1 /* |
|
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
|
3 * |
|
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
|
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
|
6 * Copyright (c) a lot of people too. Please respect their work. |
|
7 * |
|
8 * See MAINTAINERS file for support contact information. |
|
9 */ |
|
10 |
|
11 #include <linux/module.h> |
|
12 #include <linux/moduleparam.h> |
|
13 #include <linux/pci.h> |
|
14 #include <linux/netdevice.h> |
|
15 #include <linux/etherdevice.h> |
|
16 #include <linux/delay.h> |
|
17 #include <linux/ethtool.h> |
|
18 #include <linux/mii.h> |
|
19 #include <linux/if_vlan.h> |
|
20 #include <linux/crc32.h> |
|
21 #include <linux/in.h> |
|
22 #include <linux/ip.h> |
|
23 #include <linux/tcp.h> |
|
24 #include <linux/init.h> |
|
25 #include <linux/dma-mapping.h> |
|
26 |
|
27 #include <asm/system.h> |
|
28 #include <asm/io.h> |
|
29 #include <asm/irq.h> |
|
30 #include "../globals.h" |
|
31 #include "ecdev.h" |
|
32 |
|
33 #define RTL8169_VERSION "2.3LK-NAPI" |
|
34 #define MODULENAME "ec_r8169" |
|
35 #define PFX MODULENAME ": " |
|
36 |
|
37 #ifdef RTL8169_DEBUG |
|
38 #define assert(expr) \ |
|
39 if (!(expr)) { \ |
|
40 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
|
41 #expr,__FILE__,__func__,__LINE__); \ |
|
42 } |
|
43 #define dprintk(fmt, args...) \ |
|
44 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
|
45 #else |
|
46 #define assert(expr) do {} while (0) |
|
47 #define dprintk(fmt, args...) do {} while (0) |
|
48 #endif /* RTL8169_DEBUG */ |
|
49 |
|
50 #define R8169_MSG_DEFAULT \ |
|
51 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
|
52 |
|
53 #define TX_BUFFS_AVAIL(tp) \ |
|
54 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) |
|
55 |
|
56 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
|
57 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
|
58 static const int multicast_filter_limit = 32; |
|
59 |
|
60 /* MAC address length */ |
|
61 #define MAC_ADDR_LEN 6 |
|
62 |
|
63 #define MAX_READ_REQUEST_SHIFT 12 |
|
64 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
|
65 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
|
66 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
|
67 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
|
68 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
|
69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
|
70 |
|
71 #define R8169_REGS_SIZE 256 |
|
72 #define R8169_NAPI_WEIGHT 64 |
|
73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
|
74 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
|
75 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
|
76 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
|
77 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
|
78 |
|
79 #define RTL8169_TX_TIMEOUT (6*HZ) |
|
80 #define RTL8169_PHY_TIMEOUT (10*HZ) |
|
81 |
|
82 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
|
83 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
|
84 #define RTL_EEPROM_SIG_ADDR 0x0000 |
|
85 |
|
86 /* write/read MMIO register */ |
|
87 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
|
88 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
|
89 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
|
90 #define RTL_R8(reg) readb (ioaddr + (reg)) |
|
91 #define RTL_R16(reg) readw (ioaddr + (reg)) |
|
92 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
|
93 |
|
94 enum mac_version { |
|
95 RTL_GIGA_MAC_NONE = 0x00, |
|
96 RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
|
97 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S |
|
98 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S |
|
99 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB |
|
100 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd |
|
101 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
|
102 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
|
103 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e |
|
104 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e |
|
105 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e |
|
106 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
|
107 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
|
108 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb |
|
109 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? |
|
110 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? |
|
111 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec |
|
112 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf |
|
113 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP |
|
114 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
|
115 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
|
116 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
|
117 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
|
118 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
|
119 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
|
120 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D |
|
121 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D |
|
122 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP |
|
123 }; |
|
124 |
|
125 #define _R(NAME,MAC,MASK) \ |
|
126 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
|
127 |
|
128 static const struct { |
|
129 const char *name; |
|
130 u8 mac_version; |
|
131 u32 RxConfigMask; /* Clears the bits supported by this chip */ |
|
132 } rtl_chip_info[] = { |
|
133 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
|
134 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S |
|
135 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S |
|
136 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB |
|
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd |
|
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
|
139 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
|
140 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E |
|
141 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E |
|
142 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E |
|
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
|
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
|
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
|
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
|
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
|
148 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E |
|
149 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E |
|
150 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E |
|
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
|
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
|
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
|
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
|
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
|
156 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
|
157 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E |
|
158 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E |
|
159 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E |
|
160 }; |
|
161 #undef _R |
|
162 |
|
163 enum cfg_version { |
|
164 RTL_CFG_0 = 0x00, |
|
165 RTL_CFG_1, |
|
166 RTL_CFG_2 |
|
167 }; |
|
168 |
|
169 static void rtl_hw_start_8169(struct net_device *); |
|
170 static void rtl_hw_start_8168(struct net_device *); |
|
171 static void rtl_hw_start_8101(struct net_device *); |
|
172 |
|
173 static struct pci_device_id rtl8169_pci_tbl[] = { |
|
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
|
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
|
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
|
177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
|
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
|
179 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
|
180 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
|
181 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
|
182 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
|
183 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
|
184 { 0x0001, 0x8168, |
|
185 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
|
186 {0,}, |
|
187 }; |
|
188 |
|
189 /* prevent driver from being loaded automatically */ |
|
190 //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
|
191 |
|
192 static int rx_copybreak = 200; |
|
193 static int use_dac; |
|
194 static struct { |
|
195 u32 msg_enable; |
|
196 } debug = { -1 }; |
|
197 |
|
198 enum rtl_registers { |
|
199 MAC0 = 0, /* Ethernet hardware address. */ |
|
200 MAC4 = 4, |
|
201 MAR0 = 8, /* Multicast filter. */ |
|
202 CounterAddrLow = 0x10, |
|
203 CounterAddrHigh = 0x14, |
|
204 TxDescStartAddrLow = 0x20, |
|
205 TxDescStartAddrHigh = 0x24, |
|
206 TxHDescStartAddrLow = 0x28, |
|
207 TxHDescStartAddrHigh = 0x2c, |
|
208 FLASH = 0x30, |
|
209 ERSR = 0x36, |
|
210 ChipCmd = 0x37, |
|
211 TxPoll = 0x38, |
|
212 IntrMask = 0x3c, |
|
213 IntrStatus = 0x3e, |
|
214 TxConfig = 0x40, |
|
215 RxConfig = 0x44, |
|
216 RxMissed = 0x4c, |
|
217 Cfg9346 = 0x50, |
|
218 Config0 = 0x51, |
|
219 Config1 = 0x52, |
|
220 Config2 = 0x53, |
|
221 Config3 = 0x54, |
|
222 Config4 = 0x55, |
|
223 Config5 = 0x56, |
|
224 MultiIntr = 0x5c, |
|
225 PHYAR = 0x60, |
|
226 PHYstatus = 0x6c, |
|
227 RxMaxSize = 0xda, |
|
228 CPlusCmd = 0xe0, |
|
229 IntrMitigate = 0xe2, |
|
230 RxDescAddrLow = 0xe4, |
|
231 RxDescAddrHigh = 0xe8, |
|
232 EarlyTxThres = 0xec, |
|
233 FuncEvent = 0xf0, |
|
234 FuncEventMask = 0xf4, |
|
235 FuncPresetState = 0xf8, |
|
236 FuncForceEvent = 0xfc, |
|
237 }; |
|
238 |
|
239 enum rtl8110_registers { |
|
240 TBICSR = 0x64, |
|
241 TBI_ANAR = 0x68, |
|
242 TBI_LPAR = 0x6a, |
|
243 }; |
|
244 |
|
245 enum rtl8168_8101_registers { |
|
246 CSIDR = 0x64, |
|
247 CSIAR = 0x68, |
|
248 #define CSIAR_FLAG 0x80000000 |
|
249 #define CSIAR_WRITE_CMD 0x80000000 |
|
250 #define CSIAR_BYTE_ENABLE 0x0f |
|
251 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
|
252 #define CSIAR_ADDR_MASK 0x0fff |
|
253 |
|
254 EPHYAR = 0x80, |
|
255 #define EPHYAR_FLAG 0x80000000 |
|
256 #define EPHYAR_WRITE_CMD 0x80000000 |
|
257 #define EPHYAR_REG_MASK 0x1f |
|
258 #define EPHYAR_REG_SHIFT 16 |
|
259 #define EPHYAR_DATA_MASK 0xffff |
|
260 DBG_REG = 0xd1, |
|
261 #define FIX_NAK_1 (1 << 4) |
|
262 #define FIX_NAK_2 (1 << 3) |
|
263 EFUSEAR = 0xdc, |
|
264 #define EFUSEAR_FLAG 0x80000000 |
|
265 #define EFUSEAR_WRITE_CMD 0x80000000 |
|
266 #define EFUSEAR_READ_CMD 0x00000000 |
|
267 #define EFUSEAR_REG_MASK 0x03ff |
|
268 #define EFUSEAR_REG_SHIFT 8 |
|
269 #define EFUSEAR_DATA_MASK 0xff |
|
270 }; |
|
271 |
|
272 enum rtl_register_content { |
|
273 /* InterruptStatusBits */ |
|
274 SYSErr = 0x8000, |
|
275 PCSTimeout = 0x4000, |
|
276 SWInt = 0x0100, |
|
277 TxDescUnavail = 0x0080, |
|
278 RxFIFOOver = 0x0040, |
|
279 LinkChg = 0x0020, |
|
280 RxOverflow = 0x0010, |
|
281 TxErr = 0x0008, |
|
282 TxOK = 0x0004, |
|
283 RxErr = 0x0002, |
|
284 RxOK = 0x0001, |
|
285 |
|
286 /* RxStatusDesc */ |
|
287 RxFOVF = (1 << 23), |
|
288 RxRWT = (1 << 22), |
|
289 RxRES = (1 << 21), |
|
290 RxRUNT = (1 << 20), |
|
291 RxCRC = (1 << 19), |
|
292 |
|
293 /* ChipCmdBits */ |
|
294 CmdReset = 0x10, |
|
295 CmdRxEnb = 0x08, |
|
296 CmdTxEnb = 0x04, |
|
297 RxBufEmpty = 0x01, |
|
298 |
|
299 /* TXPoll register p.5 */ |
|
300 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
301 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
302 FSWInt = 0x01, /* Forced software interrupt */ |
|
303 |
|
304 /* Cfg9346Bits */ |
|
305 Cfg9346_Lock = 0x00, |
|
306 Cfg9346_Unlock = 0xc0, |
|
307 |
|
308 /* rx_mode_bits */ |
|
309 AcceptErr = 0x20, |
|
310 AcceptRunt = 0x10, |
|
311 AcceptBroadcast = 0x08, |
|
312 AcceptMulticast = 0x04, |
|
313 AcceptMyPhys = 0x02, |
|
314 AcceptAllPhys = 0x01, |
|
315 |
|
316 /* RxConfigBits */ |
|
317 RxCfgFIFOShift = 13, |
|
318 RxCfgDMAShift = 8, |
|
319 |
|
320 /* TxConfigBits */ |
|
321 TxInterFrameGapShift = 24, |
|
322 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
323 |
|
324 /* Config1 register p.24 */ |
|
325 LEDS1 = (1 << 7), |
|
326 LEDS0 = (1 << 6), |
|
327 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
|
328 Speed_down = (1 << 4), |
|
329 MEMMAP = (1 << 3), |
|
330 IOMAP = (1 << 2), |
|
331 VPD = (1 << 1), |
|
332 PMEnable = (1 << 0), /* Power Management Enable */ |
|
333 |
|
334 /* Config2 register p. 25 */ |
|
335 PCI_Clock_66MHz = 0x01, |
|
336 PCI_Clock_33MHz = 0x00, |
|
337 |
|
338 /* Config3 register p.25 */ |
|
339 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
340 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
341 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
|
342 |
|
343 /* Config5 register p.27 */ |
|
344 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
345 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
346 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
347 LanWake = (1 << 1), /* LanWake enable/disable */ |
|
348 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
349 |
|
350 /* TBICSR p.28 */ |
|
351 TBIReset = 0x80000000, |
|
352 TBILoopback = 0x40000000, |
|
353 TBINwEnable = 0x20000000, |
|
354 TBINwRestart = 0x10000000, |
|
355 TBILinkOk = 0x02000000, |
|
356 TBINwComplete = 0x01000000, |
|
357 |
|
358 /* CPlusCmd p.31 */ |
|
359 EnableBist = (1 << 15), // 8168 8101 |
|
360 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
|
361 Normal_mode = (1 << 13), // unused |
|
362 Force_half_dup = (1 << 12), // 8168 8101 |
|
363 Force_rxflow_en = (1 << 11), // 8168 8101 |
|
364 Force_txflow_en = (1 << 10), // 8168 8101 |
|
365 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
|
366 ASF = (1 << 8), // 8168 8101 |
|
367 PktCntrDisable = (1 << 7), // 8168 8101 |
|
368 Mac_dbgo_sel = 0x001c, // 8168 |
|
369 RxVlan = (1 << 6), |
|
370 RxChkSum = (1 << 5), |
|
371 PCIDAC = (1 << 4), |
|
372 PCIMulRW = (1 << 3), |
|
373 INTT_0 = 0x0000, // 8168 |
|
374 INTT_1 = 0x0001, // 8168 |
|
375 INTT_2 = 0x0002, // 8168 |
|
376 INTT_3 = 0x0003, // 8168 |
|
377 |
|
378 /* rtl8169_PHYstatus */ |
|
379 TBI_Enable = 0x80, |
|
380 TxFlowCtrl = 0x40, |
|
381 RxFlowCtrl = 0x20, |
|
382 _1000bpsF = 0x10, |
|
383 _100bps = 0x08, |
|
384 _10bps = 0x04, |
|
385 LinkStatus = 0x02, |
|
386 FullDup = 0x01, |
|
387 |
|
388 /* _TBICSRBit */ |
|
389 TBILinkOK = 0x02000000, |
|
390 |
|
391 /* DumpCounterCommand */ |
|
392 CounterDump = 0x8, |
|
393 }; |
|
394 |
|
395 enum desc_status_bit { |
|
396 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
397 RingEnd = (1 << 30), /* End of descriptor ring */ |
|
398 FirstFrag = (1 << 29), /* First segment of a packet */ |
|
399 LastFrag = (1 << 28), /* Final segment of a packet */ |
|
400 |
|
401 /* Tx private */ |
|
402 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
|
403 MSSShift = 16, /* MSS value position */ |
|
404 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ |
|
405 IPCS = (1 << 18), /* Calculate IP checksum */ |
|
406 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
407 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
408 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
409 |
|
410 /* Rx private */ |
|
411 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
412 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
413 |
|
414 #define RxProtoUDP (PID1) |
|
415 #define RxProtoTCP (PID0) |
|
416 #define RxProtoIP (PID1 | PID0) |
|
417 #define RxProtoMask RxProtoIP |
|
418 |
|
419 IPFail = (1 << 16), /* IP checksum failed */ |
|
420 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
421 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
422 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
423 }; |
|
424 |
|
425 #define RsvdMask 0x3fffc000 |
|
426 |
|
427 struct TxDesc { |
|
428 __le32 opts1; |
|
429 __le32 opts2; |
|
430 __le64 addr; |
|
431 }; |
|
432 |
|
433 struct RxDesc { |
|
434 __le32 opts1; |
|
435 __le32 opts2; |
|
436 __le64 addr; |
|
437 }; |
|
438 |
|
439 struct ring_info { |
|
440 struct sk_buff *skb; |
|
441 u32 len; |
|
442 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
443 }; |
|
444 |
|
445 enum features { |
|
446 RTL_FEATURE_WOL = (1 << 0), |
|
447 RTL_FEATURE_MSI = (1 << 1), |
|
448 RTL_FEATURE_GMII = (1 << 2), |
|
449 }; |
|
450 |
|
451 struct rtl8169_counters { |
|
452 __le64 tx_packets; |
|
453 __le64 rx_packets; |
|
454 __le64 tx_errors; |
|
455 __le32 rx_errors; |
|
456 __le16 rx_missed; |
|
457 __le16 align_errors; |
|
458 __le32 tx_one_collision; |
|
459 __le32 tx_multi_collision; |
|
460 __le64 rx_unicast; |
|
461 __le64 rx_broadcast; |
|
462 __le32 rx_multicast; |
|
463 __le16 tx_aborted; |
|
464 __le16 tx_underun; |
|
465 }; |
|
466 |
|
467 struct rtl8169_private { |
|
468 void __iomem *mmio_addr; /* memory map physical address */ |
|
469 struct pci_dev *pci_dev; /* Index of PCI device */ |
|
470 struct net_device *dev; |
|
471 struct napi_struct napi; |
|
472 spinlock_t lock; /* spin lock flag */ |
|
473 u32 msg_enable; |
|
474 int chipset; |
|
475 int mac_version; |
|
476 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
477 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
478 u32 dirty_rx; |
|
479 u32 dirty_tx; |
|
480 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
481 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
482 dma_addr_t TxPhyAddr; |
|
483 dma_addr_t RxPhyAddr; |
|
484 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
485 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
486 unsigned align; |
|
487 unsigned rx_buf_sz; |
|
488 struct timer_list timer; |
|
489 u16 cp_cmd; |
|
490 u16 intr_event; |
|
491 u16 napi_event; |
|
492 u16 intr_mask; |
|
493 int phy_1000_ctrl_reg; |
|
494 #ifdef CONFIG_R8169_VLAN |
|
495 struct vlan_group *vlgrp; |
|
496 #endif |
|
497 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); |
|
498 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
499 void (*phy_reset_enable)(void __iomem *); |
|
500 void (*hw_start)(struct net_device *); |
|
501 unsigned int (*phy_reset_pending)(void __iomem *); |
|
502 unsigned int (*link_ok)(void __iomem *); |
|
503 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
504 int pcie_cap; |
|
505 struct delayed_work task; |
|
506 unsigned features; |
|
507 |
|
508 struct mii_if_info mii; |
|
509 struct rtl8169_counters counters; |
|
510 |
|
511 ec_device_t *ecdev; |
|
512 unsigned long ec_watchdog_jiffies; |
|
513 }; |
|
514 |
|
515 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>"); |
|
516 MODULE_DESCRIPTION("EtherCAT-capable RealTek RTL-8169 Gigabit Ethernet driver"); |
|
517 module_param(rx_copybreak, int, 0); |
|
518 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
|
519 module_param(use_dac, int, 0); |
|
520 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
521 module_param_named(debug, debug.msg_enable, int, 0); |
|
522 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
523 MODULE_LICENSE("GPL"); |
|
524 MODULE_VERSION(EC_MASTER_VERSION); |
|
525 |
|
526 static int rtl8169_open(struct net_device *dev); |
|
527 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
528 struct net_device *dev); |
|
529 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
|
530 static int rtl8169_init_ring(struct net_device *dev); |
|
531 static void rtl_hw_start(struct net_device *dev); |
|
532 static int rtl8169_close(struct net_device *dev); |
|
533 static void rtl_set_rx_mode(struct net_device *dev); |
|
534 static void rtl8169_tx_timeout(struct net_device *dev); |
|
535 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
|
536 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
|
537 void __iomem *, u32 budget); |
|
538 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
|
539 static void rtl8169_down(struct net_device *dev); |
|
540 static void rtl8169_rx_clear(struct rtl8169_private *tp); |
|
541 static void ec_poll(struct net_device *dev); |
|
542 static int rtl8169_poll(struct napi_struct *napi, int budget); |
|
543 |
|
544 static const unsigned int rtl8169_rx_config = |
|
545 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
|
546 |
|
547 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
548 { |
|
549 int i; |
|
550 |
|
551 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
552 |
|
553 for (i = 20; i > 0; i--) { |
|
554 /* |
|
555 * Check if the RTL8169 has completed writing to the specified |
|
556 * MII register. |
|
557 */ |
|
558 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
559 break; |
|
560 udelay(25); |
|
561 } |
|
562 } |
|
563 |
|
564 static int mdio_read(void __iomem *ioaddr, int reg_addr) |
|
565 { |
|
566 int i, value = -1; |
|
567 |
|
568 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
569 |
|
570 for (i = 20; i > 0; i--) { |
|
571 /* |
|
572 * Check if the RTL8169 has completed retrieving data from |
|
573 * the specified MII register. |
|
574 */ |
|
575 if (RTL_R32(PHYAR) & 0x80000000) { |
|
576 value = RTL_R32(PHYAR) & 0xffff; |
|
577 break; |
|
578 } |
|
579 udelay(25); |
|
580 } |
|
581 return value; |
|
582 } |
|
583 |
|
584 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
|
585 { |
|
586 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); |
|
587 } |
|
588 |
|
589 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m) |
|
590 { |
|
591 int val; |
|
592 |
|
593 val = mdio_read(ioaddr, reg_addr); |
|
594 mdio_write(ioaddr, reg_addr, (val | p) & ~m); |
|
595 } |
|
596 |
|
597 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
598 int val) |
|
599 { |
|
600 struct rtl8169_private *tp = netdev_priv(dev); |
|
601 void __iomem *ioaddr = tp->mmio_addr; |
|
602 |
|
603 mdio_write(ioaddr, location, val); |
|
604 } |
|
605 |
|
606 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
607 { |
|
608 struct rtl8169_private *tp = netdev_priv(dev); |
|
609 void __iomem *ioaddr = tp->mmio_addr; |
|
610 |
|
611 return mdio_read(ioaddr, location); |
|
612 } |
|
613 |
|
614 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
615 { |
|
616 unsigned int i; |
|
617 |
|
618 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
619 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
620 |
|
621 for (i = 0; i < 100; i++) { |
|
622 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
623 break; |
|
624 udelay(10); |
|
625 } |
|
626 } |
|
627 |
|
628 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
629 { |
|
630 u16 value = 0xffff; |
|
631 unsigned int i; |
|
632 |
|
633 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
634 |
|
635 for (i = 0; i < 100; i++) { |
|
636 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
637 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
638 break; |
|
639 } |
|
640 udelay(10); |
|
641 } |
|
642 |
|
643 return value; |
|
644 } |
|
645 |
|
646 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
647 { |
|
648 unsigned int i; |
|
649 |
|
650 RTL_W32(CSIDR, value); |
|
651 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
652 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
653 |
|
654 for (i = 0; i < 100; i++) { |
|
655 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
656 break; |
|
657 udelay(10); |
|
658 } |
|
659 } |
|
660 |
|
661 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
662 { |
|
663 u32 value = ~0x00; |
|
664 unsigned int i; |
|
665 |
|
666 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
667 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
668 |
|
669 for (i = 0; i < 100; i++) { |
|
670 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
671 value = RTL_R32(CSIDR); |
|
672 break; |
|
673 } |
|
674 udelay(10); |
|
675 } |
|
676 |
|
677 return value; |
|
678 } |
|
679 |
|
680 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
|
681 { |
|
682 u8 value = 0xff; |
|
683 unsigned int i; |
|
684 |
|
685 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
686 |
|
687 for (i = 0; i < 300; i++) { |
|
688 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { |
|
689 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; |
|
690 break; |
|
691 } |
|
692 udelay(100); |
|
693 } |
|
694 |
|
695 return value; |
|
696 } |
|
697 |
|
698 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
|
699 { |
|
700 RTL_W16(IntrMask, 0x0000); |
|
701 |
|
702 RTL_W16(IntrStatus, 0xffff); |
|
703 } |
|
704 |
|
705 static void rtl8169_asic_down(void __iomem *ioaddr) |
|
706 { |
|
707 RTL_W8(ChipCmd, 0x00); |
|
708 rtl8169_irq_mask_and_ack(ioaddr); |
|
709 RTL_R16(CPlusCmd); |
|
710 } |
|
711 |
|
712 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) |
|
713 { |
|
714 return RTL_R32(TBICSR) & TBIReset; |
|
715 } |
|
716 |
|
717 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) |
|
718 { |
|
719 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
|
720 } |
|
721 |
|
722 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
723 { |
|
724 return RTL_R32(TBICSR) & TBILinkOk; |
|
725 } |
|
726 |
|
727 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
728 { |
|
729 return RTL_R8(PHYstatus) & LinkStatus; |
|
730 } |
|
731 |
|
732 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) |
|
733 { |
|
734 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
735 } |
|
736 |
|
737 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) |
|
738 { |
|
739 unsigned int val; |
|
740 |
|
741 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
|
742 mdio_write(ioaddr, MII_BMCR, val & 0xffff); |
|
743 } |
|
744 |
|
745 static void rtl8169_check_link_status(struct net_device *dev, |
|
746 struct rtl8169_private *tp, |
|
747 void __iomem *ioaddr) |
|
748 { |
|
749 unsigned long flags; |
|
750 |
|
751 if (tp->ecdev) { |
|
752 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
753 } else { |
|
754 spin_lock_irqsave(&tp->lock, flags); |
|
755 if (tp->link_ok(ioaddr)) { |
|
756 netif_carrier_on(dev); |
|
757 if (netif_msg_ifup(tp)) |
|
758 printk(KERN_INFO PFX "%s: link up\n", dev->name); |
|
759 } else { |
|
760 if (netif_msg_ifdown(tp)) |
|
761 printk(KERN_INFO PFX "%s: link down\n", dev->name); |
|
762 netif_carrier_off(dev); |
|
763 } |
|
764 spin_unlock_irqrestore(&tp->lock, flags); |
|
765 } |
|
766 } |
|
767 |
|
768 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
769 { |
|
770 struct rtl8169_private *tp = netdev_priv(dev); |
|
771 void __iomem *ioaddr = tp->mmio_addr; |
|
772 u8 options; |
|
773 |
|
774 wol->wolopts = 0; |
|
775 |
|
776 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
777 wol->supported = WAKE_ANY; |
|
778 |
|
779 spin_lock_irq(&tp->lock); |
|
780 |
|
781 options = RTL_R8(Config1); |
|
782 if (!(options & PMEnable)) |
|
783 goto out_unlock; |
|
784 |
|
785 options = RTL_R8(Config3); |
|
786 if (options & LinkUp) |
|
787 wol->wolopts |= WAKE_PHY; |
|
788 if (options & MagicPacket) |
|
789 wol->wolopts |= WAKE_MAGIC; |
|
790 |
|
791 options = RTL_R8(Config5); |
|
792 if (options & UWF) |
|
793 wol->wolopts |= WAKE_UCAST; |
|
794 if (options & BWF) |
|
795 wol->wolopts |= WAKE_BCAST; |
|
796 if (options & MWF) |
|
797 wol->wolopts |= WAKE_MCAST; |
|
798 |
|
799 out_unlock: |
|
800 spin_unlock_irq(&tp->lock); |
|
801 } |
|
802 |
|
803 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
804 { |
|
805 struct rtl8169_private *tp = netdev_priv(dev); |
|
806 void __iomem *ioaddr = tp->mmio_addr; |
|
807 unsigned int i; |
|
808 static struct { |
|
809 u32 opt; |
|
810 u16 reg; |
|
811 u8 mask; |
|
812 } cfg[] = { |
|
813 { WAKE_ANY, Config1, PMEnable }, |
|
814 { WAKE_PHY, Config3, LinkUp }, |
|
815 { WAKE_MAGIC, Config3, MagicPacket }, |
|
816 { WAKE_UCAST, Config5, UWF }, |
|
817 { WAKE_BCAST, Config5, BWF }, |
|
818 { WAKE_MCAST, Config5, MWF }, |
|
819 { WAKE_ANY, Config5, LanWake } |
|
820 }; |
|
821 |
|
822 spin_lock_irq(&tp->lock); |
|
823 |
|
824 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
825 |
|
826 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
827 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
828 if (wol->wolopts & cfg[i].opt) |
|
829 options |= cfg[i].mask; |
|
830 RTL_W8(cfg[i].reg, options); |
|
831 } |
|
832 |
|
833 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
834 |
|
835 if (wol->wolopts) |
|
836 tp->features |= RTL_FEATURE_WOL; |
|
837 else |
|
838 tp->features &= ~RTL_FEATURE_WOL; |
|
839 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
840 |
|
841 spin_unlock_irq(&tp->lock); |
|
842 |
|
843 return 0; |
|
844 } |
|
845 |
|
846 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
847 struct ethtool_drvinfo *info) |
|
848 { |
|
849 struct rtl8169_private *tp = netdev_priv(dev); |
|
850 |
|
851 strcpy(info->driver, MODULENAME); |
|
852 strcpy(info->version, RTL8169_VERSION); |
|
853 strcpy(info->bus_info, pci_name(tp->pci_dev)); |
|
854 } |
|
855 |
|
856 static int rtl8169_get_regs_len(struct net_device *dev) |
|
857 { |
|
858 return R8169_REGS_SIZE; |
|
859 } |
|
860 |
|
861 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
862 u8 autoneg, u16 speed, u8 duplex) |
|
863 { |
|
864 struct rtl8169_private *tp = netdev_priv(dev); |
|
865 void __iomem *ioaddr = tp->mmio_addr; |
|
866 int ret = 0; |
|
867 u32 reg; |
|
868 |
|
869 reg = RTL_R32(TBICSR); |
|
870 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
871 (duplex == DUPLEX_FULL)) { |
|
872 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
873 } else if (autoneg == AUTONEG_ENABLE) |
|
874 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
875 else { |
|
876 if (netif_msg_link(tp)) { |
|
877 printk(KERN_WARNING "%s: " |
|
878 "incorrect speed setting refused in TBI mode\n", |
|
879 dev->name); |
|
880 } |
|
881 ret = -EOPNOTSUPP; |
|
882 } |
|
883 |
|
884 return ret; |
|
885 } |
|
886 |
|
887 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
888 u8 autoneg, u16 speed, u8 duplex) |
|
889 { |
|
890 struct rtl8169_private *tp = netdev_priv(dev); |
|
891 void __iomem *ioaddr = tp->mmio_addr; |
|
892 int giga_ctrl, bmcr; |
|
893 |
|
894 if (autoneg == AUTONEG_ENABLE) { |
|
895 int auto_nego; |
|
896 |
|
897 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
|
898 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
899 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
900 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
901 |
|
902 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
|
903 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
904 |
|
905 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
906 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && |
|
907 (tp->mac_version != RTL_GIGA_MAC_VER_08) && |
|
908 (tp->mac_version != RTL_GIGA_MAC_VER_09) && |
|
909 (tp->mac_version != RTL_GIGA_MAC_VER_10) && |
|
910 (tp->mac_version != RTL_GIGA_MAC_VER_13) && |
|
911 (tp->mac_version != RTL_GIGA_MAC_VER_14) && |
|
912 (tp->mac_version != RTL_GIGA_MAC_VER_15) && |
|
913 (tp->mac_version != RTL_GIGA_MAC_VER_16)) { |
|
914 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
|
915 } else if (netif_msg_link(tp)) { |
|
916 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
|
917 dev->name); |
|
918 } |
|
919 |
|
920 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
921 |
|
922 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
|
923 (tp->mac_version == RTL_GIGA_MAC_VER_12) || |
|
924 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { |
|
925 /* |
|
926 * Wake up the PHY. |
|
927 * Vendor specific (0x1f) and reserved (0x0e) MII |
|
928 * registers. |
|
929 */ |
|
930 mdio_write(ioaddr, 0x1f, 0x0000); |
|
931 mdio_write(ioaddr, 0x0e, 0x0000); |
|
932 } |
|
933 |
|
934 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
|
935 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); |
|
936 } else { |
|
937 giga_ctrl = 0; |
|
938 |
|
939 if (speed == SPEED_10) |
|
940 bmcr = 0; |
|
941 else if (speed == SPEED_100) |
|
942 bmcr = BMCR_SPEED100; |
|
943 else |
|
944 return -EINVAL; |
|
945 |
|
946 if (duplex == DUPLEX_FULL) |
|
947 bmcr |= BMCR_FULLDPLX; |
|
948 |
|
949 mdio_write(ioaddr, 0x1f, 0x0000); |
|
950 } |
|
951 |
|
952 tp->phy_1000_ctrl_reg = giga_ctrl; |
|
953 |
|
954 mdio_write(ioaddr, MII_BMCR, bmcr); |
|
955 |
|
956 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
957 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
958 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
959 mdio_write(ioaddr, 0x17, 0x2138); |
|
960 mdio_write(ioaddr, 0x0e, 0x0260); |
|
961 } else { |
|
962 mdio_write(ioaddr, 0x17, 0x2108); |
|
963 mdio_write(ioaddr, 0x0e, 0x0000); |
|
964 } |
|
965 } |
|
966 |
|
967 return 0; |
|
968 } |
|
969 |
|
970 static int rtl8169_set_speed(struct net_device *dev, |
|
971 u8 autoneg, u16 speed, u8 duplex) |
|
972 { |
|
973 struct rtl8169_private *tp = netdev_priv(dev); |
|
974 int ret; |
|
975 |
|
976 ret = tp->set_speed(dev, autoneg, speed, duplex); |
|
977 |
|
978 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
979 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
980 |
|
981 return ret; |
|
982 } |
|
983 |
|
984 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
985 { |
|
986 struct rtl8169_private *tp = netdev_priv(dev); |
|
987 unsigned long flags; |
|
988 int ret; |
|
989 |
|
990 spin_lock_irqsave(&tp->lock, flags); |
|
991 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); |
|
992 spin_unlock_irqrestore(&tp->lock, flags); |
|
993 |
|
994 return ret; |
|
995 } |
|
996 |
|
997 static u32 rtl8169_get_rx_csum(struct net_device *dev) |
|
998 { |
|
999 struct rtl8169_private *tp = netdev_priv(dev); |
|
1000 |
|
1001 return tp->cp_cmd & RxChkSum; |
|
1002 } |
|
1003 |
|
1004 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) |
|
1005 { |
|
1006 struct rtl8169_private *tp = netdev_priv(dev); |
|
1007 void __iomem *ioaddr = tp->mmio_addr; |
|
1008 unsigned long flags; |
|
1009 |
|
1010 spin_lock_irqsave(&tp->lock, flags); |
|
1011 |
|
1012 if (data) |
|
1013 tp->cp_cmd |= RxChkSum; |
|
1014 else |
|
1015 tp->cp_cmd &= ~RxChkSum; |
|
1016 |
|
1017 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1018 RTL_R16(CPlusCmd); |
|
1019 |
|
1020 spin_unlock_irqrestore(&tp->lock, flags); |
|
1021 |
|
1022 return 0; |
|
1023 } |
|
1024 |
|
1025 #ifdef CONFIG_R8169_VLAN |
|
1026 |
|
1027 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1028 struct sk_buff *skb) |
|
1029 { |
|
1030 return (tp->vlgrp && vlan_tx_tag_present(skb)) ? |
|
1031 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1032 } |
|
1033 |
|
1034 static void rtl8169_vlan_rx_register(struct net_device *dev, |
|
1035 struct vlan_group *grp) |
|
1036 { |
|
1037 struct rtl8169_private *tp = netdev_priv(dev); |
|
1038 void __iomem *ioaddr = tp->mmio_addr; |
|
1039 unsigned long flags; |
|
1040 |
|
1041 spin_lock_irqsave(&tp->lock, flags); |
|
1042 tp->vlgrp = grp; |
|
1043 /* |
|
1044 * Do not disable RxVlan on 8110SCd. |
|
1045 */ |
|
1046 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05)) |
|
1047 tp->cp_cmd |= RxVlan; |
|
1048 else |
|
1049 tp->cp_cmd &= ~RxVlan; |
|
1050 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1051 RTL_R16(CPlusCmd); |
|
1052 spin_unlock_irqrestore(&tp->lock, flags); |
|
1053 } |
|
1054 |
|
1055 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1056 struct sk_buff *skb) |
|
1057 { |
|
1058 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1059 struct vlan_group *vlgrp = tp->vlgrp; |
|
1060 int ret; |
|
1061 |
|
1062 if (vlgrp && (opts2 & RxVlanTag)) { |
|
1063 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); |
|
1064 ret = 0; |
|
1065 } else |
|
1066 ret = -1; |
|
1067 desc->opts2 = 0; |
|
1068 return ret; |
|
1069 } |
|
1070 |
|
1071 #else /* !CONFIG_R8169_VLAN */ |
|
1072 |
|
1073 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1074 struct sk_buff *skb) |
|
1075 { |
|
1076 return 0; |
|
1077 } |
|
1078 |
|
1079 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
|
1080 struct sk_buff *skb) |
|
1081 { |
|
1082 return -1; |
|
1083 } |
|
1084 |
|
1085 #endif |
|
1086 |
|
1087 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1088 { |
|
1089 struct rtl8169_private *tp = netdev_priv(dev); |
|
1090 void __iomem *ioaddr = tp->mmio_addr; |
|
1091 u32 status; |
|
1092 |
|
1093 cmd->supported = |
|
1094 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1095 cmd->port = PORT_FIBRE; |
|
1096 cmd->transceiver = XCVR_INTERNAL; |
|
1097 |
|
1098 status = RTL_R32(TBICSR); |
|
1099 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1100 cmd->autoneg = !!(status & TBINwEnable); |
|
1101 |
|
1102 cmd->speed = SPEED_1000; |
|
1103 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1104 |
|
1105 return 0; |
|
1106 } |
|
1107 |
|
1108 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1109 { |
|
1110 struct rtl8169_private *tp = netdev_priv(dev); |
|
1111 |
|
1112 return mii_ethtool_gset(&tp->mii, cmd); |
|
1113 } |
|
1114 |
|
1115 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1116 { |
|
1117 struct rtl8169_private *tp = netdev_priv(dev); |
|
1118 unsigned long flags; |
|
1119 int rc; |
|
1120 |
|
1121 spin_lock_irqsave(&tp->lock, flags); |
|
1122 |
|
1123 rc = tp->get_settings(dev, cmd); |
|
1124 |
|
1125 spin_unlock_irqrestore(&tp->lock, flags); |
|
1126 return rc; |
|
1127 } |
|
1128 |
|
1129 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1130 void *p) |
|
1131 { |
|
1132 struct rtl8169_private *tp = netdev_priv(dev); |
|
1133 unsigned long flags; |
|
1134 |
|
1135 if (regs->len > R8169_REGS_SIZE) |
|
1136 regs->len = R8169_REGS_SIZE; |
|
1137 |
|
1138 spin_lock_irqsave(&tp->lock, flags); |
|
1139 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1140 spin_unlock_irqrestore(&tp->lock, flags); |
|
1141 } |
|
1142 |
|
1143 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1144 { |
|
1145 struct rtl8169_private *tp = netdev_priv(dev); |
|
1146 |
|
1147 return tp->msg_enable; |
|
1148 } |
|
1149 |
|
1150 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1151 { |
|
1152 struct rtl8169_private *tp = netdev_priv(dev); |
|
1153 |
|
1154 tp->msg_enable = value; |
|
1155 } |
|
1156 |
|
1157 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1158 "tx_packets", |
|
1159 "rx_packets", |
|
1160 "tx_errors", |
|
1161 "rx_errors", |
|
1162 "rx_missed", |
|
1163 "align_errors", |
|
1164 "tx_single_collisions", |
|
1165 "tx_multi_collisions", |
|
1166 "unicast", |
|
1167 "broadcast", |
|
1168 "multicast", |
|
1169 "tx_aborted", |
|
1170 "tx_underrun", |
|
1171 }; |
|
1172 |
|
1173 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1174 { |
|
1175 switch (sset) { |
|
1176 case ETH_SS_STATS: |
|
1177 return ARRAY_SIZE(rtl8169_gstrings); |
|
1178 default: |
|
1179 return -EOPNOTSUPP; |
|
1180 } |
|
1181 } |
|
1182 |
|
1183 static void rtl8169_update_counters(struct net_device *dev) |
|
1184 { |
|
1185 struct rtl8169_private *tp = netdev_priv(dev); |
|
1186 void __iomem *ioaddr = tp->mmio_addr; |
|
1187 struct rtl8169_counters *counters; |
|
1188 dma_addr_t paddr; |
|
1189 u32 cmd; |
|
1190 int wait = 1000; |
|
1191 |
|
1192 /* |
|
1193 * Some chips are unable to dump tally counters when the receiver |
|
1194 * is disabled. |
|
1195 */ |
|
1196 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1197 return; |
|
1198 |
|
1199 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); |
|
1200 if (!counters) |
|
1201 return; |
|
1202 |
|
1203 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1204 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1205 RTL_W32(CounterAddrLow, cmd); |
|
1206 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1207 |
|
1208 while (wait--) { |
|
1209 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1210 /* copy updated counters */ |
|
1211 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1212 break; |
|
1213 } |
|
1214 udelay(10); |
|
1215 } |
|
1216 |
|
1217 RTL_W32(CounterAddrLow, 0); |
|
1218 RTL_W32(CounterAddrHigh, 0); |
|
1219 |
|
1220 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
|
1221 } |
|
1222 |
|
1223 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1224 struct ethtool_stats *stats, u64 *data) |
|
1225 { |
|
1226 struct rtl8169_private *tp = netdev_priv(dev); |
|
1227 |
|
1228 ASSERT_RTNL(); |
|
1229 |
|
1230 rtl8169_update_counters(dev); |
|
1231 |
|
1232 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1233 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1234 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1235 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1236 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1237 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1238 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1239 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1240 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1241 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1242 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1243 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1244 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1245 } |
|
1246 |
|
1247 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1248 { |
|
1249 switch(stringset) { |
|
1250 case ETH_SS_STATS: |
|
1251 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1252 break; |
|
1253 } |
|
1254 } |
|
1255 |
|
1256 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1257 .get_drvinfo = rtl8169_get_drvinfo, |
|
1258 .get_regs_len = rtl8169_get_regs_len, |
|
1259 .get_link = ethtool_op_get_link, |
|
1260 .get_settings = rtl8169_get_settings, |
|
1261 .set_settings = rtl8169_set_settings, |
|
1262 .get_msglevel = rtl8169_get_msglevel, |
|
1263 .set_msglevel = rtl8169_set_msglevel, |
|
1264 .get_rx_csum = rtl8169_get_rx_csum, |
|
1265 .set_rx_csum = rtl8169_set_rx_csum, |
|
1266 .set_tx_csum = ethtool_op_set_tx_csum, |
|
1267 .set_sg = ethtool_op_set_sg, |
|
1268 .set_tso = ethtool_op_set_tso, |
|
1269 .get_regs = rtl8169_get_regs, |
|
1270 .get_wol = rtl8169_get_wol, |
|
1271 .set_wol = rtl8169_set_wol, |
|
1272 .get_strings = rtl8169_get_strings, |
|
1273 .get_sset_count = rtl8169_get_sset_count, |
|
1274 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1275 }; |
|
1276 |
|
1277 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1278 void __iomem *ioaddr) |
|
1279 { |
|
1280 /* |
|
1281 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1282 * but they can be identified more specifically through the test below |
|
1283 * if needed: |
|
1284 * |
|
1285 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1286 * |
|
1287 * Same thing for the 8101Eb and the 8101Ec: |
|
1288 * |
|
1289 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1290 */ |
|
1291 const struct { |
|
1292 u32 mask; |
|
1293 u32 val; |
|
1294 int mac_version; |
|
1295 } mac_info[] = { |
|
1296 /* 8168D family. */ |
|
1297 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
1298 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
1299 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
1300 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
1301 |
|
1302 /* 8168C family. */ |
|
1303 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, |
|
1304 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1305 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1306 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1307 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1308 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1309 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1310 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1311 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1312 |
|
1313 /* 8168B family. */ |
|
1314 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1315 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1316 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1317 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1318 |
|
1319 /* 8101 family. */ |
|
1320 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1321 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1322 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1323 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1324 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1325 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1326 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1327 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1328 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1329 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1330 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1331 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1332 /* FIXME: where did these entries come from ? -- FR */ |
|
1333 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1334 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1335 |
|
1336 /* 8110 family. */ |
|
1337 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1338 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1339 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1340 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1341 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1342 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1343 |
|
1344 /* Catch-all */ |
|
1345 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1346 }, *p = mac_info; |
|
1347 u32 reg; |
|
1348 |
|
1349 reg = RTL_R32(TxConfig); |
|
1350 while ((reg & p->mask) != p->val) |
|
1351 p++; |
|
1352 tp->mac_version = p->mac_version; |
|
1353 } |
|
1354 |
|
1355 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1356 { |
|
1357 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
1358 } |
|
1359 |
|
1360 struct phy_reg { |
|
1361 u16 reg; |
|
1362 u16 val; |
|
1363 }; |
|
1364 |
|
1365 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) |
|
1366 { |
|
1367 while (len-- > 0) { |
|
1368 mdio_write(ioaddr, regs->reg, regs->val); |
|
1369 regs++; |
|
1370 } |
|
1371 } |
|
1372 |
|
1373 static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
|
1374 { |
|
1375 struct phy_reg phy_reg_init[] = { |
|
1376 { 0x1f, 0x0001 }, |
|
1377 { 0x06, 0x006e }, |
|
1378 { 0x08, 0x0708 }, |
|
1379 { 0x15, 0x4000 }, |
|
1380 { 0x18, 0x65c7 }, |
|
1381 |
|
1382 { 0x1f, 0x0001 }, |
|
1383 { 0x03, 0x00a1 }, |
|
1384 { 0x02, 0x0008 }, |
|
1385 { 0x01, 0x0120 }, |
|
1386 { 0x00, 0x1000 }, |
|
1387 { 0x04, 0x0800 }, |
|
1388 { 0x04, 0x0000 }, |
|
1389 |
|
1390 { 0x03, 0xff41 }, |
|
1391 { 0x02, 0xdf60 }, |
|
1392 { 0x01, 0x0140 }, |
|
1393 { 0x00, 0x0077 }, |
|
1394 { 0x04, 0x7800 }, |
|
1395 { 0x04, 0x7000 }, |
|
1396 |
|
1397 { 0x03, 0x802f }, |
|
1398 { 0x02, 0x4f02 }, |
|
1399 { 0x01, 0x0409 }, |
|
1400 { 0x00, 0xf0f9 }, |
|
1401 { 0x04, 0x9800 }, |
|
1402 { 0x04, 0x9000 }, |
|
1403 |
|
1404 { 0x03, 0xdf01 }, |
|
1405 { 0x02, 0xdf20 }, |
|
1406 { 0x01, 0xff95 }, |
|
1407 { 0x00, 0xba00 }, |
|
1408 { 0x04, 0xa800 }, |
|
1409 { 0x04, 0xa000 }, |
|
1410 |
|
1411 { 0x03, 0xff41 }, |
|
1412 { 0x02, 0xdf20 }, |
|
1413 { 0x01, 0x0140 }, |
|
1414 { 0x00, 0x00bb }, |
|
1415 { 0x04, 0xb800 }, |
|
1416 { 0x04, 0xb000 }, |
|
1417 |
|
1418 { 0x03, 0xdf41 }, |
|
1419 { 0x02, 0xdc60 }, |
|
1420 { 0x01, 0x6340 }, |
|
1421 { 0x00, 0x007d }, |
|
1422 { 0x04, 0xd800 }, |
|
1423 { 0x04, 0xd000 }, |
|
1424 |
|
1425 { 0x03, 0xdf01 }, |
|
1426 { 0x02, 0xdf20 }, |
|
1427 { 0x01, 0x100a }, |
|
1428 { 0x00, 0xa0ff }, |
|
1429 { 0x04, 0xf800 }, |
|
1430 { 0x04, 0xf000 }, |
|
1431 |
|
1432 { 0x1f, 0x0000 }, |
|
1433 { 0x0b, 0x0000 }, |
|
1434 { 0x00, 0x9200 } |
|
1435 }; |
|
1436 |
|
1437 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1438 } |
|
1439 |
|
1440 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
|
1441 { |
|
1442 struct phy_reg phy_reg_init[] = { |
|
1443 { 0x1f, 0x0002 }, |
|
1444 { 0x01, 0x90d0 }, |
|
1445 { 0x1f, 0x0000 } |
|
1446 }; |
|
1447 |
|
1448 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1449 } |
|
1450 |
|
1451 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, |
|
1452 void __iomem *ioaddr) |
|
1453 { |
|
1454 struct pci_dev *pdev = tp->pci_dev; |
|
1455 u16 vendor_id, device_id; |
|
1456 |
|
1457 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); |
|
1458 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); |
|
1459 |
|
1460 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) |
|
1461 return; |
|
1462 |
|
1463 mdio_write(ioaddr, 0x1f, 0x0001); |
|
1464 mdio_write(ioaddr, 0x10, 0xf01b); |
|
1465 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1466 } |
|
1467 |
|
1468 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, |
|
1469 void __iomem *ioaddr) |
|
1470 { |
|
1471 struct phy_reg phy_reg_init[] = { |
|
1472 { 0x1f, 0x0001 }, |
|
1473 { 0x04, 0x0000 }, |
|
1474 { 0x03, 0x00a1 }, |
|
1475 { 0x02, 0x0008 }, |
|
1476 { 0x01, 0x0120 }, |
|
1477 { 0x00, 0x1000 }, |
|
1478 { 0x04, 0x0800 }, |
|
1479 { 0x04, 0x9000 }, |
|
1480 { 0x03, 0x802f }, |
|
1481 { 0x02, 0x4f02 }, |
|
1482 { 0x01, 0x0409 }, |
|
1483 { 0x00, 0xf099 }, |
|
1484 { 0x04, 0x9800 }, |
|
1485 { 0x04, 0xa000 }, |
|
1486 { 0x03, 0xdf01 }, |
|
1487 { 0x02, 0xdf20 }, |
|
1488 { 0x01, 0xff95 }, |
|
1489 { 0x00, 0xba00 }, |
|
1490 { 0x04, 0xa800 }, |
|
1491 { 0x04, 0xf000 }, |
|
1492 { 0x03, 0xdf01 }, |
|
1493 { 0x02, 0xdf20 }, |
|
1494 { 0x01, 0x101a }, |
|
1495 { 0x00, 0xa0ff }, |
|
1496 { 0x04, 0xf800 }, |
|
1497 { 0x04, 0x0000 }, |
|
1498 { 0x1f, 0x0000 }, |
|
1499 |
|
1500 { 0x1f, 0x0001 }, |
|
1501 { 0x10, 0xf41b }, |
|
1502 { 0x14, 0xfb54 }, |
|
1503 { 0x18, 0xf5c7 }, |
|
1504 { 0x1f, 0x0000 }, |
|
1505 |
|
1506 { 0x1f, 0x0001 }, |
|
1507 { 0x17, 0x0cc0 }, |
|
1508 { 0x1f, 0x0000 } |
|
1509 }; |
|
1510 |
|
1511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1512 |
|
1513 rtl8169scd_hw_phy_config_quirk(tp, ioaddr); |
|
1514 } |
|
1515 |
|
1516 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) |
|
1517 { |
|
1518 struct phy_reg phy_reg_init[] = { |
|
1519 { 0x1f, 0x0001 }, |
|
1520 { 0x04, 0x0000 }, |
|
1521 { 0x03, 0x00a1 }, |
|
1522 { 0x02, 0x0008 }, |
|
1523 { 0x01, 0x0120 }, |
|
1524 { 0x00, 0x1000 }, |
|
1525 { 0x04, 0x0800 }, |
|
1526 { 0x04, 0x9000 }, |
|
1527 { 0x03, 0x802f }, |
|
1528 { 0x02, 0x4f02 }, |
|
1529 { 0x01, 0x0409 }, |
|
1530 { 0x00, 0xf099 }, |
|
1531 { 0x04, 0x9800 }, |
|
1532 { 0x04, 0xa000 }, |
|
1533 { 0x03, 0xdf01 }, |
|
1534 { 0x02, 0xdf20 }, |
|
1535 { 0x01, 0xff95 }, |
|
1536 { 0x00, 0xba00 }, |
|
1537 { 0x04, 0xa800 }, |
|
1538 { 0x04, 0xf000 }, |
|
1539 { 0x03, 0xdf01 }, |
|
1540 { 0x02, 0xdf20 }, |
|
1541 { 0x01, 0x101a }, |
|
1542 { 0x00, 0xa0ff }, |
|
1543 { 0x04, 0xf800 }, |
|
1544 { 0x04, 0x0000 }, |
|
1545 { 0x1f, 0x0000 }, |
|
1546 |
|
1547 { 0x1f, 0x0001 }, |
|
1548 { 0x0b, 0x8480 }, |
|
1549 { 0x1f, 0x0000 }, |
|
1550 |
|
1551 { 0x1f, 0x0001 }, |
|
1552 { 0x18, 0x67c7 }, |
|
1553 { 0x04, 0x2000 }, |
|
1554 { 0x03, 0x002f }, |
|
1555 { 0x02, 0x4360 }, |
|
1556 { 0x01, 0x0109 }, |
|
1557 { 0x00, 0x3022 }, |
|
1558 { 0x04, 0x2800 }, |
|
1559 { 0x1f, 0x0000 }, |
|
1560 |
|
1561 { 0x1f, 0x0001 }, |
|
1562 { 0x17, 0x0cc0 }, |
|
1563 { 0x1f, 0x0000 } |
|
1564 }; |
|
1565 |
|
1566 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1567 } |
|
1568 |
|
1569 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
|
1570 { |
|
1571 struct phy_reg phy_reg_init[] = { |
|
1572 { 0x10, 0xf41b }, |
|
1573 { 0x1f, 0x0000 } |
|
1574 }; |
|
1575 |
|
1576 mdio_write(ioaddr, 0x1f, 0x0001); |
|
1577 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1578 |
|
1579 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1580 } |
|
1581 |
|
1582 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) |
|
1583 { |
|
1584 struct phy_reg phy_reg_init[] = { |
|
1585 { 0x1f, 0x0001 }, |
|
1586 { 0x10, 0xf41b }, |
|
1587 { 0x1f, 0x0000 } |
|
1588 }; |
|
1589 |
|
1590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1591 } |
|
1592 |
|
1593 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
|
1594 { |
|
1595 struct phy_reg phy_reg_init[] = { |
|
1596 { 0x1f, 0x0000 }, |
|
1597 { 0x1d, 0x0f00 }, |
|
1598 { 0x1f, 0x0002 }, |
|
1599 { 0x0c, 0x1ec8 }, |
|
1600 { 0x1f, 0x0000 } |
|
1601 }; |
|
1602 |
|
1603 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1604 } |
|
1605 |
|
1606 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
|
1607 { |
|
1608 struct phy_reg phy_reg_init[] = { |
|
1609 { 0x1f, 0x0001 }, |
|
1610 { 0x1d, 0x3d98 }, |
|
1611 { 0x1f, 0x0000 } |
|
1612 }; |
|
1613 |
|
1614 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1615 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1616 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1617 |
|
1618 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1619 } |
|
1620 |
|
1621 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
|
1622 { |
|
1623 struct phy_reg phy_reg_init[] = { |
|
1624 { 0x1f, 0x0001 }, |
|
1625 { 0x12, 0x2300 }, |
|
1626 { 0x1f, 0x0002 }, |
|
1627 { 0x00, 0x88d4 }, |
|
1628 { 0x01, 0x82b1 }, |
|
1629 { 0x03, 0x7002 }, |
|
1630 { 0x08, 0x9e30 }, |
|
1631 { 0x09, 0x01f0 }, |
|
1632 { 0x0a, 0x5500 }, |
|
1633 { 0x0c, 0x00c8 }, |
|
1634 { 0x1f, 0x0003 }, |
|
1635 { 0x12, 0xc096 }, |
|
1636 { 0x16, 0x000a }, |
|
1637 { 0x1f, 0x0000 }, |
|
1638 { 0x1f, 0x0000 }, |
|
1639 { 0x09, 0x2000 }, |
|
1640 { 0x09, 0x0000 } |
|
1641 }; |
|
1642 |
|
1643 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1644 |
|
1645 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1646 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1647 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1648 } |
|
1649 |
|
1650 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
|
1651 { |
|
1652 struct phy_reg phy_reg_init[] = { |
|
1653 { 0x1f, 0x0001 }, |
|
1654 { 0x12, 0x2300 }, |
|
1655 { 0x03, 0x802f }, |
|
1656 { 0x02, 0x4f02 }, |
|
1657 { 0x01, 0x0409 }, |
|
1658 { 0x00, 0xf099 }, |
|
1659 { 0x04, 0x9800 }, |
|
1660 { 0x04, 0x9000 }, |
|
1661 { 0x1d, 0x3d98 }, |
|
1662 { 0x1f, 0x0002 }, |
|
1663 { 0x0c, 0x7eb8 }, |
|
1664 { 0x06, 0x0761 }, |
|
1665 { 0x1f, 0x0003 }, |
|
1666 { 0x16, 0x0f0a }, |
|
1667 { 0x1f, 0x0000 } |
|
1668 }; |
|
1669 |
|
1670 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1671 |
|
1672 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1673 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1674 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1675 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1676 } |
|
1677 |
|
1678 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
|
1679 { |
|
1680 struct phy_reg phy_reg_init[] = { |
|
1681 { 0x1f, 0x0001 }, |
|
1682 { 0x12, 0x2300 }, |
|
1683 { 0x1d, 0x3d98 }, |
|
1684 { 0x1f, 0x0002 }, |
|
1685 { 0x0c, 0x7eb8 }, |
|
1686 { 0x06, 0x5461 }, |
|
1687 { 0x1f, 0x0003 }, |
|
1688 { 0x16, 0x0f0a }, |
|
1689 { 0x1f, 0x0000 } |
|
1690 }; |
|
1691 |
|
1692 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
1693 |
|
1694 mdio_patch(ioaddr, 0x16, 1 << 0); |
|
1695 mdio_patch(ioaddr, 0x14, 1 << 5); |
|
1696 mdio_patch(ioaddr, 0x0d, 1 << 5); |
|
1697 mdio_write(ioaddr, 0x1f, 0x0000); |
|
1698 } |
|
1699 |
|
1700 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
|
1701 { |
|
1702 rtl8168c_3_hw_phy_config(ioaddr); |
|
1703 } |
|
1704 |
|
1705 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) |
|
1706 { |
|
1707 static struct phy_reg phy_reg_init_0[] = { |
|
1708 { 0x1f, 0x0001 }, |
|
1709 { 0x06, 0x4064 }, |
|
1710 { 0x07, 0x2863 }, |
|
1711 { 0x08, 0x059c }, |
|
1712 { 0x09, 0x26b4 }, |
|
1713 { 0x0a, 0x6a19 }, |
|
1714 { 0x0b, 0xdcc8 }, |
|
1715 { 0x10, 0xf06d }, |
|
1716 { 0x14, 0x7f68 }, |
|
1717 { 0x18, 0x7fd9 }, |
|
1718 { 0x1c, 0xf0ff }, |
|
1719 { 0x1d, 0x3d9c }, |
|
1720 { 0x1f, 0x0003 }, |
|
1721 { 0x12, 0xf49f }, |
|
1722 { 0x13, 0x070b }, |
|
1723 { 0x1a, 0x05ad }, |
|
1724 { 0x14, 0x94c0 } |
|
1725 }; |
|
1726 static struct phy_reg phy_reg_init_1[] = { |
|
1727 { 0x1f, 0x0002 }, |
|
1728 { 0x06, 0x5561 }, |
|
1729 { 0x1f, 0x0005 }, |
|
1730 { 0x05, 0x8332 }, |
|
1731 { 0x06, 0x5561 } |
|
1732 }; |
|
1733 static struct phy_reg phy_reg_init_2[] = { |
|
1734 { 0x1f, 0x0005 }, |
|
1735 { 0x05, 0xffc2 }, |
|
1736 { 0x1f, 0x0005 }, |
|
1737 { 0x05, 0x8000 }, |
|
1738 { 0x06, 0xf8f9 }, |
|
1739 { 0x06, 0xfaef }, |
|
1740 { 0x06, 0x59ee }, |
|
1741 { 0x06, 0xf8ea }, |
|
1742 { 0x06, 0x00ee }, |
|
1743 { 0x06, 0xf8eb }, |
|
1744 { 0x06, 0x00e0 }, |
|
1745 { 0x06, 0xf87c }, |
|
1746 { 0x06, 0xe1f8 }, |
|
1747 { 0x06, 0x7d59 }, |
|
1748 { 0x06, 0x0fef }, |
|
1749 { 0x06, 0x0139 }, |
|
1750 { 0x06, 0x029e }, |
|
1751 { 0x06, 0x06ef }, |
|
1752 { 0x06, 0x1039 }, |
|
1753 { 0x06, 0x089f }, |
|
1754 { 0x06, 0x2aee }, |
|
1755 { 0x06, 0xf8ea }, |
|
1756 { 0x06, 0x00ee }, |
|
1757 { 0x06, 0xf8eb }, |
|
1758 { 0x06, 0x01e0 }, |
|
1759 { 0x06, 0xf87c }, |
|
1760 { 0x06, 0xe1f8 }, |
|
1761 { 0x06, 0x7d58 }, |
|
1762 { 0x06, 0x409e }, |
|
1763 { 0x06, 0x0f39 }, |
|
1764 { 0x06, 0x46aa }, |
|
1765 { 0x06, 0x0bbf }, |
|
1766 { 0x06, 0x8290 }, |
|
1767 { 0x06, 0xd682 }, |
|
1768 { 0x06, 0x9802 }, |
|
1769 { 0x06, 0x014f }, |
|
1770 { 0x06, 0xae09 }, |
|
1771 { 0x06, 0xbf82 }, |
|
1772 { 0x06, 0x98d6 }, |
|
1773 { 0x06, 0x82a0 }, |
|
1774 { 0x06, 0x0201 }, |
|
1775 { 0x06, 0x4fef }, |
|
1776 { 0x06, 0x95fe }, |
|
1777 { 0x06, 0xfdfc }, |
|
1778 { 0x06, 0x05f8 }, |
|
1779 { 0x06, 0xf9fa }, |
|
1780 { 0x06, 0xeef8 }, |
|
1781 { 0x06, 0xea00 }, |
|
1782 { 0x06, 0xeef8 }, |
|
1783 { 0x06, 0xeb00 }, |
|
1784 { 0x06, 0xe2f8 }, |
|
1785 { 0x06, 0x7ce3 }, |
|
1786 { 0x06, 0xf87d }, |
|
1787 { 0x06, 0xa511 }, |
|
1788 { 0x06, 0x1112 }, |
|
1789 { 0x06, 0xd240 }, |
|
1790 { 0x06, 0xd644 }, |
|
1791 { 0x06, 0x4402 }, |
|
1792 { 0x06, 0x8217 }, |
|
1793 { 0x06, 0xd2a0 }, |
|
1794 { 0x06, 0xd6aa }, |
|
1795 { 0x06, 0xaa02 }, |
|
1796 { 0x06, 0x8217 }, |
|
1797 { 0x06, 0xae0f }, |
|
1798 { 0x06, 0xa544 }, |
|
1799 { 0x06, 0x4402 }, |
|
1800 { 0x06, 0xae4d }, |
|
1801 { 0x06, 0xa5aa }, |
|
1802 { 0x06, 0xaa02 }, |
|
1803 { 0x06, 0xae47 }, |
|
1804 { 0x06, 0xaf82 }, |
|
1805 { 0x06, 0x13ee }, |
|
1806 { 0x06, 0x834e }, |
|
1807 { 0x06, 0x00ee }, |
|
1808 { 0x06, 0x834d }, |
|
1809 { 0x06, 0x0fee }, |
|
1810 { 0x06, 0x834c }, |
|
1811 { 0x06, 0x0fee }, |
|
1812 { 0x06, 0x834f }, |
|
1813 { 0x06, 0x00ee }, |
|
1814 { 0x06, 0x8351 }, |
|
1815 { 0x06, 0x00ee }, |
|
1816 { 0x06, 0x834a }, |
|
1817 { 0x06, 0xffee }, |
|
1818 { 0x06, 0x834b }, |
|
1819 { 0x06, 0xffe0 }, |
|
1820 { 0x06, 0x8330 }, |
|
1821 { 0x06, 0xe183 }, |
|
1822 { 0x06, 0x3158 }, |
|
1823 { 0x06, 0xfee4 }, |
|
1824 { 0x06, 0xf88a }, |
|
1825 { 0x06, 0xe5f8 }, |
|
1826 { 0x06, 0x8be0 }, |
|
1827 { 0x06, 0x8332 }, |
|
1828 { 0x06, 0xe183 }, |
|
1829 { 0x06, 0x3359 }, |
|
1830 { 0x06, 0x0fe2 }, |
|
1831 { 0x06, 0x834d }, |
|
1832 { 0x06, 0x0c24 }, |
|
1833 { 0x06, 0x5af0 }, |
|
1834 { 0x06, 0x1e12 }, |
|
1835 { 0x06, 0xe4f8 }, |
|
1836 { 0x06, 0x8ce5 }, |
|
1837 { 0x06, 0xf88d }, |
|
1838 { 0x06, 0xaf82 }, |
|
1839 { 0x06, 0x13e0 }, |
|
1840 { 0x06, 0x834f }, |
|
1841 { 0x06, 0x10e4 }, |
|
1842 { 0x06, 0x834f }, |
|
1843 { 0x06, 0xe083 }, |
|
1844 { 0x06, 0x4e78 }, |
|
1845 { 0x06, 0x009f }, |
|
1846 { 0x06, 0x0ae0 }, |
|
1847 { 0x06, 0x834f }, |
|
1848 { 0x06, 0xa010 }, |
|
1849 { 0x06, 0xa5ee }, |
|
1850 { 0x06, 0x834e }, |
|
1851 { 0x06, 0x01e0 }, |
|
1852 { 0x06, 0x834e }, |
|
1853 { 0x06, 0x7805 }, |
|
1854 { 0x06, 0x9e9a }, |
|
1855 { 0x06, 0xe083 }, |
|
1856 { 0x06, 0x4e78 }, |
|
1857 { 0x06, 0x049e }, |
|
1858 { 0x06, 0x10e0 }, |
|
1859 { 0x06, 0x834e }, |
|
1860 { 0x06, 0x7803 }, |
|
1861 { 0x06, 0x9e0f }, |
|
1862 { 0x06, 0xe083 }, |
|
1863 { 0x06, 0x4e78 }, |
|
1864 { 0x06, 0x019e }, |
|
1865 { 0x06, 0x05ae }, |
|
1866 { 0x06, 0x0caf }, |
|
1867 { 0x06, 0x81f8 }, |
|
1868 { 0x06, 0xaf81 }, |
|
1869 { 0x06, 0xa3af }, |
|
1870 { 0x06, 0x81dc }, |
|
1871 { 0x06, 0xaf82 }, |
|
1872 { 0x06, 0x13ee }, |
|
1873 { 0x06, 0x8348 }, |
|
1874 { 0x06, 0x00ee }, |
|
1875 { 0x06, 0x8349 }, |
|
1876 { 0x06, 0x00e0 }, |
|
1877 { 0x06, 0x8351 }, |
|
1878 { 0x06, 0x10e4 }, |
|
1879 { 0x06, 0x8351 }, |
|
1880 { 0x06, 0x5801 }, |
|
1881 { 0x06, 0x9fea }, |
|
1882 { 0x06, 0xd000 }, |
|
1883 { 0x06, 0xd180 }, |
|
1884 { 0x06, 0x1f66 }, |
|
1885 { 0x06, 0xe2f8 }, |
|
1886 { 0x06, 0xeae3 }, |
|
1887 { 0x06, 0xf8eb }, |
|
1888 { 0x06, 0x5af8 }, |
|
1889 { 0x06, 0x1e20 }, |
|
1890 { 0x06, 0xe6f8 }, |
|
1891 { 0x06, 0xeae5 }, |
|
1892 { 0x06, 0xf8eb }, |
|
1893 { 0x06, 0xd302 }, |
|
1894 { 0x06, 0xb3fe }, |
|
1895 { 0x06, 0xe2f8 }, |
|
1896 { 0x06, 0x7cef }, |
|
1897 { 0x06, 0x325b }, |
|
1898 { 0x06, 0x80e3 }, |
|
1899 { 0x06, 0xf87d }, |
|
1900 { 0x06, 0x9e03 }, |
|
1901 { 0x06, 0x7dff }, |
|
1902 { 0x06, 0xff0d }, |
|
1903 { 0x06, 0x581c }, |
|
1904 { 0x06, 0x551a }, |
|
1905 { 0x06, 0x6511 }, |
|
1906 { 0x06, 0xa190 }, |
|
1907 { 0x06, 0xd3e2 }, |
|
1908 { 0x06, 0x8348 }, |
|
1909 { 0x06, 0xe383 }, |
|
1910 { 0x06, 0x491b }, |
|
1911 { 0x06, 0x56ab }, |
|
1912 { 0x06, 0x08ef }, |
|
1913 { 0x06, 0x56e6 }, |
|
1914 { 0x06, 0x8348 }, |
|
1915 { 0x06, 0xe783 }, |
|
1916 { 0x06, 0x4910 }, |
|
1917 { 0x06, 0xd180 }, |
|
1918 { 0x06, 0x1f66 }, |
|
1919 { 0x06, 0xa004 }, |
|
1920 { 0x06, 0xb9e2 }, |
|
1921 { 0x06, 0x8348 }, |
|
1922 { 0x06, 0xe383 }, |
|
1923 { 0x06, 0x49ef }, |
|
1924 { 0x06, 0x65e2 }, |
|
1925 { 0x06, 0x834a }, |
|
1926 { 0x06, 0xe383 }, |
|
1927 { 0x06, 0x4b1b }, |
|
1928 { 0x06, 0x56aa }, |
|
1929 { 0x06, 0x0eef }, |
|
1930 { 0x06, 0x56e6 }, |
|
1931 { 0x06, 0x834a }, |
|
1932 { 0x06, 0xe783 }, |
|
1933 { 0x06, 0x4be2 }, |
|
1934 { 0x06, 0x834d }, |
|
1935 { 0x06, 0xe683 }, |
|
1936 { 0x06, 0x4ce0 }, |
|
1937 { 0x06, 0x834d }, |
|
1938 { 0x06, 0xa000 }, |
|
1939 { 0x06, 0x0caf }, |
|
1940 { 0x06, 0x81dc }, |
|
1941 { 0x06, 0xe083 }, |
|
1942 { 0x06, 0x4d10 }, |
|
1943 { 0x06, 0xe483 }, |
|
1944 { 0x06, 0x4dae }, |
|
1945 { 0x06, 0x0480 }, |
|
1946 { 0x06, 0xe483 }, |
|
1947 { 0x06, 0x4de0 }, |
|
1948 { 0x06, 0x834e }, |
|
1949 { 0x06, 0x7803 }, |
|
1950 { 0x06, 0x9e0b }, |
|
1951 { 0x06, 0xe083 }, |
|
1952 { 0x06, 0x4e78 }, |
|
1953 { 0x06, 0x049e }, |
|
1954 { 0x06, 0x04ee }, |
|
1955 { 0x06, 0x834e }, |
|
1956 { 0x06, 0x02e0 }, |
|
1957 { 0x06, 0x8332 }, |
|
1958 { 0x06, 0xe183 }, |
|
1959 { 0x06, 0x3359 }, |
|
1960 { 0x06, 0x0fe2 }, |
|
1961 { 0x06, 0x834d }, |
|
1962 { 0x06, 0x0c24 }, |
|
1963 { 0x06, 0x5af0 }, |
|
1964 { 0x06, 0x1e12 }, |
|
1965 { 0x06, 0xe4f8 }, |
|
1966 { 0x06, 0x8ce5 }, |
|
1967 { 0x06, 0xf88d }, |
|
1968 { 0x06, 0xe083 }, |
|
1969 { 0x06, 0x30e1 }, |
|
1970 { 0x06, 0x8331 }, |
|
1971 { 0x06, 0x6801 }, |
|
1972 { 0x06, 0xe4f8 }, |
|
1973 { 0x06, 0x8ae5 }, |
|
1974 { 0x06, 0xf88b }, |
|
1975 { 0x06, 0xae37 }, |
|
1976 { 0x06, 0xee83 }, |
|
1977 { 0x06, 0x4e03 }, |
|
1978 { 0x06, 0xe083 }, |
|
1979 { 0x06, 0x4ce1 }, |
|
1980 { 0x06, 0x834d }, |
|
1981 { 0x06, 0x1b01 }, |
|
1982 { 0x06, 0x9e04 }, |
|
1983 { 0x06, 0xaaa1 }, |
|
1984 { 0x06, 0xaea8 }, |
|
1985 { 0x06, 0xee83 }, |
|
1986 { 0x06, 0x4e04 }, |
|
1987 { 0x06, 0xee83 }, |
|
1988 { 0x06, 0x4f00 }, |
|
1989 { 0x06, 0xaeab }, |
|
1990 { 0x06, 0xe083 }, |
|
1991 { 0x06, 0x4f78 }, |
|
1992 { 0x06, 0x039f }, |
|
1993 { 0x06, 0x14ee }, |
|
1994 { 0x06, 0x834e }, |
|
1995 { 0x06, 0x05d2 }, |
|
1996 { 0x06, 0x40d6 }, |
|
1997 { 0x06, 0x5554 }, |
|
1998 { 0x06, 0x0282 }, |
|
1999 { 0x06, 0x17d2 }, |
|
2000 { 0x06, 0xa0d6 }, |
|
2001 { 0x06, 0xba00 }, |
|
2002 { 0x06, 0x0282 }, |
|
2003 { 0x06, 0x17fe }, |
|
2004 { 0x06, 0xfdfc }, |
|
2005 { 0x06, 0x05f8 }, |
|
2006 { 0x06, 0xe0f8 }, |
|
2007 { 0x06, 0x60e1 }, |
|
2008 { 0x06, 0xf861 }, |
|
2009 { 0x06, 0x6802 }, |
|
2010 { 0x06, 0xe4f8 }, |
|
2011 { 0x06, 0x60e5 }, |
|
2012 { 0x06, 0xf861 }, |
|
2013 { 0x06, 0xe0f8 }, |
|
2014 { 0x06, 0x48e1 }, |
|
2015 { 0x06, 0xf849 }, |
|
2016 { 0x06, 0x580f }, |
|
2017 { 0x06, 0x1e02 }, |
|
2018 { 0x06, 0xe4f8 }, |
|
2019 { 0x06, 0x48e5 }, |
|
2020 { 0x06, 0xf849 }, |
|
2021 { 0x06, 0xd000 }, |
|
2022 { 0x06, 0x0282 }, |
|
2023 { 0x06, 0x5bbf }, |
|
2024 { 0x06, 0x8350 }, |
|
2025 { 0x06, 0xef46 }, |
|
2026 { 0x06, 0xdc19 }, |
|
2027 { 0x06, 0xddd0 }, |
|
2028 { 0x06, 0x0102 }, |
|
2029 { 0x06, 0x825b }, |
|
2030 { 0x06, 0x0282 }, |
|
2031 { 0x06, 0x77e0 }, |
|
2032 { 0x06, 0xf860 }, |
|
2033 { 0x06, 0xe1f8 }, |
|
2034 { 0x06, 0x6158 }, |
|
2035 { 0x06, 0xfde4 }, |
|
2036 { 0x06, 0xf860 }, |
|
2037 { 0x06, 0xe5f8 }, |
|
2038 { 0x06, 0x61fc }, |
|
2039 { 0x06, 0x04f9 }, |
|
2040 { 0x06, 0xfafb }, |
|
2041 { 0x06, 0xc6bf }, |
|
2042 { 0x06, 0xf840 }, |
|
2043 { 0x06, 0xbe83 }, |
|
2044 { 0x06, 0x50a0 }, |
|
2045 { 0x06, 0x0101 }, |
|
2046 { 0x06, 0x071b }, |
|
2047 { 0x06, 0x89cf }, |
|
2048 { 0x06, 0xd208 }, |
|
2049 { 0x06, 0xebdb }, |
|
2050 { 0x06, 0x19b2 }, |
|
2051 { 0x06, 0xfbff }, |
|
2052 { 0x06, 0xfefd }, |
|
2053 { 0x06, 0x04f8 }, |
|
2054 { 0x06, 0xe0f8 }, |
|
2055 { 0x06, 0x48e1 }, |
|
2056 { 0x06, 0xf849 }, |
|
2057 { 0x06, 0x6808 }, |
|
2058 { 0x06, 0xe4f8 }, |
|
2059 { 0x06, 0x48e5 }, |
|
2060 { 0x06, 0xf849 }, |
|
2061 { 0x06, 0x58f7 }, |
|
2062 { 0x06, 0xe4f8 }, |
|
2063 { 0x06, 0x48e5 }, |
|
2064 { 0x06, 0xf849 }, |
|
2065 { 0x06, 0xfc04 }, |
|
2066 { 0x06, 0x4d20 }, |
|
2067 { 0x06, 0x0002 }, |
|
2068 { 0x06, 0x4e22 }, |
|
2069 { 0x06, 0x0002 }, |
|
2070 { 0x06, 0x4ddf }, |
|
2071 { 0x06, 0xff01 }, |
|
2072 { 0x06, 0x4edd }, |
|
2073 { 0x06, 0xff01 }, |
|
2074 { 0x05, 0x83d4 }, |
|
2075 { 0x06, 0x8000 }, |
|
2076 { 0x05, 0x83d8 }, |
|
2077 { 0x06, 0x8051 }, |
|
2078 { 0x02, 0x6010 }, |
|
2079 { 0x03, 0xdc00 }, |
|
2080 { 0x05, 0xfff6 }, |
|
2081 { 0x06, 0x00fc }, |
|
2082 { 0x1f, 0x0000 }, |
|
2083 |
|
2084 { 0x1f, 0x0000 }, |
|
2085 { 0x0d, 0xf880 }, |
|
2086 { 0x1f, 0x0000 } |
|
2087 }; |
|
2088 |
|
2089 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2090 |
|
2091 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2092 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef); |
|
2093 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00); |
|
2094 |
|
2095 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); |
|
2096 |
|
2097 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2098 struct phy_reg phy_reg_init[] = { |
|
2099 { 0x1f, 0x0002 }, |
|
2100 { 0x05, 0x669a }, |
|
2101 { 0x1f, 0x0005 }, |
|
2102 { 0x05, 0x8330 }, |
|
2103 { 0x06, 0x669a }, |
|
2104 { 0x1f, 0x0002 } |
|
2105 }; |
|
2106 int val; |
|
2107 |
|
2108 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2109 |
|
2110 val = mdio_read(ioaddr, 0x0d); |
|
2111 |
|
2112 if ((val & 0x00ff) != 0x006c) { |
|
2113 u32 set[] = { |
|
2114 0x0065, 0x0066, 0x0067, 0x0068, |
|
2115 0x0069, 0x006a, 0x006b, 0x006c |
|
2116 }; |
|
2117 int i; |
|
2118 |
|
2119 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2120 |
|
2121 val &= 0xff00; |
|
2122 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2123 mdio_write(ioaddr, 0x0d, val | set[i]); |
|
2124 } |
|
2125 } else { |
|
2126 struct phy_reg phy_reg_init[] = { |
|
2127 { 0x1f, 0x0002 }, |
|
2128 { 0x05, 0x6662 }, |
|
2129 { 0x1f, 0x0005 }, |
|
2130 { 0x05, 0x8330 }, |
|
2131 { 0x06, 0x6662 } |
|
2132 }; |
|
2133 |
|
2134 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2135 } |
|
2136 |
|
2137 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2138 mdio_patch(ioaddr, 0x0d, 0x0300); |
|
2139 mdio_patch(ioaddr, 0x0f, 0x0010); |
|
2140 |
|
2141 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2142 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); |
|
2143 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); |
|
2144 |
|
2145 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); |
|
2146 } |
|
2147 |
|
2148 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) |
|
2149 { |
|
2150 static struct phy_reg phy_reg_init_0[] = { |
|
2151 { 0x1f, 0x0001 }, |
|
2152 { 0x06, 0x4064 }, |
|
2153 { 0x07, 0x2863 }, |
|
2154 { 0x08, 0x059c }, |
|
2155 { 0x09, 0x26b4 }, |
|
2156 { 0x0a, 0x6a19 }, |
|
2157 { 0x0b, 0xdcc8 }, |
|
2158 { 0x10, 0xf06d }, |
|
2159 { 0x14, 0x7f68 }, |
|
2160 { 0x18, 0x7fd9 }, |
|
2161 { 0x1c, 0xf0ff }, |
|
2162 { 0x1d, 0x3d9c }, |
|
2163 { 0x1f, 0x0003 }, |
|
2164 { 0x12, 0xf49f }, |
|
2165 { 0x13, 0x070b }, |
|
2166 { 0x1a, 0x05ad }, |
|
2167 { 0x14, 0x94c0 }, |
|
2168 |
|
2169 { 0x1f, 0x0002 }, |
|
2170 { 0x06, 0x5561 }, |
|
2171 { 0x1f, 0x0005 }, |
|
2172 { 0x05, 0x8332 }, |
|
2173 { 0x06, 0x5561 } |
|
2174 }; |
|
2175 static struct phy_reg phy_reg_init_1[] = { |
|
2176 { 0x1f, 0x0005 }, |
|
2177 { 0x05, 0xffc2 }, |
|
2178 { 0x1f, 0x0005 }, |
|
2179 { 0x05, 0x8000 }, |
|
2180 { 0x06, 0xf8f9 }, |
|
2181 { 0x06, 0xfaee }, |
|
2182 { 0x06, 0xf8ea }, |
|
2183 { 0x06, 0x00ee }, |
|
2184 { 0x06, 0xf8eb }, |
|
2185 { 0x06, 0x00e2 }, |
|
2186 { 0x06, 0xf87c }, |
|
2187 { 0x06, 0xe3f8 }, |
|
2188 { 0x06, 0x7da5 }, |
|
2189 { 0x06, 0x1111 }, |
|
2190 { 0x06, 0x12d2 }, |
|
2191 { 0x06, 0x40d6 }, |
|
2192 { 0x06, 0x4444 }, |
|
2193 { 0x06, 0x0281 }, |
|
2194 { 0x06, 0xc6d2 }, |
|
2195 { 0x06, 0xa0d6 }, |
|
2196 { 0x06, 0xaaaa }, |
|
2197 { 0x06, 0x0281 }, |
|
2198 { 0x06, 0xc6ae }, |
|
2199 { 0x06, 0x0fa5 }, |
|
2200 { 0x06, 0x4444 }, |
|
2201 { 0x06, 0x02ae }, |
|
2202 { 0x06, 0x4da5 }, |
|
2203 { 0x06, 0xaaaa }, |
|
2204 { 0x06, 0x02ae }, |
|
2205 { 0x06, 0x47af }, |
|
2206 { 0x06, 0x81c2 }, |
|
2207 { 0x06, 0xee83 }, |
|
2208 { 0x06, 0x4e00 }, |
|
2209 { 0x06, 0xee83 }, |
|
2210 { 0x06, 0x4d0f }, |
|
2211 { 0x06, 0xee83 }, |
|
2212 { 0x06, 0x4c0f }, |
|
2213 { 0x06, 0xee83 }, |
|
2214 { 0x06, 0x4f00 }, |
|
2215 { 0x06, 0xee83 }, |
|
2216 { 0x06, 0x5100 }, |
|
2217 { 0x06, 0xee83 }, |
|
2218 { 0x06, 0x4aff }, |
|
2219 { 0x06, 0xee83 }, |
|
2220 { 0x06, 0x4bff }, |
|
2221 { 0x06, 0xe083 }, |
|
2222 { 0x06, 0x30e1 }, |
|
2223 { 0x06, 0x8331 }, |
|
2224 { 0x06, 0x58fe }, |
|
2225 { 0x06, 0xe4f8 }, |
|
2226 { 0x06, 0x8ae5 }, |
|
2227 { 0x06, 0xf88b }, |
|
2228 { 0x06, 0xe083 }, |
|
2229 { 0x06, 0x32e1 }, |
|
2230 { 0x06, 0x8333 }, |
|
2231 { 0x06, 0x590f }, |
|
2232 { 0x06, 0xe283 }, |
|
2233 { 0x06, 0x4d0c }, |
|
2234 { 0x06, 0x245a }, |
|
2235 { 0x06, 0xf01e }, |
|
2236 { 0x06, 0x12e4 }, |
|
2237 { 0x06, 0xf88c }, |
|
2238 { 0x06, 0xe5f8 }, |
|
2239 { 0x06, 0x8daf }, |
|
2240 { 0x06, 0x81c2 }, |
|
2241 { 0x06, 0xe083 }, |
|
2242 { 0x06, 0x4f10 }, |
|
2243 { 0x06, 0xe483 }, |
|
2244 { 0x06, 0x4fe0 }, |
|
2245 { 0x06, 0x834e }, |
|
2246 { 0x06, 0x7800 }, |
|
2247 { 0x06, 0x9f0a }, |
|
2248 { 0x06, 0xe083 }, |
|
2249 { 0x06, 0x4fa0 }, |
|
2250 { 0x06, 0x10a5 }, |
|
2251 { 0x06, 0xee83 }, |
|
2252 { 0x06, 0x4e01 }, |
|
2253 { 0x06, 0xe083 }, |
|
2254 { 0x06, 0x4e78 }, |
|
2255 { 0x06, 0x059e }, |
|
2256 { 0x06, 0x9ae0 }, |
|
2257 { 0x06, 0x834e }, |
|
2258 { 0x06, 0x7804 }, |
|
2259 { 0x06, 0x9e10 }, |
|
2260 { 0x06, 0xe083 }, |
|
2261 { 0x06, 0x4e78 }, |
|
2262 { 0x06, 0x039e }, |
|
2263 { 0x06, 0x0fe0 }, |
|
2264 { 0x06, 0x834e }, |
|
2265 { 0x06, 0x7801 }, |
|
2266 { 0x06, 0x9e05 }, |
|
2267 { 0x06, 0xae0c }, |
|
2268 { 0x06, 0xaf81 }, |
|
2269 { 0x06, 0xa7af }, |
|
2270 { 0x06, 0x8152 }, |
|
2271 { 0x06, 0xaf81 }, |
|
2272 { 0x06, 0x8baf }, |
|
2273 { 0x06, 0x81c2 }, |
|
2274 { 0x06, 0xee83 }, |
|
2275 { 0x06, 0x4800 }, |
|
2276 { 0x06, 0xee83 }, |
|
2277 { 0x06, 0x4900 }, |
|
2278 { 0x06, 0xe083 }, |
|
2279 { 0x06, 0x5110 }, |
|
2280 { 0x06, 0xe483 }, |
|
2281 { 0x06, 0x5158 }, |
|
2282 { 0x06, 0x019f }, |
|
2283 { 0x06, 0xead0 }, |
|
2284 { 0x06, 0x00d1 }, |
|
2285 { 0x06, 0x801f }, |
|
2286 { 0x06, 0x66e2 }, |
|
2287 { 0x06, 0xf8ea }, |
|
2288 { 0x06, 0xe3f8 }, |
|
2289 { 0x06, 0xeb5a }, |
|
2290 { 0x06, 0xf81e }, |
|
2291 { 0x06, 0x20e6 }, |
|
2292 { 0x06, 0xf8ea }, |
|
2293 { 0x06, 0xe5f8 }, |
|
2294 { 0x06, 0xebd3 }, |
|
2295 { 0x06, 0x02b3 }, |
|
2296 { 0x06, 0xfee2 }, |
|
2297 { 0x06, 0xf87c }, |
|
2298 { 0x06, 0xef32 }, |
|
2299 { 0x06, 0x5b80 }, |
|
2300 { 0x06, 0xe3f8 }, |
|
2301 { 0x06, 0x7d9e }, |
|
2302 { 0x06, 0x037d }, |
|
2303 { 0x06, 0xffff }, |
|
2304 { 0x06, 0x0d58 }, |
|
2305 { 0x06, 0x1c55 }, |
|
2306 { 0x06, 0x1a65 }, |
|
2307 { 0x06, 0x11a1 }, |
|
2308 { 0x06, 0x90d3 }, |
|
2309 { 0x06, 0xe283 }, |
|
2310 { 0x06, 0x48e3 }, |
|
2311 { 0x06, 0x8349 }, |
|
2312 { 0x06, 0x1b56 }, |
|
2313 { 0x06, 0xab08 }, |
|
2314 { 0x06, 0xef56 }, |
|
2315 { 0x06, 0xe683 }, |
|
2316 { 0x06, 0x48e7 }, |
|
2317 { 0x06, 0x8349 }, |
|
2318 { 0x06, 0x10d1 }, |
|
2319 { 0x06, 0x801f }, |
|
2320 { 0x06, 0x66a0 }, |
|
2321 { 0x06, 0x04b9 }, |
|
2322 { 0x06, 0xe283 }, |
|
2323 { 0x06, 0x48e3 }, |
|
2324 { 0x06, 0x8349 }, |
|
2325 { 0x06, 0xef65 }, |
|
2326 { 0x06, 0xe283 }, |
|
2327 { 0x06, 0x4ae3 }, |
|
2328 { 0x06, 0x834b }, |
|
2329 { 0x06, 0x1b56 }, |
|
2330 { 0x06, 0xaa0e }, |
|
2331 { 0x06, 0xef56 }, |
|
2332 { 0x06, 0xe683 }, |
|
2333 { 0x06, 0x4ae7 }, |
|
2334 { 0x06, 0x834b }, |
|
2335 { 0x06, 0xe283 }, |
|
2336 { 0x06, 0x4de6 }, |
|
2337 { 0x06, 0x834c }, |
|
2338 { 0x06, 0xe083 }, |
|
2339 { 0x06, 0x4da0 }, |
|
2340 { 0x06, 0x000c }, |
|
2341 { 0x06, 0xaf81 }, |
|
2342 { 0x06, 0x8be0 }, |
|
2343 { 0x06, 0x834d }, |
|
2344 { 0x06, 0x10e4 }, |
|
2345 { 0x06, 0x834d }, |
|
2346 { 0x06, 0xae04 }, |
|
2347 { 0x06, 0x80e4 }, |
|
2348 { 0x06, 0x834d }, |
|
2349 { 0x06, 0xe083 }, |
|
2350 { 0x06, 0x4e78 }, |
|
2351 { 0x06, 0x039e }, |
|
2352 { 0x06, 0x0be0 }, |
|
2353 { 0x06, 0x834e }, |
|
2354 { 0x06, 0x7804 }, |
|
2355 { 0x06, 0x9e04 }, |
|
2356 { 0x06, 0xee83 }, |
|
2357 { 0x06, 0x4e02 }, |
|
2358 { 0x06, 0xe083 }, |
|
2359 { 0x06, 0x32e1 }, |
|
2360 { 0x06, 0x8333 }, |
|
2361 { 0x06, 0x590f }, |
|
2362 { 0x06, 0xe283 }, |
|
2363 { 0x06, 0x4d0c }, |
|
2364 { 0x06, 0x245a }, |
|
2365 { 0x06, 0xf01e }, |
|
2366 { 0x06, 0x12e4 }, |
|
2367 { 0x06, 0xf88c }, |
|
2368 { 0x06, 0xe5f8 }, |
|
2369 { 0x06, 0x8de0 }, |
|
2370 { 0x06, 0x8330 }, |
|
2371 { 0x06, 0xe183 }, |
|
2372 { 0x06, 0x3168 }, |
|
2373 { 0x06, 0x01e4 }, |
|
2374 { 0x06, 0xf88a }, |
|
2375 { 0x06, 0xe5f8 }, |
|
2376 { 0x06, 0x8bae }, |
|
2377 { 0x06, 0x37ee }, |
|
2378 { 0x06, 0x834e }, |
|
2379 { 0x06, 0x03e0 }, |
|
2380 { 0x06, 0x834c }, |
|
2381 { 0x06, 0xe183 }, |
|
2382 { 0x06, 0x4d1b }, |
|
2383 { 0x06, 0x019e }, |
|
2384 { 0x06, 0x04aa }, |
|
2385 { 0x06, 0xa1ae }, |
|
2386 { 0x06, 0xa8ee }, |
|
2387 { 0x06, 0x834e }, |
|
2388 { 0x06, 0x04ee }, |
|
2389 { 0x06, 0x834f }, |
|
2390 { 0x06, 0x00ae }, |
|
2391 { 0x06, 0xabe0 }, |
|
2392 { 0x06, 0x834f }, |
|
2393 { 0x06, 0x7803 }, |
|
2394 { 0x06, 0x9f14 }, |
|
2395 { 0x06, 0xee83 }, |
|
2396 { 0x06, 0x4e05 }, |
|
2397 { 0x06, 0xd240 }, |
|
2398 { 0x06, 0xd655 }, |
|
2399 { 0x06, 0x5402 }, |
|
2400 { 0x06, 0x81c6 }, |
|
2401 { 0x06, 0xd2a0 }, |
|
2402 { 0x06, 0xd6ba }, |
|
2403 { 0x06, 0x0002 }, |
|
2404 { 0x06, 0x81c6 }, |
|
2405 { 0x06, 0xfefd }, |
|
2406 { 0x06, 0xfc05 }, |
|
2407 { 0x06, 0xf8e0 }, |
|
2408 { 0x06, 0xf860 }, |
|
2409 { 0x06, 0xe1f8 }, |
|
2410 { 0x06, 0x6168 }, |
|
2411 { 0x06, 0x02e4 }, |
|
2412 { 0x06, 0xf860 }, |
|
2413 { 0x06, 0xe5f8 }, |
|
2414 { 0x06, 0x61e0 }, |
|
2415 { 0x06, 0xf848 }, |
|
2416 { 0x06, 0xe1f8 }, |
|
2417 { 0x06, 0x4958 }, |
|
2418 { 0x06, 0x0f1e }, |
|
2419 { 0x06, 0x02e4 }, |
|
2420 { 0x06, 0xf848 }, |
|
2421 { 0x06, 0xe5f8 }, |
|
2422 { 0x06, 0x49d0 }, |
|
2423 { 0x06, 0x0002 }, |
|
2424 { 0x06, 0x820a }, |
|
2425 { 0x06, 0xbf83 }, |
|
2426 { 0x06, 0x50ef }, |
|
2427 { 0x06, 0x46dc }, |
|
2428 { 0x06, 0x19dd }, |
|
2429 { 0x06, 0xd001 }, |
|
2430 { 0x06, 0x0282 }, |
|
2431 { 0x06, 0x0a02 }, |
|
2432 { 0x06, 0x8226 }, |
|
2433 { 0x06, 0xe0f8 }, |
|
2434 { 0x06, 0x60e1 }, |
|
2435 { 0x06, 0xf861 }, |
|
2436 { 0x06, 0x58fd }, |
|
2437 { 0x06, 0xe4f8 }, |
|
2438 { 0x06, 0x60e5 }, |
|
2439 { 0x06, 0xf861 }, |
|
2440 { 0x06, 0xfc04 }, |
|
2441 { 0x06, 0xf9fa }, |
|
2442 { 0x06, 0xfbc6 }, |
|
2443 { 0x06, 0xbff8 }, |
|
2444 { 0x06, 0x40be }, |
|
2445 { 0x06, 0x8350 }, |
|
2446 { 0x06, 0xa001 }, |
|
2447 { 0x06, 0x0107 }, |
|
2448 { 0x06, 0x1b89 }, |
|
2449 { 0x06, 0xcfd2 }, |
|
2450 { 0x06, 0x08eb }, |
|
2451 { 0x06, 0xdb19 }, |
|
2452 { 0x06, 0xb2fb }, |
|
2453 { 0x06, 0xfffe }, |
|
2454 { 0x06, 0xfd04 }, |
|
2455 { 0x06, 0xf8e0 }, |
|
2456 { 0x06, 0xf848 }, |
|
2457 { 0x06, 0xe1f8 }, |
|
2458 { 0x06, 0x4968 }, |
|
2459 { 0x06, 0x08e4 }, |
|
2460 { 0x06, 0xf848 }, |
|
2461 { 0x06, 0xe5f8 }, |
|
2462 { 0x06, 0x4958 }, |
|
2463 { 0x06, 0xf7e4 }, |
|
2464 { 0x06, 0xf848 }, |
|
2465 { 0x06, 0xe5f8 }, |
|
2466 { 0x06, 0x49fc }, |
|
2467 { 0x06, 0x044d }, |
|
2468 { 0x06, 0x2000 }, |
|
2469 { 0x06, 0x024e }, |
|
2470 { 0x06, 0x2200 }, |
|
2471 { 0x06, 0x024d }, |
|
2472 { 0x06, 0xdfff }, |
|
2473 { 0x06, 0x014e }, |
|
2474 { 0x06, 0xddff }, |
|
2475 { 0x06, 0x0100 }, |
|
2476 { 0x05, 0x83d8 }, |
|
2477 { 0x06, 0x8000 }, |
|
2478 { 0x03, 0xdc00 }, |
|
2479 { 0x05, 0xfff6 }, |
|
2480 { 0x06, 0x00fc }, |
|
2481 { 0x1f, 0x0000 }, |
|
2482 |
|
2483 { 0x1f, 0x0000 }, |
|
2484 { 0x0d, 0xf880 }, |
|
2485 { 0x1f, 0x0000 } |
|
2486 }; |
|
2487 |
|
2488 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2489 |
|
2490 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2491 struct phy_reg phy_reg_init[] = { |
|
2492 { 0x1f, 0x0002 }, |
|
2493 { 0x05, 0x669a }, |
|
2494 { 0x1f, 0x0005 }, |
|
2495 { 0x05, 0x8330 }, |
|
2496 { 0x06, 0x669a }, |
|
2497 |
|
2498 { 0x1f, 0x0002 } |
|
2499 }; |
|
2500 int val; |
|
2501 |
|
2502 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2503 |
|
2504 val = mdio_read(ioaddr, 0x0d); |
|
2505 if ((val & 0x00ff) != 0x006c) { |
|
2506 u32 set[] = { |
|
2507 0x0065, 0x0066, 0x0067, 0x0068, |
|
2508 0x0069, 0x006a, 0x006b, 0x006c |
|
2509 }; |
|
2510 int i; |
|
2511 |
|
2512 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2513 |
|
2514 val &= 0xff00; |
|
2515 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2516 mdio_write(ioaddr, 0x0d, val | set[i]); |
|
2517 } |
|
2518 } else { |
|
2519 struct phy_reg phy_reg_init[] = { |
|
2520 { 0x1f, 0x0002 }, |
|
2521 { 0x05, 0x2642 }, |
|
2522 { 0x1f, 0x0005 }, |
|
2523 { 0x05, 0x8330 }, |
|
2524 { 0x06, 0x2642 } |
|
2525 }; |
|
2526 |
|
2527 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2528 } |
|
2529 |
|
2530 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2531 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); |
|
2532 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); |
|
2533 |
|
2534 mdio_write(ioaddr, 0x1f, 0x0001); |
|
2535 mdio_write(ioaddr, 0x17, 0x0cc0); |
|
2536 |
|
2537 mdio_write(ioaddr, 0x1f, 0x0002); |
|
2538 mdio_patch(ioaddr, 0x0f, 0x0017); |
|
2539 |
|
2540 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); |
|
2541 } |
|
2542 |
|
2543 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) |
|
2544 { |
|
2545 struct phy_reg phy_reg_init[] = { |
|
2546 { 0x1f, 0x0002 }, |
|
2547 { 0x10, 0x0008 }, |
|
2548 { 0x0d, 0x006c }, |
|
2549 |
|
2550 { 0x1f, 0x0000 }, |
|
2551 { 0x0d, 0xf880 }, |
|
2552 |
|
2553 { 0x1f, 0x0001 }, |
|
2554 { 0x17, 0x0cc0 }, |
|
2555 |
|
2556 { 0x1f, 0x0001 }, |
|
2557 { 0x0b, 0xa4d8 }, |
|
2558 { 0x09, 0x281c }, |
|
2559 { 0x07, 0x2883 }, |
|
2560 { 0x0a, 0x6b35 }, |
|
2561 { 0x1d, 0x3da4 }, |
|
2562 { 0x1c, 0xeffd }, |
|
2563 { 0x14, 0x7f52 }, |
|
2564 { 0x18, 0x7fc6 }, |
|
2565 { 0x08, 0x0601 }, |
|
2566 { 0x06, 0x4063 }, |
|
2567 { 0x10, 0xf074 }, |
|
2568 { 0x1f, 0x0003 }, |
|
2569 { 0x13, 0x0789 }, |
|
2570 { 0x12, 0xf4bd }, |
|
2571 { 0x1a, 0x04fd }, |
|
2572 { 0x14, 0x84b0 }, |
|
2573 { 0x1f, 0x0000 }, |
|
2574 { 0x00, 0x9200 }, |
|
2575 |
|
2576 { 0x1f, 0x0005 }, |
|
2577 { 0x01, 0x0340 }, |
|
2578 { 0x1f, 0x0001 }, |
|
2579 { 0x04, 0x4000 }, |
|
2580 { 0x03, 0x1d21 }, |
|
2581 { 0x02, 0x0c32 }, |
|
2582 { 0x01, 0x0200 }, |
|
2583 { 0x00, 0x5554 }, |
|
2584 { 0x04, 0x4800 }, |
|
2585 { 0x04, 0x4000 }, |
|
2586 { 0x04, 0xf000 }, |
|
2587 { 0x03, 0xdf01 }, |
|
2588 { 0x02, 0xdf20 }, |
|
2589 { 0x01, 0x101a }, |
|
2590 { 0x00, 0xa0ff }, |
|
2591 { 0x04, 0xf800 }, |
|
2592 { 0x04, 0xf000 }, |
|
2593 { 0x1f, 0x0000 }, |
|
2594 |
|
2595 { 0x1f, 0x0007 }, |
|
2596 { 0x1e, 0x0023 }, |
|
2597 { 0x16, 0x0000 }, |
|
2598 { 0x1f, 0x0000 } |
|
2599 }; |
|
2600 |
|
2601 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2602 } |
|
2603 |
|
2604 static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
|
2605 { |
|
2606 struct phy_reg phy_reg_init[] = { |
|
2607 { 0x1f, 0x0003 }, |
|
2608 { 0x08, 0x441d }, |
|
2609 { 0x01, 0x9100 }, |
|
2610 { 0x1f, 0x0000 } |
|
2611 }; |
|
2612 |
|
2613 mdio_write(ioaddr, 0x1f, 0x0000); |
|
2614 mdio_patch(ioaddr, 0x11, 1 << 12); |
|
2615 mdio_patch(ioaddr, 0x19, 1 << 13); |
|
2616 mdio_patch(ioaddr, 0x10, 1 << 15); |
|
2617 |
|
2618 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2619 } |
|
2620 |
|
2621 static void rtl_hw_phy_config(struct net_device *dev) |
|
2622 { |
|
2623 struct rtl8169_private *tp = netdev_priv(dev); |
|
2624 void __iomem *ioaddr = tp->mmio_addr; |
|
2625 |
|
2626 rtl8169_print_mac_version(tp); |
|
2627 |
|
2628 switch (tp->mac_version) { |
|
2629 case RTL_GIGA_MAC_VER_01: |
|
2630 break; |
|
2631 case RTL_GIGA_MAC_VER_02: |
|
2632 case RTL_GIGA_MAC_VER_03: |
|
2633 rtl8169s_hw_phy_config(ioaddr); |
|
2634 break; |
|
2635 case RTL_GIGA_MAC_VER_04: |
|
2636 rtl8169sb_hw_phy_config(ioaddr); |
|
2637 break; |
|
2638 case RTL_GIGA_MAC_VER_05: |
|
2639 rtl8169scd_hw_phy_config(tp, ioaddr); |
|
2640 break; |
|
2641 case RTL_GIGA_MAC_VER_06: |
|
2642 rtl8169sce_hw_phy_config(ioaddr); |
|
2643 break; |
|
2644 case RTL_GIGA_MAC_VER_07: |
|
2645 case RTL_GIGA_MAC_VER_08: |
|
2646 case RTL_GIGA_MAC_VER_09: |
|
2647 rtl8102e_hw_phy_config(ioaddr); |
|
2648 break; |
|
2649 case RTL_GIGA_MAC_VER_11: |
|
2650 rtl8168bb_hw_phy_config(ioaddr); |
|
2651 break; |
|
2652 case RTL_GIGA_MAC_VER_12: |
|
2653 rtl8168bef_hw_phy_config(ioaddr); |
|
2654 break; |
|
2655 case RTL_GIGA_MAC_VER_17: |
|
2656 rtl8168bef_hw_phy_config(ioaddr); |
|
2657 break; |
|
2658 case RTL_GIGA_MAC_VER_18: |
|
2659 rtl8168cp_1_hw_phy_config(ioaddr); |
|
2660 break; |
|
2661 case RTL_GIGA_MAC_VER_19: |
|
2662 rtl8168c_1_hw_phy_config(ioaddr); |
|
2663 break; |
|
2664 case RTL_GIGA_MAC_VER_20: |
|
2665 rtl8168c_2_hw_phy_config(ioaddr); |
|
2666 break; |
|
2667 case RTL_GIGA_MAC_VER_21: |
|
2668 rtl8168c_3_hw_phy_config(ioaddr); |
|
2669 break; |
|
2670 case RTL_GIGA_MAC_VER_22: |
|
2671 rtl8168c_4_hw_phy_config(ioaddr); |
|
2672 break; |
|
2673 case RTL_GIGA_MAC_VER_23: |
|
2674 case RTL_GIGA_MAC_VER_24: |
|
2675 rtl8168cp_2_hw_phy_config(ioaddr); |
|
2676 break; |
|
2677 case RTL_GIGA_MAC_VER_25: |
|
2678 rtl8168d_1_hw_phy_config(ioaddr); |
|
2679 break; |
|
2680 case RTL_GIGA_MAC_VER_26: |
|
2681 rtl8168d_2_hw_phy_config(ioaddr); |
|
2682 break; |
|
2683 case RTL_GIGA_MAC_VER_27: |
|
2684 rtl8168d_3_hw_phy_config(ioaddr); |
|
2685 break; |
|
2686 |
|
2687 default: |
|
2688 break; |
|
2689 } |
|
2690 } |
|
2691 |
|
2692 static void rtl8169_phy_timer(unsigned long __opaque) |
|
2693 { |
|
2694 struct net_device *dev = (struct net_device *)__opaque; |
|
2695 struct rtl8169_private *tp = netdev_priv(dev); |
|
2696 struct timer_list *timer = &tp->timer; |
|
2697 void __iomem *ioaddr = tp->mmio_addr; |
|
2698 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
2699 |
|
2700 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
2701 |
|
2702 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
|
2703 return; |
|
2704 |
|
2705 if (!tp->ecdev) |
|
2706 spin_lock_irq(&tp->lock); |
|
2707 |
|
2708 if (tp->phy_reset_pending(ioaddr)) { |
|
2709 /* |
|
2710 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
2711 * Let's delay the execution of the timer for a few ticks. |
|
2712 */ |
|
2713 timeout = HZ/10; |
|
2714 goto out_mod_timer; |
|
2715 } |
|
2716 |
|
2717 if (tp->link_ok(ioaddr)) |
|
2718 goto out_unlock; |
|
2719 |
|
2720 if (netif_msg_link(tp)) |
|
2721 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); |
|
2722 |
|
2723 tp->phy_reset_enable(ioaddr); |
|
2724 |
|
2725 out_mod_timer: |
|
2726 if (!tp->ecdev) |
|
2727 mod_timer(timer, jiffies + timeout); |
|
2728 out_unlock: |
|
2729 if (!tp->ecdev) |
|
2730 spin_unlock_irq(&tp->lock); |
|
2731 } |
|
2732 |
|
2733 static inline void rtl8169_delete_timer(struct net_device *dev) |
|
2734 { |
|
2735 struct rtl8169_private *tp = netdev_priv(dev); |
|
2736 struct timer_list *timer = &tp->timer; |
|
2737 |
|
2738 if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
2739 return; |
|
2740 |
|
2741 del_timer_sync(timer); |
|
2742 } |
|
2743 |
|
2744 static inline void rtl8169_request_timer(struct net_device *dev) |
|
2745 { |
|
2746 struct rtl8169_private *tp = netdev_priv(dev); |
|
2747 struct timer_list *timer = &tp->timer; |
|
2748 |
|
2749 if (tp->ecdev || tp->mac_version <= RTL_GIGA_MAC_VER_01) |
|
2750 return; |
|
2751 |
|
2752 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
2753 } |
|
2754 |
|
2755 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2756 /* |
|
2757 * Polling 'interrupt' - used by things like netconsole to send skbs |
|
2758 * without having to re-enable interrupts. It's not called while |
|
2759 * the interrupt routine is executing. |
|
2760 */ |
|
2761 static void rtl8169_netpoll(struct net_device *dev) |
|
2762 { |
|
2763 struct rtl8169_private *tp = netdev_priv(dev); |
|
2764 struct pci_dev *pdev = tp->pci_dev; |
|
2765 |
|
2766 disable_irq(pdev->irq); |
|
2767 rtl8169_interrupt(pdev->irq, dev); |
|
2768 enable_irq(pdev->irq); |
|
2769 } |
|
2770 #endif |
|
2771 |
|
2772 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
2773 void __iomem *ioaddr) |
|
2774 { |
|
2775 iounmap(ioaddr); |
|
2776 pci_release_regions(pdev); |
|
2777 pci_disable_device(pdev); |
|
2778 free_netdev(dev); |
|
2779 } |
|
2780 |
|
2781 static void rtl8169_phy_reset(struct net_device *dev, |
|
2782 struct rtl8169_private *tp) |
|
2783 { |
|
2784 void __iomem *ioaddr = tp->mmio_addr; |
|
2785 unsigned int i; |
|
2786 |
|
2787 tp->phy_reset_enable(ioaddr); |
|
2788 for (i = 0; i < 100; i++) { |
|
2789 if (!tp->phy_reset_pending(ioaddr)) |
|
2790 return; |
|
2791 msleep(1); |
|
2792 } |
|
2793 if (netif_msg_link(tp)) |
|
2794 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); |
|
2795 } |
|
2796 |
|
2797 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
2798 { |
|
2799 void __iomem *ioaddr = tp->mmio_addr; |
|
2800 |
|
2801 rtl_hw_phy_config(dev); |
|
2802 |
|
2803 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
2804 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
2805 RTL_W8(0x82, 0x01); |
|
2806 } |
|
2807 |
|
2808 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
2809 |
|
2810 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
2811 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
2812 |
|
2813 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
2814 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
2815 RTL_W8(0x82, 0x01); |
|
2816 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
2817 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
2818 } |
|
2819 |
|
2820 rtl8169_phy_reset(dev, tp); |
|
2821 |
|
2822 /* |
|
2823 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet |
|
2824 * only 8101. Don't panic. |
|
2825 */ |
|
2826 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); |
|
2827 |
|
2828 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) |
|
2829 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); |
|
2830 } |
|
2831 |
|
2832 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
2833 { |
|
2834 void __iomem *ioaddr = tp->mmio_addr; |
|
2835 u32 high; |
|
2836 u32 low; |
|
2837 |
|
2838 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
2839 high = addr[4] | (addr[5] << 8); |
|
2840 |
|
2841 spin_lock_irq(&tp->lock); |
|
2842 |
|
2843 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
2844 RTL_W32(MAC0, low); |
|
2845 RTL_W32(MAC4, high); |
|
2846 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
2847 |
|
2848 spin_unlock_irq(&tp->lock); |
|
2849 } |
|
2850 |
|
2851 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
2852 { |
|
2853 struct rtl8169_private *tp = netdev_priv(dev); |
|
2854 struct sockaddr *addr = p; |
|
2855 |
|
2856 if (!is_valid_ether_addr(addr->sa_data)) |
|
2857 return -EADDRNOTAVAIL; |
|
2858 |
|
2859 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
2860 |
|
2861 rtl_rar_set(tp, dev->dev_addr); |
|
2862 |
|
2863 return 0; |
|
2864 } |
|
2865 |
|
2866 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
2867 { |
|
2868 struct rtl8169_private *tp = netdev_priv(dev); |
|
2869 struct mii_ioctl_data *data = if_mii(ifr); |
|
2870 |
|
2871 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
2872 } |
|
2873 |
|
2874 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
2875 { |
|
2876 switch (cmd) { |
|
2877 case SIOCGMIIPHY: |
|
2878 data->phy_id = 32; /* Internal PHY */ |
|
2879 return 0; |
|
2880 |
|
2881 case SIOCGMIIREG: |
|
2882 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); |
|
2883 return 0; |
|
2884 |
|
2885 case SIOCSMIIREG: |
|
2886 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
|
2887 return 0; |
|
2888 } |
|
2889 return -EOPNOTSUPP; |
|
2890 } |
|
2891 |
|
2892 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
2893 { |
|
2894 return -EOPNOTSUPP; |
|
2895 } |
|
2896 |
|
2897 static const struct rtl_cfg_info { |
|
2898 void (*hw_start)(struct net_device *); |
|
2899 unsigned int region; |
|
2900 unsigned int align; |
|
2901 u16 intr_event; |
|
2902 u16 napi_event; |
|
2903 unsigned features; |
|
2904 u8 default_ver; |
|
2905 } rtl_cfg_infos [] = { |
|
2906 [RTL_CFG_0] = { |
|
2907 .hw_start = rtl_hw_start_8169, |
|
2908 .region = 1, |
|
2909 .align = 0, |
|
2910 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
2911 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
2912 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
2913 .features = RTL_FEATURE_GMII, |
|
2914 .default_ver = RTL_GIGA_MAC_VER_01, |
|
2915 }, |
|
2916 [RTL_CFG_1] = { |
|
2917 .hw_start = rtl_hw_start_8168, |
|
2918 .region = 2, |
|
2919 .align = 8, |
|
2920 .intr_event = SYSErr | LinkChg | RxOverflow | |
|
2921 TxErr | TxOK | RxOK | RxErr, |
|
2922 .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
|
2923 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
2924 .default_ver = RTL_GIGA_MAC_VER_11, |
|
2925 }, |
|
2926 [RTL_CFG_2] = { |
|
2927 .hw_start = rtl_hw_start_8101, |
|
2928 .region = 2, |
|
2929 .align = 8, |
|
2930 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | |
|
2931 RxFIFOOver | TxErr | TxOK | RxOK | RxErr, |
|
2932 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
|
2933 .features = RTL_FEATURE_MSI, |
|
2934 .default_ver = RTL_GIGA_MAC_VER_13, |
|
2935 } |
|
2936 }; |
|
2937 |
|
2938 /* Cfg9346_Unlock assumed. */ |
|
2939 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, |
|
2940 const struct rtl_cfg_info *cfg) |
|
2941 { |
|
2942 unsigned msi = 0; |
|
2943 u8 cfg2; |
|
2944 |
|
2945 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
2946 if (cfg->features & RTL_FEATURE_MSI) { |
|
2947 if (pci_enable_msi(pdev)) { |
|
2948 dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); |
|
2949 } else { |
|
2950 cfg2 |= MSIEnable; |
|
2951 msi = RTL_FEATURE_MSI; |
|
2952 } |
|
2953 } |
|
2954 RTL_W8(Config2, cfg2); |
|
2955 return msi; |
|
2956 } |
|
2957 |
|
2958 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
2959 { |
|
2960 if (tp->features & RTL_FEATURE_MSI) { |
|
2961 pci_disable_msi(pdev); |
|
2962 tp->features &= ~RTL_FEATURE_MSI; |
|
2963 } |
|
2964 } |
|
2965 |
|
2966 static const struct net_device_ops rtl8169_netdev_ops = { |
|
2967 .ndo_open = rtl8169_open, |
|
2968 .ndo_stop = rtl8169_close, |
|
2969 .ndo_get_stats = rtl8169_get_stats, |
|
2970 .ndo_start_xmit = rtl8169_start_xmit, |
|
2971 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
2972 .ndo_validate_addr = eth_validate_addr, |
|
2973 .ndo_change_mtu = rtl8169_change_mtu, |
|
2974 .ndo_set_mac_address = rtl_set_mac_address, |
|
2975 .ndo_do_ioctl = rtl8169_ioctl, |
|
2976 .ndo_set_multicast_list = rtl_set_rx_mode, |
|
2977 #ifdef CONFIG_R8169_VLAN |
|
2978 .ndo_vlan_rx_register = rtl8169_vlan_rx_register, |
|
2979 #endif |
|
2980 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2981 .ndo_poll_controller = rtl8169_netpoll, |
|
2982 #endif |
|
2983 |
|
2984 }; |
|
2985 |
|
2986 static int __devinit |
|
2987 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
2988 { |
|
2989 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
2990 const unsigned int region = cfg->region; |
|
2991 struct rtl8169_private *tp; |
|
2992 struct mii_if_info *mii; |
|
2993 struct net_device *dev; |
|
2994 void __iomem *ioaddr; |
|
2995 unsigned int i; |
|
2996 int rc; |
|
2997 |
|
2998 if (netif_msg_drv(&debug)) { |
|
2999 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
3000 MODULENAME, RTL8169_VERSION); |
|
3001 } |
|
3002 |
|
3003 dev = alloc_etherdev(sizeof (*tp)); |
|
3004 if (!dev) { |
|
3005 if (netif_msg_drv(&debug)) |
|
3006 dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
|
3007 rc = -ENOMEM; |
|
3008 goto out; |
|
3009 } |
|
3010 |
|
3011 SET_NETDEV_DEV(dev, &pdev->dev); |
|
3012 dev->netdev_ops = &rtl8169_netdev_ops; |
|
3013 tp = netdev_priv(dev); |
|
3014 tp->dev = dev; |
|
3015 tp->pci_dev = pdev; |
|
3016 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
3017 |
|
3018 mii = &tp->mii; |
|
3019 mii->dev = dev; |
|
3020 mii->mdio_read = rtl_mdio_read; |
|
3021 mii->mdio_write = rtl_mdio_write; |
|
3022 mii->phy_id_mask = 0x1f; |
|
3023 mii->reg_num_mask = 0x1f; |
|
3024 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
3025 |
|
3026 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
3027 rc = pci_enable_device(pdev); |
|
3028 if (rc < 0) { |
|
3029 if (netif_msg_probe(tp)) |
|
3030 dev_err(&pdev->dev, "enable failure\n"); |
|
3031 goto err_out_free_dev_1; |
|
3032 } |
|
3033 |
|
3034 rc = pci_set_mwi(pdev); |
|
3035 if (rc < 0) |
|
3036 goto err_out_disable_2; |
|
3037 |
|
3038 /* make sure PCI base addr 1 is MMIO */ |
|
3039 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
3040 if (netif_msg_probe(tp)) { |
|
3041 dev_err(&pdev->dev, |
|
3042 "region #%d not an MMIO resource, aborting\n", |
|
3043 region); |
|
3044 } |
|
3045 rc = -ENODEV; |
|
3046 goto err_out_mwi_3; |
|
3047 } |
|
3048 |
|
3049 /* check for weird/broken PCI region reporting */ |
|
3050 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
3051 if (netif_msg_probe(tp)) { |
|
3052 dev_err(&pdev->dev, |
|
3053 "Invalid PCI region size(s), aborting\n"); |
|
3054 } |
|
3055 rc = -ENODEV; |
|
3056 goto err_out_mwi_3; |
|
3057 } |
|
3058 |
|
3059 rc = pci_request_regions(pdev, MODULENAME); |
|
3060 if (rc < 0) { |
|
3061 if (netif_msg_probe(tp)) |
|
3062 dev_err(&pdev->dev, "could not request regions.\n"); |
|
3063 goto err_out_mwi_3; |
|
3064 } |
|
3065 |
|
3066 tp->cp_cmd = PCIMulRW | RxChkSum; |
|
3067 |
|
3068 if ((sizeof(dma_addr_t) > 4) && |
|
3069 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
3070 tp->cp_cmd |= PCIDAC; |
|
3071 dev->features |= NETIF_F_HIGHDMA; |
|
3072 } else { |
|
3073 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
3074 if (rc < 0) { |
|
3075 if (netif_msg_probe(tp)) { |
|
3076 dev_err(&pdev->dev, |
|
3077 "DMA configuration failed.\n"); |
|
3078 } |
|
3079 goto err_out_free_res_4; |
|
3080 } |
|
3081 } |
|
3082 |
|
3083 /* ioremap MMIO region */ |
|
3084 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
3085 if (!ioaddr) { |
|
3086 if (netif_msg_probe(tp)) |
|
3087 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
3088 rc = -EIO; |
|
3089 goto err_out_free_res_4; |
|
3090 } |
|
3091 |
|
3092 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
|
3093 if (!tp->pcie_cap && netif_msg_probe(tp)) |
|
3094 dev_info(&pdev->dev, "no PCI Express capability\n"); |
|
3095 |
|
3096 RTL_W16(IntrMask, 0x0000); |
|
3097 |
|
3098 /* Soft reset the chip. */ |
|
3099 RTL_W8(ChipCmd, CmdReset); |
|
3100 |
|
3101 /* Check that the chip has finished the reset. */ |
|
3102 for (i = 0; i < 100; i++) { |
|
3103 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3104 break; |
|
3105 msleep_interruptible(1); |
|
3106 } |
|
3107 |
|
3108 RTL_W16(IntrStatus, 0xffff); |
|
3109 |
|
3110 pci_set_master(pdev); |
|
3111 |
|
3112 /* Identify chip attached to board */ |
|
3113 rtl8169_get_mac_version(tp, ioaddr); |
|
3114 |
|
3115 /* Use appropriate default if unknown */ |
|
3116 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
3117 if (netif_msg_probe(tp)) { |
|
3118 dev_notice(&pdev->dev, |
|
3119 "unknown MAC, using family default\n"); |
|
3120 } |
|
3121 tp->mac_version = cfg->default_ver; |
|
3122 } |
|
3123 |
|
3124 rtl8169_print_mac_version(tp); |
|
3125 |
|
3126 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
|
3127 if (tp->mac_version == rtl_chip_info[i].mac_version) |
|
3128 break; |
|
3129 } |
|
3130 if (i == ARRAY_SIZE(rtl_chip_info)) { |
|
3131 dev_err(&pdev->dev, |
|
3132 "driver bug, MAC version not found in rtl_chip_info\n"); |
|
3133 goto err_out_msi_5; |
|
3134 } |
|
3135 tp->chipset = i; |
|
3136 |
|
3137 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3138 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
3139 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
3140 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
3141 tp->features |= RTL_FEATURE_WOL; |
|
3142 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
3143 tp->features |= RTL_FEATURE_WOL; |
|
3144 tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
|
3145 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3146 |
|
3147 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
|
3148 (RTL_R8(PHYstatus) & TBI_Enable)) { |
|
3149 tp->set_speed = rtl8169_set_speed_tbi; |
|
3150 tp->get_settings = rtl8169_gset_tbi; |
|
3151 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
3152 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
3153 tp->link_ok = rtl8169_tbi_link_ok; |
|
3154 tp->do_ioctl = rtl_tbi_ioctl; |
|
3155 |
|
3156 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
|
3157 } else { |
|
3158 tp->set_speed = rtl8169_set_speed_xmii; |
|
3159 tp->get_settings = rtl8169_gset_xmii; |
|
3160 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
3161 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
3162 tp->link_ok = rtl8169_xmii_link_ok; |
|
3163 tp->do_ioctl = rtl_xmii_ioctl; |
|
3164 } |
|
3165 |
|
3166 spin_lock_init(&tp->lock); |
|
3167 |
|
3168 tp->mmio_addr = ioaddr; |
|
3169 |
|
3170 /* Get MAC address */ |
|
3171 for (i = 0; i < MAC_ADDR_LEN; i++) |
|
3172 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
3173 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
3174 |
|
3175 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
3176 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
3177 dev->irq = pdev->irq; |
|
3178 dev->base_addr = (unsigned long) ioaddr; |
|
3179 |
|
3180 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
3181 |
|
3182 #ifdef CONFIG_R8169_VLAN |
|
3183 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
3184 #endif |
|
3185 |
|
3186 tp->intr_mask = 0xffff; |
|
3187 tp->align = cfg->align; |
|
3188 tp->hw_start = cfg->hw_start; |
|
3189 tp->intr_event = cfg->intr_event; |
|
3190 tp->napi_event = cfg->napi_event; |
|
3191 |
|
3192 init_timer(&tp->timer); |
|
3193 tp->timer.data = (unsigned long) dev; |
|
3194 tp->timer.function = rtl8169_phy_timer; |
|
3195 |
|
3196 // offer device to EtherCAT master module |
|
3197 tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
3198 |
|
3199 if (!tp->ecdev) { |
|
3200 rc = register_netdev(dev); |
|
3201 if (rc < 0) |
|
3202 goto err_out_msi_5; |
|
3203 } |
|
3204 |
|
3205 pci_set_drvdata(pdev, dev); |
|
3206 |
|
3207 if (netif_msg_probe(tp)) { |
|
3208 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff; |
|
3209 |
|
3210 printk(KERN_INFO "%s: %s at 0x%lx, " |
|
3211 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
|
3212 "XID %08x IRQ %d\n", |
|
3213 dev->name, |
|
3214 rtl_chip_info[tp->chipset].name, |
|
3215 dev->base_addr, |
|
3216 dev->dev_addr[0], dev->dev_addr[1], |
|
3217 dev->dev_addr[2], dev->dev_addr[3], |
|
3218 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
|
3219 } |
|
3220 |
|
3221 rtl8169_init_phy(dev, tp); |
|
3222 |
|
3223 /* |
|
3224 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
3225 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
3226 */ |
|
3227 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
3228 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan); |
|
3229 |
|
3230 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
3231 if (tp->ecdev && ecdev_open(tp->ecdev)) { |
|
3232 ecdev_withdraw(tp->ecdev); |
|
3233 goto err_out_msi_5; |
|
3234 } |
|
3235 |
|
3236 out: |
|
3237 return rc; |
|
3238 |
|
3239 err_out_msi_5: |
|
3240 rtl_disable_msi(pdev, tp); |
|
3241 iounmap(ioaddr); |
|
3242 err_out_free_res_4: |
|
3243 pci_release_regions(pdev); |
|
3244 err_out_mwi_3: |
|
3245 pci_clear_mwi(pdev); |
|
3246 err_out_disable_2: |
|
3247 pci_disable_device(pdev); |
|
3248 err_out_free_dev_1: |
|
3249 free_netdev(dev); |
|
3250 goto out; |
|
3251 } |
|
3252 |
|
3253 static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
|
3254 { |
|
3255 struct net_device *dev = pci_get_drvdata(pdev); |
|
3256 struct rtl8169_private *tp = netdev_priv(dev); |
|
3257 |
|
3258 flush_scheduled_work(); |
|
3259 |
|
3260 if (tp->ecdev) { |
|
3261 ecdev_close(tp->ecdev); |
|
3262 ecdev_withdraw(tp->ecdev); |
|
3263 } else { |
|
3264 unregister_netdev(dev); |
|
3265 } |
|
3266 |
|
3267 /* restore original MAC address */ |
|
3268 rtl_rar_set(tp, dev->perm_addr); |
|
3269 |
|
3270 rtl_disable_msi(pdev, tp); |
|
3271 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
3272 pci_set_drvdata(pdev, NULL); |
|
3273 } |
|
3274 |
|
3275 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
|
3276 struct net_device *dev) |
|
3277 { |
|
3278 unsigned int max_frame = dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
|
3279 |
|
3280 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE; |
|
3281 } |
|
3282 |
|
3283 static int rtl8169_open(struct net_device *dev) |
|
3284 { |
|
3285 struct rtl8169_private *tp = netdev_priv(dev); |
|
3286 struct pci_dev *pdev = tp->pci_dev; |
|
3287 int retval = -ENOMEM; |
|
3288 |
|
3289 |
|
3290 rtl8169_set_rxbufsize(tp, dev); |
|
3291 |
|
3292 /* |
|
3293 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
3294 * pci_alloc_consistent provides more. |
|
3295 */ |
|
3296 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, |
|
3297 &tp->TxPhyAddr); |
|
3298 if (!tp->TxDescArray) |
|
3299 goto out; |
|
3300 |
|
3301 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, |
|
3302 &tp->RxPhyAddr); |
|
3303 if (!tp->RxDescArray) |
|
3304 goto err_free_tx_0; |
|
3305 |
|
3306 retval = rtl8169_init_ring(dev); |
|
3307 if (retval < 0) |
|
3308 goto err_free_rx_1; |
|
3309 |
|
3310 INIT_DELAYED_WORK(&tp->task, NULL); |
|
3311 |
|
3312 smp_mb(); |
|
3313 |
|
3314 if (!tp->ecdev) { |
|
3315 retval = request_irq(dev->irq, rtl8169_interrupt, |
|
3316 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
3317 dev->name, dev); |
|
3318 if (retval < 0) |
|
3319 goto err_release_ring_2; |
|
3320 |
|
3321 napi_enable(&tp->napi); |
|
3322 |
|
3323 } |
|
3324 |
|
3325 rtl_hw_start(dev); |
|
3326 |
|
3327 rtl8169_request_timer(dev); |
|
3328 |
|
3329 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
3330 out: |
|
3331 return retval; |
|
3332 |
|
3333 err_release_ring_2: |
|
3334 rtl8169_rx_clear(tp); |
|
3335 err_free_rx_1: |
|
3336 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
3337 tp->RxPhyAddr); |
|
3338 err_free_tx_0: |
|
3339 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
3340 tp->TxPhyAddr); |
|
3341 goto out; |
|
3342 } |
|
3343 |
|
3344 static void rtl8169_hw_reset(void __iomem *ioaddr) |
|
3345 { |
|
3346 /* Disable interrupts */ |
|
3347 rtl8169_irq_mask_and_ack(ioaddr); |
|
3348 |
|
3349 /* Reset the chipset */ |
|
3350 RTL_W8(ChipCmd, CmdReset); |
|
3351 |
|
3352 /* PCI commit */ |
|
3353 RTL_R8(ChipCmd); |
|
3354 } |
|
3355 |
|
3356 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
3357 { |
|
3358 void __iomem *ioaddr = tp->mmio_addr; |
|
3359 u32 cfg = rtl8169_rx_config; |
|
3360 |
|
3361 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
3362 RTL_W32(RxConfig, cfg); |
|
3363 |
|
3364 /* Set DMA burst size and Interframe Gap Time */ |
|
3365 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
3366 (InterFrameGap << TxInterFrameGapShift)); |
|
3367 } |
|
3368 |
|
3369 static void rtl_hw_start(struct net_device *dev) |
|
3370 { |
|
3371 struct rtl8169_private *tp = netdev_priv(dev); |
|
3372 void __iomem *ioaddr = tp->mmio_addr; |
|
3373 unsigned int i; |
|
3374 |
|
3375 /* Soft reset the chip. */ |
|
3376 RTL_W8(ChipCmd, CmdReset); |
|
3377 |
|
3378 /* Check that the chip has finished the reset. */ |
|
3379 for (i = 0; i < 100; i++) { |
|
3380 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3381 break; |
|
3382 msleep_interruptible(1); |
|
3383 } |
|
3384 |
|
3385 tp->hw_start(dev); |
|
3386 |
|
3387 if (!tp->ecdev) |
|
3388 netif_start_queue(dev); |
|
3389 } |
|
3390 |
|
3391 |
|
3392 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
3393 void __iomem *ioaddr) |
|
3394 { |
|
3395 /* |
|
3396 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
3397 * register to be written before TxDescAddrLow to work. |
|
3398 * Switching from MMIO to I/O access fixes the issue as well. |
|
3399 */ |
|
3400 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
3401 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
3402 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
3403 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
3404 } |
|
3405 |
|
3406 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
3407 { |
|
3408 u16 cmd; |
|
3409 |
|
3410 cmd = RTL_R16(CPlusCmd); |
|
3411 RTL_W16(CPlusCmd, cmd); |
|
3412 return cmd; |
|
3413 } |
|
3414 |
|
3415 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
3416 { |
|
3417 /* Low hurts. Let's disable the filtering. */ |
|
3418 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
3419 } |
|
3420 |
|
3421 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
3422 { |
|
3423 struct { |
|
3424 u32 mac_version; |
|
3425 u32 clk; |
|
3426 u32 val; |
|
3427 } cfg2_info [] = { |
|
3428 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
3429 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
3430 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
3431 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
3432 }, *p = cfg2_info; |
|
3433 unsigned int i; |
|
3434 u32 clk; |
|
3435 |
|
3436 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
3437 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
3438 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
3439 RTL_W32(0x7c, p->val); |
|
3440 break; |
|
3441 } |
|
3442 } |
|
3443 } |
|
3444 |
|
3445 static void rtl_hw_start_8169(struct net_device *dev) |
|
3446 { |
|
3447 struct rtl8169_private *tp = netdev_priv(dev); |
|
3448 void __iomem *ioaddr = tp->mmio_addr; |
|
3449 struct pci_dev *pdev = tp->pci_dev; |
|
3450 |
|
3451 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
3452 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
3453 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3454 } |
|
3455 |
|
3456 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3457 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
3458 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3459 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
3460 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
3461 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3462 |
|
3463 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3464 |
|
3465 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
3466 |
|
3467 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
|
3468 (tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3469 (tp->mac_version == RTL_GIGA_MAC_VER_03) || |
|
3470 (tp->mac_version == RTL_GIGA_MAC_VER_04)) |
|
3471 rtl_set_rx_tx_config_registers(tp); |
|
3472 |
|
3473 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
3474 |
|
3475 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
|
3476 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
|
3477 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
3478 "Bit-3 and bit-14 MUST be 1\n"); |
|
3479 tp->cp_cmd |= (1 << 14); |
|
3480 } |
|
3481 |
|
3482 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3483 |
|
3484 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
3485 |
|
3486 /* |
|
3487 * Undocumented corner. Supposedly: |
|
3488 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
3489 */ |
|
3490 RTL_W16(IntrMitigate, 0x0000); |
|
3491 |
|
3492 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3493 |
|
3494 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
|
3495 (tp->mac_version != RTL_GIGA_MAC_VER_02) && |
|
3496 (tp->mac_version != RTL_GIGA_MAC_VER_03) && |
|
3497 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { |
|
3498 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3499 rtl_set_rx_tx_config_registers(tp); |
|
3500 } |
|
3501 |
|
3502 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3503 |
|
3504 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
3505 RTL_R8(IntrMask); |
|
3506 |
|
3507 RTL_W32(RxMissed, 0); |
|
3508 |
|
3509 rtl_set_rx_mode(dev); |
|
3510 |
|
3511 /* no early-rx interrupts */ |
|
3512 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
3513 |
|
3514 /* Enable all known interrupts by setting the interrupt mask. */ |
|
3515 if (!tp->ecdev) |
|
3516 RTL_W16(IntrMask, tp->intr_event); |
|
3517 } |
|
3518 |
|
3519 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
3520 { |
|
3521 struct net_device *dev = pci_get_drvdata(pdev); |
|
3522 struct rtl8169_private *tp = netdev_priv(dev); |
|
3523 int cap = tp->pcie_cap; |
|
3524 |
|
3525 if (cap) { |
|
3526 u16 ctl; |
|
3527 |
|
3528 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
3529 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
3530 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
3531 } |
|
3532 } |
|
3533 |
|
3534 static void rtl_csi_access_enable(void __iomem *ioaddr) |
|
3535 { |
|
3536 u32 csi; |
|
3537 |
|
3538 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
3539 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); |
|
3540 } |
|
3541 |
|
3542 struct ephy_info { |
|
3543 unsigned int offset; |
|
3544 u16 mask; |
|
3545 u16 bits; |
|
3546 }; |
|
3547 |
|
3548 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) |
|
3549 { |
|
3550 u16 w; |
|
3551 |
|
3552 while (len-- > 0) { |
|
3553 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
3554 rtl_ephy_write(ioaddr, e->offset, w); |
|
3555 e++; |
|
3556 } |
|
3557 } |
|
3558 |
|
3559 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
3560 { |
|
3561 struct net_device *dev = pci_get_drvdata(pdev); |
|
3562 struct rtl8169_private *tp = netdev_priv(dev); |
|
3563 int cap = tp->pcie_cap; |
|
3564 |
|
3565 if (cap) { |
|
3566 u16 ctl; |
|
3567 |
|
3568 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
3569 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
3570 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
3571 } |
|
3572 } |
|
3573 |
|
3574 #define R8168_CPCMD_QUIRK_MASK (\ |
|
3575 EnableBist | \ |
|
3576 Mac_dbgo_oe | \ |
|
3577 Force_half_dup | \ |
|
3578 Force_rxflow_en | \ |
|
3579 Force_txflow_en | \ |
|
3580 Cxpl_dbg_sel | \ |
|
3581 ASF | \ |
|
3582 PktCntrDisable | \ |
|
3583 Mac_dbgo_sel) |
|
3584 |
|
3585 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3586 { |
|
3587 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3588 |
|
3589 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3590 |
|
3591 rtl_tx_performance_tweak(pdev, |
|
3592 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3593 } |
|
3594 |
|
3595 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3596 { |
|
3597 rtl_hw_start_8168bb(ioaddr, pdev); |
|
3598 |
|
3599 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3600 |
|
3601 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
3602 } |
|
3603 |
|
3604 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3605 { |
|
3606 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
3607 |
|
3608 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3609 |
|
3610 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3611 |
|
3612 rtl_disable_clock_request(pdev); |
|
3613 |
|
3614 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3615 } |
|
3616 |
|
3617 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3618 { |
|
3619 static struct ephy_info e_info_8168cp[] = { |
|
3620 { 0x01, 0, 0x0001 }, |
|
3621 { 0x02, 0x0800, 0x1000 }, |
|
3622 { 0x03, 0, 0x0042 }, |
|
3623 { 0x06, 0x0080, 0x0000 }, |
|
3624 { 0x07, 0, 0x2000 } |
|
3625 }; |
|
3626 |
|
3627 rtl_csi_access_enable(ioaddr); |
|
3628 |
|
3629 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
3630 |
|
3631 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3632 } |
|
3633 |
|
3634 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3635 { |
|
3636 rtl_csi_access_enable(ioaddr); |
|
3637 |
|
3638 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3639 |
|
3640 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3641 |
|
3642 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3643 } |
|
3644 |
|
3645 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3646 { |
|
3647 rtl_csi_access_enable(ioaddr); |
|
3648 |
|
3649 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3650 |
|
3651 /* Magic. */ |
|
3652 RTL_W8(DBG_REG, 0x20); |
|
3653 |
|
3654 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3655 |
|
3656 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3657 |
|
3658 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3659 } |
|
3660 |
|
3661 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3662 { |
|
3663 static struct ephy_info e_info_8168c_1[] = { |
|
3664 { 0x02, 0x0800, 0x1000 }, |
|
3665 { 0x03, 0, 0x0002 }, |
|
3666 { 0x06, 0x0080, 0x0000 } |
|
3667 }; |
|
3668 |
|
3669 rtl_csi_access_enable(ioaddr); |
|
3670 |
|
3671 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
3672 |
|
3673 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
3674 |
|
3675 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3676 } |
|
3677 |
|
3678 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3679 { |
|
3680 static struct ephy_info e_info_8168c_2[] = { |
|
3681 { 0x01, 0, 0x0001 }, |
|
3682 { 0x03, 0x0400, 0x0220 } |
|
3683 }; |
|
3684 |
|
3685 rtl_csi_access_enable(ioaddr); |
|
3686 |
|
3687 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
3688 |
|
3689 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3690 } |
|
3691 |
|
3692 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3693 { |
|
3694 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
3695 } |
|
3696 |
|
3697 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3698 { |
|
3699 rtl_csi_access_enable(ioaddr); |
|
3700 |
|
3701 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
3702 } |
|
3703 |
|
3704 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3705 { |
|
3706 rtl_csi_access_enable(ioaddr); |
|
3707 |
|
3708 rtl_disable_clock_request(pdev); |
|
3709 |
|
3710 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3711 |
|
3712 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3713 |
|
3714 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
3715 } |
|
3716 |
|
3717 static void rtl_hw_start_8168(struct net_device *dev) |
|
3718 { |
|
3719 struct rtl8169_private *tp = netdev_priv(dev); |
|
3720 void __iomem *ioaddr = tp->mmio_addr; |
|
3721 struct pci_dev *pdev = tp->pci_dev; |
|
3722 |
|
3723 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3724 |
|
3725 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3726 |
|
3727 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
3728 |
|
3729 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
3730 |
|
3731 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3732 |
|
3733 RTL_W16(IntrMitigate, 0x5151); |
|
3734 |
|
3735 /* Work around for RxFIFO overflow. */ |
|
3736 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
3737 tp->intr_event |= RxFIFOOver | PCSTimeout; |
|
3738 tp->intr_event &= ~RxOverflow; |
|
3739 } |
|
3740 |
|
3741 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3742 |
|
3743 rtl_set_rx_mode(dev); |
|
3744 |
|
3745 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
3746 (InterFrameGap << TxInterFrameGapShift)); |
|
3747 |
|
3748 RTL_R8(IntrMask); |
|
3749 |
|
3750 switch (tp->mac_version) { |
|
3751 case RTL_GIGA_MAC_VER_11: |
|
3752 rtl_hw_start_8168bb(ioaddr, pdev); |
|
3753 break; |
|
3754 |
|
3755 case RTL_GIGA_MAC_VER_12: |
|
3756 case RTL_GIGA_MAC_VER_17: |
|
3757 rtl_hw_start_8168bef(ioaddr, pdev); |
|
3758 break; |
|
3759 |
|
3760 case RTL_GIGA_MAC_VER_18: |
|
3761 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
3762 break; |
|
3763 |
|
3764 case RTL_GIGA_MAC_VER_19: |
|
3765 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
3766 break; |
|
3767 |
|
3768 case RTL_GIGA_MAC_VER_20: |
|
3769 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
3770 break; |
|
3771 |
|
3772 case RTL_GIGA_MAC_VER_21: |
|
3773 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
3774 break; |
|
3775 |
|
3776 case RTL_GIGA_MAC_VER_22: |
|
3777 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
3778 break; |
|
3779 |
|
3780 case RTL_GIGA_MAC_VER_23: |
|
3781 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
3782 break; |
|
3783 |
|
3784 case RTL_GIGA_MAC_VER_24: |
|
3785 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
3786 break; |
|
3787 |
|
3788 case RTL_GIGA_MAC_VER_25: |
|
3789 case RTL_GIGA_MAC_VER_26: |
|
3790 case RTL_GIGA_MAC_VER_27: |
|
3791 rtl_hw_start_8168d(ioaddr, pdev); |
|
3792 break; |
|
3793 |
|
3794 default: |
|
3795 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
3796 dev->name, tp->mac_version); |
|
3797 break; |
|
3798 } |
|
3799 |
|
3800 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3801 |
|
3802 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3803 |
|
3804 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
3805 |
|
3806 if (!tp->ecdev) |
|
3807 RTL_W16(IntrMask, tp->intr_event); |
|
3808 } |
|
3809 |
|
3810 #define R810X_CPCMD_QUIRK_MASK (\ |
|
3811 EnableBist | \ |
|
3812 Mac_dbgo_oe | \ |
|
3813 Force_half_dup | \ |
|
3814 Force_rxflow_en | \ |
|
3815 Force_txflow_en | \ |
|
3816 Cxpl_dbg_sel | \ |
|
3817 ASF | \ |
|
3818 PktCntrDisable | \ |
|
3819 PCIDAC | \ |
|
3820 PCIMulRW) |
|
3821 |
|
3822 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3823 { |
|
3824 static struct ephy_info e_info_8102e_1[] = { |
|
3825 { 0x01, 0, 0x6e65 }, |
|
3826 { 0x02, 0, 0x091f }, |
|
3827 { 0x03, 0, 0xc2f9 }, |
|
3828 { 0x06, 0, 0xafb5 }, |
|
3829 { 0x07, 0, 0x0e00 }, |
|
3830 { 0x19, 0, 0xec80 }, |
|
3831 { 0x01, 0, 0x2e65 }, |
|
3832 { 0x01, 0, 0x6e65 } |
|
3833 }; |
|
3834 u8 cfg1; |
|
3835 |
|
3836 rtl_csi_access_enable(ioaddr); |
|
3837 |
|
3838 RTL_W8(DBG_REG, FIX_NAK_1); |
|
3839 |
|
3840 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3841 |
|
3842 RTL_W8(Config1, |
|
3843 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
3844 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3845 |
|
3846 cfg1 = RTL_R8(Config1); |
|
3847 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
3848 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
3849 |
|
3850 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
3851 |
|
3852 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
3853 } |
|
3854 |
|
3855 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3856 { |
|
3857 rtl_csi_access_enable(ioaddr); |
|
3858 |
|
3859 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3860 |
|
3861 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
3862 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
3863 |
|
3864 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); |
|
3865 } |
|
3866 |
|
3867 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
3868 { |
|
3869 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
3870 |
|
3871 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
3872 } |
|
3873 |
|
3874 static void rtl_hw_start_8101(struct net_device *dev) |
|
3875 { |
|
3876 struct rtl8169_private *tp = netdev_priv(dev); |
|
3877 void __iomem *ioaddr = tp->mmio_addr; |
|
3878 struct pci_dev *pdev = tp->pci_dev; |
|
3879 |
|
3880 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
|
3881 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { |
|
3882 int cap = tp->pcie_cap; |
|
3883 |
|
3884 if (cap) { |
|
3885 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
3886 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3887 } |
|
3888 } |
|
3889 |
|
3890 switch (tp->mac_version) { |
|
3891 case RTL_GIGA_MAC_VER_07: |
|
3892 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
3893 break; |
|
3894 |
|
3895 case RTL_GIGA_MAC_VER_08: |
|
3896 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
3897 break; |
|
3898 |
|
3899 case RTL_GIGA_MAC_VER_09: |
|
3900 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
3901 break; |
|
3902 } |
|
3903 |
|
3904 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3905 |
|
3906 RTL_W8(EarlyTxThres, EarlyTxThld); |
|
3907 |
|
3908 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
|
3909 |
|
3910 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
3911 |
|
3912 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
3913 |
|
3914 RTL_W16(IntrMitigate, 0x0000); |
|
3915 |
|
3916 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
3917 |
|
3918 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3919 rtl_set_rx_tx_config_registers(tp); |
|
3920 |
|
3921 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3922 |
|
3923 RTL_R8(IntrMask); |
|
3924 |
|
3925 rtl_set_rx_mode(dev); |
|
3926 |
|
3927 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
3928 |
|
3929 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
3930 |
|
3931 if (!tp->ecdev) |
|
3932 RTL_W16(IntrMask, tp->intr_event); |
|
3933 } |
|
3934 |
|
3935 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
3936 { |
|
3937 struct rtl8169_private *tp = netdev_priv(dev); |
|
3938 int ret = 0; |
|
3939 |
|
3940 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
|
3941 return -EINVAL; |
|
3942 |
|
3943 dev->mtu = new_mtu; |
|
3944 |
|
3945 if (!netif_running(dev)) |
|
3946 goto out; |
|
3947 |
|
3948 rtl8169_down(dev); |
|
3949 |
|
3950 rtl8169_set_rxbufsize(tp, dev); |
|
3951 |
|
3952 ret = rtl8169_init_ring(dev); |
|
3953 if (ret < 0) |
|
3954 goto out; |
|
3955 |
|
3956 napi_enable(&tp->napi); |
|
3957 |
|
3958 rtl_hw_start(dev); |
|
3959 |
|
3960 rtl8169_request_timer(dev); |
|
3961 |
|
3962 out: |
|
3963 return ret; |
|
3964 } |
|
3965 |
|
3966 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
3967 { |
|
3968 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
3969 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
3970 } |
|
3971 |
|
3972 static void rtl8169_free_rx_skb(struct rtl8169_private *tp, |
|
3973 struct sk_buff **sk_buff, struct RxDesc *desc) |
|
3974 { |
|
3975 struct pci_dev *pdev = tp->pci_dev; |
|
3976 |
|
3977 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, |
|
3978 PCI_DMA_FROMDEVICE); |
|
3979 dev_kfree_skb(*sk_buff); |
|
3980 *sk_buff = NULL; |
|
3981 rtl8169_make_unusable_by_asic(desc); |
|
3982 } |
|
3983 |
|
3984 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
3985 { |
|
3986 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
3987 |
|
3988 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
3989 } |
|
3990 |
|
3991 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
3992 u32 rx_buf_sz) |
|
3993 { |
|
3994 desc->addr = cpu_to_le64(mapping); |
|
3995 wmb(); |
|
3996 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
3997 } |
|
3998 |
|
3999 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
|
4000 struct net_device *dev, |
|
4001 struct RxDesc *desc, int rx_buf_sz, |
|
4002 unsigned int align) |
|
4003 { |
|
4004 struct sk_buff *skb; |
|
4005 dma_addr_t mapping; |
|
4006 unsigned int pad; |
|
4007 |
|
4008 pad = align ? align : NET_IP_ALIGN; |
|
4009 |
|
4010 skb = netdev_alloc_skb(dev, rx_buf_sz + pad); |
|
4011 if (!skb) |
|
4012 goto err_out; |
|
4013 |
|
4014 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
|
4015 |
|
4016 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
4017 PCI_DMA_FROMDEVICE); |
|
4018 |
|
4019 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
4020 out: |
|
4021 return skb; |
|
4022 |
|
4023 err_out: |
|
4024 rtl8169_make_unusable_by_asic(desc); |
|
4025 goto out; |
|
4026 } |
|
4027 |
|
4028 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
4029 { |
|
4030 unsigned int i; |
|
4031 |
|
4032 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4033 if (tp->Rx_skbuff[i]) { |
|
4034 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, |
|
4035 tp->RxDescArray + i); |
|
4036 } |
|
4037 } |
|
4038 } |
|
4039 |
|
4040 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, |
|
4041 u32 start, u32 end) |
|
4042 { |
|
4043 u32 cur; |
|
4044 |
|
4045 for (cur = start; end - cur != 0; cur++) { |
|
4046 struct sk_buff *skb; |
|
4047 unsigned int i = cur % NUM_RX_DESC; |
|
4048 |
|
4049 WARN_ON((s32)(end - cur) < 0); |
|
4050 |
|
4051 if (tp->Rx_skbuff[i]) |
|
4052 continue; |
|
4053 |
|
4054 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
|
4055 tp->RxDescArray + i, |
|
4056 tp->rx_buf_sz, tp->align); |
|
4057 if (!skb) |
|
4058 break; |
|
4059 |
|
4060 tp->Rx_skbuff[i] = skb; |
|
4061 } |
|
4062 return cur - start; |
|
4063 } |
|
4064 |
|
4065 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
4066 { |
|
4067 desc->opts1 |= cpu_to_le32(RingEnd); |
|
4068 } |
|
4069 |
|
4070 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
4071 { |
|
4072 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
4073 } |
|
4074 |
|
4075 static int rtl8169_init_ring(struct net_device *dev) |
|
4076 { |
|
4077 struct rtl8169_private *tp = netdev_priv(dev); |
|
4078 |
|
4079 rtl8169_init_ring_indexes(tp); |
|
4080 |
|
4081 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
4082 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); |
|
4083 |
|
4084 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) |
|
4085 goto err_out; |
|
4086 |
|
4087 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
4088 |
|
4089 return 0; |
|
4090 |
|
4091 err_out: |
|
4092 rtl8169_rx_clear(tp); |
|
4093 return -ENOMEM; |
|
4094 } |
|
4095 |
|
4096 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, |
|
4097 struct TxDesc *desc) |
|
4098 { |
|
4099 unsigned int len = tx_skb->len; |
|
4100 |
|
4101 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); |
|
4102 desc->opts1 = 0x00; |
|
4103 desc->opts2 = 0x00; |
|
4104 desc->addr = 0x00; |
|
4105 tx_skb->len = 0; |
|
4106 } |
|
4107 |
|
4108 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
4109 { |
|
4110 unsigned int i; |
|
4111 |
|
4112 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { |
|
4113 unsigned int entry = i % NUM_TX_DESC; |
|
4114 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
4115 unsigned int len = tx_skb->len; |
|
4116 |
|
4117 if (len) { |
|
4118 struct sk_buff *skb = tx_skb->skb; |
|
4119 |
|
4120 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, |
|
4121 tp->TxDescArray + entry); |
|
4122 if (skb) { |
|
4123 if (!tp->ecdev) |
|
4124 dev_kfree_skb(skb); |
|
4125 tx_skb->skb = NULL; |
|
4126 } |
|
4127 tp->dev->stats.tx_dropped++; |
|
4128 } |
|
4129 } |
|
4130 tp->cur_tx = tp->dirty_tx = 0; |
|
4131 } |
|
4132 |
|
4133 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
|
4134 { |
|
4135 struct rtl8169_private *tp = netdev_priv(dev); |
|
4136 |
|
4137 PREPARE_DELAYED_WORK(&tp->task, task); |
|
4138 schedule_delayed_work(&tp->task, 4); |
|
4139 } |
|
4140 |
|
4141 static void rtl8169_wait_for_quiescence(struct net_device *dev) |
|
4142 { |
|
4143 struct rtl8169_private *tp = netdev_priv(dev); |
|
4144 void __iomem *ioaddr = tp->mmio_addr; |
|
4145 |
|
4146 synchronize_irq(dev->irq); |
|
4147 |
|
4148 /* Wait for any pending NAPI task to complete */ |
|
4149 napi_disable(&tp->napi); |
|
4150 |
|
4151 rtl8169_irq_mask_and_ack(ioaddr); |
|
4152 |
|
4153 tp->intr_mask = 0xffff; |
|
4154 RTL_W16(IntrMask, tp->intr_event); |
|
4155 napi_enable(&tp->napi); |
|
4156 } |
|
4157 |
|
4158 static void rtl8169_reinit_task(struct work_struct *work) |
|
4159 { |
|
4160 struct rtl8169_private *tp = |
|
4161 container_of(work, struct rtl8169_private, task.work); |
|
4162 struct net_device *dev = tp->dev; |
|
4163 int ret; |
|
4164 |
|
4165 rtnl_lock(); |
|
4166 |
|
4167 if (!netif_running(dev)) |
|
4168 goto out_unlock; |
|
4169 |
|
4170 rtl8169_wait_for_quiescence(dev); |
|
4171 rtl8169_close(dev); |
|
4172 |
|
4173 ret = rtl8169_open(dev); |
|
4174 if (unlikely(ret < 0)) { |
|
4175 if (net_ratelimit() && netif_msg_drv(tp)) { |
|
4176 printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
|
4177 " Rescheduling.\n", dev->name, ret); |
|
4178 } |
|
4179 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
4180 } |
|
4181 |
|
4182 out_unlock: |
|
4183 rtnl_unlock(); |
|
4184 } |
|
4185 |
|
4186 static void rtl8169_reset_task(struct work_struct *work) |
|
4187 { |
|
4188 struct rtl8169_private *tp = |
|
4189 container_of(work, struct rtl8169_private, task.work); |
|
4190 struct net_device *dev = tp->dev; |
|
4191 |
|
4192 rtnl_lock(); |
|
4193 |
|
4194 if (!netif_running(dev)) |
|
4195 goto out_unlock; |
|
4196 |
|
4197 rtl8169_wait_for_quiescence(dev); |
|
4198 |
|
4199 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
|
4200 rtl8169_tx_clear(tp); |
|
4201 |
|
4202 if (tp->dirty_rx == tp->cur_rx) { |
|
4203 rtl8169_init_ring_indexes(tp); |
|
4204 rtl_hw_start(dev); |
|
4205 netif_wake_queue(dev); |
|
4206 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
4207 } else { |
|
4208 if (net_ratelimit() && netif_msg_intr(tp)) { |
|
4209 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
|
4210 dev->name); |
|
4211 } |
|
4212 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4213 } |
|
4214 |
|
4215 out_unlock: |
|
4216 rtnl_unlock(); |
|
4217 } |
|
4218 |
|
4219 static void rtl8169_tx_timeout(struct net_device *dev) |
|
4220 { |
|
4221 struct rtl8169_private *tp = netdev_priv(dev); |
|
4222 |
|
4223 if (tp->ecdev) |
|
4224 return; |
|
4225 |
|
4226 rtl8169_hw_reset(tp->mmio_addr); |
|
4227 |
|
4228 /* Let's wait a bit while any (async) irq lands on */ |
|
4229 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4230 } |
|
4231 |
|
4232 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
4233 u32 opts1) |
|
4234 { |
|
4235 struct skb_shared_info *info = skb_shinfo(skb); |
|
4236 unsigned int cur_frag, entry; |
|
4237 struct TxDesc * uninitialized_var(txd); |
|
4238 |
|
4239 entry = tp->cur_tx; |
|
4240 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
4241 skb_frag_t *frag = info->frags + cur_frag; |
|
4242 dma_addr_t mapping; |
|
4243 u32 status, len; |
|
4244 void *addr; |
|
4245 |
|
4246 entry = (entry + 1) % NUM_TX_DESC; |
|
4247 |
|
4248 txd = tp->TxDescArray + entry; |
|
4249 len = frag->size; |
|
4250 addr = ((void *) page_address(frag->page)) + frag->page_offset; |
|
4251 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); |
|
4252 |
|
4253 /* anti gcc 2.95.3 bugware (sic) */ |
|
4254 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
4255 |
|
4256 txd->opts1 = cpu_to_le32(status); |
|
4257 txd->addr = cpu_to_le64(mapping); |
|
4258 |
|
4259 tp->tx_skb[entry].len = len; |
|
4260 } |
|
4261 |
|
4262 if (cur_frag) { |
|
4263 tp->tx_skb[entry].skb = skb; |
|
4264 txd->opts1 |= cpu_to_le32(LastFrag); |
|
4265 } |
|
4266 |
|
4267 return cur_frag; |
|
4268 } |
|
4269 |
|
4270 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) |
|
4271 { |
|
4272 if (dev->features & NETIF_F_TSO) { |
|
4273 u32 mss = skb_shinfo(skb)->gso_size; |
|
4274 |
|
4275 if (mss) |
|
4276 return LargeSend | ((mss & MSSMask) << MSSShift); |
|
4277 } |
|
4278 if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
4279 const struct iphdr *ip = ip_hdr(skb); |
|
4280 |
|
4281 if (ip->protocol == IPPROTO_TCP) |
|
4282 return IPCS | TCPCS; |
|
4283 else if (ip->protocol == IPPROTO_UDP) |
|
4284 return IPCS | UDPCS; |
|
4285 WARN_ON(1); /* we need a WARN() */ |
|
4286 } |
|
4287 return 0; |
|
4288 } |
|
4289 |
|
4290 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
4291 struct net_device *dev) |
|
4292 { |
|
4293 struct rtl8169_private *tp = netdev_priv(dev); |
|
4294 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; |
|
4295 struct TxDesc *txd = tp->TxDescArray + entry; |
|
4296 void __iomem *ioaddr = tp->mmio_addr; |
|
4297 dma_addr_t mapping; |
|
4298 u32 status, len; |
|
4299 u32 opts1; |
|
4300 |
|
4301 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
|
4302 if (netif_msg_drv(tp)) { |
|
4303 printk(KERN_ERR |
|
4304 "%s: BUG! Tx Ring full when queue awake!\n", |
|
4305 dev->name); |
|
4306 } |
|
4307 goto err_stop; |
|
4308 } |
|
4309 |
|
4310 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
4311 goto err_stop; |
|
4312 |
|
4313 opts1 = DescOwn | rtl8169_tso_csum(skb, dev); |
|
4314 |
|
4315 frags = rtl8169_xmit_frags(tp, skb, opts1); |
|
4316 if (frags) { |
|
4317 len = skb_headlen(skb); |
|
4318 opts1 |= FirstFrag; |
|
4319 } else { |
|
4320 len = skb->len; |
|
4321 opts1 |= FirstFrag | LastFrag; |
|
4322 tp->tx_skb[entry].skb = skb; |
|
4323 } |
|
4324 |
|
4325 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
|
4326 |
|
4327 tp->tx_skb[entry].len = len; |
|
4328 txd->addr = cpu_to_le64(mapping); |
|
4329 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
4330 |
|
4331 wmb(); |
|
4332 |
|
4333 /* anti gcc 2.95.3 bugware (sic) */ |
|
4334 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
4335 txd->opts1 = cpu_to_le32(status); |
|
4336 |
|
4337 tp->cur_tx += frags + 1; |
|
4338 |
|
4339 smp_wmb(); |
|
4340 |
|
4341 RTL_W8(TxPoll, NPQ); /* set polling bit */ |
|
4342 |
|
4343 if (!tp->ecdev) { |
|
4344 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { |
|
4345 netif_stop_queue(dev); |
|
4346 smp_rmb(); |
|
4347 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) |
|
4348 netif_wake_queue(dev); |
|
4349 } |
|
4350 } |
|
4351 |
|
4352 return NETDEV_TX_OK; |
|
4353 |
|
4354 err_stop: |
|
4355 if (!tp->ecdev) |
|
4356 netif_stop_queue(dev); |
|
4357 dev->stats.tx_dropped++; |
|
4358 return NETDEV_TX_BUSY; |
|
4359 } |
|
4360 |
|
4361 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
4362 { |
|
4363 struct rtl8169_private *tp = netdev_priv(dev); |
|
4364 struct pci_dev *pdev = tp->pci_dev; |
|
4365 void __iomem *ioaddr = tp->mmio_addr; |
|
4366 u16 pci_status, pci_cmd; |
|
4367 |
|
4368 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
4369 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
4370 |
|
4371 if (netif_msg_intr(tp)) { |
|
4372 printk(KERN_ERR |
|
4373 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", |
|
4374 dev->name, pci_cmd, pci_status); |
|
4375 } |
|
4376 |
|
4377 /* |
|
4378 * The recovery sequence below admits a very elaborated explanation: |
|
4379 * - it seems to work; |
|
4380 * - I did not see what else could be done; |
|
4381 * - it makes iop3xx happy. |
|
4382 * |
|
4383 * Feel free to adjust to your needs. |
|
4384 */ |
|
4385 if (pdev->broken_parity_status) |
|
4386 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
4387 else |
|
4388 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
4389 |
|
4390 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
4391 |
|
4392 pci_write_config_word(pdev, PCI_STATUS, |
|
4393 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
4394 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
4395 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
4396 |
|
4397 /* The infamous DAC f*ckup only happens at boot time */ |
|
4398 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
4399 if (netif_msg_intr(tp)) |
|
4400 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); |
|
4401 tp->cp_cmd &= ~PCIDAC; |
|
4402 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4403 dev->features &= ~NETIF_F_HIGHDMA; |
|
4404 } |
|
4405 |
|
4406 rtl8169_hw_reset(ioaddr); |
|
4407 |
|
4408 rtl8169_schedule_work(dev, rtl8169_reinit_task); |
|
4409 } |
|
4410 |
|
4411 static void rtl8169_tx_interrupt(struct net_device *dev, |
|
4412 struct rtl8169_private *tp, |
|
4413 void __iomem *ioaddr) |
|
4414 { |
|
4415 unsigned int dirty_tx, tx_left; |
|
4416 |
|
4417 dirty_tx = tp->dirty_tx; |
|
4418 smp_rmb(); |
|
4419 tx_left = tp->cur_tx - dirty_tx; |
|
4420 |
|
4421 while (tx_left > 0) { |
|
4422 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
4423 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
4424 u32 len = tx_skb->len; |
|
4425 u32 status; |
|
4426 |
|
4427 rmb(); |
|
4428 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
4429 if (status & DescOwn) |
|
4430 break; |
|
4431 |
|
4432 dev->stats.tx_bytes += len; |
|
4433 dev->stats.tx_packets++; |
|
4434 |
|
4435 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); |
|
4436 |
|
4437 if (status & LastFrag) { |
|
4438 if (!tp->ecdev) |
|
4439 dev_kfree_skb(tx_skb->skb); |
|
4440 tx_skb->skb = NULL; |
|
4441 } |
|
4442 dirty_tx++; |
|
4443 tx_left--; |
|
4444 } |
|
4445 |
|
4446 if (tp->dirty_tx != dirty_tx) { |
|
4447 tp->dirty_tx = dirty_tx; |
|
4448 smp_wmb(); |
|
4449 if (!tp->ecdev && netif_queue_stopped(dev) && |
|
4450 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { |
|
4451 netif_wake_queue(dev); |
|
4452 } |
|
4453 /* |
|
4454 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
4455 * too close. Let's kick an extra TxPoll request when a burst |
|
4456 * of start_xmit activity is detected (if it is not detected, |
|
4457 * it is slow enough). -- FR |
|
4458 */ |
|
4459 smp_rmb(); |
|
4460 if (tp->cur_tx != dirty_tx) |
|
4461 RTL_W8(TxPoll, NPQ); |
|
4462 } |
|
4463 } |
|
4464 |
|
4465 static inline int rtl8169_fragmented_frame(u32 status) |
|
4466 { |
|
4467 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
4468 } |
|
4469 |
|
4470 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
|
4471 { |
|
4472 u32 opts1 = le32_to_cpu(desc->opts1); |
|
4473 u32 status = opts1 & RxProtoMask; |
|
4474 |
|
4475 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
4476 ((status == RxProtoUDP) && !(opts1 & UDPFail)) || |
|
4477 ((status == RxProtoIP) && !(opts1 & IPFail))) |
|
4478 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
4479 else |
|
4480 skb->ip_summed = CHECKSUM_NONE; |
|
4481 } |
|
4482 |
|
4483 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
|
4484 struct rtl8169_private *tp, int pkt_size, |
|
4485 dma_addr_t addr) |
|
4486 { |
|
4487 struct sk_buff *skb; |
|
4488 bool done = false; |
|
4489 |
|
4490 if (pkt_size >= rx_copybreak) |
|
4491 goto out; |
|
4492 |
|
4493 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
|
4494 if (!skb) |
|
4495 goto out; |
|
4496 |
|
4497 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
|
4498 PCI_DMA_FROMDEVICE); |
|
4499 skb_reserve(skb, NET_IP_ALIGN); |
|
4500 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
|
4501 *sk_buff = skb; |
|
4502 done = true; |
|
4503 out: |
|
4504 return done; |
|
4505 } |
|
4506 |
|
4507 static int rtl8169_rx_interrupt(struct net_device *dev, |
|
4508 struct rtl8169_private *tp, |
|
4509 void __iomem *ioaddr, u32 budget) |
|
4510 { |
|
4511 unsigned int cur_rx, rx_left; |
|
4512 unsigned int delta, count; |
|
4513 |
|
4514 cur_rx = tp->cur_rx; |
|
4515 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
4516 rx_left = min(rx_left, budget); |
|
4517 |
|
4518 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
4519 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
4520 struct RxDesc *desc = tp->RxDescArray + entry; |
|
4521 u32 status; |
|
4522 |
|
4523 rmb(); |
|
4524 status = le32_to_cpu(desc->opts1); |
|
4525 |
|
4526 if (status & DescOwn) |
|
4527 break; |
|
4528 if (unlikely(status & RxRES)) { |
|
4529 if (netif_msg_rx_err(tp)) { |
|
4530 printk(KERN_INFO |
|
4531 "%s: Rx ERROR. status = %08x\n", |
|
4532 dev->name, status); |
|
4533 } |
|
4534 dev->stats.rx_errors++; |
|
4535 if (status & (RxRWT | RxRUNT)) |
|
4536 dev->stats.rx_length_errors++; |
|
4537 if (status & RxCRC) |
|
4538 dev->stats.rx_crc_errors++; |
|
4539 if (status & RxFOVF) { |
|
4540 if (!tp->ecdev) |
|
4541 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4542 dev->stats.rx_fifo_errors++; |
|
4543 } |
|
4544 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
4545 } else { |
|
4546 struct sk_buff *skb = tp->Rx_skbuff[entry]; |
|
4547 dma_addr_t addr = le64_to_cpu(desc->addr); |
|
4548 int pkt_size = (status & 0x00001FFF) - 4; |
|
4549 struct pci_dev *pdev = tp->pci_dev; |
|
4550 |
|
4551 /* |
|
4552 * The driver does not support incoming fragmented |
|
4553 * frames. They are seen as a symptom of over-mtu |
|
4554 * sized frames. |
|
4555 */ |
|
4556 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
4557 dev->stats.rx_dropped++; |
|
4558 dev->stats.rx_length_errors++; |
|
4559 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
4560 continue; |
|
4561 } |
|
4562 |
|
4563 rtl8169_rx_csum(skb, desc); |
|
4564 |
|
4565 if (tp->ecdev) { |
|
4566 pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, |
|
4567 PCI_DMA_FROMDEVICE); |
|
4568 |
|
4569 ecdev_receive(tp->ecdev, skb->data, pkt_size); |
|
4570 |
|
4571 pci_dma_sync_single_for_device(pdev, addr, |
|
4572 pkt_size, PCI_DMA_FROMDEVICE); |
|
4573 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
4574 |
|
4575 // No need to detect link status as |
|
4576 // long as frames are received: Reset watchdog. |
|
4577 tp->ec_watchdog_jiffies = jiffies; |
|
4578 } else { |
|
4579 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
|
4580 pci_dma_sync_single_for_device(pdev, addr, |
|
4581 pkt_size, PCI_DMA_FROMDEVICE); |
|
4582 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
|
4583 } else { |
|
4584 pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
|
4585 PCI_DMA_FROMDEVICE); |
|
4586 tp->Rx_skbuff[entry] = NULL; |
|
4587 } |
|
4588 |
|
4589 skb_put(skb, pkt_size); |
|
4590 skb->protocol = eth_type_trans(skb, dev); |
|
4591 |
|
4592 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) |
|
4593 netif_receive_skb(skb); |
|
4594 } |
|
4595 dev->stats.rx_bytes += pkt_size; |
|
4596 dev->stats.rx_packets++; |
|
4597 } |
|
4598 |
|
4599 /* Work around for AMD plateform. */ |
|
4600 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
4601 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
4602 desc->opts2 = 0; |
|
4603 cur_rx++; |
|
4604 } |
|
4605 } |
|
4606 |
|
4607 count = cur_rx - tp->cur_rx; |
|
4608 tp->cur_rx = cur_rx; |
|
4609 |
|
4610 if (tp->ecdev) { |
|
4611 /* descriptors are cleaned up immediately. */ |
|
4612 tp->dirty_rx = tp->cur_rx; |
|
4613 } else { |
|
4614 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); |
|
4615 if (!delta && count && netif_msg_intr(tp)) |
|
4616 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
|
4617 tp->dirty_rx += delta; |
|
4618 |
|
4619 /* |
|
4620 * FIXME: until there is periodic timer to try and refill the ring, |
|
4621 * a temporary shortage may definitely kill the Rx process. |
|
4622 * - disable the asic to try and avoid an overflow and kick it again |
|
4623 * after refill ? |
|
4624 * - how do others driver handle this condition (Uh oh...). |
|
4625 */ |
|
4626 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
|
4627 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
|
4628 } |
|
4629 |
|
4630 return count; |
|
4631 } |
|
4632 |
|
4633 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
4634 { |
|
4635 struct net_device *dev = dev_instance; |
|
4636 struct rtl8169_private *tp = netdev_priv(dev); |
|
4637 void __iomem *ioaddr = tp->mmio_addr; |
|
4638 int handled = 0; |
|
4639 int status; |
|
4640 |
|
4641 /* loop handling interrupts until we have no new ones or |
|
4642 * we hit a invalid/hotplug case. |
|
4643 */ |
|
4644 status = RTL_R16(IntrStatus); |
|
4645 while (status && status != 0xffff) { |
|
4646 handled = 1; |
|
4647 |
|
4648 /* Handle all of the error cases first. These will reset |
|
4649 * the chip, so just exit the loop. |
|
4650 */ |
|
4651 if (unlikely(!tp->ecdev && !netif_running(dev))) { |
|
4652 rtl8169_asic_down(ioaddr); |
|
4653 break; |
|
4654 } |
|
4655 |
|
4656 /* Work around for rx fifo overflow */ |
|
4657 if (unlikely(status & RxFIFOOver) && |
|
4658 (tp->mac_version == RTL_GIGA_MAC_VER_11)) { |
|
4659 netif_stop_queue(dev); |
|
4660 rtl8169_tx_timeout(dev); |
|
4661 break; |
|
4662 } |
|
4663 |
|
4664 if (unlikely(status & SYSErr)) { |
|
4665 rtl8169_pcierr_interrupt(dev); |
|
4666 break; |
|
4667 } |
|
4668 |
|
4669 if (status & LinkChg) |
|
4670 rtl8169_check_link_status(dev, tp, ioaddr); |
|
4671 |
|
4672 /* We need to see the lastest version of tp->intr_mask to |
|
4673 * avoid ignoring an MSI interrupt and having to wait for |
|
4674 * another event which may never come. |
|
4675 */ |
|
4676 smp_rmb(); |
|
4677 if (status & tp->intr_mask & tp->napi_event) { |
|
4678 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); |
|
4679 tp->intr_mask = ~tp->napi_event; |
|
4680 |
|
4681 if (likely(napi_schedule_prep(&tp->napi))) |
|
4682 __napi_schedule(&tp->napi); |
|
4683 else if (netif_msg_intr(tp)) { |
|
4684 printk(KERN_INFO "%s: interrupt %04x in poll\n", |
|
4685 dev->name, status); |
|
4686 } |
|
4687 } |
|
4688 |
|
4689 /* We only get a new MSI interrupt when all active irq |
|
4690 * sources on the chip have been acknowledged. So, ack |
|
4691 * everything we've seen and check if new sources have become |
|
4692 * active to avoid blocking all interrupts from the chip. |
|
4693 */ |
|
4694 RTL_W16(IntrStatus, |
|
4695 (status & RxFIFOOver) ? (status | RxOverflow) : status); |
|
4696 status = RTL_R16(IntrStatus); |
|
4697 } |
|
4698 |
|
4699 return IRQ_RETVAL(handled); |
|
4700 } |
|
4701 |
|
4702 static void ec_poll(struct net_device *dev) |
|
4703 { |
|
4704 struct rtl8169_private *tp = netdev_priv(dev); |
|
4705 struct pci_dev *pdev = tp->pci_dev; |
|
4706 |
|
4707 rtl8169_interrupt(pdev->irq, dev); |
|
4708 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, 100); // FIXME |
|
4709 rtl8169_tx_interrupt(dev, tp, tp->mmio_addr); |
|
4710 |
|
4711 if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { |
|
4712 rtl8169_phy_timer((unsigned long) dev); |
|
4713 tp->ec_watchdog_jiffies = jiffies; |
|
4714 } |
|
4715 } |
|
4716 |
|
4717 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
4718 { |
|
4719 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
4720 struct net_device *dev = tp->dev; |
|
4721 void __iomem *ioaddr = tp->mmio_addr; |
|
4722 int work_done; |
|
4723 |
|
4724 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
|
4725 rtl8169_tx_interrupt(dev, tp, ioaddr); |
|
4726 |
|
4727 if (work_done < budget) { |
|
4728 napi_complete(napi); |
|
4729 |
|
4730 /* We need for force the visibility of tp->intr_mask |
|
4731 * for other CPUs, as we can loose an MSI interrupt |
|
4732 * and potentially wait for a retransmit timeout if we don't. |
|
4733 * The posted write to IntrMask is safe, as it will |
|
4734 * eventually make it to the chip and we won't loose anything |
|
4735 * until it does. |
|
4736 */ |
|
4737 tp->intr_mask = 0xffff; |
|
4738 smp_wmb(); |
|
4739 RTL_W16(IntrMask, tp->intr_event); |
|
4740 } |
|
4741 |
|
4742 return work_done; |
|
4743 } |
|
4744 |
|
4745 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
4746 { |
|
4747 struct rtl8169_private *tp = netdev_priv(dev); |
|
4748 |
|
4749 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
4750 return; |
|
4751 |
|
4752 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
4753 RTL_W32(RxMissed, 0); |
|
4754 } |
|
4755 |
|
4756 static void rtl8169_down(struct net_device *dev) |
|
4757 { |
|
4758 struct rtl8169_private *tp = netdev_priv(dev); |
|
4759 void __iomem *ioaddr = tp->mmio_addr; |
|
4760 unsigned int intrmask; |
|
4761 |
|
4762 rtl8169_delete_timer(dev); |
|
4763 |
|
4764 if (!tp->ecdev) { |
|
4765 netif_stop_queue(dev); |
|
4766 |
|
4767 napi_disable(&tp->napi); |
|
4768 |
|
4769 } |
|
4770 |
|
4771 core_down: |
|
4772 if (!tp->ecdev) |
|
4773 spin_lock_irq(&tp->lock); |
|
4774 |
|
4775 rtl8169_asic_down(ioaddr); |
|
4776 |
|
4777 rtl8169_rx_missed(dev, ioaddr); |
|
4778 |
|
4779 if (!tp->ecdev) |
|
4780 spin_unlock_irq(&tp->lock); |
|
4781 |
|
4782 if (!tp->ecdev) |
|
4783 synchronize_irq(dev->irq); |
|
4784 |
|
4785 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
4786 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
|
4787 |
|
4788 /* |
|
4789 * And now for the 50k$ question: are IRQ disabled or not ? |
|
4790 * |
|
4791 * Two paths lead here: |
|
4792 * 1) dev->close |
|
4793 * -> netif_running() is available to sync the current code and the |
|
4794 * IRQ handler. See rtl8169_interrupt for details. |
|
4795 * 2) dev->change_mtu |
|
4796 * -> rtl8169_poll can not be issued again and re-enable the |
|
4797 * interruptions. Let's simply issue the IRQ down sequence again. |
|
4798 * |
|
4799 * No loop if hotpluged or major error (0xffff). |
|
4800 */ |
|
4801 intrmask = RTL_R16(IntrMask); |
|
4802 if (intrmask && (intrmask != 0xffff)) |
|
4803 goto core_down; |
|
4804 |
|
4805 rtl8169_tx_clear(tp); |
|
4806 |
|
4807 rtl8169_rx_clear(tp); |
|
4808 } |
|
4809 |
|
4810 static int rtl8169_close(struct net_device *dev) |
|
4811 { |
|
4812 struct rtl8169_private *tp = netdev_priv(dev); |
|
4813 struct pci_dev *pdev = tp->pci_dev; |
|
4814 |
|
4815 /* update counters before going down */ |
|
4816 rtl8169_update_counters(dev); |
|
4817 |
|
4818 rtl8169_down(dev); |
|
4819 |
|
4820 if (!tp->ecdev) |
|
4821 free_irq(dev->irq, dev); |
|
4822 |
|
4823 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
4824 tp->RxPhyAddr); |
|
4825 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
4826 tp->TxPhyAddr); |
|
4827 tp->TxDescArray = NULL; |
|
4828 tp->RxDescArray = NULL; |
|
4829 |
|
4830 return 0; |
|
4831 } |
|
4832 |
|
4833 static void rtl_set_rx_mode(struct net_device *dev) |
|
4834 { |
|
4835 struct rtl8169_private *tp = netdev_priv(dev); |
|
4836 void __iomem *ioaddr = tp->mmio_addr; |
|
4837 unsigned long flags; |
|
4838 u32 mc_filter[2]; /* Multicast hash filter */ |
|
4839 int rx_mode; |
|
4840 u32 tmp = 0; |
|
4841 |
|
4842 if (dev->flags & IFF_PROMISC) { |
|
4843 /* Unconditionally log net taps. */ |
|
4844 if (netif_msg_link(tp)) { |
|
4845 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", |
|
4846 dev->name); |
|
4847 } |
|
4848 rx_mode = |
|
4849 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
4850 AcceptAllPhys; |
|
4851 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4852 } else if ((dev->mc_count > multicast_filter_limit) |
|
4853 || (dev->flags & IFF_ALLMULTI)) { |
|
4854 /* Too many to filter perfectly -- accept all multicasts. */ |
|
4855 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
4856 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4857 } else { |
|
4858 struct dev_mc_list *mclist; |
|
4859 unsigned int i; |
|
4860 |
|
4861 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
4862 mc_filter[1] = mc_filter[0] = 0; |
|
4863 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; |
|
4864 i++, mclist = mclist->next) { |
|
4865 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; |
|
4866 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
4867 rx_mode |= AcceptMulticast; |
|
4868 } |
|
4869 } |
|
4870 |
|
4871 spin_lock_irqsave(&tp->lock, flags); |
|
4872 |
|
4873 tmp = rtl8169_rx_config | rx_mode | |
|
4874 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
|
4875 |
|
4876 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
4877 u32 data = mc_filter[0]; |
|
4878 |
|
4879 mc_filter[0] = swab32(mc_filter[1]); |
|
4880 mc_filter[1] = swab32(data); |
|
4881 } |
|
4882 |
|
4883 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
4884 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
4885 |
|
4886 RTL_W32(RxConfig, tmp); |
|
4887 |
|
4888 spin_unlock_irqrestore(&tp->lock, flags); |
|
4889 } |
|
4890 |
|
4891 /** |
|
4892 * rtl8169_get_stats - Get rtl8169 read/write statistics |
|
4893 * @dev: The Ethernet Device to get statistics for |
|
4894 * |
|
4895 * Get TX/RX statistics for rtl8169 |
|
4896 */ |
|
4897 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) |
|
4898 { |
|
4899 struct rtl8169_private *tp = netdev_priv(dev); |
|
4900 void __iomem *ioaddr = tp->mmio_addr; |
|
4901 unsigned long flags; |
|
4902 |
|
4903 if (netif_running(dev)) { |
|
4904 spin_lock_irqsave(&tp->lock, flags); |
|
4905 rtl8169_rx_missed(dev, ioaddr); |
|
4906 spin_unlock_irqrestore(&tp->lock, flags); |
|
4907 } |
|
4908 |
|
4909 return &dev->stats; |
|
4910 } |
|
4911 |
|
4912 static void rtl8169_net_suspend(struct net_device *dev) |
|
4913 { |
|
4914 if (!netif_running(dev)) |
|
4915 return; |
|
4916 |
|
4917 netif_device_detach(dev); |
|
4918 netif_stop_queue(dev); |
|
4919 } |
|
4920 |
|
4921 #ifdef CONFIG_PM |
|
4922 |
|
4923 static int rtl8169_suspend(struct device *device) |
|
4924 { |
|
4925 struct pci_dev *pdev = to_pci_dev(device); |
|
4926 struct net_device *dev = pci_get_drvdata(pdev); |
|
4927 struct rtl8169_private *tp = netdev_priv(dev); |
|
4928 |
|
4929 if (tp->ecdev) |
|
4930 return -EBUSY; |
|
4931 |
|
4932 rtl8169_net_suspend(dev); |
|
4933 |
|
4934 return 0; |
|
4935 } |
|
4936 |
|
4937 static int rtl8169_resume(struct device *device) |
|
4938 { |
|
4939 struct pci_dev *pdev = to_pci_dev(device); |
|
4940 struct net_device *dev = pci_get_drvdata(pdev); |
|
4941 struct rtl8169_private *tp = netdev_priv(dev); |
|
4942 |
|
4943 if (tp->ecdev) |
|
4944 return -EBUSY; |
|
4945 |
|
4946 if (!netif_running(dev)) |
|
4947 goto out; |
|
4948 |
|
4949 netif_device_attach(dev); |
|
4950 |
|
4951 rtl8169_schedule_work(dev, rtl8169_reset_task); |
|
4952 out: |
|
4953 return 0; |
|
4954 } |
|
4955 |
|
4956 static struct dev_pm_ops rtl8169_pm_ops = { |
|
4957 .suspend = rtl8169_suspend, |
|
4958 .resume = rtl8169_resume, |
|
4959 .freeze = rtl8169_suspend, |
|
4960 .thaw = rtl8169_resume, |
|
4961 .poweroff = rtl8169_suspend, |
|
4962 .restore = rtl8169_resume, |
|
4963 }; |
|
4964 |
|
4965 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
4966 |
|
4967 #else /* !CONFIG_PM */ |
|
4968 |
|
4969 #define RTL8169_PM_OPS NULL |
|
4970 |
|
4971 #endif /* !CONFIG_PM */ |
|
4972 |
|
4973 static void rtl_shutdown(struct pci_dev *pdev) |
|
4974 { |
|
4975 struct net_device *dev = pci_get_drvdata(pdev); |
|
4976 struct rtl8169_private *tp = netdev_priv(dev); |
|
4977 void __iomem *ioaddr = tp->mmio_addr; |
|
4978 |
|
4979 rtl8169_net_suspend(dev); |
|
4980 |
|
4981 /* restore original MAC address */ |
|
4982 rtl_rar_set(tp, dev->perm_addr); |
|
4983 |
|
4984 spin_lock_irq(&tp->lock); |
|
4985 |
|
4986 rtl8169_asic_down(ioaddr); |
|
4987 |
|
4988 spin_unlock_irq(&tp->lock); |
|
4989 |
|
4990 if (system_state == SYSTEM_POWER_OFF) { |
|
4991 /* WoL fails with some 8168 when the receiver is disabled. */ |
|
4992 if (tp->features & RTL_FEATURE_WOL) { |
|
4993 pci_clear_master(pdev); |
|
4994 |
|
4995 RTL_W8(ChipCmd, CmdRxEnb); |
|
4996 /* PCI commit */ |
|
4997 RTL_R8(ChipCmd); |
|
4998 } |
|
4999 |
|
5000 pci_wake_from_d3(pdev, true); |
|
5001 pci_set_power_state(pdev, PCI_D3hot); |
|
5002 } |
|
5003 } |
|
5004 |
|
5005 static struct pci_driver rtl8169_pci_driver = { |
|
5006 .name = MODULENAME, |
|
5007 .id_table = rtl8169_pci_tbl, |
|
5008 .probe = rtl8169_init_one, |
|
5009 .remove = __devexit_p(rtl8169_remove_one), |
|
5010 .shutdown = rtl_shutdown, |
|
5011 .driver.pm = RTL8169_PM_OPS, |
|
5012 }; |
|
5013 |
|
5014 static int __init rtl8169_init_module(void) |
|
5015 { |
|
5016 return pci_register_driver(&rtl8169_pci_driver); |
|
5017 } |
|
5018 |
|
5019 static void __exit rtl8169_cleanup_module(void) |
|
5020 { |
|
5021 pci_unregister_driver(&rtl8169_pci_driver); |
|
5022 } |
|
5023 |
|
5024 module_init(rtl8169_init_module); |
|
5025 module_exit(rtl8169_cleanup_module); |