1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2007  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *  vim: noexpandtab

    33  *

    34  *****************************************************************************/

    35 

    36 /**

    37    \file

    38    EtherCAT driver for e100-compatible NICs.

    39 */

    40 

    41 /* Former documentation: */

    42 

    43 /*******************************************************************************

    44   Intel PRO/100 Linux driver

    45   Copyright(c) 1999 - 2006 Intel Corporation.

    46 

    47   This program is free software; you can redistribute it and/or modify it

    48   under the terms and conditions of the GNU General Public License,

    49   version 2, as published by the Free Software Foundation.

    50 

    51   This program is distributed in the hope it will be useful, but WITHOUT

    52   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    53   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    54   more details.

    55 

    56   You should have received a copy of the GNU General Public License along with

    57   this program; if not, write to the Free Software Foundation, Inc.,

    58   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

    59 

    60   The full GNU General Public License is included in this distribution in

    61   the file called "COPYING".

    62 

    63   Contact Information:

    64   Linux NICS <linux.nics@intel.com>

    65   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>

    66   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    67 

    68 *******************************************************************************/

    69 

    70 /*

    71  *	e100.c: Intel(R) PRO/100 ethernet driver

    72  *

    73  *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    74  *	original e100 driver, but better described as a munging of

    75  *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    76  *

    77  *	References:

    78  *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    79  *		Open Source Software Developers Manual,

    80  *		http://sourceforge.net/projects/e1000

    81  *

    82  *

    83  *	                      Theory of Operation

    84  *

    85  *	I.   General

    86  *

    87  *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    88  *	controller family, which includes the 82557, 82558, 82559, 82550,

    89  *	82551, and 82562 devices.  82558 and greater controllers

    90  *	integrate the Intel 82555 PHY.  The controllers are used in

    91  *	server and client network interface cards, as well as in

    92  *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    93  *	configurations.  8255x supports a 32-bit linear addressing

    94  *	mode and operates at 33Mhz PCI clock rate.

    95  *

    96  *	II.  Driver Operation

    97  *

    98  *	Memory-mapped mode is used exclusively to access the device's

    99  *	shared-memory structure, the Control/Status Registers (CSR). All

   100  *	setup, configuration, and control of the device, including queuing

   101  *	of Tx, Rx, and configuration commands is through the CSR.

   102  *	cmd_lock serializes accesses to the CSR command register.  cb_lock

   103  *	protects the shared Command Block List (CBL).

   104  *

   105  *	8255x is highly MII-compliant and all access to the PHY go

   106  *	through the Management Data Interface (MDI).  Consequently, the

   107  *	driver leverages the mii.c library shared with other MII-compliant

   108  *	devices.

   109  *

   110  *	Big- and Little-Endian byte order as well as 32- and 64-bit

   111  *	archs are supported.  Weak-ordered memory and non-cache-coherent

   112  *	archs are supported.

   113  *

   114  *	III. Transmit

   115  *

   116  *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

   117  *	together in a fixed-size ring (CBL) thus forming the flexible mode

   118  *	memory structure.  A TCB marked with the suspend-bit indicates

   119  *	the end of the ring.  The last TCB processed suspends the

   120  *	controller, and the controller can be restarted by issue a CU

   121  *	resume command to continue from the suspend point, or a CU start

   122  *	command to start at a given position in the ring.

   123  *

   124  *	Non-Tx commands (config, multicast setup, etc) are linked

   125  *	into the CBL ring along with Tx commands.  The common structure

   126  *	used for both Tx and non-Tx commands is the Command Block (CB).

   127  *

   128  *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

   129  *	is the next CB to check for completion; cb_to_send is the first

   130  *	CB to start on in case of a previous failure to resume.  CB clean

   131  *	up happens in interrupt context in response to a CU interrupt.

   132  *	cbs_avail keeps track of number of free CB resources available.

   133  *

   134  * 	Hardware padding of short packets to minimum packet size is

   135  * 	enabled.  82557 pads with 7Eh, while the later controllers pad

   136  * 	with 00h.

   137  *

   138  *	IV.  Recieve

   139  *

   140  *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   141  *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   142  *	memory structure.  Rx skbs are allocated to contain both the RFD

   143  *	and the data buffer, but the RFD is pulled off before the skb is

   144  *	indicated.  The data buffer is aligned such that encapsulated

   145  *	protocol headers are u32-aligned.  Since the RFD is part of the

   146  *	mapped shared memory, and completion status is contained within

   147  *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   148  *	view from software and hardware.

   149  *

   150  *	Under typical operation, the  receive unit (RU) is start once,

   151  *	and the controller happily fills RFDs as frames arrive.  If

   152  *	replacement RFDs cannot be allocated, or the RU goes non-active,

   153  *	the RU must be restarted.  Frame arrival generates an interrupt,

   154  *	and Rx indication and re-allocation happen in the same context,

   155  *	therefore no locking is required.  A software-generated interrupt

   156  *	is generated from the watchdog to recover from a failed allocation

   157  *	senario where all Rx resources have been indicated and none re-

   158  *	placed.

   159  *

   160  *	V.   Miscellaneous

   161  *

   162  * 	VLAN offloading of tagging, stripping and filtering is not

   163  * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   164  * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   165  * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   166  * 	not supported (hardware limitation).

   167  *

   168  * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   169  *

   170  * 	Thanks to JC (jchapman@katalix.com) for helping with

   171  * 	testing/troubleshooting the development driver.

   172  *

   173  * 	TODO:

   174  * 	o several entry points race with dev->close

   175  * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   176  *

   177  *	FIXES:

   178  * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   179  *	- Stratus87247: protect MDI control register manipulations

   180  */

   181 

   182 #include <linux/module.h>

   183 #include <linux/moduleparam.h>

   184 #include <linux/kernel.h>

   185 #include <linux/types.h>

   186 #include <linux/slab.h>

   187 #include <linux/delay.h>

   188 #include <linux/init.h>

   189 #include <linux/pci.h>

   190 #include <linux/dma-mapping.h>

   191 #include <linux/netdevice.h>

   192 #include <linux/etherdevice.h>

   193 #include <linux/mii.h>

   194 #include <linux/if_vlan.h>

   195 #include <linux/skbuff.h>

   196 #include <linux/ethtool.h>

   197 #include <linux/string.h>

   198 #include <asm/unaligned.h>

   199 

   200 // EtherCAT includes

   201 #include "../globals.h"

   202 #include "ecdev.h"

   203 

   204 #define DRV_NAME		"ec_e100"

   205 #define DRV_EXT			"-NAPI"

   206 #define DRV_VERSION		"3.5.17-k2"DRV_EXT

   207 #define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

   208 #define DRV_COPYRIGHT		"Copyright(c) 1999-2006 Intel Corporation"

   209 #define PFX			DRV_NAME ": "

   210 

   211 #define E100_WATCHDOG_PERIOD	(2 * HZ)

   212 #define E100_NAPI_WEIGHT	16

   213 

   214 MODULE_DESCRIPTION(DRV_DESCRIPTION);

   215 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   216 MODULE_LICENSE("GPL");

   217 MODULE_VERSION(DRV_VERSION ", master " EC_MASTER_VERSION);

   218 

   219 void e100_ec_poll(struct net_device *);

   220 

   221 static int debug = 3;

   222 static int eeprom_bad_csum_allow = 0;

   223 module_param(debug, int, 0);

   224 module_param(eeprom_bad_csum_allow, int, 0);

   225 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   226 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   227 #define DPRINTK(nlevel, klevel, fmt, args...) \

   228 	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   229 	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   230 		__FUNCTION__ , ## args))

   231 

   232 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   233 	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   234 	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   235 static struct pci_device_id e100_id_table[] = {

   236 	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   237 	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   238 	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   239 	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   240 	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   241 	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   242 	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   243 	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   244 	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   245 	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   246 	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   247 	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   248 	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   249 	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   250 	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   251 	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   252 	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   253 	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   254 	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   255 	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   256 	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   257 	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   258 	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   259 	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   260 	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   261 	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   262 	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   263 	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   264 	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   265 	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   266 	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   267 	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   268 	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   269 	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   270 	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   271 	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   272 	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   273 	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   274 	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   275 	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   276 	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   277 	{ 0, }

   278 };

   279 // prevent from being loaded automatically

   280 //MODULE_DEVICE_TABLE(pci, e100_id_table);

   281 

   282 enum mac {

   283 	mac_82557_D100_A  = 0,

   284 	mac_82557_D100_B  = 1,

   285 	mac_82557_D100_C  = 2,

   286 	mac_82558_D101_A4 = 4,

   287 	mac_82558_D101_B0 = 5,

   288 	mac_82559_D101M   = 8,

   289 	mac_82559_D101S   = 9,

   290 	mac_82550_D102    = 12,

   291 	mac_82550_D102_C  = 13,

   292 	mac_82551_E       = 14,

   293 	mac_82551_F       = 15,

   294 	mac_82551_10      = 16,

   295 	mac_unknown       = 0xFF,

   296 };

   297 

   298 enum phy {

   299 	phy_100a     = 0x000003E0,

   300 	phy_100c     = 0x035002A8,

   301 	phy_82555_tx = 0x015002A8,

   302 	phy_nsc_tx   = 0x5C002000,

   303 	phy_82562_et = 0x033002A8,

   304 	phy_82562_em = 0x032002A8,

   305 	phy_82562_ek = 0x031002A8,

   306 	phy_82562_eh = 0x017002A8,

   307 	phy_unknown  = 0xFFFFFFFF,

   308 };

   309 

   310 /* CSR (Control/Status Registers) */

   311 struct csr {

   312 	struct {

   313 		u8 status;

   314 		u8 stat_ack;

   315 		u8 cmd_lo;

   316 		u8 cmd_hi;

   317 		u32 gen_ptr;

   318 	} scb;

   319 	u32 port;

   320 	u16 flash_ctrl;

   321 	u8 eeprom_ctrl_lo;

   322 	u8 eeprom_ctrl_hi;

   323 	u32 mdi_ctrl;

   324 	u32 rx_dma_count;

   325 };

   326 

   327 enum scb_status {

   328 	rus_ready        = 0x10,

   329 	rus_mask         = 0x3C,

   330 };

   331 

   332 enum ru_state  {

   333 	RU_SUSPENDED = 0,

   334 	RU_RUNNING	 = 1,

   335 	RU_UNINITIALIZED = -1,

   336 };

   337 

   338 enum scb_stat_ack {

   339 	stat_ack_not_ours    = 0x00,

   340 	stat_ack_sw_gen      = 0x04,

   341 	stat_ack_rnr         = 0x10,

   342 	stat_ack_cu_idle     = 0x20,

   343 	stat_ack_frame_rx    = 0x40,

   344 	stat_ack_cu_cmd_done = 0x80,

   345 	stat_ack_not_present = 0xFF,

   346 	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   347 	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   348 };

   349 

   350 enum scb_cmd_hi {

   351 	irq_mask_none = 0x00,

   352 	irq_mask_all  = 0x01,

   353 	irq_sw_gen    = 0x02,

   354 };

   355 

   356 enum scb_cmd_lo {

   357 	cuc_nop        = 0x00,

   358 	ruc_start      = 0x01,

   359 	ruc_load_base  = 0x06,

   360 	cuc_start      = 0x10,

   361 	cuc_resume     = 0x20,

   362 	cuc_dump_addr  = 0x40,

   363 	cuc_dump_stats = 0x50,

   364 	cuc_load_base  = 0x60,

   365 	cuc_dump_reset = 0x70,

   366 };

   367 

   368 enum cuc_dump {

   369 	cuc_dump_complete       = 0x0000A005,

   370 	cuc_dump_reset_complete = 0x0000A007,

   371 };

   372 

   373 enum port {

   374 	software_reset  = 0x0000,

   375 	selftest        = 0x0001,

   376 	selective_reset = 0x0002,

   377 };

   378 

   379 enum eeprom_ctrl_lo {

   380 	eesk = 0x01,

   381 	eecs = 0x02,

   382 	eedi = 0x04,

   383 	eedo = 0x08,

   384 };

   385 

   386 enum mdi_ctrl {

   387 	mdi_write = 0x04000000,

   388 	mdi_read  = 0x08000000,

   389 	mdi_ready = 0x10000000,

   390 };

   391 

   392 enum eeprom_op {

   393 	op_write = 0x05,

   394 	op_read  = 0x06,

   395 	op_ewds  = 0x10,

   396 	op_ewen  = 0x13,

   397 };

   398 

   399 enum eeprom_offsets {

   400 	eeprom_cnfg_mdix  = 0x03,

   401 	eeprom_id         = 0x0A,

   402 	eeprom_config_asf = 0x0D,

   403 	eeprom_smbus_addr = 0x90,

   404 };

   405 

   406 enum eeprom_cnfg_mdix {

   407 	eeprom_mdix_enabled = 0x0080,

   408 };

   409 

   410 enum eeprom_id {

   411 	eeprom_id_wol = 0x0020,

   412 };

   413 

   414 enum eeprom_config_asf {

   415 	eeprom_asf = 0x8000,

   416 	eeprom_gcl = 0x4000,

   417 };

   418 

   419 enum cb_status {

   420 	cb_complete = 0x8000,

   421 	cb_ok       = 0x2000,

   422 };

   423 

   424 enum cb_command {

   425 	cb_nop    = 0x0000,

   426 	cb_iaaddr = 0x0001,

   427 	cb_config = 0x0002,

   428 	cb_multi  = 0x0003,

   429 	cb_tx     = 0x0004,

   430 	cb_ucode  = 0x0005,

   431 	cb_dump   = 0x0006,

   432 	cb_tx_sf  = 0x0008,

   433 	cb_cid    = 0x1f00,

   434 	cb_i      = 0x2000,

   435 	cb_s      = 0x4000,

   436 	cb_el     = 0x8000,

   437 };

   438 

   439 struct rfd {

   440 	u16 status;

   441 	u16 command;

   442 	u32 link;

   443 	u32 rbd;

   444 	u16 actual_size;

   445 	u16 size;

   446 };

   447 

   448 struct rx {

   449 	struct rx *next, *prev;

   450 	struct sk_buff *skb;

   451 	dma_addr_t dma_addr;

   452 };

   453 

   454 #if defined(__BIG_ENDIAN_BITFIELD)

   455 #define X(a,b)	b,a

   456 #else

   457 #define X(a,b)	a,b

   458 #endif

   459 struct config {

   460 /*0*/	u8 X(byte_count:6, pad0:2);

   461 /*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   462 /*2*/	u8 adaptive_ifs;

   463 /*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   464 	   term_write_cache_line:1), pad3:4);

   465 /*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   466 /*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   467 /*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   468 	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   469 	   rx_discard_overruns:1), rx_save_bad_frames:1);

   470 /*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   471 	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   472 	   tx_dynamic_tbd:1);

   473 /*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   474 /*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   475 	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   476 /*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   477 	   loopback:2);

   478 /*11*/	u8 X(linear_priority:3, pad11:5);

   479 /*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   480 /*13*/	u8 ip_addr_lo;

   481 /*14*/	u8 ip_addr_hi;

   482 /*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   483 	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   484 	   pad15_2:1), crs_or_cdt:1);

   485 /*16*/	u8 fc_delay_lo;

   486 /*17*/	u8 fc_delay_hi;

   487 /*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   488 	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   489 /*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   490 	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   491 	   full_duplex_force:1), full_duplex_pin:1);

   492 /*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   493 /*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   494 /*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   495 	u8 pad_d102[9];

   496 };

   497 

   498 #define E100_MAX_MULTICAST_ADDRS	64

   499 struct multi {

   500 	u16 count;

   501 	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   502 };

   503 

   504 /* Important: keep total struct u32-aligned */

   505 #define UCODE_SIZE			134

   506 struct cb {

   507 	u16 status;

   508 	u16 command;

   509 	u32 link;

   510 	union {

   511 		u8 iaaddr[ETH_ALEN];

   512 		u32 ucode[UCODE_SIZE];

   513 		struct config config;

   514 		struct multi multi;

   515 		struct {

   516 			u32 tbd_array;

   517 			u16 tcb_byte_count;

   518 			u8 threshold;

   519 			u8 tbd_count;

   520 			struct {

   521 				u32 buf_addr;

   522 				u16 size;

   523 				u16 eol;

   524 			} tbd;

   525 		} tcb;

   526 		u32 dump_buffer_addr;

   527 	} u;

   528 	struct cb *next, *prev;

   529 	dma_addr_t dma_addr;

   530 	struct sk_buff *skb;

   531 };

   532 

   533 enum loopback {

   534 	lb_none = 0, lb_mac = 1, lb_phy = 3,

   535 };

   536 

   537 struct stats {

   538 	u32 tx_good_frames, tx_max_collisions, tx_late_collisions,

   539 		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,

   540 		tx_multiple_collisions, tx_total_collisions;

   541 	u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,

   542 		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,

   543 		rx_short_frame_errors;

   544 	u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;

   545 	u16 xmt_tco_frames, rcv_tco_frames;

   546 	u32 complete;

   547 };

   548 

   549 struct mem {

   550 	struct {

   551 		u32 signature;

   552 		u32 result;

   553 	} selftest;

   554 	struct stats stats;

   555 	u8 dump_buf[596];

   556 };

   557 

   558 struct param_range {

   559 	u32 min;

   560 	u32 max;

   561 	u32 count;

   562 };

   563 

   564 struct params {

   565 	struct param_range rfds;

   566 	struct param_range cbs;

   567 };

   568 

   569 struct nic {

   570 	/* Begin: frequently used values: keep adjacent for cache effect */

   571 	u32 msg_enable				____cacheline_aligned;

   572 	struct net_device *netdev;

   573 	struct pci_dev *pdev;

   574 

   575 	struct rx *rxs				____cacheline_aligned;

   576 	struct rx *rx_to_use;

   577 	struct rx *rx_to_clean;

   578 	struct rfd blank_rfd;

   579 	enum ru_state ru_running;

   580 

   581 	spinlock_t cb_lock			____cacheline_aligned;

   582 	spinlock_t cmd_lock;

   583 	struct csr __iomem *csr;

   584 	enum scb_cmd_lo cuc_cmd;

   585 	unsigned int cbs_avail;

   586 	struct cb *cbs;

   587 	struct cb *cb_to_use;

   588 	struct cb *cb_to_send;

   589 	struct cb *cb_to_clean;

   590 	u16 tx_command;

   591 	/* End: frequently used values: keep adjacent for cache effect */

   592 

   593 	enum {

   594 		ich                = (1 << 0),

   595 		promiscuous        = (1 << 1),

   596 		multicast_all      = (1 << 2),

   597 		wol_magic          = (1 << 3),

   598 		ich_10h_workaround = (1 << 4),

   599 	} flags					____cacheline_aligned;

   600 

   601 	enum mac mac;

   602 	enum phy phy;

   603 	struct params params;

   604 	struct net_device_stats net_stats;

   605 	struct timer_list watchdog;

   606 	struct timer_list blink_timer;

   607 	struct mii_if_info mii;

   608 	struct work_struct tx_timeout_task;

   609 	enum loopback loopback;

   610 

   611 	struct mem *mem;

   612 	dma_addr_t dma_addr;

   613 

   614 	dma_addr_t cbs_dma_addr;

   615 	u8 adaptive_ifs;

   616 	u8 tx_threshold;

   617 	u32 tx_frames;

   618 	u32 tx_collisions;

   619 	u32 tx_deferred;

   620 	u32 tx_single_collisions;

   621 	u32 tx_multiple_collisions;

   622 	u32 tx_fc_pause;

   623 	u32 tx_tco_frames;

   624 

   625 	u32 rx_fc_pause;

   626 	u32 rx_fc_unsupported;

   627 	u32 rx_tco_frames;

   628 	u32 rx_over_length_errors;

   629 

   630 	u8 rev_id;

   631 	u16 leds;

   632 	u16 eeprom_wc;

   633 	u16 eeprom[256];

   634 	spinlock_t mdio_lock;

   635 

   636     ec_device_t *ecdev;

   637     unsigned long ec_watchdog_jiffies;

   638 };

   639 

   640 static inline void e100_write_flush(struct nic *nic)

   641 {

   642 	/* Flush previous PCI writes through intermediate bridges

   643 	 * by doing a benign read */

   644 	(void)readb(&nic->csr->scb.status);

   645 }

   646 

   647 static void e100_enable_irq(struct nic *nic)

   648 {

   649 	unsigned long flags;

   650 

   651     if (nic->ecdev)

   652         return;

   653 

   654 	spin_lock_irqsave(&nic->cmd_lock, flags);

   655 	writeb(irq_mask_none, &nic->csr->scb.cmd_hi);

   656 	e100_write_flush(nic);

   657 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   658 }

   659 

   660 static void e100_disable_irq(struct nic *nic)

   661 {

   662 	unsigned long flags;

   663 

   664     if (nic->ecdev)

   665         return;

   666 

   667 	spin_lock_irqsave(&nic->cmd_lock, flags);

   668 	writeb(irq_mask_all, &nic->csr->scb.cmd_hi);

   669 	e100_write_flush(nic);

   670 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   671 }

   672 

   673 static void e100_hw_reset(struct nic *nic)

   674 {

   675 	/* Put CU and RU into idle with a selective reset to get

   676 	 * device off of PCI bus */

   677 	writel(selective_reset, &nic->csr->port);

   678 	e100_write_flush(nic); udelay(20);

   679 

   680 	/* Now fully reset device */

   681 	writel(software_reset, &nic->csr->port);

   682 	e100_write_flush(nic); udelay(20);

   683 

   684 	/* Mask off our interrupt line - it's unmasked after reset */

   685 	e100_disable_irq(nic);

   686 }

   687 

   688 static int e100_self_test(struct nic *nic)

   689 {

   690 	u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);

   691 

   692 	/* Passing the self-test is a pretty good indication

   693 	 * that the device can DMA to/from host memory */

   694 

   695 	nic->mem->selftest.signature = 0;

   696 	nic->mem->selftest.result = 0xFFFFFFFF;

   697 

   698 	writel(selftest | dma_addr, &nic->csr->port);

   699 	e100_write_flush(nic);

   700 	/* Wait 10 msec for self-test to complete */

   701 	msleep(10);

   702 

   703 	/* Interrupts are enabled after self-test */

   704 	e100_disable_irq(nic);

   705 

   706 	/* Check results of self-test */

   707 	if(nic->mem->selftest.result != 0) {

   708 		DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",

   709 			nic->mem->selftest.result);

   710 		return -ETIMEDOUT;

   711 	}

   712 	if(nic->mem->selftest.signature == 0) {

   713 		DPRINTK(HW, ERR, "Self-test failed: timed out\n");

   714 		return -ETIMEDOUT;

   715 	}

   716 

   717 	return 0;

   718 }

   719 

   720 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)

   721 {

   722 	u32 cmd_addr_data[3];

   723 	u8 ctrl;

   724 	int i, j;

   725 

   726 	/* Three cmds: write/erase enable, write data, write/erase disable */

   727 	cmd_addr_data[0] = op_ewen << (addr_len - 2);

   728 	cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |

   729 		cpu_to_le16(data);

   730 	cmd_addr_data[2] = op_ewds << (addr_len - 2);

   731 

   732 	/* Bit-bang cmds to write word to eeprom */

   733 	for(j = 0; j < 3; j++) {

   734 

   735 		/* Chip select */

   736 		writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   737 		e100_write_flush(nic); udelay(4);

   738 

   739 		for(i = 31; i >= 0; i--) {

   740 			ctrl = (cmd_addr_data[j] & (1 << i)) ?

   741 				eecs | eedi : eecs;

   742 			writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   743 			e100_write_flush(nic); udelay(4);

   744 

   745 			writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   746 			e100_write_flush(nic); udelay(4);

   747 		}

   748 		/* Wait 10 msec for cmd to complete */

   749 		msleep(10);

   750 

   751 		/* Chip deselect */

   752 		writeb(0, &nic->csr->eeprom_ctrl_lo);

   753 		e100_write_flush(nic); udelay(4);

   754 	}

   755 };

   756 

   757 /* General technique stolen from the eepro100 driver - very clever */

   758 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)

   759 {

   760 	u32 cmd_addr_data;

   761 	u16 data = 0;

   762 	u8 ctrl;

   763 	int i;

   764 

   765 	cmd_addr_data = ((op_read << *addr_len) | addr) << 16;

   766 

   767 	/* Chip select */

   768 	writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   769 	e100_write_flush(nic); udelay(4);

   770 

   771 	/* Bit-bang to read word from eeprom */

   772 	for(i = 31; i >= 0; i--) {

   773 		ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;

   774 		writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   775 		e100_write_flush(nic); udelay(4);

   776 

   777 		writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   778 		e100_write_flush(nic); udelay(4);

   779 

   780 		/* Eeprom drives a dummy zero to EEDO after receiving

   781 		 * complete address.  Use this to adjust addr_len. */

   782 		ctrl = readb(&nic->csr->eeprom_ctrl_lo);

   783 		if(!(ctrl & eedo) && i > 16) {

   784 			*addr_len -= (i - 16);

   785 			i = 17;

   786 		}

   787 

   788 		data = (data << 1) | (ctrl & eedo ? 1 : 0);

   789 	}

   790 

   791 	/* Chip deselect */

   792 	writeb(0, &nic->csr->eeprom_ctrl_lo);

   793 	e100_write_flush(nic); udelay(4);

   794 

   795 	return le16_to_cpu(data);

   796 };

   797 

   798 /* Load entire EEPROM image into driver cache and validate checksum */

   799 static int e100_eeprom_load(struct nic *nic)

   800 {

   801 	u16 addr, addr_len = 8, checksum = 0;

   802 

   803 	/* Try reading with an 8-bit addr len to discover actual addr len */

   804 	e100_eeprom_read(nic, &addr_len, 0);

   805 	nic->eeprom_wc = 1 << addr_len;

   806 

   807 	for(addr = 0; addr < nic->eeprom_wc; addr++) {

   808 		nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);

   809 		if(addr < nic->eeprom_wc - 1)

   810 			checksum += cpu_to_le16(nic->eeprom[addr]);

   811 	}

   812 

   813 	/* The checksum, stored in the last word, is calculated such that

   814 	 * the sum of words should be 0xBABA */

   815 	checksum = le16_to_cpu(0xBABA - checksum);

   816 	if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {

   817 		DPRINTK(PROBE, ERR, "EEPROM corrupted\n");

   818 		if (!eeprom_bad_csum_allow)

   819 			return -EAGAIN;

   820 	}

   821 

   822 	return 0;

   823 }

   824 

   825 /* Save (portion of) driver EEPROM cache to device and update checksum */

   826 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)

   827 {

   828 	u16 addr, addr_len = 8, checksum = 0;

   829 

   830 	/* Try reading with an 8-bit addr len to discover actual addr len */

   831 	e100_eeprom_read(nic, &addr_len, 0);

   832 	nic->eeprom_wc = 1 << addr_len;

   833 

   834 	if(start + count >= nic->eeprom_wc)

   835 		return -EINVAL;

   836 

   837 	for(addr = start; addr < start + count; addr++)

   838 		e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);

   839 

   840 	/* The checksum, stored in the last word, is calculated such that

   841 	 * the sum of words should be 0xBABA */

   842 	for(addr = 0; addr < nic->eeprom_wc - 1; addr++)

   843 		checksum += cpu_to_le16(nic->eeprom[addr]);

   844 	nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);

   845 	e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,

   846 		nic->eeprom[nic->eeprom_wc - 1]);

   847 

   848 	return 0;

   849 }

   850 

   851 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */

   852 #define E100_WAIT_SCB_FAST 20       /* delay like the old code */

   853 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)

   854 {

   855 	unsigned long flags = 0;

   856 	unsigned int i;

   857 	int err = 0;

   858 

   859 	if (!nic->ecdev)

   860 		spin_lock_irqsave(&nic->cmd_lock, flags);

   861 

   862 	/* Previous command is accepted when SCB clears */

   863 	for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {

   864 		if(likely(!readb(&nic->csr->scb.cmd_lo)))

   865 			break;

   866 		cpu_relax();

   867 		if(unlikely(i > E100_WAIT_SCB_FAST))

   868 			udelay(5);

   869 	}

   870 	if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {

   871 		err = -EAGAIN;

   872 		goto err_unlock;

   873 	}

   874 

   875 	if(unlikely(cmd != cuc_resume))

   876 		writel(dma_addr, &nic->csr->scb.gen_ptr);

   877 	writeb(cmd, &nic->csr->scb.cmd_lo);

   878 

   879 err_unlock:

   880 	if (!nic->ecdev)

   881 		spin_unlock_irqrestore(&nic->cmd_lock, flags);

   882 

   883 	return err;

   884 }

   885 

   886 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,

   887 	void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))

   888 {

   889 	struct cb *cb;

   890 	unsigned long flags = 0;

   891 	int err = 0;

   892 

   893 	if (!nic->ecdev)

   894 		spin_lock_irqsave(&nic->cb_lock, flags);

   895 

   896 	if(unlikely(!nic->cbs_avail)) {

   897 		err = -ENOMEM;

   898 		goto err_unlock;

   899 	}

   900 

   901 	cb = nic->cb_to_use;

   902 	nic->cb_to_use = cb->next;

   903 	nic->cbs_avail--;

   904 	cb->skb = skb;

   905 

   906 	if(unlikely(!nic->cbs_avail))

   907 		err = -ENOSPC;

   908 

   909 	cb_prepare(nic, cb, skb);

   910 

   911 	/* Order is important otherwise we'll be in a race with h/w:

   912 	 * set S-bit in current first, then clear S-bit in previous. */

   913 	cb->command |= cpu_to_le16(cb_s);

   914 	wmb();

   915 	cb->prev->command &= cpu_to_le16(~cb_s);

   916 

   917 	while(nic->cb_to_send != nic->cb_to_use) {

   918 		if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,

   919 			nic->cb_to_send->dma_addr))) {

   920 			/* Ok, here's where things get sticky.  It's

   921 			 * possible that we can't schedule the command

   922 			 * because the controller is too busy, so

   923 			 * let's just queue the command and try again

   924 			 * when another command is scheduled. */

   925 			if(err == -ENOSPC) {

   926 				//request a reset

   927 				schedule_work(&nic->tx_timeout_task);

   928 			}

   929 			break;

   930 		} else {

   931 			nic->cuc_cmd = cuc_resume;

   932 			nic->cb_to_send = nic->cb_to_send->next;

   933 		}

   934 	}

   935 

   936 err_unlock:

   937 	if (!nic->ecdev)

   938 		spin_unlock_irqrestore(&nic->cb_lock, flags);

   939 

   940 	return err;

   941 }

   942 

   943 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)

   944 {

   945 	u32 data_out = 0;

   946 	unsigned int i;

   947 	unsigned long flags = 0;

   948 

   949 

   950 	/*

   951 	 * Stratus87247: we shouldn't be writing the MDI control

   952 	 * register until the Ready bit shows True.  Also, since

   953 	 * manipulation of the MDI control registers is a multi-step

   954 	 * procedure it should be done under lock.

   955 	 */

   956 	if (!nic->ecdev)

   957 		spin_lock_irqsave(&nic->mdio_lock, flags);

   958 	for (i = 100; i; --i) {

   959 		if (readl(&nic->csr->mdi_ctrl) & mdi_ready)

   960 			break;

   961 		udelay(20);

   962 	}

   963 	if (unlikely(!i)) {

   964 		printk("e100.mdio_ctrl(%s) won't go Ready\n",

   965 			nic->netdev->name );

   966 		if (!nic->ecdev)

   967 			spin_unlock_irqrestore(&nic->mdio_lock, flags);

   968 		return 0;		/* No way to indicate timeout error */

   969 	}

   970 	writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

   971 

   972 	for (i = 0; i < 100; i++) {

   973 		udelay(20);

   974 		if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)

   975 			break;

   976 	}

   977 	if (!nic->ecdev)

   978 		spin_unlock_irqrestore(&nic->mdio_lock, flags);

   979 	DPRINTK(HW, DEBUG,

   980 		"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",

   981 		dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);

   982 	return (u16)data_out;

   983 }

   984 

   985 static int mdio_read(struct net_device *netdev, int addr, int reg)

   986 {

   987 	return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);

   988 }

   989 

   990 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)

   991 {

   992 	mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);

   993 }

   994 

   995 static void e100_get_defaults(struct nic *nic)

   996 {

   997 	struct param_range rfds = { .min = 16, .max = 256, .count = 256 };

   998 	struct param_range cbs  = { .min = 64, .max = 256, .count = 128 };

   999 

  1000 	pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);

  1001 	/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */

  1002 	nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;

  1003 	if(nic->mac == mac_unknown)

  1004 		nic->mac = mac_82557_D100_A;

  1005 

  1006 	nic->params.rfds = rfds;

  1007 	nic->params.cbs = cbs;

  1008 

  1009 	/* Quadwords to DMA into FIFO before starting frame transmit */

  1010 	nic->tx_threshold = 0xE0;

  1011 

  1012 	/* no interrupt for every tx completion, delay = 256us if not 557*/

  1013 	nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |

  1014 		((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));

  1015 

  1016 	/* Template for a freshly allocated RFD */

  1017 	nic->blank_rfd.command = cpu_to_le16(cb_el);

  1018 	nic->blank_rfd.rbd = 0xFFFFFFFF;

  1019 	nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);

  1020 

  1021 	/* MII setup */

  1022 	nic->mii.phy_id_mask = 0x1F;

  1023 	nic->mii.reg_num_mask = 0x1F;

  1024 	nic->mii.dev = nic->netdev;

  1025 	nic->mii.mdio_read = mdio_read;

  1026 	nic->mii.mdio_write = mdio_write;

  1027 }

  1028 

  1029 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)

  1030 {

  1031 	struct config *config = &cb->u.config;

  1032 	u8 *c = (u8 *)config;

  1033 

  1034 	cb->command = cpu_to_le16(cb_config);

  1035 

  1036 	memset(config, 0, sizeof(struct config));

  1037 

  1038 	config->byte_count = 0x16;		/* bytes in this struct */

  1039 	config->rx_fifo_limit = 0x8;		/* bytes in FIFO before DMA */

  1040 	config->direct_rx_dma = 0x1;		/* reserved */

  1041 	config->standard_tcb = 0x1;		/* 1=standard, 0=extended */

  1042 	config->standard_stat_counter = 0x1;	/* 1=standard, 0=extended */

  1043 	config->rx_discard_short_frames = 0x1;	/* 1=discard, 0=pass */

  1044 	config->tx_underrun_retry = 0x3;	/* # of underrun retries */

  1045 	config->mii_mode = 0x1;			/* 1=MII mode, 0=503 mode */

  1046 	config->pad10 = 0x6;

  1047 	config->no_source_addr_insertion = 0x1;	/* 1=no, 0=yes */

  1048 	config->preamble_length = 0x2;		/* 0=1, 1=3, 2=7, 3=15 bytes */

  1049 	config->ifs = 0x6;			/* x16 = inter frame spacing */

  1050 	config->ip_addr_hi = 0xF2;		/* ARP IP filter - not used */

  1051 	config->pad15_1 = 0x1;

  1052 	config->pad15_2 = 0x1;

  1053 	config->crs_or_cdt = 0x0;		/* 0=CRS only, 1=CRS or CDT */

  1054 	config->fc_delay_hi = 0x40;		/* time delay for fc frame */

  1055 	config->tx_padding = 0x1;		/* 1=pad short frames */

  1056 	config->fc_priority_threshold = 0x7;	/* 7=priority fc disabled */

  1057 	config->pad18 = 0x1;

  1058 	config->full_duplex_pin = 0x1;		/* 1=examine FDX# pin */

  1059 	config->pad20_1 = 0x1F;

  1060 	config->fc_priority_location = 0x1;	/* 1=byte#31, 0=byte#19 */

  1061 	config->pad21_1 = 0x5;

  1062 

  1063 	config->adaptive_ifs = nic->adaptive_ifs;

  1064 	config->loopback = nic->loopback;

  1065 

  1066 	if(nic->mii.force_media && nic->mii.full_duplex)

  1067 		config->full_duplex_force = 0x1;	/* 1=force, 0=auto */

  1068 

  1069 	if(nic->flags & promiscuous || nic->loopback) {

  1070 		config->rx_save_bad_frames = 0x1;	/* 1=save, 0=discard */

  1071 		config->rx_discard_short_frames = 0x0;	/* 1=discard, 0=save */

  1072 		config->promiscuous_mode = 0x1;		/* 1=on, 0=off */

  1073 	}

  1074 

  1075 	if(nic->flags & multicast_all)

  1076 		config->multicast_all = 0x1;		/* 1=accept, 0=no */

  1077 

  1078 	/* disable WoL when up */

  1079 	if (nic->ecdev ||

  1080             (netif_running(nic->netdev) || !(nic->flags & wol_magic)))

  1081 		config->magic_packet_disable = 0x1;	/* 1=off, 0=on */

  1082 

  1083 	if(nic->mac >= mac_82558_D101_A4) {

  1084 		config->fc_disable = 0x1;	/* 1=Tx fc off, 0=Tx fc on */

  1085 		config->mwi_enable = 0x1;	/* 1=enable, 0=disable */

  1086 		config->standard_tcb = 0x0;	/* 1=standard, 0=extended */

  1087 		config->rx_long_ok = 0x1;	/* 1=VLANs ok, 0=standard */

  1088 		if(nic->mac >= mac_82559_D101M)

  1089 			config->tno_intr = 0x1;		/* TCO stats enable */

  1090 		else

  1091 			config->standard_stat_counter = 0x0;

  1092 	}

  1093 

  1094 	DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1095 		c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);

  1096 	DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1097 		c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);

  1098 	DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1099 		c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);

  1100 }

  1101 

  1102 /********************************************************/

  1103 /*  Micro code for 8086:1229 Rev 8                      */

  1104 /********************************************************/

  1105 

  1106 /*  Parameter values for the D101M B-step  */

  1107 #define D101M_CPUSAVER_TIMER_DWORD		78

  1108 #define D101M_CPUSAVER_BUNDLE_DWORD		65

  1109 #define D101M_CPUSAVER_MIN_SIZE_DWORD		126

  1110 

  1111 #define D101M_B_RCVBUNDLE_UCODE \

  1112 {\

  1113 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \

  1114 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \

  1115 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \

  1116 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \

  1117 0x00380438, 0x00000000, 0x00140000, 0x00380555, \

  1118 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \

  1119 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \

  1120 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \

  1121 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \

  1122 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \

  1123 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1124 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \

  1125 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \

  1126 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \

  1127 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \

  1128 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \

  1129 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \

  1130 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1131 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1132 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \

  1133 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \

  1134 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \

  1135 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \

  1136 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \