master/master.c
branchstable-1.1
changeset 1719 42ed27ae6785
parent 1716 9440f4ff25c7
child 1721 8d1fcfe68ced
equal deleted inserted replaced
1718:048c7310279c 1719:42ed27ae6785
   225     ec_master_clear_slaves(master);
   225     ec_master_clear_slaves(master);
   226 
   226 
   227     // empty datagram queue
   227     // empty datagram queue
   228     list_for_each_entry_safe(datagram, next_c,
   228     list_for_each_entry_safe(datagram, next_c,
   229                              &master->datagram_queue, queue) {
   229                              &master->datagram_queue, queue) {
       
   230         datagram->state = EC_DATAGRAM_ERROR;
   230         list_del_init(&datagram->queue);
   231         list_del_init(&datagram->queue);
   231         datagram->state = EC_DATAGRAM_ERROR;
       
   232     }
   232     }
   233 
   233 
   234     // clear domains
   234     // clear domains
   235     list_for_each_entry_safe(domain, next_d, &master->domains, list) {
   235     list_for_each_entry_safe(domain, next_d, &master->domains, list) {
   236         list_del(&domain->list);
   236         list_del(&domain->list);
   240 
   240 
   241     master->datagram_index = 0;
   241     master->datagram_index = 0;
   242     master->debug_level = 0;
   242     master->debug_level = 0;
   243 
   243 
   244     master->stats.timeouts = 0;
   244     master->stats.timeouts = 0;
   245     master->stats.delayed = 0;
       
   246     master->stats.corrupted = 0;
   245     master->stats.corrupted = 0;
   247     master->stats.skipped = 0;
   246     master->stats.skipped = 0;
   248     master->stats.unmatched = 0;
   247     master->stats.unmatched = 0;
   249     master->stats.t_last = 0;
   248     master->stats.output_jiffies = 0;
   250 
   249 
   251     master->mode = EC_MASTER_MODE_ORPHANED;
   250     master->mode = EC_MASTER_MODE_ORPHANED;
   252 
   251 
   253     master->request_cb = NULL;
   252     master->request_cb = NULL;
   254     master->release_cb = NULL;
   253     master->release_cb = NULL;
   314 {
   313 {
   315     ec_datagram_t *datagram;
   314     ec_datagram_t *datagram;
   316     size_t datagram_size;
   315     size_t datagram_size;
   317     uint8_t *frame_data, *cur_data;
   316     uint8_t *frame_data, *cur_data;
   318     void *follows_word;
   317     void *follows_word;
   319     cycles_t t_start, t_end;
   318     cycles_t cycles_start, cycles_end;
   320     unsigned int frame_count, more_datagrams_waiting;
   319     unsigned int frame_count, more_datagrams_waiting;
   321 
   320 
   322     frame_count = 0;
   321     frame_count = 0;
   323     t_start = get_cycles();
   322     cycles_start = get_cycles();
   324 
   323 
   325     if (unlikely(master->debug_level > 1))
   324     if (unlikely(master->debug_level > 1))
   326         EC_DBG("ec_master_send_datagrams\n");
   325         EC_DBG("ec_master_send_datagrams\n");
   327 
   326 
   328     do {
   327     do {
   343                 more_datagrams_waiting = 1;
   342                 more_datagrams_waiting = 1;
   344                 break;
   343                 break;
   345             }
   344             }
   346 
   345 
   347             datagram->state = EC_DATAGRAM_SENT;
   346             datagram->state = EC_DATAGRAM_SENT;
   348             datagram->t_sent = t_start;
   347             datagram->cycles_sent = cycles_start;
   349             datagram->index = master->datagram_index++;
   348             datagram->index = master->datagram_index++;
   350 
   349 
   351             if (unlikely(master->debug_level > 1))
   350             if (unlikely(master->debug_level > 1))
   352                 EC_DBG("adding datagram 0x%02X\n", datagram->index);
   351                 EC_DBG("adding datagram 0x%02X\n", datagram->index);
   353 
   352 
   395         frame_count++;
   394         frame_count++;
   396     }
   395     }
   397     while (more_datagrams_waiting);
   396     while (more_datagrams_waiting);
   398 
   397 
   399     if (unlikely(master->debug_level > 1)) {
   398     if (unlikely(master->debug_level > 1)) {
   400         t_end = get_cycles();
   399         cycles_end = get_cycles();
   401         EC_DBG("ec_master_send_datagrams sent %i frames in %ius.\n",
   400         EC_DBG("ec_master_send_datagrams sent %i frames in %ius.\n",
   402                frame_count, (unsigned int) (t_end - t_start) * 1000 / cpu_khz);
   401                frame_count,
       
   402                (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz);
   403     }
   403     }
   404 }
   404 }
   405 
   405 
   406 /*****************************************************************************/
   406 /*****************************************************************************/
   407 
   407 
   474             ec_master_output_stats(master);
   474             ec_master_output_stats(master);
   475             cur_data += data_size + EC_DATAGRAM_FOOTER_SIZE;
   475             cur_data += data_size + EC_DATAGRAM_FOOTER_SIZE;
   476             continue;
   476             continue;
   477         }
   477         }
   478 
   478 
   479         // copy received data in the datagram memory
   479         // copy received data into the datagram memory
   480         memcpy(datagram->data, cur_data, data_size);
   480         memcpy(datagram->data, cur_data, data_size);
   481         cur_data += data_size;
   481         cur_data += data_size;
   482 
   482 
   483         // set the datagram's working counter
   483         // set the datagram's working counter
   484         datagram->working_counter = EC_READ_U16(cur_data);
   484         datagram->working_counter = EC_READ_U16(cur_data);
   526    necessary. The output happens at most once a second.
   526    necessary. The output happens at most once a second.
   527 */
   527 */
   528 
   528 
   529 void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */)
   529 void ec_master_output_stats(ec_master_t *master /**< EtherCAT master */)
   530 {
   530 {
   531     cycles_t t_now = get_cycles();
   531     if (unlikely(jiffies - master->stats.output_jiffies >= HZ)) {
   532 
   532         master->stats.output_jiffies = jiffies;
   533     if (unlikely((u32) (t_now - master->stats.t_last) / cpu_khz > 1000)) {
   533 
   534         if (master->stats.timeouts) {
   534         if (master->stats.timeouts) {
   535             EC_WARN("%i datagrams TIMED OUT!\n", master->stats.timeouts);
   535             EC_WARN("%i datagrams TIMED OUT!\n", master->stats.timeouts);
   536             master->stats.timeouts = 0;
   536             master->stats.timeouts = 0;
   537         }
   537         }
   538         if (master->stats.delayed) {
       
   539             EC_WARN("%i frame(s) DELAYED!\n", master->stats.delayed);
       
   540             master->stats.delayed = 0;
       
   541         }
       
   542         if (master->stats.corrupted) {
   538         if (master->stats.corrupted) {
   543             EC_WARN("%i frame(s) CORRUPTED!\n", master->stats.corrupted);
   539             EC_WARN("%i frame(s) CORRUPTED!\n", master->stats.corrupted);
   544             master->stats.corrupted = 0;
   540             master->stats.corrupted = 0;
   545         }
   541         }
   546         if (master->stats.skipped) {
   542         if (master->stats.skipped) {
   549         }
   545         }
   550         if (master->stats.unmatched) {
   546         if (master->stats.unmatched) {
   551             EC_WARN("%i datagram(s) UNMATCHED!\n", master->stats.unmatched);
   547             EC_WARN("%i datagram(s) UNMATCHED!\n", master->stats.unmatched);
   552             master->stats.unmatched = 0;
   548             master->stats.unmatched = 0;
   553         }
   549         }
   554         master->stats.t_last = t_now;
       
   555     }
   550     }
   556 }
   551 }
   557 
   552 
   558 /*****************************************************************************/
   553 /*****************************************************************************/
   559 
   554 
   608 */
   603 */
   609 
   604 
   610 void ec_master_idle_run(void *data /**< master pointer */)
   605 void ec_master_idle_run(void *data /**< master pointer */)
   611 {
   606 {
   612     ec_master_t *master = (ec_master_t *) data;
   607     ec_master_t *master = (ec_master_t *) data;
   613     cycles_t start, end;
   608     cycles_t cycles_start, cycles_end;
   614 
   609 
   615     // aquire master lock
   610     // aquire master lock
   616     spin_lock_bh(&master->internal_lock);
   611     spin_lock_bh(&master->internal_lock);
   617 
   612 
   618     start = get_cycles();
   613     cycles_start = get_cycles();
   619     ecrt_master_receive(master);
   614     ecrt_master_receive(master);
   620 
   615 
   621     // execute master state machine
   616     // execute master state machine
   622     ec_fsm_execute(&master->fsm);
   617     ec_fsm_execute(&master->fsm);
   623 
   618 
   624     ecrt_master_send(master);
   619     ecrt_master_send(master);
   625     end = get_cycles();
   620     cycles_end = get_cycles();
   626 
   621 
   627     // release master lock
   622     // release master lock
   628     spin_unlock_bh(&master->internal_lock);
   623     spin_unlock_bh(&master->internal_lock);
   629 
   624 
   630     master->idle_cycle_times[master->idle_cycle_time_pos]
   625     master->idle_cycle_times[master->idle_cycle_time_pos]
   631         = (u32) (end - start) * 1000 / cpu_khz;
   626         = (u32) (cycles_end - cycles_start) * 1000 / cpu_khz;
   632     master->idle_cycle_time_pos++;
   627     master->idle_cycle_time_pos++;
   633     master->idle_cycle_time_pos %= HZ;
   628     master->idle_cycle_time_pos %= HZ;
   634 
   629 
   635     if (master->mode == EC_MASTER_MODE_IDLE)
   630     if (master->mode == EC_MASTER_MODE_IDLE)
   636         queue_delayed_work(master->workqueue, &master->idle_work, 1);
   631         queue_delayed_work(master->workqueue, &master->idle_work, 1);
   956 void ec_master_eoe_run(unsigned long data /**< master pointer */)
   951 void ec_master_eoe_run(unsigned long data /**< master pointer */)
   957 {
   952 {
   958     ec_master_t *master = (ec_master_t *) data;
   953     ec_master_t *master = (ec_master_t *) data;
   959     ec_eoe_t *eoe;
   954     ec_eoe_t *eoe;
   960     unsigned int active = 0;
   955     unsigned int active = 0;
   961     cycles_t start, end;
   956     cycles_t cycles_start, cycles_end;
       
   957     unsigned long restart_jiffies;
   962 
   958 
   963     list_for_each_entry(eoe, &master->eoe_handlers, list) {
   959     list_for_each_entry(eoe, &master->eoe_handlers, list) {
   964         if (ec_eoe_active(eoe)) active++;
   960         if (ec_eoe_active(eoe)) active++;
   965     }
   961     }
   966     if (!active) goto queue_timer;
   962     if (!active) goto queue_timer;
   975         spin_lock(&master->internal_lock);
   971         spin_lock(&master->internal_lock);
   976     }
   972     }
   977     else
   973     else
   978         goto queue_timer;
   974         goto queue_timer;
   979 
   975 
   980     // actual EoE stuff
   976     // actual EoE processing
   981     start = get_cycles();
   977     cycles_start = get_cycles();
   982     ecrt_master_receive(master);
   978     ecrt_master_receive(master);
   983 
   979 
   984     list_for_each_entry(eoe, &master->eoe_handlers, list) {
   980     list_for_each_entry(eoe, &master->eoe_handlers, list) {
   985         ec_eoe_run(eoe);
   981         ec_eoe_run(eoe);
   986     }
   982     }
   987 
   983 
   988     ecrt_master_send(master);
   984     ecrt_master_send(master);
   989     end = get_cycles();
   985     cycles_end = get_cycles();
   990 
   986 
   991     // release lock...
   987     // release lock...
   992     if (master->mode == EC_MASTER_MODE_OPERATION) {
   988     if (master->mode == EC_MASTER_MODE_OPERATION) {
   993         master->release_cb(master->cb_data);
   989         master->release_cb(master->cb_data);
   994     }
   990     }
   995     else if (master->mode == EC_MASTER_MODE_IDLE) {
   991     else if (master->mode == EC_MASTER_MODE_IDLE) {
   996         spin_unlock(&master->internal_lock);
   992         spin_unlock(&master->internal_lock);
   997     }
   993     }
   998 
   994 
   999     master->eoe_cycle_times[master->eoe_cycle_time_pos]
   995     master->eoe_cycle_times[master->eoe_cycle_time_pos]
  1000         = (u32) (end - start) * 1000 / cpu_khz;
   996         = (u32) (cycles_end - cycles_start) * 1000 / cpu_khz;
  1001     master->eoe_cycle_time_pos++;
   997     master->eoe_cycle_time_pos++;
  1002     master->eoe_cycle_time_pos %= HZ;
   998     master->eoe_cycle_time_pos %= HZ;
  1003 
   999 
  1004  queue_timer:
  1000  queue_timer:
  1005     master->eoe_timer.expires += HZ / EC_EOE_FREQUENCY;
  1001     restart_jiffies = HZ / EC_EOE_FREQUENCY;
       
  1002     if (!restart_jiffies) restart_jiffies = 1;
       
  1003     master->eoe_timer.expires += restart_jiffies;
  1006     add_timer(&master->eoe_timer);
  1004     add_timer(&master->eoe_timer);
  1007 }
  1005 }
  1008 
  1006 
  1009 /*****************************************************************************/
  1007 /*****************************************************************************/
  1010 
  1008 
  1045 */
  1043 */
  1046 
  1044 
  1047 void ec_master_measure_bus_time(ec_master_t *master)
  1045 void ec_master_measure_bus_time(ec_master_t *master)
  1048 {
  1046 {
  1049     ec_datagram_t datagram;
  1047     ec_datagram_t datagram;
  1050     cycles_t t_start, t_end, t_timeout;
  1048     cycles_t cycles_start, cycles_end, cycles_timeout;
  1051     uint32_t times[100], sum, min, max, i;
  1049     uint32_t times[100], sum, min, max, i;
  1052 
  1050 
  1053     ec_datagram_init(&datagram);
  1051     ec_datagram_init(&datagram);
  1054 
  1052 
  1055     if (ec_datagram_brd(&datagram, 0x130, 2)) {
  1053     if (ec_datagram_brd(&datagram, 0x130, 2)) {
  1056         EC_ERR("Failed to allocate datagram for bus time measuring.\n");
  1054         EC_ERR("Failed to allocate datagram for bus time measuring.\n");
  1057         ec_datagram_clear(&datagram);
  1055         ec_datagram_clear(&datagram);
  1058         return;
  1056         return;
  1059     }
  1057     }
  1060 
  1058 
  1061     t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000);
  1059     cycles_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000);
  1062 
  1060 
  1063     sum = 0;
  1061     sum = 0;
  1064     min = 0xFFFFFFFF;
  1062     min = 0xFFFFFFFF;
  1065     max = 0;
  1063     max = 0;
  1066 
  1064 
  1067     for (i = 0; i < 100; i++) {
  1065     for (i = 0; i < 100; i++) {
  1068         ec_master_queue_datagram(master, &datagram);
  1066         ec_master_queue_datagram(master, &datagram);
  1069         ecrt_master_send(master);
  1067         ecrt_master_send(master);
  1070         t_start = get_cycles();
  1068         cycles_start = get_cycles();
  1071 
  1069 
  1072         while (1) { // active waiting
  1070         while (1) { // active waiting
  1073             ec_device_call_isr(master->device);
  1071             ec_device_call_isr(master->device);
  1074             t_end = get_cycles(); // take current time
  1072             cycles_end = get_cycles(); // take current time
  1075 
  1073 
  1076             if (datagram.state == EC_DATAGRAM_RECEIVED) {
  1074             if (datagram.state == EC_DATAGRAM_RECEIVED) {
  1077                 break;
  1075                 break;
  1078             }
  1076             }
  1079             else if (datagram.state == EC_DATAGRAM_ERROR) {
  1077             else if (datagram.state == EC_DATAGRAM_ERROR) {
  1080                 EC_WARN("Failed to measure bus time.\n");
  1078                 EC_WARN("Failed to measure bus time.\n");
  1081                 goto error;
  1079                 goto error;
  1082             }
  1080             }
  1083             else if (t_end - t_start >= t_timeout) {
  1081             else if (cycles_end - cycles_start >= cycles_timeout) {
  1084                 EC_WARN("Timeout while measuring bus time.\n");
  1082                 EC_WARN("Timeout while measuring bus time.\n");
  1085                 goto error;
  1083                 goto error;
  1086             }
  1084             }
  1087         }
  1085         }
  1088 
  1086 
  1089         times[i] = (unsigned int) (t_end - t_start) * 1000 / cpu_khz;
  1087         times[i] = (unsigned int) (cycles_end - cycles_start) * 1000 / cpu_khz;
  1090         sum += times[i];
  1088         sum += times[i];
  1091         if (times[i] > max) max = times[i];
  1089         if (times[i] > max) max = times[i];
  1092         if (times[i] < min) min = times[i];
  1090         if (times[i] < min) min = times[i];
  1093     }
  1091     }
  1094 
  1092 
  1232    Sends queued datagrams and waits for their reception.
  1230    Sends queued datagrams and waits for their reception.
  1233 */
  1231 */
  1234 
  1232 
  1235 void ec_master_sync_io(ec_master_t *master /**< EtherCAT master */)
  1233 void ec_master_sync_io(ec_master_t *master /**< EtherCAT master */)
  1236 {
  1234 {
  1237     ec_datagram_t *datagram, *n;
  1235     ec_datagram_t *datagram;
  1238     unsigned int datagrams_sent;
  1236     unsigned int datagrams_waiting;
  1239     cycles_t t_start, t_end, t_timeout;
       
  1240 
  1237 
  1241     // send datagrams
  1238     // send datagrams
  1242     ecrt_master_send(master);
  1239     ecrt_master_send(master);
  1243 
  1240 
  1244     t_start = get_cycles(); // measure io time
       
  1245     t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000);
       
  1246 
       
  1247     while (1) { // active waiting
  1241     while (1) { // active waiting
  1248         ec_device_call_isr(master->device);
  1242         ecrt_master_receive(master); // receive and dequeue datagrams
  1249 
  1243 
  1250         t_end = get_cycles(); // take current time
  1244         // count number of datagrams still waiting for response
  1251         if (t_end - t_start >= t_timeout) break; // timeout!
  1245         datagrams_waiting = 0;
  1252 
  1246         list_for_each_entry(datagram, &master->datagram_queue, queue) {
  1253         datagrams_sent = 0;
  1247             datagrams_waiting++;
  1254         list_for_each_entry_safe(datagram, n, &master->datagram_queue, queue) {
  1248         }
  1255             if (datagram->state == EC_DATAGRAM_RECEIVED)
  1249 
  1256                 list_del_init(&datagram->queue);
  1250         // if there are no more datagrams waiting, abort loop.
  1257             else if (datagram->state == EC_DATAGRAM_SENT)
  1251         if (!datagrams_waiting) break;
  1258                 datagrams_sent++;
       
  1259         }
       
  1260 
       
  1261         if (!datagrams_sent) break;
       
  1262     }
       
  1263 
       
  1264     // timeout; dequeue all datagrams
       
  1265     list_for_each_entry_safe(datagram, n, &master->datagram_queue, queue) {
       
  1266         switch (datagram->state) {
       
  1267             case EC_DATAGRAM_SENT:
       
  1268             case EC_DATAGRAM_QUEUED:
       
  1269                 datagram->state = EC_DATAGRAM_TIMED_OUT;
       
  1270                 master->stats.timeouts++;
       
  1271                 ec_master_output_stats(master);
       
  1272                 break;
       
  1273             case EC_DATAGRAM_RECEIVED:
       
  1274                 master->stats.delayed++;
       
  1275                 ec_master_output_stats(master);
       
  1276                 break;
       
  1277             default:
       
  1278                 break;
       
  1279         }
       
  1280         list_del_init(&datagram->queue);
       
  1281     }
  1252     }
  1282 }
  1253 }
  1283 
  1254 
  1284 /*****************************************************************************/
  1255 /*****************************************************************************/
  1285 
  1256 
  1316 */
  1287 */
  1317 
  1288 
  1318 void ecrt_master_receive(ec_master_t *master /**< EtherCAT master */)
  1289 void ecrt_master_receive(ec_master_t *master /**< EtherCAT master */)
  1319 {
  1290 {
  1320     ec_datagram_t *datagram, *next;
  1291     ec_datagram_t *datagram, *next;
  1321     cycles_t t_received, t_timeout;
  1292     cycles_t cycles_received, cycles_timeout;
  1322 
  1293 
  1323     ec_device_call_isr(master->device);
  1294     ec_device_call_isr(master->device);
  1324 
  1295 
  1325     t_received = get_cycles();
  1296     cycles_received = get_cycles();
  1326     t_timeout = EC_IO_TIMEOUT * cpu_khz / 1000;
  1297     cycles_timeout = EC_IO_TIMEOUT * cpu_khz / 1000;
  1327 
       
  1328     // dequeue all received datagrams
       
  1329     list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue)
       
  1330         if (datagram->state == EC_DATAGRAM_RECEIVED)
       
  1331             list_del_init(&datagram->queue);
       
  1332 
  1298 
  1333     // dequeue all datagrams that timed out
  1299     // dequeue all datagrams that timed out
  1334     list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) {
  1300     list_for_each_entry_safe(datagram, next, &master->datagram_queue, queue) {
  1335         switch (datagram->state) {
  1301         switch (datagram->state) {
  1336             case EC_DATAGRAM_SENT:
  1302             case EC_DATAGRAM_SENT:
  1337             case EC_DATAGRAM_QUEUED:
  1303             case EC_DATAGRAM_QUEUED:
  1338                 if (t_received - datagram->t_sent > t_timeout) {
  1304                 if (cycles_received - datagram->cycles_sent > cycles_timeout) {
  1339                     list_del_init(&datagram->queue);
  1305                     list_del_init(&datagram->queue);
  1340                     datagram->state = EC_DATAGRAM_TIMED_OUT;
  1306                     datagram->state = EC_DATAGRAM_TIMED_OUT;
  1341                     master->stats.timeouts++;
  1307                     master->stats.timeouts++;
  1342                     ec_master_output_stats(master);
  1308                     ec_master_output_stats(master);
  1343                 }
  1309                 }
  1358 */
  1324 */
  1359 
  1325 
  1360 void ecrt_master_prepare(ec_master_t *master /**< EtherCAT master */)
  1326 void ecrt_master_prepare(ec_master_t *master /**< EtherCAT master */)
  1361 {
  1327 {
  1362     ec_domain_t *domain;
  1328     ec_domain_t *domain;
  1363     cycles_t t_start, t_end, t_timeout;
  1329     cycles_t cycles_start, cycles_end, cycles_timeout;
  1364 
  1330 
  1365     // queue datagrams of all domains
  1331     // queue datagrams of all domains
  1366     list_for_each_entry(domain, &master->domains, list)
  1332     list_for_each_entry(domain, &master->domains, list)
  1367         ec_domain_queue(domain);
  1333         ec_domain_queue(domain);
  1368 
  1334 
  1369     ecrt_master_send(master);
  1335     ecrt_master_send(master);
  1370 
  1336 
  1371     t_start = get_cycles(); // take sending time
  1337     cycles_start = get_cycles(); // take sending time
  1372     t_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000);
  1338     cycles_timeout = (cycles_t) EC_IO_TIMEOUT * (cpu_khz / 1000);
  1373 
  1339 
  1374     // active waiting
  1340     // active waiting
  1375     while (1) {
  1341     while (1) {
  1376         t_end = get_cycles();
  1342         cycles_end = get_cycles();
  1377         if (t_end - t_start >= t_timeout) break;
  1343         if (cycles_end - cycles_start >= cycles_timeout) break;
  1378     }
  1344     }
  1379 }
  1345 }
  1380 
  1346 
  1381 /*****************************************************************************/
  1347 /*****************************************************************************/
  1382 
  1348