1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *****************************************************************************/

    33 

    34 /**

    35    \file

    36    EtherCAT driver for RTL8139-compatible NICs.

    37 */

    38 

    39 /*****************************************************************************/

    40 

    41 /*

    42   Former documentation:

    43 

    44 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    45 

    46 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    47 	Copyright 2000-2002 Jeff Garzik

    48 

    49 	Much code comes from Donald Becker's rtl8139.c driver,

    50 	versions 1.13 and older.  This driver was originally based

    51 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    52 

    53 	-----<snip>-----

    54 

    55         	Written 1997-2001 by Donald Becker.

    56 		This software may be used and distributed according to the

    57 		terms of the GNU General Public License (GPL), incorporated

    58 		herein by reference.  Drivers based on or derived from this

    59 		code fall under the GPL and must retain the authorship,

    60 		copyright and license notice.  This file is not a complete

    61 		program and may only be used when the entire operating

    62 		system is licensed under the GPL.

    63 

    64 		This driver is for boards based on the RTL8129 and RTL8139

    65 		PCI ethernet chips.

    66 

    67 		The author may be reached as becker@scyld.com, or C/O Scyld

    68 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    69 		MD 21403

    70 

    71 		Support and updates available at

    72 		http://www.scyld.com/network/rtl8139.html

    73 

    74 		Twister-tuning table provided by Kinston

    75 		<shangh@realtek.com.tw>.

    76 

    77 	-----<snip>-----

    78 

    79 	This software may be used and distributed according to the terms

    80 	of the GNU General Public License, incorporated herein by reference.

    81 

    82 	Contributors:

    83 

    84 		Donald Becker - he wrote the original driver, kudos to him!

    85 		(but please don't e-mail him for support, this isn't his driver)

    86 

    87 		Tigran Aivazian - bug fixes, skbuff free cleanup

    88 

    89 		Martin Mares - suggestions for PCI cleanup

    90 

    91 		David S. Miller - PCI DMA and softnet updates

    92 

    93 		Ernst Gill - fixes ported from BSD driver

    94 

    95 		Daniel Kobras - identified specific locations of

    96 			posted MMIO write bugginess

    97 

    98 		Gerard Sharp - bug fix, testing and feedback

    99 

   100 		David Ford - Rx ring wrap fix

   101 

   102 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

   103 		to find and fix a crucial bug on older chipsets.

   104 

   105 		Donald Becker/Chris Butterworth/Marcus Westergren -

   106 		Noticed various Rx packet size-related buglets.

   107 

   108 		Santiago Garcia Mantinan - testing and feedback

   109 

   110 		Jens David - 2.2.x kernel backports

   111 

   112 		Martin Dennett - incredibly helpful insight on undocumented

   113 		features of the 8139 chips

   114 

   115 		Jean-Jacques Michel - bug fix

   116 

   117 		Tobias Ringström - Rx interrupt status checking suggestion

   118 

   119 		Andrew Morton - Clear blocked signals, avoid

   120 		buffer overrun setting current->comm.

   121 

   122 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   123 

   124 		Robert Kuebel - Save kernel thread from dying on any signal.

   125 

   126 	Submitting bug reports:

   127 

   128 		"rtl8139-diag -mmmaaavvveefN" output

   129 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   130 

   131 */

   132 

   133 #define DRV_NAME	"ec_8139too"

   134 #define DRV_VERSION	"0.9.28"

   135 

   136 

   137 #include <linux/module.h>

   138 #include <linux/kernel.h>

   139 #include <linux/compiler.h>

   140 #include <linux/pci.h>

   141 #include <linux/init.h>

   142 #include <linux/ioport.h>

   143 #include <linux/netdevice.h>

   144 #include <linux/etherdevice.h>

   145 #include <linux/rtnetlink.h>

   146 #include <linux/delay.h>

   147 #include <linux/ethtool.h>

   148 #include <linux/mii.h>

   149 #include <linux/completion.h>

   150 #include <linux/crc32.h>

   151 #include <asm/io.h>

   152 #include <asm/uaccess.h>

   153 #include <asm/irq.h>

   154 

   155 #include "../globals.h"

   156 #include "ecdev.h"

   157 

   158 #define RTL8139_DRIVER_NAME DRV_NAME \

   159                             " EtherCAT-capable Fast Ethernet driver " \

   160                             DRV_VERSION ", master " EC_MASTER_VERSION

   161 

   162 #define PFX DRV_NAME ": "

   163 

   164 /* Default Message level */

   165 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   166                                  NETIF_MSG_PROBE  | \

   167                                  NETIF_MSG_LINK)

   168 

   169 

   170 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */

   171 #ifdef CONFIG_8139TOO_PIO

   172 #define USE_IO_OPS 1

   173 #endif

   174 

   175 /* define to 1, 2 or 3 to enable copious debugging info */

   176 #define RTL8139_DEBUG 0

   177 

   178 /* define to 1 to disable lightweight runtime debugging checks */

   179 #undef RTL8139_NDEBUG

   180 

   181 

   182 #if RTL8139_DEBUG

   183 /* note: prints function name for you */

   184 #  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)

   185 #else

   186 #  define DPRINTK(fmt, args...)

   187 #endif

   188 

   189 #ifdef RTL8139_NDEBUG

   190 #  define assert(expr) do {} while (0)

   191 #else

   192 #  define assert(expr) \

   193         if(unlikely(!(expr))) {				        \

   194         printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n",	\

   195         #expr,__FILE__,__FUNCTION__,__LINE__);		        \

   196         }

   197 #endif

   198 

   199 

   200 /* A few user-configurable values. */

   201 /* media options */

   202 #define MAX_UNITS 8

   203 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   204 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   205 

   206 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   207    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   208 static int multicast_filter_limit = 32;

   209 

   210 /* bitmapped message enable number */

   211 static int debug = -1;

   212 

   213 /*

   214  * Receive ring size

   215  * Warning: 64K ring has hardware issues and may lock up.

   216  */

   217 #if defined(CONFIG_SH_DREAMCAST)

   218 #define RX_BUF_IDX	1	/* 16K ring */

   219 #else

   220 #define RX_BUF_IDX	2	/* 32K ring */

   221 #endif

   222 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   223 #define RX_BUF_PAD	16

   224 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   225 

   226 #if RX_BUF_LEN == 65536

   227 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   228 #else

   229 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   230 #endif

   231 

   232 /* Number of Tx descriptor registers. */

   233 #define NUM_TX_DESC	4

   234 

   235 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   236 #define MAX_ETH_FRAME_SIZE	1536

   237 

   238 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   239 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   240 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   241 

   242 /* PCI Tuning Parameters

   243    Threshold is bytes transferred to chip before transmission starts. */

   244 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   245 

   246 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   247 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   248 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   249 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   250 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   251 

   252 /* Operational parameters that usually are not changed. */

   253 /* Time in jiffies before concluding the transmitter is hung. */

   254 #define TX_TIMEOUT  (6*HZ)

   255 

   256 

   257 enum {

   258 	HAS_MII_XCVR = 0x010000,

   259 	HAS_CHIP_XCVR = 0x020000,

   260 	HAS_LNK_CHNG = 0x040000,

   261 };

   262 

   263 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   264 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   265 #define RTL_MIN_IO_SIZE 0x80

   266 #define RTL8139B_IO_SIZE 256

   267 

   268 #define RTL8129_CAPS	HAS_MII_XCVR

   269 #define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG

   270 

   271 typedef enum {

   272 	RTL8139 = 0,

   273 	RTL8129,

   274 } board_t;

   275 

   276 

   277 /* indexed by board_t, above */

   278 static const struct {

   279 	const char *name;

   280 	u32 hw_flags;

   281 } board_info[] __devinitdata = {

   282 	{ "RealTek RTL8139", RTL8139_CAPS },

   283 	{ "RealTek RTL8129", RTL8129_CAPS },

   284 };

   285 

   286 

   287 static struct pci_device_id rtl8139_pci_tbl[] = {

   288 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   299 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   300 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   301 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   303 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   304 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   305 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   306 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   307 

   308 #ifdef CONFIG_SH_SECUREEDGE5410

   309 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   310 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   311 #endif

   312 #ifdef CONFIG_8139TOO_8129

   313 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   314 #endif

   315 

   316 	/* some crazy cards report invalid vendor ids like

   317 	 * 0x0001 here.  The other ids are valid and constant,

   318 	 * so we simply don't match on the main vendor id.

   319 	 */

   320 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   321 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   322 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   323 

   324 	{0,}

   325 };

   326 

   327 /* prevent driver from being loaded automatically */

   328 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   329 

   330 static struct {

   331 	const char str[ETH_GSTRING_LEN];

   332 } ethtool_stats_keys[] = {

   333 	{ "early_rx" },

   334 	{ "tx_buf_mapped" },

   335 	{ "tx_timeouts" },

   336 	{ "rx_lost_in_ring" },

   337 };

   338 

   339 /* The rest of these values should never change. */

   340 

   341 /* Symbolic offsets to registers. */

   342 enum RTL8139_registers {

   343 	MAC0 = 0,		/* Ethernet hardware address. */

   344 	MAR0 = 8,		/* Multicast filter. */

   345 	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */

   346 	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */

   347 	RxBuf = 0x30,

   348 	ChipCmd = 0x37,

   349 	RxBufPtr = 0x38,

   350 	RxBufAddr = 0x3A,

   351 	IntrMask = 0x3C,

   352 	IntrStatus = 0x3E,

   353 	TxConfig = 0x40,

   354 	RxConfig = 0x44,

   355 	Timer = 0x48,		/* A general-purpose counter. */

   356 	RxMissed = 0x4C,	/* 24 bits valid, write clears. */

   357 	Cfg9346 = 0x50,

   358 	Config0 = 0x51,

   359 	Config1 = 0x52,

   360 	FlashReg = 0x54,

   361 	MediaStatus = 0x58,

   362 	Config3 = 0x59,

   363 	Config4 = 0x5A,		/* absent on RTL-8139A */

   364 	HltClk = 0x5B,

   365 	MultiIntr = 0x5C,

   366 	TxSummary = 0x60,

   367 	BasicModeCtrl = 0x62,

   368 	BasicModeStatus = 0x64,

   369 	NWayAdvert = 0x66,

   370 	NWayLPAR = 0x68,

   371 	NWayExpansion = 0x6A,

   372 	/* Undocumented registers, but required for proper operation. */

   373 	FIFOTMS = 0x70,		/* FIFO Control and test. */

   374 	CSCR = 0x74,		/* Chip Status and Configuration Register. */

   375 	PARA78 = 0x78,

   376 	PARA7c = 0x7c,		/* Magic transceiver parameter register. */

   377 	Config5 = 0xD8,		/* absent on RTL-8139A */

   378 };

   379 

   380 enum ClearBitMasks {

   381 	MultiIntrClear = 0xF000,

   382 	ChipCmdClear = 0xE2,

   383 	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   384 };

   385 

   386 enum ChipCmdBits {

   387 	CmdReset = 0x10,

   388 	CmdRxEnb = 0x08,

   389 	CmdTxEnb = 0x04,

   390 	RxBufEmpty = 0x01,

   391 };

   392 

   393 /* Interrupt register bits, using my own meaningful names. */

   394 enum IntrStatusBits {

   395 	PCIErr = 0x8000,

   396 	PCSTimeout = 0x4000,

   397 	RxFIFOOver = 0x40,

   398 	RxUnderrun = 0x20,

   399 	RxOverflow = 0x10,

   400 	TxErr = 0x08,

   401 	TxOK = 0x04,

   402 	RxErr = 0x02,

   403 	RxOK = 0x01,

   404 

   405 	RxAckBits = RxFIFOOver | RxOverflow | RxOK,

   406 };

   407 

   408 enum TxStatusBits {

   409 	TxHostOwns = 0x2000,

   410 	TxUnderrun = 0x4000,

   411 	TxStatOK = 0x8000,

   412 	TxOutOfWindow = 0x20000000,

   413 	TxAborted = 0x40000000,

   414 	TxCarrierLost = 0x80000000,

   415 };

   416 enum RxStatusBits {

   417 	RxMulticast = 0x8000,

   418 	RxPhysical = 0x4000,

   419 	RxBroadcast = 0x2000,

   420 	RxBadSymbol = 0x0020,

   421 	RxRunt = 0x0010,

   422 	RxTooLong = 0x0008,

   423 	RxCRCErr = 0x0004,

   424 	RxBadAlign = 0x0002,

   425 	RxStatusOK = 0x0001,

   426 };

   427 

   428 /* Bits in RxConfig. */

   429 enum rx_mode_bits {

   430 	AcceptErr = 0x20,

   431 	AcceptRunt = 0x10,

   432 	AcceptBroadcast = 0x08,

   433 	AcceptMulticast = 0x04,

   434 	AcceptMyPhys = 0x02,

   435 	AcceptAllPhys = 0x01,

   436 };

   437 

   438 /* Bits in TxConfig. */

   439 enum tx_config_bits {

   440 

   441         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   442         TxIFGShift = 24,

   443         TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */

   444         TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */

   445         TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */

   446         TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */

   447 

   448 	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */

   449 	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */

   450 	TxClearAbt = (1 << 0),	/* Clear abort (WO) */

   451 	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */

   452 	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */

   453 

   454 	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */

   455 };

   456 

   457 /* Bits in Config1 */

   458 enum Config1Bits {

   459 	Cfg1_PM_Enable = 0x01,

   460 	Cfg1_VPD_Enable = 0x02,

   461 	Cfg1_PIO = 0x04,

   462 	Cfg1_MMIO = 0x08,

   463 	LWAKE = 0x10,		/* not on 8139, 8139A */

   464 	Cfg1_Driver_Load = 0x20,

   465 	Cfg1_LED0 = 0x40,

   466 	Cfg1_LED1 = 0x80,

   467 	SLEEP = (1 << 1),	/* only on 8139, 8139A */

   468 	PWRDN = (1 << 0),	/* only on 8139, 8139A */

   469 };

   470 

   471 /* Bits in Config3 */

   472 enum Config3Bits {

   473 	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */

   474 	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */

   475 	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */

   476 	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */

   477 	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */

   478 	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */

   479 	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */

   480 	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */

   481 };

   482 

   483 /* Bits in Config4 */

   484 enum Config4Bits {

   485 	LWPTN = (1 << 2),	/* not on 8139, 8139A */

   486 };

   487 

   488 /* Bits in Config5 */

   489 enum Config5Bits {

   490 	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */

   491 	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */

   492 	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */

   493 	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */

   494 	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */

   495 	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */

   496 	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */

   497 };

   498 

   499 enum RxConfigBits {

   500 	/* rx fifo threshold */

   501 	RxCfgFIFOShift = 13,

   502 	RxCfgFIFONone = (7 << RxCfgFIFOShift),

   503 

   504 	/* Max DMA burst */

   505 	RxCfgDMAShift = 8,

   506 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   507 

   508 	/* rx ring buffer length */

   509 	RxCfgRcv8K = 0,

   510 	RxCfgRcv16K = (1 << 11),

   511 	RxCfgRcv32K = (1 << 12),

   512 	RxCfgRcv64K = (1 << 11) | (1 << 12),

   513 

   514 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   515 	RxNoWrap = (1 << 7),

   516 };

   517 

   518 /* Twister tuning parameters from RealTek.

   519    Completely undocumented, but required to tune bad links on some boards. */

   520 enum CSCRBits {

   521 	CSCR_LinkOKBit = 0x0400,

   522 	CSCR_LinkChangeBit = 0x0800,

   523 	CSCR_LinkStatusBits = 0x0f000,

   524 	CSCR_LinkDownOffCmd = 0x003c0,

   525 	CSCR_LinkDownCmd = 0x0f3c0,

   526 };

   527 

   528 enum Cfg9346Bits {

   529 	Cfg9346_Lock = 0x00,

   530 	Cfg9346_Unlock = 0xC0,

   531 };

   532 

   533 typedef enum {

   534 	CH_8139 = 0,

   535 	CH_8139_K,

   536 	CH_8139A,

   537 	CH_8139A_G,

   538 	CH_8139B,

   539 	CH_8130,

   540 	CH_8139C,

   541 	CH_8100,

   542 	CH_8100B_8139D,

   543 	CH_8101,

   544 } chip_t;

   545 

   546 enum chip_flags {

   547 	HasHltClk = (1 << 0),

   548 	HasLWake = (1 << 1),

   549 };

   550 

   551 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   552 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   553 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   554 

   555 /* directly indexed by chip_t, above */

   556 static const struct {

   557 	const char *name;

   558 	u32 version; /* from RTL8139C/RTL8139D docs */

   559 	u32 flags;

   560 } rtl_chip_info[] = {

   561 	{ "RTL-8139",

   562 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   563 	  HasHltClk,

   564 	},

   565 

   566 	{ "RTL-8139 rev K",

   567 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   568 	  HasHltClk,

   569 	},

   570 

   571 	{ "RTL-8139A",

   572 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   573 	  HasHltClk, /* XXX undocumented? */

   574 	},

   575 

   576 	{ "RTL-8139A rev G",

   577 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   578 	  HasHltClk, /* XXX undocumented? */

   579 	},

   580 

   581 	{ "RTL-8139B",

   582 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   583 	  HasLWake,

   584 	},

   585 

   586 	{ "RTL-8130",

   587 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   588 	  HasLWake,

   589 	},

   590 

   591 	{ "RTL-8139C",

   592 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   593 	  HasLWake,

   594 	},

   595 

   596 	{ "RTL-8100",

   597 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   598  	  HasLWake,

   599  	},

   600 

   601 	{ "RTL-8100B/8139D",

   602 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   603 	  HasHltClk /* XXX undocumented? */

   604 	| HasLWake,

   605 	},

   606 

   607 	{ "RTL-8101",

   608 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   609 	  HasLWake,

   610 	},

   611 };

   612 

   613 struct rtl_extra_stats {

   614 	unsigned long early_rx;

   615 	unsigned long tx_buf_mapped;

   616 	unsigned long tx_timeouts;

   617 	unsigned long rx_lost_in_ring;

   618 };

   619 

   620 struct rtl8139_private {

   621 	void __iomem *mmio_addr;

   622 	int drv_flags;

   623 	struct pci_dev *pci_dev;

   624 	u32 msg_enable;

   625 	struct net_device_stats stats;

   626 	unsigned char *rx_ring;

   627 	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */

   628 	unsigned int tx_flag;

   629 	unsigned long cur_tx;

   630 	unsigned long dirty_tx;

   631 	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   632 	unsigned char *tx_bufs;	/* Tx bounce buffer region. */

   633 	dma_addr_t rx_ring_dma;

   634 	dma_addr_t tx_bufs_dma;

   635 	signed char phys[4];		/* MII device addresses. */

   636 	char twistie, twist_row, twist_col;	/* Twister tune state. */

   637 	unsigned int watchdog_fired : 1;

   638 	unsigned int default_port : 4;	/* Last dev->if_port value. */

   639 	unsigned int have_thread : 1;

   640 	spinlock_t lock;

   641 	spinlock_t rx_lock;

   642 	chip_t chipset;

   643 	u32 rx_config;

   644 	struct rtl_extra_stats xstats;

   645 

   646 	struct delayed_work thread;

   647 

   648 	struct mii_if_info mii;

   649 	unsigned int regs_len;

   650 	unsigned long fifo_copy_timeout;

   651     

   652 	ec_device_t *ecdev;

   653 };

   654 

   655 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   656 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   657 MODULE_LICENSE("GPL");

   658 MODULE_VERSION(EC_MASTER_VERSION);

   659 

   660 module_param(multicast_filter_limit, int, 0);

   661 module_param_array(media, int, NULL, 0);

   662 module_param_array(full_duplex, int, NULL, 0);

   663 module_param(debug, int, 0);

   664 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   665 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   666 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   667 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   668 

   669 void ec_poll(struct net_device *);

   670 

   671 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   672 static int rtl8139_open (struct net_device *dev);

   673 static int mdio_read (struct net_device *dev, int phy_id, int location);

   674 static void mdio_write (struct net_device *dev, int phy_id, int location,

   675 			int val);

   676 static void rtl8139_start_thread(struct rtl8139_private *tp);

   677 static void rtl8139_tx_timeout (struct net_device *dev);

   678 static void rtl8139_init_ring (struct net_device *dev);

   679 static int rtl8139_start_xmit (struct sk_buff *skb,

   680 			       struct net_device *dev);

   681 static int rtl8139_poll(struct net_device *dev, int *budget);

   682 #ifdef CONFIG_NET_POLL_CONTROLLER

   683 static void rtl8139_poll_controller(struct net_device *dev);

   684 #endif

   685 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   686 static int rtl8139_close (struct net_device *dev);

   687 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   688 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   689 static void rtl8139_set_rx_mode (struct net_device *dev);

   690 static void __set_rx_mode (struct net_device *dev);

   691 static void rtl8139_hw_start (struct net_device *dev);

   692 static void rtl8139_thread (struct work_struct *work);

   693 static void rtl8139_tx_timeout_task(struct work_struct *work);

   694 static const struct ethtool_ops rtl8139_ethtool_ops;

   695 

   696 /* write MMIO register, with flush */

   697 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   698 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   699 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   700 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   701 

   702 

   703 #define MMIO_FLUSH_AUDIT_COMPLETE 1

   704 #if MMIO_FLUSH_AUDIT_COMPLETE

   705 

   706 /* write MMIO register */

   707 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   708 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   709 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   710 

   711 #else

   712 

   713 /* write MMIO register, then flush */

   714 #define RTL_W8		RTL_W8_F

   715 #define RTL_W16		RTL_W16_F

   716 #define RTL_W32		RTL_W32_F

   717 

   718 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */

   719 

   720 /* read MMIO register */

   721 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   722 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   723 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   724 

   725 

   726 static const u16 rtl8139_intr_mask =

   727 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   728 	TxErr | TxOK | RxErr | RxOK;

   729 

   730 static const u16 rtl8139_norx_intr_mask =

   731 	PCIErr | PCSTimeout | RxUnderrun |

   732 	TxErr | TxOK | RxErr ;

   733 

   734 #if RX_BUF_IDX == 0

   735 static const unsigned int rtl8139_rx_config =

   736 	RxCfgRcv8K | RxNoWrap |

   737 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   738 	(RX_DMA_BURST << RxCfgDMAShift);

   739 #elif RX_BUF_IDX == 1

   740 static const unsigned int rtl8139_rx_config =

   741 	RxCfgRcv16K | RxNoWrap |

   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   743 	(RX_DMA_BURST << RxCfgDMAShift);

   744 #elif RX_BUF_IDX == 2

   745 static const unsigned int rtl8139_rx_config =

   746 	RxCfgRcv32K | RxNoWrap |

   747 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   748 	(RX_DMA_BURST << RxCfgDMAShift);

   749 #elif RX_BUF_IDX == 3

   750 static const unsigned int rtl8139_rx_config =

   751 	RxCfgRcv64K |

   752 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   753 	(RX_DMA_BURST << RxCfgDMAShift);

   754 #else

   755 #error "Invalid configuration for 8139_RXBUF_IDX"

   756 #endif

   757 

   758 static const unsigned int rtl8139_tx_config =

   759 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   760 

   761 static void __rtl8139_cleanup_dev (struct net_device *dev)

   762 {

   763 	struct rtl8139_private *tp = netdev_priv(dev);

   764 	struct pci_dev *pdev;

   765 

   766 	assert (dev != NULL);

   767 	assert (tp->pci_dev != NULL);

   768 	pdev = tp->pci_dev;

   769 

   770 #ifdef USE_IO_OPS

   771 	if (tp->mmio_addr)

   772 		ioport_unmap (tp->mmio_addr);

   773 #else

   774 	if (tp->mmio_addr)

   775 		pci_iounmap (pdev, tp->mmio_addr);

   776 #endif /* USE_IO_OPS */

   777 

   778 	/* it's ok to call this even if we have no regions to free */

   779 	pci_release_regions (pdev);

   780 

   781 	free_netdev(dev);

   782 	pci_set_drvdata (pdev, NULL);

   783 }

   784 

   785 

   786 static void rtl8139_chip_reset (void __iomem *ioaddr)

   787 {

   788 	int i;

   789 

   790 	/* Soft reset the chip. */

   791 	RTL_W8 (ChipCmd, CmdReset);

   792 

   793 	/* Check that the chip has finished the reset. */

   794 	for (i = 1000; i > 0; i--) {

   795 		barrier();

   796 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   797 			break;

   798 		udelay (10);

   799 	}

   800 }

   801 

   802 

   803 static int __devinit rtl8139_init_board (struct pci_dev *pdev,

   804 					 struct net_device **dev_out)

   805 {

   806 	void __iomem *ioaddr;

   807 	struct net_device *dev;

   808 	struct rtl8139_private *tp;

   809 	u8 tmp8;

   810 	int rc, disable_dev_on_err = 0;

   811 	unsigned int i;

   812 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   813 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   814 	u32 version;

   815 

   816 	assert (pdev != NULL);

   817 

   818 	*dev_out = NULL;

   819 

   820 	/* dev and priv zeroed in alloc_etherdev */

   821 	dev = alloc_etherdev (sizeof (*tp));

   822 	if (dev == NULL) {

   823 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   824 		return -ENOMEM;

   825 	}

   826 	SET_MODULE_OWNER(dev);

   827 	SET_NETDEV_DEV(dev, &pdev->dev);

   828 

   829 	tp = netdev_priv(dev);

   830 	tp->pci_dev = pdev;

   831 

   832 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   833 	rc = pci_enable_device (pdev);

   834 	if (rc)

   835 		goto err_out;

   836 

   837 	pio_start = pci_resource_start (pdev, 0);

   838 	pio_end = pci_resource_end (pdev, 0);

   839 	pio_flags = pci_resource_flags (pdev, 0);

   840 	pio_len = pci_resource_len (pdev, 0);

   841 

   842 	mmio_start = pci_resource_start (pdev, 1);

   843 	mmio_end = pci_resource_end (pdev, 1);

   844 	mmio_flags = pci_resource_flags (pdev, 1);

   845 	mmio_len = pci_resource_len (pdev, 1);

   846 

   847 	/* set this immediately, we need to know before

   848 	 * we talk to the chip directly */

   849 	DPRINTK("PIO region size == 0x%02X\n", pio_len);

   850 	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);

   851 

   852 #ifdef USE_IO_OPS

   853 	/* make sure PCI base addr 0 is PIO */

   854 	if (!(pio_flags & IORESOURCE_IO)) {

   855 		dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   856 		rc = -ENODEV;

   857 		goto err_out;

   858 	}

   859 	/* check for weird/broken PCI region reporting */

   860 	if (pio_len < RTL_MIN_IO_SIZE) {

   861 		dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   862 		rc = -ENODEV;

   863 		goto err_out;

   864 	}

   865 #else

   866 	/* make sure PCI base addr 1 is MMIO */

   867 	if (!(mmio_flags & IORESOURCE_MEM)) {

   868 		dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   869 		rc = -ENODEV;

   870 		goto err_out;

   871 	}

   872 	if (mmio_len < RTL_MIN_IO_SIZE) {

   873 		dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   874 		rc = -ENODEV;

   875 		goto err_out;

   876 	}

   877 #endif

   878 

   879 	rc = pci_request_regions (pdev, DRV_NAME);

   880 	if (rc)

   881 		goto err_out;

   882 	disable_dev_on_err = 1;

   883 

   884 	/* enable PCI bus-mastering */

   885 	pci_set_master (pdev);

   886 

   887 #ifdef USE_IO_OPS

   888 	ioaddr = ioport_map(pio_start, pio_len);

   889 	if (!ioaddr) {

   890 		dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   891 		rc = -EIO;

   892 		goto err_out;

   893 	}

   894 	dev->base_addr = pio_start;

   895 	tp->mmio_addr = ioaddr;

   896 	tp->regs_len = pio_len;

   897 #else

   898 	/* ioremap MMIO region */

   899 	ioaddr = pci_iomap(pdev, 1, 0);

   900 	if (ioaddr == NULL) {

   901 		dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");

   902 		rc = -EIO;

   903 		goto err_out;

   904 	}

   905 	dev->base_addr = (long) ioaddr;

   906 	tp->mmio_addr = ioaddr;

   907 	tp->regs_len = mmio_len;

   908 #endif /* USE_IO_OPS */

   909 

   910 	/* Bring old chips out of low-power mode. */

   911 	RTL_W8 (HltClk, 'R');

   912 

   913 	/* check for missing/broken hardware */

   914 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   915 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   916 		rc = -EIO;

   917 		goto err_out;

   918 	}

   919 

   920 	/* identify chip attached to board */

   921 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   922 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   923 		if (version == rtl_chip_info[i].version) {

   924 			tp->chipset = i;

   925 			goto match;

   926 		}

   927 

   928 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   929 	dev_printk (KERN_DEBUG, &pdev->dev,

   930 		    "unknown chip version, assuming RTL-8139\n");

   931 	dev_printk (KERN_DEBUG, &pdev->dev,

   932 		    "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   933 	tp->chipset = 0;

   934 

   935 match:

   936 	DPRINTK ("chipset id (%d) == index %d, '%s'\n",

   937 		 version, i, rtl_chip_info[i].name);

   938 

   939 	if (tp->chipset >= CH_8139B) {

   940 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   941 		DPRINTK("PCI PM wakeup\n");

   942 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   943 		    (tmp8 & LWAKE))

   944 			new_tmp8 &= ~LWAKE;

   945 		new_tmp8 |= Cfg1_PM_Enable;

   946 		if (new_tmp8 != tmp8) {

   947 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   948 			RTL_W8 (Config1, tmp8);

   949 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   950 		}

   951 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   952 			tmp8 = RTL_R8 (Config4);

   953 			if (tmp8 & LWPTN) {

   954 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   955 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   956 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   957 			}

   958 		}

   959 	} else {

   960 		DPRINTK("Old chip wakeup\n");

   961 		tmp8 = RTL_R8 (Config1);

   962 		tmp8 &= ~(SLEEP | PWRDN);

   963 		RTL_W8 (Config1, tmp8);

   964 	}

   965 

   966 	rtl8139_chip_reset (ioaddr);

   967 

   968 	*dev_out = dev;

   969 	return 0;

   970 

   971 err_out:

   972 	__rtl8139_cleanup_dev (dev);

   973 	if (disable_dev_on_err)

   974 		pci_disable_device (pdev);

   975 	return rc;

   976 }

   977 

   978 

   979 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   980 				       const struct pci_device_id *ent)

   981 {

   982 	struct net_device *dev = NULL;

   983 	struct rtl8139_private *tp;

   984 	int i, addr_len, option;

   985 	void __iomem *ioaddr;

   986 	static int board_idx = -1;

   987 	u8 pci_rev;

   988 

   989 	assert (pdev != NULL);

   990 	assert (ent != NULL);

   991 

   992 	board_idx++;

   993 

   994 	/* when we're built into the kernel, the driver version message

   995 	 * is only printed if at least one 8139 board has been found

   996 	 */

   997 #ifndef MODULE

   998 	{

   999 		static int printed_version;

  1000 		if (!printed_version++)

  1001 			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");

  1002 	}

  1003 #endif

  1004 

  1005 	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);

  1006 

  1007 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1008 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {

  1009 		dev_info(&pdev->dev,

  1010 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",

  1011 		       	   pdev->vendor, pdev->device, pci_rev);

  1012 		dev_info(&pdev->dev,

  1013 			   "Use the \"8139cp\" driver for improved performance and stability.\n");

  1014 	}

  1015 

  1016 	i = rtl8139_init_board (pdev, &dev);

  1017 	if (i < 0)

  1018 		return i;

  1019 

  1020 	assert (dev != NULL);

  1021 	tp = netdev_priv(dev);

  1022 

  1023 	ioaddr = tp->mmio_addr;

  1024 	assert (ioaddr != NULL);

  1025 

  1026 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1027 	for (i = 0; i < 3; i++)

  1028 		((u16 *) (dev->dev_addr))[i] =

  1029 		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));

  1030 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1031 

  1032 	/* The Rtl8139-specific entries in the device structure. */

  1033 	dev->open = rtl8139_open;

  1034 	dev->hard_start_xmit = rtl8139_start_xmit;

  1035 	dev->poll = rtl8139_poll;

  1036 	dev->weight = 64;

  1037 	dev->stop = rtl8139_close;

  1038 	dev->get_stats = rtl8139_get_stats;

  1039 	dev->set_multicast_list = rtl8139_set_rx_mode;

  1040 	dev->do_ioctl = netdev_ioctl;

  1041 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1042 	dev->tx_timeout = rtl8139_tx_timeout;

  1043 	dev->watchdog_timeo = TX_TIMEOUT;

  1044 #ifdef CONFIG_NET_POLL_CONTROLLER

  1045 	dev->poll_controller = rtl8139_poll_controller;

  1046 #endif

  1047 

  1048 	/* note: the hardware is not capable of sg/csum/highdma, however

  1049 	 * through the use of skb_copy_and_csum_dev we enable these

  1050 	 * features

  1051 	 */

  1052 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1053 

  1054 	dev->irq = pdev->irq;

  1055 

  1056 	/* tp zeroed and aligned in alloc_etherdev */

  1057 	tp = netdev_priv(dev);

  1058 

  1059 	/* note: tp->chipset set in rtl8139_init_board */

  1060 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1061 	tp->mmio_addr = ioaddr;

  1062 	tp->msg_enable =

  1063 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1064 	spin_lock_init (&tp->lock);

  1065 	spin_lock_init (&tp->rx_lock);

  1066 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1067 	tp->mii.dev = dev;

  1068 	tp->mii.mdio_read = mdio_read;

  1069 	tp->mii.mdio_write = mdio_write;

  1070 	tp->mii.phy_id_mask = 0x3f;

  1071 	tp->mii.reg_num_mask = 0x1f;

  1072 

  1073 	/* dev is fully set up and ready to use now */

  1074     

  1075 	// offer device to EtherCAT master module

  1076 	if (ecdev_offer(dev, ec_poll, THIS_MODULE, &tp->ecdev)) {

  1077 		printk(KERN_ERR PFX "Failed to offer device.\n");

  1078 		goto err_out;

  1079 	}

  1080 

  1081 	if (!tp->ecdev) {

  1082 		DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);

  1083 		i = register_netdev (dev);

  1084 		if (i) goto err_out;

  1085 	}

  1086 

  1087 	pci_set_drvdata (pdev, dev);

  1088 

  1089 	printk (KERN_INFO "%s: %s at 0x%lx, "

  1090 		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "

  1091 		"IRQ %d\n",

  1092 		dev->name,

  1093 		board_info[ent->driver_data].name,

  1094 		dev->base_addr,

  1095 		dev->dev_addr[0], dev->dev_addr[1],

  1096 		dev->dev_addr[2], dev->dev_addr[3],

  1097 		dev->dev_addr[4], dev->dev_addr[5],

  1098 		dev->irq);

  1099 

  1100 	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",

  1101 		dev->name, rtl_chip_info[tp->chipset].name);

  1102 

  1103 	/* Find the connected MII xcvrs.

  1104 	   Doing this in open() would allow detecting external xcvrs later, but

  1105 	   takes too much time. */

  1106 #ifdef CONFIG_8139TOO_8129

  1107 	if (tp->drv_flags & HAS_MII_XCVR) {

  1108 		int phy, phy_idx = 0;

  1109 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1110 			int mii_status = mdio_read(dev, phy, 1);

  1111 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1112 				u16 advertising = mdio_read(dev, phy, 4);

  1113 				tp->phys[phy_idx++] = phy;

  1114 				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "

  1115 					   "advertising %4.4x.\n",

  1116 					   dev->name, phy, mii_status, advertising);

  1117 			}

  1118 		}

  1119 		if (phy_idx == 0) {

  1120 			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "

  1121 				   "transceiver.\n",

  1122 				   dev->name);

  1123 			tp->phys[0] = 32;

  1124 		}

  1125 	} else

  1126 #endif

  1127 		tp->phys[0] = 32;

  1128 	tp->mii.phy_id = tp->phys[0];

  1129 

  1130 	/* The lower four bits are the media type. */

  1131 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1132 	if (option > 0) {

  1133 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1134 		tp->default_port = option & 0xFF;

  1135 		if (tp->default_port)

  1136 			tp->mii.force_media = 1;