1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2006-2009  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it and/or

    10  *  modify it under the terms of the GNU General Public License version 2, as

    11  *  published by the Free Software Foundation.

    12  *

    13  *  The IgH EtherCAT Master is distributed in the hope that it will be useful,

    14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General

    16  *  Public License for more details.

    17  *

    18  *  You should have received a copy of the GNU General Public License along

    19  *  with the IgH EtherCAT Master; if not, write to the Free Software

    20  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    21  *

    22  *  ---

    23  *

    24  *  The license mentioned above concerns the source code only. Using the

    25  *  EtherCAT technology and brand is only permitted in compliance with the

    26  *  industrial property and similar rights of Beckhoff Automation GmbH.

    27  *

    28  *****************************************************************************/

    29 

    30 /**

    31    \file

    32    EtherCAT driver for RTL8139-compatible NICs.

    33 */

    34 

    35 /*****************************************************************************/

    36 

    37 /*

    38   Former documentation:

    39 

    40 	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.

    41 

    42 	Maintained by Jeff Garzik <jgarzik@pobox.com>

    43 	Copyright 2000-2002 Jeff Garzik

    44 

    45 	Much code comes from Donald Becker's rtl8139.c driver,

    46 	versions 1.13 and older.  This driver was originally based

    47 	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:

    48 

    49 	-----<snip>-----

    50 

    51         	Written 1997-2001 by Donald Becker.

    52 		This software may be used and distributed according to the

    53 		terms of the GNU General Public License (GPL), incorporated

    54 		herein by reference.  Drivers based on or derived from this

    55 		code fall under the GPL and must retain the authorship,

    56 		copyright and license notice.  This file is not a complete

    57 		program and may only be used when the entire operating

    58 		system is licensed under the GPL.

    59 

    60 		This driver is for boards based on the RTL8129 and RTL8139

    61 		PCI ethernet chips.

    62 

    63 		The author may be reached as becker@scyld.com, or C/O Scyld

    64 		Computing Corporation 410 Severn Ave., Suite 210 Annapolis

    65 		MD 21403

    66 

    67 		Support and updates available at

    68 		http://www.scyld.com/network/rtl8139.html

    69 

    70 		Twister-tuning table provided by Kinston

    71 		<shangh@realtek.com.tw>.

    72 

    73 	-----<snip>-----

    74 

    75 	This software may be used and distributed according to the terms

    76 	of the GNU General Public License, incorporated herein by reference.

    77 

    78 	Contributors:

    79 

    80 		Donald Becker - he wrote the original driver, kudos to him!

    81 		(but please don't e-mail him for support, this isn't his driver)

    82 

    83 		Tigran Aivazian - bug fixes, skbuff free cleanup

    84 

    85 		Martin Mares - suggestions for PCI cleanup

    86 

    87 		David S. Miller - PCI DMA and softnet updates

    88 

    89 		Ernst Gill - fixes ported from BSD driver

    90 

    91 		Daniel Kobras - identified specific locations of

    92 			posted MMIO write bugginess

    93 

    94 		Gerard Sharp - bug fix, testing and feedback

    95 

    96 		David Ford - Rx ring wrap fix

    97 

    98 		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me

    99 		to find and fix a crucial bug on older chipsets.

   100 

   101 		Donald Becker/Chris Butterworth/Marcus Westergren -

   102 		Noticed various Rx packet size-related buglets.

   103 

   104 		Santiago Garcia Mantinan - testing and feedback

   105 

   106 		Jens David - 2.2.x kernel backports

   107 

   108 		Martin Dennett - incredibly helpful insight on undocumented

   109 		features of the 8139 chips

   110 

   111 		Jean-Jacques Michel - bug fix

   112 

   113 		Tobias Ringström - Rx interrupt status checking suggestion

   114 

   115 		Andrew Morton - Clear blocked signals, avoid

   116 		buffer overrun setting current->comm.

   117 

   118 		Kalle Olavi Niemitalo - Wake-on-LAN ioctls

   119 

   120 		Robert Kuebel - Save kernel thread from dying on any signal.

   121 

   122 	Submitting bug reports:

   123 

   124 		"rtl8139-diag -mmmaaavvveefN" output

   125 		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log

   126 

   127 */

   128 

   129 #define DRV_NAME	"ec_8139too"

   130 #define DRV_VERSION	"0.9.28"

   131 

   132 

   133 #include <linux/module.h>

   134 #include <linux/kernel.h>

   135 #include <linux/compiler.h>

   136 #include <linux/pci.h>

   137 #include <linux/init.h>

   138 #include <linux/netdevice.h>

   139 #include <linux/etherdevice.h>

   140 #include <linux/rtnetlink.h>

   141 #include <linux/delay.h>

   142 #include <linux/ethtool.h>

   143 #include <linux/mii.h>

   144 #include <linux/completion.h>

   145 #include <linux/crc32.h>

   146 #include <linux/io.h>

   147 #include <linux/uaccess.h>

   148 #include <linux/gfp.h>

   149 #include <asm/irq.h>

   150 

   151 #include "../globals.h"

   152 #include "ecdev.h"

   153 

   154 #define RTL8139_DRIVER_NAME DRV_NAME \

   155                             " EtherCAT-capable Fast Ethernet driver " \

   156                             DRV_VERSION ", master " EC_MASTER_VERSION

   157 

   158 #define PFX DRV_NAME ": "

   159 

   160 /* Default Message level */

   161 #define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \

   162                                  NETIF_MSG_PROBE  | \

   163                                  NETIF_MSG_LINK)

   164 

   165 

   166 /* define to 1, 2 or 3 to enable copious debugging info */

   167 #define RTL8139_DEBUG 0

   168 

   169 /* define to 1 to disable lightweight runtime debugging checks */

   170 #undef RTL8139_NDEBUG

   171 

   172 

   173 #ifdef RTL8139_NDEBUG

   174 #  define assert(expr) do {} while (0)

   175 #else

   176 #  define assert(expr) \

   177         if(unlikely(!(expr))) {				        \

   178         pr_err("Assertion failed! %s,%s,%s,line=%d\n",	\

   179 	#expr, __FILE__, __func__, __LINE__);			\

   180         }

   181 #endif

   182 

   183 

   184 /* A few user-configurable values. */

   185 /* media options */

   186 #define MAX_UNITS 8

   187 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   188 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};

   189 

   190 /* Whether to use MMIO or PIO. Default to MMIO. */

   191 #ifdef CONFIG_8139TOO_PIO

   192 static int use_io = 1;

   193 #else

   194 static int use_io = 0;

   195 #endif

   196 

   197 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).

   198    The RTL chips use a 64 element hash table based on the Ethernet CRC.  */

   199 static int multicast_filter_limit = 32;

   200 

   201 /* bitmapped message enable number */

   202 static int debug = -1;

   203 

   204 /*

   205  * Receive ring size

   206  * Warning: 64K ring has hardware issues and may lock up.

   207  */

   208 #if defined(CONFIG_SH_DREAMCAST)

   209 #define RX_BUF_IDX 0	/* 8K ring */

   210 #else

   211 #define RX_BUF_IDX	2	/* 32K ring */

   212 #endif

   213 #define RX_BUF_LEN	(8192 << RX_BUF_IDX)

   214 #define RX_BUF_PAD	16

   215 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */

   216 

   217 #if RX_BUF_LEN == 65536

   218 #define RX_BUF_TOT_LEN	RX_BUF_LEN

   219 #else

   220 #define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)

   221 #endif

   222 

   223 /* Number of Tx descriptor registers. */

   224 #define NUM_TX_DESC	4

   225 

   226 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/

   227 #define MAX_ETH_FRAME_SIZE	1536

   228 

   229 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */

   230 #define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE

   231 #define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)

   232 

   233 /* PCI Tuning Parameters

   234    Threshold is bytes transferred to chip before transmission starts. */

   235 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */

   236 

   237 /* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */

   238 #define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */

   239 #define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */

   240 #define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */

   241 #define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */

   242 

   243 /* Operational parameters that usually are not changed. */

   244 /* Time in jiffies before concluding the transmitter is hung. */

   245 #define TX_TIMEOUT  (6*HZ)

   246 

   247 

   248 enum {

   249 	HAS_MII_XCVR = 0x010000,

   250 	HAS_CHIP_XCVR = 0x020000,

   251 	HAS_LNK_CHNG = 0x040000,

   252 };

   253 

   254 #define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */

   255 #define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */

   256 #define RTL_MIN_IO_SIZE 0x80

   257 #define RTL8139B_IO_SIZE 256

   258 

   259 #define RTL8129_CAPS	HAS_MII_XCVR

   260 #define RTL8139_CAPS	(HAS_CHIP_XCVR|HAS_LNK_CHNG)

   261 

   262 typedef enum {

   263 	RTL8139 = 0,

   264 	RTL8129,

   265 } board_t;

   266 

   267 

   268 /* indexed by board_t, above */

   269 static const struct {

   270 	const char *name;

   271 	u32 hw_flags;

   272 } board_info[] __devinitdata = {

   273 	{ "RealTek RTL8139", RTL8139_CAPS },

   274 	{ "RealTek RTL8129", RTL8129_CAPS },

   275 };

   276 

   277 

   278 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {

   279 	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   280 	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   281 	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   282 	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   283 	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   284 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   285 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   286 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   287 	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   288 	{0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   289 	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   290 	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   291 	{0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   292 	{0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   293 	{0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   294 	{0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   295 	{0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   296 	{0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   297 	{0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   298 

   299 #ifdef CONFIG_SH_SECUREEDGE5410

   300 	/* Bogus 8139 silicon reports 8129 without external PROM :-( */

   301 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },

   302 #endif

   303 #ifdef CONFIG_8139TOO_8129

   304 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },

   305 #endif

   306 

   307 	/* some crazy cards report invalid vendor ids like

   308 	 * 0x0001 here.  The other ids are valid and constant,

   309 	 * so we simply don't match on the main vendor id.

   310 	 */

   311 	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },

   312 	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },

   313 	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },

   314 

   315 	{0,}

   316 };

   317 

   318 /* prevent driver from being loaded automatically */

   319 //MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);

   320 

   321 static struct {

   322 	const char str[ETH_GSTRING_LEN];

   323 } ethtool_stats_keys[] = {

   324 	{ "early_rx" },

   325 	{ "tx_buf_mapped" },

   326 	{ "tx_timeouts" },

   327 	{ "rx_lost_in_ring" },

   328 };

   329 

   330 /* The rest of these values should never change. */

   331 

   332 /* Symbolic offsets to registers. */

   333 enum RTL8139_registers {

   334 	MAC0		= 0,	 /* Ethernet hardware address. */

   335 	MAR0		= 8,	 /* Multicast filter. */

   336 	TxStatus0	= 0x10,	 /* Transmit status (Four 32bit registers). */

   337 	TxAddr0		= 0x20,	 /* Tx descriptors (also four 32bit). */

   338 	RxBuf		= 0x30,

   339 	ChipCmd		= 0x37,

   340 	RxBufPtr	= 0x38,

   341 	RxBufAddr	= 0x3A,

   342 	IntrMask	= 0x3C,

   343 	IntrStatus	= 0x3E,

   344 	TxConfig	= 0x40,

   345 	RxConfig	= 0x44,

   346 	Timer		= 0x48,	 /* A general-purpose counter. */

   347 	RxMissed	= 0x4C,  /* 24 bits valid, write clears. */

   348 	Cfg9346		= 0x50,

   349 	Config0		= 0x51,

   350 	Config1		= 0x52,

   351 	TimerInt	= 0x54,

   352 	MediaStatus	= 0x58,

   353 	Config3		= 0x59,

   354 	Config4		= 0x5A,	 /* absent on RTL-8139A */

   355 	HltClk		= 0x5B,

   356 	MultiIntr	= 0x5C,

   357 	TxSummary	= 0x60,

   358 	BasicModeCtrl	= 0x62,

   359 	BasicModeStatus	= 0x64,

   360 	NWayAdvert	= 0x66,

   361 	NWayLPAR	= 0x68,

   362 	NWayExpansion	= 0x6A,

   363 	/* Undocumented registers, but required for proper operation. */

   364 	FIFOTMS		= 0x70,	 /* FIFO Control and test. */

   365 	CSCR		= 0x74,	 /* Chip Status and Configuration Register. */

   366 	PARA78		= 0x78,

   367 	FlashReg	= 0xD4,	/* Communication with Flash ROM, four bytes. */

   368 	PARA7c		= 0x7c,	 /* Magic transceiver parameter register. */

   369 	Config5		= 0xD8,	 /* absent on RTL-8139A */

   370 };

   371 

   372 enum ClearBitMasks {

   373 	MultiIntrClear	= 0xF000,

   374 	ChipCmdClear	= 0xE2,

   375 	Config1Clear	= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),

   376 };

   377 

   378 enum ChipCmdBits {

   379 	CmdReset	= 0x10,

   380 	CmdRxEnb	= 0x08,

   381 	CmdTxEnb	= 0x04,

   382 	RxBufEmpty	= 0x01,

   383 };

   384 

   385 /* Interrupt register bits, using my own meaningful names. */

   386 enum IntrStatusBits {

   387 	PCIErr		= 0x8000,

   388 	PCSTimeout	= 0x4000,

   389 	RxFIFOOver	= 0x40,

   390 	RxUnderrun	= 0x20,

   391 	RxOverflow	= 0x10,

   392 	TxErr		= 0x08,

   393 	TxOK		= 0x04,

   394 	RxErr		= 0x02,

   395 	RxOK		= 0x01,

   396 

   397 	RxAckBits	= RxFIFOOver | RxOverflow | RxOK,

   398 };

   399 

   400 enum TxStatusBits {

   401 	TxHostOwns	= 0x2000,

   402 	TxUnderrun	= 0x4000,

   403 	TxStatOK	= 0x8000,

   404 	TxOutOfWindow	= 0x20000000,

   405 	TxAborted	= 0x40000000,

   406 	TxCarrierLost	= 0x80000000,

   407 };

   408 enum RxStatusBits {

   409 	RxMulticast	= 0x8000,

   410 	RxPhysical	= 0x4000,

   411 	RxBroadcast	= 0x2000,

   412 	RxBadSymbol	= 0x0020,

   413 	RxRunt		= 0x0010,

   414 	RxTooLong	= 0x0008,

   415 	RxCRCErr	= 0x0004,

   416 	RxBadAlign	= 0x0002,

   417 	RxStatusOK	= 0x0001,

   418 };

   419 

   420 /* Bits in RxConfig. */

   421 enum rx_mode_bits {

   422 	AcceptErr	= 0x20,

   423 	AcceptRunt	= 0x10,

   424 	AcceptBroadcast	= 0x08,

   425 	AcceptMulticast	= 0x04,

   426 	AcceptMyPhys	= 0x02,

   427 	AcceptAllPhys	= 0x01,

   428 };

   429 

   430 /* Bits in TxConfig. */

   431 enum tx_config_bits {

   432         /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */

   433         TxIFGShift	= 24,

   434         TxIFG84		= (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */

   435         TxIFG88		= (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */

   436         TxIFG92		= (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */

   437         TxIFG96		= (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */

   438 

   439 	TxLoopBack	= (1 << 18) | (1 << 17), /* enable loopback test mode */

   440 	TxCRC		= (1 << 16),	/* DISABLE Tx pkt CRC append */

   441 	TxClearAbt	= (1 << 0),	/* Clear abort (WO) */

   442 	TxDMAShift	= 8, /* DMA burst value (0-7) is shifted X many bits */

   443 	TxRetryShift	= 4, /* TXRR value (0-15) is shifted X many bits */

   444 

   445 	TxVersionMask	= 0x7C800000, /* mask out version bits 30-26, 23 */

   446 };

   447 

   448 /* Bits in Config1 */

   449 enum Config1Bits {

   450 	Cfg1_PM_Enable	= 0x01,

   451 	Cfg1_VPD_Enable	= 0x02,

   452 	Cfg1_PIO	= 0x04,

   453 	Cfg1_MMIO	= 0x08,

   454 	LWAKE		= 0x10,		/* not on 8139, 8139A */

   455 	Cfg1_Driver_Load = 0x20,

   456 	Cfg1_LED0	= 0x40,

   457 	Cfg1_LED1	= 0x80,

   458 	SLEEP		= (1 << 1),	/* only on 8139, 8139A */

   459 	PWRDN		= (1 << 0),	/* only on 8139, 8139A */

   460 };

   461 

   462 /* Bits in Config3 */

   463 enum Config3Bits {

   464 	Cfg3_FBtBEn   	= (1 << 0), /* 1	= Fast Back to Back */

   465 	Cfg3_FuncRegEn	= (1 << 1), /* 1	= enable CardBus Function registers */

   466 	Cfg3_CLKRUN_En	= (1 << 2), /* 1	= enable CLKRUN */

   467 	Cfg3_CardB_En 	= (1 << 3), /* 1	= enable CardBus registers */

   468 	Cfg3_LinkUp   	= (1 << 4), /* 1	= wake up on link up */

   469 	Cfg3_Magic    	= (1 << 5), /* 1	= wake up on Magic Packet (tm) */

   470 	Cfg3_PARM_En  	= (1 << 6), /* 0	= software can set twister parameters */

   471 	Cfg3_GNTSel   	= (1 << 7), /* 1	= delay 1 clock from PCI GNT signal */

   472 };

   473 

   474 /* Bits in Config4 */

   475 enum Config4Bits {

   476 	LWPTN	= (1 << 2),	/* not on 8139, 8139A */

   477 };

   478 

   479 /* Bits in Config5 */

   480 enum Config5Bits {

   481 	Cfg5_PME_STS   	= (1 << 0), /* 1	= PCI reset resets PME_Status */

   482 	Cfg5_LANWake   	= (1 << 1), /* 1	= enable LANWake signal */

   483 	Cfg5_LDPS      	= (1 << 2), /* 0	= save power when link is down */

   484 	Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */

   485 	Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */

   486 	Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */

   487 	Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */

   488 };

   489 

   490 enum RxConfigBits {

   491 	/* rx fifo threshold */

   492 	RxCfgFIFOShift	= 13,

   493 	RxCfgFIFONone	= (7 << RxCfgFIFOShift),

   494 

   495 	/* Max DMA burst */

   496 	RxCfgDMAShift	= 8,

   497 	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),

   498 

   499 	/* rx ring buffer length */

   500 	RxCfgRcv8K	= 0,

   501 	RxCfgRcv16K	= (1 << 11),

   502 	RxCfgRcv32K	= (1 << 12),

   503 	RxCfgRcv64K	= (1 << 11) | (1 << 12),

   504 

   505 	/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */

   506 	RxNoWrap	= (1 << 7),

   507 };

   508 

   509 /* Twister tuning parameters from RealTek.

   510    Completely undocumented, but required to tune bad links on some boards. */

   511 enum CSCRBits {

   512 	CSCR_LinkOKBit		= 0x0400,

   513 	CSCR_LinkChangeBit	= 0x0800,

   514 	CSCR_LinkStatusBits	= 0x0f000,

   515 	CSCR_LinkDownOffCmd	= 0x003c0,

   516 	CSCR_LinkDownCmd	= 0x0f3c0,

   517 };

   518 

   519 enum Cfg9346Bits {

   520 	Cfg9346_Lock	= 0x00,

   521 	Cfg9346_Unlock	= 0xC0,

   522 };

   523 

   524 typedef enum {

   525 	CH_8139	= 0,

   526 	CH_8139_K,

   527 	CH_8139A,

   528 	CH_8139A_G,

   529 	CH_8139B,

   530 	CH_8130,

   531 	CH_8139C,

   532 	CH_8100,

   533 	CH_8100B_8139D,

   534 	CH_8101,

   535 } chip_t;

   536 

   537 enum chip_flags {

   538 	HasHltClk	= (1 << 0),

   539 	HasLWake	= (1 << 1),

   540 };

   541 

   542 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \

   543 	(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)

   544 #define HW_REVID_MASK	HW_REVID(1, 1, 1, 1, 1, 1, 1)

   545 

   546 /* directly indexed by chip_t, above */

   547 static const struct {

   548 	const char *name;

   549 	u32 version; /* from RTL8139C/RTL8139D docs */

   550 	u32 flags;

   551 } rtl_chip_info[] = {

   552 	{ "RTL-8139",

   553 	  HW_REVID(1, 0, 0, 0, 0, 0, 0),

   554 	  HasHltClk,

   555 	},

   556 

   557 	{ "RTL-8139 rev K",

   558 	  HW_REVID(1, 1, 0, 0, 0, 0, 0),

   559 	  HasHltClk,

   560 	},

   561 

   562 	{ "RTL-8139A",

   563 	  HW_REVID(1, 1, 1, 0, 0, 0, 0),

   564 	  HasHltClk, /* XXX undocumented? */

   565 	},

   566 

   567 	{ "RTL-8139A rev G",

   568 	  HW_REVID(1, 1, 1, 0, 0, 1, 0),

   569 	  HasHltClk, /* XXX undocumented? */

   570 	},

   571 

   572 	{ "RTL-8139B",

   573 	  HW_REVID(1, 1, 1, 1, 0, 0, 0),

   574 	  HasLWake,

   575 	},

   576 

   577 	{ "RTL-8130",

   578 	  HW_REVID(1, 1, 1, 1, 1, 0, 0),

   579 	  HasLWake,

   580 	},

   581 

   582 	{ "RTL-8139C",

   583 	  HW_REVID(1, 1, 1, 0, 1, 0, 0),

   584 	  HasLWake,

   585 	},

   586 

   587 	{ "RTL-8100",

   588 	  HW_REVID(1, 1, 1, 1, 0, 1, 0),

   589  	  HasLWake,

   590  	},

   591 

   592 	{ "RTL-8100B/8139D",

   593 	  HW_REVID(1, 1, 1, 0, 1, 0, 1),

   594 	  HasHltClk /* XXX undocumented? */

   595 	| HasLWake,

   596 	},

   597 

   598 	{ "RTL-8101",

   599 	  HW_REVID(1, 1, 1, 0, 1, 1, 1),

   600 	  HasLWake,

   601 	},

   602 };

   603 

   604 struct rtl_extra_stats {

   605 	unsigned long early_rx;

   606 	unsigned long tx_buf_mapped;

   607 	unsigned long tx_timeouts;

   608 	unsigned long rx_lost_in_ring;

   609 };

   610 

   611 struct rtl8139_private {

   612 	void __iomem		*mmio_addr;

   613 	int			drv_flags;

   614 	struct pci_dev		*pci_dev;

   615 	u32			msg_enable;

   616 	struct napi_struct	napi;

   617 	struct net_device	*dev;

   618 

   619 	unsigned char		*rx_ring;

   620 	unsigned int		cur_rx;	/* RX buf index of next pkt */

   621 	dma_addr_t		rx_ring_dma;

   622 

   623 	unsigned int		tx_flag;

   624 	unsigned long		cur_tx;

   625 	unsigned long		dirty_tx;

   626 	unsigned char		*tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */

   627 	unsigned char		*tx_bufs;	/* Tx bounce buffer region. */

   628 	dma_addr_t		tx_bufs_dma;

   629 

   630 	signed char		phys[4];	/* MII device addresses. */

   631 

   632 				/* Twister tune state. */

   633 	char			twistie, twist_row, twist_col;

   634 

   635 	unsigned int		watchdog_fired : 1;

   636 	unsigned int		default_port : 4; /* Last dev->if_port value. */

   637 	unsigned int		have_thread : 1;

   638 

   639 	spinlock_t		lock;

   640 	spinlock_t		rx_lock;

   641 

   642 	chip_t			chipset;

   643 	u32			rx_config;

   644 	struct rtl_extra_stats	xstats;

   645 

   646 	struct delayed_work	thread;

   647 

   648 	struct mii_if_info	mii;

   649 	unsigned int		regs_len;

   650 	unsigned long		fifo_copy_timeout;

   651     

   652 	ec_device_t *ecdev;

   653 };

   654 

   655 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   656 MODULE_DESCRIPTION("RealTek RTL-8139 EtherCAT driver");

   657 MODULE_LICENSE("GPL");

   658 MODULE_VERSION(EC_MASTER_VERSION);

   659 

   660 module_param(use_io, int, 0);

   661 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");

   662 module_param(multicast_filter_limit, int, 0);

   663 module_param_array(media, int, NULL, 0);

   664 module_param_array(full_duplex, int, NULL, 0);

   665 module_param(debug, int, 0);

   666 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");

   667 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");

   668 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");

   669 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");

   670 

   671 void ec_poll(struct net_device *);

   672 

   673 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);

   674 static int rtl8139_open (struct net_device *dev);

   675 static int mdio_read (struct net_device *dev, int phy_id, int location);

   676 static void mdio_write (struct net_device *dev, int phy_id, int location,

   677 			int val);

   678 static void rtl8139_start_thread(struct rtl8139_private *tp);

   679 static void rtl8139_tx_timeout (struct net_device *dev);

   680 static void rtl8139_init_ring (struct net_device *dev);

   681 static int rtl8139_start_xmit (struct sk_buff *skb,

   682 			       struct net_device *dev);

   683 #ifdef CONFIG_NET_POLL_CONTROLLER

   684 static void rtl8139_poll_controller(struct net_device *dev);

   685 #endif

   686 static int rtl8139_set_mac_address(struct net_device *dev, void *p);

   687 static int rtl8139_poll(struct napi_struct *napi, int budget);

   688 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);

   689 static int rtl8139_close (struct net_device *dev);

   690 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);

   691 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);

   692 static void rtl8139_set_rx_mode (struct net_device *dev);

   693 static void __set_rx_mode (struct net_device *dev);

   694 static void rtl8139_hw_start (struct net_device *dev);

   695 static void rtl8139_thread (struct work_struct *work);

   696 static void rtl8139_tx_timeout_task(struct work_struct *work);

   697 static const struct ethtool_ops rtl8139_ethtool_ops;

   698 

   699 /* write MMIO register, with flush */

   700 /* Flush avoids rtl8139 bug w/ posted MMIO writes */

   701 #define RTL_W8_F(reg, val8)	do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)

   702 #define RTL_W16_F(reg, val16)	do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)

   703 #define RTL_W32_F(reg, val32)	do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)

   704 

   705 /* write MMIO register */

   706 #define RTL_W8(reg, val8)	iowrite8 ((val8), ioaddr + (reg))

   707 #define RTL_W16(reg, val16)	iowrite16 ((val16), ioaddr + (reg))

   708 #define RTL_W32(reg, val32)	iowrite32 ((val32), ioaddr + (reg))

   709 

   710 /* read MMIO register */

   711 #define RTL_R8(reg)		ioread8 (ioaddr + (reg))

   712 #define RTL_R16(reg)		ioread16 (ioaddr + (reg))

   713 #define RTL_R32(reg)		((unsigned long) ioread32 (ioaddr + (reg)))

   714 

   715 

   716 static const u16 rtl8139_intr_mask =

   717 	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |

   718 	TxErr | TxOK | RxErr | RxOK;

   719 

   720 static const u16 rtl8139_norx_intr_mask =

   721 	PCIErr | PCSTimeout | RxUnderrun |

   722 	TxErr | TxOK | RxErr ;

   723 

   724 #if RX_BUF_IDX == 0

   725 static const unsigned int rtl8139_rx_config =

   726 	RxCfgRcv8K | RxNoWrap |

   727 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   728 	(RX_DMA_BURST << RxCfgDMAShift);

   729 #elif RX_BUF_IDX == 1

   730 static const unsigned int rtl8139_rx_config =

   731 	RxCfgRcv16K | RxNoWrap |

   732 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   733 	(RX_DMA_BURST << RxCfgDMAShift);

   734 #elif RX_BUF_IDX == 2

   735 static const unsigned int rtl8139_rx_config =

   736 	RxCfgRcv32K | RxNoWrap |

   737 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   738 	(RX_DMA_BURST << RxCfgDMAShift);

   739 #elif RX_BUF_IDX == 3

   740 static const unsigned int rtl8139_rx_config =

   741 	RxCfgRcv64K |

   742 	(RX_FIFO_THRESH << RxCfgFIFOShift) |

   743 	(RX_DMA_BURST << RxCfgDMAShift);

   744 #else

   745 #error "Invalid configuration for 8139_RXBUF_IDX"

   746 #endif

   747 

   748 static const unsigned int rtl8139_tx_config =

   749 	TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);

   750 

   751 static void __rtl8139_cleanup_dev (struct net_device *dev)

   752 {

   753 	struct rtl8139_private *tp = netdev_priv(dev);

   754 	struct pci_dev *pdev;

   755 

   756 	assert (dev != NULL);

   757 	assert (tp->pci_dev != NULL);

   758 	pdev = tp->pci_dev;

   759 

   760 	if (tp->mmio_addr)

   761 		pci_iounmap (pdev, tp->mmio_addr);

   762 

   763 	/* it's ok to call this even if we have no regions to free */

   764 	pci_release_regions (pdev);

   765 

   766 	free_netdev(dev);

   767 	pci_set_drvdata (pdev, NULL);

   768 }

   769 

   770 

   771 static void rtl8139_chip_reset (void __iomem *ioaddr)

   772 {

   773 	int i;

   774 

   775 	/* Soft reset the chip. */

   776 	RTL_W8 (ChipCmd, CmdReset);

   777 

   778 	/* Check that the chip has finished the reset. */

   779 	for (i = 1000; i > 0; i--) {

   780 		barrier();

   781 		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)

   782 			break;

   783 		udelay (10);

   784 	}

   785 }

   786 

   787 

   788 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)

   789 {

   790 	void __iomem *ioaddr;

   791 	struct net_device *dev;

   792 	struct rtl8139_private *tp;

   793 	u8 tmp8;

   794 	int rc, disable_dev_on_err = 0;

   795 	unsigned int i;

   796 	unsigned long pio_start, pio_end, pio_flags, pio_len;

   797 	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;

   798 	u32 version;

   799 

   800 	assert (pdev != NULL);

   801 

   802 	/* dev and priv zeroed in alloc_etherdev */

   803 	dev = alloc_etherdev (sizeof (*tp));

   804 	if (dev == NULL) {

   805 		dev_err(&pdev->dev, "Unable to alloc new net device\n");

   806 		return ERR_PTR(-ENOMEM);

   807 	}

   808 	SET_NETDEV_DEV(dev, &pdev->dev);

   809 

   810 	tp = netdev_priv(dev);

   811 	tp->pci_dev = pdev;

   812 

   813 	/* enable device (incl. PCI PM wakeup and hotplug setup) */

   814 	rc = pci_enable_device (pdev);

   815 	if (rc)

   816 		goto err_out;

   817 

   818 	pio_start = pci_resource_start (pdev, 0);

   819 	pio_end = pci_resource_end (pdev, 0);

   820 	pio_flags = pci_resource_flags (pdev, 0);

   821 	pio_len = pci_resource_len (pdev, 0);

   822 

   823 	mmio_start = pci_resource_start (pdev, 1);

   824 	mmio_end = pci_resource_end (pdev, 1);

   825 	mmio_flags = pci_resource_flags (pdev, 1);

   826 	mmio_len = pci_resource_len (pdev, 1);

   827 

   828 	/* set this immediately, we need to know before

   829 	 * we talk to the chip directly */

   830 	pr_debug("PIO region size == 0x%02lX\n", pio_len);

   831 	pr_debug("MMIO region size == 0x%02lX\n", mmio_len);

   832 

   833 retry:

   834 	if (use_io) {

   835 		/* make sure PCI base addr 0 is PIO */

   836 		if (!(pio_flags & IORESOURCE_IO)) {

   837 			dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");

   838 			rc = -ENODEV;

   839 			goto err_out;

   840 		}

   841 		/* check for weird/broken PCI region reporting */

   842 		if (pio_len < RTL_MIN_IO_SIZE) {

   843 			dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");

   844 			rc = -ENODEV;

   845 			goto err_out;

   846 		}

   847 	} else {

   848 		/* make sure PCI base addr 1 is MMIO */

   849 		if (!(mmio_flags & IORESOURCE_MEM)) {

   850 			dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");

   851 			rc = -ENODEV;

   852 			goto err_out;

   853 		}

   854 		if (mmio_len < RTL_MIN_IO_SIZE) {

   855 			dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");

   856 			rc = -ENODEV;

   857 			goto err_out;

   858 		}

   859 	}

   860 

   861 	rc = pci_request_regions (pdev, DRV_NAME);

   862 	if (rc)

   863 		goto err_out;

   864 	disable_dev_on_err = 1;

   865 

   866 	/* enable PCI bus-mastering */

   867 	pci_set_master (pdev);

   868 

   869 	if (use_io) {

   870 		ioaddr = pci_iomap(pdev, 0, 0);

   871 		if (!ioaddr) {

   872 			dev_err(&pdev->dev, "cannot map PIO, aborting\n");

   873 			rc = -EIO;

   874 			goto err_out;

   875 		}

   876 		dev->base_addr = pio_start;

   877 		tp->regs_len = pio_len;

   878 	} else {

   879 		/* ioremap MMIO region */

   880 		ioaddr = pci_iomap(pdev, 1, 0);

   881 		if (ioaddr == NULL) {

   882 			dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");

   883 			pci_release_regions(pdev);

   884 			use_io = 1;

   885 			goto retry;

   886 		}

   887 		dev->base_addr = (long) ioaddr;

   888 		tp->regs_len = mmio_len;

   889 	}

   890 	tp->mmio_addr = ioaddr;

   891 

   892 	/* Bring old chips out of low-power mode. */

   893 	RTL_W8 (HltClk, 'R');

   894 

   895 	/* check for missing/broken hardware */

   896 	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {

   897 		dev_err(&pdev->dev, "Chip not responding, ignoring board\n");

   898 		rc = -EIO;

   899 		goto err_out;

   900 	}

   901 

   902 	/* identify chip attached to board */

   903 	version = RTL_R32 (TxConfig) & HW_REVID_MASK;

   904 	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)

   905 		if (version == rtl_chip_info[i].version) {

   906 			tp->chipset = i;

   907 			goto match;

   908 		}

   909 

   910 	/* if unknown chip, assume array element #0, original RTL-8139 in this case */

   911 	i = 0;

   912 	dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");

   913 	dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));

   914 	tp->chipset = 0;

   915 

   916 match:

   917 	pr_debug("chipset id (%d) == index %d, '%s'\n",

   918 		 version, i, rtl_chip_info[i].name);

   919 

   920 	if (tp->chipset >= CH_8139B) {

   921 		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);

   922 		pr_debug("PCI PM wakeup\n");

   923 		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&

   924 		    (tmp8 & LWAKE))

   925 			new_tmp8 &= ~LWAKE;

   926 		new_tmp8 |= Cfg1_PM_Enable;

   927 		if (new_tmp8 != tmp8) {

   928 			RTL_W8 (Cfg9346, Cfg9346_Unlock);

   929 			RTL_W8 (Config1, tmp8);

   930 			RTL_W8 (Cfg9346, Cfg9346_Lock);

   931 		}

   932 		if (rtl_chip_info[tp->chipset].flags & HasLWake) {

   933 			tmp8 = RTL_R8 (Config4);

   934 			if (tmp8 & LWPTN) {

   935 				RTL_W8 (Cfg9346, Cfg9346_Unlock);

   936 				RTL_W8 (Config4, tmp8 & ~LWPTN);

   937 				RTL_W8 (Cfg9346, Cfg9346_Lock);

   938 			}

   939 		}

   940 	} else {

   941 		pr_debug("Old chip wakeup\n");

   942 		tmp8 = RTL_R8 (Config1);

   943 		tmp8 &= ~(SLEEP | PWRDN);

   944 		RTL_W8 (Config1, tmp8);

   945 	}

   946 

   947 	rtl8139_chip_reset (ioaddr);

   948 

   949 	return dev;

   950 

   951 err_out:

   952 	__rtl8139_cleanup_dev (dev);

   953 	if (disable_dev_on_err)

   954 		pci_disable_device (pdev);

   955 	return ERR_PTR(rc);

   956 }

   957 

   958 static const struct net_device_ops rtl8139_netdev_ops = {

   959 	.ndo_open		= rtl8139_open,

   960 	.ndo_stop		= rtl8139_close,

   961 	.ndo_get_stats		= rtl8139_get_stats,

   962 	.ndo_change_mtu		= eth_change_mtu,

   963 	.ndo_validate_addr	= eth_validate_addr,

   964 	.ndo_set_mac_address 	= rtl8139_set_mac_address,

   965 	.ndo_start_xmit		= rtl8139_start_xmit,

   966 	.ndo_set_multicast_list	= rtl8139_set_rx_mode,

   967 	.ndo_do_ioctl		= netdev_ioctl,

   968 	.ndo_tx_timeout		= rtl8139_tx_timeout,

   969 #ifdef CONFIG_NET_POLL_CONTROLLER

   970 	.ndo_poll_controller	= rtl8139_poll_controller,

   971 #endif

   972 };

   973 

   974 static int __devinit rtl8139_init_one (struct pci_dev *pdev,

   975 				       const struct pci_device_id *ent)

   976 {

   977 	struct net_device *dev = NULL;

   978 	struct rtl8139_private *tp;

   979 	int i, addr_len, option;

   980 	void __iomem *ioaddr;

   981 	static int board_idx = -1;

   982 

   983 	assert (pdev != NULL);

   984 	assert (ent != NULL);

   985 

   986 	board_idx++;

   987 

   988 	/* when we're built into the kernel, the driver version message

   989 	 * is only printed if at least one 8139 board has been found

   990 	 */

   991 #ifndef MODULE

   992 	{

   993 		static int printed_version;

   994 		if (!printed_version++)

   995 			pr_info(RTL8139_DRIVER_NAME "\n");

   996 	}

   997 #endif

   998 

   999 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1000 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {

  1001 		dev_info(&pdev->dev,

  1002 			   "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",

  1003 		       	   pdev->vendor, pdev->device, pdev->revision);

  1004 		return -ENODEV;

  1005 	}

  1006 

  1007 	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&

  1008 	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&

  1009 	    pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&

  1010 	    pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {

  1011 		pr_info("8139too: OQO Model 2 detected. Forcing PIO\n");

  1012 		use_io = 1;

  1013 	}

  1014 

  1015 	dev = rtl8139_init_board (pdev);

  1016 	if (IS_ERR(dev))

  1017 		return PTR_ERR(dev);

  1018 

  1019 	assert (dev != NULL);

  1020 	tp = netdev_priv(dev);

  1021 	tp->dev = dev;

  1022 

  1023 	ioaddr = tp->mmio_addr;

  1024 	assert (ioaddr != NULL);

  1025 

  1026 	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;

  1027 	for (i = 0; i < 3; i++)

  1028 		((__le16 *) (dev->dev_addr))[i] =

  1029 		    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));

  1030 	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);

  1031 

  1032 	/* The Rtl8139-specific entries in the device structure. */

  1033 	dev->netdev_ops = &rtl8139_netdev_ops;

  1034 	dev->ethtool_ops = &rtl8139_ethtool_ops;

  1035 	dev->watchdog_timeo = TX_TIMEOUT;

  1036 	netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);

  1037 

  1038 	/* note: the hardware is not capable of sg/csum/highdma, however

  1039 	 * through the use of skb_copy_and_csum_dev we enable these

  1040 	 * features

  1041 	 */

  1042 	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;

  1043 

  1044 	dev->irq = pdev->irq;

  1045 

  1046 	/* tp zeroed and aligned in alloc_etherdev */

  1047 	tp = netdev_priv(dev);

  1048 

  1049 	/* note: tp->chipset set in rtl8139_init_board */

  1050 	tp->drv_flags = board_info[ent->driver_data].hw_flags;

  1051 	tp->mmio_addr = ioaddr;

  1052 	tp->msg_enable =

  1053 		(debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));

  1054 	spin_lock_init (&tp->lock);

  1055 	spin_lock_init (&tp->rx_lock);

  1056 	INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);

  1057 	tp->mii.dev = dev;

  1058 	tp->mii.mdio_read = mdio_read;

  1059 	tp->mii.mdio_write = mdio_write;

  1060 	tp->mii.phy_id_mask = 0x3f;

  1061 	tp->mii.reg_num_mask = 0x1f;

  1062 

  1063 	/* dev is fully set up and ready to use now */

  1064 	// offer device to EtherCAT master module

  1065 	tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE);

  1066 

  1067 	if (!tp->ecdev) {

  1068 		pr_debug("about to register device named %s (%p)...\n", dev->name, dev);

  1069 		i = register_netdev (dev);

  1070 		if (i) goto err_out;

  1071 	}

  1072 

  1073 	pci_set_drvdata (pdev, dev);

  1074 

  1075 	pr_info("%s: %s at 0x%lx, %pM, IRQ %d\n",

  1076 		dev->name,

  1077 		board_info[ent->driver_data].name,

  1078 		dev->base_addr,

  1079 		dev->dev_addr,

  1080 		dev->irq);

  1081 

  1082 	pr_debug("%s:  Identified 8139 chip type '%s'\n",

  1083 		dev->name, rtl_chip_info[tp->chipset].name);

  1084 

  1085 	/* Find the connected MII xcvrs.

  1086 	   Doing this in open() would allow detecting external xcvrs later, but

  1087 	   takes too much time. */

  1088 #ifdef CONFIG_8139TOO_8129

  1089 	if (tp->drv_flags & HAS_MII_XCVR) {

  1090 		int phy, phy_idx = 0;

  1091 		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

  1092 			int mii_status = mdio_read(dev, phy, 1);

  1093 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {

  1094 				u16 advertising = mdio_read(dev, phy, 4);

  1095 				tp->phys[phy_idx++] = phy;

  1096 				pr_info("%s: MII transceiver %d status 0x%4.4x advertising %4.4x.\n",

  1097 					   dev->name, phy, mii_status, advertising);

  1098 			}

  1099 		}

  1100 		if (phy_idx == 0) {

  1101 			pr_info("%s: No MII transceivers found! Assuming SYM transceiver.\n",

  1102 				   dev->name);

  1103 			tp->phys[0] = 32;

  1104 		}

  1105 	} else

  1106 #endif

  1107 		tp->phys[0] = 32;

  1108 	tp->mii.phy_id = tp->phys[0];

  1109 

  1110 	/* The lower four bits are the media type. */

  1111 	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];

  1112 	if (option > 0) {

  1113 		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;

  1114 		tp->default_port = option & 0xFF;

  1115 		if (tp->default_port)

  1116 			tp->mii.force_media = 1;

  1117 	}

  1118 	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)

  1119 		tp->mii.full_duplex = full_duplex[board_idx];

  1120 	if (tp->mii.full_duplex) {

  1121 		pr_info("%s: Media type forced to Full Duplex.\n", dev->name);

  1122 		/* Changing the MII-advertised media because might prevent

  1123 		   re-connection. */

  1124 		tp->mii.force_media = 1;

  1125 	}

  1126 	if (tp->default_port) {

  1127 		pr_info("  Forcing %dMbps %s-duplex operation.\n",

  1128 			   (option & 0x20 ? 100 : 10),

  1129 			   (option & 0x10 ? "full" : "half"));

  1130 		mdio_write(dev, tp->phys[0], 0,

  1131 				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */

  1132 				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */

  1133 	}

  1134 

  1135 	/* Put the chip into low-power mode. */