1 /* |
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2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. |
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3 * |
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4 * Note: This driver is a cleanroom reimplementation based on reverse |
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5 * engineered documentation written by Carl-Daniel Hailfinger |
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6 * and Andrew de Quincey. It's neither supported nor endorsed |
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7 * by NVIDIA Corp. Use at your own risk. |
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8 * |
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9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered |
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10 * trademarks of NVIDIA Corporation in the United States and other |
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11 * countries. |
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12 * |
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13 * Copyright (C) 2003,4,5 Manfred Spraul |
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14 * Copyright (C) 2004 Andrew de Quincey (wol support) |
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15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane |
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16 * IRQ rate fixes, bigendian fixes, cleanups, verification) |
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17 * Copyright (c) 2004 NVIDIA Corporation |
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18 * |
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19 * This program is free software; you can redistribute it and/or modify |
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20 * it under the terms of the GNU General Public License as published by |
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21 * the Free Software Foundation; either version 2 of the License, or |
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22 * (at your option) any later version. |
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23 * |
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24 * This program is distributed in the hope that it will be useful, |
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25 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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27 * GNU General Public License for more details. |
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28 * |
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29 * You should have received a copy of the GNU General Public License |
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30 * along with this program; if not, write to the Free Software |
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31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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32 * |
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33 * Changelog: |
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34 * 0.01: 05 Oct 2003: First release that compiles without warnings. |
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35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. |
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36 * Check all PCI BARs for the register window. |
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37 * udelay added to mii_rw. |
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38 * 0.03: 06 Oct 2003: Initialize dev->irq. |
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39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. |
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40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. |
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41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, |
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42 * irq mask updated |
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43 * 0.07: 14 Oct 2003: Further irq mask updates. |
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44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill |
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45 * added into irq handler, NULL check for drain_ring. |
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46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the |
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47 * requested interrupt sources. |
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48 * 0.10: 20 Oct 2003: First cleanup for release. |
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49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. |
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50 * MAC Address init fix, set_multicast cleanup. |
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51 * 0.12: 23 Oct 2003: Cleanups for release. |
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52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. |
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53 * Set link speed correctly. start rx before starting |
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54 * tx (nv_start_rx sets the link speed). |
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55 * 0.14: 25 Oct 2003: Nic dependant irq mask. |
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56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during |
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57 * open. |
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58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size |
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59 * increased to 1628 bytes. |
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60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from |
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61 * the tx length. |
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62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats |
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63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac |
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64 * addresses, really stop rx if already running |
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65 * in nv_start_rx, clean up a bit. |
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66 * 0.20: 07 Dec 2003: alloc fixes |
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67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. |
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68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup |
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69 * on close. |
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70 * 0.23: 26 Jan 2004: various small cleanups |
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71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces |
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72 * 0.25: 09 Mar 2004: wol support |
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73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes |
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74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, |
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75 * added CK804/MCP04 device IDs, code fixes |
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76 * for registers, link status and other minor fixes. |
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77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe |
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78 * 0.29: 31 Aug 2004: Add backup timer for link change notification. |
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79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset |
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80 * into nv_close, otherwise reenabling for wol can |
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81 * cause DMA to kfree'd memory. |
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82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link |
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83 * capabilities. |
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84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added. |
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85 * 0.33: 16 May 2005: Support for MCP51 added. |
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86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. |
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87 * 0.35: 26 Jun 2005: Support for MCP55 added. |
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88 * 0.36: 28 Jun 2005: Add jumbo frame support. |
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89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list |
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90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of |
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91 * per-packet flags. |
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92 * 0.39: 18 Jul 2005: Add 64bit descriptor support. |
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93 * 0.40: 19 Jul 2005: Add support for mac address change. |
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94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead |
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95 * of nv_remove |
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96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
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97 * in the second (and later) nv_open call |
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98 * 0.43: 10 Aug 2005: Add support for tx checksum. |
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99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. |
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100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check |
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101 * 0.46: 20 Oct 2005: Add irq optimization modes. |
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102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. |
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103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single |
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104 * 0.49: 10 Dec 2005: Fix tso for large buffers. |
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105 * 0.50: 20 Jan 2006: Add 8021pq tagging support. |
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106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. |
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107 * 0.52: 20 Jan 2006: Add MSI/MSIX support. |
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108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
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109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
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110 * 0.55: 22 Mar 2006: Add flow control (pause frame). |
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111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support. |
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112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections. |
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113 * |
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114 * Known bugs: |
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115 * We suspect that on some hardware no TX done interrupts are generated. |
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116 * This means recovery from netif_stop_queue only happens if the hw timer |
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117 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) |
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118 * and the timer is active in the IRQMask, or if a rx packet arrives by chance. |
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119 * If your hardware reliably generates tx done interrupts, then you can remove |
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120 * DEV_NEED_TIMERIRQ from the driver_data flags. |
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121 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
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122 * superfluous timer interrupts from the nic. |
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123 */ |
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124 #ifdef CONFIG_FORCEDETH_NAPI |
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125 #define DRIVERNAPI "-NAPI" |
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126 #else |
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127 #define DRIVERNAPI |
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128 #endif |
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129 #define FORCEDETH_VERSION "0.57" |
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130 #define DRV_NAME "forcedeth" |
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131 |
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132 #include <linux/module.h> |
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133 #include <linux/types.h> |
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134 #include <linux/pci.h> |
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135 #include <linux/interrupt.h> |
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136 #include <linux/netdevice.h> |
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137 #include <linux/etherdevice.h> |
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138 #include <linux/delay.h> |
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139 #include <linux/spinlock.h> |
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140 #include <linux/ethtool.h> |
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141 #include <linux/timer.h> |
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142 #include <linux/skbuff.h> |
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143 #include <linux/mii.h> |
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144 #include <linux/random.h> |
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145 #include <linux/init.h> |
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146 #include <linux/if_vlan.h> |
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147 #include <linux/dma-mapping.h> |
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148 |
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149 #include <asm/irq.h> |
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150 #include <asm/io.h> |
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151 #include <asm/uaccess.h> |
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152 #include <asm/system.h> |
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153 |
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154 #if 0 |
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155 #define dprintk printk |
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156 #else |
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157 #define dprintk(x...) do { } while (0) |
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158 #endif |
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159 |
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160 |
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161 /* |
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162 * Hardware access: |
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163 */ |
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164 |
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165 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */ |
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166 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ |
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167 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ |
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168 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
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169 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ |
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170 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */ |
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171 #define DEV_HAS_MSI 0x0040 /* device supports MSI */ |
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172 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */ |
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173 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */ |
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174 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */ |
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175 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */ |
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176 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */ |
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177 |
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178 enum { |
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179 NvRegIrqStatus = 0x000, |
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180 #define NVREG_IRQSTAT_MIIEVENT 0x040 |
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181 #define NVREG_IRQSTAT_MASK 0x1ff |
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182 NvRegIrqMask = 0x004, |
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183 #define NVREG_IRQ_RX_ERROR 0x0001 |
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184 #define NVREG_IRQ_RX 0x0002 |
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185 #define NVREG_IRQ_RX_NOBUF 0x0004 |
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186 #define NVREG_IRQ_TX_ERR 0x0008 |
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187 #define NVREG_IRQ_TX_OK 0x0010 |
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188 #define NVREG_IRQ_TIMER 0x0020 |
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189 #define NVREG_IRQ_LINK 0x0040 |
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190 #define NVREG_IRQ_RX_FORCED 0x0080 |
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191 #define NVREG_IRQ_TX_FORCED 0x0100 |
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192 #define NVREG_IRQMASK_THROUGHPUT 0x00df |
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193 #define NVREG_IRQMASK_CPU 0x0040 |
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194 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
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195 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) |
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196 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) |
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197 |
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198 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ |
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199 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
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200 NVREG_IRQ_TX_FORCED)) |
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201 |
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202 NvRegUnknownSetupReg6 = 0x008, |
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203 #define NVREG_UNKSETUP6_VAL 3 |
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204 |
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205 /* |
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206 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic |
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207 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms |
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208 */ |
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209 NvRegPollingInterval = 0x00c, |
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210 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 |
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211 #define NVREG_POLL_DEFAULT_CPU 13 |
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212 NvRegMSIMap0 = 0x020, |
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213 NvRegMSIMap1 = 0x024, |
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214 NvRegMSIIrqMask = 0x030, |
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215 #define NVREG_MSI_VECTOR_0_ENABLED 0x01 |
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216 NvRegMisc1 = 0x080, |
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217 #define NVREG_MISC1_PAUSE_TX 0x01 |
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218 #define NVREG_MISC1_HD 0x02 |
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219 #define NVREG_MISC1_FORCE 0x3b0f3c |
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220 |
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221 NvRegMacReset = 0x3c, |
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222 #define NVREG_MAC_RESET_ASSERT 0x0F3 |
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223 NvRegTransmitterControl = 0x084, |
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224 #define NVREG_XMITCTL_START 0x01 |
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225 NvRegTransmitterStatus = 0x088, |
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226 #define NVREG_XMITSTAT_BUSY 0x01 |
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227 |
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228 NvRegPacketFilterFlags = 0x8c, |
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229 #define NVREG_PFF_PAUSE_RX 0x08 |
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230 #define NVREG_PFF_ALWAYS 0x7F0000 |
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231 #define NVREG_PFF_PROMISC 0x80 |
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232 #define NVREG_PFF_MYADDR 0x20 |
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233 #define NVREG_PFF_LOOPBACK 0x10 |
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234 |
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235 NvRegOffloadConfig = 0x90, |
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236 #define NVREG_OFFLOAD_HOMEPHY 0x601 |
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237 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
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238 NvRegReceiverControl = 0x094, |
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239 #define NVREG_RCVCTL_START 0x01 |
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240 NvRegReceiverStatus = 0x98, |
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241 #define NVREG_RCVSTAT_BUSY 0x01 |
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242 |
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243 NvRegRandomSeed = 0x9c, |
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244 #define NVREG_RNDSEED_MASK 0x00ff |
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245 #define NVREG_RNDSEED_FORCE 0x7f00 |
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246 #define NVREG_RNDSEED_FORCE2 0x2d00 |
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247 #define NVREG_RNDSEED_FORCE3 0x7400 |
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248 |
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249 NvRegTxDeferral = 0xA0, |
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250 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
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251 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f |
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252 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f |
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253 NvRegRxDeferral = 0xA4, |
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254 #define NVREG_RX_DEFERRAL_DEFAULT 0x16 |
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255 NvRegMacAddrA = 0xA8, |
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256 NvRegMacAddrB = 0xAC, |
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257 NvRegMulticastAddrA = 0xB0, |
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258 #define NVREG_MCASTADDRA_FORCE 0x01 |
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259 NvRegMulticastAddrB = 0xB4, |
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260 NvRegMulticastMaskA = 0xB8, |
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261 NvRegMulticastMaskB = 0xBC, |
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262 |
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263 NvRegPhyInterface = 0xC0, |
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264 #define PHY_RGMII 0x10000000 |
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265 |
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266 NvRegTxRingPhysAddr = 0x100, |
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267 NvRegRxRingPhysAddr = 0x104, |
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268 NvRegRingSizes = 0x108, |
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269 #define NVREG_RINGSZ_TXSHIFT 0 |
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270 #define NVREG_RINGSZ_RXSHIFT 16 |
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271 NvRegTransmitPoll = 0x10c, |
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272 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 |
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273 NvRegLinkSpeed = 0x110, |
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274 #define NVREG_LINKSPEED_FORCE 0x10000 |
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275 #define NVREG_LINKSPEED_10 1000 |
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276 #define NVREG_LINKSPEED_100 100 |
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277 #define NVREG_LINKSPEED_1000 50 |
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278 #define NVREG_LINKSPEED_MASK (0xFFF) |
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279 NvRegUnknownSetupReg5 = 0x130, |
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280 #define NVREG_UNKSETUP5_BIT31 (1<<31) |
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281 NvRegTxWatermark = 0x13c, |
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282 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 |
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283 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 |
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284 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 |
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285 NvRegTxRxControl = 0x144, |
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286 #define NVREG_TXRXCTL_KICK 0x0001 |
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287 #define NVREG_TXRXCTL_BIT1 0x0002 |
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288 #define NVREG_TXRXCTL_BIT2 0x0004 |
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289 #define NVREG_TXRXCTL_IDLE 0x0008 |
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290 #define NVREG_TXRXCTL_RESET 0x0010 |
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291 #define NVREG_TXRXCTL_RXCHECK 0x0400 |
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292 #define NVREG_TXRXCTL_DESC_1 0 |
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293 #define NVREG_TXRXCTL_DESC_2 0x02100 |
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294 #define NVREG_TXRXCTL_DESC_3 0x02200 |
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295 #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
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296 #define NVREG_TXRXCTL_VLANINS 0x00080 |
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297 NvRegTxRingPhysAddrHigh = 0x148, |
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298 NvRegRxRingPhysAddrHigh = 0x14C, |
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299 NvRegTxPauseFrame = 0x170, |
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300 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080 |
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301 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030 |
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302 NvRegMIIStatus = 0x180, |
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303 #define NVREG_MIISTAT_ERROR 0x0001 |
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304 #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
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305 #define NVREG_MIISTAT_MASK 0x000f |
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306 #define NVREG_MIISTAT_MASK2 0x000f |
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307 NvRegUnknownSetupReg4 = 0x184, |
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308 #define NVREG_UNKSETUP4_VAL 8 |
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309 |
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310 NvRegAdapterControl = 0x188, |
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311 #define NVREG_ADAPTCTL_START 0x02 |
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312 #define NVREG_ADAPTCTL_LINKUP 0x04 |
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313 #define NVREG_ADAPTCTL_PHYVALID 0x40000 |
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314 #define NVREG_ADAPTCTL_RUNNING 0x100000 |
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315 #define NVREG_ADAPTCTL_PHYSHIFT 24 |
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316 NvRegMIISpeed = 0x18c, |
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317 #define NVREG_MIISPEED_BIT8 (1<<8) |
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318 #define NVREG_MIIDELAY 5 |
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319 NvRegMIIControl = 0x190, |
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320 #define NVREG_MIICTL_INUSE 0x08000 |
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321 #define NVREG_MIICTL_WRITE 0x00400 |
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322 #define NVREG_MIICTL_ADDRSHIFT 5 |
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323 NvRegMIIData = 0x194, |
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324 NvRegWakeUpFlags = 0x200, |
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325 #define NVREG_WAKEUPFLAGS_VAL 0x7770 |
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326 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 |
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327 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 |
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328 #define NVREG_WAKEUPFLAGS_D3SHIFT 12 |
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329 #define NVREG_WAKEUPFLAGS_D2SHIFT 8 |
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330 #define NVREG_WAKEUPFLAGS_D1SHIFT 4 |
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331 #define NVREG_WAKEUPFLAGS_D0SHIFT 0 |
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332 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 |
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333 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 |
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334 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 |
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335 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
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336 |
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337 NvRegPatternCRC = 0x204, |
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338 NvRegPatternMask = 0x208, |
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339 NvRegPowerCap = 0x268, |
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340 #define NVREG_POWERCAP_D3SUPP (1<<30) |
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341 #define NVREG_POWERCAP_D2SUPP (1<<26) |
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342 #define NVREG_POWERCAP_D1SUPP (1<<25) |
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343 NvRegPowerState = 0x26c, |
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344 #define NVREG_POWERSTATE_POWEREDUP 0x8000 |
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345 #define NVREG_POWERSTATE_VALID 0x0100 |
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346 #define NVREG_POWERSTATE_MASK 0x0003 |
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347 #define NVREG_POWERSTATE_D0 0x0000 |
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348 #define NVREG_POWERSTATE_D1 0x0001 |
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349 #define NVREG_POWERSTATE_D2 0x0002 |
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350 #define NVREG_POWERSTATE_D3 0x0003 |
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351 NvRegTxCnt = 0x280, |
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352 NvRegTxZeroReXmt = 0x284, |
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353 NvRegTxOneReXmt = 0x288, |
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354 NvRegTxManyReXmt = 0x28c, |
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355 NvRegTxLateCol = 0x290, |
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356 NvRegTxUnderflow = 0x294, |
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357 NvRegTxLossCarrier = 0x298, |
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358 NvRegTxExcessDef = 0x29c, |
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359 NvRegTxRetryErr = 0x2a0, |
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360 NvRegRxFrameErr = 0x2a4, |
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361 NvRegRxExtraByte = 0x2a8, |
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362 NvRegRxLateCol = 0x2ac, |
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363 NvRegRxRunt = 0x2b0, |
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364 NvRegRxFrameTooLong = 0x2b4, |
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365 NvRegRxOverflow = 0x2b8, |
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366 NvRegRxFCSErr = 0x2bc, |
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367 NvRegRxFrameAlignErr = 0x2c0, |
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368 NvRegRxLenErr = 0x2c4, |
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369 NvRegRxUnicast = 0x2c8, |
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370 NvRegRxMulticast = 0x2cc, |
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371 NvRegRxBroadcast = 0x2d0, |
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372 NvRegTxDef = 0x2d4, |
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373 NvRegTxFrame = 0x2d8, |
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374 NvRegRxCnt = 0x2dc, |
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375 NvRegTxPause = 0x2e0, |
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376 NvRegRxPause = 0x2e4, |
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377 NvRegRxDropFrame = 0x2e8, |
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378 NvRegVlanControl = 0x300, |
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379 #define NVREG_VLANCONTROL_ENABLE 0x2000 |
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380 NvRegMSIXMap0 = 0x3e0, |
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381 NvRegMSIXMap1 = 0x3e4, |
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382 NvRegMSIXIrqStatus = 0x3f0, |
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383 |
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384 NvRegPowerState2 = 0x600, |
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385 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 |
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386 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
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387 }; |
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388 |
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389 /* Big endian: should work, but is untested */ |
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390 struct ring_desc { |
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391 __le32 buf; |
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392 __le32 flaglen; |
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393 }; |
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394 |
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395 struct ring_desc_ex { |
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396 __le32 bufhigh; |
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397 __le32 buflow; |
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398 __le32 txvlan; |
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399 __le32 flaglen; |
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400 }; |
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401 |
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402 union ring_type { |
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403 struct ring_desc* orig; |
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404 struct ring_desc_ex* ex; |
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405 }; |
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406 |
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407 #define FLAG_MASK_V1 0xffff0000 |
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408 #define FLAG_MASK_V2 0xffffc000 |
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409 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) |
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410 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) |
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411 |
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412 #define NV_TX_LASTPACKET (1<<16) |
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413 #define NV_TX_RETRYERROR (1<<19) |
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414 #define NV_TX_FORCED_INTERRUPT (1<<24) |
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415 #define NV_TX_DEFERRED (1<<26) |
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416 #define NV_TX_CARRIERLOST (1<<27) |
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417 #define NV_TX_LATECOLLISION (1<<28) |
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418 #define NV_TX_UNDERFLOW (1<<29) |
|
419 #define NV_TX_ERROR (1<<30) |
|
420 #define NV_TX_VALID (1<<31) |
|
421 |
|
422 #define NV_TX2_LASTPACKET (1<<29) |
|
423 #define NV_TX2_RETRYERROR (1<<18) |
|
424 #define NV_TX2_FORCED_INTERRUPT (1<<30) |
|
425 #define NV_TX2_DEFERRED (1<<25) |
|
426 #define NV_TX2_CARRIERLOST (1<<26) |
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427 #define NV_TX2_LATECOLLISION (1<<27) |
|
428 #define NV_TX2_UNDERFLOW (1<<28) |
|
429 /* error and valid are the same for both */ |
|
430 #define NV_TX2_ERROR (1<<30) |
|
431 #define NV_TX2_VALID (1<<31) |
|
432 #define NV_TX2_TSO (1<<28) |
|
433 #define NV_TX2_TSO_SHIFT 14 |
|
434 #define NV_TX2_TSO_MAX_SHIFT 14 |
|
435 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) |
|
436 #define NV_TX2_CHECKSUM_L3 (1<<27) |
|
437 #define NV_TX2_CHECKSUM_L4 (1<<26) |
|
438 |
|
439 #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
|
440 |
|
441 #define NV_RX_DESCRIPTORVALID (1<<16) |
|
442 #define NV_RX_MISSEDFRAME (1<<17) |
|
443 #define NV_RX_SUBSTRACT1 (1<<18) |
|
444 #define NV_RX_ERROR1 (1<<23) |
|
445 #define NV_RX_ERROR2 (1<<24) |
|
446 #define NV_RX_ERROR3 (1<<25) |
|
447 #define NV_RX_ERROR4 (1<<26) |
|
448 #define NV_RX_CRCERR (1<<27) |
|
449 #define NV_RX_OVERFLOW (1<<28) |
|
450 #define NV_RX_FRAMINGERR (1<<29) |
|
451 #define NV_RX_ERROR (1<<30) |
|
452 #define NV_RX_AVAIL (1<<31) |
|
453 |
|
454 #define NV_RX2_CHECKSUMMASK (0x1C000000) |
|
455 #define NV_RX2_CHECKSUMOK1 (0x10000000) |
|
456 #define NV_RX2_CHECKSUMOK2 (0x14000000) |
|
457 #define NV_RX2_CHECKSUMOK3 (0x18000000) |
|
458 #define NV_RX2_DESCRIPTORVALID (1<<29) |
|
459 #define NV_RX2_SUBSTRACT1 (1<<25) |
|
460 #define NV_RX2_ERROR1 (1<<18) |
|
461 #define NV_RX2_ERROR2 (1<<19) |
|
462 #define NV_RX2_ERROR3 (1<<20) |
|
463 #define NV_RX2_ERROR4 (1<<21) |
|
464 #define NV_RX2_CRCERR (1<<22) |
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465 #define NV_RX2_OVERFLOW (1<<23) |
|
466 #define NV_RX2_FRAMINGERR (1<<24) |
|
467 /* error and avail are the same for both */ |
|
468 #define NV_RX2_ERROR (1<<30) |
|
469 #define NV_RX2_AVAIL (1<<31) |
|
470 |
|
471 #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
|
472 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) |
|
473 |
|
474 /* Miscelaneous hardware related defines: */ |
|
475 #define NV_PCI_REGSZ_VER1 0x270 |
|
476 #define NV_PCI_REGSZ_VER2 0x604 |
|
477 |
|
478 /* various timeout delays: all in usec */ |
|
479 #define NV_TXRX_RESET_DELAY 4 |
|
480 #define NV_TXSTOP_DELAY1 10 |
|
481 #define NV_TXSTOP_DELAY1MAX 500000 |
|
482 #define NV_TXSTOP_DELAY2 100 |
|
483 #define NV_RXSTOP_DELAY1 10 |
|
484 #define NV_RXSTOP_DELAY1MAX 500000 |
|
485 #define NV_RXSTOP_DELAY2 100 |
|
486 #define NV_SETUP5_DELAY 5 |
|
487 #define NV_SETUP5_DELAYMAX 50000 |
|
488 #define NV_POWERUP_DELAY 5 |
|
489 #define NV_POWERUP_DELAYMAX 5000 |
|
490 #define NV_MIIBUSY_DELAY 50 |
|
491 #define NV_MIIPHY_DELAY 10 |
|
492 #define NV_MIIPHY_DELAYMAX 10000 |
|
493 #define NV_MAC_RESET_DELAY 64 |
|
494 |
|
495 #define NV_WAKEUPPATTERNS 5 |
|
496 #define NV_WAKEUPMASKENTRIES 4 |
|
497 |
|
498 /* General driver defaults */ |
|
499 #define NV_WATCHDOG_TIMEO (5*HZ) |
|
500 |
|
501 #define RX_RING_DEFAULT 128 |
|
502 #define TX_RING_DEFAULT 256 |
|
503 #define RX_RING_MIN 128 |
|
504 #define TX_RING_MIN 64 |
|
505 #define RING_MAX_DESC_VER_1 1024 |
|
506 #define RING_MAX_DESC_VER_2_3 16384 |
|
507 /* |
|
508 * Difference between the get and put pointers for the tx ring. |
|
509 * This is used to throttle the amount of data outstanding in the |
|
510 * tx ring. |
|
511 */ |
|
512 #define TX_LIMIT_DIFFERENCE 1 |
|
513 |
|
514 /* rx/tx mac addr + type + vlan + align + slack*/ |
|
515 #define NV_RX_HEADERS (64) |
|
516 /* even more slack. */ |
|
517 #define NV_RX_ALLOC_PAD (64) |
|
518 |
|
519 /* maximum mtu size */ |
|
520 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ |
|
521 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ |
|
522 |
|
523 #define OOM_REFILL (1+HZ/20) |
|
524 #define POLL_WAIT (1+HZ/100) |
|
525 #define LINK_TIMEOUT (3*HZ) |
|
526 #define STATS_INTERVAL (10*HZ) |
|
527 |
|
528 /* |
|
529 * desc_ver values: |
|
530 * The nic supports three different descriptor types: |
|
531 * - DESC_VER_1: Original |
|
532 * - DESC_VER_2: support for jumbo frames. |
|
533 * - DESC_VER_3: 64-bit format. |
|
534 */ |
|
535 #define DESC_VER_1 1 |
|
536 #define DESC_VER_2 2 |
|
537 #define DESC_VER_3 3 |
|
538 |
|
539 /* PHY defines */ |
|
540 #define PHY_OUI_MARVELL 0x5043 |
|
541 #define PHY_OUI_CICADA 0x03f1 |
|
542 #define PHYID1_OUI_MASK 0x03ff |
|
543 #define PHYID1_OUI_SHFT 6 |
|
544 #define PHYID2_OUI_MASK 0xfc00 |
|
545 #define PHYID2_OUI_SHFT 10 |
|
546 #define PHYID2_MODEL_MASK 0x03f0 |
|
547 #define PHY_MODEL_MARVELL_E3016 0x220 |
|
548 #define PHY_MARVELL_E3016_INITMASK 0x0300 |
|
549 #define PHY_INIT1 0x0f000 |
|
550 #define PHY_INIT2 0x0e00 |
|
551 #define PHY_INIT3 0x01000 |
|
552 #define PHY_INIT4 0x0200 |
|
553 #define PHY_INIT5 0x0004 |
|
554 #define PHY_INIT6 0x02000 |
|
555 #define PHY_GIGABIT 0x0100 |
|
556 |
|
557 #define PHY_TIMEOUT 0x1 |
|
558 #define PHY_ERROR 0x2 |
|
559 |
|
560 #define PHY_100 0x1 |
|
561 #define PHY_1000 0x2 |
|
562 #define PHY_HALF 0x100 |
|
563 |
|
564 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
|
565 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 |
|
566 #define NV_PAUSEFRAME_RX_ENABLE 0x0004 |
|
567 #define NV_PAUSEFRAME_TX_ENABLE 0x0008 |
|
568 #define NV_PAUSEFRAME_RX_REQ 0x0010 |
|
569 #define NV_PAUSEFRAME_TX_REQ 0x0020 |
|
570 #define NV_PAUSEFRAME_AUTONEG 0x0040 |
|
571 |
|
572 /* MSI/MSI-X defines */ |
|
573 #define NV_MSI_X_MAX_VECTORS 8 |
|
574 #define NV_MSI_X_VECTORS_MASK 0x000f |
|
575 #define NV_MSI_CAPABLE 0x0010 |
|
576 #define NV_MSI_X_CAPABLE 0x0020 |
|
577 #define NV_MSI_ENABLED 0x0040 |
|
578 #define NV_MSI_X_ENABLED 0x0080 |
|
579 |
|
580 #define NV_MSI_X_VECTOR_ALL 0x0 |
|
581 #define NV_MSI_X_VECTOR_RX 0x0 |
|
582 #define NV_MSI_X_VECTOR_TX 0x1 |
|
583 #define NV_MSI_X_VECTOR_OTHER 0x2 |
|
584 |
|
585 /* statistics */ |
|
586 struct nv_ethtool_str { |
|
587 char name[ETH_GSTRING_LEN]; |
|
588 }; |
|
589 |
|
590 static const struct nv_ethtool_str nv_estats_str[] = { |
|
591 { "tx_bytes" }, |
|
592 { "tx_zero_rexmt" }, |
|
593 { "tx_one_rexmt" }, |
|
594 { "tx_many_rexmt" }, |
|
595 { "tx_late_collision" }, |
|
596 { "tx_fifo_errors" }, |
|
597 { "tx_carrier_errors" }, |
|
598 { "tx_excess_deferral" }, |
|
599 { "tx_retry_error" }, |
|
600 { "tx_deferral" }, |
|
601 { "tx_packets" }, |
|
602 { "tx_pause" }, |
|
603 { "rx_frame_error" }, |
|
604 { "rx_extra_byte" }, |
|
605 { "rx_late_collision" }, |
|
606 { "rx_runt" }, |
|
607 { "rx_frame_too_long" }, |
|
608 { "rx_over_errors" }, |
|
609 { "rx_crc_errors" }, |
|
610 { "rx_frame_align_error" }, |
|
611 { "rx_length_error" }, |
|
612 { "rx_unicast" }, |
|
613 { "rx_multicast" }, |
|
614 { "rx_broadcast" }, |
|
615 { "rx_bytes" }, |
|
616 { "rx_pause" }, |
|
617 { "rx_drop_frame" }, |
|
618 { "rx_packets" }, |
|
619 { "rx_errors_total" } |
|
620 }; |
|
621 |
|
622 struct nv_ethtool_stats { |
|
623 u64 tx_bytes; |
|
624 u64 tx_zero_rexmt; |
|
625 u64 tx_one_rexmt; |
|
626 u64 tx_many_rexmt; |
|
627 u64 tx_late_collision; |
|
628 u64 tx_fifo_errors; |
|
629 u64 tx_carrier_errors; |
|
630 u64 tx_excess_deferral; |
|
631 u64 tx_retry_error; |
|
632 u64 tx_deferral; |
|
633 u64 tx_packets; |
|
634 u64 tx_pause; |
|
635 u64 rx_frame_error; |
|
636 u64 rx_extra_byte; |
|
637 u64 rx_late_collision; |
|
638 u64 rx_runt; |
|
639 u64 rx_frame_too_long; |
|
640 u64 rx_over_errors; |
|
641 u64 rx_crc_errors; |
|
642 u64 rx_frame_align_error; |
|
643 u64 rx_length_error; |
|
644 u64 rx_unicast; |
|
645 u64 rx_multicast; |
|
646 u64 rx_broadcast; |
|
647 u64 rx_bytes; |
|
648 u64 rx_pause; |
|
649 u64 rx_drop_frame; |
|
650 u64 rx_packets; |
|
651 u64 rx_errors_total; |
|
652 }; |
|
653 |
|
654 /* diagnostics */ |
|
655 #define NV_TEST_COUNT_BASE 3 |
|
656 #define NV_TEST_COUNT_EXTENDED 4 |
|
657 |
|
658 static const struct nv_ethtool_str nv_etests_str[] = { |
|
659 { "link (online/offline)" }, |
|
660 { "register (offline) " }, |
|
661 { "interrupt (offline) " }, |
|
662 { "loopback (offline) " } |
|
663 }; |
|
664 |
|
665 struct register_test { |
|
666 __le32 reg; |
|
667 __le32 mask; |
|
668 }; |
|
669 |
|
670 static const struct register_test nv_registers_test[] = { |
|
671 { NvRegUnknownSetupReg6, 0x01 }, |
|
672 { NvRegMisc1, 0x03c }, |
|
673 { NvRegOffloadConfig, 0x03ff }, |
|
674 { NvRegMulticastAddrA, 0xffffffff }, |
|
675 { NvRegTxWatermark, 0x0ff }, |
|
676 { NvRegWakeUpFlags, 0x07777 }, |
|
677 { 0,0 } |
|
678 }; |
|
679 |
|
680 /* |
|
681 * SMP locking: |
|
682 * All hardware access under dev->priv->lock, except the performance |
|
683 * critical parts: |
|
684 * - rx is (pseudo-) lockless: it relies on the single-threading provided |
|
685 * by the arch code for interrupts. |
|
686 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
|
687 * needs dev->priv->lock :-( |
|
688 * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
|
689 */ |
|
690 |
|
691 /* in dev: base, irq */ |
|
692 struct fe_priv { |
|
693 spinlock_t lock; |
|
694 |
|
695 /* General data: |
|
696 * Locking: spin_lock(&np->lock); */ |
|
697 struct net_device_stats stats; |
|
698 struct nv_ethtool_stats estats; |
|
699 int in_shutdown; |
|
700 u32 linkspeed; |
|
701 int duplex; |
|
702 int autoneg; |
|
703 int fixed_mode; |
|
704 int phyaddr; |
|
705 int wolenabled; |
|
706 unsigned int phy_oui; |
|
707 unsigned int phy_model; |
|
708 u16 gigabit; |
|
709 int intr_test; |
|
710 |
|
711 /* General data: RO fields */ |
|
712 dma_addr_t ring_addr; |
|
713 struct pci_dev *pci_dev; |
|
714 u32 orig_mac[2]; |
|
715 u32 irqmask; |
|
716 u32 desc_ver; |
|
717 u32 txrxctl_bits; |
|
718 u32 vlanctl_bits; |
|
719 u32 driver_data; |
|
720 u32 register_size; |
|
721 int rx_csum; |
|
722 |
|
723 void __iomem *base; |
|
724 |
|
725 /* rx specific fields. |
|
726 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
727 */ |
|
728 union ring_type rx_ring; |
|
729 unsigned int cur_rx, refill_rx; |
|
730 struct sk_buff **rx_skbuff; |
|
731 dma_addr_t *rx_dma; |
|
732 unsigned int rx_buf_sz; |
|
733 unsigned int pkt_limit; |
|
734 struct timer_list oom_kick; |
|
735 struct timer_list nic_poll; |
|
736 struct timer_list stats_poll; |
|
737 u32 nic_poll_irq; |
|
738 int rx_ring_size; |
|
739 |
|
740 /* media detection workaround. |
|
741 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
742 */ |
|
743 int need_linktimer; |
|
744 unsigned long link_timeout; |
|
745 /* |
|
746 * tx specific fields. |
|
747 */ |
|
748 union ring_type tx_ring; |
|
749 unsigned int next_tx, nic_tx; |
|
750 struct sk_buff **tx_skbuff; |
|
751 dma_addr_t *tx_dma; |
|
752 unsigned int *tx_dma_len; |
|
753 u32 tx_flags; |
|
754 int tx_ring_size; |
|
755 int tx_limit_start; |
|
756 int tx_limit_stop; |
|
757 |
|
758 /* vlan fields */ |
|
759 struct vlan_group *vlangrp; |
|
760 |
|
761 /* msi/msi-x fields */ |
|
762 u32 msi_flags; |
|
763 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; |
|
764 |
|
765 /* flow control */ |
|
766 u32 pause_flags; |
|
767 }; |
|
768 |
|
769 /* |
|
770 * Maximum number of loops until we assume that a bit in the irq mask |
|
771 * is stuck. Overridable with module param. |
|
772 */ |
|
773 static int max_interrupt_work = 5; |
|
774 |
|
775 /* |
|
776 * Optimization can be either throuput mode or cpu mode |
|
777 * |
|
778 * Throughput Mode: Every tx and rx packet will generate an interrupt. |
|
779 * CPU Mode: Interrupts are controlled by a timer. |
|
780 */ |
|
781 enum { |
|
782 NV_OPTIMIZATION_MODE_THROUGHPUT, |
|
783 NV_OPTIMIZATION_MODE_CPU |
|
784 }; |
|
785 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
|
786 |
|
787 /* |
|
788 * Poll interval for timer irq |
|
789 * |
|
790 * This interval determines how frequent an interrupt is generated. |
|
791 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] |
|
792 * Min = 0, and Max = 65535 |
|
793 */ |
|
794 static int poll_interval = -1; |
|
795 |
|
796 /* |
|
797 * MSI interrupts |
|
798 */ |
|
799 enum { |
|
800 NV_MSI_INT_DISABLED, |
|
801 NV_MSI_INT_ENABLED |
|
802 }; |
|
803 static int msi = NV_MSI_INT_ENABLED; |
|
804 |
|
805 /* |
|
806 * MSIX interrupts |
|
807 */ |
|
808 enum { |
|
809 NV_MSIX_INT_DISABLED, |
|
810 NV_MSIX_INT_ENABLED |
|
811 }; |
|
812 static int msix = NV_MSIX_INT_ENABLED; |
|
813 |
|
814 /* |
|
815 * DMA 64bit |
|
816 */ |
|
817 enum { |
|
818 NV_DMA_64BIT_DISABLED, |
|
819 NV_DMA_64BIT_ENABLED |
|
820 }; |
|
821 static int dma_64bit = NV_DMA_64BIT_ENABLED; |
|
822 |
|
823 static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
|
824 { |
|
825 return netdev_priv(dev); |
|
826 } |
|
827 |
|
828 static inline u8 __iomem *get_hwbase(struct net_device *dev) |
|
829 { |
|
830 return ((struct fe_priv *)netdev_priv(dev))->base; |
|
831 } |
|
832 |
|
833 static inline void pci_push(u8 __iomem *base) |
|
834 { |
|
835 /* force out pending posted writes */ |
|
836 readl(base); |
|
837 } |
|
838 |
|
839 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) |
|
840 { |
|
841 return le32_to_cpu(prd->flaglen) |
|
842 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
|
843 } |
|
844 |
|
845 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
|
846 { |
|
847 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
|
848 } |
|
849 |
|
850 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
|
851 int delay, int delaymax, const char *msg) |
|
852 { |
|
853 u8 __iomem *base = get_hwbase(dev); |
|
854 |
|
855 pci_push(base); |
|
856 do { |
|
857 udelay(delay); |
|
858 delaymax -= delay; |
|
859 if (delaymax < 0) { |
|
860 if (msg) |
|
861 printk(msg); |
|
862 return 1; |
|
863 } |
|
864 } while ((readl(base + offset) & mask) != target); |
|
865 return 0; |
|
866 } |
|
867 |
|
868 #define NV_SETUP_RX_RING 0x01 |
|
869 #define NV_SETUP_TX_RING 0x02 |
|
870 |
|
871 static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
|
872 { |
|
873 struct fe_priv *np = get_nvpriv(dev); |
|
874 u8 __iomem *base = get_hwbase(dev); |
|
875 |
|
876 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
877 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
878 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
879 } |
|
880 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
881 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
|
882 } |
|
883 } else { |
|
884 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
885 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
886 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh); |
|
887 } |
|
888 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
889 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
|
890 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh); |
|
891 } |
|
892 } |
|
893 } |
|
894 |
|
895 static void free_rings(struct net_device *dev) |
|
896 { |
|
897 struct fe_priv *np = get_nvpriv(dev); |
|
898 |
|
899 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
900 if (np->rx_ring.orig) |
|
901 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
|
902 np->rx_ring.orig, np->ring_addr); |
|
903 } else { |
|
904 if (np->rx_ring.ex) |
|
905 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
|
906 np->rx_ring.ex, np->ring_addr); |
|
907 } |
|
908 if (np->rx_skbuff) |
|
909 kfree(np->rx_skbuff); |
|
910 if (np->rx_dma) |
|
911 kfree(np->rx_dma); |
|
912 if (np->tx_skbuff) |
|
913 kfree(np->tx_skbuff); |
|
914 if (np->tx_dma) |
|
915 kfree(np->tx_dma); |
|
916 if (np->tx_dma_len) |
|
917 kfree(np->tx_dma_len); |
|
918 } |
|
919 |
|
920 static int using_multi_irqs(struct net_device *dev) |
|
921 { |
|
922 struct fe_priv *np = get_nvpriv(dev); |
|
923 |
|
924 if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
|
925 ((np->msi_flags & NV_MSI_X_ENABLED) && |
|
926 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) |
|
927 return 0; |
|
928 else |
|
929 return 1; |
|
930 } |
|
931 |
|
932 static void nv_enable_irq(struct net_device *dev) |
|
933 { |
|
934 struct fe_priv *np = get_nvpriv(dev); |
|
935 |
|
936 if (!using_multi_irqs(dev)) { |
|
937 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
938 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
939 else |
|
940 enable_irq(dev->irq); |
|
941 } else { |
|
942 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
943 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
944 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
945 } |
|
946 } |
|
947 |
|
948 static void nv_disable_irq(struct net_device *dev) |
|
949 { |
|
950 struct fe_priv *np = get_nvpriv(dev); |
|
951 |
|
952 if (!using_multi_irqs(dev)) { |
|
953 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
954 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
955 else |
|
956 disable_irq(dev->irq); |
|
957 } else { |
|
958 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
959 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
960 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
961 } |
|
962 } |
|
963 |
|
964 /* In MSIX mode, a write to irqmask behaves as XOR */ |
|
965 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) |
|
966 { |
|
967 u8 __iomem *base = get_hwbase(dev); |
|
968 |
|
969 writel(mask, base + NvRegIrqMask); |
|
970 } |
|
971 |
|
972 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) |
|
973 { |
|
974 struct fe_priv *np = get_nvpriv(dev); |
|
975 u8 __iomem *base = get_hwbase(dev); |
|
976 |
|
977 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
978 writel(mask, base + NvRegIrqMask); |
|
979 } else { |
|
980 if (np->msi_flags & NV_MSI_ENABLED) |
|
981 writel(0, base + NvRegMSIIrqMask); |
|
982 writel(0, base + NvRegIrqMask); |
|
983 } |
|
984 } |
|
985 |
|
986 #define MII_READ (-1) |
|
987 /* mii_rw: read/write a register on the PHY. |
|
988 * |
|
989 * Caller must guarantee serialization |
|
990 */ |
|
991 static int mii_rw(struct net_device *dev, int addr, int miireg, int value) |
|
992 { |
|
993 u8 __iomem *base = get_hwbase(dev); |
|
994 u32 reg; |
|
995 int retval; |
|
996 |
|
997 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
998 |
|
999 reg = readl(base + NvRegMIIControl); |
|
1000 if (reg & NVREG_MIICTL_INUSE) { |
|
1001 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); |
|
1002 udelay(NV_MIIBUSY_DELAY); |
|
1003 } |
|
1004 |
|
1005 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; |
|
1006 if (value != MII_READ) { |
|
1007 writel(value, base + NvRegMIIData); |
|
1008 reg |= NVREG_MIICTL_WRITE; |
|
1009 } |
|
1010 writel(reg, base + NvRegMIIControl); |
|
1011 |
|
1012 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, |
|
1013 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { |
|
1014 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", |
|
1015 dev->name, miireg, addr); |
|
1016 retval = -1; |
|
1017 } else if (value != MII_READ) { |
|
1018 /* it was a write operation - fewer failures are detectable */ |
|
1019 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", |
|
1020 dev->name, value, miireg, addr); |
|
1021 retval = 0; |
|
1022 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { |
|
1023 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", |
|
1024 dev->name, miireg, addr); |
|
1025 retval = -1; |
|
1026 } else { |
|
1027 retval = readl(base + NvRegMIIData); |
|
1028 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", |
|
1029 dev->name, miireg, addr, retval); |
|
1030 } |
|
1031 |
|
1032 return retval; |
|
1033 } |
|
1034 |
|
1035 static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
|
1036 { |
|
1037 struct fe_priv *np = netdev_priv(dev); |
|
1038 u32 miicontrol; |
|
1039 unsigned int tries = 0; |
|
1040 |
|
1041 miicontrol = BMCR_RESET | bmcr_setup; |
|
1042 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
|
1043 return -1; |
|
1044 } |
|
1045 |
|
1046 /* wait for 500ms */ |
|
1047 msleep(500); |
|
1048 |
|
1049 /* must wait till reset is deasserted */ |
|
1050 while (miicontrol & BMCR_RESET) { |
|
1051 msleep(10); |
|
1052 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
1053 /* FIXME: 100 tries seem excessive */ |
|
1054 if (tries++ > 100) |
|
1055 return -1; |
|
1056 } |
|
1057 return 0; |
|
1058 } |
|
1059 |
|
1060 static int phy_init(struct net_device *dev) |
|
1061 { |
|
1062 struct fe_priv *np = get_nvpriv(dev); |
|
1063 u8 __iomem *base = get_hwbase(dev); |
|
1064 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
|
1065 |
|
1066 /* phy errata for E3016 phy */ |
|
1067 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
|
1068 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
|
1069 reg &= ~PHY_MARVELL_E3016_INITMASK; |
|
1070 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { |
|
1071 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); |
|
1072 return PHY_ERROR; |
|
1073 } |
|
1074 } |
|
1075 |
|
1076 /* set advertise register */ |
|
1077 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
1078 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
|
1079 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
|
1080 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
|
1081 return PHY_ERROR; |
|
1082 } |
|
1083 |
|
1084 /* get phy interface type */ |
|
1085 phyinterface = readl(base + NvRegPhyInterface); |
|
1086 |
|
1087 /* see if gigabit phy */ |
|
1088 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
1089 if (mii_status & PHY_GIGABIT) { |
|
1090 np->gigabit = PHY_GIGABIT; |
|
1091 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
|
1092 mii_control_1000 &= ~ADVERTISE_1000HALF; |
|
1093 if (phyinterface & PHY_RGMII) |
|
1094 mii_control_1000 |= ADVERTISE_1000FULL; |
|
1095 else |
|
1096 mii_control_1000 &= ~ADVERTISE_1000FULL; |
|
1097 |
|
1098 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
|
1099 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
1100 return PHY_ERROR; |
|
1101 } |
|
1102 } |
|
1103 else |
|
1104 np->gigabit = 0; |
|
1105 |
|
1106 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
1107 mii_control |= BMCR_ANENABLE; |
|
1108 |
|
1109 /* reset the phy |
|
1110 * (certain phys need bmcr to be setup with reset) |
|
1111 */ |
|
1112 if (phy_reset(dev, mii_control)) { |
|
1113 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
|
1114 return PHY_ERROR; |
|
1115 } |
|
1116 |
|
1117 /* phy vendor specific configuration */ |
|
1118 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
|
1119 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
|
1120 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); |
|
1121 phy_reserved |= (PHY_INIT3 | PHY_INIT4); |
|
1122 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
|
1123 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
1124 return PHY_ERROR; |
|
1125 } |
|
1126 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
|
1127 phy_reserved |= PHY_INIT5; |
|
1128 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
|
1129 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
1130 return PHY_ERROR; |
|
1131 } |
|
1132 } |
|
1133 if (np->phy_oui == PHY_OUI_CICADA) { |
|
1134 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
|
1135 phy_reserved |= PHY_INIT6; |
|
1136 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
|
1137 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
1138 return PHY_ERROR; |
|
1139 } |
|
1140 } |
|
1141 /* some phys clear out pause advertisment on reset, set it back */ |
|
1142 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
|
1143 |
|
1144 /* restart auto negotiation */ |
|
1145 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
1146 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
|
1147 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
|
1148 return PHY_ERROR; |
|
1149 } |
|
1150 |
|
1151 return 0; |
|
1152 } |
|
1153 |
|
1154 static void nv_start_rx(struct net_device *dev) |
|
1155 { |
|
1156 struct fe_priv *np = netdev_priv(dev); |
|
1157 u8 __iomem *base = get_hwbase(dev); |
|
1158 |
|
1159 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
|
1160 /* Already running? Stop it. */ |
|
1161 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { |
|
1162 writel(0, base + NvRegReceiverControl); |
|
1163 pci_push(base); |
|
1164 } |
|
1165 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
1166 pci_push(base); |
|
1167 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); |
|
1168 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
|
1169 dev->name, np->duplex, np->linkspeed); |
|
1170 pci_push(base); |
|
1171 } |
|
1172 |
|
1173 static void nv_stop_rx(struct net_device *dev) |
|
1174 { |
|
1175 u8 __iomem *base = get_hwbase(dev); |
|
1176 |
|
1177 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
|
1178 writel(0, base + NvRegReceiverControl); |
|
1179 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
|
1180 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
|
1181 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
|
1182 |
|
1183 udelay(NV_RXSTOP_DELAY2); |
|
1184 writel(0, base + NvRegLinkSpeed); |
|
1185 } |
|
1186 |
|
1187 static void nv_start_tx(struct net_device *dev) |
|
1188 { |
|
1189 u8 __iomem *base = get_hwbase(dev); |
|
1190 |
|
1191 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
|
1192 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); |
|
1193 pci_push(base); |
|
1194 } |
|
1195 |
|
1196 static void nv_stop_tx(struct net_device *dev) |
|
1197 { |
|
1198 u8 __iomem *base = get_hwbase(dev); |
|
1199 |
|
1200 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
|
1201 writel(0, base + NvRegTransmitterControl); |
|
1202 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
|
1203 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
|
1204 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
|
1205 |
|
1206 udelay(NV_TXSTOP_DELAY2); |
|
1207 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
|
1208 } |
|
1209 |
|
1210 static void nv_txrx_reset(struct net_device *dev) |
|
1211 { |
|
1212 struct fe_priv *np = netdev_priv(dev); |
|
1213 u8 __iomem *base = get_hwbase(dev); |
|
1214 |
|
1215 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
|
1216 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1217 pci_push(base); |
|
1218 udelay(NV_TXRX_RESET_DELAY); |
|
1219 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1220 pci_push(base); |
|
1221 } |
|
1222 |
|
1223 static void nv_mac_reset(struct net_device *dev) |
|
1224 { |
|
1225 struct fe_priv *np = netdev_priv(dev); |
|
1226 u8 __iomem *base = get_hwbase(dev); |
|
1227 |
|
1228 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); |
|
1229 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1230 pci_push(base); |
|
1231 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
|
1232 pci_push(base); |
|
1233 udelay(NV_MAC_RESET_DELAY); |
|
1234 writel(0, base + NvRegMacReset); |
|
1235 pci_push(base); |
|
1236 udelay(NV_MAC_RESET_DELAY); |
|
1237 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1238 pci_push(base); |
|
1239 } |
|
1240 |
|
1241 /* |
|
1242 * nv_get_stats: dev->get_stats function |
|
1243 * Get latest stats value from the nic. |
|
1244 * Called with read_lock(&dev_base_lock) held for read - |
|
1245 * only synchronized against unregister_netdevice. |
|
1246 */ |
|
1247 static struct net_device_stats *nv_get_stats(struct net_device *dev) |
|
1248 { |
|
1249 struct fe_priv *np = netdev_priv(dev); |
|
1250 |
|
1251 /* It seems that the nic always generates interrupts and doesn't |
|
1252 * accumulate errors internally. Thus the current values in np->stats |
|
1253 * are already up to date. |
|
1254 */ |
|
1255 return &np->stats; |
|
1256 } |
|
1257 |
|
1258 /* |
|
1259 * nv_alloc_rx: fill rx ring entries. |
|
1260 * Return 1 if the allocations for the skbs failed and the |
|
1261 * rx engine is without Available descriptors |
|
1262 */ |
|
1263 static int nv_alloc_rx(struct net_device *dev) |
|
1264 { |
|
1265 struct fe_priv *np = netdev_priv(dev); |
|
1266 unsigned int refill_rx = np->refill_rx; |
|
1267 int nr; |
|
1268 |
|
1269 while (np->cur_rx != refill_rx) { |
|
1270 struct sk_buff *skb; |
|
1271 |
|
1272 nr = refill_rx % np->rx_ring_size; |
|
1273 if (np->rx_skbuff[nr] == NULL) { |
|
1274 |
|
1275 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
|
1276 if (!skb) |
|
1277 break; |
|
1278 |
|
1279 skb->dev = dev; |
|
1280 np->rx_skbuff[nr] = skb; |
|
1281 } else { |
|
1282 skb = np->rx_skbuff[nr]; |
|
1283 } |
|
1284 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, |
|
1285 skb->end-skb->data, PCI_DMA_FROMDEVICE); |
|
1286 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1287 np->rx_ring.orig[nr].buf = cpu_to_le32(np->rx_dma[nr]); |
|
1288 wmb(); |
|
1289 np->rx_ring.orig[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); |
|
1290 } else { |
|
1291 np->rx_ring.ex[nr].bufhigh = cpu_to_le64(np->rx_dma[nr]) >> 32; |
|
1292 np->rx_ring.ex[nr].buflow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; |
|
1293 wmb(); |
|
1294 np->rx_ring.ex[nr].flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); |
|
1295 } |
|
1296 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
|
1297 dev->name, refill_rx); |
|
1298 refill_rx++; |
|
1299 } |
|
1300 np->refill_rx = refill_rx; |
|
1301 if (np->cur_rx - refill_rx == np->rx_ring_size) |
|
1302 return 1; |
|
1303 return 0; |
|
1304 } |
|
1305 |
|
1306 /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
|
1307 #ifdef CONFIG_FORCEDETH_NAPI |
|
1308 static void nv_do_rx_refill(unsigned long data) |
|
1309 { |
|
1310 struct net_device *dev = (struct net_device *) data; |
|
1311 |
|
1312 /* Just reschedule NAPI rx processing */ |
|
1313 netif_rx_schedule(dev); |
|
1314 } |
|
1315 #else |
|
1316 static void nv_do_rx_refill(unsigned long data) |
|
1317 { |
|
1318 struct net_device *dev = (struct net_device *) data; |
|
1319 struct fe_priv *np = netdev_priv(dev); |
|
1320 |
|
1321 if (!using_multi_irqs(dev)) { |
|
1322 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1323 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1324 else |
|
1325 disable_irq(dev->irq); |
|
1326 } else { |
|
1327 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1328 } |
|
1329 if (nv_alloc_rx(dev)) { |
|
1330 spin_lock_irq(&np->lock); |
|
1331 if (!np->in_shutdown) |
|
1332 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
1333 spin_unlock_irq(&np->lock); |
|
1334 } |
|
1335 if (!using_multi_irqs(dev)) { |
|
1336 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1337 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1338 else |
|
1339 enable_irq(dev->irq); |
|
1340 } else { |
|
1341 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1342 } |
|
1343 } |
|
1344 #endif |
|
1345 |
|
1346 static void nv_init_rx(struct net_device *dev) |
|
1347 { |
|
1348 struct fe_priv *np = netdev_priv(dev); |
|
1349 int i; |
|
1350 |
|
1351 np->cur_rx = np->rx_ring_size; |
|
1352 np->refill_rx = 0; |
|
1353 for (i = 0; i < np->rx_ring_size; i++) |
|
1354 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1355 np->rx_ring.orig[i].flaglen = 0; |
|
1356 else |
|
1357 np->rx_ring.ex[i].flaglen = 0; |
|
1358 } |
|
1359 |
|
1360 static void nv_init_tx(struct net_device *dev) |
|
1361 { |
|
1362 struct fe_priv *np = netdev_priv(dev); |
|
1363 int i; |
|
1364 |
|
1365 np->next_tx = np->nic_tx = 0; |
|
1366 for (i = 0; i < np->tx_ring_size; i++) { |
|
1367 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1368 np->tx_ring.orig[i].flaglen = 0; |
|
1369 else |
|
1370 np->tx_ring.ex[i].flaglen = 0; |
|
1371 np->tx_skbuff[i] = NULL; |
|
1372 np->tx_dma[i] = 0; |
|
1373 } |
|
1374 } |
|
1375 |
|
1376 static int nv_init_ring(struct net_device *dev) |
|
1377 { |
|
1378 nv_init_tx(dev); |
|
1379 nv_init_rx(dev); |
|
1380 return nv_alloc_rx(dev); |
|
1381 } |
|
1382 |
|
1383 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
|
1384 { |
|
1385 struct fe_priv *np = netdev_priv(dev); |
|
1386 |
|
1387 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", |
|
1388 dev->name, skbnr); |
|
1389 |
|
1390 if (np->tx_dma[skbnr]) { |
|
1391 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr], |
|
1392 np->tx_dma_len[skbnr], |
|
1393 PCI_DMA_TODEVICE); |
|
1394 np->tx_dma[skbnr] = 0; |
|
1395 } |
|
1396 |
|
1397 if (np->tx_skbuff[skbnr]) { |
|
1398 dev_kfree_skb_any(np->tx_skbuff[skbnr]); |
|
1399 np->tx_skbuff[skbnr] = NULL; |
|
1400 return 1; |
|
1401 } else { |
|
1402 return 0; |
|
1403 } |
|
1404 } |
|
1405 |
|
1406 static void nv_drain_tx(struct net_device *dev) |
|
1407 { |
|
1408 struct fe_priv *np = netdev_priv(dev); |
|
1409 unsigned int i; |
|
1410 |
|
1411 for (i = 0; i < np->tx_ring_size; i++) { |
|
1412 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1413 np->tx_ring.orig[i].flaglen = 0; |
|
1414 else |
|
1415 np->tx_ring.ex[i].flaglen = 0; |
|
1416 if (nv_release_txskb(dev, i)) |
|
1417 np->stats.tx_dropped++; |
|
1418 } |
|
1419 } |
|
1420 |
|
1421 static void nv_drain_rx(struct net_device *dev) |
|
1422 { |
|
1423 struct fe_priv *np = netdev_priv(dev); |
|
1424 int i; |
|
1425 for (i = 0; i < np->rx_ring_size; i++) { |
|
1426 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1427 np->rx_ring.orig[i].flaglen = 0; |
|
1428 else |
|
1429 np->rx_ring.ex[i].flaglen = 0; |
|
1430 wmb(); |
|
1431 if (np->rx_skbuff[i]) { |
|
1432 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1433 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1434 PCI_DMA_FROMDEVICE); |
|
1435 dev_kfree_skb(np->rx_skbuff[i]); |
|
1436 np->rx_skbuff[i] = NULL; |
|
1437 } |
|
1438 } |
|
1439 } |
|
1440 |
|
1441 static void drain_ring(struct net_device *dev) |
|
1442 { |
|
1443 nv_drain_tx(dev); |
|
1444 nv_drain_rx(dev); |
|
1445 } |
|
1446 |
|
1447 /* |
|
1448 * nv_start_xmit: dev->hard_start_xmit function |
|
1449 * Called with netif_tx_lock held. |
|
1450 */ |
|
1451 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
1452 { |
|
1453 struct fe_priv *np = netdev_priv(dev); |
|
1454 u32 tx_flags = 0; |
|
1455 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
|
1456 unsigned int fragments = skb_shinfo(skb)->nr_frags; |
|
1457 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size; |
|
1458 unsigned int start_nr = np->next_tx % np->tx_ring_size; |
|
1459 unsigned int i; |
|
1460 u32 offset = 0; |
|
1461 u32 bcnt; |
|
1462 u32 size = skb->len-skb->data_len; |
|
1463 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1464 u32 tx_flags_vlan = 0; |
|
1465 |
|
1466 /* add fragments to entries count */ |
|
1467 for (i = 0; i < fragments; i++) { |
|
1468 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
|
1469 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1470 } |
|
1471 |
|
1472 spin_lock_irq(&np->lock); |
|
1473 |
|
1474 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) { |
|
1475 spin_unlock_irq(&np->lock); |
|
1476 netif_stop_queue(dev); |
|
1477 return NETDEV_TX_BUSY; |
|
1478 } |
|
1479 |
|
1480 /* setup the header buffer */ |
|
1481 do { |
|
1482 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1483 nr = (nr + 1) % np->tx_ring_size; |
|
1484 |
|
1485 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
|
1486 PCI_DMA_TODEVICE); |
|
1487 np->tx_dma_len[nr] = bcnt; |
|
1488 |
|
1489 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1490 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]); |
|
1491 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1492 } else { |
|
1493 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1494 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1495 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1496 } |
|
1497 tx_flags = np->tx_flags; |
|
1498 offset += bcnt; |
|
1499 size -= bcnt; |
|
1500 } while (size); |
|
1501 |
|
1502 /* setup the fragments */ |
|
1503 for (i = 0; i < fragments; i++) { |
|
1504 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
|
1505 u32 size = frag->size; |
|
1506 offset = 0; |
|
1507 |
|
1508 do { |
|
1509 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1510 nr = (nr + 1) % np->tx_ring_size; |
|
1511 |
|
1512 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
|
1513 PCI_DMA_TODEVICE); |
|
1514 np->tx_dma_len[nr] = bcnt; |
|
1515 |
|
1516 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1517 np->tx_ring.orig[nr].buf = cpu_to_le32(np->tx_dma[nr]); |
|
1518 np->tx_ring.orig[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1519 } else { |
|
1520 np->tx_ring.ex[nr].bufhigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1521 np->tx_ring.ex[nr].buflow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1522 np->tx_ring.ex[nr].flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1523 } |
|
1524 offset += bcnt; |
|
1525 size -= bcnt; |
|
1526 } while (size); |
|
1527 } |
|
1528 |
|
1529 /* set last fragment flag */ |
|
1530 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1531 np->tx_ring.orig[nr].flaglen |= cpu_to_le32(tx_flags_extra); |
|
1532 } else { |
|
1533 np->tx_ring.ex[nr].flaglen |= cpu_to_le32(tx_flags_extra); |
|
1534 } |
|
1535 |
|
1536 np->tx_skbuff[nr] = skb; |
|
1537 |
|
1538 #ifdef NETIF_F_TSO |
|
1539 if (skb_is_gso(skb)) |
|
1540 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
|
1541 else |
|
1542 #endif |
|
1543 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
|
1544 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
|
1545 |
|
1546 /* vlan tag */ |
|
1547 if (np->vlangrp && vlan_tx_tag_present(skb)) { |
|
1548 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb); |
|
1549 } |
|
1550 |
|
1551 /* set tx flags */ |
|
1552 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1553 np->tx_ring.orig[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1554 } else { |
|
1555 np->tx_ring.ex[start_nr].txvlan = cpu_to_le32(tx_flags_vlan); |
|
1556 np->tx_ring.ex[start_nr].flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1557 } |
|
1558 |
|
1559 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", |
|
1560 dev->name, np->next_tx, entries, tx_flags_extra); |
|
1561 { |
|
1562 int j; |
|
1563 for (j=0; j<64; j++) { |
|
1564 if ((j%16) == 0) |
|
1565 dprintk("\n%03x:", j); |
|
1566 dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
|
1567 } |
|
1568 dprintk("\n"); |
|
1569 } |
|
1570 |
|
1571 np->next_tx += entries; |
|
1572 |
|
1573 dev->trans_start = jiffies; |
|
1574 spin_unlock_irq(&np->lock); |
|
1575 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
1576 pci_push(get_hwbase(dev)); |
|
1577 return NETDEV_TX_OK; |
|
1578 } |
|
1579 |
|
1580 /* |
|
1581 * nv_tx_done: check for completed packets, release the skbs. |
|
1582 * |
|
1583 * Caller must own np->lock. |
|
1584 */ |
|
1585 static void nv_tx_done(struct net_device *dev) |
|
1586 { |
|
1587 struct fe_priv *np = netdev_priv(dev); |
|
1588 u32 flags; |
|
1589 unsigned int i; |
|
1590 struct sk_buff *skb; |
|
1591 |
|
1592 while (np->nic_tx != np->next_tx) { |
|
1593 i = np->nic_tx % np->tx_ring_size; |
|
1594 |
|
1595 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1596 flags = le32_to_cpu(np->tx_ring.orig[i].flaglen); |
|
1597 else |
|
1598 flags = le32_to_cpu(np->tx_ring.ex[i].flaglen); |
|
1599 |
|
1600 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, flags 0x%x.\n", |
|
1601 dev->name, np->nic_tx, flags); |
|
1602 if (flags & NV_TX_VALID) |
|
1603 break; |
|
1604 if (np->desc_ver == DESC_VER_1) { |
|
1605 if (flags & NV_TX_LASTPACKET) { |
|
1606 skb = np->tx_skbuff[i]; |
|
1607 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
|
1608 NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
|
1609 if (flags & NV_TX_UNDERFLOW) |
|
1610 np->stats.tx_fifo_errors++; |
|
1611 if (flags & NV_TX_CARRIERLOST) |
|
1612 np->stats.tx_carrier_errors++; |
|
1613 np->stats.tx_errors++; |
|
1614 } else { |
|
1615 np->stats.tx_packets++; |
|
1616 np->stats.tx_bytes += skb->len; |
|
1617 } |
|
1618 } |
|
1619 } else { |
|
1620 if (flags & NV_TX2_LASTPACKET) { |
|
1621 skb = np->tx_skbuff[i]; |
|
1622 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
|
1623 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
|
1624 if (flags & NV_TX2_UNDERFLOW) |
|
1625 np->stats.tx_fifo_errors++; |
|
1626 if (flags & NV_TX2_CARRIERLOST) |
|
1627 np->stats.tx_carrier_errors++; |
|
1628 np->stats.tx_errors++; |
|
1629 } else { |
|
1630 np->stats.tx_packets++; |
|
1631 np->stats.tx_bytes += skb->len; |
|
1632 } |
|
1633 } |
|
1634 } |
|
1635 nv_release_txskb(dev, i); |
|
1636 np->nic_tx++; |
|
1637 } |
|
1638 if (np->next_tx - np->nic_tx < np->tx_limit_start) |
|
1639 netif_wake_queue(dev); |
|
1640 } |
|
1641 |
|
1642 /* |
|
1643 * nv_tx_timeout: dev->tx_timeout function |
|
1644 * Called with netif_tx_lock held. |
|
1645 */ |
|
1646 static void nv_tx_timeout(struct net_device *dev) |
|
1647 { |
|
1648 struct fe_priv *np = netdev_priv(dev); |
|
1649 u8 __iomem *base = get_hwbase(dev); |
|
1650 u32 status; |
|
1651 |
|
1652 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1653 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1654 else |
|
1655 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1656 |
|
1657 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
|
1658 |
|
1659 { |
|
1660 int i; |
|
1661 |
|
1662 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n", |
|
1663 dev->name, (unsigned long)np->ring_addr, |
|
1664 np->next_tx, np->nic_tx); |
|
1665 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
|
1666 for (i=0;i<=np->register_size;i+= 32) { |
|
1667 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
|
1668 i, |
|
1669 readl(base + i + 0), readl(base + i + 4), |
|
1670 readl(base + i + 8), readl(base + i + 12), |
|
1671 readl(base + i + 16), readl(base + i + 20), |
|
1672 readl(base + i + 24), readl(base + i + 28)); |
|
1673 } |
|
1674 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); |
|
1675 for (i=0;i<np->tx_ring_size;i+= 4) { |
|
1676 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1677 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
|
1678 i, |
|
1679 le32_to_cpu(np->tx_ring.orig[i].buf), |
|
1680 le32_to_cpu(np->tx_ring.orig[i].flaglen), |
|
1681 le32_to_cpu(np->tx_ring.orig[i+1].buf), |
|
1682 le32_to_cpu(np->tx_ring.orig[i+1].flaglen), |
|
1683 le32_to_cpu(np->tx_ring.orig[i+2].buf), |
|
1684 le32_to_cpu(np->tx_ring.orig[i+2].flaglen), |
|
1685 le32_to_cpu(np->tx_ring.orig[i+3].buf), |
|
1686 le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); |
|
1687 } else { |
|
1688 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
|
1689 i, |
|
1690 le32_to_cpu(np->tx_ring.ex[i].bufhigh), |
|
1691 le32_to_cpu(np->tx_ring.ex[i].buflow), |
|
1692 le32_to_cpu(np->tx_ring.ex[i].flaglen), |
|
1693 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), |
|
1694 le32_to_cpu(np->tx_ring.ex[i+1].buflow), |
|
1695 le32_to_cpu(np->tx_ring.ex[i+1].flaglen), |
|
1696 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), |
|
1697 le32_to_cpu(np->tx_ring.ex[i+2].buflow), |
|
1698 le32_to_cpu(np->tx_ring.ex[i+2].flaglen), |
|
1699 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), |
|
1700 le32_to_cpu(np->tx_ring.ex[i+3].buflow), |
|
1701 le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); |
|
1702 } |
|
1703 } |
|
1704 } |
|
1705 |
|
1706 spin_lock_irq(&np->lock); |
|
1707 |
|
1708 /* 1) stop tx engine */ |
|
1709 nv_stop_tx(dev); |
|
1710 |
|
1711 /* 2) check that the packets were not sent already: */ |
|
1712 nv_tx_done(dev); |
|
1713 |
|
1714 /* 3) if there are dead entries: clear everything */ |
|
1715 if (np->next_tx != np->nic_tx) { |
|
1716 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
|
1717 nv_drain_tx(dev); |
|
1718 np->next_tx = np->nic_tx = 0; |
|
1719 setup_hw_rings(dev, NV_SETUP_TX_RING); |
|
1720 netif_wake_queue(dev); |
|
1721 } |
|
1722 |
|
1723 /* 4) restart tx engine */ |
|
1724 nv_start_tx(dev); |
|
1725 spin_unlock_irq(&np->lock); |
|
1726 } |
|
1727 |
|
1728 /* |
|
1729 * Called when the nic notices a mismatch between the actual data len on the |
|
1730 * wire and the len indicated in the 802 header |
|
1731 */ |
|
1732 static int nv_getlen(struct net_device *dev, void *packet, int datalen) |
|
1733 { |
|
1734 int hdrlen; /* length of the 802 header */ |
|
1735 int protolen; /* length as stored in the proto field */ |
|
1736 |
|
1737 /* 1) calculate len according to header */ |
|
1738 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
|
1739 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
|
1740 hdrlen = VLAN_HLEN; |
|
1741 } else { |
|
1742 protolen = ntohs( ((struct ethhdr *)packet)->h_proto); |
|
1743 hdrlen = ETH_HLEN; |
|
1744 } |
|
1745 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", |
|
1746 dev->name, datalen, protolen, hdrlen); |
|
1747 if (protolen > ETH_DATA_LEN) |
|
1748 return datalen; /* Value in proto field not a len, no checks possible */ |
|
1749 |
|
1750 protolen += hdrlen; |
|
1751 /* consistency checks: */ |
|
1752 if (datalen > ETH_ZLEN) { |
|
1753 if (datalen >= protolen) { |
|
1754 /* more data on wire than in 802 header, trim of |
|
1755 * additional data. |
|
1756 */ |
|
1757 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1758 dev->name, protolen); |
|
1759 return protolen; |
|
1760 } else { |
|
1761 /* less data on wire than mentioned in header. |
|
1762 * Discard the packet. |
|
1763 */ |
|
1764 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", |
|
1765 dev->name); |
|
1766 return -1; |
|
1767 } |
|
1768 } else { |
|
1769 /* short packet. Accept only if 802 values are also short */ |
|
1770 if (protolen > ETH_ZLEN) { |
|
1771 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", |
|
1772 dev->name); |
|
1773 return -1; |
|
1774 } |
|
1775 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1776 dev->name, datalen); |
|
1777 return datalen; |
|
1778 } |
|
1779 } |
|
1780 |
|
1781 static int nv_rx_process(struct net_device *dev, int limit) |
|
1782 { |
|
1783 struct fe_priv *np = netdev_priv(dev); |
|
1784 u32 flags; |
|
1785 u32 vlanflags = 0; |
|
1786 int count; |
|
1787 |
|
1788 for (count = 0; count < limit; ++count) { |
|
1789 struct sk_buff *skb; |
|
1790 int len; |
|
1791 int i; |
|
1792 if (np->cur_rx - np->refill_rx >= np->rx_ring_size) |
|
1793 break; /* we scanned the whole ring - do not continue */ |
|
1794 |
|
1795 i = np->cur_rx % np->rx_ring_size; |
|
1796 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1797 flags = le32_to_cpu(np->rx_ring.orig[i].flaglen); |
|
1798 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); |
|
1799 } else { |
|
1800 flags = le32_to_cpu(np->rx_ring.ex[i].flaglen); |
|
1801 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); |
|
1802 vlanflags = le32_to_cpu(np->rx_ring.ex[i].buflow); |
|
1803 } |
|
1804 |
|
1805 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, flags 0x%x.\n", |
|
1806 dev->name, np->cur_rx, flags); |
|
1807 |
|
1808 if (flags & NV_RX_AVAIL) |
|
1809 break; /* still owned by hardware, */ |
|
1810 |
|
1811 /* |
|
1812 * the packet is for us - immediately tear down the pci mapping. |
|
1813 * TODO: check if a prefetch of the first cacheline improves |
|
1814 * the performance. |
|
1815 */ |
|
1816 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1817 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1818 PCI_DMA_FROMDEVICE); |
|
1819 |
|
1820 { |
|
1821 int j; |
|
1822 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags); |
|
1823 for (j=0; j<64; j++) { |
|
1824 if ((j%16) == 0) |
|
1825 dprintk("\n%03x:", j); |
|
1826 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); |
|
1827 } |
|
1828 dprintk("\n"); |
|
1829 } |
|
1830 /* look at what we actually got: */ |
|
1831 if (np->desc_ver == DESC_VER_1) { |
|
1832 if (!(flags & NV_RX_DESCRIPTORVALID)) |
|
1833 goto next_pkt; |
|
1834 |
|
1835 if (flags & NV_RX_ERROR) { |
|
1836 if (flags & NV_RX_MISSEDFRAME) { |
|
1837 np->stats.rx_missed_errors++; |
|
1838 np->stats.rx_errors++; |
|
1839 goto next_pkt; |
|
1840 } |
|
1841 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
|
1842 np->stats.rx_errors++; |
|
1843 goto next_pkt; |
|
1844 } |
|
1845 if (flags & NV_RX_CRCERR) { |
|
1846 np->stats.rx_crc_errors++; |
|
1847 np->stats.rx_errors++; |
|
1848 goto next_pkt; |
|
1849 } |
|
1850 if (flags & NV_RX_OVERFLOW) { |
|
1851 np->stats.rx_over_errors++; |
|
1852 np->stats.rx_errors++; |
|
1853 goto next_pkt; |
|
1854 } |
|
1855 if (flags & NV_RX_ERROR4) { |
|
1856 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1857 if (len < 0) { |
|
1858 np->stats.rx_errors++; |
|
1859 goto next_pkt; |
|
1860 } |
|
1861 } |
|
1862 /* framing errors are soft errors. */ |
|
1863 if (flags & NV_RX_FRAMINGERR) { |
|
1864 if (flags & NV_RX_SUBSTRACT1) { |
|
1865 len--; |
|
1866 } |
|
1867 } |
|
1868 } |
|
1869 } else { |
|
1870 if (!(flags & NV_RX2_DESCRIPTORVALID)) |
|
1871 goto next_pkt; |
|
1872 |
|
1873 if (flags & NV_RX2_ERROR) { |
|
1874 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { |
|
1875 np->stats.rx_errors++; |
|
1876 goto next_pkt; |
|
1877 } |
|
1878 if (flags & NV_RX2_CRCERR) { |
|
1879 np->stats.rx_crc_errors++; |
|
1880 np->stats.rx_errors++; |
|
1881 goto next_pkt; |
|
1882 } |
|
1883 if (flags & NV_RX2_OVERFLOW) { |
|
1884 np->stats.rx_over_errors++; |
|
1885 np->stats.rx_errors++; |
|
1886 goto next_pkt; |
|
1887 } |
|
1888 if (flags & NV_RX2_ERROR4) { |
|
1889 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1890 if (len < 0) { |
|
1891 np->stats.rx_errors++; |
|
1892 goto next_pkt; |
|
1893 } |
|
1894 } |
|
1895 /* framing errors are soft errors */ |
|
1896 if (flags & NV_RX2_FRAMINGERR) { |
|
1897 if (flags & NV_RX2_SUBSTRACT1) { |
|
1898 len--; |
|
1899 } |
|
1900 } |
|
1901 } |
|
1902 if (np->rx_csum) { |
|
1903 flags &= NV_RX2_CHECKSUMMASK; |
|
1904 if (flags == NV_RX2_CHECKSUMOK1 || |
|
1905 flags == NV_RX2_CHECKSUMOK2 || |
|
1906 flags == NV_RX2_CHECKSUMOK3) { |
|
1907 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); |
|
1908 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; |
|
1909 } else { |
|
1910 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); |
|
1911 } |
|
1912 } |
|
1913 } |
|
1914 /* got a valid packet - forward it to the network core */ |
|
1915 skb = np->rx_skbuff[i]; |
|
1916 np->rx_skbuff[i] = NULL; |
|
1917 |
|
1918 skb_put(skb, len); |
|
1919 skb->protocol = eth_type_trans(skb, dev); |
|
1920 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", |
|
1921 dev->name, np->cur_rx, len, skb->protocol); |
|
1922 #ifdef CONFIG_FORCEDETH_NAPI |
|
1923 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) |
|
1924 vlan_hwaccel_receive_skb(skb, np->vlangrp, |
|
1925 vlanflags & NV_RX3_VLAN_TAG_MASK); |
|
1926 else |
|
1927 netif_receive_skb(skb); |
|
1928 #else |
|
1929 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) |
|
1930 vlan_hwaccel_rx(skb, np->vlangrp, |
|
1931 vlanflags & NV_RX3_VLAN_TAG_MASK); |
|
1932 else |
|
1933 netif_rx(skb); |
|
1934 #endif |
|
1935 dev->last_rx = jiffies; |
|
1936 np->stats.rx_packets++; |
|
1937 np->stats.rx_bytes += len; |
|
1938 next_pkt: |
|
1939 np->cur_rx++; |
|
1940 } |
|
1941 |
|
1942 return count; |
|
1943 } |
|
1944 |
|
1945 static void set_bufsize(struct net_device *dev) |
|
1946 { |
|
1947 struct fe_priv *np = netdev_priv(dev); |
|
1948 |
|
1949 if (dev->mtu <= ETH_DATA_LEN) |
|
1950 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; |
|
1951 else |
|
1952 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; |
|
1953 } |
|
1954 |
|
1955 /* |
|
1956 * nv_change_mtu: dev->change_mtu function |
|
1957 * Called with dev_base_lock held for read. |
|
1958 */ |
|
1959 static int nv_change_mtu(struct net_device *dev, int new_mtu) |
|
1960 { |
|
1961 struct fe_priv *np = netdev_priv(dev); |
|
1962 int old_mtu; |
|
1963 |
|
1964 if (new_mtu < 64 || new_mtu > np->pkt_limit) |
|
1965 return -EINVAL; |
|
1966 |
|
1967 old_mtu = dev->mtu; |
|
1968 dev->mtu = new_mtu; |
|
1969 |
|
1970 /* return early if the buffer sizes will not change */ |
|
1971 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) |
|
1972 return 0; |
|
1973 if (old_mtu == new_mtu) |
|
1974 return 0; |
|
1975 |
|
1976 /* synchronized against open : rtnl_lock() held by caller */ |
|
1977 if (netif_running(dev)) { |
|
1978 u8 __iomem *base = get_hwbase(dev); |
|
1979 /* |
|
1980 * It seems that the nic preloads valid ring entries into an |
|
1981 * internal buffer. The procedure for flushing everything is |
|
1982 * guessed, there is probably a simpler approach. |
|
1983 * Changing the MTU is a rare event, it shouldn't matter. |
|
1984 */ |
|
1985 nv_disable_irq(dev); |
|
1986 netif_tx_lock_bh(dev); |
|
1987 spin_lock(&np->lock); |
|
1988 /* stop engines */ |
|
1989 nv_stop_rx(dev); |
|
1990 nv_stop_tx(dev); |
|
1991 nv_txrx_reset(dev); |
|
1992 /* drain rx queue */ |
|
1993 nv_drain_rx(dev); |
|
1994 nv_drain_tx(dev); |
|
1995 /* reinit driver view of the rx queue */ |
|
1996 set_bufsize(dev); |
|
1997 if (nv_init_ring(dev)) { |
|
1998 if (!np->in_shutdown) |
|
1999 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2000 } |
|
2001 /* reinit nic view of the rx queue */ |
|
2002 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
2003 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
2004 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
|
2005 base + NvRegRingSizes); |
|
2006 pci_push(base); |
|
2007 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
2008 pci_push(base); |
|
2009 |
|
2010 /* restart rx engine */ |
|
2011 nv_start_rx(dev); |
|
2012 nv_start_tx(dev); |
|
2013 spin_unlock(&np->lock); |
|
2014 netif_tx_unlock_bh(dev); |
|
2015 nv_enable_irq(dev); |
|
2016 } |
|
2017 return 0; |
|
2018 } |
|
2019 |
|
2020 static void nv_copy_mac_to_hw(struct net_device *dev) |
|
2021 { |
|
2022 u8 __iomem *base = get_hwbase(dev); |
|
2023 u32 mac[2]; |
|
2024 |
|
2025 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
|
2026 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
|
2027 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
|
2028 |
|
2029 writel(mac[0], base + NvRegMacAddrA); |
|
2030 writel(mac[1], base + NvRegMacAddrB); |
|
2031 } |
|
2032 |
|
2033 /* |
|
2034 * nv_set_mac_address: dev->set_mac_address function |
|
2035 * Called with rtnl_lock() held. |
|
2036 */ |
|
2037 static int nv_set_mac_address(struct net_device *dev, void *addr) |
|
2038 { |
|
2039 struct fe_priv *np = netdev_priv(dev); |
|
2040 struct sockaddr *macaddr = (struct sockaddr*)addr; |
|
2041 |
|
2042 if (!is_valid_ether_addr(macaddr->sa_data)) |
|
2043 return -EADDRNOTAVAIL; |
|
2044 |
|
2045 /* synchronized against open : rtnl_lock() held by caller */ |
|
2046 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); |
|
2047 |
|
2048 if (netif_running(dev)) { |
|
2049 netif_tx_lock_bh(dev); |
|
2050 spin_lock_irq(&np->lock); |
|
2051 |
|
2052 /* stop rx engine */ |
|
2053 nv_stop_rx(dev); |
|
2054 |
|
2055 /* set mac address */ |
|
2056 nv_copy_mac_to_hw(dev); |
|
2057 |
|
2058 /* restart rx engine */ |
|
2059 nv_start_rx(dev); |
|
2060 spin_unlock_irq(&np->lock); |
|
2061 netif_tx_unlock_bh(dev); |
|
2062 } else { |
|
2063 nv_copy_mac_to_hw(dev); |
|
2064 } |
|
2065 return 0; |
|
2066 } |
|
2067 |
|
2068 /* |
|
2069 * nv_set_multicast: dev->set_multicast function |
|
2070 * Called with netif_tx_lock held. |
|
2071 */ |
|
2072 static void nv_set_multicast(struct net_device *dev) |
|
2073 { |
|
2074 struct fe_priv *np = netdev_priv(dev); |
|
2075 u8 __iomem *base = get_hwbase(dev); |
|
2076 u32 addr[2]; |
|
2077 u32 mask[2]; |
|
2078 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
|
2079 |
|
2080 memset(addr, 0, sizeof(addr)); |
|
2081 memset(mask, 0, sizeof(mask)); |
|
2082 |
|
2083 if (dev->flags & IFF_PROMISC) { |
|
2084 pff |= NVREG_PFF_PROMISC; |
|
2085 } else { |
|
2086 pff |= NVREG_PFF_MYADDR; |
|
2087 |
|
2088 if (dev->flags & IFF_ALLMULTI || dev->mc_list) { |
|
2089 u32 alwaysOff[2]; |
|
2090 u32 alwaysOn[2]; |
|
2091 |
|
2092 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; |
|
2093 if (dev->flags & IFF_ALLMULTI) { |
|
2094 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; |
|
2095 } else { |
|
2096 struct dev_mc_list *walk; |
|
2097 |
|
2098 walk = dev->mc_list; |
|
2099 while (walk != NULL) { |
|
2100 u32 a, b; |
|
2101 a = le32_to_cpu(*(u32 *) walk->dmi_addr); |
|
2102 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); |
|
2103 alwaysOn[0] &= a; |
|
2104 alwaysOff[0] &= ~a; |
|
2105 alwaysOn[1] &= b; |
|
2106 alwaysOff[1] &= ~b; |
|
2107 walk = walk->next; |
|
2108 } |
|
2109 } |
|
2110 addr[0] = alwaysOn[0]; |
|
2111 addr[1] = alwaysOn[1]; |
|
2112 mask[0] = alwaysOn[0] | alwaysOff[0]; |
|
2113 mask[1] = alwaysOn[1] | alwaysOff[1]; |
|
2114 } |
|
2115 } |
|
2116 addr[0] |= NVREG_MCASTADDRA_FORCE; |
|
2117 pff |= NVREG_PFF_ALWAYS; |
|
2118 spin_lock_irq(&np->lock); |
|
2119 nv_stop_rx(dev); |
|
2120 writel(addr[0], base + NvRegMulticastAddrA); |
|
2121 writel(addr[1], base + NvRegMulticastAddrB); |
|
2122 writel(mask[0], base + NvRegMulticastMaskA); |
|
2123 writel(mask[1], base + NvRegMulticastMaskB); |
|
2124 writel(pff, base + NvRegPacketFilterFlags); |
|
2125 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", |
|
2126 dev->name); |
|
2127 nv_start_rx(dev); |
|
2128 spin_unlock_irq(&np->lock); |
|
2129 } |
|
2130 |
|
2131 static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
|
2132 { |
|
2133 struct fe_priv *np = netdev_priv(dev); |
|
2134 u8 __iomem *base = get_hwbase(dev); |
|
2135 |
|
2136 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); |
|
2137 |
|
2138 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { |
|
2139 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; |
|
2140 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { |
|
2141 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); |
|
2142 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
2143 } else { |
|
2144 writel(pff, base + NvRegPacketFilterFlags); |
|
2145 } |
|
2146 } |
|
2147 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { |
|
2148 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; |
|
2149 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { |
|
2150 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame); |
|
2151 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
|
2152 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
2153 } else { |
|
2154 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
|
2155 writel(regmisc, base + NvRegMisc1); |
|
2156 } |
|
2157 } |
|
2158 } |
|
2159 |
|
2160 /** |
|
2161 * nv_update_linkspeed: Setup the MAC according to the link partner |
|
2162 * @dev: Network device to be configured |
|
2163 * |
|
2164 * The function queries the PHY and checks if there is a link partner. |
|
2165 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is |
|
2166 * set to 10 MBit HD. |
|
2167 * |
|
2168 * The function returns 0 if there is no link partner and 1 if there is |
|
2169 * a good link partner. |
|
2170 */ |
|
2171 static int nv_update_linkspeed(struct net_device *dev) |
|
2172 { |
|
2173 struct fe_priv *np = netdev_priv(dev); |
|
2174 u8 __iomem *base = get_hwbase(dev); |
|
2175 int adv = 0; |
|
2176 int lpa = 0; |
|
2177 int adv_lpa, adv_pause, lpa_pause; |
|
2178 int newls = np->linkspeed; |
|
2179 int newdup = np->duplex; |
|
2180 int mii_status; |
|
2181 int retval = 0; |
|
2182 u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
|
2183 |
|
2184 /* BMSR_LSTATUS is latched, read it twice: |
|
2185 * we want the current value. |
|
2186 */ |
|
2187 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
2188 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
2189 |
|
2190 if (!(mii_status & BMSR_LSTATUS)) { |
|
2191 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", |
|
2192 dev->name); |
|
2193 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2194 newdup = 0; |
|
2195 retval = 0; |
|
2196 goto set_speed; |
|
2197 } |
|
2198 |
|
2199 if (np->autoneg == 0) { |
|
2200 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
|
2201 dev->name, np->fixed_mode); |
|
2202 if (np->fixed_mode & LPA_100FULL) { |
|
2203 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
2204 newdup = 1; |
|
2205 } else if (np->fixed_mode & LPA_100HALF) { |
|
2206 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
2207 newdup = 0; |
|
2208 } else if (np->fixed_mode & LPA_10FULL) { |
|
2209 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2210 newdup = 1; |
|
2211 } else { |
|
2212 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2213 newdup = 0; |
|
2214 } |
|
2215 retval = 1; |
|
2216 goto set_speed; |
|
2217 } |
|
2218 /* check auto negotiation is complete */ |
|
2219 if (!(mii_status & BMSR_ANEGCOMPLETE)) { |
|
2220 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ |
|
2221 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2222 newdup = 0; |
|
2223 retval = 0; |
|
2224 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); |
|
2225 goto set_speed; |
|
2226 } |
|
2227 |
|
2228 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2229 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
|
2230 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
|
2231 dev->name, adv, lpa); |
|
2232 |
|
2233 retval = 1; |
|
2234 if (np->gigabit == PHY_GIGABIT) { |
|
2235 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
|
2236 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); |
|
2237 |
|
2238 if ((control_1000 & ADVERTISE_1000FULL) && |
|
2239 (status_1000 & LPA_1000FULL)) { |
|
2240 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", |
|
2241 dev->name); |
|
2242 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
|
2243 newdup = 1; |
|
2244 goto set_speed; |
|
2245 } |
|
2246 } |
|
2247 |
|
2248 /* FIXME: handle parallel detection properly */ |
|
2249 adv_lpa = lpa & adv; |
|
2250 if (adv_lpa & LPA_100FULL) { |
|
2251 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
2252 newdup = 1; |
|
2253 } else if (adv_lpa & LPA_100HALF) { |
|
2254 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
2255 newdup = 0; |
|
2256 } else if (adv_lpa & LPA_10FULL) { |
|
2257 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2258 newdup = 1; |
|
2259 } else if (adv_lpa & LPA_10HALF) { |
|
2260 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2261 newdup = 0; |
|
2262 } else { |
|
2263 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa); |
|
2264 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2265 newdup = 0; |
|
2266 } |
|
2267 |
|
2268 set_speed: |
|
2269 if (np->duplex == newdup && np->linkspeed == newls) |
|
2270 return retval; |
|
2271 |
|
2272 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", |
|
2273 dev->name, np->linkspeed, np->duplex, newls, newdup); |
|
2274 |
|
2275 np->duplex = newdup; |
|
2276 np->linkspeed = newls; |
|
2277 |
|
2278 if (np->gigabit == PHY_GIGABIT) { |
|
2279 phyreg = readl(base + NvRegRandomSeed); |
|
2280 phyreg &= ~(0x3FF00); |
|
2281 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) |
|
2282 phyreg |= NVREG_RNDSEED_FORCE3; |
|
2283 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) |
|
2284 phyreg |= NVREG_RNDSEED_FORCE2; |
|
2285 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
|
2286 phyreg |= NVREG_RNDSEED_FORCE; |
|
2287 writel(phyreg, base + NvRegRandomSeed); |
|
2288 } |
|
2289 |
|
2290 phyreg = readl(base + NvRegPhyInterface); |
|
2291 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); |
|
2292 if (np->duplex == 0) |
|
2293 phyreg |= PHY_HALF; |
|
2294 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) |
|
2295 phyreg |= PHY_100; |
|
2296 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
|
2297 phyreg |= PHY_1000; |
|
2298 writel(phyreg, base + NvRegPhyInterface); |
|
2299 |
|
2300 if (phyreg & PHY_RGMII) { |
|
2301 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
|
2302 txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
|
2303 else |
|
2304 txreg = NVREG_TX_DEFERRAL_RGMII_10_100; |
|
2305 } else { |
|
2306 txreg = NVREG_TX_DEFERRAL_DEFAULT; |
|
2307 } |
|
2308 writel(txreg, base + NvRegTxDeferral); |
|
2309 |
|
2310 if (np->desc_ver == DESC_VER_1) { |
|
2311 txreg = NVREG_TX_WM_DESC1_DEFAULT; |
|
2312 } else { |
|
2313 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
|
2314 txreg = NVREG_TX_WM_DESC2_3_1000; |
|
2315 else |
|
2316 txreg = NVREG_TX_WM_DESC2_3_DEFAULT; |
|
2317 } |
|
2318 writel(txreg, base + NvRegTxWatermark); |
|
2319 |
|
2320 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
|
2321 base + NvRegMisc1); |
|
2322 pci_push(base); |
|
2323 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
2324 pci_push(base); |
|
2325 |
|
2326 pause_flags = 0; |
|
2327 /* setup pause frame */ |
|
2328 if (np->duplex != 0) { |
|
2329 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
|
2330 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM); |
|
2331 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM); |
|
2332 |
|
2333 switch (adv_pause) { |
|
2334 case ADVERTISE_PAUSE_CAP: |
|
2335 if (lpa_pause & LPA_PAUSE_CAP) { |
|
2336 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
2337 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
|
2338 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
2339 } |
|
2340 break; |
|
2341 case ADVERTISE_PAUSE_ASYM: |
|
2342 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM)) |
|
2343 { |
|
2344 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
2345 } |
|
2346 break; |
|
2347 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM: |
|
2348 if (lpa_pause & LPA_PAUSE_CAP) |
|
2349 { |
|
2350 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
2351 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
|
2352 pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
2353 } |
|
2354 if (lpa_pause == LPA_PAUSE_ASYM) |
|
2355 { |
|
2356 pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
2357 } |
|
2358 break; |
|
2359 } |
|
2360 } else { |
|
2361 pause_flags = np->pause_flags; |
|
2362 } |
|
2363 } |
|
2364 nv_update_pause(dev, pause_flags); |
|
2365 |
|
2366 return retval; |
|
2367 } |
|
2368 |
|
2369 static void nv_linkchange(struct net_device *dev) |
|
2370 { |
|
2371 if (nv_update_linkspeed(dev)) { |
|
2372 if (!netif_carrier_ok(dev)) { |
|
2373 netif_carrier_on(dev); |
|
2374 printk(KERN_INFO "%s: link up.\n", dev->name); |
|
2375 nv_start_rx(dev); |
|
2376 } |
|
2377 } else { |
|
2378 if (netif_carrier_ok(dev)) { |
|
2379 netif_carrier_off(dev); |
|
2380 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
2381 nv_stop_rx(dev); |
|
2382 } |
|
2383 } |
|
2384 } |
|
2385 |
|
2386 static void nv_link_irq(struct net_device *dev) |
|
2387 { |
|
2388 u8 __iomem *base = get_hwbase(dev); |
|
2389 u32 miistat; |
|
2390 |
|
2391 miistat = readl(base + NvRegMIIStatus); |
|
2392 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
2393 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
|
2394 |
|
2395 if (miistat & (NVREG_MIISTAT_LINKCHANGE)) |
|
2396 nv_linkchange(dev); |
|
2397 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); |
|
2398 } |
|
2399 |
|
2400 static irqreturn_t nv_nic_irq(int foo, void *data) |
|
2401 { |
|
2402 struct net_device *dev = (struct net_device *) data; |
|
2403 struct fe_priv *np = netdev_priv(dev); |
|
2404 u8 __iomem *base = get_hwbase(dev); |
|
2405 u32 events; |
|
2406 int i; |
|
2407 |
|
2408 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); |
|
2409 |
|
2410 for (i=0; ; i++) { |
|
2411 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
|
2412 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2413 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2414 } else { |
|
2415 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2416 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
|
2417 } |
|
2418 pci_push(base); |
|
2419 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2420 if (!(events & np->irqmask)) |
|
2421 break; |
|
2422 |
|
2423 spin_lock(&np->lock); |
|
2424 nv_tx_done(dev); |
|
2425 spin_unlock(&np->lock); |
|
2426 |
|
2427 if (events & NVREG_IRQ_LINK) { |
|
2428 spin_lock(&np->lock); |
|
2429 nv_link_irq(dev); |
|
2430 spin_unlock(&np->lock); |
|
2431 } |
|
2432 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2433 spin_lock(&np->lock); |
|
2434 nv_linkchange(dev); |
|
2435 spin_unlock(&np->lock); |
|
2436 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2437 } |
|
2438 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2439 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2440 dev->name, events); |
|
2441 } |
|
2442 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2443 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2444 dev->name, events); |
|
2445 } |
|
2446 #ifdef CONFIG_FORCEDETH_NAPI |
|
2447 if (events & NVREG_IRQ_RX_ALL) { |
|
2448 netif_rx_schedule(dev); |
|
2449 |
|
2450 /* Disable furthur receive irq's */ |
|
2451 spin_lock(&np->lock); |
|
2452 np->irqmask &= ~NVREG_IRQ_RX_ALL; |
|
2453 |
|
2454 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2455 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2456 else |
|
2457 writel(np->irqmask, base + NvRegIrqMask); |
|
2458 spin_unlock(&np->lock); |
|
2459 } |
|
2460 #else |
|
2461 nv_rx_process(dev, dev->weight); |
|
2462 if (nv_alloc_rx(dev)) { |
|
2463 spin_lock(&np->lock); |
|
2464 if (!np->in_shutdown) |
|
2465 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2466 spin_unlock(&np->lock); |
|
2467 } |
|
2468 #endif |
|
2469 if (i > max_interrupt_work) { |
|
2470 spin_lock(&np->lock); |
|
2471 /* disable interrupts on the nic */ |
|
2472 if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
|
2473 writel(0, base + NvRegIrqMask); |
|
2474 else |
|
2475 writel(np->irqmask, base + NvRegIrqMask); |
|
2476 pci_push(base); |
|
2477 |
|
2478 if (!np->in_shutdown) { |
|
2479 np->nic_poll_irq = np->irqmask; |
|
2480 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2481 } |
|
2482 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
|
2483 spin_unlock(&np->lock); |
|
2484 break; |
|
2485 } |
|
2486 |
|
2487 } |
|
2488 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); |
|
2489 |
|
2490 return IRQ_RETVAL(i); |
|
2491 } |
|
2492 |
|
2493 static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
|
2494 { |
|
2495 struct net_device *dev = (struct net_device *) data; |
|
2496 struct fe_priv *np = netdev_priv(dev); |
|
2497 u8 __iomem *base = get_hwbase(dev); |
|
2498 u32 events; |
|
2499 int i; |
|
2500 unsigned long flags; |
|
2501 |
|
2502 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); |
|
2503 |
|
2504 for (i=0; ; i++) { |
|
2505 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
|
2506 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
|
2507 pci_push(base); |
|
2508 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
|
2509 if (!(events & np->irqmask)) |
|
2510 break; |
|
2511 |
|
2512 spin_lock_irqsave(&np->lock, flags); |
|
2513 nv_tx_done(dev); |
|
2514 spin_unlock_irqrestore(&np->lock, flags); |
|
2515 |
|
2516 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2517 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2518 dev->name, events); |
|
2519 } |
|
2520 if (i > max_interrupt_work) { |
|
2521 spin_lock_irqsave(&np->lock, flags); |
|
2522 /* disable interrupts on the nic */ |
|
2523 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); |
|
2524 pci_push(base); |
|
2525 |
|
2526 if (!np->in_shutdown) { |
|
2527 np->nic_poll_irq |= NVREG_IRQ_TX_ALL; |
|
2528 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2529 } |
|
2530 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
|
2531 spin_unlock_irqrestore(&np->lock, flags); |
|
2532 break; |
|
2533 } |
|
2534 |
|
2535 } |
|
2536 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); |
|
2537 |
|
2538 return IRQ_RETVAL(i); |
|
2539 } |
|
2540 |
|
2541 #ifdef CONFIG_FORCEDETH_NAPI |
|
2542 static int nv_napi_poll(struct net_device *dev, int *budget) |
|
2543 { |
|
2544 int pkts, limit = min(*budget, dev->quota); |
|
2545 struct fe_priv *np = netdev_priv(dev); |
|
2546 u8 __iomem *base = get_hwbase(dev); |
|
2547 |
|
2548 pkts = nv_rx_process(dev, limit); |
|
2549 |
|
2550 if (nv_alloc_rx(dev)) { |
|
2551 spin_lock_irq(&np->lock); |
|
2552 if (!np->in_shutdown) |
|
2553 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2554 spin_unlock_irq(&np->lock); |
|
2555 } |
|
2556 |
|
2557 if (pkts < limit) { |
|
2558 /* all done, no more packets present */ |
|
2559 netif_rx_complete(dev); |
|
2560 |
|
2561 /* re-enable receive interrupts */ |
|
2562 spin_lock_irq(&np->lock); |
|
2563 np->irqmask |= NVREG_IRQ_RX_ALL; |
|
2564 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2565 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2566 else |
|
2567 writel(np->irqmask, base + NvRegIrqMask); |
|
2568 spin_unlock_irq(&np->lock); |
|
2569 return 0; |
|
2570 } else { |
|
2571 /* used up our quantum, so reschedule */ |
|
2572 dev->quota -= pkts; |
|
2573 *budget -= pkts; |
|
2574 return 1; |
|
2575 } |
|
2576 } |
|
2577 #endif |
|
2578 |
|
2579 #ifdef CONFIG_FORCEDETH_NAPI |
|
2580 static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
|
2581 { |
|
2582 struct net_device *dev = (struct net_device *) data; |
|
2583 u8 __iomem *base = get_hwbase(dev); |
|
2584 u32 events; |
|
2585 |
|
2586 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
|
2587 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
|
2588 |
|
2589 if (events) { |
|
2590 netif_rx_schedule(dev); |
|
2591 /* disable receive interrupts on the nic */ |
|
2592 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2593 pci_push(base); |
|
2594 } |
|
2595 return IRQ_HANDLED; |
|
2596 } |
|
2597 #else |
|
2598 static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
|
2599 { |
|
2600 struct net_device *dev = (struct net_device *) data; |
|
2601 struct fe_priv *np = netdev_priv(dev); |
|
2602 u8 __iomem *base = get_hwbase(dev); |
|
2603 u32 events; |
|
2604 int i; |
|
2605 unsigned long flags; |
|
2606 |
|
2607 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); |
|
2608 |
|
2609 for (i=0; ; i++) { |
|
2610 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
|
2611 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
|
2612 pci_push(base); |
|
2613 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
|
2614 if (!(events & np->irqmask)) |
|
2615 break; |
|
2616 |
|
2617 nv_rx_process(dev, dev->weight); |
|
2618 if (nv_alloc_rx(dev)) { |
|
2619 spin_lock_irqsave(&np->lock, flags); |
|
2620 if (!np->in_shutdown) |
|
2621 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2622 spin_unlock_irqrestore(&np->lock, flags); |
|
2623 } |
|
2624 |
|
2625 if (i > max_interrupt_work) { |
|
2626 spin_lock_irqsave(&np->lock, flags); |
|
2627 /* disable interrupts on the nic */ |
|
2628 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2629 pci_push(base); |
|
2630 |
|
2631 if (!np->in_shutdown) { |
|
2632 np->nic_poll_irq |= NVREG_IRQ_RX_ALL; |
|
2633 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2634 } |
|
2635 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
|
2636 spin_unlock_irqrestore(&np->lock, flags); |
|
2637 break; |
|
2638 } |
|
2639 } |
|
2640 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); |
|
2641 |
|
2642 return IRQ_RETVAL(i); |
|
2643 } |
|
2644 #endif |
|
2645 |
|
2646 static irqreturn_t nv_nic_irq_other(int foo, void *data) |
|
2647 { |
|
2648 struct net_device *dev = (struct net_device *) data; |
|
2649 struct fe_priv *np = netdev_priv(dev); |
|
2650 u8 __iomem *base = get_hwbase(dev); |
|
2651 u32 events; |
|
2652 int i; |
|
2653 unsigned long flags; |
|
2654 |
|
2655 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); |
|
2656 |
|
2657 for (i=0; ; i++) { |
|
2658 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
|
2659 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
|
2660 pci_push(base); |
|
2661 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2662 if (!(events & np->irqmask)) |
|
2663 break; |
|
2664 |
|
2665 if (events & NVREG_IRQ_LINK) { |
|
2666 spin_lock_irqsave(&np->lock, flags); |
|
2667 nv_link_irq(dev); |
|
2668 spin_unlock_irqrestore(&np->lock, flags); |
|
2669 } |
|
2670 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2671 spin_lock_irqsave(&np->lock, flags); |
|
2672 nv_linkchange(dev); |
|
2673 spin_unlock_irqrestore(&np->lock, flags); |
|
2674 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2675 } |
|
2676 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2677 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2678 dev->name, events); |
|
2679 } |
|
2680 if (i > max_interrupt_work) { |
|
2681 spin_lock_irqsave(&np->lock, flags); |
|
2682 /* disable interrupts on the nic */ |
|
2683 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); |
|
2684 pci_push(base); |
|
2685 |
|
2686 if (!np->in_shutdown) { |
|
2687 np->nic_poll_irq |= NVREG_IRQ_OTHER; |
|
2688 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2689 } |
|
2690 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
|
2691 spin_unlock_irqrestore(&np->lock, flags); |
|
2692 break; |
|
2693 } |
|
2694 |
|
2695 } |
|
2696 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); |
|
2697 |
|
2698 return IRQ_RETVAL(i); |
|
2699 } |
|
2700 |
|
2701 static irqreturn_t nv_nic_irq_test(int foo, void *data) |
|
2702 { |
|
2703 struct net_device *dev = (struct net_device *) data; |
|
2704 struct fe_priv *np = netdev_priv(dev); |
|
2705 u8 __iomem *base = get_hwbase(dev); |
|
2706 u32 events; |
|
2707 |
|
2708 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name); |
|
2709 |
|
2710 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
|
2711 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2712 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); |
|
2713 } else { |
|
2714 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2715 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); |
|
2716 } |
|
2717 pci_push(base); |
|
2718 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2719 if (!(events & NVREG_IRQ_TIMER)) |
|
2720 return IRQ_RETVAL(0); |
|
2721 |
|
2722 spin_lock(&np->lock); |
|
2723 np->intr_test = 1; |
|
2724 spin_unlock(&np->lock); |
|
2725 |
|
2726 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); |
|
2727 |
|
2728 return IRQ_RETVAL(1); |
|
2729 } |
|
2730 |
|
2731 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
|
2732 { |
|
2733 u8 __iomem *base = get_hwbase(dev); |
|
2734 int i; |
|
2735 u32 msixmap = 0; |
|
2736 |
|
2737 /* Each interrupt bit can be mapped to a MSIX vector (4 bits). |
|
2738 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents |
|
2739 * the remaining 8 interrupts. |
|
2740 */ |
|
2741 for (i = 0; i < 8; i++) { |
|
2742 if ((irqmask >> i) & 0x1) { |
|
2743 msixmap |= vector << (i << 2); |
|
2744 } |
|
2745 } |
|
2746 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); |
|
2747 |
|
2748 msixmap = 0; |
|
2749 for (i = 0; i < 8; i++) { |
|
2750 if ((irqmask >> (i + 8)) & 0x1) { |
|
2751 msixmap |= vector << (i << 2); |
|
2752 } |
|
2753 } |
|
2754 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
|
2755 } |
|
2756 |
|
2757 static int nv_request_irq(struct net_device *dev, int intr_test) |
|
2758 { |
|
2759 struct fe_priv *np = get_nvpriv(dev); |
|
2760 u8 __iomem *base = get_hwbase(dev); |
|
2761 int ret = 1; |
|
2762 int i; |
|
2763 |
|
2764 if (np->msi_flags & NV_MSI_X_CAPABLE) { |
|
2765 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2766 np->msi_x_entry[i].entry = i; |
|
2767 } |
|
2768 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { |
|
2769 np->msi_flags |= NV_MSI_X_ENABLED; |
|
2770 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
|
2771 /* Request irq for rx handling */ |
|
2772 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) { |
|
2773 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
|
2774 pci_disable_msix(np->pci_dev); |
|
2775 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2776 goto out_err; |
|
2777 } |
|
2778 /* Request irq for tx handling */ |
|
2779 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) { |
|
2780 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
|
2781 pci_disable_msix(np->pci_dev); |
|
2782 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2783 goto out_free_rx; |
|
2784 } |
|
2785 /* Request irq for link and timer handling */ |
|
2786 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) { |
|
2787 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
|
2788 pci_disable_msix(np->pci_dev); |
|
2789 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2790 goto out_free_tx; |
|
2791 } |
|
2792 /* map interrupts to their respective vector */ |
|
2793 writel(0, base + NvRegMSIXMap0); |
|
2794 writel(0, base + NvRegMSIXMap1); |
|
2795 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
|
2796 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
|
2797 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
|
2798 } else { |
|
2799 /* Request irq for all interrupts */ |
|
2800 if ((!intr_test && |
|
2801 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
|
2802 (intr_test && |
|
2803 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) { |
|
2804 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2805 pci_disable_msix(np->pci_dev); |
|
2806 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2807 goto out_err; |
|
2808 } |
|
2809 |
|
2810 /* map interrupts to vector 0 */ |
|
2811 writel(0, base + NvRegMSIXMap0); |
|
2812 writel(0, base + NvRegMSIXMap1); |
|
2813 } |
|
2814 } |
|
2815 } |
|
2816 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
|
2817 if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
|
2818 pci_intx(np->pci_dev, 0); |
|
2819 np->msi_flags |= NV_MSI_ENABLED; |
|
2820 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
|
2821 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) { |
|
2822 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2823 pci_disable_msi(np->pci_dev); |
|
2824 pci_intx(np->pci_dev, 1); |
|
2825 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2826 goto out_err; |
|
2827 } |
|
2828 |
|
2829 /* map interrupts to vector 0 */ |
|
2830 writel(0, base + NvRegMSIMap0); |
|
2831 writel(0, base + NvRegMSIMap1); |
|
2832 /* enable msi vector 0 */ |
|
2833 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
|
2834 } |
|
2835 } |
|
2836 if (ret != 0) { |
|
2837 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
|
2838 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) |
|
2839 goto out_err; |
|
2840 |
|
2841 } |
|
2842 |
|
2843 return 0; |
|
2844 out_free_tx: |
|
2845 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
|
2846 out_free_rx: |
|
2847 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
|
2848 out_err: |
|
2849 return 1; |
|
2850 } |
|
2851 |
|
2852 static void nv_free_irq(struct net_device *dev) |
|
2853 { |
|
2854 struct fe_priv *np = get_nvpriv(dev); |
|
2855 int i; |
|
2856 |
|
2857 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
2858 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2859 free_irq(np->msi_x_entry[i].vector, dev); |
|
2860 } |
|
2861 pci_disable_msix(np->pci_dev); |
|
2862 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2863 } else { |
|
2864 free_irq(np->pci_dev->irq, dev); |
|
2865 if (np->msi_flags & NV_MSI_ENABLED) { |
|
2866 pci_disable_msi(np->pci_dev); |
|
2867 pci_intx(np->pci_dev, 1); |
|
2868 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2869 } |
|
2870 } |
|
2871 } |
|
2872 |
|
2873 static void nv_do_nic_poll(unsigned long data) |
|
2874 { |
|
2875 struct net_device *dev = (struct net_device *) data; |
|
2876 struct fe_priv *np = netdev_priv(dev); |
|
2877 u8 __iomem *base = get_hwbase(dev); |
|
2878 u32 mask = 0; |
|
2879 |
|
2880 /* |
|
2881 * First disable irq(s) and then |
|
2882 * reenable interrupts on the nic, we have to do this before calling |
|
2883 * nv_nic_irq because that may decide to do otherwise |
|
2884 */ |
|
2885 |
|
2886 if (!using_multi_irqs(dev)) { |
|
2887 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2888 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2889 else |
|
2890 disable_irq_lockdep(dev->irq); |
|
2891 mask = np->irqmask; |
|
2892 } else { |
|
2893 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2894 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2895 mask |= NVREG_IRQ_RX_ALL; |
|
2896 } |
|
2897 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2898 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2899 mask |= NVREG_IRQ_TX_ALL; |
|
2900 } |
|
2901 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2902 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2903 mask |= NVREG_IRQ_OTHER; |
|
2904 } |
|
2905 } |
|
2906 np->nic_poll_irq = 0; |
|
2907 |
|
2908 /* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
|
2909 |
|
2910 writel(mask, base + NvRegIrqMask); |
|
2911 pci_push(base); |
|
2912 |
|
2913 if (!using_multi_irqs(dev)) { |
|
2914 nv_nic_irq(0, dev); |
|
2915 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2916 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2917 else |
|
2918 enable_irq_lockdep(dev->irq); |
|
2919 } else { |
|
2920 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2921 nv_nic_irq_rx(0, dev); |
|
2922 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2923 } |
|
2924 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2925 nv_nic_irq_tx(0, dev); |
|
2926 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2927 } |
|
2928 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2929 nv_nic_irq_other(0, dev); |
|
2930 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2931 } |
|
2932 } |
|
2933 } |
|
2934 |
|
2935 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2936 static void nv_poll_controller(struct net_device *dev) |
|
2937 { |
|
2938 nv_do_nic_poll((unsigned long) dev); |
|
2939 } |
|
2940 #endif |
|
2941 |
|
2942 static void nv_do_stats_poll(unsigned long data) |
|
2943 { |
|
2944 struct net_device *dev = (struct net_device *) data; |
|
2945 struct fe_priv *np = netdev_priv(dev); |
|
2946 u8 __iomem *base = get_hwbase(dev); |
|
2947 |
|
2948 np->estats.tx_bytes += readl(base + NvRegTxCnt); |
|
2949 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); |
|
2950 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); |
|
2951 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); |
|
2952 np->estats.tx_late_collision += readl(base + NvRegTxLateCol); |
|
2953 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); |
|
2954 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); |
|
2955 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); |
|
2956 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); |
|
2957 np->estats.tx_deferral += readl(base + NvRegTxDef); |
|
2958 np->estats.tx_packets += readl(base + NvRegTxFrame); |
|
2959 np->estats.tx_pause += readl(base + NvRegTxPause); |
|
2960 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); |
|
2961 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); |
|
2962 np->estats.rx_late_collision += readl(base + NvRegRxLateCol); |
|
2963 np->estats.rx_runt += readl(base + NvRegRxRunt); |
|
2964 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); |
|
2965 np->estats.rx_over_errors += readl(base + NvRegRxOverflow); |
|
2966 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); |
|
2967 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); |
|
2968 np->estats.rx_length_error += readl(base + NvRegRxLenErr); |
|
2969 np->estats.rx_unicast += readl(base + NvRegRxUnicast); |
|
2970 np->estats.rx_multicast += readl(base + NvRegRxMulticast); |
|
2971 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); |
|
2972 np->estats.rx_bytes += readl(base + NvRegRxCnt); |
|
2973 np->estats.rx_pause += readl(base + NvRegRxPause); |
|
2974 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); |
|
2975 np->estats.rx_packets = |
|
2976 np->estats.rx_unicast + |
|
2977 np->estats.rx_multicast + |
|
2978 np->estats.rx_broadcast; |
|
2979 np->estats.rx_errors_total = |
|
2980 np->estats.rx_crc_errors + |
|
2981 np->estats.rx_over_errors + |
|
2982 np->estats.rx_frame_error + |
|
2983 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + |
|
2984 np->estats.rx_late_collision + |
|
2985 np->estats.rx_runt + |
|
2986 np->estats.rx_frame_too_long; |
|
2987 |
|
2988 if (!np->in_shutdown) |
|
2989 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
|
2990 } |
|
2991 |
|
2992 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
|
2993 { |
|
2994 struct fe_priv *np = netdev_priv(dev); |
|
2995 strcpy(info->driver, "forcedeth"); |
|
2996 strcpy(info->version, FORCEDETH_VERSION); |
|
2997 strcpy(info->bus_info, pci_name(np->pci_dev)); |
|
2998 } |
|
2999 |
|
3000 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
3001 { |
|
3002 struct fe_priv *np = netdev_priv(dev); |
|
3003 wolinfo->supported = WAKE_MAGIC; |
|
3004 |
|
3005 spin_lock_irq(&np->lock); |
|
3006 if (np->wolenabled) |
|
3007 wolinfo->wolopts = WAKE_MAGIC; |
|
3008 spin_unlock_irq(&np->lock); |
|
3009 } |
|
3010 |
|
3011 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
3012 { |
|
3013 struct fe_priv *np = netdev_priv(dev); |
|
3014 u8 __iomem *base = get_hwbase(dev); |
|
3015 u32 flags = 0; |
|
3016 |
|
3017 if (wolinfo->wolopts == 0) { |
|
3018 np->wolenabled = 0; |
|
3019 } else if (wolinfo->wolopts & WAKE_MAGIC) { |
|
3020 np->wolenabled = 1; |
|
3021 flags = NVREG_WAKEUPFLAGS_ENABLE; |
|
3022 } |
|
3023 if (netif_running(dev)) { |
|
3024 spin_lock_irq(&np->lock); |
|
3025 writel(flags, base + NvRegWakeUpFlags); |
|
3026 spin_unlock_irq(&np->lock); |
|
3027 } |
|
3028 return 0; |
|
3029 } |
|
3030 |
|
3031 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
3032 { |
|
3033 struct fe_priv *np = netdev_priv(dev); |
|
3034 int adv; |
|
3035 |
|
3036 spin_lock_irq(&np->lock); |
|
3037 ecmd->port = PORT_MII; |
|
3038 if (!netif_running(dev)) { |
|
3039 /* We do not track link speed / duplex setting if the |
|
3040 * interface is disabled. Force a link check */ |
|
3041 if (nv_update_linkspeed(dev)) { |
|
3042 if (!netif_carrier_ok(dev)) |
|
3043 netif_carrier_on(dev); |
|
3044 } else { |
|
3045 if (netif_carrier_ok(dev)) |
|
3046 netif_carrier_off(dev); |
|
3047 } |
|
3048 } |
|
3049 |
|
3050 if (netif_carrier_ok(dev)) { |
|
3051 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
|
3052 case NVREG_LINKSPEED_10: |
|
3053 ecmd->speed = SPEED_10; |
|
3054 break; |
|
3055 case NVREG_LINKSPEED_100: |
|
3056 ecmd->speed = SPEED_100; |
|
3057 break; |
|
3058 case NVREG_LINKSPEED_1000: |
|
3059 ecmd->speed = SPEED_1000; |
|
3060 break; |
|
3061 } |
|
3062 ecmd->duplex = DUPLEX_HALF; |
|
3063 if (np->duplex) |
|
3064 ecmd->duplex = DUPLEX_FULL; |
|
3065 } else { |
|
3066 ecmd->speed = -1; |
|
3067 ecmd->duplex = -1; |
|
3068 } |
|
3069 |
|
3070 ecmd->autoneg = np->autoneg; |
|
3071 |
|
3072 ecmd->advertising = ADVERTISED_MII; |
|
3073 if (np->autoneg) { |
|
3074 ecmd->advertising |= ADVERTISED_Autoneg; |
|
3075 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
3076 if (adv & ADVERTISE_10HALF) |
|
3077 ecmd->advertising |= ADVERTISED_10baseT_Half; |
|
3078 if (adv & ADVERTISE_10FULL) |
|
3079 ecmd->advertising |= ADVERTISED_10baseT_Full; |
|
3080 if (adv & ADVERTISE_100HALF) |
|
3081 ecmd->advertising |= ADVERTISED_100baseT_Half; |
|
3082 if (adv & ADVERTISE_100FULL) |
|
3083 ecmd->advertising |= ADVERTISED_100baseT_Full; |
|
3084 if (np->gigabit == PHY_GIGABIT) { |
|
3085 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
|
3086 if (adv & ADVERTISE_1000FULL) |
|
3087 ecmd->advertising |= ADVERTISED_1000baseT_Full; |
|
3088 } |
|
3089 } |
|
3090 ecmd->supported = (SUPPORTED_Autoneg | |
|
3091 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
|
3092 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | |
|
3093 SUPPORTED_MII); |
|
3094 if (np->gigabit == PHY_GIGABIT) |
|
3095 ecmd->supported |= SUPPORTED_1000baseT_Full; |
|
3096 |
|
3097 ecmd->phy_address = np->phyaddr; |
|
3098 ecmd->transceiver = XCVR_EXTERNAL; |
|
3099 |
|
3100 /* ignore maxtxpkt, maxrxpkt for now */ |
|
3101 spin_unlock_irq(&np->lock); |
|
3102 return 0; |
|
3103 } |
|
3104 |
|
3105 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
3106 { |
|
3107 struct fe_priv *np = netdev_priv(dev); |
|
3108 |
|
3109 if (ecmd->port != PORT_MII) |
|
3110 return -EINVAL; |
|
3111 if (ecmd->transceiver != XCVR_EXTERNAL) |
|
3112 return -EINVAL; |
|
3113 if (ecmd->phy_address != np->phyaddr) { |
|
3114 /* TODO: support switching between multiple phys. Should be |
|
3115 * trivial, but not enabled due to lack of test hardware. */ |
|
3116 return -EINVAL; |
|
3117 } |
|
3118 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
3119 u32 mask; |
|
3120 |
|
3121 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
3122 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; |
|
3123 if (np->gigabit == PHY_GIGABIT) |
|
3124 mask |= ADVERTISED_1000baseT_Full; |
|
3125 |
|
3126 if ((ecmd->advertising & mask) == 0) |
|
3127 return -EINVAL; |
|
3128 |
|
3129 } else if (ecmd->autoneg == AUTONEG_DISABLE) { |
|
3130 /* Note: autonegotiation disable, speed 1000 intentionally |
|
3131 * forbidden - noone should need that. */ |
|
3132 |
|
3133 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) |
|
3134 return -EINVAL; |
|
3135 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) |
|
3136 return -EINVAL; |
|
3137 } else { |
|
3138 return -EINVAL; |
|
3139 } |
|
3140 |
|
3141 netif_carrier_off(dev); |
|
3142 if (netif_running(dev)) { |
|
3143 nv_disable_irq(dev); |
|
3144 netif_tx_lock_bh(dev); |
|
3145 spin_lock(&np->lock); |
|
3146 /* stop engines */ |
|
3147 nv_stop_rx(dev); |
|
3148 nv_stop_tx(dev); |
|
3149 spin_unlock(&np->lock); |
|
3150 netif_tx_unlock_bh(dev); |
|
3151 } |
|
3152 |
|
3153 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
3154 int adv, bmcr; |
|
3155 |
|
3156 np->autoneg = 1; |
|
3157 |
|
3158 /* advertise only what has been requested */ |
|
3159 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
3160 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
|
3161 if (ecmd->advertising & ADVERTISED_10baseT_Half) |
|
3162 adv |= ADVERTISE_10HALF; |
|
3163 if (ecmd->advertising & ADVERTISED_10baseT_Full) |
|
3164 adv |= ADVERTISE_10FULL; |
|
3165 if (ecmd->advertising & ADVERTISED_100baseT_Half) |
|
3166 adv |= ADVERTISE_100HALF; |
|
3167 if (ecmd->advertising & ADVERTISED_100baseT_Full) |
|
3168 adv |= ADVERTISE_100FULL; |
|
3169 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ |
|
3170 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
3171 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
|
3172 adv |= ADVERTISE_PAUSE_ASYM; |
|
3173 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
3174 |
|
3175 if (np->gigabit == PHY_GIGABIT) { |
|
3176 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
|
3177 adv &= ~ADVERTISE_1000FULL; |
|
3178 if (ecmd->advertising & ADVERTISED_1000baseT_Full) |
|
3179 adv |= ADVERTISE_1000FULL; |
|
3180 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
|
3181 } |
|
3182 |
|
3183 if (netif_running(dev)) |
|
3184 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
3185 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
3186 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
|
3187 bmcr |= BMCR_ANENABLE; |
|
3188 /* reset the phy in order for settings to stick, |
|
3189 * and cause autoneg to start */ |
|
3190 if (phy_reset(dev, bmcr)) { |
|
3191 printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
|
3192 return -EINVAL; |
|
3193 } |
|
3194 } else { |
|
3195 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
3196 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
3197 } |
|
3198 } else { |
|
3199 int adv, bmcr; |
|
3200 |
|
3201 np->autoneg = 0; |
|
3202 |
|
3203 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
3204 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
|
3205 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
|
3206 adv |= ADVERTISE_10HALF; |
|
3207 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) |
|
3208 adv |= ADVERTISE_10FULL; |
|
3209 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
|
3210 adv |= ADVERTISE_100HALF; |
|
3211 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) |
|
3212 adv |= ADVERTISE_100FULL; |
|
3213 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); |
|
3214 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */ |
|
3215 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
3216 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
3217 } |
|
3218 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { |
|
3219 adv |= ADVERTISE_PAUSE_ASYM; |
|
3220 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
3221 } |
|
3222 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
3223 np->fixed_mode = adv; |
|
3224 |
|
3225 if (np->gigabit == PHY_GIGABIT) { |
|
3226 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
|
3227 adv &= ~ADVERTISE_1000FULL; |
|
3228 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
|
3229 } |
|
3230 |
|
3231 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
3232 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
|
3233 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) |
|
3234 bmcr |= BMCR_FULLDPLX; |
|
3235 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
|
3236 bmcr |= BMCR_SPEED100; |
|
3237 if (np->phy_oui == PHY_OUI_MARVELL) { |
|
3238 /* reset the phy in order for forced mode settings to stick */ |
|
3239 if (phy_reset(dev, bmcr)) { |
|
3240 printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
|
3241 return -EINVAL; |
|
3242 } |
|
3243 } else { |
|
3244 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
3245 if (netif_running(dev)) { |
|
3246 /* Wait a bit and then reconfigure the nic. */ |
|
3247 udelay(10); |
|
3248 nv_linkchange(dev); |
|
3249 } |
|
3250 } |
|
3251 } |
|
3252 |
|
3253 if (netif_running(dev)) { |
|
3254 nv_start_rx(dev); |
|
3255 nv_start_tx(dev); |
|
3256 nv_enable_irq(dev); |
|
3257 } |
|
3258 |
|
3259 return 0; |
|
3260 } |
|
3261 |
|
3262 #define FORCEDETH_REGS_VER 1 |
|
3263 |
|
3264 static int nv_get_regs_len(struct net_device *dev) |
|
3265 { |
|
3266 struct fe_priv *np = netdev_priv(dev); |
|
3267 return np->register_size; |
|
3268 } |
|
3269 |
|
3270 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
|
3271 { |
|
3272 struct fe_priv *np = netdev_priv(dev); |
|
3273 u8 __iomem *base = get_hwbase(dev); |
|
3274 u32 *rbuf = buf; |
|
3275 int i; |
|
3276 |
|
3277 regs->version = FORCEDETH_REGS_VER; |
|
3278 spin_lock_irq(&np->lock); |
|
3279 for (i = 0;i <= np->register_size/sizeof(u32); i++) |
|
3280 rbuf[i] = readl(base + i*sizeof(u32)); |
|
3281 spin_unlock_irq(&np->lock); |
|
3282 } |
|
3283 |
|
3284 static int nv_nway_reset(struct net_device *dev) |
|
3285 { |
|
3286 struct fe_priv *np = netdev_priv(dev); |
|
3287 int ret; |
|
3288 |
|
3289 if (np->autoneg) { |
|
3290 int bmcr; |
|
3291 |
|
3292 netif_carrier_off(dev); |
|
3293 if (netif_running(dev)) { |
|
3294 nv_disable_irq(dev); |
|
3295 netif_tx_lock_bh(dev); |
|
3296 spin_lock(&np->lock); |
|
3297 /* stop engines */ |
|
3298 nv_stop_rx(dev); |
|
3299 nv_stop_tx(dev); |
|
3300 spin_unlock(&np->lock); |
|
3301 netif_tx_unlock_bh(dev); |
|
3302 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
3303 } |
|
3304 |
|
3305 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
3306 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
|
3307 bmcr |= BMCR_ANENABLE; |
|
3308 /* reset the phy in order for settings to stick*/ |
|
3309 if (phy_reset(dev, bmcr)) { |
|
3310 printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
|
3311 return -EINVAL; |
|
3312 } |
|
3313 } else { |
|
3314 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
3315 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
3316 } |
|
3317 |
|
3318 if (netif_running(dev)) { |
|
3319 nv_start_rx(dev); |
|
3320 nv_start_tx(dev); |
|
3321 nv_enable_irq(dev); |
|
3322 } |
|
3323 ret = 0; |
|
3324 } else { |
|
3325 ret = -EINVAL; |
|
3326 } |
|
3327 |
|
3328 return ret; |
|
3329 } |
|
3330 |
|
3331 static int nv_set_tso(struct net_device *dev, u32 value) |
|
3332 { |
|
3333 struct fe_priv *np = netdev_priv(dev); |
|
3334 |
|
3335 if ((np->driver_data & DEV_HAS_CHECKSUM)) |
|
3336 return ethtool_op_set_tso(dev, value); |
|
3337 else |
|
3338 return -EOPNOTSUPP; |
|
3339 } |
|
3340 |
|
3341 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
|
3342 { |
|
3343 struct fe_priv *np = netdev_priv(dev); |
|
3344 |
|
3345 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
|
3346 ring->rx_mini_max_pending = 0; |
|
3347 ring->rx_jumbo_max_pending = 0; |
|
3348 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
|
3349 |
|
3350 ring->rx_pending = np->rx_ring_size; |
|
3351 ring->rx_mini_pending = 0; |
|
3352 ring->rx_jumbo_pending = 0; |
|
3353 ring->tx_pending = np->tx_ring_size; |
|
3354 } |
|
3355 |
|
3356 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
|
3357 { |
|
3358 struct fe_priv *np = netdev_priv(dev); |
|
3359 u8 __iomem *base = get_hwbase(dev); |
|
3360 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len; |
|
3361 dma_addr_t ring_addr; |
|
3362 |
|
3363 if (ring->rx_pending < RX_RING_MIN || |
|
3364 ring->tx_pending < TX_RING_MIN || |
|
3365 ring->rx_mini_pending != 0 || |
|
3366 ring->rx_jumbo_pending != 0 || |
|
3367 (np->desc_ver == DESC_VER_1 && |
|
3368 (ring->rx_pending > RING_MAX_DESC_VER_1 || |
|
3369 ring->tx_pending > RING_MAX_DESC_VER_1)) || |
|
3370 (np->desc_ver != DESC_VER_1 && |
|
3371 (ring->rx_pending > RING_MAX_DESC_VER_2_3 || |
|
3372 ring->tx_pending > RING_MAX_DESC_VER_2_3))) { |
|
3373 return -EINVAL; |
|
3374 } |
|
3375 |
|
3376 /* allocate new rings */ |
|
3377 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3378 rxtx_ring = pci_alloc_consistent(np->pci_dev, |
|
3379 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
|
3380 &ring_addr); |
|
3381 } else { |
|
3382 rxtx_ring = pci_alloc_consistent(np->pci_dev, |
|
3383 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), |
|
3384 &ring_addr); |
|
3385 } |
|
3386 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL); |
|
3387 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL); |
|
3388 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL); |
|
3389 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL); |
|
3390 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL); |
|
3391 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) { |
|
3392 /* fall back to old rings */ |
|
3393 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3394 if (rxtx_ring) |
|
3395 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending), |
|
3396 rxtx_ring, ring_addr); |
|
3397 } else { |
|
3398 if (rxtx_ring) |
|
3399 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), |
|
3400 rxtx_ring, ring_addr); |
|
3401 } |
|
3402 if (rx_skbuff) |
|
3403 kfree(rx_skbuff); |
|
3404 if (rx_dma) |
|
3405 kfree(rx_dma); |
|
3406 if (tx_skbuff) |
|
3407 kfree(tx_skbuff); |
|
3408 if (tx_dma) |
|
3409 kfree(tx_dma); |
|
3410 if (tx_dma_len) |
|
3411 kfree(tx_dma_len); |
|
3412 goto exit; |
|
3413 } |
|
3414 |
|
3415 if (netif_running(dev)) { |
|
3416 nv_disable_irq(dev); |
|
3417 netif_tx_lock_bh(dev); |
|
3418 spin_lock(&np->lock); |
|
3419 /* stop engines */ |
|
3420 nv_stop_rx(dev); |
|
3421 nv_stop_tx(dev); |
|
3422 nv_txrx_reset(dev); |
|
3423 /* drain queues */ |
|
3424 nv_drain_rx(dev); |
|
3425 nv_drain_tx(dev); |
|
3426 /* delete queues */ |
|
3427 free_rings(dev); |
|
3428 } |
|
3429 |
|
3430 /* set new values */ |
|
3431 np->rx_ring_size = ring->rx_pending; |
|
3432 np->tx_ring_size = ring->tx_pending; |
|
3433 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE; |
|
3434 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1; |
|
3435 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3436 np->rx_ring.orig = (struct ring_desc*)rxtx_ring; |
|
3437 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
|
3438 } else { |
|
3439 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; |
|
3440 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
|
3441 } |
|
3442 np->rx_skbuff = (struct sk_buff**)rx_skbuff; |
|
3443 np->rx_dma = (dma_addr_t*)rx_dma; |
|
3444 np->tx_skbuff = (struct sk_buff**)tx_skbuff; |
|
3445 np->tx_dma = (dma_addr_t*)tx_dma; |
|
3446 np->tx_dma_len = (unsigned int*)tx_dma_len; |
|
3447 np->ring_addr = ring_addr; |
|
3448 |
|
3449 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size); |
|
3450 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size); |
|
3451 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size); |
|
3452 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size); |
|
3453 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size); |
|
3454 |
|
3455 if (netif_running(dev)) { |
|
3456 /* reinit driver view of the queues */ |
|
3457 set_bufsize(dev); |
|
3458 if (nv_init_ring(dev)) { |
|
3459 if (!np->in_shutdown) |
|
3460 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
3461 } |
|
3462 |
|
3463 /* reinit nic view of the queues */ |
|
3464 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
3465 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
3466 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
|
3467 base + NvRegRingSizes); |
|
3468 pci_push(base); |
|
3469 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
3470 pci_push(base); |
|
3471 |
|
3472 /* restart engines */ |
|
3473 nv_start_rx(dev); |
|
3474 nv_start_tx(dev); |
|
3475 spin_unlock(&np->lock); |
|
3476 netif_tx_unlock_bh(dev); |
|
3477 nv_enable_irq(dev); |
|
3478 } |
|
3479 return 0; |
|
3480 exit: |
|
3481 return -ENOMEM; |
|
3482 } |
|
3483 |
|
3484 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
|
3485 { |
|
3486 struct fe_priv *np = netdev_priv(dev); |
|
3487 |
|
3488 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; |
|
3489 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; |
|
3490 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; |
|
3491 } |
|
3492 |
|
3493 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
|
3494 { |
|
3495 struct fe_priv *np = netdev_priv(dev); |
|
3496 int adv, bmcr; |
|
3497 |
|
3498 if ((!np->autoneg && np->duplex == 0) || |
|
3499 (np->autoneg && !pause->autoneg && np->duplex == 0)) { |
|
3500 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", |
|
3501 dev->name); |
|
3502 return -EINVAL; |
|
3503 } |
|
3504 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { |
|
3505 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); |
|
3506 return -EINVAL; |
|
3507 } |
|
3508 |
|
3509 netif_carrier_off(dev); |
|
3510 if (netif_running(dev)) { |
|
3511 nv_disable_irq(dev); |
|
3512 netif_tx_lock_bh(dev); |
|
3513 spin_lock(&np->lock); |
|
3514 /* stop engines */ |
|
3515 nv_stop_rx(dev); |
|
3516 nv_stop_tx(dev); |
|
3517 spin_unlock(&np->lock); |
|
3518 netif_tx_unlock_bh(dev); |
|
3519 } |
|
3520 |
|
3521 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); |
|
3522 if (pause->rx_pause) |
|
3523 np->pause_flags |= NV_PAUSEFRAME_RX_REQ; |
|
3524 if (pause->tx_pause) |
|
3525 np->pause_flags |= NV_PAUSEFRAME_TX_REQ; |
|
3526 |
|
3527 if (np->autoneg && pause->autoneg) { |
|
3528 np->pause_flags |= NV_PAUSEFRAME_AUTONEG; |
|
3529 |
|
3530 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
3531 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
|
3532 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ |
|
3533 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
3534 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
|
3535 adv |= ADVERTISE_PAUSE_ASYM; |
|
3536 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
3537 |
|
3538 if (netif_running(dev)) |
|
3539 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
3540 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
3541 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
3542 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
3543 } else { |
|
3544 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); |
|
3545 if (pause->rx_pause) |
|
3546 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
|
3547 if (pause->tx_pause) |
|
3548 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
|
3549 |
|
3550 if (!netif_running(dev)) |
|
3551 nv_update_linkspeed(dev); |
|
3552 else |
|
3553 nv_update_pause(dev, np->pause_flags); |
|
3554 } |
|
3555 |
|
3556 if (netif_running(dev)) { |
|
3557 nv_start_rx(dev); |
|
3558 nv_start_tx(dev); |
|
3559 nv_enable_irq(dev); |
|
3560 } |
|
3561 return 0; |
|
3562 } |
|
3563 |
|
3564 static u32 nv_get_rx_csum(struct net_device *dev) |
|
3565 { |
|
3566 struct fe_priv *np = netdev_priv(dev); |
|
3567 return (np->rx_csum) != 0; |
|
3568 } |
|
3569 |
|
3570 static int nv_set_rx_csum(struct net_device *dev, u32 data) |
|
3571 { |
|
3572 struct fe_priv *np = netdev_priv(dev); |
|
3573 u8 __iomem *base = get_hwbase(dev); |
|
3574 int retcode = 0; |
|
3575 |
|
3576 if (np->driver_data & DEV_HAS_CHECKSUM) { |
|
3577 if (data) { |
|
3578 np->rx_csum = 1; |
|
3579 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
|
3580 } else { |
|
3581 np->rx_csum = 0; |
|
3582 /* vlan is dependent on rx checksum offload */ |
|
3583 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) |
|
3584 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; |
|
3585 } |
|
3586 if (netif_running(dev)) { |
|
3587 spin_lock_irq(&np->lock); |
|
3588 writel(np->txrxctl_bits, base + NvRegTxRxControl); |
|
3589 spin_unlock_irq(&np->lock); |
|
3590 } |
|
3591 } else { |
|
3592 return -EINVAL; |
|
3593 } |
|
3594 |
|
3595 return retcode; |
|
3596 } |
|
3597 |
|
3598 static int nv_set_tx_csum(struct net_device *dev, u32 data) |
|
3599 { |
|
3600 struct fe_priv *np = netdev_priv(dev); |
|
3601 |
|
3602 if (np->driver_data & DEV_HAS_CHECKSUM) |
|
3603 return ethtool_op_set_tx_hw_csum(dev, data); |
|
3604 else |
|
3605 return -EOPNOTSUPP; |
|
3606 } |
|
3607 |
|
3608 static int nv_set_sg(struct net_device *dev, u32 data) |
|
3609 { |
|
3610 struct fe_priv *np = netdev_priv(dev); |
|
3611 |
|
3612 if (np->driver_data & DEV_HAS_CHECKSUM) |
|
3613 return ethtool_op_set_sg(dev, data); |
|
3614 else |
|
3615 return -EOPNOTSUPP; |
|
3616 } |
|
3617 |
|
3618 static int nv_get_stats_count(struct net_device *dev) |
|
3619 { |
|
3620 struct fe_priv *np = netdev_priv(dev); |
|
3621 |
|
3622 if (np->driver_data & DEV_HAS_STATISTICS) |
|
3623 return sizeof(struct nv_ethtool_stats)/sizeof(u64); |
|
3624 else |
|
3625 return 0; |
|
3626 } |
|
3627 |
|
3628 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) |
|
3629 { |
|
3630 struct fe_priv *np = netdev_priv(dev); |
|
3631 |
|
3632 /* update stats */ |
|
3633 nv_do_stats_poll((unsigned long)dev); |
|
3634 |
|
3635 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64)); |
|
3636 } |
|
3637 |
|
3638 static int nv_self_test_count(struct net_device *dev) |
|
3639 { |
|
3640 struct fe_priv *np = netdev_priv(dev); |
|
3641 |
|
3642 if (np->driver_data & DEV_HAS_TEST_EXTENDED) |
|
3643 return NV_TEST_COUNT_EXTENDED; |
|
3644 else |
|
3645 return NV_TEST_COUNT_BASE; |
|
3646 } |
|
3647 |
|
3648 static int nv_link_test(struct net_device *dev) |
|
3649 { |
|
3650 struct fe_priv *np = netdev_priv(dev); |
|
3651 int mii_status; |
|
3652 |
|
3653 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
3654 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
3655 |
|
3656 /* check phy link status */ |
|
3657 if (!(mii_status & BMSR_LSTATUS)) |
|
3658 return 0; |
|
3659 else |
|
3660 return 1; |
|
3661 } |
|
3662 |
|
3663 static int nv_register_test(struct net_device *dev) |
|
3664 { |
|
3665 u8 __iomem *base = get_hwbase(dev); |
|
3666 int i = 0; |
|
3667 u32 orig_read, new_read; |
|
3668 |
|
3669 do { |
|
3670 orig_read = readl(base + nv_registers_test[i].reg); |
|
3671 |
|
3672 /* xor with mask to toggle bits */ |
|
3673 orig_read ^= nv_registers_test[i].mask; |
|
3674 |
|
3675 writel(orig_read, base + nv_registers_test[i].reg); |
|
3676 |
|
3677 new_read = readl(base + nv_registers_test[i].reg); |
|
3678 |
|
3679 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) |
|
3680 return 0; |
|
3681 |
|
3682 /* restore original value */ |
|
3683 orig_read ^= nv_registers_test[i].mask; |
|
3684 writel(orig_read, base + nv_registers_test[i].reg); |
|
3685 |
|
3686 } while (nv_registers_test[++i].reg != 0); |
|
3687 |
|
3688 return 1; |
|
3689 } |
|
3690 |
|
3691 static int nv_interrupt_test(struct net_device *dev) |
|
3692 { |
|
3693 struct fe_priv *np = netdev_priv(dev); |
|
3694 u8 __iomem *base = get_hwbase(dev); |
|
3695 int ret = 1; |
|
3696 int testcnt; |
|
3697 u32 save_msi_flags, save_poll_interval = 0; |
|
3698 |
|
3699 if (netif_running(dev)) { |
|
3700 /* free current irq */ |
|
3701 nv_free_irq(dev); |
|
3702 save_poll_interval = readl(base+NvRegPollingInterval); |
|
3703 } |
|
3704 |
|
3705 /* flag to test interrupt handler */ |
|
3706 np->intr_test = 0; |
|
3707 |
|
3708 /* setup test irq */ |
|
3709 save_msi_flags = np->msi_flags; |
|
3710 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; |
|
3711 np->msi_flags |= 0x001; /* setup 1 vector */ |
|
3712 if (nv_request_irq(dev, 1)) |
|
3713 return 0; |
|
3714 |
|
3715 /* setup timer interrupt */ |
|
3716 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); |
|
3717 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
|
3718 |
|
3719 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); |
|
3720 |
|
3721 /* wait for at least one interrupt */ |
|
3722 msleep(100); |
|
3723 |
|
3724 spin_lock_irq(&np->lock); |
|
3725 |
|
3726 /* flag should be set within ISR */ |
|
3727 testcnt = np->intr_test; |
|
3728 if (!testcnt) |
|
3729 ret = 2; |
|
3730 |
|
3731 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); |
|
3732 if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
|
3733 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
3734 else |
|
3735 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
|
3736 |
|
3737 spin_unlock_irq(&np->lock); |
|
3738 |
|
3739 nv_free_irq(dev); |
|
3740 |
|
3741 np->msi_flags = save_msi_flags; |
|
3742 |
|
3743 if (netif_running(dev)) { |
|
3744 writel(save_poll_interval, base + NvRegPollingInterval); |
|
3745 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
|
3746 /* restore original irq */ |
|
3747 if (nv_request_irq(dev, 0)) |
|
3748 return 0; |
|
3749 } |
|
3750 |
|
3751 return ret; |
|
3752 } |
|
3753 |
|
3754 static int nv_loopback_test(struct net_device *dev) |
|
3755 { |
|
3756 struct fe_priv *np = netdev_priv(dev); |
|
3757 u8 __iomem *base = get_hwbase(dev); |
|
3758 struct sk_buff *tx_skb, *rx_skb; |
|
3759 dma_addr_t test_dma_addr; |
|
3760 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
|
3761 u32 flags; |
|
3762 int len, i, pkt_len; |
|
3763 u8 *pkt_data; |
|
3764 u32 filter_flags = 0; |
|
3765 u32 misc1_flags = 0; |
|
3766 int ret = 1; |
|
3767 |
|
3768 if (netif_running(dev)) { |
|
3769 nv_disable_irq(dev); |
|
3770 filter_flags = readl(base + NvRegPacketFilterFlags); |
|
3771 misc1_flags = readl(base + NvRegMisc1); |
|
3772 } else { |
|
3773 nv_txrx_reset(dev); |
|
3774 } |
|
3775 |
|
3776 /* reinit driver view of the rx queue */ |
|
3777 set_bufsize(dev); |
|
3778 nv_init_ring(dev); |
|
3779 |
|
3780 /* setup hardware for loopback */ |
|
3781 writel(NVREG_MISC1_FORCE, base + NvRegMisc1); |
|
3782 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); |
|
3783 |
|
3784 /* reinit nic view of the rx queue */ |
|
3785 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
3786 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
3787 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
|
3788 base + NvRegRingSizes); |
|
3789 pci_push(base); |
|
3790 |
|
3791 /* restart rx engine */ |
|
3792 nv_start_rx(dev); |
|
3793 nv_start_tx(dev); |
|
3794 |
|
3795 /* setup packet for tx */ |
|
3796 pkt_len = ETH_DATA_LEN; |
|
3797 tx_skb = dev_alloc_skb(pkt_len); |
|
3798 if (!tx_skb) { |
|
3799 printk(KERN_ERR "dev_alloc_skb() failed during loopback test" |
|
3800 " of %s\n", dev->name); |
|
3801 ret = 0; |
|
3802 goto out; |
|
3803 } |
|
3804 pkt_data = skb_put(tx_skb, pkt_len); |
|
3805 for (i = 0; i < pkt_len; i++) |
|
3806 pkt_data[i] = (u8)(i & 0xff); |
|
3807 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data, |
|
3808 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE); |
|
3809 |
|
3810 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3811 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
|
3812 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
|
3813 } else { |
|
3814 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32; |
|
3815 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF; |
|
3816 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
|
3817 } |
|
3818 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
3819 pci_push(get_hwbase(dev)); |
|
3820 |
|
3821 msleep(500); |
|
3822 |
|
3823 /* check for rx of the packet */ |
|
3824 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3825 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
|
3826 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
|
3827 |
|
3828 } else { |
|
3829 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
|
3830 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
|
3831 } |
|
3832 |
|
3833 if (flags & NV_RX_AVAIL) { |
|
3834 ret = 0; |
|
3835 } else if (np->desc_ver == DESC_VER_1) { |
|
3836 if (flags & NV_RX_ERROR) |
|
3837 ret = 0; |
|
3838 } else { |
|
3839 if (flags & NV_RX2_ERROR) { |
|
3840 ret = 0; |
|
3841 } |
|
3842 } |
|
3843 |
|
3844 if (ret) { |
|
3845 if (len != pkt_len) { |
|
3846 ret = 0; |
|
3847 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", |
|
3848 dev->name, len, pkt_len); |
|
3849 } else { |
|
3850 rx_skb = np->rx_skbuff[0]; |
|
3851 for (i = 0; i < pkt_len; i++) { |
|
3852 if (rx_skb->data[i] != (u8)(i & 0xff)) { |
|
3853 ret = 0; |
|
3854 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", |
|
3855 dev->name, i); |
|
3856 break; |
|
3857 } |
|
3858 } |
|
3859 } |
|
3860 } else { |
|
3861 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name); |
|
3862 } |
|
3863 |
|
3864 pci_unmap_page(np->pci_dev, test_dma_addr, |
|
3865 tx_skb->end-tx_skb->data, |
|
3866 PCI_DMA_TODEVICE); |
|
3867 dev_kfree_skb_any(tx_skb); |
|
3868 out: |
|
3869 /* stop engines */ |
|
3870 nv_stop_rx(dev); |
|
3871 nv_stop_tx(dev); |
|
3872 nv_txrx_reset(dev); |
|
3873 /* drain rx queue */ |
|
3874 nv_drain_rx(dev); |
|
3875 nv_drain_tx(dev); |
|
3876 |
|
3877 if (netif_running(dev)) { |
|
3878 writel(misc1_flags, base + NvRegMisc1); |
|
3879 writel(filter_flags, base + NvRegPacketFilterFlags); |
|
3880 nv_enable_irq(dev); |
|
3881 } |
|
3882 |
|
3883 return ret; |
|
3884 } |
|
3885 |
|
3886 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) |
|
3887 { |
|
3888 struct fe_priv *np = netdev_priv(dev); |
|
3889 u8 __iomem *base = get_hwbase(dev); |
|
3890 int result; |
|
3891 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64)); |
|
3892 |
|
3893 if (!nv_link_test(dev)) { |
|
3894 test->flags |= ETH_TEST_FL_FAILED; |
|
3895 buffer[0] = 1; |
|
3896 } |
|
3897 |
|
3898 if (test->flags & ETH_TEST_FL_OFFLINE) { |
|
3899 if (netif_running(dev)) { |
|
3900 netif_stop_queue(dev); |
|
3901 netif_poll_disable(dev); |
|
3902 netif_tx_lock_bh(dev); |
|
3903 spin_lock_irq(&np->lock); |
|
3904 nv_disable_hw_interrupts(dev, np->irqmask); |
|
3905 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
|
3906 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
3907 } else { |
|
3908 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
|
3909 } |
|
3910 /* stop engines */ |
|
3911 nv_stop_rx(dev); |
|
3912 nv_stop_tx(dev); |
|
3913 nv_txrx_reset(dev); |
|
3914 /* drain rx queue */ |
|
3915 nv_drain_rx(dev); |
|
3916 nv_drain_tx(dev); |
|
3917 spin_unlock_irq(&np->lock); |
|
3918 netif_tx_unlock_bh(dev); |
|
3919 } |
|
3920 |
|
3921 if (!nv_register_test(dev)) { |
|
3922 test->flags |= ETH_TEST_FL_FAILED; |
|
3923 buffer[1] = 1; |
|
3924 } |
|
3925 |
|
3926 result = nv_interrupt_test(dev); |
|
3927 if (result != 1) { |
|
3928 test->flags |= ETH_TEST_FL_FAILED; |
|
3929 buffer[2] = 1; |
|
3930 } |
|
3931 if (result == 0) { |
|
3932 /* bail out */ |
|
3933 return; |
|
3934 } |
|
3935 |
|
3936 if (!nv_loopback_test(dev)) { |
|
3937 test->flags |= ETH_TEST_FL_FAILED; |
|
3938 buffer[3] = 1; |
|
3939 } |
|
3940 |
|
3941 if (netif_running(dev)) { |
|
3942 /* reinit driver view of the rx queue */ |
|
3943 set_bufsize(dev); |
|
3944 if (nv_init_ring(dev)) { |
|
3945 if (!np->in_shutdown) |
|
3946 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
3947 } |
|
3948 /* reinit nic view of the rx queue */ |
|
3949 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
3950 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
3951 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
|
3952 base + NvRegRingSizes); |
|
3953 pci_push(base); |
|
3954 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
3955 pci_push(base); |
|
3956 /* restart rx engine */ |
|
3957 nv_start_rx(dev); |
|
3958 nv_start_tx(dev); |
|
3959 netif_start_queue(dev); |
|
3960 netif_poll_enable(dev); |
|
3961 nv_enable_hw_interrupts(dev, np->irqmask); |
|
3962 } |
|
3963 } |
|
3964 } |
|
3965 |
|
3966 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
|
3967 { |
|
3968 switch (stringset) { |
|
3969 case ETH_SS_STATS: |
|
3970 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str)); |
|
3971 break; |
|
3972 case ETH_SS_TEST: |
|
3973 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str)); |
|
3974 break; |
|
3975 } |
|
3976 } |
|
3977 |
|
3978 static const struct ethtool_ops ops = { |
|
3979 .get_drvinfo = nv_get_drvinfo, |
|
3980 .get_link = ethtool_op_get_link, |
|
3981 .get_wol = nv_get_wol, |
|
3982 .set_wol = nv_set_wol, |
|
3983 .get_settings = nv_get_settings, |
|
3984 .set_settings = nv_set_settings, |
|
3985 .get_regs_len = nv_get_regs_len, |
|
3986 .get_regs = nv_get_regs, |
|
3987 .nway_reset = nv_nway_reset, |
|
3988 .get_perm_addr = ethtool_op_get_perm_addr, |
|
3989 .get_tso = ethtool_op_get_tso, |
|
3990 .set_tso = nv_set_tso, |
|
3991 .get_ringparam = nv_get_ringparam, |
|
3992 .set_ringparam = nv_set_ringparam, |
|
3993 .get_pauseparam = nv_get_pauseparam, |
|
3994 .set_pauseparam = nv_set_pauseparam, |
|
3995 .get_rx_csum = nv_get_rx_csum, |
|
3996 .set_rx_csum = nv_set_rx_csum, |
|
3997 .get_tx_csum = ethtool_op_get_tx_csum, |
|
3998 .set_tx_csum = nv_set_tx_csum, |
|
3999 .get_sg = ethtool_op_get_sg, |
|
4000 .set_sg = nv_set_sg, |
|
4001 .get_strings = nv_get_strings, |
|
4002 .get_stats_count = nv_get_stats_count, |
|
4003 .get_ethtool_stats = nv_get_ethtool_stats, |
|
4004 .self_test_count = nv_self_test_count, |
|
4005 .self_test = nv_self_test, |
|
4006 }; |
|
4007 |
|
4008 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
|
4009 { |
|
4010 struct fe_priv *np = get_nvpriv(dev); |
|
4011 |
|
4012 spin_lock_irq(&np->lock); |
|
4013 |
|
4014 /* save vlan group */ |
|
4015 np->vlangrp = grp; |
|
4016 |
|
4017 if (grp) { |
|
4018 /* enable vlan on MAC */ |
|
4019 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; |
|
4020 } else { |
|
4021 /* disable vlan on MAC */ |
|
4022 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; |
|
4023 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; |
|
4024 } |
|
4025 |
|
4026 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
4027 |
|
4028 spin_unlock_irq(&np->lock); |
|
4029 }; |
|
4030 |
|
4031 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) |
|
4032 { |
|
4033 /* nothing to do */ |
|
4034 }; |
|
4035 |
|
4036 static int nv_open(struct net_device *dev) |
|
4037 { |
|
4038 struct fe_priv *np = netdev_priv(dev); |
|
4039 u8 __iomem *base = get_hwbase(dev); |
|
4040 int ret = 1; |
|
4041 int oom, i; |
|
4042 |
|
4043 dprintk(KERN_DEBUG "nv_open: begin\n"); |
|
4044 |
|
4045 /* erase previous misconfiguration */ |
|
4046 if (np->driver_data & DEV_HAS_POWER_CNTRL) |
|
4047 nv_mac_reset(dev); |
|
4048 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
4049 writel(0, base + NvRegMulticastAddrB); |
|
4050 writel(0, base + NvRegMulticastMaskA); |
|
4051 writel(0, base + NvRegMulticastMaskB); |
|
4052 writel(0, base + NvRegPacketFilterFlags); |
|
4053 |
|
4054 writel(0, base + NvRegTransmitterControl); |
|
4055 writel(0, base + NvRegReceiverControl); |
|
4056 |
|
4057 writel(0, base + NvRegAdapterControl); |
|
4058 |
|
4059 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
|
4060 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
|
4061 |
|
4062 /* initialize descriptor rings */ |
|
4063 set_bufsize(dev); |
|
4064 oom = nv_init_ring(dev); |
|
4065 |
|
4066 writel(0, base + NvRegLinkSpeed); |
|
4067 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
|
4068 nv_txrx_reset(dev); |
|
4069 writel(0, base + NvRegUnknownSetupReg6); |
|
4070 |
|
4071 np->in_shutdown = 0; |
|
4072 |
|
4073 /* give hw rings */ |
|
4074 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
4075 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
|
4076 base + NvRegRingSizes); |
|
4077 |
|
4078 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
4079 if (np->desc_ver == DESC_VER_1) |
|
4080 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); |
|
4081 else |
|
4082 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); |
|
4083 writel(np->txrxctl_bits, base + NvRegTxRxControl); |
|
4084 writel(np->vlanctl_bits, base + NvRegVlanControl); |
|
4085 pci_push(base); |
|
4086 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
|
4087 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
|
4088 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
|
4089 KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
|
4090 |
|
4091 writel(0, base + NvRegUnknownSetupReg4); |
|
4092 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
4093 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
4094 |
|
4095 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
|
4096 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
|
4097 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
|
4098 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
4099 |
|
4100 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); |
|
4101 get_random_bytes(&i, sizeof(i)); |
|
4102 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); |
|
4103 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
|
4104 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); |
|
4105 if (poll_interval == -1) { |
|
4106 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) |
|
4107 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); |
|
4108 else |
|
4109 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); |
|
4110 } |
|
4111 else |
|
4112 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
|
4113 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
|
4114 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
|
4115 base + NvRegAdapterControl); |
|
4116 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
|
4117 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); |
|
4118 if (np->wolenabled) |
|
4119 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); |
|
4120 |
|
4121 i = readl(base + NvRegPowerState); |
|
4122 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) |
|
4123 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
|
4124 |
|
4125 pci_push(base); |
|
4126 udelay(10); |
|
4127 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); |
|
4128 |
|
4129 nv_disable_hw_interrupts(dev, np->irqmask); |
|
4130 pci_push(base); |
|
4131 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
4132 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
4133 pci_push(base); |
|
4134 |
|
4135 if (nv_request_irq(dev, 0)) { |
|
4136 goto out_drain; |
|
4137 } |
|
4138 |
|
4139 /* ask for interrupts */ |
|
4140 nv_enable_hw_interrupts(dev, np->irqmask); |
|
4141 |
|
4142 spin_lock_irq(&np->lock); |
|
4143 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
4144 writel(0, base + NvRegMulticastAddrB); |
|
4145 writel(0, base + NvRegMulticastMaskA); |
|
4146 writel(0, base + NvRegMulticastMaskB); |
|
4147 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
|
4148 /* One manual link speed update: Interrupts are enabled, future link |
|
4149 * speed changes cause interrupts and are handled by nv_link_irq(). |
|
4150 */ |
|
4151 { |
|
4152 u32 miistat; |
|
4153 miistat = readl(base + NvRegMIIStatus); |
|
4154 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
4155 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
|
4156 } |
|
4157 /* set linkspeed to invalid value, thus force nv_update_linkspeed |
|
4158 * to init hw */ |
|
4159 np->linkspeed = 0; |
|
4160 ret = nv_update_linkspeed(dev); |
|
4161 nv_start_rx(dev); |
|
4162 nv_start_tx(dev); |
|
4163 netif_start_queue(dev); |
|
4164 netif_poll_enable(dev); |
|
4165 |
|
4166 if (ret) { |
|
4167 netif_carrier_on(dev); |
|
4168 } else { |
|
4169 printk("%s: no link during initialization.\n", dev->name); |
|
4170 netif_carrier_off(dev); |
|
4171 } |
|
4172 if (oom) |
|
4173 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
4174 |
|
4175 /* start statistics timer */ |
|
4176 if (np->driver_data & DEV_HAS_STATISTICS) |
|
4177 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
|
4178 |
|
4179 spin_unlock_irq(&np->lock); |
|
4180 |
|
4181 return 0; |
|
4182 out_drain: |
|
4183 drain_ring(dev); |
|
4184 return ret; |
|
4185 } |
|
4186 |
|
4187 static int nv_close(struct net_device *dev) |
|
4188 { |
|
4189 struct fe_priv *np = netdev_priv(dev); |
|
4190 u8 __iomem *base; |
|
4191 |
|
4192 spin_lock_irq(&np->lock); |
|
4193 np->in_shutdown = 1; |
|
4194 spin_unlock_irq(&np->lock); |
|
4195 netif_poll_disable(dev); |
|
4196 synchronize_irq(dev->irq); |
|
4197 |
|
4198 del_timer_sync(&np->oom_kick); |
|
4199 del_timer_sync(&np->nic_poll); |
|
4200 del_timer_sync(&np->stats_poll); |
|
4201 |
|
4202 netif_stop_queue(dev); |
|
4203 spin_lock_irq(&np->lock); |
|
4204 nv_stop_tx(dev); |
|
4205 nv_stop_rx(dev); |
|
4206 nv_txrx_reset(dev); |
|
4207 |
|
4208 /* disable interrupts on the nic or we will lock up */ |
|
4209 base = get_hwbase(dev); |
|
4210 nv_disable_hw_interrupts(dev, np->irqmask); |
|
4211 pci_push(base); |
|
4212 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); |
|
4213 |
|
4214 spin_unlock_irq(&np->lock); |
|
4215 |
|
4216 nv_free_irq(dev); |
|
4217 |
|
4218 drain_ring(dev); |
|
4219 |
|
4220 if (np->wolenabled) |
|
4221 nv_start_rx(dev); |
|
4222 |
|
4223 /* FIXME: power down nic */ |
|
4224 |
|
4225 return 0; |
|
4226 } |
|
4227 |
|
4228 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
|
4229 { |
|
4230 struct net_device *dev; |
|
4231 struct fe_priv *np; |
|
4232 unsigned long addr; |
|
4233 u8 __iomem *base; |
|
4234 int err, i; |
|
4235 u32 powerstate, txreg; |
|
4236 |
|
4237 dev = alloc_etherdev(sizeof(struct fe_priv)); |
|
4238 err = -ENOMEM; |
|
4239 if (!dev) |
|
4240 goto out; |
|
4241 |
|
4242 np = netdev_priv(dev); |
|
4243 np->pci_dev = pci_dev; |
|
4244 spin_lock_init(&np->lock); |
|
4245 SET_MODULE_OWNER(dev); |
|
4246 SET_NETDEV_DEV(dev, &pci_dev->dev); |
|
4247 |
|
4248 init_timer(&np->oom_kick); |
|
4249 np->oom_kick.data = (unsigned long) dev; |
|
4250 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ |
|
4251 init_timer(&np->nic_poll); |
|
4252 np->nic_poll.data = (unsigned long) dev; |
|
4253 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ |
|
4254 init_timer(&np->stats_poll); |
|
4255 np->stats_poll.data = (unsigned long) dev; |
|
4256 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */ |
|
4257 |
|
4258 err = pci_enable_device(pci_dev); |
|
4259 if (err) { |
|
4260 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", |
|
4261 err, pci_name(pci_dev)); |
|
4262 goto out_free; |
|
4263 } |
|
4264 |
|
4265 pci_set_master(pci_dev); |
|
4266 |
|
4267 err = pci_request_regions(pci_dev, DRV_NAME); |
|
4268 if (err < 0) |
|
4269 goto out_disable; |
|
4270 |
|
4271 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS)) |
|
4272 np->register_size = NV_PCI_REGSZ_VER2; |
|
4273 else |
|
4274 np->register_size = NV_PCI_REGSZ_VER1; |
|
4275 |
|
4276 err = -EINVAL; |
|
4277 addr = 0; |
|
4278 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
|
4279 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", |
|
4280 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), |
|
4281 pci_resource_len(pci_dev, i), |
|
4282 pci_resource_flags(pci_dev, i)); |
|
4283 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
|
4284 pci_resource_len(pci_dev, i) >= np->register_size) { |
|
4285 addr = pci_resource_start(pci_dev, i); |
|
4286 break; |
|
4287 } |
|
4288 } |
|
4289 if (i == DEVICE_COUNT_RESOURCE) { |
|
4290 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", |
|
4291 pci_name(pci_dev)); |
|
4292 goto out_relreg; |
|
4293 } |
|
4294 |
|
4295 /* copy of driver data */ |
|
4296 np->driver_data = id->driver_data; |
|
4297 |
|
4298 /* handle different descriptor versions */ |
|
4299 if (id->driver_data & DEV_HAS_HIGH_DMA) { |
|
4300 /* packet format 3: supports 40-bit addressing */ |
|
4301 np->desc_ver = DESC_VER_3; |
|
4302 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
|
4303 if (dma_64bit) { |
|
4304 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
|
4305 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", |
|
4306 pci_name(pci_dev)); |
|
4307 } else { |
|
4308 dev->features |= NETIF_F_HIGHDMA; |
|
4309 printk(KERN_INFO "forcedeth: using HIGHDMA\n"); |
|
4310 } |
|
4311 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
|
4312 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n", |
|
4313 pci_name(pci_dev)); |
|
4314 } |
|
4315 } |
|
4316 } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
|
4317 /* packet format 2: supports jumbo frames */ |
|
4318 np->desc_ver = DESC_VER_2; |
|
4319 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
|
4320 } else { |
|
4321 /* original packet format */ |
|
4322 np->desc_ver = DESC_VER_1; |
|
4323 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
|
4324 } |
|
4325 |
|
4326 np->pkt_limit = NV_PKTLIMIT_1; |
|
4327 if (id->driver_data & DEV_HAS_LARGEDESC) |
|
4328 np->pkt_limit = NV_PKTLIMIT_2; |
|
4329 |
|
4330 if (id->driver_data & DEV_HAS_CHECKSUM) { |
|
4331 np->rx_csum = 1; |
|
4332 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
|
4333 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
|
4334 #ifdef NETIF_F_TSO |
|
4335 dev->features |= NETIF_F_TSO; |
|
4336 #endif |
|
4337 } |
|
4338 |
|
4339 np->vlanctl_bits = 0; |
|
4340 if (id->driver_data & DEV_HAS_VLAN) { |
|
4341 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; |
|
4342 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; |
|
4343 dev->vlan_rx_register = nv_vlan_rx_register; |
|
4344 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; |
|
4345 } |
|
4346 |
|
4347 np->msi_flags = 0; |
|
4348 if ((id->driver_data & DEV_HAS_MSI) && msi) { |
|
4349 np->msi_flags |= NV_MSI_CAPABLE; |
|
4350 } |
|
4351 if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
|
4352 np->msi_flags |= NV_MSI_X_CAPABLE; |
|
4353 } |
|
4354 |
|
4355 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
|
4356 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) { |
|
4357 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
|
4358 } |
|
4359 |
|
4360 |
|
4361 err = -ENOMEM; |
|
4362 np->base = ioremap(addr, np->register_size); |
|
4363 if (!np->base) |
|
4364 goto out_relreg; |
|
4365 dev->base_addr = (unsigned long)np->base; |
|
4366 |
|
4367 dev->irq = pci_dev->irq; |
|
4368 |
|
4369 np->rx_ring_size = RX_RING_DEFAULT; |
|
4370 np->tx_ring_size = TX_RING_DEFAULT; |
|
4371 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE; |
|
4372 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1; |
|
4373 |
|
4374 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
4375 np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
|
4376 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size), |
|
4377 &np->ring_addr); |
|
4378 if (!np->rx_ring.orig) |
|
4379 goto out_unmap; |
|
4380 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
|
4381 } else { |
|
4382 np->rx_ring.ex = pci_alloc_consistent(pci_dev, |
|
4383 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
|
4384 &np->ring_addr); |
|
4385 if (!np->rx_ring.ex) |
|
4386 goto out_unmap; |
|
4387 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
|
4388 } |
|
4389 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL); |
|
4390 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL); |
|
4391 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL); |
|
4392 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL); |
|
4393 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL); |
|
4394 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len) |
|
4395 goto out_freering; |
|
4396 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size); |
|
4397 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size); |
|
4398 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size); |
|
4399 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size); |
|
4400 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size); |
|
4401 |
|
4402 dev->open = nv_open; |
|
4403 dev->stop = nv_close; |
|
4404 dev->hard_start_xmit = nv_start_xmit; |
|
4405 dev->get_stats = nv_get_stats; |
|
4406 dev->change_mtu = nv_change_mtu; |
|
4407 dev->set_mac_address = nv_set_mac_address; |
|
4408 dev->set_multicast_list = nv_set_multicast; |
|
4409 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
4410 dev->poll_controller = nv_poll_controller; |
|
4411 #endif |
|
4412 dev->weight = 64; |
|
4413 #ifdef CONFIG_FORCEDETH_NAPI |
|
4414 dev->poll = nv_napi_poll; |
|
4415 #endif |
|
4416 SET_ETHTOOL_OPS(dev, &ops); |
|
4417 dev->tx_timeout = nv_tx_timeout; |
|
4418 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
|
4419 |
|
4420 pci_set_drvdata(pci_dev, dev); |
|
4421 |
|
4422 /* read the mac address */ |
|
4423 base = get_hwbase(dev); |
|
4424 np->orig_mac[0] = readl(base + NvRegMacAddrA); |
|
4425 np->orig_mac[1] = readl(base + NvRegMacAddrB); |
|
4426 |
|
4427 /* check the workaround bit for correct mac address order */ |
|
4428 txreg = readl(base + NvRegTransmitPoll); |
|
4429 if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
|
4430 /* mac address is already in correct order */ |
|
4431 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; |
|
4432 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; |
|
4433 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; |
|
4434 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; |
|
4435 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; |
|
4436 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; |
|
4437 } else { |
|
4438 /* need to reverse mac address to correct order */ |
|
4439 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
|
4440 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
|
4441 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
|
4442 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
|
4443 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
|
4444 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
|
4445 /* set permanent address to be correct aswell */ |
|
4446 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
|
4447 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
|
4448 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
|
4449 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
|
4450 } |
|
4451 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
4452 |
|
4453 if (!is_valid_ether_addr(dev->perm_addr)) { |
|
4454 /* |
|
4455 * Bad mac address. At least one bios sets the mac address |
|
4456 * to 01:23:45:67:89:ab |
|
4457 */ |
|
4458 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", |
|
4459 pci_name(pci_dev), |
|
4460 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
4461 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
4462 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); |
|
4463 dev->dev_addr[0] = 0x00; |
|
4464 dev->dev_addr[1] = 0x00; |
|
4465 dev->dev_addr[2] = 0x6c; |
|
4466 get_random_bytes(&dev->dev_addr[3], 3); |
|
4467 } |
|
4468 |
|
4469 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
|
4470 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
4471 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
4472 |
|
4473 /* set mac address */ |
|
4474 nv_copy_mac_to_hw(dev); |
|
4475 |
|
4476 /* disable WOL */ |
|
4477 writel(0, base + NvRegWakeUpFlags); |
|
4478 np->wolenabled = 0; |
|
4479 |
|
4480 if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
|
4481 u8 revision_id; |
|
4482 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id); |
|
4483 |
|
4484 /* take phy and nic out of low power mode */ |
|
4485 powerstate = readl(base + NvRegPowerState2); |
|
4486 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; |
|
4487 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || |
|
4488 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && |
|
4489 revision_id >= 0xA3) |
|
4490 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
|
4491 writel(powerstate, base + NvRegPowerState2); |
|
4492 } |
|
4493 |
|
4494 if (np->desc_ver == DESC_VER_1) { |
|
4495 np->tx_flags = NV_TX_VALID; |
|
4496 } else { |
|
4497 np->tx_flags = NV_TX2_VALID; |
|
4498 } |
|
4499 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
|
4500 np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
|
4501 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
4502 np->msi_flags |= 0x0003; |
|
4503 } else { |
|
4504 np->irqmask = NVREG_IRQMASK_CPU; |
|
4505 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
4506 np->msi_flags |= 0x0001; |
|
4507 } |
|
4508 |
|
4509 if (id->driver_data & DEV_NEED_TIMERIRQ) |
|
4510 np->irqmask |= NVREG_IRQ_TIMER; |
|
4511 if (id->driver_data & DEV_NEED_LINKTIMER) { |
|
4512 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); |
|
4513 np->need_linktimer = 1; |
|
4514 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
4515 } else { |
|
4516 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); |
|
4517 np->need_linktimer = 0; |
|
4518 } |
|
4519 |
|
4520 /* find a suitable phy */ |
|
4521 for (i = 1; i <= 32; i++) { |
|
4522 int id1, id2; |
|
4523 int phyaddr = i & 0x1F; |
|
4524 |
|
4525 spin_lock_irq(&np->lock); |
|
4526 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
|
4527 spin_unlock_irq(&np->lock); |
|
4528 if (id1 < 0 || id1 == 0xffff) |
|
4529 continue; |
|
4530 spin_lock_irq(&np->lock); |
|
4531 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
|
4532 spin_unlock_irq(&np->lock); |
|
4533 if (id2 < 0 || id2 == 0xffff) |
|
4534 continue; |
|
4535 |
|
4536 np->phy_model = id2 & PHYID2_MODEL_MASK; |
|
4537 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
|
4538 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
|
4539 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
|
4540 pci_name(pci_dev), id1, id2, phyaddr); |
|
4541 np->phyaddr = phyaddr; |
|
4542 np->phy_oui = id1 | id2; |
|
4543 break; |
|
4544 } |
|
4545 if (i == 33) { |
|
4546 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
|
4547 pci_name(pci_dev)); |
|
4548 goto out_error; |
|
4549 } |
|
4550 |
|
4551 /* reset it */ |
|
4552 phy_init(dev); |
|
4553 |
|
4554 /* set default link speed settings */ |
|
4555 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
4556 np->duplex = 0; |
|
4557 np->autoneg = 1; |
|
4558 |
|
4559 err = register_netdev(dev); |
|
4560 if (err) { |
|
4561 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); |
|
4562 goto out_error; |
|
4563 } |
|
4564 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", |
|
4565 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, |
|
4566 pci_name(pci_dev)); |
|
4567 |
|
4568 return 0; |
|
4569 |
|
4570 out_error: |
|
4571 pci_set_drvdata(pci_dev, NULL); |
|
4572 out_freering: |
|
4573 free_rings(dev); |
|
4574 out_unmap: |
|
4575 iounmap(get_hwbase(dev)); |
|
4576 out_relreg: |
|
4577 pci_release_regions(pci_dev); |
|
4578 out_disable: |
|
4579 pci_disable_device(pci_dev); |
|
4580 out_free: |
|
4581 free_netdev(dev); |
|
4582 out: |
|
4583 return err; |
|
4584 } |
|
4585 |
|
4586 static void __devexit nv_remove(struct pci_dev *pci_dev) |
|
4587 { |
|
4588 struct net_device *dev = pci_get_drvdata(pci_dev); |
|
4589 struct fe_priv *np = netdev_priv(dev); |
|
4590 u8 __iomem *base = get_hwbase(dev); |
|
4591 |
|
4592 unregister_netdev(dev); |
|
4593 |
|
4594 /* special op: write back the misordered MAC address - otherwise |
|
4595 * the next nv_probe would see a wrong address. |
|
4596 */ |
|
4597 writel(np->orig_mac[0], base + NvRegMacAddrA); |
|
4598 writel(np->orig_mac[1], base + NvRegMacAddrB); |
|
4599 |
|
4600 /* free all structures */ |
|
4601 free_rings(dev); |
|
4602 iounmap(get_hwbase(dev)); |
|
4603 pci_release_regions(pci_dev); |
|
4604 pci_disable_device(pci_dev); |
|
4605 free_netdev(dev); |
|
4606 pci_set_drvdata(pci_dev, NULL); |
|
4607 } |
|
4608 |
|
4609 static struct pci_device_id pci_tbl[] = { |
|
4610 { /* nForce Ethernet Controller */ |
|
4611 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
|
4612 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
4613 }, |
|
4614 { /* nForce2 Ethernet Controller */ |
|
4615 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
|
4616 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
4617 }, |
|
4618 { /* nForce3 Ethernet Controller */ |
|
4619 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
|
4620 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
4621 }, |
|
4622 { /* nForce3 Ethernet Controller */ |
|
4623 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
|
4624 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
4625 }, |
|
4626 { /* nForce3 Ethernet Controller */ |
|
4627 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
|
4628 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
4629 }, |
|
4630 { /* nForce3 Ethernet Controller */ |
|
4631 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
|
4632 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
4633 }, |
|
4634 { /* nForce3 Ethernet Controller */ |
|
4635 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
|
4636 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
4637 }, |
|
4638 { /* CK804 Ethernet Controller */ |
|
4639 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
|
4640 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
4641 }, |
|
4642 { /* CK804 Ethernet Controller */ |
|
4643 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
|
4644 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
4645 }, |
|
4646 { /* MCP04 Ethernet Controller */ |
|
4647 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
|
4648 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
4649 }, |
|
4650 { /* MCP04 Ethernet Controller */ |
|
4651 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
|
4652 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
4653 }, |
|
4654 { /* MCP51 Ethernet Controller */ |
|
4655 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
|
4656 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
4657 }, |
|
4658 { /* MCP51 Ethernet Controller */ |
|
4659 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
|
4660 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
4661 }, |
|
4662 { /* MCP55 Ethernet Controller */ |
|
4663 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
|
4664 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4665 }, |
|
4666 { /* MCP55 Ethernet Controller */ |
|
4667 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
|
4668 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4669 }, |
|
4670 { /* MCP61 Ethernet Controller */ |
|
4671 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), |
|
4672 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4673 }, |
|
4674 { /* MCP61 Ethernet Controller */ |
|
4675 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), |
|
4676 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4677 }, |
|
4678 { /* MCP61 Ethernet Controller */ |
|
4679 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), |
|
4680 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4681 }, |
|
4682 { /* MCP61 Ethernet Controller */ |
|
4683 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), |
|
4684 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4685 }, |
|
4686 { /* MCP65 Ethernet Controller */ |
|
4687 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), |
|
4688 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4689 }, |
|
4690 { /* MCP65 Ethernet Controller */ |
|
4691 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), |
|
4692 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4693 }, |
|
4694 { /* MCP65 Ethernet Controller */ |
|
4695 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), |
|
4696 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4697 }, |
|
4698 { /* MCP65 Ethernet Controller */ |
|
4699 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), |
|
4700 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
|
4701 }, |
|
4702 {0,}, |
|
4703 }; |
|
4704 |
|
4705 static struct pci_driver driver = { |
|
4706 .name = "forcedeth", |
|
4707 .id_table = pci_tbl, |
|
4708 .probe = nv_probe, |
|
4709 .remove = __devexit_p(nv_remove), |
|
4710 }; |
|
4711 |
|
4712 |
|
4713 static int __init init_nic(void) |
|
4714 { |
|
4715 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); |
|
4716 return pci_register_driver(&driver); |
|
4717 } |
|
4718 |
|
4719 static void __exit exit_nic(void) |
|
4720 { |
|
4721 pci_unregister_driver(&driver); |
|
4722 } |
|
4723 |
|
4724 module_param(max_interrupt_work, int, 0); |
|
4725 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
|
4726 module_param(optimization_mode, int, 0); |
|
4727 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); |
|
4728 module_param(poll_interval, int, 0); |
|
4729 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); |
|
4730 module_param(msi, int, 0); |
|
4731 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); |
|
4732 module_param(msix, int, 0); |
|
4733 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); |
|
4734 module_param(dma_64bit, int, 0); |
|
4735 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); |
|
4736 |
|
4737 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
|
4738 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); |
|
4739 MODULE_LICENSE("GPL"); |
|
4740 |
|
4741 MODULE_DEVICE_TABLE(pci, pci_tbl); |
|
4742 |
|
4743 module_init(init_nic); |
|
4744 module_exit(exit_nic); |
|