1 /* |
|
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. |
|
3 * |
|
4 * Note: This driver is a cleanroom reimplementation based on reverse |
|
5 * engineered documentation written by Carl-Daniel Hailfinger |
|
6 * and Andrew de Quincey. It's neither supported nor endorsed |
|
7 * by NVIDIA Corp. Use at your own risk. |
|
8 * |
|
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered |
|
10 * trademarks of NVIDIA Corporation in the United States and other |
|
11 * countries. |
|
12 * |
|
13 * Copyright (C) 2003,4,5 Manfred Spraul |
|
14 * Copyright (C) 2004 Andrew de Quincey (wol support) |
|
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane |
|
16 * IRQ rate fixes, bigendian fixes, cleanups, verification) |
|
17 * Copyright (c) 2004 NVIDIA Corporation |
|
18 * |
|
19 * This program is free software; you can redistribute it and/or modify |
|
20 * it under the terms of the GNU General Public License as published by |
|
21 * the Free Software Foundation; either version 2 of the License, or |
|
22 * (at your option) any later version. |
|
23 * |
|
24 * This program is distributed in the hope that it will be useful, |
|
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
27 * GNU General Public License for more details. |
|
28 * |
|
29 * You should have received a copy of the GNU General Public License |
|
30 * along with this program; if not, write to the Free Software |
|
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
32 * |
|
33 * Changelog: |
|
34 * 0.01: 05 Oct 2003: First release that compiles without warnings. |
|
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. |
|
36 * Check all PCI BARs for the register window. |
|
37 * udelay added to mii_rw. |
|
38 * 0.03: 06 Oct 2003: Initialize dev->irq. |
|
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. |
|
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. |
|
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, |
|
42 * irq mask updated |
|
43 * 0.07: 14 Oct 2003: Further irq mask updates. |
|
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill |
|
45 * added into irq handler, NULL check for drain_ring. |
|
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the |
|
47 * requested interrupt sources. |
|
48 * 0.10: 20 Oct 2003: First cleanup for release. |
|
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. |
|
50 * MAC Address init fix, set_multicast cleanup. |
|
51 * 0.12: 23 Oct 2003: Cleanups for release. |
|
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. |
|
53 * Set link speed correctly. start rx before starting |
|
54 * tx (nv_start_rx sets the link speed). |
|
55 * 0.14: 25 Oct 2003: Nic dependant irq mask. |
|
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during |
|
57 * open. |
|
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size |
|
59 * increased to 1628 bytes. |
|
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from |
|
61 * the tx length. |
|
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats |
|
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac |
|
64 * addresses, really stop rx if already running |
|
65 * in nv_start_rx, clean up a bit. |
|
66 * 0.20: 07 Dec 2003: alloc fixes |
|
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. |
|
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup |
|
69 * on close. |
|
70 * 0.23: 26 Jan 2004: various small cleanups |
|
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces |
|
72 * 0.25: 09 Mar 2004: wol support |
|
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes |
|
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, |
|
75 * added CK804/MCP04 device IDs, code fixes |
|
76 * for registers, link status and other minor fixes. |
|
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe |
|
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification. |
|
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset |
|
80 * into nv_close, otherwise reenabling for wol can |
|
81 * cause DMA to kfree'd memory. |
|
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link |
|
83 * capabilities. |
|
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added. |
|
85 * 0.33: 16 May 2005: Support for MCP51 added. |
|
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. |
|
87 * 0.35: 26 Jun 2005: Support for MCP55 added. |
|
88 * 0.36: 28 Jun 2005: Add jumbo frame support. |
|
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list |
|
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of |
|
91 * per-packet flags. |
|
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support. |
|
93 * 0.40: 19 Jul 2005: Add support for mac address change. |
|
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead |
|
95 * of nv_remove |
|
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
|
97 * in the second (and later) nv_open call |
|
98 * 0.43: 10 Aug 2005: Add support for tx checksum. |
|
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. |
|
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check |
|
101 * 0.46: 20 Oct 2005: Add irq optimization modes. |
|
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. |
|
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single |
|
104 * 0.49: 10 Dec 2005: Fix tso for large buffers. |
|
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support. |
|
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. |
|
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support. |
|
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
|
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
|
110 * |
|
111 * Known bugs: |
|
112 * We suspect that on some hardware no TX done interrupts are generated. |
|
113 * This means recovery from netif_stop_queue only happens if the hw timer |
|
114 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) |
|
115 * and the timer is active in the IRQMask, or if a rx packet arrives by chance. |
|
116 * If your hardware reliably generates tx done interrupts, then you can remove |
|
117 * DEV_NEED_TIMERIRQ from the driver_data flags. |
|
118 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
|
119 * superfluous timer interrupts from the nic. |
|
120 */ |
|
121 #define FORCEDETH_VERSION "0.54" |
|
122 #define DRV_NAME "forcedeth" |
|
123 |
|
124 #include <linux/module.h> |
|
125 #include <linux/types.h> |
|
126 #include <linux/pci.h> |
|
127 #include <linux/interrupt.h> |
|
128 #include <linux/netdevice.h> |
|
129 #include <linux/etherdevice.h> |
|
130 #include <linux/delay.h> |
|
131 #include <linux/spinlock.h> |
|
132 #include <linux/ethtool.h> |
|
133 #include <linux/timer.h> |
|
134 #include <linux/skbuff.h> |
|
135 #include <linux/mii.h> |
|
136 #include <linux/random.h> |
|
137 #include <linux/init.h> |
|
138 #include <linux/if_vlan.h> |
|
139 #include <linux/dma-mapping.h> |
|
140 |
|
141 #include <asm/irq.h> |
|
142 #include <asm/io.h> |
|
143 #include <asm/uaccess.h> |
|
144 #include <asm/system.h> |
|
145 |
|
146 #if 0 |
|
147 #define dprintk printk |
|
148 #else |
|
149 #define dprintk(x...) do { } while (0) |
|
150 #endif |
|
151 |
|
152 |
|
153 /* |
|
154 * Hardware access: |
|
155 */ |
|
156 |
|
157 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */ |
|
158 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ |
|
159 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ |
|
160 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
|
161 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ |
|
162 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */ |
|
163 #define DEV_HAS_MSI 0x0040 /* device supports MSI */ |
|
164 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */ |
|
165 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */ |
|
166 |
|
167 enum { |
|
168 NvRegIrqStatus = 0x000, |
|
169 #define NVREG_IRQSTAT_MIIEVENT 0x040 |
|
170 #define NVREG_IRQSTAT_MASK 0x1ff |
|
171 NvRegIrqMask = 0x004, |
|
172 #define NVREG_IRQ_RX_ERROR 0x0001 |
|
173 #define NVREG_IRQ_RX 0x0002 |
|
174 #define NVREG_IRQ_RX_NOBUF 0x0004 |
|
175 #define NVREG_IRQ_TX_ERR 0x0008 |
|
176 #define NVREG_IRQ_TX_OK 0x0010 |
|
177 #define NVREG_IRQ_TIMER 0x0020 |
|
178 #define NVREG_IRQ_LINK 0x0040 |
|
179 #define NVREG_IRQ_RX_FORCED 0x0080 |
|
180 #define NVREG_IRQ_TX_FORCED 0x0100 |
|
181 #define NVREG_IRQMASK_THROUGHPUT 0x00df |
|
182 #define NVREG_IRQMASK_CPU 0x0040 |
|
183 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
|
184 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) |
|
185 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) |
|
186 |
|
187 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ |
|
188 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
|
189 NVREG_IRQ_TX_FORCED)) |
|
190 |
|
191 NvRegUnknownSetupReg6 = 0x008, |
|
192 #define NVREG_UNKSETUP6_VAL 3 |
|
193 |
|
194 /* |
|
195 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic |
|
196 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms |
|
197 */ |
|
198 NvRegPollingInterval = 0x00c, |
|
199 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 |
|
200 #define NVREG_POLL_DEFAULT_CPU 13 |
|
201 NvRegMSIMap0 = 0x020, |
|
202 NvRegMSIMap1 = 0x024, |
|
203 NvRegMSIIrqMask = 0x030, |
|
204 #define NVREG_MSI_VECTOR_0_ENABLED 0x01 |
|
205 NvRegMisc1 = 0x080, |
|
206 #define NVREG_MISC1_HD 0x02 |
|
207 #define NVREG_MISC1_FORCE 0x3b0f3c |
|
208 |
|
209 NvRegMacReset = 0x3c, |
|
210 #define NVREG_MAC_RESET_ASSERT 0x0F3 |
|
211 NvRegTransmitterControl = 0x084, |
|
212 #define NVREG_XMITCTL_START 0x01 |
|
213 NvRegTransmitterStatus = 0x088, |
|
214 #define NVREG_XMITSTAT_BUSY 0x01 |
|
215 |
|
216 NvRegPacketFilterFlags = 0x8c, |
|
217 #define NVREG_PFF_ALWAYS 0x7F0008 |
|
218 #define NVREG_PFF_PROMISC 0x80 |
|
219 #define NVREG_PFF_MYADDR 0x20 |
|
220 |
|
221 NvRegOffloadConfig = 0x90, |
|
222 #define NVREG_OFFLOAD_HOMEPHY 0x601 |
|
223 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
|
224 NvRegReceiverControl = 0x094, |
|
225 #define NVREG_RCVCTL_START 0x01 |
|
226 NvRegReceiverStatus = 0x98, |
|
227 #define NVREG_RCVSTAT_BUSY 0x01 |
|
228 |
|
229 NvRegRandomSeed = 0x9c, |
|
230 #define NVREG_RNDSEED_MASK 0x00ff |
|
231 #define NVREG_RNDSEED_FORCE 0x7f00 |
|
232 #define NVREG_RNDSEED_FORCE2 0x2d00 |
|
233 #define NVREG_RNDSEED_FORCE3 0x7400 |
|
234 |
|
235 NvRegUnknownSetupReg1 = 0xA0, |
|
236 #define NVREG_UNKSETUP1_VAL 0x16070f |
|
237 NvRegUnknownSetupReg2 = 0xA4, |
|
238 #define NVREG_UNKSETUP2_VAL 0x16 |
|
239 NvRegMacAddrA = 0xA8, |
|
240 NvRegMacAddrB = 0xAC, |
|
241 NvRegMulticastAddrA = 0xB0, |
|
242 #define NVREG_MCASTADDRA_FORCE 0x01 |
|
243 NvRegMulticastAddrB = 0xB4, |
|
244 NvRegMulticastMaskA = 0xB8, |
|
245 NvRegMulticastMaskB = 0xBC, |
|
246 |
|
247 NvRegPhyInterface = 0xC0, |
|
248 #define PHY_RGMII 0x10000000 |
|
249 |
|
250 NvRegTxRingPhysAddr = 0x100, |
|
251 NvRegRxRingPhysAddr = 0x104, |
|
252 NvRegRingSizes = 0x108, |
|
253 #define NVREG_RINGSZ_TXSHIFT 0 |
|
254 #define NVREG_RINGSZ_RXSHIFT 16 |
|
255 NvRegUnknownTransmitterReg = 0x10c, |
|
256 NvRegLinkSpeed = 0x110, |
|
257 #define NVREG_LINKSPEED_FORCE 0x10000 |
|
258 #define NVREG_LINKSPEED_10 1000 |
|
259 #define NVREG_LINKSPEED_100 100 |
|
260 #define NVREG_LINKSPEED_1000 50 |
|
261 #define NVREG_LINKSPEED_MASK (0xFFF) |
|
262 NvRegUnknownSetupReg5 = 0x130, |
|
263 #define NVREG_UNKSETUP5_BIT31 (1<<31) |
|
264 NvRegUnknownSetupReg3 = 0x13c, |
|
265 #define NVREG_UNKSETUP3_VAL1 0x200010 |
|
266 NvRegTxRxControl = 0x144, |
|
267 #define NVREG_TXRXCTL_KICK 0x0001 |
|
268 #define NVREG_TXRXCTL_BIT1 0x0002 |
|
269 #define NVREG_TXRXCTL_BIT2 0x0004 |
|
270 #define NVREG_TXRXCTL_IDLE 0x0008 |
|
271 #define NVREG_TXRXCTL_RESET 0x0010 |
|
272 #define NVREG_TXRXCTL_RXCHECK 0x0400 |
|
273 #define NVREG_TXRXCTL_DESC_1 0 |
|
274 #define NVREG_TXRXCTL_DESC_2 0x02100 |
|
275 #define NVREG_TXRXCTL_DESC_3 0x02200 |
|
276 #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
|
277 #define NVREG_TXRXCTL_VLANINS 0x00080 |
|
278 NvRegTxRingPhysAddrHigh = 0x148, |
|
279 NvRegRxRingPhysAddrHigh = 0x14C, |
|
280 NvRegMIIStatus = 0x180, |
|
281 #define NVREG_MIISTAT_ERROR 0x0001 |
|
282 #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
|
283 #define NVREG_MIISTAT_MASK 0x000f |
|
284 #define NVREG_MIISTAT_MASK2 0x000f |
|
285 NvRegUnknownSetupReg4 = 0x184, |
|
286 #define NVREG_UNKSETUP4_VAL 8 |
|
287 |
|
288 NvRegAdapterControl = 0x188, |
|
289 #define NVREG_ADAPTCTL_START 0x02 |
|
290 #define NVREG_ADAPTCTL_LINKUP 0x04 |
|
291 #define NVREG_ADAPTCTL_PHYVALID 0x40000 |
|
292 #define NVREG_ADAPTCTL_RUNNING 0x100000 |
|
293 #define NVREG_ADAPTCTL_PHYSHIFT 24 |
|
294 NvRegMIISpeed = 0x18c, |
|
295 #define NVREG_MIISPEED_BIT8 (1<<8) |
|
296 #define NVREG_MIIDELAY 5 |
|
297 NvRegMIIControl = 0x190, |
|
298 #define NVREG_MIICTL_INUSE 0x08000 |
|
299 #define NVREG_MIICTL_WRITE 0x00400 |
|
300 #define NVREG_MIICTL_ADDRSHIFT 5 |
|
301 NvRegMIIData = 0x194, |
|
302 NvRegWakeUpFlags = 0x200, |
|
303 #define NVREG_WAKEUPFLAGS_VAL 0x7770 |
|
304 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 |
|
305 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 |
|
306 #define NVREG_WAKEUPFLAGS_D3SHIFT 12 |
|
307 #define NVREG_WAKEUPFLAGS_D2SHIFT 8 |
|
308 #define NVREG_WAKEUPFLAGS_D1SHIFT 4 |
|
309 #define NVREG_WAKEUPFLAGS_D0SHIFT 0 |
|
310 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 |
|
311 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 |
|
312 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 |
|
313 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
|
314 |
|
315 NvRegPatternCRC = 0x204, |
|
316 NvRegPatternMask = 0x208, |
|
317 NvRegPowerCap = 0x268, |
|
318 #define NVREG_POWERCAP_D3SUPP (1<<30) |
|
319 #define NVREG_POWERCAP_D2SUPP (1<<26) |
|
320 #define NVREG_POWERCAP_D1SUPP (1<<25) |
|
321 NvRegPowerState = 0x26c, |
|
322 #define NVREG_POWERSTATE_POWEREDUP 0x8000 |
|
323 #define NVREG_POWERSTATE_VALID 0x0100 |
|
324 #define NVREG_POWERSTATE_MASK 0x0003 |
|
325 #define NVREG_POWERSTATE_D0 0x0000 |
|
326 #define NVREG_POWERSTATE_D1 0x0001 |
|
327 #define NVREG_POWERSTATE_D2 0x0002 |
|
328 #define NVREG_POWERSTATE_D3 0x0003 |
|
329 NvRegVlanControl = 0x300, |
|
330 #define NVREG_VLANCONTROL_ENABLE 0x2000 |
|
331 NvRegMSIXMap0 = 0x3e0, |
|
332 NvRegMSIXMap1 = 0x3e4, |
|
333 NvRegMSIXIrqStatus = 0x3f0, |
|
334 |
|
335 NvRegPowerState2 = 0x600, |
|
336 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 |
|
337 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
|
338 }; |
|
339 |
|
340 /* Big endian: should work, but is untested */ |
|
341 struct ring_desc { |
|
342 u32 PacketBuffer; |
|
343 u32 FlagLen; |
|
344 }; |
|
345 |
|
346 struct ring_desc_ex { |
|
347 u32 PacketBufferHigh; |
|
348 u32 PacketBufferLow; |
|
349 u32 TxVlan; |
|
350 u32 FlagLen; |
|
351 }; |
|
352 |
|
353 typedef union _ring_type { |
|
354 struct ring_desc* orig; |
|
355 struct ring_desc_ex* ex; |
|
356 } ring_type; |
|
357 |
|
358 #define FLAG_MASK_V1 0xffff0000 |
|
359 #define FLAG_MASK_V2 0xffffc000 |
|
360 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) |
|
361 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) |
|
362 |
|
363 #define NV_TX_LASTPACKET (1<<16) |
|
364 #define NV_TX_RETRYERROR (1<<19) |
|
365 #define NV_TX_FORCED_INTERRUPT (1<<24) |
|
366 #define NV_TX_DEFERRED (1<<26) |
|
367 #define NV_TX_CARRIERLOST (1<<27) |
|
368 #define NV_TX_LATECOLLISION (1<<28) |
|
369 #define NV_TX_UNDERFLOW (1<<29) |
|
370 #define NV_TX_ERROR (1<<30) |
|
371 #define NV_TX_VALID (1<<31) |
|
372 |
|
373 #define NV_TX2_LASTPACKET (1<<29) |
|
374 #define NV_TX2_RETRYERROR (1<<18) |
|
375 #define NV_TX2_FORCED_INTERRUPT (1<<30) |
|
376 #define NV_TX2_DEFERRED (1<<25) |
|
377 #define NV_TX2_CARRIERLOST (1<<26) |
|
378 #define NV_TX2_LATECOLLISION (1<<27) |
|
379 #define NV_TX2_UNDERFLOW (1<<28) |
|
380 /* error and valid are the same for both */ |
|
381 #define NV_TX2_ERROR (1<<30) |
|
382 #define NV_TX2_VALID (1<<31) |
|
383 #define NV_TX2_TSO (1<<28) |
|
384 #define NV_TX2_TSO_SHIFT 14 |
|
385 #define NV_TX2_TSO_MAX_SHIFT 14 |
|
386 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) |
|
387 #define NV_TX2_CHECKSUM_L3 (1<<27) |
|
388 #define NV_TX2_CHECKSUM_L4 (1<<26) |
|
389 |
|
390 #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
|
391 |
|
392 #define NV_RX_DESCRIPTORVALID (1<<16) |
|
393 #define NV_RX_MISSEDFRAME (1<<17) |
|
394 #define NV_RX_SUBSTRACT1 (1<<18) |
|
395 #define NV_RX_ERROR1 (1<<23) |
|
396 #define NV_RX_ERROR2 (1<<24) |
|
397 #define NV_RX_ERROR3 (1<<25) |
|
398 #define NV_RX_ERROR4 (1<<26) |
|
399 #define NV_RX_CRCERR (1<<27) |
|
400 #define NV_RX_OVERFLOW (1<<28) |
|
401 #define NV_RX_FRAMINGERR (1<<29) |
|
402 #define NV_RX_ERROR (1<<30) |
|
403 #define NV_RX_AVAIL (1<<31) |
|
404 |
|
405 #define NV_RX2_CHECKSUMMASK (0x1C000000) |
|
406 #define NV_RX2_CHECKSUMOK1 (0x10000000) |
|
407 #define NV_RX2_CHECKSUMOK2 (0x14000000) |
|
408 #define NV_RX2_CHECKSUMOK3 (0x18000000) |
|
409 #define NV_RX2_DESCRIPTORVALID (1<<29) |
|
410 #define NV_RX2_SUBSTRACT1 (1<<25) |
|
411 #define NV_RX2_ERROR1 (1<<18) |
|
412 #define NV_RX2_ERROR2 (1<<19) |
|
413 #define NV_RX2_ERROR3 (1<<20) |
|
414 #define NV_RX2_ERROR4 (1<<21) |
|
415 #define NV_RX2_CRCERR (1<<22) |
|
416 #define NV_RX2_OVERFLOW (1<<23) |
|
417 #define NV_RX2_FRAMINGERR (1<<24) |
|
418 /* error and avail are the same for both */ |
|
419 #define NV_RX2_ERROR (1<<30) |
|
420 #define NV_RX2_AVAIL (1<<31) |
|
421 |
|
422 #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
|
423 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) |
|
424 |
|
425 /* Miscelaneous hardware related defines: */ |
|
426 #define NV_PCI_REGSZ_VER1 0x270 |
|
427 #define NV_PCI_REGSZ_VER2 0x604 |
|
428 |
|
429 /* various timeout delays: all in usec */ |
|
430 #define NV_TXRX_RESET_DELAY 4 |
|
431 #define NV_TXSTOP_DELAY1 10 |
|
432 #define NV_TXSTOP_DELAY1MAX 500000 |
|
433 #define NV_TXSTOP_DELAY2 100 |
|
434 #define NV_RXSTOP_DELAY1 10 |
|
435 #define NV_RXSTOP_DELAY1MAX 500000 |
|
436 #define NV_RXSTOP_DELAY2 100 |
|
437 #define NV_SETUP5_DELAY 5 |
|
438 #define NV_SETUP5_DELAYMAX 50000 |
|
439 #define NV_POWERUP_DELAY 5 |
|
440 #define NV_POWERUP_DELAYMAX 5000 |
|
441 #define NV_MIIBUSY_DELAY 50 |
|
442 #define NV_MIIPHY_DELAY 10 |
|
443 #define NV_MIIPHY_DELAYMAX 10000 |
|
444 #define NV_MAC_RESET_DELAY 64 |
|
445 |
|
446 #define NV_WAKEUPPATTERNS 5 |
|
447 #define NV_WAKEUPMASKENTRIES 4 |
|
448 |
|
449 /* General driver defaults */ |
|
450 #define NV_WATCHDOG_TIMEO (5*HZ) |
|
451 |
|
452 #define RX_RING 128 |
|
453 #define TX_RING 256 |
|
454 /* |
|
455 * If your nic mysteriously hangs then try to reduce the limits |
|
456 * to 1/0: It might be required to set NV_TX_LASTPACKET in the |
|
457 * last valid ring entry. But this would be impossible to |
|
458 * implement - probably a disassembly error. |
|
459 */ |
|
460 #define TX_LIMIT_STOP 255 |
|
461 #define TX_LIMIT_START 254 |
|
462 |
|
463 /* rx/tx mac addr + type + vlan + align + slack*/ |
|
464 #define NV_RX_HEADERS (64) |
|
465 /* even more slack. */ |
|
466 #define NV_RX_ALLOC_PAD (64) |
|
467 |
|
468 /* maximum mtu size */ |
|
469 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ |
|
470 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ |
|
471 |
|
472 #define OOM_REFILL (1+HZ/20) |
|
473 #define POLL_WAIT (1+HZ/100) |
|
474 #define LINK_TIMEOUT (3*HZ) |
|
475 |
|
476 /* |
|
477 * desc_ver values: |
|
478 * The nic supports three different descriptor types: |
|
479 * - DESC_VER_1: Original |
|
480 * - DESC_VER_2: support for jumbo frames. |
|
481 * - DESC_VER_3: 64-bit format. |
|
482 */ |
|
483 #define DESC_VER_1 1 |
|
484 #define DESC_VER_2 2 |
|
485 #define DESC_VER_3 3 |
|
486 |
|
487 /* PHY defines */ |
|
488 #define PHY_OUI_MARVELL 0x5043 |
|
489 #define PHY_OUI_CICADA 0x03f1 |
|
490 #define PHYID1_OUI_MASK 0x03ff |
|
491 #define PHYID1_OUI_SHFT 6 |
|
492 #define PHYID2_OUI_MASK 0xfc00 |
|
493 #define PHYID2_OUI_SHFT 10 |
|
494 #define PHY_INIT1 0x0f000 |
|
495 #define PHY_INIT2 0x0e00 |
|
496 #define PHY_INIT3 0x01000 |
|
497 #define PHY_INIT4 0x0200 |
|
498 #define PHY_INIT5 0x0004 |
|
499 #define PHY_INIT6 0x02000 |
|
500 #define PHY_GIGABIT 0x0100 |
|
501 |
|
502 #define PHY_TIMEOUT 0x1 |
|
503 #define PHY_ERROR 0x2 |
|
504 |
|
505 #define PHY_100 0x1 |
|
506 #define PHY_1000 0x2 |
|
507 #define PHY_HALF 0x100 |
|
508 |
|
509 /* FIXME: MII defines that should be added to <linux/mii.h> */ |
|
510 #define MII_1000BT_CR 0x09 |
|
511 #define MII_1000BT_SR 0x0a |
|
512 #define ADVERTISE_1000FULL 0x0200 |
|
513 #define ADVERTISE_1000HALF 0x0100 |
|
514 #define LPA_1000FULL 0x0800 |
|
515 #define LPA_1000HALF 0x0400 |
|
516 |
|
517 /* MSI/MSI-X defines */ |
|
518 #define NV_MSI_X_MAX_VECTORS 8 |
|
519 #define NV_MSI_X_VECTORS_MASK 0x000f |
|
520 #define NV_MSI_CAPABLE 0x0010 |
|
521 #define NV_MSI_X_CAPABLE 0x0020 |
|
522 #define NV_MSI_ENABLED 0x0040 |
|
523 #define NV_MSI_X_ENABLED 0x0080 |
|
524 |
|
525 #define NV_MSI_X_VECTOR_ALL 0x0 |
|
526 #define NV_MSI_X_VECTOR_RX 0x0 |
|
527 #define NV_MSI_X_VECTOR_TX 0x1 |
|
528 #define NV_MSI_X_VECTOR_OTHER 0x2 |
|
529 |
|
530 /* |
|
531 * SMP locking: |
|
532 * All hardware access under dev->priv->lock, except the performance |
|
533 * critical parts: |
|
534 * - rx is (pseudo-) lockless: it relies on the single-threading provided |
|
535 * by the arch code for interrupts. |
|
536 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission |
|
537 * needs dev->priv->lock :-( |
|
538 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock. |
|
539 */ |
|
540 |
|
541 /* in dev: base, irq */ |
|
542 struct fe_priv { |
|
543 spinlock_t lock; |
|
544 |
|
545 /* General data: |
|
546 * Locking: spin_lock(&np->lock); */ |
|
547 struct net_device_stats stats; |
|
548 int in_shutdown; |
|
549 u32 linkspeed; |
|
550 int duplex; |
|
551 int autoneg; |
|
552 int fixed_mode; |
|
553 int phyaddr; |
|
554 int wolenabled; |
|
555 unsigned int phy_oui; |
|
556 u16 gigabit; |
|
557 |
|
558 /* General data: RO fields */ |
|
559 dma_addr_t ring_addr; |
|
560 struct pci_dev *pci_dev; |
|
561 u32 orig_mac[2]; |
|
562 u32 irqmask; |
|
563 u32 desc_ver; |
|
564 u32 txrxctl_bits; |
|
565 u32 vlanctl_bits; |
|
566 u32 driver_data; |
|
567 u32 register_size; |
|
568 |
|
569 void __iomem *base; |
|
570 |
|
571 /* rx specific fields. |
|
572 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
573 */ |
|
574 ring_type rx_ring; |
|
575 unsigned int cur_rx, refill_rx; |
|
576 struct sk_buff *rx_skbuff[RX_RING]; |
|
577 dma_addr_t rx_dma[RX_RING]; |
|
578 unsigned int rx_buf_sz; |
|
579 unsigned int pkt_limit; |
|
580 struct timer_list oom_kick; |
|
581 struct timer_list nic_poll; |
|
582 u32 nic_poll_irq; |
|
583 |
|
584 /* media detection workaround. |
|
585 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
586 */ |
|
587 int need_linktimer; |
|
588 unsigned long link_timeout; |
|
589 /* |
|
590 * tx specific fields. |
|
591 */ |
|
592 ring_type tx_ring; |
|
593 unsigned int next_tx, nic_tx; |
|
594 struct sk_buff *tx_skbuff[TX_RING]; |
|
595 dma_addr_t tx_dma[TX_RING]; |
|
596 unsigned int tx_dma_len[TX_RING]; |
|
597 u32 tx_flags; |
|
598 |
|
599 /* vlan fields */ |
|
600 struct vlan_group *vlangrp; |
|
601 |
|
602 /* msi/msi-x fields */ |
|
603 u32 msi_flags; |
|
604 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; |
|
605 }; |
|
606 |
|
607 /* |
|
608 * Maximum number of loops until we assume that a bit in the irq mask |
|
609 * is stuck. Overridable with module param. |
|
610 */ |
|
611 static int max_interrupt_work = 5; |
|
612 |
|
613 /* |
|
614 * Optimization can be either throuput mode or cpu mode |
|
615 * |
|
616 * Throughput Mode: Every tx and rx packet will generate an interrupt. |
|
617 * CPU Mode: Interrupts are controlled by a timer. |
|
618 */ |
|
619 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0 |
|
620 #define NV_OPTIMIZATION_MODE_CPU 1 |
|
621 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
|
622 |
|
623 /* |
|
624 * Poll interval for timer irq |
|
625 * |
|
626 * This interval determines how frequent an interrupt is generated. |
|
627 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] |
|
628 * Min = 0, and Max = 65535 |
|
629 */ |
|
630 static int poll_interval = -1; |
|
631 |
|
632 /* |
|
633 * Disable MSI interrupts |
|
634 */ |
|
635 static int disable_msi = 0; |
|
636 |
|
637 /* |
|
638 * Disable MSIX interrupts |
|
639 */ |
|
640 static int disable_msix = 0; |
|
641 |
|
642 static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
|
643 { |
|
644 return netdev_priv(dev); |
|
645 } |
|
646 |
|
647 static inline u8 __iomem *get_hwbase(struct net_device *dev) |
|
648 { |
|
649 return ((struct fe_priv *)netdev_priv(dev))->base; |
|
650 } |
|
651 |
|
652 static inline void pci_push(u8 __iomem *base) |
|
653 { |
|
654 /* force out pending posted writes */ |
|
655 readl(base); |
|
656 } |
|
657 |
|
658 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) |
|
659 { |
|
660 return le32_to_cpu(prd->FlagLen) |
|
661 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
|
662 } |
|
663 |
|
664 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
|
665 { |
|
666 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2; |
|
667 } |
|
668 |
|
669 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
|
670 int delay, int delaymax, const char *msg) |
|
671 { |
|
672 u8 __iomem *base = get_hwbase(dev); |
|
673 |
|
674 pci_push(base); |
|
675 do { |
|
676 udelay(delay); |
|
677 delaymax -= delay; |
|
678 if (delaymax < 0) { |
|
679 if (msg) |
|
680 printk(msg); |
|
681 return 1; |
|
682 } |
|
683 } while ((readl(base + offset) & mask) != target); |
|
684 return 0; |
|
685 } |
|
686 |
|
687 #define NV_SETUP_RX_RING 0x01 |
|
688 #define NV_SETUP_TX_RING 0x02 |
|
689 |
|
690 static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
|
691 { |
|
692 struct fe_priv *np = get_nvpriv(dev); |
|
693 u8 __iomem *base = get_hwbase(dev); |
|
694 |
|
695 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
696 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
697 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
698 } |
|
699 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
700 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
|
701 } |
|
702 } else { |
|
703 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
704 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
705 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh); |
|
706 } |
|
707 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
708 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
|
709 writel((u32) (cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh); |
|
710 } |
|
711 } |
|
712 } |
|
713 |
|
714 static int using_multi_irqs(struct net_device *dev) |
|
715 { |
|
716 struct fe_priv *np = get_nvpriv(dev); |
|
717 |
|
718 if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
|
719 ((np->msi_flags & NV_MSI_X_ENABLED) && |
|
720 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) |
|
721 return 0; |
|
722 else |
|
723 return 1; |
|
724 } |
|
725 |
|
726 static void nv_enable_irq(struct net_device *dev) |
|
727 { |
|
728 struct fe_priv *np = get_nvpriv(dev); |
|
729 |
|
730 if (!using_multi_irqs(dev)) { |
|
731 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
732 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
733 else |
|
734 enable_irq(dev->irq); |
|
735 } else { |
|
736 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
737 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
738 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
739 } |
|
740 } |
|
741 |
|
742 static void nv_disable_irq(struct net_device *dev) |
|
743 { |
|
744 struct fe_priv *np = get_nvpriv(dev); |
|
745 |
|
746 if (!using_multi_irqs(dev)) { |
|
747 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
748 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
749 else |
|
750 disable_irq(dev->irq); |
|
751 } else { |
|
752 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
753 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
754 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
755 } |
|
756 } |
|
757 |
|
758 /* In MSIX mode, a write to irqmask behaves as XOR */ |
|
759 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) |
|
760 { |
|
761 u8 __iomem *base = get_hwbase(dev); |
|
762 |
|
763 writel(mask, base + NvRegIrqMask); |
|
764 } |
|
765 |
|
766 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) |
|
767 { |
|
768 struct fe_priv *np = get_nvpriv(dev); |
|
769 u8 __iomem *base = get_hwbase(dev); |
|
770 |
|
771 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
772 writel(mask, base + NvRegIrqMask); |
|
773 } else { |
|
774 if (np->msi_flags & NV_MSI_ENABLED) |
|
775 writel(0, base + NvRegMSIIrqMask); |
|
776 writel(0, base + NvRegIrqMask); |
|
777 } |
|
778 } |
|
779 |
|
780 #define MII_READ (-1) |
|
781 /* mii_rw: read/write a register on the PHY. |
|
782 * |
|
783 * Caller must guarantee serialization |
|
784 */ |
|
785 static int mii_rw(struct net_device *dev, int addr, int miireg, int value) |
|
786 { |
|
787 u8 __iomem *base = get_hwbase(dev); |
|
788 u32 reg; |
|
789 int retval; |
|
790 |
|
791 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
792 |
|
793 reg = readl(base + NvRegMIIControl); |
|
794 if (reg & NVREG_MIICTL_INUSE) { |
|
795 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); |
|
796 udelay(NV_MIIBUSY_DELAY); |
|
797 } |
|
798 |
|
799 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; |
|
800 if (value != MII_READ) { |
|
801 writel(value, base + NvRegMIIData); |
|
802 reg |= NVREG_MIICTL_WRITE; |
|
803 } |
|
804 writel(reg, base + NvRegMIIControl); |
|
805 |
|
806 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, |
|
807 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { |
|
808 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", |
|
809 dev->name, miireg, addr); |
|
810 retval = -1; |
|
811 } else if (value != MII_READ) { |
|
812 /* it was a write operation - fewer failures are detectable */ |
|
813 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", |
|
814 dev->name, value, miireg, addr); |
|
815 retval = 0; |
|
816 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { |
|
817 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", |
|
818 dev->name, miireg, addr); |
|
819 retval = -1; |
|
820 } else { |
|
821 retval = readl(base + NvRegMIIData); |
|
822 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", |
|
823 dev->name, miireg, addr, retval); |
|
824 } |
|
825 |
|
826 return retval; |
|
827 } |
|
828 |
|
829 static int phy_reset(struct net_device *dev) |
|
830 { |
|
831 struct fe_priv *np = netdev_priv(dev); |
|
832 u32 miicontrol; |
|
833 unsigned int tries = 0; |
|
834 |
|
835 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
836 miicontrol |= BMCR_RESET; |
|
837 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
|
838 return -1; |
|
839 } |
|
840 |
|
841 /* wait for 500ms */ |
|
842 msleep(500); |
|
843 |
|
844 /* must wait till reset is deasserted */ |
|
845 while (miicontrol & BMCR_RESET) { |
|
846 msleep(10); |
|
847 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
848 /* FIXME: 100 tries seem excessive */ |
|
849 if (tries++ > 100) |
|
850 return -1; |
|
851 } |
|
852 return 0; |
|
853 } |
|
854 |
|
855 static int phy_init(struct net_device *dev) |
|
856 { |
|
857 struct fe_priv *np = get_nvpriv(dev); |
|
858 u8 __iomem *base = get_hwbase(dev); |
|
859 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
|
860 |
|
861 /* set advertise register */ |
|
862 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
863 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400); |
|
864 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
|
865 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
|
866 return PHY_ERROR; |
|
867 } |
|
868 |
|
869 /* get phy interface type */ |
|
870 phyinterface = readl(base + NvRegPhyInterface); |
|
871 |
|
872 /* see if gigabit phy */ |
|
873 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
874 if (mii_status & PHY_GIGABIT) { |
|
875 np->gigabit = PHY_GIGABIT; |
|
876 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
877 mii_control_1000 &= ~ADVERTISE_1000HALF; |
|
878 if (phyinterface & PHY_RGMII) |
|
879 mii_control_1000 |= ADVERTISE_1000FULL; |
|
880 else |
|
881 mii_control_1000 &= ~ADVERTISE_1000FULL; |
|
882 |
|
883 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) { |
|
884 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
885 return PHY_ERROR; |
|
886 } |
|
887 } |
|
888 else |
|
889 np->gigabit = 0; |
|
890 |
|
891 /* reset the phy */ |
|
892 if (phy_reset(dev)) { |
|
893 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
|
894 return PHY_ERROR; |
|
895 } |
|
896 |
|
897 /* phy vendor specific configuration */ |
|
898 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
|
899 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
|
900 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); |
|
901 phy_reserved |= (PHY_INIT3 | PHY_INIT4); |
|
902 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
|
903 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
904 return PHY_ERROR; |
|
905 } |
|
906 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
|
907 phy_reserved |= PHY_INIT5; |
|
908 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
|
909 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
910 return PHY_ERROR; |
|
911 } |
|
912 } |
|
913 if (np->phy_oui == PHY_OUI_CICADA) { |
|
914 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
|
915 phy_reserved |= PHY_INIT6; |
|
916 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
|
917 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
918 return PHY_ERROR; |
|
919 } |
|
920 } |
|
921 |
|
922 /* restart auto negotiation */ |
|
923 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
924 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
|
925 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
|
926 return PHY_ERROR; |
|
927 } |
|
928 |
|
929 return 0; |
|
930 } |
|
931 |
|
932 static void nv_start_rx(struct net_device *dev) |
|
933 { |
|
934 struct fe_priv *np = netdev_priv(dev); |
|
935 u8 __iomem *base = get_hwbase(dev); |
|
936 |
|
937 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
|
938 /* Already running? Stop it. */ |
|
939 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { |
|
940 writel(0, base + NvRegReceiverControl); |
|
941 pci_push(base); |
|
942 } |
|
943 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
944 pci_push(base); |
|
945 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); |
|
946 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
|
947 dev->name, np->duplex, np->linkspeed); |
|
948 pci_push(base); |
|
949 } |
|
950 |
|
951 static void nv_stop_rx(struct net_device *dev) |
|
952 { |
|
953 u8 __iomem *base = get_hwbase(dev); |
|
954 |
|
955 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
|
956 writel(0, base + NvRegReceiverControl); |
|
957 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
|
958 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
|
959 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
|
960 |
|
961 udelay(NV_RXSTOP_DELAY2); |
|
962 writel(0, base + NvRegLinkSpeed); |
|
963 } |
|
964 |
|
965 static void nv_start_tx(struct net_device *dev) |
|
966 { |
|
967 u8 __iomem *base = get_hwbase(dev); |
|
968 |
|
969 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
|
970 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); |
|
971 pci_push(base); |
|
972 } |
|
973 |
|
974 static void nv_stop_tx(struct net_device *dev) |
|
975 { |
|
976 u8 __iomem *base = get_hwbase(dev); |
|
977 |
|
978 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
|
979 writel(0, base + NvRegTransmitterControl); |
|
980 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
|
981 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
|
982 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
|
983 |
|
984 udelay(NV_TXSTOP_DELAY2); |
|
985 writel(0, base + NvRegUnknownTransmitterReg); |
|
986 } |
|
987 |
|
988 static void nv_txrx_reset(struct net_device *dev) |
|
989 { |
|
990 struct fe_priv *np = netdev_priv(dev); |
|
991 u8 __iomem *base = get_hwbase(dev); |
|
992 |
|
993 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
|
994 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
995 pci_push(base); |
|
996 udelay(NV_TXRX_RESET_DELAY); |
|
997 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
998 pci_push(base); |
|
999 } |
|
1000 |
|
1001 static void nv_mac_reset(struct net_device *dev) |
|
1002 { |
|
1003 struct fe_priv *np = netdev_priv(dev); |
|
1004 u8 __iomem *base = get_hwbase(dev); |
|
1005 |
|
1006 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); |
|
1007 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1008 pci_push(base); |
|
1009 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
|
1010 pci_push(base); |
|
1011 udelay(NV_MAC_RESET_DELAY); |
|
1012 writel(0, base + NvRegMacReset); |
|
1013 pci_push(base); |
|
1014 udelay(NV_MAC_RESET_DELAY); |
|
1015 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1016 pci_push(base); |
|
1017 } |
|
1018 |
|
1019 /* |
|
1020 * nv_get_stats: dev->get_stats function |
|
1021 * Get latest stats value from the nic. |
|
1022 * Called with read_lock(&dev_base_lock) held for read - |
|
1023 * only synchronized against unregister_netdevice. |
|
1024 */ |
|
1025 static struct net_device_stats *nv_get_stats(struct net_device *dev) |
|
1026 { |
|
1027 struct fe_priv *np = netdev_priv(dev); |
|
1028 |
|
1029 /* It seems that the nic always generates interrupts and doesn't |
|
1030 * accumulate errors internally. Thus the current values in np->stats |
|
1031 * are already up to date. |
|
1032 */ |
|
1033 return &np->stats; |
|
1034 } |
|
1035 |
|
1036 /* |
|
1037 * nv_alloc_rx: fill rx ring entries. |
|
1038 * Return 1 if the allocations for the skbs failed and the |
|
1039 * rx engine is without Available descriptors |
|
1040 */ |
|
1041 static int nv_alloc_rx(struct net_device *dev) |
|
1042 { |
|
1043 struct fe_priv *np = netdev_priv(dev); |
|
1044 unsigned int refill_rx = np->refill_rx; |
|
1045 int nr; |
|
1046 |
|
1047 while (np->cur_rx != refill_rx) { |
|
1048 struct sk_buff *skb; |
|
1049 |
|
1050 nr = refill_rx % RX_RING; |
|
1051 if (np->rx_skbuff[nr] == NULL) { |
|
1052 |
|
1053 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
|
1054 if (!skb) |
|
1055 break; |
|
1056 |
|
1057 skb->dev = dev; |
|
1058 np->rx_skbuff[nr] = skb; |
|
1059 } else { |
|
1060 skb = np->rx_skbuff[nr]; |
|
1061 } |
|
1062 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, |
|
1063 skb->end-skb->data, PCI_DMA_FROMDEVICE); |
|
1064 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1065 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); |
|
1066 wmb(); |
|
1067 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); |
|
1068 } else { |
|
1069 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32; |
|
1070 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; |
|
1071 wmb(); |
|
1072 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); |
|
1073 } |
|
1074 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
|
1075 dev->name, refill_rx); |
|
1076 refill_rx++; |
|
1077 } |
|
1078 np->refill_rx = refill_rx; |
|
1079 if (np->cur_rx - refill_rx == RX_RING) |
|
1080 return 1; |
|
1081 return 0; |
|
1082 } |
|
1083 |
|
1084 static void nv_do_rx_refill(unsigned long data) |
|
1085 { |
|
1086 struct net_device *dev = (struct net_device *) data; |
|
1087 struct fe_priv *np = netdev_priv(dev); |
|
1088 |
|
1089 if (!using_multi_irqs(dev)) { |
|
1090 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1091 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1092 else |
|
1093 disable_irq(dev->irq); |
|
1094 } else { |
|
1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1096 } |
|
1097 if (nv_alloc_rx(dev)) { |
|
1098 spin_lock_irq(&np->lock); |
|
1099 if (!np->in_shutdown) |
|
1100 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
1101 spin_unlock_irq(&np->lock); |
|
1102 } |
|
1103 if (!using_multi_irqs(dev)) { |
|
1104 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1105 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1106 else |
|
1107 enable_irq(dev->irq); |
|
1108 } else { |
|
1109 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1110 } |
|
1111 } |
|
1112 |
|
1113 static void nv_init_rx(struct net_device *dev) |
|
1114 { |
|
1115 struct fe_priv *np = netdev_priv(dev); |
|
1116 int i; |
|
1117 |
|
1118 np->cur_rx = RX_RING; |
|
1119 np->refill_rx = 0; |
|
1120 for (i = 0; i < RX_RING; i++) |
|
1121 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1122 np->rx_ring.orig[i].FlagLen = 0; |
|
1123 else |
|
1124 np->rx_ring.ex[i].FlagLen = 0; |
|
1125 } |
|
1126 |
|
1127 static void nv_init_tx(struct net_device *dev) |
|
1128 { |
|
1129 struct fe_priv *np = netdev_priv(dev); |
|
1130 int i; |
|
1131 |
|
1132 np->next_tx = np->nic_tx = 0; |
|
1133 for (i = 0; i < TX_RING; i++) { |
|
1134 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1135 np->tx_ring.orig[i].FlagLen = 0; |
|
1136 else |
|
1137 np->tx_ring.ex[i].FlagLen = 0; |
|
1138 np->tx_skbuff[i] = NULL; |
|
1139 np->tx_dma[i] = 0; |
|
1140 } |
|
1141 } |
|
1142 |
|
1143 static int nv_init_ring(struct net_device *dev) |
|
1144 { |
|
1145 nv_init_tx(dev); |
|
1146 nv_init_rx(dev); |
|
1147 return nv_alloc_rx(dev); |
|
1148 } |
|
1149 |
|
1150 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
|
1151 { |
|
1152 struct fe_priv *np = netdev_priv(dev); |
|
1153 |
|
1154 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", |
|
1155 dev->name, skbnr); |
|
1156 |
|
1157 if (np->tx_dma[skbnr]) { |
|
1158 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr], |
|
1159 np->tx_dma_len[skbnr], |
|
1160 PCI_DMA_TODEVICE); |
|
1161 np->tx_dma[skbnr] = 0; |
|
1162 } |
|
1163 |
|
1164 if (np->tx_skbuff[skbnr]) { |
|
1165 dev_kfree_skb_any(np->tx_skbuff[skbnr]); |
|
1166 np->tx_skbuff[skbnr] = NULL; |
|
1167 return 1; |
|
1168 } else { |
|
1169 return 0; |
|
1170 } |
|
1171 } |
|
1172 |
|
1173 static void nv_drain_tx(struct net_device *dev) |
|
1174 { |
|
1175 struct fe_priv *np = netdev_priv(dev); |
|
1176 unsigned int i; |
|
1177 |
|
1178 for (i = 0; i < TX_RING; i++) { |
|
1179 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1180 np->tx_ring.orig[i].FlagLen = 0; |
|
1181 else |
|
1182 np->tx_ring.ex[i].FlagLen = 0; |
|
1183 if (nv_release_txskb(dev, i)) |
|
1184 np->stats.tx_dropped++; |
|
1185 } |
|
1186 } |
|
1187 |
|
1188 static void nv_drain_rx(struct net_device *dev) |
|
1189 { |
|
1190 struct fe_priv *np = netdev_priv(dev); |
|
1191 int i; |
|
1192 for (i = 0; i < RX_RING; i++) { |
|
1193 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1194 np->rx_ring.orig[i].FlagLen = 0; |
|
1195 else |
|
1196 np->rx_ring.ex[i].FlagLen = 0; |
|
1197 wmb(); |
|
1198 if (np->rx_skbuff[i]) { |
|
1199 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1200 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1201 PCI_DMA_FROMDEVICE); |
|
1202 dev_kfree_skb(np->rx_skbuff[i]); |
|
1203 np->rx_skbuff[i] = NULL; |
|
1204 } |
|
1205 } |
|
1206 } |
|
1207 |
|
1208 static void drain_ring(struct net_device *dev) |
|
1209 { |
|
1210 nv_drain_tx(dev); |
|
1211 nv_drain_rx(dev); |
|
1212 } |
|
1213 |
|
1214 /* |
|
1215 * nv_start_xmit: dev->hard_start_xmit function |
|
1216 * Called with dev->xmit_lock held. |
|
1217 */ |
|
1218 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
1219 { |
|
1220 struct fe_priv *np = netdev_priv(dev); |
|
1221 u32 tx_flags = 0; |
|
1222 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
|
1223 unsigned int fragments = skb_shinfo(skb)->nr_frags; |
|
1224 unsigned int nr = (np->next_tx - 1) % TX_RING; |
|
1225 unsigned int start_nr = np->next_tx % TX_RING; |
|
1226 unsigned int i; |
|
1227 u32 offset = 0; |
|
1228 u32 bcnt; |
|
1229 u32 size = skb->len-skb->data_len; |
|
1230 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1231 u32 tx_flags_vlan = 0; |
|
1232 |
|
1233 /* add fragments to entries count */ |
|
1234 for (i = 0; i < fragments; i++) { |
|
1235 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
|
1236 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1237 } |
|
1238 |
|
1239 spin_lock_irq(&np->lock); |
|
1240 |
|
1241 if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) { |
|
1242 spin_unlock_irq(&np->lock); |
|
1243 netif_stop_queue(dev); |
|
1244 return NETDEV_TX_BUSY; |
|
1245 } |
|
1246 |
|
1247 /* setup the header buffer */ |
|
1248 do { |
|
1249 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1250 nr = (nr + 1) % TX_RING; |
|
1251 |
|
1252 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
|
1253 PCI_DMA_TODEVICE); |
|
1254 np->tx_dma_len[nr] = bcnt; |
|
1255 |
|
1256 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1257 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
|
1258 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1259 } else { |
|
1260 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1261 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1262 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1263 } |
|
1264 tx_flags = np->tx_flags; |
|
1265 offset += bcnt; |
|
1266 size -= bcnt; |
|
1267 } while(size); |
|
1268 |
|
1269 /* setup the fragments */ |
|
1270 for (i = 0; i < fragments; i++) { |
|
1271 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
|
1272 u32 size = frag->size; |
|
1273 offset = 0; |
|
1274 |
|
1275 do { |
|
1276 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1277 nr = (nr + 1) % TX_RING; |
|
1278 |
|
1279 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
|
1280 PCI_DMA_TODEVICE); |
|
1281 np->tx_dma_len[nr] = bcnt; |
|
1282 |
|
1283 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1284 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
|
1285 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1286 } else { |
|
1287 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1288 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1289 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1290 } |
|
1291 offset += bcnt; |
|
1292 size -= bcnt; |
|
1293 } while (size); |
|
1294 } |
|
1295 |
|
1296 /* set last fragment flag */ |
|
1297 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1298 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
|
1299 } else { |
|
1300 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
|
1301 } |
|
1302 |
|
1303 np->tx_skbuff[nr] = skb; |
|
1304 |
|
1305 #ifdef NETIF_F_TSO |
|
1306 if (skb_shinfo(skb)->tso_size) |
|
1307 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT); |
|
1308 else |
|
1309 #endif |
|
1310 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
|
1311 |
|
1312 /* vlan tag */ |
|
1313 if (np->vlangrp && vlan_tx_tag_present(skb)) { |
|
1314 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb); |
|
1315 } |
|
1316 |
|
1317 /* set tx flags */ |
|
1318 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1319 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1320 } else { |
|
1321 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan); |
|
1322 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1323 } |
|
1324 |
|
1325 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", |
|
1326 dev->name, np->next_tx, entries, tx_flags_extra); |
|
1327 { |
|
1328 int j; |
|
1329 for (j=0; j<64; j++) { |
|
1330 if ((j%16) == 0) |
|
1331 dprintk("\n%03x:", j); |
|
1332 dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
|
1333 } |
|
1334 dprintk("\n"); |
|
1335 } |
|
1336 |
|
1337 np->next_tx += entries; |
|
1338 |
|
1339 dev->trans_start = jiffies; |
|
1340 spin_unlock_irq(&np->lock); |
|
1341 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
1342 pci_push(get_hwbase(dev)); |
|
1343 return NETDEV_TX_OK; |
|
1344 } |
|
1345 |
|
1346 /* |
|
1347 * nv_tx_done: check for completed packets, release the skbs. |
|
1348 * |
|
1349 * Caller must own np->lock. |
|
1350 */ |
|
1351 static void nv_tx_done(struct net_device *dev) |
|
1352 { |
|
1353 struct fe_priv *np = netdev_priv(dev); |
|
1354 u32 Flags; |
|
1355 unsigned int i; |
|
1356 struct sk_buff *skb; |
|
1357 |
|
1358 while (np->nic_tx != np->next_tx) { |
|
1359 i = np->nic_tx % TX_RING; |
|
1360 |
|
1361 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1362 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen); |
|
1363 else |
|
1364 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen); |
|
1365 |
|
1366 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", |
|
1367 dev->name, np->nic_tx, Flags); |
|
1368 if (Flags & NV_TX_VALID) |
|
1369 break; |
|
1370 if (np->desc_ver == DESC_VER_1) { |
|
1371 if (Flags & NV_TX_LASTPACKET) { |
|
1372 skb = np->tx_skbuff[i]; |
|
1373 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
|
1374 NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
|
1375 if (Flags & NV_TX_UNDERFLOW) |
|
1376 np->stats.tx_fifo_errors++; |
|
1377 if (Flags & NV_TX_CARRIERLOST) |
|
1378 np->stats.tx_carrier_errors++; |
|
1379 np->stats.tx_errors++; |
|
1380 } else { |
|
1381 np->stats.tx_packets++; |
|
1382 np->stats.tx_bytes += skb->len; |
|
1383 } |
|
1384 } |
|
1385 } else { |
|
1386 if (Flags & NV_TX2_LASTPACKET) { |
|
1387 skb = np->tx_skbuff[i]; |
|
1388 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
|
1389 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
|
1390 if (Flags & NV_TX2_UNDERFLOW) |
|
1391 np->stats.tx_fifo_errors++; |
|
1392 if (Flags & NV_TX2_CARRIERLOST) |
|
1393 np->stats.tx_carrier_errors++; |
|
1394 np->stats.tx_errors++; |
|
1395 } else { |
|
1396 np->stats.tx_packets++; |
|
1397 np->stats.tx_bytes += skb->len; |
|
1398 } |
|
1399 } |
|
1400 } |
|
1401 nv_release_txskb(dev, i); |
|
1402 np->nic_tx++; |
|
1403 } |
|
1404 if (np->next_tx - np->nic_tx < TX_LIMIT_START) |
|
1405 netif_wake_queue(dev); |
|
1406 } |
|
1407 |
|
1408 /* |
|
1409 * nv_tx_timeout: dev->tx_timeout function |
|
1410 * Called with dev->xmit_lock held. |
|
1411 */ |
|
1412 static void nv_tx_timeout(struct net_device *dev) |
|
1413 { |
|
1414 struct fe_priv *np = netdev_priv(dev); |
|
1415 u8 __iomem *base = get_hwbase(dev); |
|
1416 u32 status; |
|
1417 |
|
1418 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1419 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1420 else |
|
1421 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1422 |
|
1423 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
|
1424 |
|
1425 { |
|
1426 int i; |
|
1427 |
|
1428 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n", |
|
1429 dev->name, (unsigned long)np->ring_addr, |
|
1430 np->next_tx, np->nic_tx); |
|
1431 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
|
1432 for (i=0;i<=np->register_size;i+= 32) { |
|
1433 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
|
1434 i, |
|
1435 readl(base + i + 0), readl(base + i + 4), |
|
1436 readl(base + i + 8), readl(base + i + 12), |
|
1437 readl(base + i + 16), readl(base + i + 20), |
|
1438 readl(base + i + 24), readl(base + i + 28)); |
|
1439 } |
|
1440 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); |
|
1441 for (i=0;i<TX_RING;i+= 4) { |
|
1442 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1443 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
|
1444 i, |
|
1445 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), |
|
1446 le32_to_cpu(np->tx_ring.orig[i].FlagLen), |
|
1447 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), |
|
1448 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen), |
|
1449 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer), |
|
1450 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen), |
|
1451 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer), |
|
1452 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); |
|
1453 } else { |
|
1454 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
|
1455 i, |
|
1456 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), |
|
1457 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), |
|
1458 le32_to_cpu(np->tx_ring.ex[i].FlagLen), |
|
1459 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh), |
|
1460 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow), |
|
1461 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen), |
|
1462 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh), |
|
1463 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow), |
|
1464 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen), |
|
1465 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh), |
|
1466 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow), |
|
1467 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen)); |
|
1468 } |
|
1469 } |
|
1470 } |
|
1471 |
|
1472 spin_lock_irq(&np->lock); |
|
1473 |
|
1474 /* 1) stop tx engine */ |
|
1475 nv_stop_tx(dev); |
|
1476 |
|
1477 /* 2) check that the packets were not sent already: */ |
|
1478 nv_tx_done(dev); |
|
1479 |
|
1480 /* 3) if there are dead entries: clear everything */ |
|
1481 if (np->next_tx != np->nic_tx) { |
|
1482 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
|
1483 nv_drain_tx(dev); |
|
1484 np->next_tx = np->nic_tx = 0; |
|
1485 setup_hw_rings(dev, NV_SETUP_TX_RING); |
|
1486 netif_wake_queue(dev); |
|
1487 } |
|
1488 |
|
1489 /* 4) restart tx engine */ |
|
1490 nv_start_tx(dev); |
|
1491 spin_unlock_irq(&np->lock); |
|
1492 } |
|
1493 |
|
1494 /* |
|
1495 * Called when the nic notices a mismatch between the actual data len on the |
|
1496 * wire and the len indicated in the 802 header |
|
1497 */ |
|
1498 static int nv_getlen(struct net_device *dev, void *packet, int datalen) |
|
1499 { |
|
1500 int hdrlen; /* length of the 802 header */ |
|
1501 int protolen; /* length as stored in the proto field */ |
|
1502 |
|
1503 /* 1) calculate len according to header */ |
|
1504 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { |
|
1505 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
|
1506 hdrlen = VLAN_HLEN; |
|
1507 } else { |
|
1508 protolen = ntohs( ((struct ethhdr *)packet)->h_proto); |
|
1509 hdrlen = ETH_HLEN; |
|
1510 } |
|
1511 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", |
|
1512 dev->name, datalen, protolen, hdrlen); |
|
1513 if (protolen > ETH_DATA_LEN) |
|
1514 return datalen; /* Value in proto field not a len, no checks possible */ |
|
1515 |
|
1516 protolen += hdrlen; |
|
1517 /* consistency checks: */ |
|
1518 if (datalen > ETH_ZLEN) { |
|
1519 if (datalen >= protolen) { |
|
1520 /* more data on wire than in 802 header, trim of |
|
1521 * additional data. |
|
1522 */ |
|
1523 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1524 dev->name, protolen); |
|
1525 return protolen; |
|
1526 } else { |
|
1527 /* less data on wire than mentioned in header. |
|
1528 * Discard the packet. |
|
1529 */ |
|
1530 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", |
|
1531 dev->name); |
|
1532 return -1; |
|
1533 } |
|
1534 } else { |
|
1535 /* short packet. Accept only if 802 values are also short */ |
|
1536 if (protolen > ETH_ZLEN) { |
|
1537 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", |
|
1538 dev->name); |
|
1539 return -1; |
|
1540 } |
|
1541 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1542 dev->name, datalen); |
|
1543 return datalen; |
|
1544 } |
|
1545 } |
|
1546 |
|
1547 static void nv_rx_process(struct net_device *dev) |
|
1548 { |
|
1549 struct fe_priv *np = netdev_priv(dev); |
|
1550 u32 Flags; |
|
1551 u32 vlanflags = 0; |
|
1552 |
|
1553 |
|
1554 for (;;) { |
|
1555 struct sk_buff *skb; |
|
1556 int len; |
|
1557 int i; |
|
1558 if (np->cur_rx - np->refill_rx >= RX_RING) |
|
1559 break; /* we scanned the whole ring - do not continue */ |
|
1560 |
|
1561 i = np->cur_rx % RX_RING; |
|
1562 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1563 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen); |
|
1564 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); |
|
1565 } else { |
|
1566 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen); |
|
1567 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); |
|
1568 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow); |
|
1569 } |
|
1570 |
|
1571 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", |
|
1572 dev->name, np->cur_rx, Flags); |
|
1573 |
|
1574 if (Flags & NV_RX_AVAIL) |
|
1575 break; /* still owned by hardware, */ |
|
1576 |
|
1577 /* |
|
1578 * the packet is for us - immediately tear down the pci mapping. |
|
1579 * TODO: check if a prefetch of the first cacheline improves |
|
1580 * the performance. |
|
1581 */ |
|
1582 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1583 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1584 PCI_DMA_FROMDEVICE); |
|
1585 |
|
1586 { |
|
1587 int j; |
|
1588 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags); |
|
1589 for (j=0; j<64; j++) { |
|
1590 if ((j%16) == 0) |
|
1591 dprintk("\n%03x:", j); |
|
1592 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); |
|
1593 } |
|
1594 dprintk("\n"); |
|
1595 } |
|
1596 /* look at what we actually got: */ |
|
1597 if (np->desc_ver == DESC_VER_1) { |
|
1598 if (!(Flags & NV_RX_DESCRIPTORVALID)) |
|
1599 goto next_pkt; |
|
1600 |
|
1601 if (Flags & NV_RX_ERROR) { |
|
1602 if (Flags & NV_RX_MISSEDFRAME) { |
|
1603 np->stats.rx_missed_errors++; |
|
1604 np->stats.rx_errors++; |
|
1605 goto next_pkt; |
|
1606 } |
|
1607 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
|
1608 np->stats.rx_errors++; |
|
1609 goto next_pkt; |
|
1610 } |
|
1611 if (Flags & NV_RX_CRCERR) { |
|
1612 np->stats.rx_crc_errors++; |
|
1613 np->stats.rx_errors++; |
|
1614 goto next_pkt; |
|
1615 } |
|
1616 if (Flags & NV_RX_OVERFLOW) { |
|
1617 np->stats.rx_over_errors++; |
|
1618 np->stats.rx_errors++; |
|
1619 goto next_pkt; |
|
1620 } |
|
1621 if (Flags & NV_RX_ERROR4) { |
|
1622 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1623 if (len < 0) { |
|
1624 np->stats.rx_errors++; |
|
1625 goto next_pkt; |
|
1626 } |
|
1627 } |
|
1628 /* framing errors are soft errors. */ |
|
1629 if (Flags & NV_RX_FRAMINGERR) { |
|
1630 if (Flags & NV_RX_SUBSTRACT1) { |
|
1631 len--; |
|
1632 } |
|
1633 } |
|
1634 } |
|
1635 } else { |
|
1636 if (!(Flags & NV_RX2_DESCRIPTORVALID)) |
|
1637 goto next_pkt; |
|
1638 |
|
1639 if (Flags & NV_RX2_ERROR) { |
|
1640 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { |
|
1641 np->stats.rx_errors++; |
|
1642 goto next_pkt; |
|
1643 } |
|
1644 if (Flags & NV_RX2_CRCERR) { |
|
1645 np->stats.rx_crc_errors++; |
|
1646 np->stats.rx_errors++; |
|
1647 goto next_pkt; |
|
1648 } |
|
1649 if (Flags & NV_RX2_OVERFLOW) { |
|
1650 np->stats.rx_over_errors++; |
|
1651 np->stats.rx_errors++; |
|
1652 goto next_pkt; |
|
1653 } |
|
1654 if (Flags & NV_RX2_ERROR4) { |
|
1655 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1656 if (len < 0) { |
|
1657 np->stats.rx_errors++; |
|
1658 goto next_pkt; |
|
1659 } |
|
1660 } |
|
1661 /* framing errors are soft errors */ |
|
1662 if (Flags & NV_RX2_FRAMINGERR) { |
|
1663 if (Flags & NV_RX2_SUBSTRACT1) { |
|
1664 len--; |
|
1665 } |
|
1666 } |
|
1667 } |
|
1668 Flags &= NV_RX2_CHECKSUMMASK; |
|
1669 if (Flags == NV_RX2_CHECKSUMOK1 || |
|
1670 Flags == NV_RX2_CHECKSUMOK2 || |
|
1671 Flags == NV_RX2_CHECKSUMOK3) { |
|
1672 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); |
|
1673 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; |
|
1674 } else { |
|
1675 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); |
|
1676 } |
|
1677 } |
|
1678 /* got a valid packet - forward it to the network core */ |
|
1679 skb = np->rx_skbuff[i]; |
|
1680 np->rx_skbuff[i] = NULL; |
|
1681 |
|
1682 skb_put(skb, len); |
|
1683 skb->protocol = eth_type_trans(skb, dev); |
|
1684 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", |
|
1685 dev->name, np->cur_rx, len, skb->protocol); |
|
1686 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) { |
|
1687 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); |
|
1688 } else { |
|
1689 netif_rx(skb); |
|
1690 } |
|
1691 dev->last_rx = jiffies; |
|
1692 np->stats.rx_packets++; |
|
1693 np->stats.rx_bytes += len; |
|
1694 next_pkt: |
|
1695 np->cur_rx++; |
|
1696 } |
|
1697 } |
|
1698 |
|
1699 static void set_bufsize(struct net_device *dev) |
|
1700 { |
|
1701 struct fe_priv *np = netdev_priv(dev); |
|
1702 |
|
1703 if (dev->mtu <= ETH_DATA_LEN) |
|
1704 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; |
|
1705 else |
|
1706 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; |
|
1707 } |
|
1708 |
|
1709 /* |
|
1710 * nv_change_mtu: dev->change_mtu function |
|
1711 * Called with dev_base_lock held for read. |
|
1712 */ |
|
1713 static int nv_change_mtu(struct net_device *dev, int new_mtu) |
|
1714 { |
|
1715 struct fe_priv *np = netdev_priv(dev); |
|
1716 int old_mtu; |
|
1717 |
|
1718 if (new_mtu < 64 || new_mtu > np->pkt_limit) |
|
1719 return -EINVAL; |
|
1720 |
|
1721 old_mtu = dev->mtu; |
|
1722 dev->mtu = new_mtu; |
|
1723 |
|
1724 /* return early if the buffer sizes will not change */ |
|
1725 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) |
|
1726 return 0; |
|
1727 if (old_mtu == new_mtu) |
|
1728 return 0; |
|
1729 |
|
1730 /* synchronized against open : rtnl_lock() held by caller */ |
|
1731 if (netif_running(dev)) { |
|
1732 u8 __iomem *base = get_hwbase(dev); |
|
1733 /* |
|
1734 * It seems that the nic preloads valid ring entries into an |
|
1735 * internal buffer. The procedure for flushing everything is |
|
1736 * guessed, there is probably a simpler approach. |
|
1737 * Changing the MTU is a rare event, it shouldn't matter. |
|
1738 */ |
|
1739 nv_disable_irq(dev); |
|
1740 spin_lock_bh(&dev->xmit_lock); |
|
1741 spin_lock(&np->lock); |
|
1742 /* stop engines */ |
|
1743 nv_stop_rx(dev); |
|
1744 nv_stop_tx(dev); |
|
1745 nv_txrx_reset(dev); |
|
1746 /* drain rx queue */ |
|
1747 nv_drain_rx(dev); |
|
1748 nv_drain_tx(dev); |
|
1749 /* reinit driver view of the rx queue */ |
|
1750 nv_init_rx(dev); |
|
1751 nv_init_tx(dev); |
|
1752 /* alloc new rx buffers */ |
|
1753 set_bufsize(dev); |
|
1754 if (nv_alloc_rx(dev)) { |
|
1755 if (!np->in_shutdown) |
|
1756 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
1757 } |
|
1758 /* reinit nic view of the rx queue */ |
|
1759 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
1760 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
1761 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
|
1762 base + NvRegRingSizes); |
|
1763 pci_push(base); |
|
1764 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
1765 pci_push(base); |
|
1766 |
|
1767 /* restart rx engine */ |
|
1768 nv_start_rx(dev); |
|
1769 nv_start_tx(dev); |
|
1770 spin_unlock(&np->lock); |
|
1771 spin_unlock_bh(&dev->xmit_lock); |
|
1772 nv_enable_irq(dev); |
|
1773 } |
|
1774 return 0; |
|
1775 } |
|
1776 |
|
1777 static void nv_copy_mac_to_hw(struct net_device *dev) |
|
1778 { |
|
1779 u8 __iomem *base = get_hwbase(dev); |
|
1780 u32 mac[2]; |
|
1781 |
|
1782 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
|
1783 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
|
1784 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
|
1785 |
|
1786 writel(mac[0], base + NvRegMacAddrA); |
|
1787 writel(mac[1], base + NvRegMacAddrB); |
|
1788 } |
|
1789 |
|
1790 /* |
|
1791 * nv_set_mac_address: dev->set_mac_address function |
|
1792 * Called with rtnl_lock() held. |
|
1793 */ |
|
1794 static int nv_set_mac_address(struct net_device *dev, void *addr) |
|
1795 { |
|
1796 struct fe_priv *np = netdev_priv(dev); |
|
1797 struct sockaddr *macaddr = (struct sockaddr*)addr; |
|
1798 |
|
1799 if(!is_valid_ether_addr(macaddr->sa_data)) |
|
1800 return -EADDRNOTAVAIL; |
|
1801 |
|
1802 /* synchronized against open : rtnl_lock() held by caller */ |
|
1803 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); |
|
1804 |
|
1805 if (netif_running(dev)) { |
|
1806 spin_lock_bh(&dev->xmit_lock); |
|
1807 spin_lock_irq(&np->lock); |
|
1808 |
|
1809 /* stop rx engine */ |
|
1810 nv_stop_rx(dev); |
|
1811 |
|
1812 /* set mac address */ |
|
1813 nv_copy_mac_to_hw(dev); |
|
1814 |
|
1815 /* restart rx engine */ |
|
1816 nv_start_rx(dev); |
|
1817 spin_unlock_irq(&np->lock); |
|
1818 spin_unlock_bh(&dev->xmit_lock); |
|
1819 } else { |
|
1820 nv_copy_mac_to_hw(dev); |
|
1821 } |
|
1822 return 0; |
|
1823 } |
|
1824 |
|
1825 /* |
|
1826 * nv_set_multicast: dev->set_multicast function |
|
1827 * Called with dev->xmit_lock held. |
|
1828 */ |
|
1829 static void nv_set_multicast(struct net_device *dev) |
|
1830 { |
|
1831 struct fe_priv *np = netdev_priv(dev); |
|
1832 u8 __iomem *base = get_hwbase(dev); |
|
1833 u32 addr[2]; |
|
1834 u32 mask[2]; |
|
1835 u32 pff; |
|
1836 |
|
1837 memset(addr, 0, sizeof(addr)); |
|
1838 memset(mask, 0, sizeof(mask)); |
|
1839 |
|
1840 if (dev->flags & IFF_PROMISC) { |
|
1841 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); |
|
1842 pff = NVREG_PFF_PROMISC; |
|
1843 } else { |
|
1844 pff = NVREG_PFF_MYADDR; |
|
1845 |
|
1846 if (dev->flags & IFF_ALLMULTI || dev->mc_list) { |
|
1847 u32 alwaysOff[2]; |
|
1848 u32 alwaysOn[2]; |
|
1849 |
|
1850 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; |
|
1851 if (dev->flags & IFF_ALLMULTI) { |
|
1852 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; |
|
1853 } else { |
|
1854 struct dev_mc_list *walk; |
|
1855 |
|
1856 walk = dev->mc_list; |
|
1857 while (walk != NULL) { |
|
1858 u32 a, b; |
|
1859 a = le32_to_cpu(*(u32 *) walk->dmi_addr); |
|
1860 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); |
|
1861 alwaysOn[0] &= a; |
|
1862 alwaysOff[0] &= ~a; |
|
1863 alwaysOn[1] &= b; |
|
1864 alwaysOff[1] &= ~b; |
|
1865 walk = walk->next; |
|
1866 } |
|
1867 } |
|
1868 addr[0] = alwaysOn[0]; |
|
1869 addr[1] = alwaysOn[1]; |
|
1870 mask[0] = alwaysOn[0] | alwaysOff[0]; |
|
1871 mask[1] = alwaysOn[1] | alwaysOff[1]; |
|
1872 } |
|
1873 } |
|
1874 addr[0] |= NVREG_MCASTADDRA_FORCE; |
|
1875 pff |= NVREG_PFF_ALWAYS; |
|
1876 spin_lock_irq(&np->lock); |
|
1877 nv_stop_rx(dev); |
|
1878 writel(addr[0], base + NvRegMulticastAddrA); |
|
1879 writel(addr[1], base + NvRegMulticastAddrB); |
|
1880 writel(mask[0], base + NvRegMulticastMaskA); |
|
1881 writel(mask[1], base + NvRegMulticastMaskB); |
|
1882 writel(pff, base + NvRegPacketFilterFlags); |
|
1883 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", |
|
1884 dev->name); |
|
1885 nv_start_rx(dev); |
|
1886 spin_unlock_irq(&np->lock); |
|
1887 } |
|
1888 |
|
1889 /** |
|
1890 * nv_update_linkspeed: Setup the MAC according to the link partner |
|
1891 * @dev: Network device to be configured |
|
1892 * |
|
1893 * The function queries the PHY and checks if there is a link partner. |
|
1894 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is |
|
1895 * set to 10 MBit HD. |
|
1896 * |
|
1897 * The function returns 0 if there is no link partner and 1 if there is |
|
1898 * a good link partner. |
|
1899 */ |
|
1900 static int nv_update_linkspeed(struct net_device *dev) |
|
1901 { |
|
1902 struct fe_priv *np = netdev_priv(dev); |
|
1903 u8 __iomem *base = get_hwbase(dev); |
|
1904 int adv, lpa; |
|
1905 int newls = np->linkspeed; |
|
1906 int newdup = np->duplex; |
|
1907 int mii_status; |
|
1908 int retval = 0; |
|
1909 u32 control_1000, status_1000, phyreg; |
|
1910 |
|
1911 /* BMSR_LSTATUS is latched, read it twice: |
|
1912 * we want the current value. |
|
1913 */ |
|
1914 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
1915 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
1916 |
|
1917 if (!(mii_status & BMSR_LSTATUS)) { |
|
1918 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", |
|
1919 dev->name); |
|
1920 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1921 newdup = 0; |
|
1922 retval = 0; |
|
1923 goto set_speed; |
|
1924 } |
|
1925 |
|
1926 if (np->autoneg == 0) { |
|
1927 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
|
1928 dev->name, np->fixed_mode); |
|
1929 if (np->fixed_mode & LPA_100FULL) { |
|
1930 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1931 newdup = 1; |
|
1932 } else if (np->fixed_mode & LPA_100HALF) { |
|
1933 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1934 newdup = 0; |
|
1935 } else if (np->fixed_mode & LPA_10FULL) { |
|
1936 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1937 newdup = 1; |
|
1938 } else { |
|
1939 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1940 newdup = 0; |
|
1941 } |
|
1942 retval = 1; |
|
1943 goto set_speed; |
|
1944 } |
|
1945 /* check auto negotiation is complete */ |
|
1946 if (!(mii_status & BMSR_ANEGCOMPLETE)) { |
|
1947 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ |
|
1948 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1949 newdup = 0; |
|
1950 retval = 0; |
|
1951 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); |
|
1952 goto set_speed; |
|
1953 } |
|
1954 |
|
1955 retval = 1; |
|
1956 if (np->gigabit == PHY_GIGABIT) { |
|
1957 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
1958 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ); |
|
1959 |
|
1960 if ((control_1000 & ADVERTISE_1000FULL) && |
|
1961 (status_1000 & LPA_1000FULL)) { |
|
1962 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", |
|
1963 dev->name); |
|
1964 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
|
1965 newdup = 1; |
|
1966 goto set_speed; |
|
1967 } |
|
1968 } |
|
1969 |
|
1970 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
1971 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
|
1972 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
|
1973 dev->name, adv, lpa); |
|
1974 |
|
1975 /* FIXME: handle parallel detection properly */ |
|
1976 lpa = lpa & adv; |
|
1977 if (lpa & LPA_100FULL) { |
|
1978 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1979 newdup = 1; |
|
1980 } else if (lpa & LPA_100HALF) { |
|
1981 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1982 newdup = 0; |
|
1983 } else if (lpa & LPA_10FULL) { |
|
1984 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1985 newdup = 1; |
|
1986 } else if (lpa & LPA_10HALF) { |
|
1987 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1988 newdup = 0; |
|
1989 } else { |
|
1990 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa); |
|
1991 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1992 newdup = 0; |
|
1993 } |
|
1994 |
|
1995 set_speed: |
|
1996 if (np->duplex == newdup && np->linkspeed == newls) |
|
1997 return retval; |
|
1998 |
|
1999 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", |
|
2000 dev->name, np->linkspeed, np->duplex, newls, newdup); |
|
2001 |
|
2002 np->duplex = newdup; |
|
2003 np->linkspeed = newls; |
|
2004 |
|
2005 if (np->gigabit == PHY_GIGABIT) { |
|
2006 phyreg = readl(base + NvRegRandomSeed); |
|
2007 phyreg &= ~(0x3FF00); |
|
2008 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) |
|
2009 phyreg |= NVREG_RNDSEED_FORCE3; |
|
2010 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) |
|
2011 phyreg |= NVREG_RNDSEED_FORCE2; |
|
2012 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
|
2013 phyreg |= NVREG_RNDSEED_FORCE; |
|
2014 writel(phyreg, base + NvRegRandomSeed); |
|
2015 } |
|
2016 |
|
2017 phyreg = readl(base + NvRegPhyInterface); |
|
2018 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); |
|
2019 if (np->duplex == 0) |
|
2020 phyreg |= PHY_HALF; |
|
2021 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) |
|
2022 phyreg |= PHY_100; |
|
2023 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
|
2024 phyreg |= PHY_1000; |
|
2025 writel(phyreg, base + NvRegPhyInterface); |
|
2026 |
|
2027 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
|
2028 base + NvRegMisc1); |
|
2029 pci_push(base); |
|
2030 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
2031 pci_push(base); |
|
2032 |
|
2033 return retval; |
|
2034 } |
|
2035 |
|
2036 static void nv_linkchange(struct net_device *dev) |
|
2037 { |
|
2038 if (nv_update_linkspeed(dev)) { |
|
2039 if (!netif_carrier_ok(dev)) { |
|
2040 netif_carrier_on(dev); |
|
2041 printk(KERN_INFO "%s: link up.\n", dev->name); |
|
2042 nv_start_rx(dev); |
|
2043 } |
|
2044 } else { |
|
2045 if (netif_carrier_ok(dev)) { |
|
2046 netif_carrier_off(dev); |
|
2047 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
2048 nv_stop_rx(dev); |
|
2049 } |
|
2050 } |
|
2051 } |
|
2052 |
|
2053 static void nv_link_irq(struct net_device *dev) |
|
2054 { |
|
2055 u8 __iomem *base = get_hwbase(dev); |
|
2056 u32 miistat; |
|
2057 |
|
2058 miistat = readl(base + NvRegMIIStatus); |
|
2059 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
2060 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
|
2061 |
|
2062 if (miistat & (NVREG_MIISTAT_LINKCHANGE)) |
|
2063 nv_linkchange(dev); |
|
2064 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); |
|
2065 } |
|
2066 |
|
2067 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
|
2068 { |
|
2069 struct net_device *dev = (struct net_device *) data; |
|
2070 struct fe_priv *np = netdev_priv(dev); |
|
2071 u8 __iomem *base = get_hwbase(dev); |
|
2072 u32 events; |
|
2073 int i; |
|
2074 |
|
2075 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); |
|
2076 |
|
2077 for (i=0; ; i++) { |
|
2078 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
|
2079 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2080 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2081 } else { |
|
2082 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2083 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
|
2084 } |
|
2085 pci_push(base); |
|
2086 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2087 if (!(events & np->irqmask)) |
|
2088 break; |
|
2089 |
|
2090 spin_lock(&np->lock); |
|
2091 nv_tx_done(dev); |
|
2092 spin_unlock(&np->lock); |
|
2093 |
|
2094 nv_rx_process(dev); |
|
2095 if (nv_alloc_rx(dev)) { |
|
2096 spin_lock(&np->lock); |
|
2097 if (!np->in_shutdown) |
|
2098 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2099 spin_unlock(&np->lock); |
|
2100 } |
|
2101 |
|
2102 if (events & NVREG_IRQ_LINK) { |
|
2103 spin_lock(&np->lock); |
|
2104 nv_link_irq(dev); |
|
2105 spin_unlock(&np->lock); |
|
2106 } |
|
2107 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2108 spin_lock(&np->lock); |
|
2109 nv_linkchange(dev); |
|
2110 spin_unlock(&np->lock); |
|
2111 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2112 } |
|
2113 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2114 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2115 dev->name, events); |
|
2116 } |
|
2117 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2118 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2119 dev->name, events); |
|
2120 } |
|
2121 if (i > max_interrupt_work) { |
|
2122 spin_lock(&np->lock); |
|
2123 /* disable interrupts on the nic */ |
|
2124 if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
|
2125 writel(0, base + NvRegIrqMask); |
|
2126 else |
|
2127 writel(np->irqmask, base + NvRegIrqMask); |
|
2128 pci_push(base); |
|
2129 |
|
2130 if (!np->in_shutdown) { |
|
2131 np->nic_poll_irq = np->irqmask; |
|
2132 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2133 } |
|
2134 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
|
2135 spin_unlock(&np->lock); |
|
2136 break; |
|
2137 } |
|
2138 |
|
2139 } |
|
2140 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); |
|
2141 |
|
2142 return IRQ_RETVAL(i); |
|
2143 } |
|
2144 |
|
2145 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs) |
|
2146 { |
|
2147 struct net_device *dev = (struct net_device *) data; |
|
2148 struct fe_priv *np = netdev_priv(dev); |
|
2149 u8 __iomem *base = get_hwbase(dev); |
|
2150 u32 events; |
|
2151 int i; |
|
2152 |
|
2153 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); |
|
2154 |
|
2155 for (i=0; ; i++) { |
|
2156 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
|
2157 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
|
2158 pci_push(base); |
|
2159 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
|
2160 if (!(events & np->irqmask)) |
|
2161 break; |
|
2162 |
|
2163 spin_lock_irq(&np->lock); |
|
2164 nv_tx_done(dev); |
|
2165 spin_unlock_irq(&np->lock); |
|
2166 |
|
2167 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2168 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2169 dev->name, events); |
|
2170 } |
|
2171 if (i > max_interrupt_work) { |
|
2172 spin_lock_irq(&np->lock); |
|
2173 /* disable interrupts on the nic */ |
|
2174 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); |
|
2175 pci_push(base); |
|
2176 |
|
2177 if (!np->in_shutdown) { |
|
2178 np->nic_poll_irq |= NVREG_IRQ_TX_ALL; |
|
2179 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2180 } |
|
2181 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
|
2182 spin_unlock_irq(&np->lock); |
|
2183 break; |
|
2184 } |
|
2185 |
|
2186 } |
|
2187 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); |
|
2188 |
|
2189 return IRQ_RETVAL(i); |
|
2190 } |
|
2191 |
|
2192 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) |
|
2193 { |
|
2194 struct net_device *dev = (struct net_device *) data; |
|
2195 struct fe_priv *np = netdev_priv(dev); |
|
2196 u8 __iomem *base = get_hwbase(dev); |
|
2197 u32 events; |
|
2198 int i; |
|
2199 |
|
2200 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); |
|
2201 |
|
2202 for (i=0; ; i++) { |
|
2203 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
|
2204 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
|
2205 pci_push(base); |
|
2206 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
|
2207 if (!(events & np->irqmask)) |
|
2208 break; |
|
2209 |
|
2210 nv_rx_process(dev); |
|
2211 if (nv_alloc_rx(dev)) { |
|
2212 spin_lock_irq(&np->lock); |
|
2213 if (!np->in_shutdown) |
|
2214 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2215 spin_unlock_irq(&np->lock); |
|
2216 } |
|
2217 |
|
2218 if (i > max_interrupt_work) { |
|
2219 spin_lock_irq(&np->lock); |
|
2220 /* disable interrupts on the nic */ |
|
2221 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2222 pci_push(base); |
|
2223 |
|
2224 if (!np->in_shutdown) { |
|
2225 np->nic_poll_irq |= NVREG_IRQ_RX_ALL; |
|
2226 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2227 } |
|
2228 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
|
2229 spin_unlock_irq(&np->lock); |
|
2230 break; |
|
2231 } |
|
2232 |
|
2233 } |
|
2234 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); |
|
2235 |
|
2236 return IRQ_RETVAL(i); |
|
2237 } |
|
2238 |
|
2239 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) |
|
2240 { |
|
2241 struct net_device *dev = (struct net_device *) data; |
|
2242 struct fe_priv *np = netdev_priv(dev); |
|
2243 u8 __iomem *base = get_hwbase(dev); |
|
2244 u32 events; |
|
2245 int i; |
|
2246 |
|
2247 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); |
|
2248 |
|
2249 for (i=0; ; i++) { |
|
2250 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
|
2251 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
|
2252 pci_push(base); |
|
2253 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2254 if (!(events & np->irqmask)) |
|
2255 break; |
|
2256 |
|
2257 if (events & NVREG_IRQ_LINK) { |
|
2258 spin_lock_irq(&np->lock); |
|
2259 nv_link_irq(dev); |
|
2260 spin_unlock_irq(&np->lock); |
|
2261 } |
|
2262 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2263 spin_lock_irq(&np->lock); |
|
2264 nv_linkchange(dev); |
|
2265 spin_unlock_irq(&np->lock); |
|
2266 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2267 } |
|
2268 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2269 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2270 dev->name, events); |
|
2271 } |
|
2272 if (i > max_interrupt_work) { |
|
2273 spin_lock_irq(&np->lock); |
|
2274 /* disable interrupts on the nic */ |
|
2275 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); |
|
2276 pci_push(base); |
|
2277 |
|
2278 if (!np->in_shutdown) { |
|
2279 np->nic_poll_irq |= NVREG_IRQ_OTHER; |
|
2280 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2281 } |
|
2282 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
|
2283 spin_unlock_irq(&np->lock); |
|
2284 break; |
|
2285 } |
|
2286 |
|
2287 } |
|
2288 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); |
|
2289 |
|
2290 return IRQ_RETVAL(i); |
|
2291 } |
|
2292 |
|
2293 static void nv_do_nic_poll(unsigned long data) |
|
2294 { |
|
2295 struct net_device *dev = (struct net_device *) data; |
|
2296 struct fe_priv *np = netdev_priv(dev); |
|
2297 u8 __iomem *base = get_hwbase(dev); |
|
2298 u32 mask = 0; |
|
2299 |
|
2300 /* |
|
2301 * First disable irq(s) and then |
|
2302 * reenable interrupts on the nic, we have to do this before calling |
|
2303 * nv_nic_irq because that may decide to do otherwise |
|
2304 */ |
|
2305 |
|
2306 if (!using_multi_irqs(dev)) { |
|
2307 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2308 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2309 else |
|
2310 disable_irq(dev->irq); |
|
2311 mask = np->irqmask; |
|
2312 } else { |
|
2313 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2314 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2315 mask |= NVREG_IRQ_RX_ALL; |
|
2316 } |
|
2317 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2318 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2319 mask |= NVREG_IRQ_TX_ALL; |
|
2320 } |
|
2321 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2322 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2323 mask |= NVREG_IRQ_OTHER; |
|
2324 } |
|
2325 } |
|
2326 np->nic_poll_irq = 0; |
|
2327 |
|
2328 /* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
|
2329 |
|
2330 writel(mask, base + NvRegIrqMask); |
|
2331 pci_push(base); |
|
2332 |
|
2333 if (!using_multi_irqs(dev)) { |
|
2334 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2335 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2336 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2337 else |
|
2338 enable_irq(dev->irq); |
|
2339 } else { |
|
2340 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2341 nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2342 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2343 } |
|
2344 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2345 nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2346 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2347 } |
|
2348 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2349 nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2350 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2351 } |
|
2352 } |
|
2353 } |
|
2354 |
|
2355 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2356 static void nv_poll_controller(struct net_device *dev) |
|
2357 { |
|
2358 nv_do_nic_poll((unsigned long) dev); |
|
2359 } |
|
2360 #endif |
|
2361 |
|
2362 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
|
2363 { |
|
2364 struct fe_priv *np = netdev_priv(dev); |
|
2365 strcpy(info->driver, "forcedeth"); |
|
2366 strcpy(info->version, FORCEDETH_VERSION); |
|
2367 strcpy(info->bus_info, pci_name(np->pci_dev)); |
|
2368 } |
|
2369 |
|
2370 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
2371 { |
|
2372 struct fe_priv *np = netdev_priv(dev); |
|
2373 wolinfo->supported = WAKE_MAGIC; |
|
2374 |
|
2375 spin_lock_irq(&np->lock); |
|
2376 if (np->wolenabled) |
|
2377 wolinfo->wolopts = WAKE_MAGIC; |
|
2378 spin_unlock_irq(&np->lock); |
|
2379 } |
|
2380 |
|
2381 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
2382 { |
|
2383 struct fe_priv *np = netdev_priv(dev); |
|
2384 u8 __iomem *base = get_hwbase(dev); |
|
2385 |
|
2386 spin_lock_irq(&np->lock); |
|
2387 if (wolinfo->wolopts == 0) { |
|
2388 writel(0, base + NvRegWakeUpFlags); |
|
2389 np->wolenabled = 0; |
|
2390 } |
|
2391 if (wolinfo->wolopts & WAKE_MAGIC) { |
|
2392 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags); |
|
2393 np->wolenabled = 1; |
|
2394 } |
|
2395 spin_unlock_irq(&np->lock); |
|
2396 return 0; |
|
2397 } |
|
2398 |
|
2399 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
2400 { |
|
2401 struct fe_priv *np = netdev_priv(dev); |
|
2402 int adv; |
|
2403 |
|
2404 spin_lock_irq(&np->lock); |
|
2405 ecmd->port = PORT_MII; |
|
2406 if (!netif_running(dev)) { |
|
2407 /* We do not track link speed / duplex setting if the |
|
2408 * interface is disabled. Force a link check */ |
|
2409 nv_update_linkspeed(dev); |
|
2410 } |
|
2411 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
|
2412 case NVREG_LINKSPEED_10: |
|
2413 ecmd->speed = SPEED_10; |
|
2414 break; |
|
2415 case NVREG_LINKSPEED_100: |
|
2416 ecmd->speed = SPEED_100; |
|
2417 break; |
|
2418 case NVREG_LINKSPEED_1000: |
|
2419 ecmd->speed = SPEED_1000; |
|
2420 break; |
|
2421 } |
|
2422 ecmd->duplex = DUPLEX_HALF; |
|
2423 if (np->duplex) |
|
2424 ecmd->duplex = DUPLEX_FULL; |
|
2425 |
|
2426 ecmd->autoneg = np->autoneg; |
|
2427 |
|
2428 ecmd->advertising = ADVERTISED_MII; |
|
2429 if (np->autoneg) { |
|
2430 ecmd->advertising |= ADVERTISED_Autoneg; |
|
2431 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2432 } else { |
|
2433 adv = np->fixed_mode; |
|
2434 } |
|
2435 if (adv & ADVERTISE_10HALF) |
|
2436 ecmd->advertising |= ADVERTISED_10baseT_Half; |
|
2437 if (adv & ADVERTISE_10FULL) |
|
2438 ecmd->advertising |= ADVERTISED_10baseT_Full; |
|
2439 if (adv & ADVERTISE_100HALF) |
|
2440 ecmd->advertising |= ADVERTISED_100baseT_Half; |
|
2441 if (adv & ADVERTISE_100FULL) |
|
2442 ecmd->advertising |= ADVERTISED_100baseT_Full; |
|
2443 if (np->autoneg && np->gigabit == PHY_GIGABIT) { |
|
2444 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2445 if (adv & ADVERTISE_1000FULL) |
|
2446 ecmd->advertising |= ADVERTISED_1000baseT_Full; |
|
2447 } |
|
2448 |
|
2449 ecmd->supported = (SUPPORTED_Autoneg | |
|
2450 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
|
2451 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | |
|
2452 SUPPORTED_MII); |
|
2453 if (np->gigabit == PHY_GIGABIT) |
|
2454 ecmd->supported |= SUPPORTED_1000baseT_Full; |
|
2455 |
|
2456 ecmd->phy_address = np->phyaddr; |
|
2457 ecmd->transceiver = XCVR_EXTERNAL; |
|
2458 |
|
2459 /* ignore maxtxpkt, maxrxpkt for now */ |
|
2460 spin_unlock_irq(&np->lock); |
|
2461 return 0; |
|
2462 } |
|
2463 |
|
2464 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
2465 { |
|
2466 struct fe_priv *np = netdev_priv(dev); |
|
2467 |
|
2468 if (ecmd->port != PORT_MII) |
|
2469 return -EINVAL; |
|
2470 if (ecmd->transceiver != XCVR_EXTERNAL) |
|
2471 return -EINVAL; |
|
2472 if (ecmd->phy_address != np->phyaddr) { |
|
2473 /* TODO: support switching between multiple phys. Should be |
|
2474 * trivial, but not enabled due to lack of test hardware. */ |
|
2475 return -EINVAL; |
|
2476 } |
|
2477 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
2478 u32 mask; |
|
2479 |
|
2480 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
2481 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; |
|
2482 if (np->gigabit == PHY_GIGABIT) |
|
2483 mask |= ADVERTISED_1000baseT_Full; |
|
2484 |
|
2485 if ((ecmd->advertising & mask) == 0) |
|
2486 return -EINVAL; |
|
2487 |
|
2488 } else if (ecmd->autoneg == AUTONEG_DISABLE) { |
|
2489 /* Note: autonegotiation disable, speed 1000 intentionally |
|
2490 * forbidden - noone should need that. */ |
|
2491 |
|
2492 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) |
|
2493 return -EINVAL; |
|
2494 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) |
|
2495 return -EINVAL; |
|
2496 } else { |
|
2497 return -EINVAL; |
|
2498 } |
|
2499 |
|
2500 spin_lock_irq(&np->lock); |
|
2501 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
2502 int adv, bmcr; |
|
2503 |
|
2504 np->autoneg = 1; |
|
2505 |
|
2506 /* advertise only what has been requested */ |
|
2507 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2508 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
|
2509 if (ecmd->advertising & ADVERTISED_10baseT_Half) |
|
2510 adv |= ADVERTISE_10HALF; |
|
2511 if (ecmd->advertising & ADVERTISED_10baseT_Full) |
|
2512 adv |= ADVERTISE_10FULL; |
|
2513 if (ecmd->advertising & ADVERTISED_100baseT_Half) |
|
2514 adv |= ADVERTISE_100HALF; |
|
2515 if (ecmd->advertising & ADVERTISED_100baseT_Full) |
|
2516 adv |= ADVERTISE_100FULL; |
|
2517 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
2518 |
|
2519 if (np->gigabit == PHY_GIGABIT) { |
|
2520 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2521 adv &= ~ADVERTISE_1000FULL; |
|
2522 if (ecmd->advertising & ADVERTISED_1000baseT_Full) |
|
2523 adv |= ADVERTISE_1000FULL; |
|
2524 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
|
2525 } |
|
2526 |
|
2527 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2528 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
2529 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2530 |
|
2531 } else { |
|
2532 int adv, bmcr; |
|
2533 |
|
2534 np->autoneg = 0; |
|
2535 |
|
2536 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2537 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
|
2538 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
|
2539 adv |= ADVERTISE_10HALF; |
|
2540 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) |
|
2541 adv |= ADVERTISE_10FULL; |
|
2542 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
|
2543 adv |= ADVERTISE_100HALF; |
|
2544 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) |
|
2545 adv |= ADVERTISE_100FULL; |
|
2546 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
2547 np->fixed_mode = adv; |
|
2548 |
|
2549 if (np->gigabit == PHY_GIGABIT) { |
|
2550 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2551 adv &= ~ADVERTISE_1000FULL; |
|
2552 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
|
2553 } |
|
2554 |
|
2555 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2556 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX); |
|
2557 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL)) |
|
2558 bmcr |= BMCR_FULLDPLX; |
|
2559 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
|
2560 bmcr |= BMCR_SPEED100; |
|
2561 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2562 |
|
2563 if (netif_running(dev)) { |
|
2564 /* Wait a bit and then reconfigure the nic. */ |
|
2565 udelay(10); |
|
2566 nv_linkchange(dev); |
|
2567 } |
|
2568 } |
|
2569 spin_unlock_irq(&np->lock); |
|
2570 |
|
2571 return 0; |
|
2572 } |
|
2573 |
|
2574 #define FORCEDETH_REGS_VER 1 |
|
2575 |
|
2576 static int nv_get_regs_len(struct net_device *dev) |
|
2577 { |
|
2578 struct fe_priv *np = netdev_priv(dev); |
|
2579 return np->register_size; |
|
2580 } |
|
2581 |
|
2582 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
|
2583 { |
|
2584 struct fe_priv *np = netdev_priv(dev); |
|
2585 u8 __iomem *base = get_hwbase(dev); |
|
2586 u32 *rbuf = buf; |
|
2587 int i; |
|
2588 |
|
2589 regs->version = FORCEDETH_REGS_VER; |
|
2590 spin_lock_irq(&np->lock); |
|
2591 for (i = 0;i <= np->register_size/sizeof(u32); i++) |
|
2592 rbuf[i] = readl(base + i*sizeof(u32)); |
|
2593 spin_unlock_irq(&np->lock); |
|
2594 } |
|
2595 |
|
2596 static int nv_nway_reset(struct net_device *dev) |
|
2597 { |
|
2598 struct fe_priv *np = netdev_priv(dev); |
|
2599 int ret; |
|
2600 |
|
2601 spin_lock_irq(&np->lock); |
|
2602 if (np->autoneg) { |
|
2603 int bmcr; |
|
2604 |
|
2605 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2606 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
2607 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2608 |
|
2609 ret = 0; |
|
2610 } else { |
|
2611 ret = -EINVAL; |
|
2612 } |
|
2613 spin_unlock_irq(&np->lock); |
|
2614 |
|
2615 return ret; |
|
2616 } |
|
2617 |
|
2618 #ifdef NETIF_F_TSO |
|
2619 static int nv_set_tso(struct net_device *dev, u32 value) |
|
2620 { |
|
2621 struct fe_priv *np = netdev_priv(dev); |
|
2622 |
|
2623 if ((np->driver_data & DEV_HAS_CHECKSUM)) |
|
2624 return ethtool_op_set_tso(dev, value); |
|
2625 else |
|
2626 return value ? -EOPNOTSUPP : 0; |
|
2627 } |
|
2628 #endif |
|
2629 |
|
2630 static struct ethtool_ops ops = { |
|
2631 .get_drvinfo = nv_get_drvinfo, |
|
2632 .get_link = ethtool_op_get_link, |
|
2633 .get_wol = nv_get_wol, |
|
2634 .set_wol = nv_set_wol, |
|
2635 .get_settings = nv_get_settings, |
|
2636 .set_settings = nv_set_settings, |
|
2637 .get_regs_len = nv_get_regs_len, |
|
2638 .get_regs = nv_get_regs, |
|
2639 .nway_reset = nv_nway_reset, |
|
2640 .get_perm_addr = ethtool_op_get_perm_addr, |
|
2641 #ifdef NETIF_F_TSO |
|
2642 .get_tso = ethtool_op_get_tso, |
|
2643 .set_tso = nv_set_tso |
|
2644 #endif |
|
2645 }; |
|
2646 |
|
2647 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
|
2648 { |
|
2649 struct fe_priv *np = get_nvpriv(dev); |
|
2650 |
|
2651 spin_lock_irq(&np->lock); |
|
2652 |
|
2653 /* save vlan group */ |
|
2654 np->vlangrp = grp; |
|
2655 |
|
2656 if (grp) { |
|
2657 /* enable vlan on MAC */ |
|
2658 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; |
|
2659 } else { |
|
2660 /* disable vlan on MAC */ |
|
2661 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; |
|
2662 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; |
|
2663 } |
|
2664 |
|
2665 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
2666 |
|
2667 spin_unlock_irq(&np->lock); |
|
2668 }; |
|
2669 |
|
2670 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) |
|
2671 { |
|
2672 /* nothing to do */ |
|
2673 }; |
|
2674 |
|
2675 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
|
2676 { |
|
2677 u8 __iomem *base = get_hwbase(dev); |
|
2678 int i; |
|
2679 u32 msixmap = 0; |
|
2680 |
|
2681 /* Each interrupt bit can be mapped to a MSIX vector (4 bits). |
|
2682 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents |
|
2683 * the remaining 8 interrupts. |
|
2684 */ |
|
2685 for (i = 0; i < 8; i++) { |
|
2686 if ((irqmask >> i) & 0x1) { |
|
2687 msixmap |= vector << (i << 2); |
|
2688 } |
|
2689 } |
|
2690 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); |
|
2691 |
|
2692 msixmap = 0; |
|
2693 for (i = 0; i < 8; i++) { |
|
2694 if ((irqmask >> (i + 8)) & 0x1) { |
|
2695 msixmap |= vector << (i << 2); |
|
2696 } |
|
2697 } |
|
2698 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
|
2699 } |
|
2700 |
|
2701 static int nv_request_irq(struct net_device *dev) |
|
2702 { |
|
2703 struct fe_priv *np = get_nvpriv(dev); |
|
2704 u8 __iomem *base = get_hwbase(dev); |
|
2705 int ret = 1; |
|
2706 int i; |
|
2707 |
|
2708 if (np->msi_flags & NV_MSI_X_CAPABLE) { |
|
2709 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2710 np->msi_x_entry[i].entry = i; |
|
2711 } |
|
2712 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { |
|
2713 np->msi_flags |= NV_MSI_X_ENABLED; |
|
2714 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
|
2715 /* Request irq for rx handling */ |
|
2716 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) { |
|
2717 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
|
2718 pci_disable_msix(np->pci_dev); |
|
2719 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2720 goto out_err; |
|
2721 } |
|
2722 /* Request irq for tx handling */ |
|
2723 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) { |
|
2724 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
|
2725 pci_disable_msix(np->pci_dev); |
|
2726 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2727 goto out_free_rx; |
|
2728 } |
|
2729 /* Request irq for link and timer handling */ |
|
2730 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) { |
|
2731 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
|
2732 pci_disable_msix(np->pci_dev); |
|
2733 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2734 goto out_free_tx; |
|
2735 } |
|
2736 /* map interrupts to their respective vector */ |
|
2737 writel(0, base + NvRegMSIXMap0); |
|
2738 writel(0, base + NvRegMSIXMap1); |
|
2739 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
|
2740 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
|
2741 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
|
2742 } else { |
|
2743 /* Request irq for all interrupts */ |
|
2744 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { |
|
2745 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2746 pci_disable_msix(np->pci_dev); |
|
2747 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2748 goto out_err; |
|
2749 } |
|
2750 |
|
2751 /* map interrupts to vector 0 */ |
|
2752 writel(0, base + NvRegMSIXMap0); |
|
2753 writel(0, base + NvRegMSIXMap1); |
|
2754 } |
|
2755 } |
|
2756 } |
|
2757 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
|
2758 if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
|
2759 np->msi_flags |= NV_MSI_ENABLED; |
|
2760 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { |
|
2761 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2762 pci_disable_msi(np->pci_dev); |
|
2763 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2764 goto out_err; |
|
2765 } |
|
2766 |
|
2767 /* map interrupts to vector 0 */ |
|
2768 writel(0, base + NvRegMSIMap0); |
|
2769 writel(0, base + NvRegMSIMap1); |
|
2770 /* enable msi vector 0 */ |
|
2771 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
|
2772 } |
|
2773 } |
|
2774 if (ret != 0) { |
|
2775 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) |
|
2776 goto out_err; |
|
2777 } |
|
2778 |
|
2779 return 0; |
|
2780 out_free_tx: |
|
2781 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
|
2782 out_free_rx: |
|
2783 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
|
2784 out_err: |
|
2785 return 1; |
|
2786 } |
|
2787 |
|
2788 static void nv_free_irq(struct net_device *dev) |
|
2789 { |
|
2790 struct fe_priv *np = get_nvpriv(dev); |
|
2791 int i; |
|
2792 |
|
2793 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
2794 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2795 free_irq(np->msi_x_entry[i].vector, dev); |
|
2796 } |
|
2797 pci_disable_msix(np->pci_dev); |
|
2798 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2799 } else { |
|
2800 free_irq(np->pci_dev->irq, dev); |
|
2801 if (np->msi_flags & NV_MSI_ENABLED) { |
|
2802 pci_disable_msi(np->pci_dev); |
|
2803 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2804 } |
|
2805 } |
|
2806 } |
|
2807 |
|
2808 static int nv_open(struct net_device *dev) |
|
2809 { |
|
2810 struct fe_priv *np = netdev_priv(dev); |
|
2811 u8 __iomem *base = get_hwbase(dev); |
|
2812 int ret = 1; |
|
2813 int oom, i; |
|
2814 |
|
2815 dprintk(KERN_DEBUG "nv_open: begin\n"); |
|
2816 |
|
2817 /* 1) erase previous misconfiguration */ |
|
2818 if (np->driver_data & DEV_HAS_POWER_CNTRL) |
|
2819 nv_mac_reset(dev); |
|
2820 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ |
|
2821 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
2822 writel(0, base + NvRegMulticastAddrB); |
|
2823 writel(0, base + NvRegMulticastMaskA); |
|
2824 writel(0, base + NvRegMulticastMaskB); |
|
2825 writel(0, base + NvRegPacketFilterFlags); |
|
2826 |
|
2827 writel(0, base + NvRegTransmitterControl); |
|
2828 writel(0, base + NvRegReceiverControl); |
|
2829 |
|
2830 writel(0, base + NvRegAdapterControl); |
|
2831 |
|
2832 /* 2) initialize descriptor rings */ |
|
2833 set_bufsize(dev); |
|
2834 oom = nv_init_ring(dev); |
|
2835 |
|
2836 writel(0, base + NvRegLinkSpeed); |
|
2837 writel(0, base + NvRegUnknownTransmitterReg); |
|
2838 nv_txrx_reset(dev); |
|
2839 writel(0, base + NvRegUnknownSetupReg6); |
|
2840 |
|
2841 np->in_shutdown = 0; |
|
2842 |
|
2843 /* 3) set mac address */ |
|
2844 nv_copy_mac_to_hw(dev); |
|
2845 |
|
2846 /* 4) give hw rings */ |
|
2847 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
2848 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
|
2849 base + NvRegRingSizes); |
|
2850 |
|
2851 /* 5) continue setup */ |
|
2852 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
2853 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); |
|
2854 writel(np->txrxctl_bits, base + NvRegTxRxControl); |
|
2855 writel(np->vlanctl_bits, base + NvRegVlanControl); |
|
2856 pci_push(base); |
|
2857 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
|
2858 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
|
2859 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
|
2860 KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
|
2861 |
|
2862 writel(0, base + NvRegUnknownSetupReg4); |
|
2863 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2864 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
2865 |
|
2866 /* 6) continue setup */ |
|
2867 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
|
2868 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
|
2869 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
|
2870 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
2871 |
|
2872 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); |
|
2873 get_random_bytes(&i, sizeof(i)); |
|
2874 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); |
|
2875 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); |
|
2876 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); |
|
2877 if (poll_interval == -1) { |
|
2878 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) |
|
2879 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); |
|
2880 else |
|
2881 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); |
|
2882 } |
|
2883 else |
|
2884 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
|
2885 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
|
2886 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
|
2887 base + NvRegAdapterControl); |
|
2888 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
|
2889 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); |
|
2890 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); |
|
2891 |
|
2892 i = readl(base + NvRegPowerState); |
|
2893 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) |
|
2894 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
|
2895 |
|
2896 pci_push(base); |
|
2897 udelay(10); |
|
2898 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); |
|
2899 |
|
2900 nv_disable_hw_interrupts(dev, np->irqmask); |
|
2901 pci_push(base); |
|
2902 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
2903 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2904 pci_push(base); |
|
2905 |
|
2906 if (nv_request_irq(dev)) { |
|
2907 goto out_drain; |
|
2908 } |
|
2909 |
|
2910 /* ask for interrupts */ |
|
2911 nv_enable_hw_interrupts(dev, np->irqmask); |
|
2912 |
|
2913 spin_lock_irq(&np->lock); |
|
2914 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
2915 writel(0, base + NvRegMulticastAddrB); |
|
2916 writel(0, base + NvRegMulticastMaskA); |
|
2917 writel(0, base + NvRegMulticastMaskB); |
|
2918 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
|
2919 /* One manual link speed update: Interrupts are enabled, future link |
|
2920 * speed changes cause interrupts and are handled by nv_link_irq(). |
|
2921 */ |
|
2922 { |
|
2923 u32 miistat; |
|
2924 miistat = readl(base + NvRegMIIStatus); |
|
2925 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
2926 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
|
2927 } |
|
2928 /* set linkspeed to invalid value, thus force nv_update_linkspeed |
|
2929 * to init hw */ |
|
2930 np->linkspeed = 0; |
|
2931 ret = nv_update_linkspeed(dev); |
|
2932 nv_start_rx(dev); |
|
2933 nv_start_tx(dev); |
|
2934 netif_start_queue(dev); |
|
2935 if (ret) { |
|
2936 netif_carrier_on(dev); |
|
2937 } else { |
|
2938 printk("%s: no link during initialization.\n", dev->name); |
|
2939 netif_carrier_off(dev); |
|
2940 } |
|
2941 if (oom) |
|
2942 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2943 spin_unlock_irq(&np->lock); |
|
2944 |
|
2945 return 0; |
|
2946 out_drain: |
|
2947 drain_ring(dev); |
|
2948 return ret; |
|
2949 } |
|
2950 |
|
2951 static int nv_close(struct net_device *dev) |
|
2952 { |
|
2953 struct fe_priv *np = netdev_priv(dev); |
|
2954 u8 __iomem *base; |
|
2955 |
|
2956 spin_lock_irq(&np->lock); |
|
2957 np->in_shutdown = 1; |
|
2958 spin_unlock_irq(&np->lock); |
|
2959 synchronize_irq(dev->irq); |
|
2960 |
|
2961 del_timer_sync(&np->oom_kick); |
|
2962 del_timer_sync(&np->nic_poll); |
|
2963 |
|
2964 netif_stop_queue(dev); |
|
2965 spin_lock_irq(&np->lock); |
|
2966 nv_stop_tx(dev); |
|
2967 nv_stop_rx(dev); |
|
2968 nv_txrx_reset(dev); |
|
2969 |
|
2970 /* disable interrupts on the nic or we will lock up */ |
|
2971 base = get_hwbase(dev); |
|
2972 nv_disable_hw_interrupts(dev, np->irqmask); |
|
2973 pci_push(base); |
|
2974 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); |
|
2975 |
|
2976 spin_unlock_irq(&np->lock); |
|
2977 |
|
2978 nv_free_irq(dev); |
|
2979 |
|
2980 drain_ring(dev); |
|
2981 |
|
2982 if (np->wolenabled) |
|
2983 nv_start_rx(dev); |
|
2984 |
|
2985 /* special op: write back the misordered MAC address - otherwise |
|
2986 * the next nv_probe would see a wrong address. |
|
2987 */ |
|
2988 writel(np->orig_mac[0], base + NvRegMacAddrA); |
|
2989 writel(np->orig_mac[1], base + NvRegMacAddrB); |
|
2990 |
|
2991 /* FIXME: power down nic */ |
|
2992 |
|
2993 return 0; |
|
2994 } |
|
2995 |
|
2996 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
|
2997 { |
|
2998 struct net_device *dev; |
|
2999 struct fe_priv *np; |
|
3000 unsigned long addr; |
|
3001 u8 __iomem *base; |
|
3002 int err, i; |
|
3003 u32 powerstate; |
|
3004 |
|
3005 dev = alloc_etherdev(sizeof(struct fe_priv)); |
|
3006 err = -ENOMEM; |
|
3007 if (!dev) |
|
3008 goto out; |
|
3009 |
|
3010 np = netdev_priv(dev); |
|
3011 np->pci_dev = pci_dev; |
|
3012 spin_lock_init(&np->lock); |
|
3013 SET_MODULE_OWNER(dev); |
|
3014 SET_NETDEV_DEV(dev, &pci_dev->dev); |
|
3015 |
|
3016 init_timer(&np->oom_kick); |
|
3017 np->oom_kick.data = (unsigned long) dev; |
|
3018 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ |
|
3019 init_timer(&np->nic_poll); |
|
3020 np->nic_poll.data = (unsigned long) dev; |
|
3021 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ |
|
3022 |
|
3023 err = pci_enable_device(pci_dev); |
|
3024 if (err) { |
|
3025 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", |
|
3026 err, pci_name(pci_dev)); |
|
3027 goto out_free; |
|
3028 } |
|
3029 |
|
3030 pci_set_master(pci_dev); |
|
3031 |
|
3032 err = pci_request_regions(pci_dev, DRV_NAME); |
|
3033 if (err < 0) |
|
3034 goto out_disable; |
|
3035 |
|
3036 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL)) |
|
3037 np->register_size = NV_PCI_REGSZ_VER2; |
|
3038 else |
|
3039 np->register_size = NV_PCI_REGSZ_VER1; |
|
3040 |
|
3041 err = -EINVAL; |
|
3042 addr = 0; |
|
3043 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
|
3044 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", |
|
3045 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), |
|
3046 pci_resource_len(pci_dev, i), |
|
3047 pci_resource_flags(pci_dev, i)); |
|
3048 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
|
3049 pci_resource_len(pci_dev, i) >= np->register_size) { |
|
3050 addr = pci_resource_start(pci_dev, i); |
|
3051 break; |
|
3052 } |
|
3053 } |
|
3054 if (i == DEVICE_COUNT_RESOURCE) { |
|
3055 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", |
|
3056 pci_name(pci_dev)); |
|
3057 goto out_relreg; |
|
3058 } |
|
3059 |
|
3060 /* copy of driver data */ |
|
3061 np->driver_data = id->driver_data; |
|
3062 |
|
3063 /* handle different descriptor versions */ |
|
3064 if (id->driver_data & DEV_HAS_HIGH_DMA) { |
|
3065 /* packet format 3: supports 40-bit addressing */ |
|
3066 np->desc_ver = DESC_VER_3; |
|
3067 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
|
3068 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
|
3069 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", |
|
3070 pci_name(pci_dev)); |
|
3071 } else { |
|
3072 dev->features |= NETIF_F_HIGHDMA; |
|
3073 printk(KERN_INFO "forcedeth: using HIGHDMA\n"); |
|
3074 } |
|
3075 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) { |
|
3076 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n", |
|
3077 pci_name(pci_dev)); |
|
3078 } |
|
3079 } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
|
3080 /* packet format 2: supports jumbo frames */ |
|
3081 np->desc_ver = DESC_VER_2; |
|
3082 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
|
3083 } else { |
|
3084 /* original packet format */ |
|
3085 np->desc_ver = DESC_VER_1; |
|
3086 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
|
3087 } |
|
3088 |
|
3089 np->pkt_limit = NV_PKTLIMIT_1; |
|
3090 if (id->driver_data & DEV_HAS_LARGEDESC) |
|
3091 np->pkt_limit = NV_PKTLIMIT_2; |
|
3092 |
|
3093 if (id->driver_data & DEV_HAS_CHECKSUM) { |
|
3094 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
|
3095 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
|
3096 #ifdef NETIF_F_TSO |
|
3097 dev->features |= NETIF_F_TSO; |
|
3098 #endif |
|
3099 } |
|
3100 |
|
3101 np->vlanctl_bits = 0; |
|
3102 if (id->driver_data & DEV_HAS_VLAN) { |
|
3103 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; |
|
3104 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; |
|
3105 dev->vlan_rx_register = nv_vlan_rx_register; |
|
3106 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; |
|
3107 } |
|
3108 |
|
3109 np->msi_flags = 0; |
|
3110 if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) { |
|
3111 np->msi_flags |= NV_MSI_CAPABLE; |
|
3112 } |
|
3113 if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) { |
|
3114 np->msi_flags |= NV_MSI_X_CAPABLE; |
|
3115 } |
|
3116 |
|
3117 err = -ENOMEM; |
|
3118 np->base = ioremap(addr, np->register_size); |
|
3119 if (!np->base) |
|
3120 goto out_relreg; |
|
3121 dev->base_addr = (unsigned long)np->base; |
|
3122 |
|
3123 dev->irq = pci_dev->irq; |
|
3124 |
|
3125 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3126 np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
|
3127 sizeof(struct ring_desc) * (RX_RING + TX_RING), |
|
3128 &np->ring_addr); |
|
3129 if (!np->rx_ring.orig) |
|
3130 goto out_unmap; |
|
3131 np->tx_ring.orig = &np->rx_ring.orig[RX_RING]; |
|
3132 } else { |
|
3133 np->rx_ring.ex = pci_alloc_consistent(pci_dev, |
|
3134 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), |
|
3135 &np->ring_addr); |
|
3136 if (!np->rx_ring.ex) |
|
3137 goto out_unmap; |
|
3138 np->tx_ring.ex = &np->rx_ring.ex[RX_RING]; |
|
3139 } |
|
3140 |
|
3141 dev->open = nv_open; |
|
3142 dev->stop = nv_close; |
|
3143 dev->hard_start_xmit = nv_start_xmit; |
|
3144 dev->get_stats = nv_get_stats; |
|
3145 dev->change_mtu = nv_change_mtu; |
|
3146 dev->set_mac_address = nv_set_mac_address; |
|
3147 dev->set_multicast_list = nv_set_multicast; |
|
3148 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
3149 dev->poll_controller = nv_poll_controller; |
|
3150 #endif |
|
3151 SET_ETHTOOL_OPS(dev, &ops); |
|
3152 dev->tx_timeout = nv_tx_timeout; |
|
3153 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
|
3154 |
|
3155 pci_set_drvdata(pci_dev, dev); |
|
3156 |
|
3157 /* read the mac address */ |
|
3158 base = get_hwbase(dev); |
|
3159 np->orig_mac[0] = readl(base + NvRegMacAddrA); |
|
3160 np->orig_mac[1] = readl(base + NvRegMacAddrB); |
|
3161 |
|
3162 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
|
3163 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
|
3164 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
|
3165 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
|
3166 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
|
3167 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
|
3168 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
3169 |
|
3170 if (!is_valid_ether_addr(dev->perm_addr)) { |
|
3171 /* |
|
3172 * Bad mac address. At least one bios sets the mac address |
|
3173 * to 01:23:45:67:89:ab |
|
3174 */ |
|
3175 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", |
|
3176 pci_name(pci_dev), |
|
3177 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
3178 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
3179 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); |
|
3180 dev->dev_addr[0] = 0x00; |
|
3181 dev->dev_addr[1] = 0x00; |
|
3182 dev->dev_addr[2] = 0x6c; |
|
3183 get_random_bytes(&dev->dev_addr[3], 3); |
|
3184 } |
|
3185 |
|
3186 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
|
3187 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
3188 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
3189 |
|
3190 /* disable WOL */ |
|
3191 writel(0, base + NvRegWakeUpFlags); |
|
3192 np->wolenabled = 0; |
|
3193 |
|
3194 if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
|
3195 u8 revision_id; |
|
3196 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id); |
|
3197 |
|
3198 /* take phy and nic out of low power mode */ |
|
3199 powerstate = readl(base + NvRegPowerState2); |
|
3200 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; |
|
3201 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || |
|
3202 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && |
|
3203 revision_id >= 0xA3) |
|
3204 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
|
3205 writel(powerstate, base + NvRegPowerState2); |
|
3206 } |
|
3207 |
|
3208 if (np->desc_ver == DESC_VER_1) { |
|
3209 np->tx_flags = NV_TX_VALID; |
|
3210 } else { |
|
3211 np->tx_flags = NV_TX2_VALID; |
|
3212 } |
|
3213 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
|
3214 np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
|
3215 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
3216 np->msi_flags |= 0x0003; |
|
3217 } else { |
|
3218 np->irqmask = NVREG_IRQMASK_CPU; |
|
3219 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
3220 np->msi_flags |= 0x0001; |
|
3221 } |
|
3222 |
|
3223 if (id->driver_data & DEV_NEED_TIMERIRQ) |
|
3224 np->irqmask |= NVREG_IRQ_TIMER; |
|
3225 if (id->driver_data & DEV_NEED_LINKTIMER) { |
|
3226 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); |
|
3227 np->need_linktimer = 1; |
|
3228 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
3229 } else { |
|
3230 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); |
|
3231 np->need_linktimer = 0; |
|
3232 } |
|
3233 |
|
3234 /* find a suitable phy */ |
|
3235 for (i = 1; i <= 32; i++) { |
|
3236 int id1, id2; |
|
3237 int phyaddr = i & 0x1F; |
|
3238 |
|
3239 spin_lock_irq(&np->lock); |
|
3240 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
|
3241 spin_unlock_irq(&np->lock); |
|
3242 if (id1 < 0 || id1 == 0xffff) |
|
3243 continue; |
|
3244 spin_lock_irq(&np->lock); |
|
3245 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
|
3246 spin_unlock_irq(&np->lock); |
|
3247 if (id2 < 0 || id2 == 0xffff) |
|
3248 continue; |
|
3249 |
|
3250 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
|
3251 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
|
3252 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
|
3253 pci_name(pci_dev), id1, id2, phyaddr); |
|
3254 np->phyaddr = phyaddr; |
|
3255 np->phy_oui = id1 | id2; |
|
3256 break; |
|
3257 } |
|
3258 if (i == 33) { |
|
3259 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
|
3260 pci_name(pci_dev)); |
|
3261 goto out_freering; |
|
3262 } |
|
3263 |
|
3264 /* reset it */ |
|
3265 phy_init(dev); |
|
3266 |
|
3267 /* set default link speed settings */ |
|
3268 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
3269 np->duplex = 0; |
|
3270 np->autoneg = 1; |
|
3271 |
|
3272 err = register_netdev(dev); |
|
3273 if (err) { |
|
3274 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); |
|
3275 goto out_freering; |
|
3276 } |
|
3277 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", |
|
3278 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, |
|
3279 pci_name(pci_dev)); |
|
3280 |
|
3281 return 0; |
|
3282 |
|
3283 out_freering: |
|
3284 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
3285 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), |
|
3286 np->rx_ring.orig, np->ring_addr); |
|
3287 else |
|
3288 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), |
|
3289 np->rx_ring.ex, np->ring_addr); |
|
3290 pci_set_drvdata(pci_dev, NULL); |
|
3291 out_unmap: |
|
3292 iounmap(get_hwbase(dev)); |
|
3293 out_relreg: |
|
3294 pci_release_regions(pci_dev); |
|
3295 out_disable: |
|
3296 pci_disable_device(pci_dev); |
|
3297 out_free: |
|
3298 free_netdev(dev); |
|
3299 out: |
|
3300 return err; |
|
3301 } |
|
3302 |
|
3303 static void __devexit nv_remove(struct pci_dev *pci_dev) |
|
3304 { |
|
3305 struct net_device *dev = pci_get_drvdata(pci_dev); |
|
3306 struct fe_priv *np = netdev_priv(dev); |
|
3307 |
|
3308 unregister_netdev(dev); |
|
3309 |
|
3310 /* free all structures */ |
|
3311 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
3312 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr); |
|
3313 else |
|
3314 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr); |
|
3315 iounmap(get_hwbase(dev)); |
|
3316 pci_release_regions(pci_dev); |
|
3317 pci_disable_device(pci_dev); |
|
3318 free_netdev(dev); |
|
3319 pci_set_drvdata(pci_dev, NULL); |
|
3320 } |
|
3321 |
|
3322 static struct pci_device_id pci_tbl[] = { |
|
3323 { /* nForce Ethernet Controller */ |
|
3324 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
|
3325 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3326 }, |
|
3327 { /* nForce2 Ethernet Controller */ |
|
3328 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
|
3329 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3330 }, |
|
3331 { /* nForce3 Ethernet Controller */ |
|
3332 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
|
3333 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3334 }, |
|
3335 { /* nForce3 Ethernet Controller */ |
|
3336 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
|
3337 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3338 }, |
|
3339 { /* nForce3 Ethernet Controller */ |
|
3340 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
|
3341 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3342 }, |
|
3343 { /* nForce3 Ethernet Controller */ |
|
3344 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
|
3345 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3346 }, |
|
3347 { /* nForce3 Ethernet Controller */ |
|
3348 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
|
3349 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3350 }, |
|
3351 { /* CK804 Ethernet Controller */ |
|
3352 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
|
3353 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3354 }, |
|
3355 { /* CK804 Ethernet Controller */ |
|
3356 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
|
3357 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3358 }, |
|
3359 { /* MCP04 Ethernet Controller */ |
|
3360 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
|
3361 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3362 }, |
|
3363 { /* MCP04 Ethernet Controller */ |
|
3364 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
|
3365 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3366 }, |
|
3367 { /* MCP51 Ethernet Controller */ |
|
3368 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
|
3369 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
3370 }, |
|
3371 { /* MCP51 Ethernet Controller */ |
|
3372 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
|
3373 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
3374 }, |
|
3375 { /* MCP55 Ethernet Controller */ |
|
3376 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
|
3377 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
|
3378 }, |
|
3379 { /* MCP55 Ethernet Controller */ |
|
3380 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
|
3381 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
|
3382 }, |
|
3383 {0,}, |
|
3384 }; |
|
3385 |
|
3386 static struct pci_driver driver = { |
|
3387 .name = "forcedeth", |
|
3388 .id_table = pci_tbl, |
|
3389 .probe = nv_probe, |
|
3390 .remove = __devexit_p(nv_remove), |
|
3391 }; |
|
3392 |
|
3393 |
|
3394 static int __init init_nic(void) |
|
3395 { |
|
3396 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); |
|
3397 return pci_module_init(&driver); |
|
3398 } |
|
3399 |
|
3400 static void __exit exit_nic(void) |
|
3401 { |
|
3402 pci_unregister_driver(&driver); |
|
3403 } |
|
3404 |
|
3405 module_param(max_interrupt_work, int, 0); |
|
3406 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
|
3407 module_param(optimization_mode, int, 0); |
|
3408 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); |
|
3409 module_param(poll_interval, int, 0); |
|
3410 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); |
|
3411 module_param(disable_msi, int, 0); |
|
3412 MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1."); |
|
3413 module_param(disable_msix, int, 0); |
|
3414 MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1."); |
|
3415 |
|
3416 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
|
3417 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); |
|
3418 MODULE_LICENSE("GPL"); |
|
3419 |
|
3420 MODULE_DEVICE_TABLE(pci, pci_tbl); |
|
3421 |
|
3422 module_init(init_nic); |
|
3423 module_exit(exit_nic); |
|