1 /* |
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2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. |
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3 * |
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4 * Note: This driver is a cleanroom reimplementation based on reverse |
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5 * engineered documentation written by Carl-Daniel Hailfinger |
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6 * and Andrew de Quincey. It's neither supported nor endorsed |
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7 * by NVIDIA Corp. Use at your own risk. |
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8 * |
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9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered |
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10 * trademarks of NVIDIA Corporation in the United States and other |
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11 * countries. |
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12 * |
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13 * Copyright (C) 2003,4,5 Manfred Spraul |
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14 * Copyright (C) 2004 Andrew de Quincey (wol support) |
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15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane |
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16 * IRQ rate fixes, bigendian fixes, cleanups, verification) |
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17 * Copyright (c) 2004 NVIDIA Corporation |
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18 * |
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19 * This program is free software; you can redistribute it and/or modify |
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20 * it under the terms of the GNU General Public License as published by |
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21 * the Free Software Foundation; either version 2 of the License, or |
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22 * (at your option) any later version. |
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23 * |
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24 * This program is distributed in the hope that it will be useful, |
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25 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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27 * GNU General Public License for more details. |
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28 * |
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29 * You should have received a copy of the GNU General Public License |
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30 * along with this program; if not, write to the Free Software |
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31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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32 * |
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33 * Changelog: |
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34 * 0.01: 05 Oct 2003: First release that compiles without warnings. |
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35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs. |
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36 * Check all PCI BARs for the register window. |
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37 * udelay added to mii_rw. |
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38 * 0.03: 06 Oct 2003: Initialize dev->irq. |
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39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks. |
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40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout. |
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41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated, |
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42 * irq mask updated |
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43 * 0.07: 14 Oct 2003: Further irq mask updates. |
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44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill |
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45 * added into irq handler, NULL check for drain_ring. |
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46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the |
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47 * requested interrupt sources. |
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48 * 0.10: 20 Oct 2003: First cleanup for release. |
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49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased. |
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50 * MAC Address init fix, set_multicast cleanup. |
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51 * 0.12: 23 Oct 2003: Cleanups for release. |
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52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10. |
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53 * Set link speed correctly. start rx before starting |
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54 * tx (nv_start_rx sets the link speed). |
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55 * 0.14: 25 Oct 2003: Nic dependant irq mask. |
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56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during |
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57 * open. |
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58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size |
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59 * increased to 1628 bytes. |
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60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from |
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61 * the tx length. |
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62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats |
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63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac |
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64 * addresses, really stop rx if already running |
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65 * in nv_start_rx, clean up a bit. |
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66 * 0.20: 07 Dec 2003: alloc fixes |
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67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix. |
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68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup |
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69 * on close. |
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70 * 0.23: 26 Jan 2004: various small cleanups |
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71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces |
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72 * 0.25: 09 Mar 2004: wol support |
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73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes |
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74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings, |
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75 * added CK804/MCP04 device IDs, code fixes |
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76 * for registers, link status and other minor fixes. |
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77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe |
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78 * 0.29: 31 Aug 2004: Add backup timer for link change notification. |
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79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset |
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80 * into nv_close, otherwise reenabling for wol can |
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81 * cause DMA to kfree'd memory. |
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82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link |
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83 * capabilities. |
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84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added. |
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85 * 0.33: 16 May 2005: Support for MCP51 added. |
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86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics. |
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87 * 0.35: 26 Jun 2005: Support for MCP55 added. |
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88 * 0.36: 28 Jun 2005: Add jumbo frame support. |
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89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list |
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90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of |
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91 * per-packet flags. |
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92 * 0.39: 18 Jul 2005: Add 64bit descriptor support. |
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93 * 0.40: 19 Jul 2005: Add support for mac address change. |
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94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead |
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95 * of nv_remove |
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96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization |
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97 * in the second (and later) nv_open call |
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98 * 0.43: 10 Aug 2005: Add support for tx checksum. |
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99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation. |
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100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check |
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101 * 0.46: 20 Oct 2005: Add irq optimization modes. |
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102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. |
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103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single |
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104 * 0.49: 10 Dec 2005: Fix tso for large buffers. |
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105 * 0.50: 20 Jan 2006: Add 8021pq tagging support. |
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106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings. |
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107 * 0.52: 20 Jan 2006: Add MSI/MSIX support. |
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108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
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109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
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110 * |
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111 * Known bugs: |
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112 * We suspect that on some hardware no TX done interrupts are generated. |
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113 * This means recovery from netif_stop_queue only happens if the hw timer |
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114 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) |
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115 * and the timer is active in the IRQMask, or if a rx packet arrives by chance. |
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116 * If your hardware reliably generates tx done interrupts, then you can remove |
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117 * DEV_NEED_TIMERIRQ from the driver_data flags. |
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118 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
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119 * superfluous timer interrupts from the nic. |
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120 */ |
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121 #define FORCEDETH_VERSION "0.54" |
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122 #define DRV_NAME "forcedeth" |
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123 |
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124 #include <linux/module.h> |
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125 #include <linux/types.h> |
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126 #include <linux/pci.h> |
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127 #include <linux/interrupt.h> |
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128 #include <linux/netdevice.h> |
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129 #include <linux/etherdevice.h> |
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130 #include <linux/delay.h> |
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131 #include <linux/spinlock.h> |
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132 #include <linux/ethtool.h> |
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133 #include <linux/timer.h> |
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134 #include <linux/skbuff.h> |
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135 #include <linux/mii.h> |
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136 #include <linux/random.h> |
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137 #include <linux/init.h> |
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138 #include <linux/if_vlan.h> |
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139 #include <linux/dma-mapping.h> |
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140 |
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141 #include <asm/irq.h> |
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142 #include <asm/io.h> |
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143 #include <asm/uaccess.h> |
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144 #include <asm/system.h> |
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145 |
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146 #include "../globals.h" |
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147 #include "ecdev.h" |
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148 |
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149 #if 0 |
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150 #define dprintk printk |
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151 #else |
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152 #define dprintk(x...) do { } while (0) |
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153 #endif |
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154 |
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155 |
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156 /* |
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157 * Hardware access: |
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158 */ |
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159 |
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160 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */ |
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161 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */ |
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162 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */ |
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163 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */ |
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164 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */ |
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165 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */ |
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166 #define DEV_HAS_MSI 0x0040 /* device supports MSI */ |
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167 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */ |
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168 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */ |
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169 |
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170 enum { |
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171 NvRegIrqStatus = 0x000, |
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172 #define NVREG_IRQSTAT_MIIEVENT 0x040 |
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173 #define NVREG_IRQSTAT_MASK 0x1ff |
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174 NvRegIrqMask = 0x004, |
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175 #define NVREG_IRQ_RX_ERROR 0x0001 |
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176 #define NVREG_IRQ_RX 0x0002 |
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177 #define NVREG_IRQ_RX_NOBUF 0x0004 |
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178 #define NVREG_IRQ_TX_ERR 0x0008 |
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179 #define NVREG_IRQ_TX_OK 0x0010 |
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180 #define NVREG_IRQ_TIMER 0x0020 |
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181 #define NVREG_IRQ_LINK 0x0040 |
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182 #define NVREG_IRQ_RX_FORCED 0x0080 |
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183 #define NVREG_IRQ_TX_FORCED 0x0100 |
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184 #define NVREG_IRQMASK_THROUGHPUT 0x00df |
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185 #define NVREG_IRQMASK_CPU 0x0040 |
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186 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
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187 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) |
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188 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) |
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189 |
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190 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ |
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191 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
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192 NVREG_IRQ_TX_FORCED)) |
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193 |
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194 NvRegUnknownSetupReg6 = 0x008, |
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195 #define NVREG_UNKSETUP6_VAL 3 |
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196 |
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197 /* |
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198 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic |
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199 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms |
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200 */ |
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201 NvRegPollingInterval = 0x00c, |
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202 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 |
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203 #define NVREG_POLL_DEFAULT_CPU 13 |
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204 NvRegMSIMap0 = 0x020, |
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205 NvRegMSIMap1 = 0x024, |
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206 NvRegMSIIrqMask = 0x030, |
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207 #define NVREG_MSI_VECTOR_0_ENABLED 0x01 |
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208 NvRegMisc1 = 0x080, |
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209 #define NVREG_MISC1_HD 0x02 |
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210 #define NVREG_MISC1_FORCE 0x3b0f3c |
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211 |
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212 NvRegMacReset = 0x3c, |
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213 #define NVREG_MAC_RESET_ASSERT 0x0F3 |
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214 NvRegTransmitterControl = 0x084, |
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215 #define NVREG_XMITCTL_START 0x01 |
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216 NvRegTransmitterStatus = 0x088, |
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217 #define NVREG_XMITSTAT_BUSY 0x01 |
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218 |
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219 NvRegPacketFilterFlags = 0x8c, |
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220 #define NVREG_PFF_ALWAYS 0x7F0008 |
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221 #define NVREG_PFF_PROMISC 0x80 |
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222 #define NVREG_PFF_MYADDR 0x20 |
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223 |
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224 NvRegOffloadConfig = 0x90, |
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225 #define NVREG_OFFLOAD_HOMEPHY 0x601 |
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226 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
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227 NvRegReceiverControl = 0x094, |
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228 #define NVREG_RCVCTL_START 0x01 |
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229 NvRegReceiverStatus = 0x98, |
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230 #define NVREG_RCVSTAT_BUSY 0x01 |
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231 |
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232 NvRegRandomSeed = 0x9c, |
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233 #define NVREG_RNDSEED_MASK 0x00ff |
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234 #define NVREG_RNDSEED_FORCE 0x7f00 |
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235 #define NVREG_RNDSEED_FORCE2 0x2d00 |
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236 #define NVREG_RNDSEED_FORCE3 0x7400 |
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237 |
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238 NvRegUnknownSetupReg1 = 0xA0, |
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239 #define NVREG_UNKSETUP1_VAL 0x16070f |
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240 NvRegUnknownSetupReg2 = 0xA4, |
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241 #define NVREG_UNKSETUP2_VAL 0x16 |
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242 NvRegMacAddrA = 0xA8, |
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243 NvRegMacAddrB = 0xAC, |
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244 NvRegMulticastAddrA = 0xB0, |
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245 #define NVREG_MCASTADDRA_FORCE 0x01 |
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246 NvRegMulticastAddrB = 0xB4, |
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247 NvRegMulticastMaskA = 0xB8, |
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248 NvRegMulticastMaskB = 0xBC, |
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249 |
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250 NvRegPhyInterface = 0xC0, |
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251 #define PHY_RGMII 0x10000000 |
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252 |
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253 NvRegTxRingPhysAddr = 0x100, |
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254 NvRegRxRingPhysAddr = 0x104, |
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255 NvRegRingSizes = 0x108, |
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256 #define NVREG_RINGSZ_TXSHIFT 0 |
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257 #define NVREG_RINGSZ_RXSHIFT 16 |
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258 NvRegUnknownTransmitterReg = 0x10c, |
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259 NvRegLinkSpeed = 0x110, |
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260 #define NVREG_LINKSPEED_FORCE 0x10000 |
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261 #define NVREG_LINKSPEED_10 1000 |
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262 #define NVREG_LINKSPEED_100 100 |
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263 #define NVREG_LINKSPEED_1000 50 |
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264 #define NVREG_LINKSPEED_MASK (0xFFF) |
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265 NvRegUnknownSetupReg5 = 0x130, |
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266 #define NVREG_UNKSETUP5_BIT31 (1<<31) |
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267 NvRegUnknownSetupReg3 = 0x13c, |
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268 #define NVREG_UNKSETUP3_VAL1 0x200010 |
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269 NvRegTxRxControl = 0x144, |
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270 #define NVREG_TXRXCTL_KICK 0x0001 |
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271 #define NVREG_TXRXCTL_BIT1 0x0002 |
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272 #define NVREG_TXRXCTL_BIT2 0x0004 |
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273 #define NVREG_TXRXCTL_IDLE 0x0008 |
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274 #define NVREG_TXRXCTL_RESET 0x0010 |
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275 #define NVREG_TXRXCTL_RXCHECK 0x0400 |
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276 #define NVREG_TXRXCTL_DESC_1 0 |
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277 #define NVREG_TXRXCTL_DESC_2 0x02100 |
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278 #define NVREG_TXRXCTL_DESC_3 0x02200 |
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279 #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
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280 #define NVREG_TXRXCTL_VLANINS 0x00080 |
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281 NvRegTxRingPhysAddrHigh = 0x148, |
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282 NvRegRxRingPhysAddrHigh = 0x14C, |
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283 NvRegMIIStatus = 0x180, |
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284 #define NVREG_MIISTAT_ERROR 0x0001 |
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285 #define NVREG_MIISTAT_LINKCHANGE 0x0008 |
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286 #define NVREG_MIISTAT_MASK 0x000f |
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287 #define NVREG_MIISTAT_MASK2 0x000f |
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288 NvRegUnknownSetupReg4 = 0x184, |
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289 #define NVREG_UNKSETUP4_VAL 8 |
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290 |
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291 NvRegAdapterControl = 0x188, |
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292 #define NVREG_ADAPTCTL_START 0x02 |
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293 #define NVREG_ADAPTCTL_LINKUP 0x04 |
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294 #define NVREG_ADAPTCTL_PHYVALID 0x40000 |
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295 #define NVREG_ADAPTCTL_RUNNING 0x100000 |
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296 #define NVREG_ADAPTCTL_PHYSHIFT 24 |
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297 NvRegMIISpeed = 0x18c, |
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298 #define NVREG_MIISPEED_BIT8 (1<<8) |
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299 #define NVREG_MIIDELAY 5 |
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300 NvRegMIIControl = 0x190, |
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301 #define NVREG_MIICTL_INUSE 0x08000 |
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302 #define NVREG_MIICTL_WRITE 0x00400 |
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303 #define NVREG_MIICTL_ADDRSHIFT 5 |
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304 NvRegMIIData = 0x194, |
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305 NvRegWakeUpFlags = 0x200, |
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306 #define NVREG_WAKEUPFLAGS_VAL 0x7770 |
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307 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 |
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308 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 |
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309 #define NVREG_WAKEUPFLAGS_D3SHIFT 12 |
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310 #define NVREG_WAKEUPFLAGS_D2SHIFT 8 |
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311 #define NVREG_WAKEUPFLAGS_D1SHIFT 4 |
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312 #define NVREG_WAKEUPFLAGS_D0SHIFT 0 |
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313 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 |
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314 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 |
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315 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 |
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316 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
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317 |
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318 NvRegPatternCRC = 0x204, |
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319 NvRegPatternMask = 0x208, |
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320 NvRegPowerCap = 0x268, |
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321 #define NVREG_POWERCAP_D3SUPP (1<<30) |
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322 #define NVREG_POWERCAP_D2SUPP (1<<26) |
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323 #define NVREG_POWERCAP_D1SUPP (1<<25) |
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324 NvRegPowerState = 0x26c, |
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325 #define NVREG_POWERSTATE_POWEREDUP 0x8000 |
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326 #define NVREG_POWERSTATE_VALID 0x0100 |
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327 #define NVREG_POWERSTATE_MASK 0x0003 |
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328 #define NVREG_POWERSTATE_D0 0x0000 |
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329 #define NVREG_POWERSTATE_D1 0x0001 |
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330 #define NVREG_POWERSTATE_D2 0x0002 |
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331 #define NVREG_POWERSTATE_D3 0x0003 |
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332 NvRegVlanControl = 0x300, |
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333 #define NVREG_VLANCONTROL_ENABLE 0x2000 |
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334 NvRegMSIXMap0 = 0x3e0, |
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335 NvRegMSIXMap1 = 0x3e4, |
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336 NvRegMSIXIrqStatus = 0x3f0, |
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337 |
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338 NvRegPowerState2 = 0x600, |
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339 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 |
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340 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
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341 }; |
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342 |
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343 /* Big endian: should work, but is untested */ |
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344 struct ring_desc { |
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345 u32 PacketBuffer; |
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346 u32 FlagLen; |
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347 }; |
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348 |
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349 struct ring_desc_ex { |
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350 u32 PacketBufferHigh; |
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351 u32 PacketBufferLow; |
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352 u32 TxVlan; |
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353 u32 FlagLen; |
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354 }; |
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355 |
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356 typedef union _ring_type { |
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357 struct ring_desc* orig; |
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358 struct ring_desc_ex* ex; |
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359 } ring_type; |
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360 |
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361 #define FLAG_MASK_V1 0xffff0000 |
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362 #define FLAG_MASK_V2 0xffffc000 |
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363 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) |
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364 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) |
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365 |
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366 #define NV_TX_LASTPACKET (1<<16) |
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367 #define NV_TX_RETRYERROR (1<<19) |
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368 #define NV_TX_FORCED_INTERRUPT (1<<24) |
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369 #define NV_TX_DEFERRED (1<<26) |
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370 #define NV_TX_CARRIERLOST (1<<27) |
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371 #define NV_TX_LATECOLLISION (1<<28) |
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372 #define NV_TX_UNDERFLOW (1<<29) |
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373 #define NV_TX_ERROR (1<<30) |
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374 #define NV_TX_VALID (1<<31) |
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375 |
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376 #define NV_TX2_LASTPACKET (1<<29) |
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377 #define NV_TX2_RETRYERROR (1<<18) |
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378 #define NV_TX2_FORCED_INTERRUPT (1<<30) |
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379 #define NV_TX2_DEFERRED (1<<25) |
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380 #define NV_TX2_CARRIERLOST (1<<26) |
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381 #define NV_TX2_LATECOLLISION (1<<27) |
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382 #define NV_TX2_UNDERFLOW (1<<28) |
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383 /* error and valid are the same for both */ |
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384 #define NV_TX2_ERROR (1<<30) |
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385 #define NV_TX2_VALID (1<<31) |
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386 #define NV_TX2_TSO (1<<28) |
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387 #define NV_TX2_TSO_SHIFT 14 |
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388 #define NV_TX2_TSO_MAX_SHIFT 14 |
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389 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) |
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390 #define NV_TX2_CHECKSUM_L3 (1<<27) |
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391 #define NV_TX2_CHECKSUM_L4 (1<<26) |
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392 |
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393 #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
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394 |
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395 #define NV_RX_DESCRIPTORVALID (1<<16) |
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396 #define NV_RX_MISSEDFRAME (1<<17) |
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397 #define NV_RX_SUBSTRACT1 (1<<18) |
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398 #define NV_RX_ERROR1 (1<<23) |
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399 #define NV_RX_ERROR2 (1<<24) |
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400 #define NV_RX_ERROR3 (1<<25) |
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401 #define NV_RX_ERROR4 (1<<26) |
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402 #define NV_RX_CRCERR (1<<27) |
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403 #define NV_RX_OVERFLOW (1<<28) |
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404 #define NV_RX_FRAMINGERR (1<<29) |
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405 #define NV_RX_ERROR (1<<30) |
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406 #define NV_RX_AVAIL (1<<31) |
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407 |
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408 #define NV_RX2_CHECKSUMMASK (0x1C000000) |
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409 #define NV_RX2_CHECKSUMOK1 (0x10000000) |
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410 #define NV_RX2_CHECKSUMOK2 (0x14000000) |
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411 #define NV_RX2_CHECKSUMOK3 (0x18000000) |
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412 #define NV_RX2_DESCRIPTORVALID (1<<29) |
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413 #define NV_RX2_SUBSTRACT1 (1<<25) |
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414 #define NV_RX2_ERROR1 (1<<18) |
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415 #define NV_RX2_ERROR2 (1<<19) |
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416 #define NV_RX2_ERROR3 (1<<20) |
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417 #define NV_RX2_ERROR4 (1<<21) |
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418 #define NV_RX2_CRCERR (1<<22) |
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419 #define NV_RX2_OVERFLOW (1<<23) |
|
420 #define NV_RX2_FRAMINGERR (1<<24) |
|
421 /* error and avail are the same for both */ |
|
422 #define NV_RX2_ERROR (1<<30) |
|
423 #define NV_RX2_AVAIL (1<<31) |
|
424 |
|
425 #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
|
426 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) |
|
427 |
|
428 /* Miscelaneous hardware related defines: */ |
|
429 #define NV_PCI_REGSZ_VER1 0x270 |
|
430 #define NV_PCI_REGSZ_VER2 0x604 |
|
431 |
|
432 /* various timeout delays: all in usec */ |
|
433 #define NV_TXRX_RESET_DELAY 4 |
|
434 #define NV_TXSTOP_DELAY1 10 |
|
435 #define NV_TXSTOP_DELAY1MAX 500000 |
|
436 #define NV_TXSTOP_DELAY2 100 |
|
437 #define NV_RXSTOP_DELAY1 10 |
|
438 #define NV_RXSTOP_DELAY1MAX 500000 |
|
439 #define NV_RXSTOP_DELAY2 100 |
|
440 #define NV_SETUP5_DELAY 5 |
|
441 #define NV_SETUP5_DELAYMAX 50000 |
|
442 #define NV_POWERUP_DELAY 5 |
|
443 #define NV_POWERUP_DELAYMAX 5000 |
|
444 #define NV_MIIBUSY_DELAY 50 |
|
445 #define NV_MIIPHY_DELAY 10 |
|
446 #define NV_MIIPHY_DELAYMAX 10000 |
|
447 #define NV_MAC_RESET_DELAY 64 |
|
448 |
|
449 #define NV_WAKEUPPATTERNS 5 |
|
450 #define NV_WAKEUPMASKENTRIES 4 |
|
451 |
|
452 /* General driver defaults */ |
|
453 #define NV_WATCHDOG_TIMEO (5*HZ) |
|
454 |
|
455 #define RX_RING 128 |
|
456 #define TX_RING 256 |
|
457 /* |
|
458 * If your nic mysteriously hangs then try to reduce the limits |
|
459 * to 1/0: It might be required to set NV_TX_LASTPACKET in the |
|
460 * last valid ring entry. But this would be impossible to |
|
461 * implement - probably a disassembly error. |
|
462 */ |
|
463 #define TX_LIMIT_STOP 255 |
|
464 #define TX_LIMIT_START 254 |
|
465 |
|
466 /* rx/tx mac addr + type + vlan + align + slack*/ |
|
467 #define NV_RX_HEADERS (64) |
|
468 /* even more slack. */ |
|
469 #define NV_RX_ALLOC_PAD (64) |
|
470 |
|
471 /* maximum mtu size */ |
|
472 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ |
|
473 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ |
|
474 |
|
475 #define OOM_REFILL (1+HZ/20) |
|
476 #define POLL_WAIT (1+HZ/100) |
|
477 #define LINK_TIMEOUT (3*HZ) |
|
478 |
|
479 /* |
|
480 * desc_ver values: |
|
481 * The nic supports three different descriptor types: |
|
482 * - DESC_VER_1: Original |
|
483 * - DESC_VER_2: support for jumbo frames. |
|
484 * - DESC_VER_3: 64-bit format. |
|
485 */ |
|
486 #define DESC_VER_1 1 |
|
487 #define DESC_VER_2 2 |
|
488 #define DESC_VER_3 3 |
|
489 |
|
490 /* PHY defines */ |
|
491 #define PHY_OUI_MARVELL 0x5043 |
|
492 #define PHY_OUI_CICADA 0x03f1 |
|
493 #define PHYID1_OUI_MASK 0x03ff |
|
494 #define PHYID1_OUI_SHFT 6 |
|
495 #define PHYID2_OUI_MASK 0xfc00 |
|
496 #define PHYID2_OUI_SHFT 10 |
|
497 #define PHY_INIT1 0x0f000 |
|
498 #define PHY_INIT2 0x0e00 |
|
499 #define PHY_INIT3 0x01000 |
|
500 #define PHY_INIT4 0x0200 |
|
501 #define PHY_INIT5 0x0004 |
|
502 #define PHY_INIT6 0x02000 |
|
503 #define PHY_GIGABIT 0x0100 |
|
504 |
|
505 #define PHY_TIMEOUT 0x1 |
|
506 #define PHY_ERROR 0x2 |
|
507 |
|
508 #define PHY_100 0x1 |
|
509 #define PHY_1000 0x2 |
|
510 #define PHY_HALF 0x100 |
|
511 |
|
512 /* FIXME: MII defines that should be added to <linux/mii.h> */ |
|
513 #define MII_1000BT_CR 0x09 |
|
514 #define MII_1000BT_SR 0x0a |
|
515 #define ADVERTISE_1000FULL 0x0200 |
|
516 #define ADVERTISE_1000HALF 0x0100 |
|
517 #define LPA_1000FULL 0x0800 |
|
518 #define LPA_1000HALF 0x0400 |
|
519 |
|
520 /* MSI/MSI-X defines */ |
|
521 #define NV_MSI_X_MAX_VECTORS 8 |
|
522 #define NV_MSI_X_VECTORS_MASK 0x000f |
|
523 #define NV_MSI_CAPABLE 0x0010 |
|
524 #define NV_MSI_X_CAPABLE 0x0020 |
|
525 #define NV_MSI_ENABLED 0x0040 |
|
526 #define NV_MSI_X_ENABLED 0x0080 |
|
527 |
|
528 #define NV_MSI_X_VECTOR_ALL 0x0 |
|
529 #define NV_MSI_X_VECTOR_RX 0x0 |
|
530 #define NV_MSI_X_VECTOR_TX 0x1 |
|
531 #define NV_MSI_X_VECTOR_OTHER 0x2 |
|
532 |
|
533 /* |
|
534 * SMP locking: |
|
535 * All hardware access under dev->priv->lock, except the performance |
|
536 * critical parts: |
|
537 * - rx is (pseudo-) lockless: it relies on the single-threading provided |
|
538 * by the arch code for interrupts. |
|
539 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission |
|
540 * needs dev->priv->lock :-( |
|
541 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock. |
|
542 */ |
|
543 |
|
544 /* in dev: base, irq */ |
|
545 struct fe_priv { |
|
546 spinlock_t lock; |
|
547 |
|
548 /* General data: |
|
549 * Locking: spin_lock(&np->lock); */ |
|
550 struct net_device_stats stats; |
|
551 int in_shutdown; |
|
552 u32 linkspeed; |
|
553 int duplex; |
|
554 int autoneg; |
|
555 int fixed_mode; |
|
556 int phyaddr; |
|
557 int wolenabled; |
|
558 unsigned int phy_oui; |
|
559 u16 gigabit; |
|
560 |
|
561 /* General data: RO fields */ |
|
562 dma_addr_t ring_addr; |
|
563 struct pci_dev *pci_dev; |
|
564 u32 orig_mac[2]; |
|
565 u32 irqmask; |
|
566 u32 desc_ver; |
|
567 u32 txrxctl_bits; |
|
568 u32 vlanctl_bits; |
|
569 u32 driver_data; |
|
570 u32 register_size; |
|
571 |
|
572 void __iomem *base; |
|
573 |
|
574 /* rx specific fields. |
|
575 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
576 */ |
|
577 ring_type rx_ring; |
|
578 unsigned int cur_rx, refill_rx; |
|
579 struct sk_buff *rx_skbuff[RX_RING]; |
|
580 dma_addr_t rx_dma[RX_RING]; |
|
581 unsigned int rx_buf_sz; |
|
582 unsigned int pkt_limit; |
|
583 struct timer_list oom_kick; |
|
584 struct timer_list nic_poll; |
|
585 u32 nic_poll_irq; |
|
586 |
|
587 /* media detection workaround. |
|
588 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
|
589 */ |
|
590 int need_linktimer; |
|
591 unsigned long link_timeout; |
|
592 /* |
|
593 * tx specific fields. |
|
594 */ |
|
595 ring_type tx_ring; |
|
596 unsigned int next_tx, nic_tx; |
|
597 struct sk_buff *tx_skbuff[TX_RING]; |
|
598 dma_addr_t tx_dma[TX_RING]; |
|
599 unsigned int tx_dma_len[TX_RING]; |
|
600 u32 tx_flags; |
|
601 |
|
602 /* vlan fields */ |
|
603 struct vlan_group *vlangrp; |
|
604 |
|
605 /* msi/msi-x fields */ |
|
606 u32 msi_flags; |
|
607 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; |
|
608 |
|
609 ec_device_t *ecdev; |
|
610 }; |
|
611 |
|
612 /* |
|
613 * Maximum number of loops until we assume that a bit in the irq mask |
|
614 * is stuck. Overridable with module param. |
|
615 */ |
|
616 static int max_interrupt_work = 5; |
|
617 |
|
618 /* |
|
619 * Optimization can be either throuput mode or cpu mode |
|
620 * |
|
621 * Throughput Mode: Every tx and rx packet will generate an interrupt. |
|
622 * CPU Mode: Interrupts are controlled by a timer. |
|
623 */ |
|
624 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0 |
|
625 #define NV_OPTIMIZATION_MODE_CPU 1 |
|
626 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
|
627 |
|
628 /* |
|
629 * Poll interval for timer irq |
|
630 * |
|
631 * This interval determines how frequent an interrupt is generated. |
|
632 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] |
|
633 * Min = 0, and Max = 65535 |
|
634 */ |
|
635 static int poll_interval = -1; |
|
636 |
|
637 /* |
|
638 * Disable MSI interrupts |
|
639 */ |
|
640 static int disable_msi = 0; |
|
641 |
|
642 /* |
|
643 * Disable MSIX interrupts |
|
644 */ |
|
645 static int disable_msix = 0; |
|
646 |
|
647 static int board_idx = -1; |
|
648 |
|
649 static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
|
650 { |
|
651 return netdev_priv(dev); |
|
652 } |
|
653 |
|
654 static inline u8 __iomem *get_hwbase(struct net_device *dev) |
|
655 { |
|
656 return ((struct fe_priv *)netdev_priv(dev))->base; |
|
657 } |
|
658 |
|
659 static inline void pci_push(u8 __iomem *base) |
|
660 { |
|
661 /* force out pending posted writes */ |
|
662 readl(base); |
|
663 } |
|
664 |
|
665 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) |
|
666 { |
|
667 return le32_to_cpu(prd->FlagLen) |
|
668 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
|
669 } |
|
670 |
|
671 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
|
672 { |
|
673 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2; |
|
674 } |
|
675 |
|
676 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
|
677 int delay, int delaymax, const char *msg) |
|
678 { |
|
679 u8 __iomem *base = get_hwbase(dev); |
|
680 |
|
681 pci_push(base); |
|
682 do { |
|
683 udelay(delay); |
|
684 delaymax -= delay; |
|
685 if (delaymax < 0) { |
|
686 if (msg) |
|
687 printk(msg); |
|
688 return 1; |
|
689 } |
|
690 } while ((readl(base + offset) & mask) != target); |
|
691 return 0; |
|
692 } |
|
693 |
|
694 #define NV_SETUP_RX_RING 0x01 |
|
695 #define NV_SETUP_TX_RING 0x02 |
|
696 |
|
697 static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
|
698 { |
|
699 struct fe_priv *np = get_nvpriv(dev); |
|
700 u8 __iomem *base = get_hwbase(dev); |
|
701 |
|
702 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
703 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
704 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
705 } |
|
706 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
707 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
|
708 } |
|
709 } else { |
|
710 if (rxtx_flags & NV_SETUP_RX_RING) { |
|
711 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr); |
|
712 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh); |
|
713 } |
|
714 if (rxtx_flags & NV_SETUP_TX_RING) { |
|
715 writel((u32) cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
|
716 writel((u32) (cpu_to_le64(np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh); |
|
717 } |
|
718 } |
|
719 } |
|
720 |
|
721 static int using_multi_irqs(struct net_device *dev) |
|
722 { |
|
723 struct fe_priv *np = get_nvpriv(dev); |
|
724 |
|
725 if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
|
726 ((np->msi_flags & NV_MSI_X_ENABLED) && |
|
727 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) |
|
728 return 0; |
|
729 else |
|
730 return 1; |
|
731 } |
|
732 |
|
733 static void nv_enable_irq(struct net_device *dev) |
|
734 { |
|
735 struct fe_priv *np = get_nvpriv(dev); |
|
736 |
|
737 if (!using_multi_irqs(dev)) { |
|
738 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
739 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
740 else |
|
741 enable_irq(dev->irq); |
|
742 } else { |
|
743 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
744 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
745 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
746 } |
|
747 } |
|
748 |
|
749 static void nv_disable_irq(struct net_device *dev) |
|
750 { |
|
751 struct fe_priv *np = get_nvpriv(dev); |
|
752 |
|
753 if (!using_multi_irqs(dev)) { |
|
754 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
755 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
756 else |
|
757 disable_irq(dev->irq); |
|
758 } else { |
|
759 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
760 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
761 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
762 } |
|
763 } |
|
764 |
|
765 /* In MSIX mode, a write to irqmask behaves as XOR */ |
|
766 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) |
|
767 { |
|
768 u8 __iomem *base = get_hwbase(dev); |
|
769 |
|
770 writel(mask, base + NvRegIrqMask); |
|
771 } |
|
772 |
|
773 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) |
|
774 { |
|
775 struct fe_priv *np = get_nvpriv(dev); |
|
776 u8 __iomem *base = get_hwbase(dev); |
|
777 |
|
778 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
779 writel(mask, base + NvRegIrqMask); |
|
780 } else { |
|
781 if (np->msi_flags & NV_MSI_ENABLED) |
|
782 writel(0, base + NvRegMSIIrqMask); |
|
783 writel(0, base + NvRegIrqMask); |
|
784 } |
|
785 } |
|
786 |
|
787 #define MII_READ (-1) |
|
788 /* mii_rw: read/write a register on the PHY. |
|
789 * |
|
790 * Caller must guarantee serialization |
|
791 */ |
|
792 static int mii_rw(struct net_device *dev, int addr, int miireg, int value) |
|
793 { |
|
794 u8 __iomem *base = get_hwbase(dev); |
|
795 u32 reg; |
|
796 int retval; |
|
797 |
|
798 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
799 |
|
800 reg = readl(base + NvRegMIIControl); |
|
801 if (reg & NVREG_MIICTL_INUSE) { |
|
802 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); |
|
803 udelay(NV_MIIBUSY_DELAY); |
|
804 } |
|
805 |
|
806 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; |
|
807 if (value != MII_READ) { |
|
808 writel(value, base + NvRegMIIData); |
|
809 reg |= NVREG_MIICTL_WRITE; |
|
810 } |
|
811 writel(reg, base + NvRegMIIControl); |
|
812 |
|
813 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, |
|
814 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) { |
|
815 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n", |
|
816 dev->name, miireg, addr); |
|
817 retval = -1; |
|
818 } else if (value != MII_READ) { |
|
819 /* it was a write operation - fewer failures are detectable */ |
|
820 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n", |
|
821 dev->name, value, miireg, addr); |
|
822 retval = 0; |
|
823 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { |
|
824 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n", |
|
825 dev->name, miireg, addr); |
|
826 retval = -1; |
|
827 } else { |
|
828 retval = readl(base + NvRegMIIData); |
|
829 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n", |
|
830 dev->name, miireg, addr, retval); |
|
831 } |
|
832 |
|
833 return retval; |
|
834 } |
|
835 |
|
836 static int phy_reset(struct net_device *dev) |
|
837 { |
|
838 struct fe_priv *np = netdev_priv(dev); |
|
839 u32 miicontrol; |
|
840 unsigned int tries = 0; |
|
841 |
|
842 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
843 miicontrol |= BMCR_RESET; |
|
844 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
|
845 return -1; |
|
846 } |
|
847 |
|
848 /* wait for 500ms */ |
|
849 msleep(500); |
|
850 |
|
851 /* must wait till reset is deasserted */ |
|
852 while (miicontrol & BMCR_RESET) { |
|
853 msleep(10); |
|
854 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
855 /* FIXME: 100 tries seem excessive */ |
|
856 if (tries++ > 100) |
|
857 return -1; |
|
858 } |
|
859 return 0; |
|
860 } |
|
861 |
|
862 static int phy_init(struct net_device *dev) |
|
863 { |
|
864 struct fe_priv *np = get_nvpriv(dev); |
|
865 u8 __iomem *base = get_hwbase(dev); |
|
866 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
|
867 |
|
868 /* set advertise register */ |
|
869 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
870 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400); |
|
871 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
|
872 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
|
873 return PHY_ERROR; |
|
874 } |
|
875 |
|
876 /* get phy interface type */ |
|
877 phyinterface = readl(base + NvRegPhyInterface); |
|
878 |
|
879 /* see if gigabit phy */ |
|
880 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
881 if (mii_status & PHY_GIGABIT) { |
|
882 np->gigabit = PHY_GIGABIT; |
|
883 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
884 mii_control_1000 &= ~ADVERTISE_1000HALF; |
|
885 if (phyinterface & PHY_RGMII) |
|
886 mii_control_1000 |= ADVERTISE_1000FULL; |
|
887 else |
|
888 mii_control_1000 &= ~ADVERTISE_1000FULL; |
|
889 |
|
890 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) { |
|
891 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
892 return PHY_ERROR; |
|
893 } |
|
894 } |
|
895 else |
|
896 np->gigabit = 0; |
|
897 |
|
898 /* reset the phy */ |
|
899 if (phy_reset(dev)) { |
|
900 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
|
901 return PHY_ERROR; |
|
902 } |
|
903 |
|
904 /* phy vendor specific configuration */ |
|
905 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
|
906 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
|
907 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); |
|
908 phy_reserved |= (PHY_INIT3 | PHY_INIT4); |
|
909 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
|
910 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
911 return PHY_ERROR; |
|
912 } |
|
913 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
|
914 phy_reserved |= PHY_INIT5; |
|
915 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
|
916 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
917 return PHY_ERROR; |
|
918 } |
|
919 } |
|
920 if (np->phy_oui == PHY_OUI_CICADA) { |
|
921 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
|
922 phy_reserved |= PHY_INIT6; |
|
923 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
|
924 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
|
925 return PHY_ERROR; |
|
926 } |
|
927 } |
|
928 |
|
929 /* restart auto negotiation */ |
|
930 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
931 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
|
932 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
|
933 return PHY_ERROR; |
|
934 } |
|
935 |
|
936 return 0; |
|
937 } |
|
938 |
|
939 static void nv_start_rx(struct net_device *dev) |
|
940 { |
|
941 struct fe_priv *np = netdev_priv(dev); |
|
942 u8 __iomem *base = get_hwbase(dev); |
|
943 |
|
944 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
|
945 /* Already running? Stop it. */ |
|
946 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { |
|
947 writel(0, base + NvRegReceiverControl); |
|
948 pci_push(base); |
|
949 } |
|
950 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
951 pci_push(base); |
|
952 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); |
|
953 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
|
954 dev->name, np->duplex, np->linkspeed); |
|
955 pci_push(base); |
|
956 } |
|
957 |
|
958 static void nv_stop_rx(struct net_device *dev) |
|
959 { |
|
960 u8 __iomem *base = get_hwbase(dev); |
|
961 |
|
962 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
|
963 writel(0, base + NvRegReceiverControl); |
|
964 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
|
965 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
|
966 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
|
967 |
|
968 udelay(NV_RXSTOP_DELAY2); |
|
969 writel(0, base + NvRegLinkSpeed); |
|
970 } |
|
971 |
|
972 static void nv_start_tx(struct net_device *dev) |
|
973 { |
|
974 u8 __iomem *base = get_hwbase(dev); |
|
975 |
|
976 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
|
977 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); |
|
978 pci_push(base); |
|
979 } |
|
980 |
|
981 static void nv_stop_tx(struct net_device *dev) |
|
982 { |
|
983 u8 __iomem *base = get_hwbase(dev); |
|
984 |
|
985 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
|
986 writel(0, base + NvRegTransmitterControl); |
|
987 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
|
988 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
|
989 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
|
990 |
|
991 udelay(NV_TXSTOP_DELAY2); |
|
992 writel(0, base + NvRegUnknownTransmitterReg); |
|
993 } |
|
994 |
|
995 static void nv_txrx_reset(struct net_device *dev) |
|
996 { |
|
997 struct fe_priv *np = netdev_priv(dev); |
|
998 u8 __iomem *base = get_hwbase(dev); |
|
999 |
|
1000 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
|
1001 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1002 pci_push(base); |
|
1003 udelay(NV_TXRX_RESET_DELAY); |
|
1004 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1005 pci_push(base); |
|
1006 } |
|
1007 |
|
1008 static void nv_mac_reset(struct net_device *dev) |
|
1009 { |
|
1010 struct fe_priv *np = netdev_priv(dev); |
|
1011 u8 __iomem *base = get_hwbase(dev); |
|
1012 |
|
1013 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); |
|
1014 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1015 pci_push(base); |
|
1016 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
|
1017 pci_push(base); |
|
1018 udelay(NV_MAC_RESET_DELAY); |
|
1019 writel(0, base + NvRegMacReset); |
|
1020 pci_push(base); |
|
1021 udelay(NV_MAC_RESET_DELAY); |
|
1022 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
|
1023 pci_push(base); |
|
1024 } |
|
1025 |
|
1026 /* |
|
1027 * nv_get_stats: dev->get_stats function |
|
1028 * Get latest stats value from the nic. |
|
1029 * Called with read_lock(&dev_base_lock) held for read - |
|
1030 * only synchronized against unregister_netdevice. |
|
1031 */ |
|
1032 static struct net_device_stats *nv_get_stats(struct net_device *dev) |
|
1033 { |
|
1034 struct fe_priv *np = netdev_priv(dev); |
|
1035 |
|
1036 /* It seems that the nic always generates interrupts and doesn't |
|
1037 * accumulate errors internally. Thus the current values in np->stats |
|
1038 * are already up to date. |
|
1039 */ |
|
1040 return &np->stats; |
|
1041 } |
|
1042 |
|
1043 /* |
|
1044 * nv_alloc_rx: fill rx ring entries. |
|
1045 * Return 1 if the allocations for the skbs failed and the |
|
1046 * rx engine is without Available descriptors |
|
1047 */ |
|
1048 static int nv_alloc_rx(struct net_device *dev) |
|
1049 { |
|
1050 struct fe_priv *np = netdev_priv(dev); |
|
1051 unsigned int refill_rx = np->refill_rx; |
|
1052 int nr; |
|
1053 |
|
1054 while (np->cur_rx != refill_rx) { |
|
1055 struct sk_buff *skb; |
|
1056 |
|
1057 nr = refill_rx % RX_RING; |
|
1058 if (np->rx_skbuff[nr] == NULL) { |
|
1059 |
|
1060 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
|
1061 if (!skb) |
|
1062 break; |
|
1063 |
|
1064 skb->dev = dev; |
|
1065 np->rx_skbuff[nr] = skb; |
|
1066 } else { |
|
1067 skb = np->rx_skbuff[nr]; |
|
1068 } |
|
1069 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, |
|
1070 skb->end-skb->data, PCI_DMA_FROMDEVICE); |
|
1071 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1072 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); |
|
1073 wmb(); |
|
1074 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); |
|
1075 } else { |
|
1076 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32; |
|
1077 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; |
|
1078 wmb(); |
|
1079 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); |
|
1080 } |
|
1081 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
|
1082 dev->name, refill_rx); |
|
1083 refill_rx++; |
|
1084 } |
|
1085 np->refill_rx = refill_rx; |
|
1086 if (np->cur_rx - refill_rx == RX_RING) |
|
1087 return 1; |
|
1088 return 0; |
|
1089 } |
|
1090 |
|
1091 static void nv_do_rx_refill(unsigned long data) |
|
1092 { |
|
1093 struct net_device *dev = (struct net_device *) data; |
|
1094 struct fe_priv *np = netdev_priv(dev); |
|
1095 |
|
1096 if (!using_multi_irqs(dev)) { |
|
1097 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1098 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1099 else |
|
1100 disable_irq(dev->irq); |
|
1101 } else { |
|
1102 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1103 } |
|
1104 if (nv_alloc_rx(dev)) { |
|
1105 spin_lock_irq(&np->lock); |
|
1106 if (!np->in_shutdown) |
|
1107 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
1108 spin_unlock_irq(&np->lock); |
|
1109 } |
|
1110 if (!using_multi_irqs(dev)) { |
|
1111 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1112 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
1113 else |
|
1114 enable_irq(dev->irq); |
|
1115 } else { |
|
1116 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
1117 } |
|
1118 } |
|
1119 |
|
1120 static void nv_init_rx(struct net_device *dev) |
|
1121 { |
|
1122 struct fe_priv *np = netdev_priv(dev); |
|
1123 int i; |
|
1124 |
|
1125 np->cur_rx = RX_RING; |
|
1126 np->refill_rx = 0; |
|
1127 for (i = 0; i < RX_RING; i++) |
|
1128 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1129 np->rx_ring.orig[i].FlagLen = 0; |
|
1130 else |
|
1131 np->rx_ring.ex[i].FlagLen = 0; |
|
1132 } |
|
1133 |
|
1134 static void nv_init_tx(struct net_device *dev) |
|
1135 { |
|
1136 struct fe_priv *np = netdev_priv(dev); |
|
1137 int i; |
|
1138 |
|
1139 np->next_tx = np->nic_tx = 0; |
|
1140 for (i = 0; i < TX_RING; i++) { |
|
1141 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1142 np->tx_ring.orig[i].FlagLen = 0; |
|
1143 else |
|
1144 np->tx_ring.ex[i].FlagLen = 0; |
|
1145 np->tx_skbuff[i] = NULL; |
|
1146 np->tx_dma[i] = 0; |
|
1147 } |
|
1148 } |
|
1149 |
|
1150 static int nv_init_ring(struct net_device *dev) |
|
1151 { |
|
1152 nv_init_tx(dev); |
|
1153 nv_init_rx(dev); |
|
1154 return nv_alloc_rx(dev); |
|
1155 } |
|
1156 |
|
1157 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
|
1158 { |
|
1159 struct fe_priv *np = netdev_priv(dev); |
|
1160 |
|
1161 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", |
|
1162 dev->name, skbnr); |
|
1163 |
|
1164 if (np->tx_dma[skbnr]) { |
|
1165 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr], |
|
1166 np->tx_dma_len[skbnr], |
|
1167 PCI_DMA_TODEVICE); |
|
1168 np->tx_dma[skbnr] = 0; |
|
1169 } |
|
1170 |
|
1171 if (np->tx_skbuff[skbnr]) { |
|
1172 if (!np->ecdev) dev_kfree_skb_any(np->tx_skbuff[skbnr]); |
|
1173 np->tx_skbuff[skbnr] = NULL; |
|
1174 return 1; |
|
1175 } else { |
|
1176 return 0; |
|
1177 } |
|
1178 } |
|
1179 |
|
1180 static void nv_drain_tx(struct net_device *dev) |
|
1181 { |
|
1182 struct fe_priv *np = netdev_priv(dev); |
|
1183 unsigned int i; |
|
1184 |
|
1185 for (i = 0; i < TX_RING; i++) { |
|
1186 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1187 np->tx_ring.orig[i].FlagLen = 0; |
|
1188 else |
|
1189 np->tx_ring.ex[i].FlagLen = 0; |
|
1190 if (nv_release_txskb(dev, i)) |
|
1191 np->stats.tx_dropped++; |
|
1192 } |
|
1193 } |
|
1194 |
|
1195 static void nv_drain_rx(struct net_device *dev) |
|
1196 { |
|
1197 struct fe_priv *np = netdev_priv(dev); |
|
1198 int i; |
|
1199 for (i = 0; i < RX_RING; i++) { |
|
1200 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1201 np->rx_ring.orig[i].FlagLen = 0; |
|
1202 else |
|
1203 np->rx_ring.ex[i].FlagLen = 0; |
|
1204 wmb(); |
|
1205 if (np->rx_skbuff[i]) { |
|
1206 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1207 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1208 PCI_DMA_FROMDEVICE); |
|
1209 if (!np->ecdev) dev_kfree_skb(np->rx_skbuff[i]); |
|
1210 np->rx_skbuff[i] = NULL; |
|
1211 } |
|
1212 } |
|
1213 } |
|
1214 |
|
1215 static void drain_ring(struct net_device *dev) |
|
1216 { |
|
1217 nv_drain_tx(dev); |
|
1218 nv_drain_rx(dev); |
|
1219 } |
|
1220 |
|
1221 /* |
|
1222 * nv_start_xmit: dev->hard_start_xmit function |
|
1223 * Called with dev->xmit_lock held. |
|
1224 */ |
|
1225 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
|
1226 { |
|
1227 struct fe_priv *np = netdev_priv(dev); |
|
1228 u32 tx_flags = 0; |
|
1229 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
|
1230 unsigned int fragments = skb_shinfo(skb)->nr_frags; |
|
1231 unsigned int nr = (np->next_tx - 1) % TX_RING; |
|
1232 unsigned int start_nr = np->next_tx % TX_RING; |
|
1233 unsigned int i; |
|
1234 u32 offset = 0; |
|
1235 u32 bcnt; |
|
1236 u32 size = skb->len-skb->data_len; |
|
1237 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1238 u32 tx_flags_vlan = 0; |
|
1239 |
|
1240 /* add fragments to entries count */ |
|
1241 for (i = 0; i < fragments; i++) { |
|
1242 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
|
1243 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
|
1244 } |
|
1245 |
|
1246 if (!np->ecdev) { |
|
1247 spin_lock_irq(&np->lock); |
|
1248 |
|
1249 if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) { |
|
1250 spin_unlock_irq(&np->lock); |
|
1251 netif_stop_queue(dev); |
|
1252 return NETDEV_TX_BUSY; |
|
1253 } |
|
1254 } |
|
1255 |
|
1256 /* setup the header buffer */ |
|
1257 do { |
|
1258 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1259 nr = (nr + 1) % TX_RING; |
|
1260 |
|
1261 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
|
1262 PCI_DMA_TODEVICE); |
|
1263 np->tx_dma_len[nr] = bcnt; |
|
1264 |
|
1265 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1266 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
|
1267 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1268 } else { |
|
1269 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1270 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1271 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1272 } |
|
1273 tx_flags = np->tx_flags; |
|
1274 offset += bcnt; |
|
1275 size -= bcnt; |
|
1276 } while(size); |
|
1277 |
|
1278 /* setup the fragments */ |
|
1279 for (i = 0; i < fragments; i++) { |
|
1280 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
|
1281 u32 size = frag->size; |
|
1282 offset = 0; |
|
1283 |
|
1284 do { |
|
1285 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
|
1286 nr = (nr + 1) % TX_RING; |
|
1287 |
|
1288 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
|
1289 PCI_DMA_TODEVICE); |
|
1290 np->tx_dma_len[nr] = bcnt; |
|
1291 |
|
1292 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1293 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
|
1294 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1295 } else { |
|
1296 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
|
1297 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
|
1298 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
1299 } |
|
1300 offset += bcnt; |
|
1301 size -= bcnt; |
|
1302 } while (size); |
|
1303 } |
|
1304 |
|
1305 /* set last fragment flag */ |
|
1306 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1307 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
|
1308 } else { |
|
1309 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
|
1310 } |
|
1311 |
|
1312 np->tx_skbuff[nr] = skb; |
|
1313 |
|
1314 #ifdef NETIF_F_TSO |
|
1315 if (skb_shinfo(skb)->tso_size) |
|
1316 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT); |
|
1317 else |
|
1318 #endif |
|
1319 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
|
1320 |
|
1321 /* vlan tag */ |
|
1322 if (np->vlangrp && vlan_tx_tag_present(skb)) { |
|
1323 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb); |
|
1324 } |
|
1325 |
|
1326 /* set tx flags */ |
|
1327 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1328 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1329 } else { |
|
1330 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan); |
|
1331 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
|
1332 } |
|
1333 |
|
1334 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", |
|
1335 dev->name, np->next_tx, entries, tx_flags_extra); |
|
1336 { |
|
1337 int j; |
|
1338 for (j=0; j<64; j++) { |
|
1339 if ((j%16) == 0) |
|
1340 dprintk("\n%03x:", j); |
|
1341 dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
|
1342 } |
|
1343 dprintk("\n"); |
|
1344 } |
|
1345 |
|
1346 np->next_tx += entries; |
|
1347 |
|
1348 dev->trans_start = jiffies; |
|
1349 if (!np->ecdev) spin_unlock_irq(&np->lock); |
|
1350 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
1351 pci_push(get_hwbase(dev)); |
|
1352 return NETDEV_TX_OK; |
|
1353 } |
|
1354 |
|
1355 /* |
|
1356 * nv_tx_done: check for completed packets, release the skbs. |
|
1357 * |
|
1358 * Caller must own np->lock. |
|
1359 */ |
|
1360 static void nv_tx_done(struct net_device *dev) |
|
1361 { |
|
1362 struct fe_priv *np = netdev_priv(dev); |
|
1363 u32 Flags; |
|
1364 unsigned int i; |
|
1365 struct sk_buff *skb; |
|
1366 |
|
1367 while (np->nic_tx != np->next_tx) { |
|
1368 i = np->nic_tx % TX_RING; |
|
1369 |
|
1370 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
1371 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen); |
|
1372 else |
|
1373 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen); |
|
1374 |
|
1375 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", |
|
1376 dev->name, np->nic_tx, Flags); |
|
1377 if (Flags & NV_TX_VALID) |
|
1378 break; |
|
1379 if (np->desc_ver == DESC_VER_1) { |
|
1380 if (Flags & NV_TX_LASTPACKET) { |
|
1381 skb = np->tx_skbuff[i]; |
|
1382 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
|
1383 NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
|
1384 if (Flags & NV_TX_UNDERFLOW) |
|
1385 np->stats.tx_fifo_errors++; |
|
1386 if (Flags & NV_TX_CARRIERLOST) |
|
1387 np->stats.tx_carrier_errors++; |
|
1388 np->stats.tx_errors++; |
|
1389 } else { |
|
1390 np->stats.tx_packets++; |
|
1391 np->stats.tx_bytes += skb->len; |
|
1392 } |
|
1393 } |
|
1394 } else { |
|
1395 if (Flags & NV_TX2_LASTPACKET) { |
|
1396 skb = np->tx_skbuff[i]; |
|
1397 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
|
1398 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
|
1399 if (Flags & NV_TX2_UNDERFLOW) |
|
1400 np->stats.tx_fifo_errors++; |
|
1401 if (Flags & NV_TX2_CARRIERLOST) |
|
1402 np->stats.tx_carrier_errors++; |
|
1403 np->stats.tx_errors++; |
|
1404 } else { |
|
1405 np->stats.tx_packets++; |
|
1406 np->stats.tx_bytes += skb->len; |
|
1407 } |
|
1408 } |
|
1409 } |
|
1410 nv_release_txskb(dev, i); |
|
1411 np->nic_tx++; |
|
1412 } |
|
1413 if (!np->ecdev && np->next_tx - np->nic_tx < TX_LIMIT_START) |
|
1414 netif_wake_queue(dev); |
|
1415 } |
|
1416 |
|
1417 /* |
|
1418 * nv_tx_timeout: dev->tx_timeout function |
|
1419 * Called with dev->xmit_lock held. |
|
1420 */ |
|
1421 static void nv_tx_timeout(struct net_device *dev) |
|
1422 { |
|
1423 struct fe_priv *np = netdev_priv(dev); |
|
1424 u8 __iomem *base = get_hwbase(dev); |
|
1425 u32 status; |
|
1426 |
|
1427 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
1428 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1429 else |
|
1430 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
1431 |
|
1432 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); |
|
1433 |
|
1434 { |
|
1435 int i; |
|
1436 |
|
1437 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n", |
|
1438 dev->name, (unsigned long)np->ring_addr, |
|
1439 np->next_tx, np->nic_tx); |
|
1440 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
|
1441 for (i=0;i<=np->register_size;i+= 32) { |
|
1442 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
|
1443 i, |
|
1444 readl(base + i + 0), readl(base + i + 4), |
|
1445 readl(base + i + 8), readl(base + i + 12), |
|
1446 readl(base + i + 16), readl(base + i + 20), |
|
1447 readl(base + i + 24), readl(base + i + 28)); |
|
1448 } |
|
1449 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); |
|
1450 for (i=0;i<TX_RING;i+= 4) { |
|
1451 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1452 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
|
1453 i, |
|
1454 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), |
|
1455 le32_to_cpu(np->tx_ring.orig[i].FlagLen), |
|
1456 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), |
|
1457 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen), |
|
1458 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer), |
|
1459 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen), |
|
1460 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer), |
|
1461 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); |
|
1462 } else { |
|
1463 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
|
1464 i, |
|
1465 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), |
|
1466 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), |
|
1467 le32_to_cpu(np->tx_ring.ex[i].FlagLen), |
|
1468 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh), |
|
1469 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow), |
|
1470 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen), |
|
1471 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh), |
|
1472 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow), |
|
1473 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen), |
|
1474 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh), |
|
1475 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow), |
|
1476 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen)); |
|
1477 } |
|
1478 } |
|
1479 } |
|
1480 |
|
1481 if (!np->ecdev) spin_lock_irq(&np->lock); |
|
1482 |
|
1483 /* 1) stop tx engine */ |
|
1484 nv_stop_tx(dev); |
|
1485 |
|
1486 /* 2) check that the packets were not sent already: */ |
|
1487 nv_tx_done(dev); |
|
1488 |
|
1489 /* 3) if there are dead entries: clear everything */ |
|
1490 if (np->next_tx != np->nic_tx) { |
|
1491 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
|
1492 nv_drain_tx(dev); |
|
1493 np->next_tx = np->nic_tx = 0; |
|
1494 setup_hw_rings(dev, NV_SETUP_TX_RING); |
|
1495 if (!np->ecdev) netif_wake_queue(dev); |
|
1496 } |
|
1497 |
|
1498 /* 4) restart tx engine */ |
|
1499 nv_start_tx(dev); |
|
1500 if (!np->ecdev) spin_unlock_irq(&np->lock); |
|
1501 } |
|
1502 |
|
1503 /* |
|
1504 * Called when the nic notices a mismatch between the actual data len on the |
|
1505 * wire and the len indicated in the 802 header |
|
1506 */ |
|
1507 static int nv_getlen(struct net_device *dev, void *packet, int datalen) |
|
1508 { |
|
1509 int hdrlen; /* length of the 802 header */ |
|
1510 int protolen; /* length as stored in the proto field */ |
|
1511 |
|
1512 /* 1) calculate len according to header */ |
|
1513 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { |
|
1514 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); |
|
1515 hdrlen = VLAN_HLEN; |
|
1516 } else { |
|
1517 protolen = ntohs( ((struct ethhdr *)packet)->h_proto); |
|
1518 hdrlen = ETH_HLEN; |
|
1519 } |
|
1520 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", |
|
1521 dev->name, datalen, protolen, hdrlen); |
|
1522 if (protolen > ETH_DATA_LEN) |
|
1523 return datalen; /* Value in proto field not a len, no checks possible */ |
|
1524 |
|
1525 protolen += hdrlen; |
|
1526 /* consistency checks: */ |
|
1527 if (datalen > ETH_ZLEN) { |
|
1528 if (datalen >= protolen) { |
|
1529 /* more data on wire than in 802 header, trim of |
|
1530 * additional data. |
|
1531 */ |
|
1532 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1533 dev->name, protolen); |
|
1534 return protolen; |
|
1535 } else { |
|
1536 /* less data on wire than mentioned in header. |
|
1537 * Discard the packet. |
|
1538 */ |
|
1539 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", |
|
1540 dev->name); |
|
1541 return -1; |
|
1542 } |
|
1543 } else { |
|
1544 /* short packet. Accept only if 802 values are also short */ |
|
1545 if (protolen > ETH_ZLEN) { |
|
1546 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", |
|
1547 dev->name); |
|
1548 return -1; |
|
1549 } |
|
1550 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", |
|
1551 dev->name, datalen); |
|
1552 return datalen; |
|
1553 } |
|
1554 } |
|
1555 |
|
1556 static void nv_rx_process(struct net_device *dev) |
|
1557 { |
|
1558 struct fe_priv *np = netdev_priv(dev); |
|
1559 u32 Flags; |
|
1560 u32 vlanflags = 0; |
|
1561 |
|
1562 |
|
1563 for (;;) { |
|
1564 struct sk_buff *skb; |
|
1565 int len; |
|
1566 int i; |
|
1567 if (np->cur_rx - np->refill_rx >= RX_RING) |
|
1568 break; /* we scanned the whole ring - do not continue */ |
|
1569 |
|
1570 i = np->cur_rx % RX_RING; |
|
1571 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
1572 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen); |
|
1573 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); |
|
1574 } else { |
|
1575 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen); |
|
1576 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); |
|
1577 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow); |
|
1578 } |
|
1579 |
|
1580 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", |
|
1581 dev->name, np->cur_rx, Flags); |
|
1582 |
|
1583 if (Flags & NV_RX_AVAIL) |
|
1584 break; /* still owned by hardware, */ |
|
1585 |
|
1586 /* |
|
1587 * the packet is for us - immediately tear down the pci mapping. |
|
1588 * TODO: check if a prefetch of the first cacheline improves |
|
1589 * the performance. |
|
1590 */ |
|
1591 pci_unmap_single(np->pci_dev, np->rx_dma[i], |
|
1592 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
|
1593 PCI_DMA_FROMDEVICE); |
|
1594 |
|
1595 { |
|
1596 int j; |
|
1597 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags); |
|
1598 for (j=0; j<64; j++) { |
|
1599 if ((j%16) == 0) |
|
1600 dprintk("\n%03x:", j); |
|
1601 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); |
|
1602 } |
|
1603 dprintk("\n"); |
|
1604 } |
|
1605 /* look at what we actually got: */ |
|
1606 if (np->desc_ver == DESC_VER_1) { |
|
1607 if (!(Flags & NV_RX_DESCRIPTORVALID)) |
|
1608 goto next_pkt; |
|
1609 |
|
1610 if (Flags & NV_RX_ERROR) { |
|
1611 if (Flags & NV_RX_MISSEDFRAME) { |
|
1612 np->stats.rx_missed_errors++; |
|
1613 np->stats.rx_errors++; |
|
1614 goto next_pkt; |
|
1615 } |
|
1616 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
|
1617 np->stats.rx_errors++; |
|
1618 goto next_pkt; |
|
1619 } |
|
1620 if (Flags & NV_RX_CRCERR) { |
|
1621 np->stats.rx_crc_errors++; |
|
1622 np->stats.rx_errors++; |
|
1623 goto next_pkt; |
|
1624 } |
|
1625 if (Flags & NV_RX_OVERFLOW) { |
|
1626 np->stats.rx_over_errors++; |
|
1627 np->stats.rx_errors++; |
|
1628 goto next_pkt; |
|
1629 } |
|
1630 if (Flags & NV_RX_ERROR4) { |
|
1631 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1632 if (len < 0) { |
|
1633 np->stats.rx_errors++; |
|
1634 goto next_pkt; |
|
1635 } |
|
1636 } |
|
1637 /* framing errors are soft errors. */ |
|
1638 if (Flags & NV_RX_FRAMINGERR) { |
|
1639 if (Flags & NV_RX_SUBSTRACT1) { |
|
1640 len--; |
|
1641 } |
|
1642 } |
|
1643 } |
|
1644 } else { |
|
1645 if (!(Flags & NV_RX2_DESCRIPTORVALID)) |
|
1646 goto next_pkt; |
|
1647 |
|
1648 if (Flags & NV_RX2_ERROR) { |
|
1649 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { |
|
1650 np->stats.rx_errors++; |
|
1651 goto next_pkt; |
|
1652 } |
|
1653 if (Flags & NV_RX2_CRCERR) { |
|
1654 np->stats.rx_crc_errors++; |
|
1655 np->stats.rx_errors++; |
|
1656 goto next_pkt; |
|
1657 } |
|
1658 if (Flags & NV_RX2_OVERFLOW) { |
|
1659 np->stats.rx_over_errors++; |
|
1660 np->stats.rx_errors++; |
|
1661 goto next_pkt; |
|
1662 } |
|
1663 if (Flags & NV_RX2_ERROR4) { |
|
1664 len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
|
1665 if (len < 0) { |
|
1666 np->stats.rx_errors++; |
|
1667 goto next_pkt; |
|
1668 } |
|
1669 } |
|
1670 /* framing errors are soft errors */ |
|
1671 if (Flags & NV_RX2_FRAMINGERR) { |
|
1672 if (Flags & NV_RX2_SUBSTRACT1) { |
|
1673 len--; |
|
1674 } |
|
1675 } |
|
1676 } |
|
1677 Flags &= NV_RX2_CHECKSUMMASK; |
|
1678 if (Flags == NV_RX2_CHECKSUMOK1 || |
|
1679 Flags == NV_RX2_CHECKSUMOK2 || |
|
1680 Flags == NV_RX2_CHECKSUMOK3) { |
|
1681 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); |
|
1682 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; |
|
1683 } else { |
|
1684 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); |
|
1685 } |
|
1686 } |
|
1687 if (np->ecdev) { |
|
1688 ecdev_receive(np->ecdev, np->rx_skbuff[i]->data, len); |
|
1689 } |
|
1690 else { |
|
1691 /* got a valid packet - forward it to the network core */ |
|
1692 skb = np->rx_skbuff[i]; |
|
1693 np->rx_skbuff[i] = NULL; |
|
1694 |
|
1695 skb_put(skb, len); |
|
1696 skb->protocol = eth_type_trans(skb, dev); |
|
1697 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", |
|
1698 dev->name, np->cur_rx, len, skb->protocol); |
|
1699 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) { |
|
1700 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); |
|
1701 } else { |
|
1702 netif_rx(skb); |
|
1703 } |
|
1704 } |
|
1705 dev->last_rx = jiffies; |
|
1706 np->stats.rx_packets++; |
|
1707 np->stats.rx_bytes += len; |
|
1708 next_pkt: |
|
1709 np->cur_rx++; |
|
1710 } |
|
1711 } |
|
1712 |
|
1713 static void set_bufsize(struct net_device *dev) |
|
1714 { |
|
1715 struct fe_priv *np = netdev_priv(dev); |
|
1716 |
|
1717 if (dev->mtu <= ETH_DATA_LEN) |
|
1718 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; |
|
1719 else |
|
1720 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; |
|
1721 } |
|
1722 |
|
1723 /* |
|
1724 * nv_change_mtu: dev->change_mtu function |
|
1725 * Called with dev_base_lock held for read. |
|
1726 */ |
|
1727 static int nv_change_mtu(struct net_device *dev, int new_mtu) |
|
1728 { |
|
1729 struct fe_priv *np = netdev_priv(dev); |
|
1730 int old_mtu; |
|
1731 |
|
1732 if (new_mtu < 64 || new_mtu > np->pkt_limit) |
|
1733 return -EINVAL; |
|
1734 |
|
1735 old_mtu = dev->mtu; |
|
1736 dev->mtu = new_mtu; |
|
1737 |
|
1738 /* return early if the buffer sizes will not change */ |
|
1739 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) |
|
1740 return 0; |
|
1741 if (old_mtu == new_mtu) |
|
1742 return 0; |
|
1743 |
|
1744 /* synchronized against open : rtnl_lock() held by caller */ |
|
1745 if (netif_running(dev)) { |
|
1746 u8 __iomem *base = get_hwbase(dev); |
|
1747 /* |
|
1748 * It seems that the nic preloads valid ring entries into an |
|
1749 * internal buffer. The procedure for flushing everything is |
|
1750 * guessed, there is probably a simpler approach. |
|
1751 * Changing the MTU is a rare event, it shouldn't matter. |
|
1752 */ |
|
1753 nv_disable_irq(dev); |
|
1754 spin_lock_bh(&dev->xmit_lock); |
|
1755 spin_lock(&np->lock); |
|
1756 /* stop engines */ |
|
1757 nv_stop_rx(dev); |
|
1758 nv_stop_tx(dev); |
|
1759 nv_txrx_reset(dev); |
|
1760 /* drain rx queue */ |
|
1761 nv_drain_rx(dev); |
|
1762 nv_drain_tx(dev); |
|
1763 /* reinit driver view of the rx queue */ |
|
1764 nv_init_rx(dev); |
|
1765 nv_init_tx(dev); |
|
1766 /* alloc new rx buffers */ |
|
1767 set_bufsize(dev); |
|
1768 if (nv_alloc_rx(dev)) { |
|
1769 if (!np->in_shutdown) |
|
1770 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
1771 } |
|
1772 /* reinit nic view of the rx queue */ |
|
1773 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
1774 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
1775 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
|
1776 base + NvRegRingSizes); |
|
1777 pci_push(base); |
|
1778 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
1779 pci_push(base); |
|
1780 |
|
1781 /* restart rx engine */ |
|
1782 nv_start_rx(dev); |
|
1783 nv_start_tx(dev); |
|
1784 spin_unlock(&np->lock); |
|
1785 spin_unlock_bh(&dev->xmit_lock); |
|
1786 nv_enable_irq(dev); |
|
1787 } |
|
1788 return 0; |
|
1789 } |
|
1790 |
|
1791 static void nv_copy_mac_to_hw(struct net_device *dev) |
|
1792 { |
|
1793 u8 __iomem *base = get_hwbase(dev); |
|
1794 u32 mac[2]; |
|
1795 |
|
1796 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
|
1797 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
|
1798 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
|
1799 |
|
1800 writel(mac[0], base + NvRegMacAddrA); |
|
1801 writel(mac[1], base + NvRegMacAddrB); |
|
1802 } |
|
1803 |
|
1804 /* |
|
1805 * nv_set_mac_address: dev->set_mac_address function |
|
1806 * Called with rtnl_lock() held. |
|
1807 */ |
|
1808 static int nv_set_mac_address(struct net_device *dev, void *addr) |
|
1809 { |
|
1810 struct fe_priv *np = netdev_priv(dev); |
|
1811 struct sockaddr *macaddr = (struct sockaddr*)addr; |
|
1812 |
|
1813 if(!is_valid_ether_addr(macaddr->sa_data)) |
|
1814 return -EADDRNOTAVAIL; |
|
1815 |
|
1816 /* synchronized against open : rtnl_lock() held by caller */ |
|
1817 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); |
|
1818 |
|
1819 if (netif_running(dev)) { |
|
1820 spin_lock_bh(&dev->xmit_lock); |
|
1821 spin_lock_irq(&np->lock); |
|
1822 |
|
1823 /* stop rx engine */ |
|
1824 nv_stop_rx(dev); |
|
1825 |
|
1826 /* set mac address */ |
|
1827 nv_copy_mac_to_hw(dev); |
|
1828 |
|
1829 /* restart rx engine */ |
|
1830 nv_start_rx(dev); |
|
1831 spin_unlock_irq(&np->lock); |
|
1832 spin_unlock_bh(&dev->xmit_lock); |
|
1833 } else { |
|
1834 nv_copy_mac_to_hw(dev); |
|
1835 } |
|
1836 return 0; |
|
1837 } |
|
1838 |
|
1839 /* |
|
1840 * nv_set_multicast: dev->set_multicast function |
|
1841 * Called with dev->xmit_lock held. |
|
1842 */ |
|
1843 static void nv_set_multicast(struct net_device *dev) |
|
1844 { |
|
1845 struct fe_priv *np = netdev_priv(dev); |
|
1846 u8 __iomem *base = get_hwbase(dev); |
|
1847 u32 addr[2]; |
|
1848 u32 mask[2]; |
|
1849 u32 pff; |
|
1850 |
|
1851 memset(addr, 0, sizeof(addr)); |
|
1852 memset(mask, 0, sizeof(mask)); |
|
1853 |
|
1854 if (dev->flags & IFF_PROMISC) { |
|
1855 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); |
|
1856 pff = NVREG_PFF_PROMISC; |
|
1857 } else { |
|
1858 pff = NVREG_PFF_MYADDR; |
|
1859 |
|
1860 if (dev->flags & IFF_ALLMULTI || dev->mc_list) { |
|
1861 u32 alwaysOff[2]; |
|
1862 u32 alwaysOn[2]; |
|
1863 |
|
1864 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; |
|
1865 if (dev->flags & IFF_ALLMULTI) { |
|
1866 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; |
|
1867 } else { |
|
1868 struct dev_mc_list *walk; |
|
1869 |
|
1870 walk = dev->mc_list; |
|
1871 while (walk != NULL) { |
|
1872 u32 a, b; |
|
1873 a = le32_to_cpu(*(u32 *) walk->dmi_addr); |
|
1874 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4])); |
|
1875 alwaysOn[0] &= a; |
|
1876 alwaysOff[0] &= ~a; |
|
1877 alwaysOn[1] &= b; |
|
1878 alwaysOff[1] &= ~b; |
|
1879 walk = walk->next; |
|
1880 } |
|
1881 } |
|
1882 addr[0] = alwaysOn[0]; |
|
1883 addr[1] = alwaysOn[1]; |
|
1884 mask[0] = alwaysOn[0] | alwaysOff[0]; |
|
1885 mask[1] = alwaysOn[1] | alwaysOff[1]; |
|
1886 } |
|
1887 } |
|
1888 addr[0] |= NVREG_MCASTADDRA_FORCE; |
|
1889 pff |= NVREG_PFF_ALWAYS; |
|
1890 spin_lock_irq(&np->lock); |
|
1891 nv_stop_rx(dev); |
|
1892 writel(addr[0], base + NvRegMulticastAddrA); |
|
1893 writel(addr[1], base + NvRegMulticastAddrB); |
|
1894 writel(mask[0], base + NvRegMulticastMaskA); |
|
1895 writel(mask[1], base + NvRegMulticastMaskB); |
|
1896 writel(pff, base + NvRegPacketFilterFlags); |
|
1897 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n", |
|
1898 dev->name); |
|
1899 nv_start_rx(dev); |
|
1900 spin_unlock_irq(&np->lock); |
|
1901 } |
|
1902 |
|
1903 /** |
|
1904 * nv_update_linkspeed: Setup the MAC according to the link partner |
|
1905 * @dev: Network device to be configured |
|
1906 * |
|
1907 * The function queries the PHY and checks if there is a link partner. |
|
1908 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is |
|
1909 * set to 10 MBit HD. |
|
1910 * |
|
1911 * The function returns 0 if there is no link partner and 1 if there is |
|
1912 * a good link partner. |
|
1913 */ |
|
1914 static int nv_update_linkspeed(struct net_device *dev) |
|
1915 { |
|
1916 struct fe_priv *np = netdev_priv(dev); |
|
1917 u8 __iomem *base = get_hwbase(dev); |
|
1918 int adv, lpa; |
|
1919 int newls = np->linkspeed; |
|
1920 int newdup = np->duplex; |
|
1921 int mii_status; |
|
1922 int retval = 0; |
|
1923 u32 control_1000, status_1000, phyreg; |
|
1924 |
|
1925 /* BMSR_LSTATUS is latched, read it twice: |
|
1926 * we want the current value. |
|
1927 */ |
|
1928 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
1929 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
|
1930 |
|
1931 if (!(mii_status & BMSR_LSTATUS)) { |
|
1932 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n", |
|
1933 dev->name); |
|
1934 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1935 newdup = 0; |
|
1936 retval = 0; |
|
1937 goto set_speed; |
|
1938 } |
|
1939 |
|
1940 if (np->autoneg == 0) { |
|
1941 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
|
1942 dev->name, np->fixed_mode); |
|
1943 if (np->fixed_mode & LPA_100FULL) { |
|
1944 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1945 newdup = 1; |
|
1946 } else if (np->fixed_mode & LPA_100HALF) { |
|
1947 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1948 newdup = 0; |
|
1949 } else if (np->fixed_mode & LPA_10FULL) { |
|
1950 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1951 newdup = 1; |
|
1952 } else { |
|
1953 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1954 newdup = 0; |
|
1955 } |
|
1956 retval = 1; |
|
1957 goto set_speed; |
|
1958 } |
|
1959 /* check auto negotiation is complete */ |
|
1960 if (!(mii_status & BMSR_ANEGCOMPLETE)) { |
|
1961 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ |
|
1962 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1963 newdup = 0; |
|
1964 retval = 0; |
|
1965 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name); |
|
1966 goto set_speed; |
|
1967 } |
|
1968 |
|
1969 retval = 1; |
|
1970 if (np->gigabit == PHY_GIGABIT) { |
|
1971 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
1972 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ); |
|
1973 |
|
1974 if ((control_1000 & ADVERTISE_1000FULL) && |
|
1975 (status_1000 & LPA_1000FULL)) { |
|
1976 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n", |
|
1977 dev->name); |
|
1978 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
|
1979 newdup = 1; |
|
1980 goto set_speed; |
|
1981 } |
|
1982 } |
|
1983 |
|
1984 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
1985 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
|
1986 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
|
1987 dev->name, adv, lpa); |
|
1988 |
|
1989 /* FIXME: handle parallel detection properly */ |
|
1990 lpa = lpa & adv; |
|
1991 if (lpa & LPA_100FULL) { |
|
1992 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1993 newdup = 1; |
|
1994 } else if (lpa & LPA_100HALF) { |
|
1995 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
|
1996 newdup = 0; |
|
1997 } else if (lpa & LPA_10FULL) { |
|
1998 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
1999 newdup = 1; |
|
2000 } else if (lpa & LPA_10HALF) { |
|
2001 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2002 newdup = 0; |
|
2003 } else { |
|
2004 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa); |
|
2005 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
2006 newdup = 0; |
|
2007 } |
|
2008 |
|
2009 set_speed: |
|
2010 if (np->duplex == newdup && np->linkspeed == newls) |
|
2011 return retval; |
|
2012 |
|
2013 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n", |
|
2014 dev->name, np->linkspeed, np->duplex, newls, newdup); |
|
2015 |
|
2016 np->duplex = newdup; |
|
2017 np->linkspeed = newls; |
|
2018 |
|
2019 if (np->gigabit == PHY_GIGABIT) { |
|
2020 phyreg = readl(base + NvRegRandomSeed); |
|
2021 phyreg &= ~(0x3FF00); |
|
2022 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) |
|
2023 phyreg |= NVREG_RNDSEED_FORCE3; |
|
2024 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) |
|
2025 phyreg |= NVREG_RNDSEED_FORCE2; |
|
2026 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
|
2027 phyreg |= NVREG_RNDSEED_FORCE; |
|
2028 writel(phyreg, base + NvRegRandomSeed); |
|
2029 } |
|
2030 |
|
2031 phyreg = readl(base + NvRegPhyInterface); |
|
2032 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); |
|
2033 if (np->duplex == 0) |
|
2034 phyreg |= PHY_HALF; |
|
2035 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) |
|
2036 phyreg |= PHY_100; |
|
2037 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) |
|
2038 phyreg |= PHY_1000; |
|
2039 writel(phyreg, base + NvRegPhyInterface); |
|
2040 |
|
2041 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
|
2042 base + NvRegMisc1); |
|
2043 pci_push(base); |
|
2044 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
2045 pci_push(base); |
|
2046 |
|
2047 return retval; |
|
2048 } |
|
2049 |
|
2050 static void nv_linkchange(struct net_device *dev) |
|
2051 { |
|
2052 struct fe_priv *np = netdev_priv(dev); |
|
2053 |
|
2054 if (np->ecdev) { |
|
2055 int link = nv_update_linkspeed(dev); |
|
2056 ecdev_set_link(np->ecdev, link); |
|
2057 return; |
|
2058 } |
|
2059 |
|
2060 if (nv_update_linkspeed(dev)) { |
|
2061 if (!netif_carrier_ok(dev)) { |
|
2062 netif_carrier_on(dev); |
|
2063 printk(KERN_INFO "%s: link up.\n", dev->name); |
|
2064 nv_start_rx(dev); |
|
2065 } |
|
2066 } else { |
|
2067 if (netif_carrier_ok(dev)) { |
|
2068 netif_carrier_off(dev); |
|
2069 printk(KERN_INFO "%s: link down.\n", dev->name); |
|
2070 nv_stop_rx(dev); |
|
2071 } |
|
2072 } |
|
2073 } |
|
2074 |
|
2075 static void nv_link_irq(struct net_device *dev) |
|
2076 { |
|
2077 u8 __iomem *base = get_hwbase(dev); |
|
2078 u32 miistat; |
|
2079 |
|
2080 miistat = readl(base + NvRegMIIStatus); |
|
2081 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
2082 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat); |
|
2083 |
|
2084 if (miistat & (NVREG_MIISTAT_LINKCHANGE)) |
|
2085 nv_linkchange(dev); |
|
2086 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name); |
|
2087 } |
|
2088 |
|
2089 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
|
2090 { |
|
2091 struct net_device *dev = (struct net_device *) data; |
|
2092 struct fe_priv *np = netdev_priv(dev); |
|
2093 u8 __iomem *base = get_hwbase(dev); |
|
2094 u32 events; |
|
2095 int i; |
|
2096 |
|
2097 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name); |
|
2098 |
|
2099 for (i=0; ; i++) { |
|
2100 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
|
2101 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2102 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2103 } else { |
|
2104 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
|
2105 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
|
2106 } |
|
2107 pci_push(base); |
|
2108 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2109 if (!(events & np->irqmask)) |
|
2110 break; |
|
2111 |
|
2112 if (!np->ecdev) spin_lock(&np->lock); |
|
2113 nv_tx_done(dev); |
|
2114 if (!np->ecdev) spin_unlock(&np->lock); |
|
2115 |
|
2116 nv_rx_process(dev); |
|
2117 if (nv_alloc_rx(dev)) { |
|
2118 spin_lock(&np->lock); |
|
2119 if (!np->in_shutdown) |
|
2120 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2121 spin_unlock(&np->lock); |
|
2122 } |
|
2123 |
|
2124 if (events & NVREG_IRQ_LINK) { |
|
2125 if (!np->ecdev) spin_lock(&np->lock); |
|
2126 nv_link_irq(dev); |
|
2127 if (!np->ecdev) spin_unlock(&np->lock); |
|
2128 } |
|
2129 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2130 if (!np->ecdev) spin_lock(&np->lock); |
|
2131 nv_linkchange(dev); |
|
2132 if (!np->ecdev) spin_unlock(&np->lock); |
|
2133 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2134 } |
|
2135 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2136 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2137 dev->name, events); |
|
2138 } |
|
2139 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2140 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2141 dev->name, events); |
|
2142 } |
|
2143 if (i > max_interrupt_work) { |
|
2144 if (!np->ecdev) { |
|
2145 spin_lock(&np->lock); |
|
2146 /* disable interrupts on the nic */ |
|
2147 if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
|
2148 writel(0, base + NvRegIrqMask); |
|
2149 else |
|
2150 writel(np->irqmask, base + NvRegIrqMask); |
|
2151 pci_push(base); |
|
2152 |
|
2153 if (!np->in_shutdown) { |
|
2154 np->nic_poll_irq = np->irqmask; |
|
2155 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2156 } |
|
2157 spin_unlock(&np->lock); |
|
2158 } |
|
2159 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i); |
|
2160 break; |
|
2161 } |
|
2162 |
|
2163 } |
|
2164 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name); |
|
2165 |
|
2166 return IRQ_RETVAL(i); |
|
2167 } |
|
2168 |
|
2169 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs) |
|
2170 { |
|
2171 struct net_device *dev = (struct net_device *) data; |
|
2172 struct fe_priv *np = netdev_priv(dev); |
|
2173 u8 __iomem *base = get_hwbase(dev); |
|
2174 u32 events; |
|
2175 int i; |
|
2176 |
|
2177 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name); |
|
2178 |
|
2179 for (i=0; ; i++) { |
|
2180 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
|
2181 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
|
2182 pci_push(base); |
|
2183 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
|
2184 if (!(events & np->irqmask)) |
|
2185 break; |
|
2186 |
|
2187 if (!np->ecdev) spin_lock_irq(&np->lock); |
|
2188 nv_tx_done(dev); |
|
2189 if (!np->ecdev) spin_unlock_irq(&np->lock); |
|
2190 |
|
2191 if (events & (NVREG_IRQ_TX_ERR)) { |
|
2192 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
|
2193 dev->name, events); |
|
2194 } |
|
2195 if (i > max_interrupt_work) { |
|
2196 if (!np->ecdev) { |
|
2197 spin_lock_irq(&np->lock); |
|
2198 /* disable interrupts on the nic */ |
|
2199 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); |
|
2200 pci_push(base); |
|
2201 |
|
2202 if (!np->in_shutdown) { |
|
2203 np->nic_poll_irq |= NVREG_IRQ_TX_ALL; |
|
2204 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2205 } |
|
2206 spin_unlock_irq(&np->lock); |
|
2207 } |
|
2208 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i); |
|
2209 break; |
|
2210 } |
|
2211 |
|
2212 } |
|
2213 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name); |
|
2214 |
|
2215 return IRQ_RETVAL(i); |
|
2216 } |
|
2217 |
|
2218 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) |
|
2219 { |
|
2220 struct net_device *dev = (struct net_device *) data; |
|
2221 struct fe_priv *np = netdev_priv(dev); |
|
2222 u8 __iomem *base = get_hwbase(dev); |
|
2223 u32 events; |
|
2224 int i; |
|
2225 |
|
2226 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name); |
|
2227 |
|
2228 for (i=0; ; i++) { |
|
2229 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
|
2230 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
|
2231 pci_push(base); |
|
2232 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
|
2233 if (!(events & np->irqmask)) |
|
2234 break; |
|
2235 |
|
2236 nv_rx_process(dev); |
|
2237 if (nv_alloc_rx(dev) && !np->ecdev) { |
|
2238 spin_lock_irq(&np->lock); |
|
2239 if (!np->in_shutdown) |
|
2240 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
2241 spin_unlock_irq(&np->lock); |
|
2242 } |
|
2243 |
|
2244 if (i > max_interrupt_work) { |
|
2245 if (!np->ecdev) { |
|
2246 spin_lock_irq(&np->lock); |
|
2247 /* disable interrupts on the nic */ |
|
2248 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); |
|
2249 pci_push(base); |
|
2250 |
|
2251 if (!np->in_shutdown) { |
|
2252 np->nic_poll_irq |= NVREG_IRQ_RX_ALL; |
|
2253 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2254 } |
|
2255 spin_unlock_irq(&np->lock); |
|
2256 } |
|
2257 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i); |
|
2258 break; |
|
2259 } |
|
2260 |
|
2261 } |
|
2262 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name); |
|
2263 |
|
2264 return IRQ_RETVAL(i); |
|
2265 } |
|
2266 |
|
2267 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) |
|
2268 { |
|
2269 struct net_device *dev = (struct net_device *) data; |
|
2270 struct fe_priv *np = netdev_priv(dev); |
|
2271 u8 __iomem *base = get_hwbase(dev); |
|
2272 u32 events; |
|
2273 int i; |
|
2274 |
|
2275 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name); |
|
2276 |
|
2277 for (i=0; ; i++) { |
|
2278 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
|
2279 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
|
2280 pci_push(base); |
|
2281 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
|
2282 if (!(events & np->irqmask)) |
|
2283 break; |
|
2284 |
|
2285 if (events & NVREG_IRQ_LINK) { |
|
2286 if (!np->ecdev) spin_lock_irq(&np->lock); |
|
2287 nv_link_irq(dev); |
|
2288 if (!np->ecdev) spin_unlock_irq(&np->lock); |
|
2289 } |
|
2290 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { |
|
2291 if (!np->ecdev) spin_lock_irq(&np->lock); |
|
2292 nv_linkchange(dev); |
|
2293 if (!np->ecdev) spin_unlock_irq(&np->lock); |
|
2294 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
2295 } |
|
2296 if (events & (NVREG_IRQ_UNKNOWN)) { |
|
2297 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
|
2298 dev->name, events); |
|
2299 } |
|
2300 if (i > max_interrupt_work) { |
|
2301 if (!np->ecdev) { |
|
2302 spin_lock_irq(&np->lock); |
|
2303 /* disable interrupts on the nic */ |
|
2304 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); |
|
2305 pci_push(base); |
|
2306 |
|
2307 if (!np->in_shutdown) { |
|
2308 np->nic_poll_irq |= NVREG_IRQ_OTHER; |
|
2309 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
|
2310 } |
|
2311 spin_unlock_irq(&np->lock); |
|
2312 } |
|
2313 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i); |
|
2314 break; |
|
2315 } |
|
2316 |
|
2317 } |
|
2318 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name); |
|
2319 |
|
2320 return IRQ_RETVAL(i); |
|
2321 } |
|
2322 |
|
2323 void ec_poll(struct net_device *dev) |
|
2324 { |
|
2325 struct fe_priv *np = netdev_priv(dev); |
|
2326 |
|
2327 if (!using_multi_irqs(dev)) { |
|
2328 nv_nic_irq((int) 0, dev, (struct pt_regs *) NULL); |
|
2329 } else { |
|
2330 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2331 nv_nic_irq_rx((int) 0, dev, (struct pt_regs *) NULL); |
|
2332 } |
|
2333 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2334 nv_nic_irq_tx((int) 0, dev, (struct pt_regs *) NULL); |
|
2335 } |
|
2336 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2337 nv_nic_irq_other((int) 0, dev, (struct pt_regs *) NULL); |
|
2338 } |
|
2339 } |
|
2340 } |
|
2341 |
|
2342 static void nv_do_nic_poll(unsigned long data) |
|
2343 { |
|
2344 struct net_device *dev = (struct net_device *) data; |
|
2345 struct fe_priv *np = netdev_priv(dev); |
|
2346 u8 __iomem *base = get_hwbase(dev); |
|
2347 u32 mask = 0; |
|
2348 |
|
2349 /* |
|
2350 * First disable irq(s) and then |
|
2351 * reenable interrupts on the nic, we have to do this before calling |
|
2352 * nv_nic_irq because that may decide to do otherwise |
|
2353 */ |
|
2354 |
|
2355 if (!using_multi_irqs(dev)) { |
|
2356 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2357 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2358 else |
|
2359 disable_irq(dev->irq); |
|
2360 mask = np->irqmask; |
|
2361 } else { |
|
2362 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2363 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2364 mask |= NVREG_IRQ_RX_ALL; |
|
2365 } |
|
2366 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2367 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2368 mask |= NVREG_IRQ_TX_ALL; |
|
2369 } |
|
2370 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2371 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2372 mask |= NVREG_IRQ_OTHER; |
|
2373 } |
|
2374 } |
|
2375 np->nic_poll_irq = 0; |
|
2376 |
|
2377 /* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
|
2378 |
|
2379 writel(mask, base + NvRegIrqMask); |
|
2380 pci_push(base); |
|
2381 |
|
2382 if (!using_multi_irqs(dev)) { |
|
2383 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2384 if (np->msi_flags & NV_MSI_X_ENABLED) |
|
2385 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
|
2386 else |
|
2387 enable_irq(dev->irq); |
|
2388 } else { |
|
2389 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
|
2390 nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2391 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
|
2392 } |
|
2393 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
|
2394 nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2395 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
|
2396 } |
|
2397 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
|
2398 nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL); |
|
2399 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
|
2400 } |
|
2401 } |
|
2402 } |
|
2403 |
|
2404 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
2405 static void nv_poll_controller(struct net_device *dev) |
|
2406 { |
|
2407 nv_do_nic_poll((unsigned long) dev); |
|
2408 } |
|
2409 #endif |
|
2410 |
|
2411 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
|
2412 { |
|
2413 struct fe_priv *np = netdev_priv(dev); |
|
2414 strcpy(info->driver, "forcedeth"); |
|
2415 strcpy(info->version, FORCEDETH_VERSION); |
|
2416 strcpy(info->bus_info, pci_name(np->pci_dev)); |
|
2417 } |
|
2418 |
|
2419 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
2420 { |
|
2421 struct fe_priv *np = netdev_priv(dev); |
|
2422 wolinfo->supported = WAKE_MAGIC; |
|
2423 |
|
2424 spin_lock_irq(&np->lock); |
|
2425 if (np->wolenabled) |
|
2426 wolinfo->wolopts = WAKE_MAGIC; |
|
2427 spin_unlock_irq(&np->lock); |
|
2428 } |
|
2429 |
|
2430 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
|
2431 { |
|
2432 struct fe_priv *np = netdev_priv(dev); |
|
2433 u8 __iomem *base = get_hwbase(dev); |
|
2434 |
|
2435 spin_lock_irq(&np->lock); |
|
2436 if (wolinfo->wolopts == 0) { |
|
2437 writel(0, base + NvRegWakeUpFlags); |
|
2438 np->wolenabled = 0; |
|
2439 } |
|
2440 if (wolinfo->wolopts & WAKE_MAGIC) { |
|
2441 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags); |
|
2442 np->wolenabled = 1; |
|
2443 } |
|
2444 spin_unlock_irq(&np->lock); |
|
2445 return 0; |
|
2446 } |
|
2447 |
|
2448 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
2449 { |
|
2450 struct fe_priv *np = netdev_priv(dev); |
|
2451 int adv; |
|
2452 |
|
2453 spin_lock_irq(&np->lock); |
|
2454 ecmd->port = PORT_MII; |
|
2455 if (!netif_running(dev)) { |
|
2456 /* We do not track link speed / duplex setting if the |
|
2457 * interface is disabled. Force a link check */ |
|
2458 nv_update_linkspeed(dev); |
|
2459 } |
|
2460 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
|
2461 case NVREG_LINKSPEED_10: |
|
2462 ecmd->speed = SPEED_10; |
|
2463 break; |
|
2464 case NVREG_LINKSPEED_100: |
|
2465 ecmd->speed = SPEED_100; |
|
2466 break; |
|
2467 case NVREG_LINKSPEED_1000: |
|
2468 ecmd->speed = SPEED_1000; |
|
2469 break; |
|
2470 } |
|
2471 ecmd->duplex = DUPLEX_HALF; |
|
2472 if (np->duplex) |
|
2473 ecmd->duplex = DUPLEX_FULL; |
|
2474 |
|
2475 ecmd->autoneg = np->autoneg; |
|
2476 |
|
2477 ecmd->advertising = ADVERTISED_MII; |
|
2478 if (np->autoneg) { |
|
2479 ecmd->advertising |= ADVERTISED_Autoneg; |
|
2480 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2481 } else { |
|
2482 adv = np->fixed_mode; |
|
2483 } |
|
2484 if (adv & ADVERTISE_10HALF) |
|
2485 ecmd->advertising |= ADVERTISED_10baseT_Half; |
|
2486 if (adv & ADVERTISE_10FULL) |
|
2487 ecmd->advertising |= ADVERTISED_10baseT_Full; |
|
2488 if (adv & ADVERTISE_100HALF) |
|
2489 ecmd->advertising |= ADVERTISED_100baseT_Half; |
|
2490 if (adv & ADVERTISE_100FULL) |
|
2491 ecmd->advertising |= ADVERTISED_100baseT_Full; |
|
2492 if (np->autoneg && np->gigabit == PHY_GIGABIT) { |
|
2493 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2494 if (adv & ADVERTISE_1000FULL) |
|
2495 ecmd->advertising |= ADVERTISED_1000baseT_Full; |
|
2496 } |
|
2497 |
|
2498 ecmd->supported = (SUPPORTED_Autoneg | |
|
2499 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
|
2500 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | |
|
2501 SUPPORTED_MII); |
|
2502 if (np->gigabit == PHY_GIGABIT) |
|
2503 ecmd->supported |= SUPPORTED_1000baseT_Full; |
|
2504 |
|
2505 ecmd->phy_address = np->phyaddr; |
|
2506 ecmd->transceiver = XCVR_EXTERNAL; |
|
2507 |
|
2508 /* ignore maxtxpkt, maxrxpkt for now */ |
|
2509 spin_unlock_irq(&np->lock); |
|
2510 return 0; |
|
2511 } |
|
2512 |
|
2513 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
|
2514 { |
|
2515 struct fe_priv *np = netdev_priv(dev); |
|
2516 |
|
2517 if (ecmd->port != PORT_MII) |
|
2518 return -EINVAL; |
|
2519 if (ecmd->transceiver != XCVR_EXTERNAL) |
|
2520 return -EINVAL; |
|
2521 if (ecmd->phy_address != np->phyaddr) { |
|
2522 /* TODO: support switching between multiple phys. Should be |
|
2523 * trivial, but not enabled due to lack of test hardware. */ |
|
2524 return -EINVAL; |
|
2525 } |
|
2526 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
2527 u32 mask; |
|
2528 |
|
2529 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
2530 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; |
|
2531 if (np->gigabit == PHY_GIGABIT) |
|
2532 mask |= ADVERTISED_1000baseT_Full; |
|
2533 |
|
2534 if ((ecmd->advertising & mask) == 0) |
|
2535 return -EINVAL; |
|
2536 |
|
2537 } else if (ecmd->autoneg == AUTONEG_DISABLE) { |
|
2538 /* Note: autonegotiation disable, speed 1000 intentionally |
|
2539 * forbidden - noone should need that. */ |
|
2540 |
|
2541 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) |
|
2542 return -EINVAL; |
|
2543 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) |
|
2544 return -EINVAL; |
|
2545 } else { |
|
2546 return -EINVAL; |
|
2547 } |
|
2548 |
|
2549 spin_lock_irq(&np->lock); |
|
2550 if (ecmd->autoneg == AUTONEG_ENABLE) { |
|
2551 int adv, bmcr; |
|
2552 |
|
2553 np->autoneg = 1; |
|
2554 |
|
2555 /* advertise only what has been requested */ |
|
2556 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2557 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
|
2558 if (ecmd->advertising & ADVERTISED_10baseT_Half) |
|
2559 adv |= ADVERTISE_10HALF; |
|
2560 if (ecmd->advertising & ADVERTISED_10baseT_Full) |
|
2561 adv |= ADVERTISE_10FULL; |
|
2562 if (ecmd->advertising & ADVERTISED_100baseT_Half) |
|
2563 adv |= ADVERTISE_100HALF; |
|
2564 if (ecmd->advertising & ADVERTISED_100baseT_Full) |
|
2565 adv |= ADVERTISE_100FULL; |
|
2566 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
2567 |
|
2568 if (np->gigabit == PHY_GIGABIT) { |
|
2569 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2570 adv &= ~ADVERTISE_1000FULL; |
|
2571 if (ecmd->advertising & ADVERTISED_1000baseT_Full) |
|
2572 adv |= ADVERTISE_1000FULL; |
|
2573 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
|
2574 } |
|
2575 |
|
2576 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2577 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
2578 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2579 |
|
2580 } else { |
|
2581 int adv, bmcr; |
|
2582 |
|
2583 np->autoneg = 0; |
|
2584 |
|
2585 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
|
2586 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); |
|
2587 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF) |
|
2588 adv |= ADVERTISE_10HALF; |
|
2589 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL) |
|
2590 adv |= ADVERTISE_10FULL; |
|
2591 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF) |
|
2592 adv |= ADVERTISE_100HALF; |
|
2593 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL) |
|
2594 adv |= ADVERTISE_100FULL; |
|
2595 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
|
2596 np->fixed_mode = adv; |
|
2597 |
|
2598 if (np->gigabit == PHY_GIGABIT) { |
|
2599 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ); |
|
2600 adv &= ~ADVERTISE_1000FULL; |
|
2601 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv); |
|
2602 } |
|
2603 |
|
2604 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2605 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX); |
|
2606 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL)) |
|
2607 bmcr |= BMCR_FULLDPLX; |
|
2608 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
|
2609 bmcr |= BMCR_SPEED100; |
|
2610 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2611 |
|
2612 if (netif_running(dev)) { |
|
2613 /* Wait a bit and then reconfigure the nic. */ |
|
2614 udelay(10); |
|
2615 nv_linkchange(dev); |
|
2616 } |
|
2617 } |
|
2618 spin_unlock_irq(&np->lock); |
|
2619 |
|
2620 return 0; |
|
2621 } |
|
2622 |
|
2623 #define FORCEDETH_REGS_VER 1 |
|
2624 |
|
2625 static int nv_get_regs_len(struct net_device *dev) |
|
2626 { |
|
2627 struct fe_priv *np = netdev_priv(dev); |
|
2628 return np->register_size; |
|
2629 } |
|
2630 |
|
2631 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
|
2632 { |
|
2633 struct fe_priv *np = netdev_priv(dev); |
|
2634 u8 __iomem *base = get_hwbase(dev); |
|
2635 u32 *rbuf = buf; |
|
2636 int i; |
|
2637 |
|
2638 regs->version = FORCEDETH_REGS_VER; |
|
2639 spin_lock_irq(&np->lock); |
|
2640 for (i = 0;i <= np->register_size/sizeof(u32); i++) |
|
2641 rbuf[i] = readl(base + i*sizeof(u32)); |
|
2642 spin_unlock_irq(&np->lock); |
|
2643 } |
|
2644 |
|
2645 static int nv_nway_reset(struct net_device *dev) |
|
2646 { |
|
2647 struct fe_priv *np = netdev_priv(dev); |
|
2648 int ret; |
|
2649 |
|
2650 spin_lock_irq(&np->lock); |
|
2651 if (np->autoneg) { |
|
2652 int bmcr; |
|
2653 |
|
2654 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
2655 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
|
2656 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
2657 |
|
2658 ret = 0; |
|
2659 } else { |
|
2660 ret = -EINVAL; |
|
2661 } |
|
2662 spin_unlock_irq(&np->lock); |
|
2663 |
|
2664 return ret; |
|
2665 } |
|
2666 |
|
2667 #ifdef NETIF_F_TSO |
|
2668 static int nv_set_tso(struct net_device *dev, u32 value) |
|
2669 { |
|
2670 struct fe_priv *np = netdev_priv(dev); |
|
2671 |
|
2672 if ((np->driver_data & DEV_HAS_CHECKSUM)) |
|
2673 return ethtool_op_set_tso(dev, value); |
|
2674 else |
|
2675 return value ? -EOPNOTSUPP : 0; |
|
2676 } |
|
2677 #endif |
|
2678 |
|
2679 static struct ethtool_ops ops = { |
|
2680 .get_drvinfo = nv_get_drvinfo, |
|
2681 .get_link = ethtool_op_get_link, |
|
2682 .get_wol = nv_get_wol, |
|
2683 .set_wol = nv_set_wol, |
|
2684 .get_settings = nv_get_settings, |
|
2685 .set_settings = nv_set_settings, |
|
2686 .get_regs_len = nv_get_regs_len, |
|
2687 .get_regs = nv_get_regs, |
|
2688 .nway_reset = nv_nway_reset, |
|
2689 .get_perm_addr = ethtool_op_get_perm_addr, |
|
2690 #ifdef NETIF_F_TSO |
|
2691 .get_tso = ethtool_op_get_tso, |
|
2692 .set_tso = nv_set_tso |
|
2693 #endif |
|
2694 }; |
|
2695 |
|
2696 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) |
|
2697 { |
|
2698 struct fe_priv *np = get_nvpriv(dev); |
|
2699 |
|
2700 spin_lock_irq(&np->lock); |
|
2701 |
|
2702 /* save vlan group */ |
|
2703 np->vlangrp = grp; |
|
2704 |
|
2705 if (grp) { |
|
2706 /* enable vlan on MAC */ |
|
2707 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; |
|
2708 } else { |
|
2709 /* disable vlan on MAC */ |
|
2710 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; |
|
2711 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; |
|
2712 } |
|
2713 |
|
2714 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
|
2715 |
|
2716 spin_unlock_irq(&np->lock); |
|
2717 }; |
|
2718 |
|
2719 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) |
|
2720 { |
|
2721 /* nothing to do */ |
|
2722 }; |
|
2723 |
|
2724 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
|
2725 { |
|
2726 u8 __iomem *base = get_hwbase(dev); |
|
2727 int i; |
|
2728 u32 msixmap = 0; |
|
2729 |
|
2730 /* Each interrupt bit can be mapped to a MSIX vector (4 bits). |
|
2731 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents |
|
2732 * the remaining 8 interrupts. |
|
2733 */ |
|
2734 for (i = 0; i < 8; i++) { |
|
2735 if ((irqmask >> i) & 0x1) { |
|
2736 msixmap |= vector << (i << 2); |
|
2737 } |
|
2738 } |
|
2739 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); |
|
2740 |
|
2741 msixmap = 0; |
|
2742 for (i = 0; i < 8; i++) { |
|
2743 if ((irqmask >> (i + 8)) & 0x1) { |
|
2744 msixmap |= vector << (i << 2); |
|
2745 } |
|
2746 } |
|
2747 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
|
2748 } |
|
2749 |
|
2750 static int nv_request_irq(struct net_device *dev) |
|
2751 { |
|
2752 struct fe_priv *np = get_nvpriv(dev); |
|
2753 u8 __iomem *base = get_hwbase(dev); |
|
2754 int ret = 1; |
|
2755 int i; |
|
2756 |
|
2757 if (np->msi_flags & NV_MSI_X_CAPABLE) { |
|
2758 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2759 np->msi_x_entry[i].entry = i; |
|
2760 } |
|
2761 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) { |
|
2762 np->msi_flags |= NV_MSI_X_ENABLED; |
|
2763 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
|
2764 /* Request irq for rx handling */ |
|
2765 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) { |
|
2766 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
|
2767 pci_disable_msix(np->pci_dev); |
|
2768 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2769 goto out_err; |
|
2770 } |
|
2771 /* Request irq for tx handling */ |
|
2772 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) { |
|
2773 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
|
2774 pci_disable_msix(np->pci_dev); |
|
2775 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2776 goto out_free_rx; |
|
2777 } |
|
2778 /* Request irq for link and timer handling */ |
|
2779 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) { |
|
2780 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
|
2781 pci_disable_msix(np->pci_dev); |
|
2782 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2783 goto out_free_tx; |
|
2784 } |
|
2785 /* map interrupts to their respective vector */ |
|
2786 writel(0, base + NvRegMSIXMap0); |
|
2787 writel(0, base + NvRegMSIXMap1); |
|
2788 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
|
2789 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
|
2790 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
|
2791 } else { |
|
2792 /* Request irq for all interrupts */ |
|
2793 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { |
|
2794 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2795 pci_disable_msix(np->pci_dev); |
|
2796 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2797 goto out_err; |
|
2798 } |
|
2799 |
|
2800 /* map interrupts to vector 0 */ |
|
2801 writel(0, base + NvRegMSIXMap0); |
|
2802 writel(0, base + NvRegMSIXMap1); |
|
2803 } |
|
2804 } |
|
2805 } |
|
2806 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
|
2807 if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
|
2808 np->msi_flags |= NV_MSI_ENABLED; |
|
2809 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) { |
|
2810 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
|
2811 pci_disable_msi(np->pci_dev); |
|
2812 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2813 goto out_err; |
|
2814 } |
|
2815 |
|
2816 /* map interrupts to vector 0 */ |
|
2817 writel(0, base + NvRegMSIMap0); |
|
2818 writel(0, base + NvRegMSIMap1); |
|
2819 /* enable msi vector 0 */ |
|
2820 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
|
2821 } |
|
2822 } |
|
2823 if (ret != 0) { |
|
2824 if (request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) |
|
2825 goto out_err; |
|
2826 } |
|
2827 |
|
2828 return 0; |
|
2829 out_free_tx: |
|
2830 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
|
2831 out_free_rx: |
|
2832 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
|
2833 out_err: |
|
2834 return 1; |
|
2835 } |
|
2836 |
|
2837 static void nv_free_irq(struct net_device *dev) |
|
2838 { |
|
2839 struct fe_priv *np = get_nvpriv(dev); |
|
2840 int i; |
|
2841 |
|
2842 if (np->msi_flags & NV_MSI_X_ENABLED) { |
|
2843 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
|
2844 free_irq(np->msi_x_entry[i].vector, dev); |
|
2845 } |
|
2846 pci_disable_msix(np->pci_dev); |
|
2847 np->msi_flags &= ~NV_MSI_X_ENABLED; |
|
2848 } else { |
|
2849 free_irq(np->pci_dev->irq, dev); |
|
2850 if (np->msi_flags & NV_MSI_ENABLED) { |
|
2851 pci_disable_msi(np->pci_dev); |
|
2852 np->msi_flags &= ~NV_MSI_ENABLED; |
|
2853 } |
|
2854 } |
|
2855 } |
|
2856 |
|
2857 static int nv_open(struct net_device *dev) |
|
2858 { |
|
2859 struct fe_priv *np = netdev_priv(dev); |
|
2860 u8 __iomem *base = get_hwbase(dev); |
|
2861 int ret = 1; |
|
2862 int oom, i; |
|
2863 |
|
2864 dprintk(KERN_DEBUG "nv_open: begin\n"); |
|
2865 |
|
2866 /* 1) erase previous misconfiguration */ |
|
2867 if (np->driver_data & DEV_HAS_POWER_CNTRL) |
|
2868 nv_mac_reset(dev); |
|
2869 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ |
|
2870 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
2871 writel(0, base + NvRegMulticastAddrB); |
|
2872 writel(0, base + NvRegMulticastMaskA); |
|
2873 writel(0, base + NvRegMulticastMaskB); |
|
2874 writel(0, base + NvRegPacketFilterFlags); |
|
2875 |
|
2876 writel(0, base + NvRegTransmitterControl); |
|
2877 writel(0, base + NvRegReceiverControl); |
|
2878 |
|
2879 writel(0, base + NvRegAdapterControl); |
|
2880 |
|
2881 /* 2) initialize descriptor rings */ |
|
2882 set_bufsize(dev); |
|
2883 oom = nv_init_ring(dev); |
|
2884 |
|
2885 writel(0, base + NvRegLinkSpeed); |
|
2886 writel(0, base + NvRegUnknownTransmitterReg); |
|
2887 nv_txrx_reset(dev); |
|
2888 writel(0, base + NvRegUnknownSetupReg6); |
|
2889 |
|
2890 np->in_shutdown = 0; |
|
2891 |
|
2892 /* 3) set mac address */ |
|
2893 nv_copy_mac_to_hw(dev); |
|
2894 |
|
2895 /* 4) give hw rings */ |
|
2896 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
|
2897 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT), |
|
2898 base + NvRegRingSizes); |
|
2899 |
|
2900 /* 5) continue setup */ |
|
2901 writel(np->linkspeed, base + NvRegLinkSpeed); |
|
2902 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3); |
|
2903 writel(np->txrxctl_bits, base + NvRegTxRxControl); |
|
2904 writel(np->vlanctl_bits, base + NvRegVlanControl); |
|
2905 pci_push(base); |
|
2906 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
|
2907 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, |
|
2908 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
|
2909 KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
|
2910 |
|
2911 writel(0, base + NvRegUnknownSetupReg4); |
|
2912 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2913 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
2914 |
|
2915 /* 6) continue setup */ |
|
2916 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
|
2917 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
|
2918 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
|
2919 writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
|
2920 |
|
2921 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); |
|
2922 get_random_bytes(&i, sizeof(i)); |
|
2923 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); |
|
2924 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); |
|
2925 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); |
|
2926 if (poll_interval == -1) { |
|
2927 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) |
|
2928 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); |
|
2929 else |
|
2930 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); |
|
2931 } |
|
2932 else |
|
2933 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
|
2934 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
|
2935 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
|
2936 base + NvRegAdapterControl); |
|
2937 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
|
2938 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); |
|
2939 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags); |
|
2940 |
|
2941 i = readl(base + NvRegPowerState); |
|
2942 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) |
|
2943 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
|
2944 |
|
2945 pci_push(base); |
|
2946 udelay(10); |
|
2947 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); |
|
2948 |
|
2949 nv_disable_hw_interrupts(dev, np->irqmask); |
|
2950 pci_push(base); |
|
2951 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
|
2952 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
|
2953 pci_push(base); |
|
2954 |
|
2955 if (!np->ecdev) { |
|
2956 if (nv_request_irq(dev)) { |
|
2957 goto out_drain; |
|
2958 } |
|
2959 |
|
2960 /* ask for interrupts */ |
|
2961 nv_enable_hw_interrupts(dev, np->irqmask); |
|
2962 |
|
2963 spin_lock_irq(&np->lock); |
|
2964 } |
|
2965 |
|
2966 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
|
2967 writel(0, base + NvRegMulticastAddrB); |
|
2968 writel(0, base + NvRegMulticastMaskA); |
|
2969 writel(0, base + NvRegMulticastMaskB); |
|
2970 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
|
2971 /* One manual link speed update: Interrupts are enabled, future link |
|
2972 * speed changes cause interrupts and are handled by nv_link_irq(). |
|
2973 */ |
|
2974 { |
|
2975 u32 miistat; |
|
2976 miistat = readl(base + NvRegMIIStatus); |
|
2977 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
|
2978 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat); |
|
2979 } |
|
2980 /* set linkspeed to invalid value, thus force nv_update_linkspeed |
|
2981 * to init hw */ |
|
2982 np->linkspeed = 0; |
|
2983 ret = nv_update_linkspeed(dev); |
|
2984 nv_start_rx(dev); |
|
2985 nv_start_tx(dev); |
|
2986 |
|
2987 if (np->ecdev) { |
|
2988 ecdev_set_link(np->ecdev, ret); |
|
2989 } |
|
2990 else { |
|
2991 netif_start_queue(dev); |
|
2992 if (ret) { |
|
2993 netif_carrier_on(dev); |
|
2994 } else { |
|
2995 printk("%s: no link during initialization.\n", dev->name); |
|
2996 netif_carrier_off(dev); |
|
2997 } |
|
2998 if (oom) |
|
2999 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
|
3000 spin_unlock_irq(&np->lock); |
|
3001 } |
|
3002 |
|
3003 return 0; |
|
3004 out_drain: |
|
3005 drain_ring(dev); |
|
3006 return ret; |
|
3007 } |
|
3008 |
|
3009 static int nv_close(struct net_device *dev) |
|
3010 { |
|
3011 struct fe_priv *np = netdev_priv(dev); |
|
3012 u8 __iomem *base; |
|
3013 |
|
3014 if (!np->ecdev) { |
|
3015 spin_lock_irq(&np->lock); |
|
3016 np->in_shutdown = 1; |
|
3017 spin_unlock_irq(&np->lock); |
|
3018 synchronize_irq(dev->irq); |
|
3019 |
|
3020 del_timer_sync(&np->oom_kick); |
|
3021 del_timer_sync(&np->nic_poll); |
|
3022 |
|
3023 netif_stop_queue(dev); |
|
3024 spin_lock_irq(&np->lock); |
|
3025 } |
|
3026 |
|
3027 nv_stop_tx(dev); |
|
3028 nv_stop_rx(dev); |
|
3029 nv_txrx_reset(dev); |
|
3030 |
|
3031 base = get_hwbase(dev); |
|
3032 |
|
3033 if (!np->ecdev) { |
|
3034 /* disable interrupts on the nic or we will lock up */ |
|
3035 nv_disable_hw_interrupts(dev, np->irqmask); |
|
3036 pci_push(base); |
|
3037 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name); |
|
3038 |
|
3039 spin_unlock_irq(&np->lock); |
|
3040 |
|
3041 nv_free_irq(dev); |
|
3042 } |
|
3043 |
|
3044 drain_ring(dev); |
|
3045 |
|
3046 if (np->wolenabled) |
|
3047 nv_start_rx(dev); |
|
3048 |
|
3049 /* special op: write back the misordered MAC address - otherwise |
|
3050 * the next nv_probe would see a wrong address. |
|
3051 */ |
|
3052 writel(np->orig_mac[0], base + NvRegMacAddrA); |
|
3053 writel(np->orig_mac[1], base + NvRegMacAddrB); |
|
3054 |
|
3055 /* FIXME: power down nic */ |
|
3056 |
|
3057 return 0; |
|
3058 } |
|
3059 |
|
3060 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
|
3061 { |
|
3062 struct net_device *dev; |
|
3063 struct fe_priv *np; |
|
3064 unsigned long addr; |
|
3065 u8 __iomem *base; |
|
3066 int err, i; |
|
3067 u32 powerstate; |
|
3068 |
|
3069 board_idx++; |
|
3070 |
|
3071 dev = alloc_etherdev(sizeof(struct fe_priv)); |
|
3072 err = -ENOMEM; |
|
3073 if (!dev) |
|
3074 goto out; |
|
3075 |
|
3076 np = netdev_priv(dev); |
|
3077 np->pci_dev = pci_dev; |
|
3078 spin_lock_init(&np->lock); |
|
3079 SET_MODULE_OWNER(dev); |
|
3080 SET_NETDEV_DEV(dev, &pci_dev->dev); |
|
3081 |
|
3082 init_timer(&np->oom_kick); |
|
3083 np->oom_kick.data = (unsigned long) dev; |
|
3084 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */ |
|
3085 init_timer(&np->nic_poll); |
|
3086 np->nic_poll.data = (unsigned long) dev; |
|
3087 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */ |
|
3088 |
|
3089 err = pci_enable_device(pci_dev); |
|
3090 if (err) { |
|
3091 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n", |
|
3092 err, pci_name(pci_dev)); |
|
3093 goto out_free; |
|
3094 } |
|
3095 |
|
3096 pci_set_master(pci_dev); |
|
3097 |
|
3098 err = pci_request_regions(pci_dev, DRV_NAME); |
|
3099 if (err < 0) |
|
3100 goto out_disable; |
|
3101 |
|
3102 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL)) |
|
3103 np->register_size = NV_PCI_REGSZ_VER2; |
|
3104 else |
|
3105 np->register_size = NV_PCI_REGSZ_VER1; |
|
3106 |
|
3107 err = -EINVAL; |
|
3108 addr = 0; |
|
3109 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
|
3110 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n", |
|
3111 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i), |
|
3112 pci_resource_len(pci_dev, i), |
|
3113 pci_resource_flags(pci_dev, i)); |
|
3114 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
|
3115 pci_resource_len(pci_dev, i) >= np->register_size) { |
|
3116 addr = pci_resource_start(pci_dev, i); |
|
3117 break; |
|
3118 } |
|
3119 } |
|
3120 if (i == DEVICE_COUNT_RESOURCE) { |
|
3121 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n", |
|
3122 pci_name(pci_dev)); |
|
3123 goto out_relreg; |
|
3124 } |
|
3125 |
|
3126 /* copy of driver data */ |
|
3127 np->driver_data = id->driver_data; |
|
3128 |
|
3129 /* handle different descriptor versions */ |
|
3130 if (id->driver_data & DEV_HAS_HIGH_DMA) { |
|
3131 /* packet format 3: supports 40-bit addressing */ |
|
3132 np->desc_ver = DESC_VER_3; |
|
3133 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
|
3134 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
|
3135 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n", |
|
3136 pci_name(pci_dev)); |
|
3137 } else { |
|
3138 dev->features |= NETIF_F_HIGHDMA; |
|
3139 printk(KERN_INFO "forcedeth: using HIGHDMA\n"); |
|
3140 } |
|
3141 if (pci_set_consistent_dma_mask(pci_dev, 0x0000007fffffffffULL)) { |
|
3142 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed for device %s.\n", |
|
3143 pci_name(pci_dev)); |
|
3144 } |
|
3145 } else if (id->driver_data & DEV_HAS_LARGEDESC) { |
|
3146 /* packet format 2: supports jumbo frames */ |
|
3147 np->desc_ver = DESC_VER_2; |
|
3148 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
|
3149 } else { |
|
3150 /* original packet format */ |
|
3151 np->desc_ver = DESC_VER_1; |
|
3152 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
|
3153 } |
|
3154 |
|
3155 np->pkt_limit = NV_PKTLIMIT_1; |
|
3156 if (id->driver_data & DEV_HAS_LARGEDESC) |
|
3157 np->pkt_limit = NV_PKTLIMIT_2; |
|
3158 |
|
3159 if (id->driver_data & DEV_HAS_CHECKSUM) { |
|
3160 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
|
3161 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
|
3162 #ifdef NETIF_F_TSO |
|
3163 dev->features |= NETIF_F_TSO; |
|
3164 #endif |
|
3165 } |
|
3166 |
|
3167 np->vlanctl_bits = 0; |
|
3168 if (id->driver_data & DEV_HAS_VLAN) { |
|
3169 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; |
|
3170 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; |
|
3171 dev->vlan_rx_register = nv_vlan_rx_register; |
|
3172 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; |
|
3173 } |
|
3174 |
|
3175 np->msi_flags = 0; |
|
3176 if ((id->driver_data & DEV_HAS_MSI) && !disable_msi) { |
|
3177 np->msi_flags |= NV_MSI_CAPABLE; |
|
3178 } |
|
3179 if ((id->driver_data & DEV_HAS_MSI_X) && !disable_msix) { |
|
3180 np->msi_flags |= NV_MSI_X_CAPABLE; |
|
3181 } |
|
3182 |
|
3183 err = -ENOMEM; |
|
3184 np->base = ioremap(addr, np->register_size); |
|
3185 if (!np->base) |
|
3186 goto out_relreg; |
|
3187 dev->base_addr = (unsigned long)np->base; |
|
3188 |
|
3189 dev->irq = pci_dev->irq; |
|
3190 |
|
3191 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
3192 np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
|
3193 sizeof(struct ring_desc) * (RX_RING + TX_RING), |
|
3194 &np->ring_addr); |
|
3195 if (!np->rx_ring.orig) |
|
3196 goto out_unmap; |
|
3197 np->tx_ring.orig = &np->rx_ring.orig[RX_RING]; |
|
3198 } else { |
|
3199 np->rx_ring.ex = pci_alloc_consistent(pci_dev, |
|
3200 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), |
|
3201 &np->ring_addr); |
|
3202 if (!np->rx_ring.ex) |
|
3203 goto out_unmap; |
|
3204 np->tx_ring.ex = &np->rx_ring.ex[RX_RING]; |
|
3205 } |
|
3206 |
|
3207 dev->open = nv_open; |
|
3208 dev->stop = nv_close; |
|
3209 dev->hard_start_xmit = nv_start_xmit; |
|
3210 dev->get_stats = nv_get_stats; |
|
3211 dev->change_mtu = nv_change_mtu; |
|
3212 dev->set_mac_address = nv_set_mac_address; |
|
3213 dev->set_multicast_list = nv_set_multicast; |
|
3214 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
3215 dev->poll_controller = nv_poll_controller; |
|
3216 #endif |
|
3217 SET_ETHTOOL_OPS(dev, &ops); |
|
3218 dev->tx_timeout = nv_tx_timeout; |
|
3219 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
|
3220 |
|
3221 pci_set_drvdata(pci_dev, dev); |
|
3222 |
|
3223 /* read the mac address */ |
|
3224 base = get_hwbase(dev); |
|
3225 np->orig_mac[0] = readl(base + NvRegMacAddrA); |
|
3226 np->orig_mac[1] = readl(base + NvRegMacAddrB); |
|
3227 |
|
3228 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
|
3229 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
|
3230 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
|
3231 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
|
3232 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
|
3233 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
|
3234 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
3235 |
|
3236 if (!is_valid_ether_addr(dev->perm_addr)) { |
|
3237 /* |
|
3238 * Bad mac address. At least one bios sets the mac address |
|
3239 * to 01:23:45:67:89:ab |
|
3240 */ |
|
3241 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n", |
|
3242 pci_name(pci_dev), |
|
3243 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
3244 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
3245 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n"); |
|
3246 dev->dev_addr[0] = 0x00; |
|
3247 dev->dev_addr[1] = 0x00; |
|
3248 dev->dev_addr[2] = 0x6c; |
|
3249 get_random_bytes(&dev->dev_addr[3], 3); |
|
3250 } |
|
3251 |
|
3252 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
|
3253 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
|
3254 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
3255 |
|
3256 /* disable WOL */ |
|
3257 writel(0, base + NvRegWakeUpFlags); |
|
3258 np->wolenabled = 0; |
|
3259 |
|
3260 if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
|
3261 u8 revision_id; |
|
3262 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id); |
|
3263 |
|
3264 /* take phy and nic out of low power mode */ |
|
3265 powerstate = readl(base + NvRegPowerState2); |
|
3266 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; |
|
3267 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 || |
|
3268 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) && |
|
3269 revision_id >= 0xA3) |
|
3270 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
|
3271 writel(powerstate, base + NvRegPowerState2); |
|
3272 } |
|
3273 |
|
3274 if (np->desc_ver == DESC_VER_1) { |
|
3275 np->tx_flags = NV_TX_VALID; |
|
3276 } else { |
|
3277 np->tx_flags = NV_TX2_VALID; |
|
3278 } |
|
3279 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) { |
|
3280 np->irqmask = NVREG_IRQMASK_THROUGHPUT; |
|
3281 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
3282 np->msi_flags |= 0x0003; |
|
3283 } else { |
|
3284 np->irqmask = NVREG_IRQMASK_CPU; |
|
3285 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
|
3286 np->msi_flags |= 0x0001; |
|
3287 } |
|
3288 |
|
3289 if (id->driver_data & DEV_NEED_TIMERIRQ) |
|
3290 np->irqmask |= NVREG_IRQ_TIMER; |
|
3291 if (id->driver_data & DEV_NEED_LINKTIMER) { |
|
3292 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev)); |
|
3293 np->need_linktimer = 1; |
|
3294 np->link_timeout = jiffies + LINK_TIMEOUT; |
|
3295 } else { |
|
3296 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev)); |
|
3297 np->need_linktimer = 0; |
|
3298 } |
|
3299 |
|
3300 /* find a suitable phy */ |
|
3301 for (i = 1; i <= 32; i++) { |
|
3302 int id1, id2; |
|
3303 int phyaddr = i & 0x1F; |
|
3304 |
|
3305 spin_lock_irq(&np->lock); |
|
3306 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
|
3307 spin_unlock_irq(&np->lock); |
|
3308 if (id1 < 0 || id1 == 0xffff) |
|
3309 continue; |
|
3310 spin_lock_irq(&np->lock); |
|
3311 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
|
3312 spin_unlock_irq(&np->lock); |
|
3313 if (id2 < 0 || id2 == 0xffff) |
|
3314 continue; |
|
3315 |
|
3316 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
|
3317 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
|
3318 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
|
3319 pci_name(pci_dev), id1, id2, phyaddr); |
|
3320 np->phyaddr = phyaddr; |
|
3321 np->phy_oui = id1 | id2; |
|
3322 break; |
|
3323 } |
|
3324 if (i == 33) { |
|
3325 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n", |
|
3326 pci_name(pci_dev)); |
|
3327 goto out_freering; |
|
3328 } |
|
3329 |
|
3330 /* reset it */ |
|
3331 phy_init(dev); |
|
3332 |
|
3333 /* set default link speed settings */ |
|
3334 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
|
3335 np->duplex = 0; |
|
3336 np->autoneg = 1; |
|
3337 |
|
3338 // offer device to EtherCAT master module |
|
3339 if (ecdev_offer(dev, ec_poll, THIS_MODULE, &np->ecdev)) { |
|
3340 printk(KERN_ERR "forcedeth: Failed to offer device.\n"); |
|
3341 goto out_freering; |
|
3342 } |
|
3343 |
|
3344 if (np->ecdev) { |
|
3345 if (ecdev_open(np->ecdev)) { |
|
3346 ecdev_withdraw(np->ecdev); |
|
3347 goto out_freering; |
|
3348 } |
|
3349 } |
|
3350 else { |
|
3351 err = register_netdev(dev); |
|
3352 if (err) { |
|
3353 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err); |
|
3354 goto out_freering; |
|
3355 } |
|
3356 } |
|
3357 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n", |
|
3358 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device, |
|
3359 pci_name(pci_dev)); |
|
3360 |
|
3361 return 0; |
|
3362 |
|
3363 out_freering: |
|
3364 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
3365 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), |
|
3366 np->rx_ring.orig, np->ring_addr); |
|
3367 else |
|
3368 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), |
|
3369 np->rx_ring.ex, np->ring_addr); |
|
3370 pci_set_drvdata(pci_dev, NULL); |
|
3371 out_unmap: |
|
3372 iounmap(get_hwbase(dev)); |
|
3373 out_relreg: |
|
3374 pci_release_regions(pci_dev); |
|
3375 out_disable: |
|
3376 pci_disable_device(pci_dev); |
|
3377 out_free: |
|
3378 free_netdev(dev); |
|
3379 out: |
|
3380 return err; |
|
3381 } |
|
3382 |
|
3383 static void __devexit nv_remove(struct pci_dev *pci_dev) |
|
3384 { |
|
3385 struct net_device *dev = pci_get_drvdata(pci_dev); |
|
3386 struct fe_priv *np = netdev_priv(dev); |
|
3387 |
|
3388 if (np->ecdev) { |
|
3389 ecdev_close(np->ecdev); |
|
3390 ecdev_withdraw(np->ecdev); |
|
3391 } |
|
3392 else { |
|
3393 unregister_netdev(dev); |
|
3394 } |
|
3395 |
|
3396 /* free all structures */ |
|
3397 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
3398 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr); |
|
3399 else |
|
3400 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr); |
|
3401 iounmap(get_hwbase(dev)); |
|
3402 pci_release_regions(pci_dev); |
|
3403 pci_disable_device(pci_dev); |
|
3404 free_netdev(dev); |
|
3405 pci_set_drvdata(pci_dev, NULL); |
|
3406 } |
|
3407 |
|
3408 static struct pci_device_id pci_tbl[] = { |
|
3409 { /* nForce Ethernet Controller */ |
|
3410 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1), |
|
3411 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3412 }, |
|
3413 { /* nForce2 Ethernet Controller */ |
|
3414 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2), |
|
3415 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3416 }, |
|
3417 { /* nForce3 Ethernet Controller */ |
|
3418 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3), |
|
3419 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER, |
|
3420 }, |
|
3421 { /* nForce3 Ethernet Controller */ |
|
3422 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4), |
|
3423 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3424 }, |
|
3425 { /* nForce3 Ethernet Controller */ |
|
3426 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5), |
|
3427 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3428 }, |
|
3429 { /* nForce3 Ethernet Controller */ |
|
3430 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6), |
|
3431 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3432 }, |
|
3433 { /* nForce3 Ethernet Controller */ |
|
3434 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7), |
|
3435 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM, |
|
3436 }, |
|
3437 { /* CK804 Ethernet Controller */ |
|
3438 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8), |
|
3439 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3440 }, |
|
3441 { /* CK804 Ethernet Controller */ |
|
3442 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9), |
|
3443 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3444 }, |
|
3445 { /* MCP04 Ethernet Controller */ |
|
3446 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10), |
|
3447 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3448 }, |
|
3449 { /* MCP04 Ethernet Controller */ |
|
3450 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11), |
|
3451 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA, |
|
3452 }, |
|
3453 { /* MCP51 Ethernet Controller */ |
|
3454 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12), |
|
3455 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
3456 }, |
|
3457 { /* MCP51 Ethernet Controller */ |
|
3458 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13), |
|
3459 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL, |
|
3460 }, |
|
3461 { /* MCP55 Ethernet Controller */ |
|
3462 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
|
3463 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
|
3464 }, |
|
3465 { /* MCP55 Ethernet Controller */ |
|
3466 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
|
3467 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL, |
|
3468 }, |
|
3469 {0,}, |
|
3470 }; |
|
3471 |
|
3472 static struct pci_driver driver = { |
|
3473 .name = "forcedeth", |
|
3474 .id_table = pci_tbl, |
|
3475 .probe = nv_probe, |
|
3476 .remove = __devexit_p(nv_remove), |
|
3477 }; |
|
3478 |
|
3479 |
|
3480 static int __init init_nic(void) |
|
3481 { |
|
3482 printk(KERN_INFO "forcedeth: EtherCAT-capable nForce ethernet driver." |
|
3483 " Version %s, master %s.\n", |
|
3484 FORCEDETH_VERSION, EC_MASTER_VERSION); |
|
3485 return pci_module_init(&driver); |
|
3486 } |
|
3487 |
|
3488 static void __exit exit_nic(void) |
|
3489 { |
|
3490 pci_unregister_driver(&driver); |
|
3491 } |
|
3492 |
|
3493 module_param(max_interrupt_work, int, 0); |
|
3494 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
|
3495 module_param(optimization_mode, int, 0); |
|
3496 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); |
|
3497 module_param(poll_interval, int, 0); |
|
3498 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); |
|
3499 module_param(disable_msi, int, 0); |
|
3500 MODULE_PARM_DESC(disable_msi, "Disable MSI interrupts by setting to 1."); |
|
3501 module_param(disable_msix, int, 0); |
|
3502 MODULE_PARM_DESC(disable_msix, "Disable MSIX interrupts by setting to 1."); |
|
3503 |
|
3504 MODULE_AUTHOR("Dipl.-Ing. (FH) Florian Pose <fp@igh-essen.com>"); |
|
3505 MODULE_DESCRIPTION("EtherCAT-capable nForce ethernet driver"); |
|
3506 MODULE_LICENSE("GPL"); |
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3507 |
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3508 //MODULE_DEVICE_TABLE(pci, pci_tbl); // prevent auto-loading |
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3509 |
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3510 module_init(init_nic); |
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3511 module_exit(exit_nic); |
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