1 /*******************************************************************************

     2 

     3 

     4   Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.

     5 

     6   This program is free software; you can redistribute it and/or modify it

     7   under the terms of the GNU General Public License as published by the Free

     8   Software Foundation; either version 2 of the License, or (at your option)

     9   any later version.

    10 

    11   This program is distributed in the hope that it will be useful, but WITHOUT

    12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    14   more details.

    15 

    16   You should have received a copy of the GNU General Public License along with

    17   this program; if not, write to the Free Software Foundation, Inc., 59

    18   Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    19 

    20   The full GNU General Public License is included in this distribution in the

    21   file called LICENSE.

    22 

    23   Contact Information:

    24   Linux NICS <linux.nics@intel.com>

    25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    26 

    27 *******************************************************************************/

    28 

    29 /*

    30  *	e100.c: Intel(R) PRO/100 ethernet driver

    31  *

    32  *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    33  *	original e100 driver, but better described as a munging of

    34  *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    35  *

    36  *	References:

    37  *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    38  *		Open Source Software Developers Manual,

    39  *		http://sourceforge.net/projects/e1000

    40  *

    41  *

    42  *	                      Theory of Operation

    43  *

    44  *	I.   General

    45  *

    46  *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    47  *	controller family, which includes the 82557, 82558, 82559, 82550,

    48  *	82551, and 82562 devices.  82558 and greater controllers

    49  *	integrate the Intel 82555 PHY.  The controllers are used in

    50  *	server and client network interface cards, as well as in

    51  *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    52  *	configurations.  8255x supports a 32-bit linear addressing

    53  *	mode and operates at 33Mhz PCI clock rate.

    54  *

    55  *	II.  Driver Operation

    56  *

    57  *	Memory-mapped mode is used exclusively to access the device's

    58  *	shared-memory structure, the Control/Status Registers (CSR). All

    59  *	setup, configuration, and control of the device, including queuing

    60  *	of Tx, Rx, and configuration commands is through the CSR.

    61  *	cmd_lock serializes accesses to the CSR command register.  cb_lock

    62  *	protects the shared Command Block List (CBL).

    63  *

    64  *	8255x is highly MII-compliant and all access to the PHY go

    65  *	through the Management Data Interface (MDI).  Consequently, the

    66  *	driver leverages the mii.c library shared with other MII-compliant

    67  *	devices.

    68  *

    69  *	Big- and Little-Endian byte order as well as 32- and 64-bit

    70  *	archs are supported.  Weak-ordered memory and non-cache-coherent

    71  *	archs are supported.

    72  *

    73  *	III. Transmit

    74  *

    75  *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

    76  *	together in a fixed-size ring (CBL) thus forming the flexible mode

    77  *	memory structure.  A TCB marked with the suspend-bit indicates

    78  *	the end of the ring.  The last TCB processed suspends the

    79  *	controller, and the controller can be restarted by issue a CU

    80  *	resume command to continue from the suspend point, or a CU start

    81  *	command to start at a given position in the ring.

    82  *

    83  *	Non-Tx commands (config, multicast setup, etc) are linked

    84  *	into the CBL ring along with Tx commands.  The common structure

    85  *	used for both Tx and non-Tx commands is the Command Block (CB).

    86  *

    87  *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

    88  *	is the next CB to check for completion; cb_to_send is the first

    89  *	CB to start on in case of a previous failure to resume.  CB clean

    90  *	up happens in interrupt context in response to a CU interrupt.

    91  *	cbs_avail keeps track of number of free CB resources available.

    92  *

    93  * 	Hardware padding of short packets to minimum packet size is

    94  * 	enabled.  82557 pads with 7Eh, while the later controllers pad

    95  * 	with 00h.

    96  *

    97  *	IV.  Recieve

    98  *

    99  *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   100  *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   101  *	memory structure.  Rx skbs are allocated to contain both the RFD

   102  *	and the data buffer, but the RFD is pulled off before the skb is

   103  *	indicated.  The data buffer is aligned such that encapsulated

   104  *	protocol headers are u32-aligned.  Since the RFD is part of the

   105  *	mapped shared memory, and completion status is contained within

   106  *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   107  *	view from software and hardware.

   108  *

   109  *	Under typical operation, the  receive unit (RU) is start once,

   110  *	and the controller happily fills RFDs as frames arrive.  If

   111  *	replacement RFDs cannot be allocated, or the RU goes non-active,

   112  *	the RU must be restarted.  Frame arrival generates an interrupt,

   113  *	and Rx indication and re-allocation happen in the same context,

   114  *	therefore no locking is required.  A software-generated interrupt

   115  *	is generated from the watchdog to recover from a failed allocation

   116  *	senario where all Rx resources have been indicated and none re-

   117  *	placed.

   118  *

   119  *	V.   Miscellaneous

   120  *

   121  * 	VLAN offloading of tagging, stripping and filtering is not

   122  * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   123  * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   124  * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   125  * 	not supported (hardware limitation).

   126  *

   127  * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   128  *

   129  * 	Thanks to JC (jchapman@katalix.com) for helping with

   130  * 	testing/troubleshooting the development driver.

   131  *

   132  * 	TODO:

   133  * 	o several entry points race with dev->close

   134  * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   135  *

   136  *	FIXES:

   137  * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   138  *	- Stratus87247: protect MDI control register manipulations

   139  */

   140 

   141 #include <linux/module.h>

   142 #include <linux/moduleparam.h>

   143 #include <linux/kernel.h>

   144 #include <linux/types.h>

   145 #include <linux/slab.h>

   146 #include <linux/delay.h>

   147 #include <linux/init.h>

   148 #include <linux/pci.h>

   149 #include <linux/dma-mapping.h>

   150 #include <linux/netdevice.h>

   151 #include <linux/etherdevice.h>

   152 #include <linux/mii.h>

   153 #include <linux/if_vlan.h>

   154 #include <linux/skbuff.h>

   155 #include <linux/ethtool.h>

   156 #include <linux/string.h>

   157 #include <asm/unaligned.h>

   158 

   159 

   160 #define DRV_NAME		"e100"

   161 #define DRV_EXT		"-NAPI"

   162 #define DRV_VERSION		"3.5.10-k2"DRV_EXT

   163 #define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"

   164 #define DRV_COPYRIGHT		"Copyright(c) 1999-2005 Intel Corporation"

   165 #define PFX			DRV_NAME ": "

   166 

   167 #define E100_WATCHDOG_PERIOD	(2 * HZ)

   168 #define E100_NAPI_WEIGHT	16

   169 

   170 MODULE_DESCRIPTION(DRV_DESCRIPTION);

   171 MODULE_AUTHOR(DRV_COPYRIGHT);

   172 MODULE_LICENSE("GPL");

   173 MODULE_VERSION(DRV_VERSION);

   174 

   175 static int debug = 3;

   176 static int eeprom_bad_csum_allow = 0;

   177 module_param(debug, int, 0);

   178 module_param(eeprom_bad_csum_allow, int, 0);

   179 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   180 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   181 #define DPRINTK(nlevel, klevel, fmt, args...) \

   182 	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   183 	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   184 		__FUNCTION__ , ## args))

   185 

   186 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   187 	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   188 	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   189 static struct pci_device_id e100_id_table[] = {

   190 	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   191 	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   192 	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   193 	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   194 	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   195 	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   196 	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   197 	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   198 	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   199 	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   200 	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   201 	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   202 	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   203 	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   204 	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   205 	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   206 	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   207 	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   208 	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   209 	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   210 	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   211 	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   212 	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   213 	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   214 	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   215 	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   216 	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   217 	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   218 	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   219 	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   220 	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   221 	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   222 	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   223 	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   224 	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   225 	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   226 	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   227 	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   228 	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   229 	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   230 	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   231 	{ 0, }

   232 };

   233 MODULE_DEVICE_TABLE(pci, e100_id_table);

   234 

   235 enum mac {

   236 	mac_82557_D100_A  = 0,

   237 	mac_82557_D100_B  = 1,

   238 	mac_82557_D100_C  = 2,

   239 	mac_82558_D101_A4 = 4,

   240 	mac_82558_D101_B0 = 5,

   241 	mac_82559_D101M   = 8,

   242 	mac_82559_D101S   = 9,

   243 	mac_82550_D102    = 12,

   244 	mac_82550_D102_C  = 13,

   245 	mac_82551_E       = 14,

   246 	mac_82551_F       = 15,

   247 	mac_82551_10      = 16,

   248 	mac_unknown       = 0xFF,

   249 };

   250 

   251 enum phy {

   252 	phy_100a     = 0x000003E0,

   253 	phy_100c     = 0x035002A8,

   254 	phy_82555_tx = 0x015002A8,

   255 	phy_nsc_tx   = 0x5C002000,

   256 	phy_82562_et = 0x033002A8,

   257 	phy_82562_em = 0x032002A8,

   258 	phy_82562_ek = 0x031002A8,

   259 	phy_82562_eh = 0x017002A8,

   260 	phy_unknown  = 0xFFFFFFFF,

   261 };

   262 

   263 /* CSR (Control/Status Registers) */

   264 struct csr {

   265 	struct {

   266 		u8 status;

   267 		u8 stat_ack;

   268 		u8 cmd_lo;

   269 		u8 cmd_hi;

   270 		u32 gen_ptr;

   271 	} scb;

   272 	u32 port;

   273 	u16 flash_ctrl;

   274 	u8 eeprom_ctrl_lo;

   275 	u8 eeprom_ctrl_hi;

   276 	u32 mdi_ctrl;

   277 	u32 rx_dma_count;

   278 };

   279 

   280 enum scb_status {

   281 	rus_ready        = 0x10,

   282 	rus_mask         = 0x3C,

   283 };

   284 

   285 enum ru_state  {

   286 	RU_SUSPENDED = 0,

   287 	RU_RUNNING	 = 1,

   288 	RU_UNINITIALIZED = -1,

   289 };

   290 

   291 enum scb_stat_ack {

   292 	stat_ack_not_ours    = 0x00,

   293 	stat_ack_sw_gen      = 0x04,

   294 	stat_ack_rnr         = 0x10,

   295 	stat_ack_cu_idle     = 0x20,

   296 	stat_ack_frame_rx    = 0x40,

   297 	stat_ack_cu_cmd_done = 0x80,

   298 	stat_ack_not_present = 0xFF,

   299 	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   300 	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   301 };

   302 

   303 enum scb_cmd_hi {

   304 	irq_mask_none = 0x00,

   305 	irq_mask_all  = 0x01,

   306 	irq_sw_gen    = 0x02,

   307 };

   308 

   309 enum scb_cmd_lo {

   310 	cuc_nop        = 0x00,

   311 	ruc_start      = 0x01,

   312 	ruc_load_base  = 0x06,

   313 	cuc_start      = 0x10,

   314 	cuc_resume     = 0x20,

   315 	cuc_dump_addr  = 0x40,

   316 	cuc_dump_stats = 0x50,

   317 	cuc_load_base  = 0x60,

   318 	cuc_dump_reset = 0x70,

   319 };

   320 

   321 enum cuc_dump {

   322 	cuc_dump_complete       = 0x0000A005,

   323 	cuc_dump_reset_complete = 0x0000A007,

   324 };

   325 

   326 enum port {

   327 	software_reset  = 0x0000,

   328 	selftest        = 0x0001,

   329 	selective_reset = 0x0002,

   330 };

   331 

   332 enum eeprom_ctrl_lo {

   333 	eesk = 0x01,

   334 	eecs = 0x02,

   335 	eedi = 0x04,

   336 	eedo = 0x08,

   337 };

   338 

   339 enum mdi_ctrl {

   340 	mdi_write = 0x04000000,

   341 	mdi_read  = 0x08000000,

   342 	mdi_ready = 0x10000000,

   343 };

   344 

   345 enum eeprom_op {

   346 	op_write = 0x05,

   347 	op_read  = 0x06,

   348 	op_ewds  = 0x10,

   349 	op_ewen  = 0x13,

   350 };

   351 

   352 enum eeprom_offsets {

   353 	eeprom_cnfg_mdix  = 0x03,

   354 	eeprom_id         = 0x0A,

   355 	eeprom_config_asf = 0x0D,

   356 	eeprom_smbus_addr = 0x90,

   357 };

   358 

   359 enum eeprom_cnfg_mdix {

   360 	eeprom_mdix_enabled = 0x0080,

   361 };

   362 

   363 enum eeprom_id {

   364 	eeprom_id_wol = 0x0020,

   365 };

   366 

   367 enum eeprom_config_asf {

   368 	eeprom_asf = 0x8000,

   369 	eeprom_gcl = 0x4000,

   370 };

   371 

   372 enum cb_status {

   373 	cb_complete = 0x8000,

   374 	cb_ok       = 0x2000,

   375 };

   376 

   377 enum cb_command {

   378 	cb_nop    = 0x0000,

   379 	cb_iaaddr = 0x0001,

   380 	cb_config = 0x0002,

   381 	cb_multi  = 0x0003,

   382 	cb_tx     = 0x0004,

   383 	cb_ucode  = 0x0005,

   384 	cb_dump   = 0x0006,

   385 	cb_tx_sf  = 0x0008,

   386 	cb_cid    = 0x1f00,

   387 	cb_i      = 0x2000,

   388 	cb_s      = 0x4000,

   389 	cb_el     = 0x8000,

   390 };

   391 

   392 struct rfd {

   393 	u16 status;

   394 	u16 command;

   395 	u32 link;

   396 	u32 rbd;

   397 	u16 actual_size;

   398 	u16 size;

   399 };

   400 

   401 struct rx {

   402 	struct rx *next, *prev;

   403 	struct sk_buff *skb;

   404 	dma_addr_t dma_addr;

   405 };

   406 

   407 #if defined(__BIG_ENDIAN_BITFIELD)

   408 #define X(a,b)	b,a

   409 #else

   410 #define X(a,b)	a,b

   411 #endif

   412 struct config {

   413 /*0*/	u8 X(byte_count:6, pad0:2);

   414 /*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   415 /*2*/	u8 adaptive_ifs;

   416 /*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   417 	   term_write_cache_line:1), pad3:4);

   418 /*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   419 /*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   420 /*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   421 	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   422 	   rx_discard_overruns:1), rx_save_bad_frames:1);

   423 /*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   424 	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   425 	   tx_dynamic_tbd:1);

   426 /*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   427 /*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   428 	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   429 /*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   430 	   loopback:2);

   431 /*11*/	u8 X(linear_priority:3, pad11:5);

   432 /*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   433 /*13*/	u8 ip_addr_lo;

   434 /*14*/	u8 ip_addr_hi;

   435 /*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   436 	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   437 	   pad15_2:1), crs_or_cdt:1);

   438 /*16*/	u8 fc_delay_lo;

   439 /*17*/	u8 fc_delay_hi;

   440 /*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   441 	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   442 /*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   443 	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   444 	   full_duplex_force:1), full_duplex_pin:1);

   445 /*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   446 /*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   447 /*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   448 	u8 pad_d102[9];

   449 };

   450 

   451 #define E100_MAX_MULTICAST_ADDRS	64

   452 struct multi {

   453 	u16 count;

   454 	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   455 };

   456 

   457 /* Important: keep total struct u32-aligned */

   458 #define UCODE_SIZE			134

   459 struct cb {

   460 	u16 status;

   461 	u16 command;

   462 	u32 link;

   463 	union {

   464 		u8 iaaddr[ETH_ALEN];

   465 		u32 ucode[UCODE_SIZE];

   466 		struct config config;

   467 		struct multi multi;

   468 		struct {

   469 			u32 tbd_array;

   470 			u16 tcb_byte_count;

   471 			u8 threshold;

   472 			u8 tbd_count;

   473 			struct {

   474 				u32 buf_addr;

   475 				u16 size;

   476 				u16 eol;

   477 			} tbd;

   478 		} tcb;

   479 		u32 dump_buffer_addr;

   480 	} u;

   481 	struct cb *next, *prev;

   482 	dma_addr_t dma_addr;

   483 	struct sk_buff *skb;

   484 };

   485 

   486 enum loopback {

   487 	lb_none = 0, lb_mac = 1, lb_phy = 3,

   488 };

   489 

   490 struct stats {

   491 	u32 tx_good_frames, tx_max_collisions, tx_late_collisions,

   492 		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,

   493 		tx_multiple_collisions, tx_total_collisions;

   494 	u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,

   495 		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,

   496 		rx_short_frame_errors;

   497 	u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;

   498 	u16 xmt_tco_frames, rcv_tco_frames;

   499 	u32 complete;

   500 };

   501 

   502 struct mem {

   503 	struct {

   504 		u32 signature;

   505 		u32 result;

   506 	} selftest;

   507 	struct stats stats;

   508 	u8 dump_buf[596];

   509 };

   510 

   511 struct param_range {

   512 	u32 min;

   513 	u32 max;

   514 	u32 count;

   515 };

   516 

   517 struct params {

   518 	struct param_range rfds;

   519 	struct param_range cbs;

   520 };

   521 

   522 struct nic {

   523 	/* Begin: frequently used values: keep adjacent for cache effect */

   524 	u32 msg_enable				____cacheline_aligned;

   525 	struct net_device *netdev;

   526 	struct pci_dev *pdev;

   527 

   528 	struct rx *rxs				____cacheline_aligned;

   529 	struct rx *rx_to_use;

   530 	struct rx *rx_to_clean;

   531 	struct rfd blank_rfd;

   532 	enum ru_state ru_running;

   533 

   534 	spinlock_t cb_lock			____cacheline_aligned;

   535 	spinlock_t cmd_lock;

   536 	struct csr __iomem *csr;

   537 	enum scb_cmd_lo cuc_cmd;

   538 	unsigned int cbs_avail;

   539 	struct cb *cbs;

   540 	struct cb *cb_to_use;

   541 	struct cb *cb_to_send;

   542 	struct cb *cb_to_clean;

   543 	u16 tx_command;

   544 	/* End: frequently used values: keep adjacent for cache effect */

   545 

   546 	enum {

   547 		ich                = (1 << 0),

   548 		promiscuous        = (1 << 1),

   549 		multicast_all      = (1 << 2),

   550 		wol_magic          = (1 << 3),

   551 		ich_10h_workaround = (1 << 4),

   552 	} flags					____cacheline_aligned;

   553 

   554 	enum mac mac;

   555 	enum phy phy;

   556 	struct params params;

   557 	struct net_device_stats net_stats;

   558 	struct timer_list watchdog;

   559 	struct timer_list blink_timer;

   560 	struct mii_if_info mii;

   561 	struct work_struct tx_timeout_task;

   562 	enum loopback loopback;

   563 

   564 	struct mem *mem;

   565 	dma_addr_t dma_addr;

   566 

   567 	dma_addr_t cbs_dma_addr;

   568 	u8 adaptive_ifs;

   569 	u8 tx_threshold;

   570 	u32 tx_frames;

   571 	u32 tx_collisions;

   572 	u32 tx_deferred;

   573 	u32 tx_single_collisions;

   574 	u32 tx_multiple_collisions;

   575 	u32 tx_fc_pause;

   576 	u32 tx_tco_frames;

   577 

   578 	u32 rx_fc_pause;

   579 	u32 rx_fc_unsupported;

   580 	u32 rx_tco_frames;

   581 	u32 rx_over_length_errors;

   582 

   583 	u8 rev_id;

   584 	u16 leds;

   585 	u16 eeprom_wc;

   586 	u16 eeprom[256];

   587 	spinlock_t mdio_lock;

   588 };

   589 

   590 static inline void e100_write_flush(struct nic *nic)

   591 {

   592 	/* Flush previous PCI writes through intermediate bridges

   593 	 * by doing a benign read */

   594 	(void)readb(&nic->csr->scb.status);

   595 }

   596 

   597 static void e100_enable_irq(struct nic *nic)

   598 {

   599 	unsigned long flags;

   600 

   601 	spin_lock_irqsave(&nic->cmd_lock, flags);

   602 	writeb(irq_mask_none, &nic->csr->scb.cmd_hi);

   603 	e100_write_flush(nic);

   604 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   605 }

   606 

   607 static void e100_disable_irq(struct nic *nic)

   608 {

   609 	unsigned long flags;

   610 

   611 	spin_lock_irqsave(&nic->cmd_lock, flags);

   612 	writeb(irq_mask_all, &nic->csr->scb.cmd_hi);

   613 	e100_write_flush(nic);

   614 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   615 }

   616 

   617 static void e100_hw_reset(struct nic *nic)

   618 {

   619 	/* Put CU and RU into idle with a selective reset to get

   620 	 * device off of PCI bus */

   621 	writel(selective_reset, &nic->csr->port);

   622 	e100_write_flush(nic); udelay(20);

   623 

   624 	/* Now fully reset device */

   625 	writel(software_reset, &nic->csr->port);

   626 	e100_write_flush(nic); udelay(20);

   627 

   628 	/* Mask off our interrupt line - it's unmasked after reset */

   629 	e100_disable_irq(nic);

   630 }

   631 

   632 static int e100_self_test(struct nic *nic)

   633 {

   634 	u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);

   635 

   636 	/* Passing the self-test is a pretty good indication

   637 	 * that the device can DMA to/from host memory */

   638 

   639 	nic->mem->selftest.signature = 0;

   640 	nic->mem->selftest.result = 0xFFFFFFFF;

   641 

   642 	writel(selftest | dma_addr, &nic->csr->port);

   643 	e100_write_flush(nic);

   644 	/* Wait 10 msec for self-test to complete */

   645 	msleep(10);

   646 

   647 	/* Interrupts are enabled after self-test */

   648 	e100_disable_irq(nic);

   649 

   650 	/* Check results of self-test */

   651 	if(nic->mem->selftest.result != 0) {

   652 		DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",

   653 			nic->mem->selftest.result);

   654 		return -ETIMEDOUT;

   655 	}

   656 	if(nic->mem->selftest.signature == 0) {

   657 		DPRINTK(HW, ERR, "Self-test failed: timed out\n");

   658 		return -ETIMEDOUT;

   659 	}

   660 

   661 	return 0;

   662 }

   663 

   664 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)

   665 {

   666 	u32 cmd_addr_data[3];

   667 	u8 ctrl;

   668 	int i, j;

   669 

   670 	/* Three cmds: write/erase enable, write data, write/erase disable */

   671 	cmd_addr_data[0] = op_ewen << (addr_len - 2);

   672 	cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |

   673 		cpu_to_le16(data);

   674 	cmd_addr_data[2] = op_ewds << (addr_len - 2);

   675 

   676 	/* Bit-bang cmds to write word to eeprom */

   677 	for(j = 0; j < 3; j++) {

   678 

   679 		/* Chip select */

   680 		writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   681 		e100_write_flush(nic); udelay(4);

   682 

   683 		for(i = 31; i >= 0; i--) {

   684 			ctrl = (cmd_addr_data[j] & (1 << i)) ?

   685 				eecs | eedi : eecs;

   686 			writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   687 			e100_write_flush(nic); udelay(4);

   688 

   689 			writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   690 			e100_write_flush(nic); udelay(4);

   691 		}

   692 		/* Wait 10 msec for cmd to complete */

   693 		msleep(10);

   694 

   695 		/* Chip deselect */

   696 		writeb(0, &nic->csr->eeprom_ctrl_lo);

   697 		e100_write_flush(nic); udelay(4);

   698 	}

   699 };

   700 

   701 /* General technique stolen from the eepro100 driver - very clever */

   702 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)

   703 {

   704 	u32 cmd_addr_data;

   705 	u16 data = 0;

   706 	u8 ctrl;

   707 	int i;

   708 

   709 	cmd_addr_data = ((op_read << *addr_len) | addr) << 16;

   710 

   711 	/* Chip select */

   712 	writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   713 	e100_write_flush(nic); udelay(4);

   714 

   715 	/* Bit-bang to read word from eeprom */

   716 	for(i = 31; i >= 0; i--) {

   717 		ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;

   718 		writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   719 		e100_write_flush(nic); udelay(4);

   720 

   721 		writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   722 		e100_write_flush(nic); udelay(4);

   723 

   724 		/* Eeprom drives a dummy zero to EEDO after receiving

   725 		 * complete address.  Use this to adjust addr_len. */

   726 		ctrl = readb(&nic->csr->eeprom_ctrl_lo);

   727 		if(!(ctrl & eedo) && i > 16) {

   728 			*addr_len -= (i - 16);

   729 			i = 17;

   730 		}

   731 

   732 		data = (data << 1) | (ctrl & eedo ? 1 : 0);

   733 	}

   734 

   735 	/* Chip deselect */

   736 	writeb(0, &nic->csr->eeprom_ctrl_lo);

   737 	e100_write_flush(nic); udelay(4);

   738 

   739 	return le16_to_cpu(data);

   740 };

   741 

   742 /* Load entire EEPROM image into driver cache and validate checksum */

   743 static int e100_eeprom_load(struct nic *nic)

   744 {

   745 	u16 addr, addr_len = 8, checksum = 0;

   746 

   747 	/* Try reading with an 8-bit addr len to discover actual addr len */

   748 	e100_eeprom_read(nic, &addr_len, 0);

   749 	nic->eeprom_wc = 1 << addr_len;

   750 

   751 	for(addr = 0; addr < nic->eeprom_wc; addr++) {

   752 		nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);

   753 		if(addr < nic->eeprom_wc - 1)

   754 			checksum += cpu_to_le16(nic->eeprom[addr]);

   755 	}

   756 

   757 	/* The checksum, stored in the last word, is calculated such that

   758 	 * the sum of words should be 0xBABA */

   759 	checksum = le16_to_cpu(0xBABA - checksum);

   760 	if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {

   761 		DPRINTK(PROBE, ERR, "EEPROM corrupted\n");

   762 		if (!eeprom_bad_csum_allow)

   763 			return -EAGAIN;

   764 	}

   765 

   766 	return 0;

   767 }

   768 

   769 /* Save (portion of) driver EEPROM cache to device and update checksum */

   770 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)

   771 {

   772 	u16 addr, addr_len = 8, checksum = 0;

   773 

   774 	/* Try reading with an 8-bit addr len to discover actual addr len */

   775 	e100_eeprom_read(nic, &addr_len, 0);

   776 	nic->eeprom_wc = 1 << addr_len;

   777 

   778 	if(start + count >= nic->eeprom_wc)

   779 		return -EINVAL;

   780 

   781 	for(addr = start; addr < start + count; addr++)

   782 		e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);

   783 

   784 	/* The checksum, stored in the last word, is calculated such that

   785 	 * the sum of words should be 0xBABA */

   786 	for(addr = 0; addr < nic->eeprom_wc - 1; addr++)

   787 		checksum += cpu_to_le16(nic->eeprom[addr]);

   788 	nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);

   789 	e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,

   790 		nic->eeprom[nic->eeprom_wc - 1]);

   791 

   792 	return 0;

   793 }

   794 

   795 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */

   796 #define E100_WAIT_SCB_FAST 20       /* delay like the old code */

   797 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)

   798 {

   799 	unsigned long flags;

   800 	unsigned int i;

   801 	int err = 0;

   802 

   803 	spin_lock_irqsave(&nic->cmd_lock, flags);

   804 

   805 	/* Previous command is accepted when SCB clears */

   806 	for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {

   807 		if(likely(!readb(&nic->csr->scb.cmd_lo)))

   808 			break;

   809 		cpu_relax();

   810 		if(unlikely(i > E100_WAIT_SCB_FAST))

   811 			udelay(5);

   812 	}

   813 	if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {

   814 		err = -EAGAIN;

   815 		goto err_unlock;

   816 	}

   817 

   818 	if(unlikely(cmd != cuc_resume))

   819 		writel(dma_addr, &nic->csr->scb.gen_ptr);

   820 	writeb(cmd, &nic->csr->scb.cmd_lo);

   821 

   822 err_unlock:

   823 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   824 

   825 	return err;

   826 }

   827 

   828 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,

   829 	void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))

   830 {

   831 	struct cb *cb;

   832 	unsigned long flags;

   833 	int err = 0;

   834 

   835 	spin_lock_irqsave(&nic->cb_lock, flags);

   836 

   837 	if(unlikely(!nic->cbs_avail)) {

   838 		err = -ENOMEM;

   839 		goto err_unlock;

   840 	}

   841 

   842 	cb = nic->cb_to_use;

   843 	nic->cb_to_use = cb->next;

   844 	nic->cbs_avail--;

   845 	cb->skb = skb;

   846 

   847 	if(unlikely(!nic->cbs_avail))

   848 		err = -ENOSPC;

   849 

   850 	cb_prepare(nic, cb, skb);

   851 

   852 	/* Order is important otherwise we'll be in a race with h/w:

   853 	 * set S-bit in current first, then clear S-bit in previous. */

   854 	cb->command |= cpu_to_le16(cb_s);

   855 	wmb();

   856 	cb->prev->command &= cpu_to_le16(~cb_s);

   857 

   858 	while(nic->cb_to_send != nic->cb_to_use) {

   859 		if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,

   860 			nic->cb_to_send->dma_addr))) {

   861 			/* Ok, here's where things get sticky.  It's

   862 			 * possible that we can't schedule the command

   863 			 * because the controller is too busy, so

   864 			 * let's just queue the command and try again

   865 			 * when another command is scheduled. */

   866 			if(err == -ENOSPC) {

   867 				//request a reset

   868 				schedule_work(&nic->tx_timeout_task);

   869 			}

   870 			break;

   871 		} else {

   872 			nic->cuc_cmd = cuc_resume;

   873 			nic->cb_to_send = nic->cb_to_send->next;

   874 		}

   875 	}

   876 

   877 err_unlock:

   878 	spin_unlock_irqrestore(&nic->cb_lock, flags);

   879 

   880 	return err;

   881 }

   882 

   883 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)

   884 {

   885 	u32 data_out = 0;

   886 	unsigned int i;

   887 	unsigned long flags;

   888 

   889 

   890 	/*

   891 	 * Stratus87247: we shouldn't be writing the MDI control

   892 	 * register until the Ready bit shows True.  Also, since

   893 	 * manipulation of the MDI control registers is a multi-step

   894 	 * procedure it should be done under lock.

   895 	 */

   896 	spin_lock_irqsave(&nic->mdio_lock, flags);

   897 	for (i = 100; i; --i) {

   898 		if (readl(&nic->csr->mdi_ctrl) & mdi_ready)

   899 			break;

   900 		udelay(20);

   901 	}

   902 	if (unlikely(!i)) {

   903 		printk("e100.mdio_ctrl(%s) won't go Ready\n",

   904 			nic->netdev->name );

   905 		spin_unlock_irqrestore(&nic->mdio_lock, flags);

   906 		return 0;		/* No way to indicate timeout error */

   907 	}

   908 	writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

   909 

   910 	for (i = 0; i < 100; i++) {

   911 		udelay(20);

   912 		if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)

   913 			break;

   914 	}

   915 	spin_unlock_irqrestore(&nic->mdio_lock, flags);

   916 	DPRINTK(HW, DEBUG,

   917 		"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",

   918 		dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);

   919 	return (u16)data_out;

   920 }

   921 

   922 static int mdio_read(struct net_device *netdev, int addr, int reg)

   923 {

   924 	return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);

   925 }

   926 

   927 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)

   928 {

   929 	mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);

   930 }

   931 

   932 static void e100_get_defaults(struct nic *nic)

   933 {

   934 	struct param_range rfds = { .min = 16, .max = 256, .count = 256 };

   935 	struct param_range cbs  = { .min = 64, .max = 256, .count = 128 };

   936 

   937 	pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);

   938 	/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */

   939 	nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;

   940 	if(nic->mac == mac_unknown)

   941 		nic->mac = mac_82557_D100_A;

   942 

   943 	nic->params.rfds = rfds;

   944 	nic->params.cbs = cbs;

   945 

   946 	/* Quadwords to DMA into FIFO before starting frame transmit */

   947 	nic->tx_threshold = 0xE0;

   948 

   949 	/* no interrupt for every tx completion, delay = 256us if not 557*/

   950 	nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |

   951 		((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));

   952 

   953 	/* Template for a freshly allocated RFD */

   954 	nic->blank_rfd.command = cpu_to_le16(cb_el);

   955 	nic->blank_rfd.rbd = 0xFFFFFFFF;

   956 	nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);

   957 

   958 	/* MII setup */

   959 	nic->mii.phy_id_mask = 0x1F;

   960 	nic->mii.reg_num_mask = 0x1F;

   961 	nic->mii.dev = nic->netdev;

   962 	nic->mii.mdio_read = mdio_read;

   963 	nic->mii.mdio_write = mdio_write;

   964 }

   965 

   966 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)

   967 {

   968 	struct config *config = &cb->u.config;

   969 	u8 *c = (u8 *)config;

   970 

   971 	cb->command = cpu_to_le16(cb_config);

   972 

   973 	memset(config, 0, sizeof(struct config));

   974 

   975 	config->byte_count = 0x16;		/* bytes in this struct */

   976 	config->rx_fifo_limit = 0x8;		/* bytes in FIFO before DMA */

   977 	config->direct_rx_dma = 0x1;		/* reserved */

   978 	config->standard_tcb = 0x1;		/* 1=standard, 0=extended */

   979 	config->standard_stat_counter = 0x1;	/* 1=standard, 0=extended */

   980 	config->rx_discard_short_frames = 0x1;	/* 1=discard, 0=pass */

   981 	config->tx_underrun_retry = 0x3;	/* # of underrun retries */

   982 	config->mii_mode = 0x1;			/* 1=MII mode, 0=503 mode */

   983 	config->pad10 = 0x6;

   984 	config->no_source_addr_insertion = 0x1;	/* 1=no, 0=yes */

   985 	config->preamble_length = 0x2;		/* 0=1, 1=3, 2=7, 3=15 bytes */

   986 	config->ifs = 0x6;			/* x16 = inter frame spacing */

   987 	config->ip_addr_hi = 0xF2;		/* ARP IP filter - not used */

   988 	config->pad15_1 = 0x1;

   989 	config->pad15_2 = 0x1;

   990 	config->crs_or_cdt = 0x0;		/* 0=CRS only, 1=CRS or CDT */

   991 	config->fc_delay_hi = 0x40;		/* time delay for fc frame */

   992 	config->tx_padding = 0x1;		/* 1=pad short frames */

   993 	config->fc_priority_threshold = 0x7;	/* 7=priority fc disabled */

   994 	config->pad18 = 0x1;

   995 	config->full_duplex_pin = 0x1;		/* 1=examine FDX# pin */

   996 	config->pad20_1 = 0x1F;

   997 	config->fc_priority_location = 0x1;	/* 1=byte#31, 0=byte#19 */

   998 	config->pad21_1 = 0x5;

   999 

  1000 	config->adaptive_ifs = nic->adaptive_ifs;

  1001 	config->loopback = nic->loopback;

  1002 

  1003 	if(nic->mii.force_media && nic->mii.full_duplex)

  1004 		config->full_duplex_force = 0x1;	/* 1=force, 0=auto */

  1005 

  1006 	if(nic->flags & promiscuous || nic->loopback) {

  1007 		config->rx_save_bad_frames = 0x1;	/* 1=save, 0=discard */

  1008 		config->rx_discard_short_frames = 0x0;	/* 1=discard, 0=save */

  1009 		config->promiscuous_mode = 0x1;		/* 1=on, 0=off */

  1010 	}

  1011 

  1012 	if(nic->flags & multicast_all)

  1013 		config->multicast_all = 0x1;		/* 1=accept, 0=no */

  1014 

  1015 	/* disable WoL when up */

  1016 	if(netif_running(nic->netdev) || !(nic->flags & wol_magic))

  1017 		config->magic_packet_disable = 0x1;	/* 1=off, 0=on */

  1018 

  1019 	if(nic->mac >= mac_82558_D101_A4) {

  1020 		config->fc_disable = 0x1;	/* 1=Tx fc off, 0=Tx fc on */

  1021 		config->mwi_enable = 0x1;	/* 1=enable, 0=disable */

  1022 		config->standard_tcb = 0x0;	/* 1=standard, 0=extended */

  1023 		config->rx_long_ok = 0x1;	/* 1=VLANs ok, 0=standard */

  1024 		if(nic->mac >= mac_82559_D101M)

  1025 			config->tno_intr = 0x1;		/* TCO stats enable */

  1026 		else

  1027 			config->standard_stat_counter = 0x0;

  1028 	}

  1029 

  1030 	DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1031 		c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);

  1032 	DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1033 		c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);

  1034 	DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1035 		c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);

  1036 }

  1037 

  1038 /********************************************************/

  1039 /*  Micro code for 8086:1229 Rev 8                      */

  1040 /********************************************************/

  1041 

  1042 /*  Parameter values for the D101M B-step  */

  1043 #define D101M_CPUSAVER_TIMER_DWORD		78

  1044 #define D101M_CPUSAVER_BUNDLE_DWORD		65

  1045 #define D101M_CPUSAVER_MIN_SIZE_DWORD		126

  1046 

  1047 #define D101M_B_RCVBUNDLE_UCODE \

  1048 {\

  1049 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \

  1050 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \

  1051 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \

  1052 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \

  1053 0x00380438, 0x00000000, 0x00140000, 0x00380555, \

  1054 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \

  1055 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \

  1056 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \

  1057 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \

  1058 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \

  1059 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1060 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \

  1061 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \

  1062 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \

  1063 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \

  1064 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \

  1065 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \

  1066 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1067 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1068 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \

  1069 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \

  1070 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \

  1071 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \

  1072 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \

  1073 0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \

  1074 0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \

  1075 0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \

  1076 0x00130826, 0x000C0001, 0x00220559, 0x00101313, \

  1077 0x00380559, 0x00000000, 0x00000000, 0x00000000, \

  1078 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1079 0x00000000, 0x00130831, 0x0010090B, 0x00124813, \

  1080 0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \

  1081 0x003806A8, 0x00000000, 0x00000000, 0x00000000, \

  1082 }

  1083 

  1084 /********************************************************/

  1085 /*  Micro code for 8086:1229 Rev 9                      */

  1086 /********************************************************/

  1087 

  1088 /*  Parameter values for the D101S  */

  1089 #define D101S_CPUSAVER_TIMER_DWORD		78

  1090 #define D101S_CPUSAVER_BUNDLE_DWORD		67

  1091 #define D101S_CPUSAVER_MIN_SIZE_DWORD		128

  1092 

  1093 #define D101S_RCVBUNDLE_UCODE \

  1094 {\

  1095 0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \

  1096 0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \

  1097 0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \

  1098 0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \

  1099 0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \

  1100 0x00308000, 0x00100610, 0x00100561, 0x000E0408, \

  1101 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \

  1102 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \

  1103 0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \

  1104 0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \

  1105 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1106 0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \

  1107 0x003A047E, 0x00044010, 0x00380819, 0x00000000, \

  1108 0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \

  1109 0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \

  1110 0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \

  1111 0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \

  1112 0x00101313, 0x00380700, 0x00000000, 0x00000000, \

  1113 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1114 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \

  1115 0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \

  1116 0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \

  1117 0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \

  1118 0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \

  1119 0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \

  1120 0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \

  1121 0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \

  1122 0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \

  1123 0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \

  1124 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1125 0x00000000, 0x00000000, 0x00000000, 0x00130831, \

  1126 0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \

  1127 0x00041000, 0x00010004, 0x00380700  \

  1128 }

  1129 

  1130 /********************************************************/

  1131 /*  Micro code for the 8086:1229 Rev F/10               */

  1132 /********************************************************/

  1133 

  1134 /*  Parameter values for the D102 E-step  */

  1135 #define D102_E_CPUSAVER_TIMER_DWORD		42