1 /******************************************************************************

     2  *

     3  *  $Id$

     4  *

     5  *  Copyright (C) 2007  Florian Pose, Ingenieurgemeinschaft IgH

     6  *

     7  *  This file is part of the IgH EtherCAT Master.

     8  *

     9  *  The IgH EtherCAT Master is free software; you can redistribute it

    10  *  and/or modify it under the terms of the GNU General Public License

    11  *  as published by the Free Software Foundation; either version 2 of the

    12  *  License, or (at your option) any later version.

    13  *

    14  *  The IgH EtherCAT Master is distributed in the hope that it will be

    15  *  useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  *  GNU General Public License for more details.

    18  *

    19  *  You should have received a copy of the GNU General Public License

    20  *  along with the IgH EtherCAT Master; if not, write to the Free Software

    21  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

    22  *

    23  *  The right to use EtherCAT Technology is granted and comes free of

    24  *  charge under condition of compatibility of product made by

    25  *  Licensee. People intending to distribute/sell products based on the

    26  *  code, have to sign an agreement to guarantee that products using

    27  *  software based on IgH EtherCAT master stay compatible with the actual

    28  *  EtherCAT specification (which are released themselves as an open

    29  *  standard) as the (only) precondition to have the right to use EtherCAT

    30  *  Technology, IP and trade marks.

    31  *

    32  *****************************************************************************/

    33 

    34 /**

    35    \file

    36    EtherCAT driver for e100-compatible NICs.

    37 */

    38 

    39 /* Former documentation: */

    40 

    41 /*******************************************************************************

    42 

    43   Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.

    44 

    45   This program is free software; you can redistribute it and/or modify it

    46   under the terms of the GNU General Public License as published by the Free

    47   Software Foundation; either version 2 of the License, or (at your option)

    48   any later version.

    49 

    50   This program is distributed in the hope that it will be useful, but WITHOUT

    51   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    52   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

    53   more details.

    54 

    55   You should have received a copy of the GNU General Public License along with

    56   this program; if not, write to the Free Software Foundation, Inc., 59

    57   Temple Place - Suite 330, Boston, MA  02111-1307, USA.

    58 

    59   The full GNU General Public License is included in this distribution in the

    60   file called LICENSE.

    61 

    62   Contact Information:

    63   Linux NICS <linux.nics@intel.com>

    64   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

    65 

    66 *******************************************************************************/

    67 

    68 /*

    69  *	e100.c: Intel(R) PRO/100 ethernet driver

    70  *

    71  *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on

    72  *	original e100 driver, but better described as a munging of

    73  *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.

    74  *

    75  *	References:

    76  *		Intel 8255x 10/100 Mbps Ethernet Controller Family,

    77  *		Open Source Software Developers Manual,

    78  *		http://sourceforge.net/projects/e1000

    79  *

    80  *

    81  *	                      Theory of Operation

    82  *

    83  *	I.   General

    84  *

    85  *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet

    86  *	controller family, which includes the 82557, 82558, 82559, 82550,

    87  *	82551, and 82562 devices.  82558 and greater controllers

    88  *	integrate the Intel 82555 PHY.  The controllers are used in

    89  *	server and client network interface cards, as well as in

    90  *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx

    91  *	configurations.  8255x supports a 32-bit linear addressing

    92  *	mode and operates at 33Mhz PCI clock rate.

    93  *

    94  *	II.  Driver Operation

    95  *

    96  *	Memory-mapped mode is used exclusively to access the device's

    97  *	shared-memory structure, the Control/Status Registers (CSR). All

    98  *	setup, configuration, and control of the device, including queuing

    99  *	of Tx, Rx, and configuration commands is through the CSR.

   100  *	cmd_lock serializes accesses to the CSR command register.  cb_lock

   101  *	protects the shared Command Block List (CBL).

   102  *

   103  *	8255x is highly MII-compliant and all access to the PHY go

   104  *	through the Management Data Interface (MDI).  Consequently, the

   105  *	driver leverages the mii.c library shared with other MII-compliant

   106  *	devices.

   107  *

   108  *	Big- and Little-Endian byte order as well as 32- and 64-bit

   109  *	archs are supported.  Weak-ordered memory and non-cache-coherent

   110  *	archs are supported.

   111  *

   112  *	III. Transmit

   113  *

   114  *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked

   115  *	together in a fixed-size ring (CBL) thus forming the flexible mode

   116  *	memory structure.  A TCB marked with the suspend-bit indicates

   117  *	the end of the ring.  The last TCB processed suspends the

   118  *	controller, and the controller can be restarted by issue a CU

   119  *	resume command to continue from the suspend point, or a CU start

   120  *	command to start at a given position in the ring.

   121  *

   122  *	Non-Tx commands (config, multicast setup, etc) are linked

   123  *	into the CBL ring along with Tx commands.  The common structure

   124  *	used for both Tx and non-Tx commands is the Command Block (CB).

   125  *

   126  *	cb_to_use is the next CB to use for queuing a command; cb_to_clean

   127  *	is the next CB to check for completion; cb_to_send is the first

   128  *	CB to start on in case of a previous failure to resume.  CB clean

   129  *	up happens in interrupt context in response to a CU interrupt.

   130  *	cbs_avail keeps track of number of free CB resources available.

   131  *

   132  * 	Hardware padding of short packets to minimum packet size is

   133  * 	enabled.  82557 pads with 7Eh, while the later controllers pad

   134  * 	with 00h.

   135  *

   136  *	IV.  Recieve

   137  *

   138  *	The Receive Frame Area (RFA) comprises a ring of Receive Frame

   139  *	Descriptors (RFD) + data buffer, thus forming the simplified mode

   140  *	memory structure.  Rx skbs are allocated to contain both the RFD

   141  *	and the data buffer, but the RFD is pulled off before the skb is

   142  *	indicated.  The data buffer is aligned such that encapsulated

   143  *	protocol headers are u32-aligned.  Since the RFD is part of the

   144  *	mapped shared memory, and completion status is contained within

   145  *	the RFD, the RFD must be dma_sync'ed to maintain a consistent

   146  *	view from software and hardware.

   147  *

   148  *	Under typical operation, the  receive unit (RU) is start once,

   149  *	and the controller happily fills RFDs as frames arrive.  If

   150  *	replacement RFDs cannot be allocated, or the RU goes non-active,

   151  *	the RU must be restarted.  Frame arrival generates an interrupt,

   152  *	and Rx indication and re-allocation happen in the same context,

   153  *	therefore no locking is required.  A software-generated interrupt

   154  *	is generated from the watchdog to recover from a failed allocation

   155  *	senario where all Rx resources have been indicated and none re-

   156  *	placed.

   157  *

   158  *	V.   Miscellaneous

   159  *

   160  * 	VLAN offloading of tagging, stripping and filtering is not

   161  * 	supported, but driver will accommodate the extra 4-byte VLAN tag

   162  * 	for processing by upper layers.  Tx/Rx Checksum offloading is not

   163  * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is

   164  * 	not supported (hardware limitation).

   165  *

   166  * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.

   167  *

   168  * 	Thanks to JC (jchapman@katalix.com) for helping with

   169  * 	testing/troubleshooting the development driver.

   170  *

   171  * 	TODO:

   172  * 	o several entry points race with dev->close

   173  * 	o check for tx-no-resources/stop Q races with tx clean/wake Q

   174  *

   175  *	FIXES:

   176  * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>

   177  *	- Stratus87247: protect MDI control register manipulations

   178  */

   179 

   180 #include <linux/module.h>

   181 #include <linux/moduleparam.h>

   182 #include <linux/kernel.h>

   183 #include <linux/types.h>

   184 #include <linux/slab.h>

   185 #include <linux/delay.h>

   186 #include <linux/init.h>

   187 #include <linux/pci.h>

   188 #include <linux/dma-mapping.h>

   189 #include <linux/netdevice.h>

   190 #include <linux/etherdevice.h>

   191 #include <linux/mii.h>

   192 #include <linux/if_vlan.h>

   193 #include <linux/skbuff.h>

   194 #include <linux/ethtool.h>

   195 #include <linux/string.h>

   196 #include <asm/unaligned.h>

   197 

   198 // EtherCAT includes

   199 #include "../globals.h"

   200 #include "ecdev.h"

   201 

   202 #define DRV_NAME		"ec_e100"

   203 #define DRV_EXT		"-NAPI"

   204 #define DRV_VERSION		"3.5.10-k2"DRV_EXT

   205 #define DRV_DESCRIPTION		"EtherCAT-capable Intel(R) PRO/100 Network Driver"

   206 #define PFX			DRV_NAME ": "

   207 

   208 #define E100_WATCHDOG_PERIOD	(2 * HZ)

   209 #define E100_NAPI_WEIGHT	16

   210 

   211 MODULE_DESCRIPTION(DRV_DESCRIPTION);

   212 MODULE_AUTHOR("Florian Pose <fp@igh-essen.com>");

   213 MODULE_LICENSE("GPL");

   214 MODULE_VERSION(DRV_VERSION ", master " EC_MASTER_VERSION);

   215 

   216 // EtherCAT variables

   217 static int ec_device_index = -1;

   218 static int ec_device_master_index = 0;

   219 struct net_device *e100_ec_netdev = NULL;

   220 unsigned int e100_device_index = 0;

   221 

   222 // EtherCAT module parameters

   223 module_param(ec_device_index, int, -1);

   224 module_param(ec_device_master_index, int, 0);

   225 MODULE_PARM_DESC(ec_device_index,

   226                  "Index of the device reserved for EtherCAT.");

   227 MODULE_PARM_DESC(ec_device_master_index,

   228                  "Index of the EtherCAT master to register the device.");

   229 

   230 void e100_ec_poll(struct net_device *);

   231 

   232 static int debug = 3;

   233 static int eeprom_bad_csum_allow = 0;

   234 module_param(debug, int, 0);

   235 module_param(eeprom_bad_csum_allow, int, 0);

   236 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

   237 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");

   238 #define DPRINTK(nlevel, klevel, fmt, args...) \

   239 	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \

   240 	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \

   241 		__FUNCTION__ , ## args))

   242 

   243 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\

   244 	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \

   245 	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }

   246 static struct pci_device_id e100_id_table[] = {

   247 	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),

   248 	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),

   249 	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),

   250 	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),

   251 	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),

   252 	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),

   253 	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),

   254 	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),

   255 	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),

   256 	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),

   257 	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),

   258 	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),

   259 	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),

   260 	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),

   261 	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),

   262 	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),

   263 	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),

   264 	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),

   265 	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),

   266 	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),

   267 	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),

   268 	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),

   269 	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),

   270 	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),

   271 	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),

   272 	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),

   273 	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),

   274 	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),

   275 	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),

   276 	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),

   277 	INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),

   278 	INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),

   279 	INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),

   280 	INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),

   281 	INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),

   282 	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),

   283 	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),

   284 	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),

   285 	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),

   286 	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),

   287 	INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),

   288 	{ 0, }

   289 };

   290 // prevent from being loaded automatically

   291 //MODULE_DEVICE_TABLE(pci, e100_id_table);

   292 

   293 enum mac {

   294 	mac_82557_D100_A  = 0,

   295 	mac_82557_D100_B  = 1,

   296 	mac_82557_D100_C  = 2,

   297 	mac_82558_D101_A4 = 4,

   298 	mac_82558_D101_B0 = 5,

   299 	mac_82559_D101M   = 8,

   300 	mac_82559_D101S   = 9,

   301 	mac_82550_D102    = 12,

   302 	mac_82550_D102_C  = 13,

   303 	mac_82551_E       = 14,

   304 	mac_82551_F       = 15,

   305 	mac_82551_10      = 16,

   306 	mac_unknown       = 0xFF,

   307 };

   308 

   309 enum phy {

   310 	phy_100a     = 0x000003E0,

   311 	phy_100c     = 0x035002A8,

   312 	phy_82555_tx = 0x015002A8,

   313 	phy_nsc_tx   = 0x5C002000,

   314 	phy_82562_et = 0x033002A8,

   315 	phy_82562_em = 0x032002A8,

   316 	phy_82562_ek = 0x031002A8,

   317 	phy_82562_eh = 0x017002A8,

   318 	phy_unknown  = 0xFFFFFFFF,

   319 };

   320 

   321 /* CSR (Control/Status Registers) */

   322 struct csr {

   323 	struct {

   324 		u8 status;

   325 		u8 stat_ack;

   326 		u8 cmd_lo;

   327 		u8 cmd_hi;

   328 		u32 gen_ptr;

   329 	} scb;

   330 	u32 port;

   331 	u16 flash_ctrl;

   332 	u8 eeprom_ctrl_lo;

   333 	u8 eeprom_ctrl_hi;

   334 	u32 mdi_ctrl;

   335 	u32 rx_dma_count;

   336 };

   337 

   338 enum scb_status {

   339 	rus_ready        = 0x10,

   340 	rus_mask         = 0x3C,

   341 };

   342 

   343 enum ru_state  {

   344 	RU_SUSPENDED = 0,

   345 	RU_RUNNING	 = 1,

   346 	RU_UNINITIALIZED = -1,

   347 };

   348 

   349 enum scb_stat_ack {

   350 	stat_ack_not_ours    = 0x00,

   351 	stat_ack_sw_gen      = 0x04,

   352 	stat_ack_rnr         = 0x10,

   353 	stat_ack_cu_idle     = 0x20,

   354 	stat_ack_frame_rx    = 0x40,

   355 	stat_ack_cu_cmd_done = 0x80,

   356 	stat_ack_not_present = 0xFF,

   357 	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),

   358 	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),

   359 };

   360 

   361 enum scb_cmd_hi {

   362 	irq_mask_none = 0x00,

   363 	irq_mask_all  = 0x01,

   364 	irq_sw_gen    = 0x02,

   365 };

   366 

   367 enum scb_cmd_lo {

   368 	cuc_nop        = 0x00,

   369 	ruc_start      = 0x01,

   370 	ruc_load_base  = 0x06,

   371 	cuc_start      = 0x10,

   372 	cuc_resume     = 0x20,

   373 	cuc_dump_addr  = 0x40,

   374 	cuc_dump_stats = 0x50,

   375 	cuc_load_base  = 0x60,

   376 	cuc_dump_reset = 0x70,

   377 };

   378 

   379 enum cuc_dump {

   380 	cuc_dump_complete       = 0x0000A005,

   381 	cuc_dump_reset_complete = 0x0000A007,

   382 };

   383 

   384 enum port {

   385 	software_reset  = 0x0000,

   386 	selftest        = 0x0001,

   387 	selective_reset = 0x0002,

   388 };

   389 

   390 enum eeprom_ctrl_lo {

   391 	eesk = 0x01,

   392 	eecs = 0x02,

   393 	eedi = 0x04,

   394 	eedo = 0x08,

   395 };

   396 

   397 enum mdi_ctrl {

   398 	mdi_write = 0x04000000,

   399 	mdi_read  = 0x08000000,

   400 	mdi_ready = 0x10000000,

   401 };

   402 

   403 enum eeprom_op {

   404 	op_write = 0x05,

   405 	op_read  = 0x06,

   406 	op_ewds  = 0x10,

   407 	op_ewen  = 0x13,

   408 };

   409 

   410 enum eeprom_offsets {

   411 	eeprom_cnfg_mdix  = 0x03,

   412 	eeprom_id         = 0x0A,

   413 	eeprom_config_asf = 0x0D,

   414 	eeprom_smbus_addr = 0x90,

   415 };

   416 

   417 enum eeprom_cnfg_mdix {

   418 	eeprom_mdix_enabled = 0x0080,

   419 };

   420 

   421 enum eeprom_id {

   422 	eeprom_id_wol = 0x0020,

   423 };

   424 

   425 enum eeprom_config_asf {

   426 	eeprom_asf = 0x8000,

   427 	eeprom_gcl = 0x4000,

   428 };

   429 

   430 enum cb_status {

   431 	cb_complete = 0x8000,

   432 	cb_ok       = 0x2000,

   433 };

   434 

   435 enum cb_command {

   436 	cb_nop    = 0x0000,

   437 	cb_iaaddr = 0x0001,

   438 	cb_config = 0x0002,

   439 	cb_multi  = 0x0003,

   440 	cb_tx     = 0x0004,

   441 	cb_ucode  = 0x0005,

   442 	cb_dump   = 0x0006,

   443 	cb_tx_sf  = 0x0008,

   444 	cb_cid    = 0x1f00,

   445 	cb_i      = 0x2000,

   446 	cb_s      = 0x4000,

   447 	cb_el     = 0x8000,

   448 };

   449 

   450 struct rfd {

   451 	u16 status;

   452 	u16 command;

   453 	u32 link;

   454 	u32 rbd;

   455 	u16 actual_size;

   456 	u16 size;

   457 };

   458 

   459 struct rx {

   460 	struct rx *next, *prev;

   461 	struct sk_buff *skb;

   462 	dma_addr_t dma_addr;

   463 };

   464 

   465 #if defined(__BIG_ENDIAN_BITFIELD)

   466 #define X(a,b)	b,a

   467 #else

   468 #define X(a,b)	a,b

   469 #endif

   470 struct config {

   471 /*0*/	u8 X(byte_count:6, pad0:2);

   472 /*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);

   473 /*2*/	u8 adaptive_ifs;

   474 /*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),

   475 	   term_write_cache_line:1), pad3:4);

   476 /*4*/	u8 X(rx_dma_max_count:7, pad4:1);

   477 /*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);

   478 /*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),

   479 	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),

   480 	   rx_discard_overruns:1), rx_save_bad_frames:1);

   481 /*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),

   482 	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),

   483 	   tx_dynamic_tbd:1);

   484 /*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);

   485 /*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),

   486 	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);

   487 /*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),

   488 	   loopback:2);

   489 /*11*/	u8 X(linear_priority:3, pad11:5);

   490 /*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);

   491 /*13*/	u8 ip_addr_lo;

   492 /*14*/	u8 ip_addr_hi;

   493 /*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),

   494 	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),

   495 	   pad15_2:1), crs_or_cdt:1);

   496 /*16*/	u8 fc_delay_lo;

   497 /*17*/	u8 fc_delay_hi;

   498 /*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),

   499 	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);

   500 /*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),

   501 	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),

   502 	   full_duplex_force:1), full_duplex_pin:1);

   503 /*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);

   504 /*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);

   505 /*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);

   506 	u8 pad_d102[9];

   507 };

   508 

   509 #define E100_MAX_MULTICAST_ADDRS	64

   510 struct multi {

   511 	u16 count;

   512 	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];

   513 };

   514 

   515 /* Important: keep total struct u32-aligned */

   516 #define UCODE_SIZE			134

   517 struct cb {

   518 	u16 status;

   519 	u16 command;

   520 	u32 link;

   521 	union {

   522 		u8 iaaddr[ETH_ALEN];

   523 		u32 ucode[UCODE_SIZE];

   524 		struct config config;

   525 		struct multi multi;

   526 		struct {

   527 			u32 tbd_array;

   528 			u16 tcb_byte_count;

   529 			u8 threshold;

   530 			u8 tbd_count;

   531 			struct {

   532 				u32 buf_addr;

   533 				u16 size;

   534 				u16 eol;

   535 			} tbd;

   536 		} tcb;

   537 		u32 dump_buffer_addr;

   538 	} u;

   539 	struct cb *next, *prev;

   540 	dma_addr_t dma_addr;

   541 	struct sk_buff *skb;

   542 };

   543 

   544 enum loopback {

   545 	lb_none = 0, lb_mac = 1, lb_phy = 3,

   546 };

   547 

   548 struct stats {

   549 	u32 tx_good_frames, tx_max_collisions, tx_late_collisions,

   550 		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,

   551 		tx_multiple_collisions, tx_total_collisions;

   552 	u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,

   553 		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,

   554 		rx_short_frame_errors;

   555 	u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;

   556 	u16 xmt_tco_frames, rcv_tco_frames;

   557 	u32 complete;

   558 };

   559 

   560 struct mem {

   561 	struct {

   562 		u32 signature;

   563 		u32 result;

   564 	} selftest;

   565 	struct stats stats;

   566 	u8 dump_buf[596];

   567 };

   568 

   569 struct param_range {

   570 	u32 min;

   571 	u32 max;

   572 	u32 count;

   573 };

   574 

   575 struct params {

   576 	struct param_range rfds;

   577 	struct param_range cbs;

   578 };

   579 

   580 struct nic {

   581 	/* Begin: frequently used values: keep adjacent for cache effect */

   582 	u32 msg_enable				____cacheline_aligned;

   583 	struct net_device *netdev;

   584 	struct pci_dev *pdev;

   585 

   586 	struct rx *rxs				____cacheline_aligned;

   587 	struct rx *rx_to_use;

   588 	struct rx *rx_to_clean;

   589 	struct rfd blank_rfd;

   590 	enum ru_state ru_running;

   591 

   592 	spinlock_t cb_lock			____cacheline_aligned;

   593 	spinlock_t cmd_lock;

   594 	struct csr __iomem *csr;

   595 	enum scb_cmd_lo cuc_cmd;

   596 	unsigned int cbs_avail;

   597 	struct cb *cbs;

   598 	struct cb *cb_to_use;

   599 	struct cb *cb_to_send;

   600 	struct cb *cb_to_clean;

   601 	u16 tx_command;

   602 	/* End: frequently used values: keep adjacent for cache effect */

   603 

   604 	enum {

   605 		ich                = (1 << 0),

   606 		promiscuous        = (1 << 1),

   607 		multicast_all      = (1 << 2),

   608 		wol_magic          = (1 << 3),

   609 		ich_10h_workaround = (1 << 4),

   610 	} flags					____cacheline_aligned;

   611 

   612 	enum mac mac;

   613 	enum phy phy;

   614 	struct params params;

   615 	struct net_device_stats net_stats;

   616 	struct timer_list watchdog;

   617 	struct timer_list blink_timer;

   618 	struct mii_if_info mii;

   619 	struct work_struct tx_timeout_task;

   620 	enum loopback loopback;

   621 

   622 	struct mem *mem;

   623 	dma_addr_t dma_addr;

   624 

   625 	dma_addr_t cbs_dma_addr;

   626 	u8 adaptive_ifs;

   627 	u8 tx_threshold;

   628 	u32 tx_frames;

   629 	u32 tx_collisions;

   630 	u32 tx_deferred;

   631 	u32 tx_single_collisions;

   632 	u32 tx_multiple_collisions;

   633 	u32 tx_fc_pause;

   634 	u32 tx_tco_frames;

   635 

   636 	u32 rx_fc_pause;

   637 	u32 rx_fc_unsupported;

   638 	u32 rx_tco_frames;

   639 	u32 rx_over_length_errors;

   640 

   641 	u8 rev_id;

   642 	u16 leds;

   643 	u16 eeprom_wc;

   644 	u16 eeprom[256];

   645 	spinlock_t mdio_lock;

   646 

   647     u8 ethercat;

   648     ec_device_t *ecdev;

   649 };

   650 

   651 static inline void e100_write_flush(struct nic *nic)

   652 {

   653 	/* Flush previous PCI writes through intermediate bridges

   654 	 * by doing a benign read */

   655 	(void)readb(&nic->csr->scb.status);

   656 }

   657 

   658 static void e100_enable_irq(struct nic *nic)

   659 {

   660 	unsigned long flags;

   661 

   662 	spin_lock_irqsave(&nic->cmd_lock, flags);

   663 	writeb(irq_mask_none, &nic->csr->scb.cmd_hi);

   664 	e100_write_flush(nic);

   665 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   666 }

   667 

   668 static void e100_disable_irq(struct nic *nic)

   669 {

   670 	unsigned long flags;

   671 

   672 	spin_lock_irqsave(&nic->cmd_lock, flags);

   673 	writeb(irq_mask_all, &nic->csr->scb.cmd_hi);

   674 	e100_write_flush(nic);

   675 	spin_unlock_irqrestore(&nic->cmd_lock, flags);

   676 }

   677 

   678 static void e100_hw_reset(struct nic *nic)

   679 {

   680 	/* Put CU and RU into idle with a selective reset to get

   681 	 * device off of PCI bus */

   682 	writel(selective_reset, &nic->csr->port);

   683 	e100_write_flush(nic); udelay(20);

   684 

   685 	/* Now fully reset device */

   686 	writel(software_reset, &nic->csr->port);

   687 	e100_write_flush(nic); udelay(20);

   688 

   689 	/* Mask off our interrupt line - it's unmasked after reset */

   690 	e100_disable_irq(nic);

   691 }

   692 

   693 static int e100_self_test(struct nic *nic)

   694 {

   695 	u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);

   696 

   697 	/* Passing the self-test is a pretty good indication

   698 	 * that the device can DMA to/from host memory */

   699 

   700 	nic->mem->selftest.signature = 0;

   701 	nic->mem->selftest.result = 0xFFFFFFFF;

   702 

   703 	writel(selftest | dma_addr, &nic->csr->port);

   704 	e100_write_flush(nic);

   705 	/* Wait 10 msec for self-test to complete */

   706 	msleep(10);

   707 

   708 	/* Interrupts are enabled after self-test */

   709 	e100_disable_irq(nic);

   710 

   711 	/* Check results of self-test */

   712 	if(nic->mem->selftest.result != 0) {

   713 		DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",

   714 			nic->mem->selftest.result);

   715 		return -ETIMEDOUT;

   716 	}

   717 	if(nic->mem->selftest.signature == 0) {

   718 		DPRINTK(HW, ERR, "Self-test failed: timed out\n");

   719 		return -ETIMEDOUT;

   720 	}

   721 

   722 	return 0;

   723 }

   724 

   725 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)

   726 {

   727 	u32 cmd_addr_data[3];

   728 	u8 ctrl;

   729 	int i, j;

   730 

   731 	/* Three cmds: write/erase enable, write data, write/erase disable */

   732 	cmd_addr_data[0] = op_ewen << (addr_len - 2);

   733 	cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |

   734 		cpu_to_le16(data);

   735 	cmd_addr_data[2] = op_ewds << (addr_len - 2);

   736 

   737 	/* Bit-bang cmds to write word to eeprom */

   738 	for(j = 0; j < 3; j++) {

   739 

   740 		/* Chip select */

   741 		writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   742 		e100_write_flush(nic); udelay(4);

   743 

   744 		for(i = 31; i >= 0; i--) {

   745 			ctrl = (cmd_addr_data[j] & (1 << i)) ?

   746 				eecs | eedi : eecs;

   747 			writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   748 			e100_write_flush(nic); udelay(4);

   749 

   750 			writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   751 			e100_write_flush(nic); udelay(4);

   752 		}

   753 		/* Wait 10 msec for cmd to complete */

   754 		msleep(10);

   755 

   756 		/* Chip deselect */

   757 		writeb(0, &nic->csr->eeprom_ctrl_lo);

   758 		e100_write_flush(nic); udelay(4);

   759 	}

   760 };

   761 

   762 /* General technique stolen from the eepro100 driver - very clever */

   763 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)

   764 {

   765 	u32 cmd_addr_data;

   766 	u16 data = 0;

   767 	u8 ctrl;

   768 	int i;

   769 

   770 	cmd_addr_data = ((op_read << *addr_len) | addr) << 16;

   771 

   772 	/* Chip select */

   773 	writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);

   774 	e100_write_flush(nic); udelay(4);

   775 

   776 	/* Bit-bang to read word from eeprom */

   777 	for(i = 31; i >= 0; i--) {

   778 		ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;

   779 		writeb(ctrl, &nic->csr->eeprom_ctrl_lo);

   780 		e100_write_flush(nic); udelay(4);

   781 

   782 		writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);

   783 		e100_write_flush(nic); udelay(4);

   784 

   785 		/* Eeprom drives a dummy zero to EEDO after receiving

   786 		 * complete address.  Use this to adjust addr_len. */

   787 		ctrl = readb(&nic->csr->eeprom_ctrl_lo);

   788 		if(!(ctrl & eedo) && i > 16) {

   789 			*addr_len -= (i - 16);

   790 			i = 17;

   791 		}

   792 

   793 		data = (data << 1) | (ctrl & eedo ? 1 : 0);

   794 	}

   795 

   796 	/* Chip deselect */

   797 	writeb(0, &nic->csr->eeprom_ctrl_lo);

   798 	e100_write_flush(nic); udelay(4);

   799 

   800 	return le16_to_cpu(data);

   801 };

   802 

   803 /* Load entire EEPROM image into driver cache and validate checksum */

   804 static int e100_eeprom_load(struct nic *nic)

   805 {

   806 	u16 addr, addr_len = 8, checksum = 0;

   807 

   808 	/* Try reading with an 8-bit addr len to discover actual addr len */

   809 	e100_eeprom_read(nic, &addr_len, 0);

   810 	nic->eeprom_wc = 1 << addr_len;

   811 

   812 	for(addr = 0; addr < nic->eeprom_wc; addr++) {

   813 		nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);

   814 		if(addr < nic->eeprom_wc - 1)

   815 			checksum += cpu_to_le16(nic->eeprom[addr]);

   816 	}

   817 

   818 	/* The checksum, stored in the last word, is calculated such that

   819 	 * the sum of words should be 0xBABA */

   820 	checksum = le16_to_cpu(0xBABA - checksum);

   821 	if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {

   822 		DPRINTK(PROBE, ERR, "EEPROM corrupted\n");

   823 		if (!eeprom_bad_csum_allow)

   824 			return -EAGAIN;

   825 	}

   826 

   827 	return 0;

   828 }

   829 

   830 /* Save (portion of) driver EEPROM cache to device and update checksum */

   831 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)

   832 {

   833 	u16 addr, addr_len = 8, checksum = 0;

   834 

   835 	/* Try reading with an 8-bit addr len to discover actual addr len */

   836 	e100_eeprom_read(nic, &addr_len, 0);

   837 	nic->eeprom_wc = 1 << addr_len;

   838 

   839 	if(start + count >= nic->eeprom_wc)

   840 		return -EINVAL;

   841 

   842 	for(addr = start; addr < start + count; addr++)

   843 		e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);

   844 

   845 	/* The checksum, stored in the last word, is calculated such that

   846 	 * the sum of words should be 0xBABA */

   847 	for(addr = 0; addr < nic->eeprom_wc - 1; addr++)

   848 		checksum += cpu_to_le16(nic->eeprom[addr]);

   849 	nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);

   850 	e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,

   851 		nic->eeprom[nic->eeprom_wc - 1]);

   852 

   853 	return 0;

   854 }

   855 

   856 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */

   857 #define E100_WAIT_SCB_FAST 20       /* delay like the old code */

   858 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)

   859 {

   860 	unsigned long flags = 0;

   861 	unsigned int i;

   862 	int err = 0;

   863 

   864     if (!nic->ethercat)

   865         spin_lock_irqsave(&nic->cmd_lock, flags);

   866 

   867 	/* Previous command is accepted when SCB clears */

   868 	for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {

   869 		if(likely(!readb(&nic->csr->scb.cmd_lo)))

   870 			break;

   871 		cpu_relax();

   872 		if(unlikely(i > E100_WAIT_SCB_FAST))

   873 			udelay(5);

   874 	}

   875 	if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {

   876 		err = -EAGAIN;

   877 		goto err_unlock;

   878 	}

   879 

   880 	if(unlikely(cmd != cuc_resume))

   881 		writel(dma_addr, &nic->csr->scb.gen_ptr);

   882 	writeb(cmd, &nic->csr->scb.cmd_lo);

   883 

   884 err_unlock:

   885     if (!nic->ethercat)

   886         spin_unlock_irqrestore(&nic->cmd_lock, flags);

   887 

   888 	return err;

   889 }

   890 

   891 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,

   892 	void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))

   893 {

   894 	struct cb *cb;

   895 	unsigned long flags = 0;

   896 	int err = 0;

   897 

   898     if (!nic->ethercat)

   899         spin_lock_irqsave(&nic->cb_lock, flags);

   900 

   901 	if(unlikely(!nic->cbs_avail)) {

   902 		err = -ENOMEM;

   903 		goto err_unlock;

   904 	}

   905 

   906 	cb = nic->cb_to_use;

   907 	nic->cb_to_use = cb->next;

   908 	nic->cbs_avail--;

   909 	cb->skb = skb;

   910 

   911 	if(unlikely(!nic->cbs_avail))

   912 		err = -ENOSPC;

   913 

   914 	cb_prepare(nic, cb, skb);

   915 

   916 	/* Order is important otherwise we'll be in a race with h/w:

   917 	 * set S-bit in current first, then clear S-bit in previous. */

   918 	cb->command |= cpu_to_le16(cb_s);

   919 	wmb();

   920 	cb->prev->command &= cpu_to_le16(~cb_s);

   921 

   922 	while(nic->cb_to_send != nic->cb_to_use) {

   923 		if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,

   924 			nic->cb_to_send->dma_addr))) {

   925 			/* Ok, here's where things get sticky.  It's

   926 			 * possible that we can't schedule the command

   927 			 * because the controller is too busy, so

   928 			 * let's just queue the command and try again

   929 			 * when another command is scheduled. */

   930 			if(err == -ENOSPC) {

   931 				//request a reset

   932                 if (!nic->ethercat)

   933                     schedule_work(&nic->tx_timeout_task);

   934 			}

   935 			break;

   936 		} else {

   937 			nic->cuc_cmd = cuc_resume;

   938 			nic->cb_to_send = nic->cb_to_send->next;

   939 		}

   940 	}

   941 

   942 err_unlock:

   943     if (!nic->ethercat)

   944         spin_unlock_irqrestore(&nic->cb_lock, flags);

   945 

   946 	return err;

   947 }

   948 

   949 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)

   950 {

   951 	u32 data_out = 0;

   952 	unsigned int i;

   953 	unsigned long flags;

   954 

   955 

   956 	/*

   957 	 * Stratus87247: we shouldn't be writing the MDI control

   958 	 * register until the Ready bit shows True.  Also, since

   959 	 * manipulation of the MDI control registers is a multi-step

   960 	 * procedure it should be done under lock.

   961 	 */

   962 	spin_lock_irqsave(&nic->mdio_lock, flags);

   963 	for (i = 100; i; --i) {

   964 		if (readl(&nic->csr->mdi_ctrl) & mdi_ready)

   965 			break;

   966 		udelay(20);

   967 	}

   968 	if (unlikely(!i)) {

   969 		printk("e100.mdio_ctrl(%s) won't go Ready\n",

   970 			nic->netdev->name );

   971 		spin_unlock_irqrestore(&nic->mdio_lock, flags);

   972 		return 0;		/* No way to indicate timeout error */

   973 	}

   974 	writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

   975 

   976 	for (i = 0; i < 100; i++) {

   977 		udelay(20);

   978 		if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)

   979 			break;

   980 	}

   981 	spin_unlock_irqrestore(&nic->mdio_lock, flags);

   982 	DPRINTK(HW, DEBUG,

   983 		"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",

   984 		dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);

   985 	return (u16)data_out;

   986 }

   987 

   988 static int mdio_read(struct net_device *netdev, int addr, int reg)

   989 {

   990 	return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);

   991 }

   992 

   993 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)

   994 {

   995 	mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);

   996 }

   997 

   998 static void e100_get_defaults(struct nic *nic)

   999 {

  1000 	struct param_range rfds = { .min = 16, .max = 256, .count = 256 };

  1001 	struct param_range cbs  = { .min = 64, .max = 256, .count = 128 };

  1002 

  1003 	pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);

  1004 	/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */

  1005 	nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;

  1006 	if(nic->mac == mac_unknown)

  1007 		nic->mac = mac_82557_D100_A;

  1008 

  1009 	nic->params.rfds = rfds;

  1010 	nic->params.cbs = cbs;

  1011 

  1012 	/* Quadwords to DMA into FIFO before starting frame transmit */

  1013 	nic->tx_threshold = 0xE0;

  1014 

  1015 	/* no interrupt for every tx completion, delay = 256us if not 557*/

  1016 	nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |

  1017 		((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));

  1018 

  1019 	/* Template for a freshly allocated RFD */

  1020 	nic->blank_rfd.command = cpu_to_le16(cb_el);

  1021 	nic->blank_rfd.rbd = 0xFFFFFFFF;

  1022 	nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);

  1023 

  1024 	/* MII setup */

  1025 	nic->mii.phy_id_mask = 0x1F;

  1026 	nic->mii.reg_num_mask = 0x1F;

  1027 	nic->mii.dev = nic->netdev;

  1028 	nic->mii.mdio_read = mdio_read;

  1029 	nic->mii.mdio_write = mdio_write;

  1030 }

  1031 

  1032 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)

  1033 {

  1034 	struct config *config = &cb->u.config;

  1035 	u8 *c = (u8 *)config;

  1036 

  1037 	cb->command = cpu_to_le16(cb_config);

  1038 

  1039 	memset(config, 0, sizeof(struct config));

  1040 

  1041 	config->byte_count = 0x16;		/* bytes in this struct */

  1042 	config->rx_fifo_limit = 0x8;		/* bytes in FIFO before DMA */

  1043 	config->direct_rx_dma = 0x1;		/* reserved */

  1044 	config->standard_tcb = 0x1;		/* 1=standard, 0=extended */

  1045 	config->standard_stat_counter = 0x1;	/* 1=standard, 0=extended */

  1046 	config->rx_discard_short_frames = 0x1;	/* 1=discard, 0=pass */

  1047 	config->tx_underrun_retry = 0x3;	/* # of underrun retries */

  1048 	config->mii_mode = 0x1;			/* 1=MII mode, 0=503 mode */

  1049 	config->pad10 = 0x6;

  1050 	config->no_source_addr_insertion = 0x1;	/* 1=no, 0=yes */

  1051 	config->preamble_length = 0x2;		/* 0=1, 1=3, 2=7, 3=15 bytes */

  1052 	config->ifs = 0x6;			/* x16 = inter frame spacing */

  1053 	config->ip_addr_hi = 0xF2;		/* ARP IP filter - not used */

  1054 	config->pad15_1 = 0x1;

  1055 	config->pad15_2 = 0x1;

  1056 	config->crs_or_cdt = 0x0;		/* 0=CRS only, 1=CRS or CDT */

  1057 	config->fc_delay_hi = 0x40;		/* time delay for fc frame */

  1058 	config->tx_padding = 0x1;		/* 1=pad short frames */

  1059 	config->fc_priority_threshold = 0x7;	/* 7=priority fc disabled */

  1060 	config->pad18 = 0x1;

  1061 	config->full_duplex_pin = 0x1;		/* 1=examine FDX# pin */

  1062 	config->pad20_1 = 0x1F;

  1063 	config->fc_priority_location = 0x1;	/* 1=byte#31, 0=byte#19 */

  1064 	config->pad21_1 = 0x5;

  1065 

  1066 	config->adaptive_ifs = nic->adaptive_ifs;

  1067 	config->loopback = nic->loopback;

  1068 

  1069 	if(nic->mii.force_media && nic->mii.full_duplex)

  1070 		config->full_duplex_force = 0x1;	/* 1=force, 0=auto */

  1071 

  1072 	if(nic->flags & promiscuous || nic->loopback) {

  1073 		config->rx_save_bad_frames = 0x1;	/* 1=save, 0=discard */

  1074 		config->rx_discard_short_frames = 0x0;	/* 1=discard, 0=save */

  1075 		config->promiscuous_mode = 0x1;		/* 1=on, 0=off */

  1076 	}

  1077 

  1078 	if(nic->flags & multicast_all)

  1079 		config->multicast_all = 0x1;		/* 1=accept, 0=no */

  1080 

  1081 	/* disable WoL when up */

  1082 	if (nic->ethercat ||

  1083             (netif_running(nic->netdev) || !(nic->flags & wol_magic)))

  1084 		config->magic_packet_disable = 0x1;	/* 1=off, 0=on */

  1085 

  1086 	if(nic->mac >= mac_82558_D101_A4) {

  1087 		config->fc_disable = 0x1;	/* 1=Tx fc off, 0=Tx fc on */

  1088 		config->mwi_enable = 0x1;	/* 1=enable, 0=disable */

  1089 		config->standard_tcb = 0x0;	/* 1=standard, 0=extended */

  1090 		config->rx_long_ok = 0x1;	/* 1=VLANs ok, 0=standard */

  1091 		if(nic->mac >= mac_82559_D101M)

  1092 			config->tno_intr = 0x1;		/* TCO stats enable */

  1093 		else

  1094 			config->standard_stat_counter = 0x0;

  1095 	}

  1096 

  1097 	DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1098 		c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);

  1099 	DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1100 		c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);

  1101 	DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",

  1102 		c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);

  1103 }

  1104 

  1105 /********************************************************/

  1106 /*  Micro code for 8086:1229 Rev 8                      */

  1107 /********************************************************/

  1108 

  1109 /*  Parameter values for the D101M B-step  */

  1110 #define D101M_CPUSAVER_TIMER_DWORD		78

  1111 #define D101M_CPUSAVER_BUNDLE_DWORD		65

  1112 #define D101M_CPUSAVER_MIN_SIZE_DWORD		126

  1113 

  1114 #define D101M_B_RCVBUNDLE_UCODE \

  1115 {\

  1116 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \

  1117 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \

  1118 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \

  1119 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \

  1120 0x00380438, 0x00000000, 0x00140000, 0x00380555, \

  1121 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \

  1122 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \

  1123 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \

  1124 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \

  1125 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \

  1126 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1127 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \

  1128 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \

  1129 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \

  1130 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \

  1131 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \

  1132 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \

  1133 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1134 0x00000000, 0x00000000, 0x00000000, 0x00000000, \

  1135 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \