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1 /* |
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2 * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
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3 * |
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4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> |
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5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> |
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6 * Copyright (c) a lot of people too. Please respect their work. |
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7 * |
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8 * See MAINTAINERS file for support contact information. |
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9 */ |
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10 |
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11 #include <linux/module.h> |
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12 #include <linux/moduleparam.h> |
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13 #include <linux/pci.h> |
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14 #include <linux/netdevice.h> |
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15 #include <linux/etherdevice.h> |
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16 #include <linux/delay.h> |
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17 #include <linux/ethtool.h> |
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18 #include <linux/mii.h> |
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19 #include <linux/if_vlan.h> |
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20 #include <linux/crc32.h> |
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21 #include <linux/in.h> |
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22 #include <linux/ip.h> |
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23 #include <linux/tcp.h> |
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24 #include <linux/init.h> |
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25 #include <linux/interrupt.h> |
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26 #include <linux/dma-mapping.h> |
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27 #include <linux/pm_runtime.h> |
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28 #include <linux/firmware.h> |
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29 #include <linux/pci-aspm.h> |
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30 #include <linux/prefetch.h> |
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31 |
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32 #include <asm/io.h> |
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33 #include <asm/irq.h> |
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34 |
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35 #include "../globals.h" |
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36 #include "ecdev.h" |
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37 |
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38 #define RTL8169_VERSION "2.3LK-NAPI" |
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39 #define MODULENAME "ec_r8169" |
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40 #define PFX MODULENAME ": " |
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41 |
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42 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
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43 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
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44 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
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45 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" |
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46 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
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47 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
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48 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" |
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49 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
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50 |
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51 #ifdef RTL8169_DEBUG |
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52 #define assert(expr) \ |
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53 if (!(expr)) { \ |
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54 printk( "Assertion failed! %s,%s,%s,line=%d\n", \ |
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55 #expr,__FILE__,__func__,__LINE__); \ |
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56 } |
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57 #define dprintk(fmt, args...) \ |
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58 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) |
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59 #else |
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60 #define assert(expr) do {} while (0) |
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61 #define dprintk(fmt, args...) do {} while (0) |
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62 #endif /* RTL8169_DEBUG */ |
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63 |
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64 #define R8169_MSG_DEFAULT \ |
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65 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
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66 |
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67 #define TX_SLOTS_AVAIL(tp) \ |
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68 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) |
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69 |
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70 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ |
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71 #define TX_FRAGS_READY_FOR(tp,nr_frags) \ |
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72 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) |
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73 |
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74 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
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75 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ |
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76 static const int multicast_filter_limit = 32; |
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77 |
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78 #define MAX_READ_REQUEST_SHIFT 12 |
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79 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
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80 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
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81 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
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82 |
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83 #define R8169_REGS_SIZE 256 |
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84 #define R8169_NAPI_WEIGHT 64 |
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85 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
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86 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
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87 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ |
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88 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
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89 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
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90 |
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91 #define RTL8169_TX_TIMEOUT (6*HZ) |
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92 #define RTL8169_PHY_TIMEOUT (10*HZ) |
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93 |
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94 #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
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95 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
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96 #define RTL_EEPROM_SIG_ADDR 0x0000 |
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97 |
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98 /* write/read MMIO register */ |
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99 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
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100 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
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101 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
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102 #define RTL_R8(reg) readb (ioaddr + (reg)) |
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103 #define RTL_R16(reg) readw (ioaddr + (reg)) |
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104 #define RTL_R32(reg) readl (ioaddr + (reg)) |
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105 |
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106 enum mac_version { |
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107 RTL_GIGA_MAC_VER_01 = 0, |
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108 RTL_GIGA_MAC_VER_02, |
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109 RTL_GIGA_MAC_VER_03, |
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110 RTL_GIGA_MAC_VER_04, |
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111 RTL_GIGA_MAC_VER_05, |
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112 RTL_GIGA_MAC_VER_06, |
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113 RTL_GIGA_MAC_VER_07, |
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114 RTL_GIGA_MAC_VER_08, |
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115 RTL_GIGA_MAC_VER_09, |
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116 RTL_GIGA_MAC_VER_10, |
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117 RTL_GIGA_MAC_VER_11, |
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118 RTL_GIGA_MAC_VER_12, |
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119 RTL_GIGA_MAC_VER_13, |
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120 RTL_GIGA_MAC_VER_14, |
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121 RTL_GIGA_MAC_VER_15, |
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122 RTL_GIGA_MAC_VER_16, |
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123 RTL_GIGA_MAC_VER_17, |
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124 RTL_GIGA_MAC_VER_18, |
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125 RTL_GIGA_MAC_VER_19, |
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126 RTL_GIGA_MAC_VER_20, |
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127 RTL_GIGA_MAC_VER_21, |
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128 RTL_GIGA_MAC_VER_22, |
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129 RTL_GIGA_MAC_VER_23, |
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130 RTL_GIGA_MAC_VER_24, |
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131 RTL_GIGA_MAC_VER_25, |
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132 RTL_GIGA_MAC_VER_26, |
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133 RTL_GIGA_MAC_VER_27, |
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134 RTL_GIGA_MAC_VER_28, |
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135 RTL_GIGA_MAC_VER_29, |
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136 RTL_GIGA_MAC_VER_30, |
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137 RTL_GIGA_MAC_VER_31, |
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138 RTL_GIGA_MAC_VER_32, |
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139 RTL_GIGA_MAC_VER_33, |
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140 RTL_GIGA_MAC_VER_34, |
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141 RTL_GIGA_MAC_VER_35, |
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142 RTL_GIGA_MAC_VER_36, |
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143 RTL_GIGA_MAC_NONE = 0xff, |
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144 }; |
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145 |
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146 enum rtl_tx_desc_version { |
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147 RTL_TD_0 = 0, |
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148 RTL_TD_1 = 1, |
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149 }; |
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150 |
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151 #define JUMBO_1K ETH_DATA_LEN |
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152 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) |
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153 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) |
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154 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) |
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155 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) |
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156 |
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157 #define _R(NAME,TD,FW,SZ,B) { \ |
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158 .name = NAME, \ |
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159 .txd_version = TD, \ |
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160 .fw_name = FW, \ |
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161 .jumbo_max = SZ, \ |
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162 .jumbo_tx_csum = B \ |
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163 } |
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164 |
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165 static const struct { |
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166 const char *name; |
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167 enum rtl_tx_desc_version txd_version; |
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168 const char *fw_name; |
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169 u16 jumbo_max; |
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170 bool jumbo_tx_csum; |
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171 } rtl_chip_infos[] = { |
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172 /* PCI devices. */ |
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173 [RTL_GIGA_MAC_VER_01] = |
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174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
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175 [RTL_GIGA_MAC_VER_02] = |
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176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
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177 [RTL_GIGA_MAC_VER_03] = |
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178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
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179 [RTL_GIGA_MAC_VER_04] = |
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180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
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181 [RTL_GIGA_MAC_VER_05] = |
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182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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183 [RTL_GIGA_MAC_VER_06] = |
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184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
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185 /* PCI-E devices. */ |
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186 [RTL_GIGA_MAC_VER_07] = |
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187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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188 [RTL_GIGA_MAC_VER_08] = |
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189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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190 [RTL_GIGA_MAC_VER_09] = |
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191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
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192 [RTL_GIGA_MAC_VER_10] = |
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193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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194 [RTL_GIGA_MAC_VER_11] = |
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195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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196 [RTL_GIGA_MAC_VER_12] = |
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197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
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198 [RTL_GIGA_MAC_VER_13] = |
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199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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200 [RTL_GIGA_MAC_VER_14] = |
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201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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202 [RTL_GIGA_MAC_VER_15] = |
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203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
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204 [RTL_GIGA_MAC_VER_16] = |
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205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
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206 [RTL_GIGA_MAC_VER_17] = |
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207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false), |
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208 [RTL_GIGA_MAC_VER_18] = |
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209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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210 [RTL_GIGA_MAC_VER_19] = |
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211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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212 [RTL_GIGA_MAC_VER_20] = |
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213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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214 [RTL_GIGA_MAC_VER_21] = |
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215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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216 [RTL_GIGA_MAC_VER_22] = |
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217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
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218 [RTL_GIGA_MAC_VER_23] = |
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219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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220 [RTL_GIGA_MAC_VER_24] = |
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221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
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222 [RTL_GIGA_MAC_VER_25] = |
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223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
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224 JUMBO_9K, false), |
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225 [RTL_GIGA_MAC_VER_26] = |
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226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
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227 JUMBO_9K, false), |
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228 [RTL_GIGA_MAC_VER_27] = |
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229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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230 [RTL_GIGA_MAC_VER_28] = |
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231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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232 [RTL_GIGA_MAC_VER_29] = |
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233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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234 JUMBO_1K, true), |
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235 [RTL_GIGA_MAC_VER_30] = |
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236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
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237 JUMBO_1K, true), |
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238 [RTL_GIGA_MAC_VER_31] = |
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239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
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240 [RTL_GIGA_MAC_VER_32] = |
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241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
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242 JUMBO_9K, false), |
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243 [RTL_GIGA_MAC_VER_33] = |
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244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
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245 JUMBO_9K, false), |
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246 [RTL_GIGA_MAC_VER_34] = |
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247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
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248 JUMBO_9K, false), |
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249 [RTL_GIGA_MAC_VER_35] = |
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250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
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251 JUMBO_9K, false), |
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252 [RTL_GIGA_MAC_VER_36] = |
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253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
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254 JUMBO_9K, false), |
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255 }; |
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256 #undef _R |
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257 |
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258 enum cfg_version { |
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259 RTL_CFG_0 = 0x00, |
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260 RTL_CFG_1, |
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261 RTL_CFG_2 |
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262 }; |
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263 |
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264 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
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265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
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266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
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267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
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268 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
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269 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
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270 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
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271 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
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272 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
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273 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
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274 { PCI_VENDOR_ID_LINKSYS, 0x1032, |
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275 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
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276 { 0x0001, 0x8168, |
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277 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, |
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278 {0,}, |
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279 }; |
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280 |
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281 /* prevent driver from being loaded automatically */ |
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282 //MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); |
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283 |
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284 static int rx_buf_sz = 16383; |
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285 static int use_dac; |
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286 static struct { |
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287 u32 msg_enable; |
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288 } debug = { -1 }; |
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289 |
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290 enum rtl_registers { |
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291 MAC0 = 0, /* Ethernet hardware address. */ |
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292 MAC4 = 4, |
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293 MAR0 = 8, /* Multicast filter. */ |
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294 CounterAddrLow = 0x10, |
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295 CounterAddrHigh = 0x14, |
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296 TxDescStartAddrLow = 0x20, |
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297 TxDescStartAddrHigh = 0x24, |
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298 TxHDescStartAddrLow = 0x28, |
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299 TxHDescStartAddrHigh = 0x2c, |
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300 FLASH = 0x30, |
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301 ERSR = 0x36, |
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302 ChipCmd = 0x37, |
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303 TxPoll = 0x38, |
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304 IntrMask = 0x3c, |
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305 IntrStatus = 0x3e, |
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306 |
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307 TxConfig = 0x40, |
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308 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
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309 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ |
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310 |
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311 RxConfig = 0x44, |
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312 #define RX128_INT_EN (1 << 15) /* 8111c and later */ |
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313 #define RX_MULTI_EN (1 << 14) /* 8111c only */ |
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314 #define RXCFG_FIFO_SHIFT 13 |
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315 /* No threshold before first PCI xfer */ |
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316 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) |
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317 #define RXCFG_DMA_SHIFT 8 |
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318 /* Unlimited maximum PCI burst. */ |
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319 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) |
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320 |
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321 RxMissed = 0x4c, |
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322 Cfg9346 = 0x50, |
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323 Config0 = 0x51, |
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324 Config1 = 0x52, |
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325 Config2 = 0x53, |
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326 #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
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327 |
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328 Config3 = 0x54, |
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329 Config4 = 0x55, |
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330 Config5 = 0x56, |
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331 MultiIntr = 0x5c, |
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332 PHYAR = 0x60, |
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333 PHYstatus = 0x6c, |
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334 RxMaxSize = 0xda, |
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335 CPlusCmd = 0xe0, |
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336 IntrMitigate = 0xe2, |
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337 RxDescAddrLow = 0xe4, |
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338 RxDescAddrHigh = 0xe8, |
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339 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
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340 |
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341 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ |
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342 |
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343 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ |
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344 |
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345 #define TxPacketMax (8064 >> 7) |
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346 #define EarlySize 0x27 |
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347 |
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348 FuncEvent = 0xf0, |
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349 FuncEventMask = 0xf4, |
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350 FuncPresetState = 0xf8, |
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351 FuncForceEvent = 0xfc, |
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352 }; |
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353 |
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354 enum rtl8110_registers { |
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355 TBICSR = 0x64, |
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356 TBI_ANAR = 0x68, |
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357 TBI_LPAR = 0x6a, |
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358 }; |
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359 |
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360 enum rtl8168_8101_registers { |
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361 CSIDR = 0x64, |
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362 CSIAR = 0x68, |
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363 #define CSIAR_FLAG 0x80000000 |
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364 #define CSIAR_WRITE_CMD 0x80000000 |
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365 #define CSIAR_BYTE_ENABLE 0x0f |
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366 #define CSIAR_BYTE_ENABLE_SHIFT 12 |
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367 #define CSIAR_ADDR_MASK 0x0fff |
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368 PMCH = 0x6f, |
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369 EPHYAR = 0x80, |
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370 #define EPHYAR_FLAG 0x80000000 |
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371 #define EPHYAR_WRITE_CMD 0x80000000 |
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372 #define EPHYAR_REG_MASK 0x1f |
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373 #define EPHYAR_REG_SHIFT 16 |
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374 #define EPHYAR_DATA_MASK 0xffff |
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375 DLLPR = 0xd0, |
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376 #define PFM_EN (1 << 6) |
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377 DBG_REG = 0xd1, |
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378 #define FIX_NAK_1 (1 << 4) |
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379 #define FIX_NAK_2 (1 << 3) |
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380 TWSI = 0xd2, |
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381 MCU = 0xd3, |
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382 #define NOW_IS_OOB (1 << 7) |
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383 #define EN_NDP (1 << 3) |
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384 #define EN_OOB_RESET (1 << 2) |
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385 EFUSEAR = 0xdc, |
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386 #define EFUSEAR_FLAG 0x80000000 |
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387 #define EFUSEAR_WRITE_CMD 0x80000000 |
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388 #define EFUSEAR_READ_CMD 0x00000000 |
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389 #define EFUSEAR_REG_MASK 0x03ff |
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390 #define EFUSEAR_REG_SHIFT 8 |
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391 #define EFUSEAR_DATA_MASK 0xff |
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392 }; |
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393 |
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394 enum rtl8168_registers { |
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395 LED_FREQ = 0x1a, |
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396 EEE_LED = 0x1b, |
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397 ERIDR = 0x70, |
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398 ERIAR = 0x74, |
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399 #define ERIAR_FLAG 0x80000000 |
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400 #define ERIAR_WRITE_CMD 0x80000000 |
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401 #define ERIAR_READ_CMD 0x00000000 |
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402 #define ERIAR_ADDR_BYTE_ALIGN 4 |
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403 #define ERIAR_TYPE_SHIFT 16 |
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404 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
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405 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) |
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406 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) |
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407 #define ERIAR_MASK_SHIFT 12 |
|
408 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) |
|
409 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) |
|
410 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
|
411 EPHY_RXER_NUM = 0x7c, |
|
412 OCPDR = 0xb0, /* OCP GPHY access */ |
|
413 #define OCPDR_WRITE_CMD 0x80000000 |
|
414 #define OCPDR_READ_CMD 0x00000000 |
|
415 #define OCPDR_REG_MASK 0x7f |
|
416 #define OCPDR_GPHY_REG_SHIFT 16 |
|
417 #define OCPDR_DATA_MASK 0xffff |
|
418 OCPAR = 0xb4, |
|
419 #define OCPAR_FLAG 0x80000000 |
|
420 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 |
|
421 #define OCPAR_GPHY_READ_CMD 0x0000f060 |
|
422 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
|
423 MISC = 0xf0, /* 8168e only. */ |
|
424 #define TXPLA_RST (1 << 29) |
|
425 #define PWM_EN (1 << 22) |
|
426 }; |
|
427 |
|
428 enum rtl_register_content { |
|
429 /* InterruptStatusBits */ |
|
430 SYSErr = 0x8000, |
|
431 PCSTimeout = 0x4000, |
|
432 SWInt = 0x0100, |
|
433 TxDescUnavail = 0x0080, |
|
434 RxFIFOOver = 0x0040, |
|
435 LinkChg = 0x0020, |
|
436 RxOverflow = 0x0010, |
|
437 TxErr = 0x0008, |
|
438 TxOK = 0x0004, |
|
439 RxErr = 0x0002, |
|
440 RxOK = 0x0001, |
|
441 |
|
442 /* RxStatusDesc */ |
|
443 RxBOVF = (1 << 24), |
|
444 RxFOVF = (1 << 23), |
|
445 RxRWT = (1 << 22), |
|
446 RxRES = (1 << 21), |
|
447 RxRUNT = (1 << 20), |
|
448 RxCRC = (1 << 19), |
|
449 |
|
450 /* ChipCmdBits */ |
|
451 StopReq = 0x80, |
|
452 CmdReset = 0x10, |
|
453 CmdRxEnb = 0x08, |
|
454 CmdTxEnb = 0x04, |
|
455 RxBufEmpty = 0x01, |
|
456 |
|
457 /* TXPoll register p.5 */ |
|
458 HPQ = 0x80, /* Poll cmd on the high prio queue */ |
|
459 NPQ = 0x40, /* Poll cmd on the low prio queue */ |
|
460 FSWInt = 0x01, /* Forced software interrupt */ |
|
461 |
|
462 /* Cfg9346Bits */ |
|
463 Cfg9346_Lock = 0x00, |
|
464 Cfg9346_Unlock = 0xc0, |
|
465 |
|
466 /* rx_mode_bits */ |
|
467 AcceptErr = 0x20, |
|
468 AcceptRunt = 0x10, |
|
469 AcceptBroadcast = 0x08, |
|
470 AcceptMulticast = 0x04, |
|
471 AcceptMyPhys = 0x02, |
|
472 AcceptAllPhys = 0x01, |
|
473 #define RX_CONFIG_ACCEPT_MASK 0x3f |
|
474 |
|
475 /* TxConfigBits */ |
|
476 TxInterFrameGapShift = 24, |
|
477 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ |
|
478 |
|
479 /* Config1 register p.24 */ |
|
480 LEDS1 = (1 << 7), |
|
481 LEDS0 = (1 << 6), |
|
482 Speed_down = (1 << 4), |
|
483 MEMMAP = (1 << 3), |
|
484 IOMAP = (1 << 2), |
|
485 VPD = (1 << 1), |
|
486 PMEnable = (1 << 0), /* Power Management Enable */ |
|
487 |
|
488 /* Config2 register p. 25 */ |
|
489 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
|
490 PCI_Clock_66MHz = 0x01, |
|
491 PCI_Clock_33MHz = 0x00, |
|
492 |
|
493 /* Config3 register p.25 */ |
|
494 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ |
|
495 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ |
|
496 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
|
497 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
|
498 |
|
499 /* Config4 register */ |
|
500 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ |
|
501 |
|
502 /* Config5 register p.27 */ |
|
503 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
|
504 MWF = (1 << 5), /* Accept Multicast wakeup frame */ |
|
505 UWF = (1 << 4), /* Accept Unicast wakeup frame */ |
|
506 Spi_en = (1 << 3), |
|
507 LanWake = (1 << 1), /* LanWake enable/disable */ |
|
508 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
|
509 |
|
510 /* TBICSR p.28 */ |
|
511 TBIReset = 0x80000000, |
|
512 TBILoopback = 0x40000000, |
|
513 TBINwEnable = 0x20000000, |
|
514 TBINwRestart = 0x10000000, |
|
515 TBILinkOk = 0x02000000, |
|
516 TBINwComplete = 0x01000000, |
|
517 |
|
518 /* CPlusCmd p.31 */ |
|
519 EnableBist = (1 << 15), // 8168 8101 |
|
520 Mac_dbgo_oe = (1 << 14), // 8168 8101 |
|
521 Normal_mode = (1 << 13), // unused |
|
522 Force_half_dup = (1 << 12), // 8168 8101 |
|
523 Force_rxflow_en = (1 << 11), // 8168 8101 |
|
524 Force_txflow_en = (1 << 10), // 8168 8101 |
|
525 Cxpl_dbg_sel = (1 << 9), // 8168 8101 |
|
526 ASF = (1 << 8), // 8168 8101 |
|
527 PktCntrDisable = (1 << 7), // 8168 8101 |
|
528 Mac_dbgo_sel = 0x001c, // 8168 |
|
529 RxVlan = (1 << 6), |
|
530 RxChkSum = (1 << 5), |
|
531 PCIDAC = (1 << 4), |
|
532 PCIMulRW = (1 << 3), |
|
533 INTT_0 = 0x0000, // 8168 |
|
534 INTT_1 = 0x0001, // 8168 |
|
535 INTT_2 = 0x0002, // 8168 |
|
536 INTT_3 = 0x0003, // 8168 |
|
537 |
|
538 /* rtl8169_PHYstatus */ |
|
539 TBI_Enable = 0x80, |
|
540 TxFlowCtrl = 0x40, |
|
541 RxFlowCtrl = 0x20, |
|
542 _1000bpsF = 0x10, |
|
543 _100bps = 0x08, |
|
544 _10bps = 0x04, |
|
545 LinkStatus = 0x02, |
|
546 FullDup = 0x01, |
|
547 |
|
548 /* _TBICSRBit */ |
|
549 TBILinkOK = 0x02000000, |
|
550 |
|
551 /* DumpCounterCommand */ |
|
552 CounterDump = 0x8, |
|
553 }; |
|
554 |
|
555 enum rtl_desc_bit { |
|
556 /* First doubleword. */ |
|
557 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
|
558 RingEnd = (1 << 30), /* End of descriptor ring */ |
|
559 FirstFrag = (1 << 29), /* First segment of a packet */ |
|
560 LastFrag = (1 << 28), /* Final segment of a packet */ |
|
561 }; |
|
562 |
|
563 /* Generic case. */ |
|
564 enum rtl_tx_desc_bit { |
|
565 /* First doubleword. */ |
|
566 TD_LSO = (1 << 27), /* Large Send Offload */ |
|
567 #define TD_MSS_MAX 0x07ffu /* MSS value */ |
|
568 |
|
569 /* Second doubleword. */ |
|
570 TxVlanTag = (1 << 17), /* Add VLAN tag */ |
|
571 }; |
|
572 |
|
573 /* 8169, 8168b and 810x except 8102e. */ |
|
574 enum rtl_tx_desc_bit_0 { |
|
575 /* First doubleword. */ |
|
576 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ |
|
577 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ |
|
578 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ |
|
579 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ |
|
580 }; |
|
581 |
|
582 /* 8102e, 8168c and beyond. */ |
|
583 enum rtl_tx_desc_bit_1 { |
|
584 /* Second doubleword. */ |
|
585 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
|
586 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ |
|
587 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
|
588 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ |
|
589 }; |
|
590 |
|
591 static const struct rtl_tx_desc_info { |
|
592 struct { |
|
593 u32 udp; |
|
594 u32 tcp; |
|
595 } checksum; |
|
596 u16 mss_shift; |
|
597 u16 opts_offset; |
|
598 } tx_desc_info [] = { |
|
599 [RTL_TD_0] = { |
|
600 .checksum = { |
|
601 .udp = TD0_IP_CS | TD0_UDP_CS, |
|
602 .tcp = TD0_IP_CS | TD0_TCP_CS |
|
603 }, |
|
604 .mss_shift = TD0_MSS_SHIFT, |
|
605 .opts_offset = 0 |
|
606 }, |
|
607 [RTL_TD_1] = { |
|
608 .checksum = { |
|
609 .udp = TD1_IP_CS | TD1_UDP_CS, |
|
610 .tcp = TD1_IP_CS | TD1_TCP_CS |
|
611 }, |
|
612 .mss_shift = TD1_MSS_SHIFT, |
|
613 .opts_offset = 1 |
|
614 } |
|
615 }; |
|
616 |
|
617 enum rtl_rx_desc_bit { |
|
618 /* Rx private */ |
|
619 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ |
|
620 PID0 = (1 << 17), /* Protocol ID bit 2/2 */ |
|
621 |
|
622 #define RxProtoUDP (PID1) |
|
623 #define RxProtoTCP (PID0) |
|
624 #define RxProtoIP (PID1 | PID0) |
|
625 #define RxProtoMask RxProtoIP |
|
626 |
|
627 IPFail = (1 << 16), /* IP checksum failed */ |
|
628 UDPFail = (1 << 15), /* UDP/IP checksum failed */ |
|
629 TCPFail = (1 << 14), /* TCP/IP checksum failed */ |
|
630 RxVlanTag = (1 << 16), /* VLAN tag available */ |
|
631 }; |
|
632 |
|
633 #define RsvdMask 0x3fffc000 |
|
634 |
|
635 struct TxDesc { |
|
636 __le32 opts1; |
|
637 __le32 opts2; |
|
638 __le64 addr; |
|
639 }; |
|
640 |
|
641 struct RxDesc { |
|
642 __le32 opts1; |
|
643 __le32 opts2; |
|
644 __le64 addr; |
|
645 }; |
|
646 |
|
647 struct ring_info { |
|
648 struct sk_buff *skb; |
|
649 u32 len; |
|
650 u8 __pad[sizeof(void *) - sizeof(u32)]; |
|
651 }; |
|
652 |
|
653 enum features { |
|
654 RTL_FEATURE_WOL = (1 << 0), |
|
655 RTL_FEATURE_MSI = (1 << 1), |
|
656 RTL_FEATURE_GMII = (1 << 2), |
|
657 }; |
|
658 |
|
659 struct rtl8169_counters { |
|
660 __le64 tx_packets; |
|
661 __le64 rx_packets; |
|
662 __le64 tx_errors; |
|
663 __le32 rx_errors; |
|
664 __le16 rx_missed; |
|
665 __le16 align_errors; |
|
666 __le32 tx_one_collision; |
|
667 __le32 tx_multi_collision; |
|
668 __le64 rx_unicast; |
|
669 __le64 rx_broadcast; |
|
670 __le32 rx_multicast; |
|
671 __le16 tx_aborted; |
|
672 __le16 tx_underun; |
|
673 }; |
|
674 |
|
675 enum rtl_flag { |
|
676 RTL_FLAG_TASK_ENABLED, |
|
677 RTL_FLAG_TASK_SLOW_PENDING, |
|
678 RTL_FLAG_TASK_RESET_PENDING, |
|
679 RTL_FLAG_TASK_PHY_PENDING, |
|
680 RTL_FLAG_MAX |
|
681 }; |
|
682 |
|
683 struct rtl8169_stats { |
|
684 u64 packets; |
|
685 u64 bytes; |
|
686 struct u64_stats_sync syncp; |
|
687 }; |
|
688 |
|
689 struct rtl8169_private { |
|
690 void __iomem *mmio_addr; /* memory map physical address */ |
|
691 struct pci_dev *pci_dev; |
|
692 struct net_device *dev; |
|
693 struct napi_struct napi; |
|
694 u32 msg_enable; |
|
695 u16 txd_version; |
|
696 u16 mac_version; |
|
697 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
|
698 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ |
|
699 u32 dirty_rx; |
|
700 u32 dirty_tx; |
|
701 struct rtl8169_stats rx_stats; |
|
702 struct rtl8169_stats tx_stats; |
|
703 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
|
704 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ |
|
705 dma_addr_t TxPhyAddr; |
|
706 dma_addr_t RxPhyAddr; |
|
707 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
|
708 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
709 struct timer_list timer; |
|
710 u16 cp_cmd; |
|
711 |
|
712 u16 event_slow; |
|
713 |
|
714 struct mdio_ops { |
|
715 void (*write)(void __iomem *, int, int); |
|
716 int (*read)(void __iomem *, int); |
|
717 } mdio_ops; |
|
718 |
|
719 struct pll_power_ops { |
|
720 void (*down)(struct rtl8169_private *); |
|
721 void (*up)(struct rtl8169_private *); |
|
722 } pll_power_ops; |
|
723 |
|
724 struct jumbo_ops { |
|
725 void (*enable)(struct rtl8169_private *); |
|
726 void (*disable)(struct rtl8169_private *); |
|
727 } jumbo_ops; |
|
728 |
|
729 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
|
730 int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
|
731 void (*phy_reset_enable)(struct rtl8169_private *tp); |
|
732 void (*hw_start)(struct net_device *); |
|
733 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
|
734 unsigned int (*link_ok)(void __iomem *); |
|
735 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
|
736 |
|
737 struct { |
|
738 DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
|
739 struct mutex mutex; |
|
740 struct work_struct work; |
|
741 } wk; |
|
742 |
|
743 unsigned features; |
|
744 |
|
745 struct mii_if_info mii; |
|
746 struct rtl8169_counters counters; |
|
747 u32 saved_wolopts; |
|
748 u32 opts1_mask; |
|
749 |
|
750 struct rtl_fw { |
|
751 const struct firmware *fw; |
|
752 |
|
753 #define RTL_VER_SIZE 32 |
|
754 |
|
755 char version[RTL_VER_SIZE]; |
|
756 |
|
757 struct rtl_fw_phy_action { |
|
758 __le32 *code; |
|
759 size_t size; |
|
760 } phy_action; |
|
761 } *rtl_fw; |
|
762 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
|
763 |
|
764 ec_device_t *ecdev; |
|
765 unsigned long ec_watchdog_jiffies; |
|
766 }; |
|
767 |
|
768 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
|
769 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver (EtherCAT)"); |
|
770 module_param(use_dac, int, 0); |
|
771 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
|
772 module_param_named(debug, debug.msg_enable, int, 0); |
|
773 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); |
|
774 MODULE_LICENSE("GPL"); |
|
775 MODULE_VERSION(EC_MASTER_VERSION); |
|
776 MODULE_FIRMWARE(FIRMWARE_8168D_1); |
|
777 MODULE_FIRMWARE(FIRMWARE_8168D_2); |
|
778 MODULE_FIRMWARE(FIRMWARE_8168E_1); |
|
779 MODULE_FIRMWARE(FIRMWARE_8168E_2); |
|
780 MODULE_FIRMWARE(FIRMWARE_8168E_3); |
|
781 MODULE_FIRMWARE(FIRMWARE_8105E_1); |
|
782 MODULE_FIRMWARE(FIRMWARE_8168F_1); |
|
783 MODULE_FIRMWARE(FIRMWARE_8168F_2); |
|
784 |
|
785 static void rtl_lock_work(struct rtl8169_private *tp) |
|
786 { |
|
787 mutex_lock(&tp->wk.mutex); |
|
788 } |
|
789 |
|
790 static void rtl_unlock_work(struct rtl8169_private *tp) |
|
791 { |
|
792 mutex_unlock(&tp->wk.mutex); |
|
793 } |
|
794 |
|
795 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
|
796 { |
|
797 int cap = pci_pcie_cap(pdev); |
|
798 |
|
799 if (cap) { |
|
800 u16 ctl; |
|
801 |
|
802 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
|
803 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; |
|
804 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); |
|
805 } |
|
806 } |
|
807 |
|
808 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
|
809 { |
|
810 void __iomem *ioaddr = tp->mmio_addr; |
|
811 int i; |
|
812 |
|
813 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
814 for (i = 0; i < 20; i++) { |
|
815 udelay(100); |
|
816 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
817 break; |
|
818 } |
|
819 return RTL_R32(OCPDR); |
|
820 } |
|
821 |
|
822 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) |
|
823 { |
|
824 void __iomem *ioaddr = tp->mmio_addr; |
|
825 int i; |
|
826 |
|
827 RTL_W32(OCPDR, data); |
|
828 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
|
829 for (i = 0; i < 20; i++) { |
|
830 udelay(100); |
|
831 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) |
|
832 break; |
|
833 } |
|
834 } |
|
835 |
|
836 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
|
837 { |
|
838 void __iomem *ioaddr = tp->mmio_addr; |
|
839 int i; |
|
840 |
|
841 RTL_W8(ERIDR, cmd); |
|
842 RTL_W32(ERIAR, 0x800010e8); |
|
843 msleep(2); |
|
844 for (i = 0; i < 5; i++) { |
|
845 udelay(100); |
|
846 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
847 break; |
|
848 } |
|
849 |
|
850 ocp_write(tp, 0x1, 0x30, 0x00000001); |
|
851 } |
|
852 |
|
853 #define OOB_CMD_RESET 0x00 |
|
854 #define OOB_CMD_DRIVER_START 0x05 |
|
855 #define OOB_CMD_DRIVER_STOP 0x06 |
|
856 |
|
857 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
|
858 { |
|
859 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; |
|
860 } |
|
861 |
|
862 static void rtl8168_driver_start(struct rtl8169_private *tp) |
|
863 { |
|
864 u16 reg; |
|
865 int i; |
|
866 |
|
867 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
|
868 |
|
869 reg = rtl8168_get_ocp_reg(tp); |
|
870 |
|
871 for (i = 0; i < 10; i++) { |
|
872 msleep(10); |
|
873 if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
|
874 break; |
|
875 } |
|
876 } |
|
877 |
|
878 static void rtl8168_driver_stop(struct rtl8169_private *tp) |
|
879 { |
|
880 u16 reg; |
|
881 int i; |
|
882 |
|
883 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); |
|
884 |
|
885 reg = rtl8168_get_ocp_reg(tp); |
|
886 |
|
887 for (i = 0; i < 10; i++) { |
|
888 msleep(10); |
|
889 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
|
890 break; |
|
891 } |
|
892 } |
|
893 |
|
894 static int r8168dp_check_dash(struct rtl8169_private *tp) |
|
895 { |
|
896 u16 reg = rtl8168_get_ocp_reg(tp); |
|
897 |
|
898 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
|
899 } |
|
900 |
|
901 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
902 { |
|
903 int i; |
|
904 |
|
905 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
|
906 |
|
907 for (i = 20; i > 0; i--) { |
|
908 /* |
|
909 * Check if the RTL8169 has completed writing to the specified |
|
910 * MII register. |
|
911 */ |
|
912 if (!(RTL_R32(PHYAR) & 0x80000000)) |
|
913 break; |
|
914 udelay(25); |
|
915 } |
|
916 /* |
|
917 * According to hardware specs a 20us delay is required after write |
|
918 * complete indication, but before sending next command. |
|
919 */ |
|
920 udelay(20); |
|
921 } |
|
922 |
|
923 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
924 { |
|
925 int i, value = -1; |
|
926 |
|
927 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
|
928 |
|
929 for (i = 20; i > 0; i--) { |
|
930 /* |
|
931 * Check if the RTL8169 has completed retrieving data from |
|
932 * the specified MII register. |
|
933 */ |
|
934 if (RTL_R32(PHYAR) & 0x80000000) { |
|
935 value = RTL_R32(PHYAR) & 0xffff; |
|
936 break; |
|
937 } |
|
938 udelay(25); |
|
939 } |
|
940 /* |
|
941 * According to hardware specs a 20us delay is required after read |
|
942 * complete indication, but before sending next command. |
|
943 */ |
|
944 udelay(20); |
|
945 |
|
946 return value; |
|
947 } |
|
948 |
|
949 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
|
950 { |
|
951 int i; |
|
952 |
|
953 RTL_W32(OCPDR, data | |
|
954 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
|
955 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
|
956 RTL_W32(EPHY_RXER_NUM, 0); |
|
957 |
|
958 for (i = 0; i < 100; i++) { |
|
959 mdelay(1); |
|
960 if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) |
|
961 break; |
|
962 } |
|
963 } |
|
964 |
|
965 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
966 { |
|
967 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | |
|
968 (value & OCPDR_DATA_MASK)); |
|
969 } |
|
970 |
|
971 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
972 { |
|
973 int i; |
|
974 |
|
975 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); |
|
976 |
|
977 mdelay(1); |
|
978 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); |
|
979 RTL_W32(EPHY_RXER_NUM, 0); |
|
980 |
|
981 for (i = 0; i < 100; i++) { |
|
982 mdelay(1); |
|
983 if (RTL_R32(OCPAR) & OCPAR_FLAG) |
|
984 break; |
|
985 } |
|
986 |
|
987 return RTL_R32(OCPDR) & OCPDR_DATA_MASK; |
|
988 } |
|
989 |
|
990 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
|
991 |
|
992 static void r8168dp_2_mdio_start(void __iomem *ioaddr) |
|
993 { |
|
994 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
|
995 } |
|
996 |
|
997 static void r8168dp_2_mdio_stop(void __iomem *ioaddr) |
|
998 { |
|
999 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
|
1000 } |
|
1001 |
|
1002 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
|
1003 { |
|
1004 r8168dp_2_mdio_start(ioaddr); |
|
1005 |
|
1006 r8169_mdio_write(ioaddr, reg_addr, value); |
|
1007 |
|
1008 r8168dp_2_mdio_stop(ioaddr); |
|
1009 } |
|
1010 |
|
1011 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) |
|
1012 { |
|
1013 int value; |
|
1014 |
|
1015 r8168dp_2_mdio_start(ioaddr); |
|
1016 |
|
1017 value = r8169_mdio_read(ioaddr, reg_addr); |
|
1018 |
|
1019 r8168dp_2_mdio_stop(ioaddr); |
|
1020 |
|
1021 return value; |
|
1022 } |
|
1023 |
|
1024 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
|
1025 { |
|
1026 tp->mdio_ops.write(tp->mmio_addr, location, val); |
|
1027 } |
|
1028 |
|
1029 static int rtl_readphy(struct rtl8169_private *tp, int location) |
|
1030 { |
|
1031 return tp->mdio_ops.read(tp->mmio_addr, location); |
|
1032 } |
|
1033 |
|
1034 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) |
|
1035 { |
|
1036 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); |
|
1037 } |
|
1038 |
|
1039 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
|
1040 { |
|
1041 int val; |
|
1042 |
|
1043 val = rtl_readphy(tp, reg_addr); |
|
1044 rtl_writephy(tp, reg_addr, (val | p) & ~m); |
|
1045 } |
|
1046 |
|
1047 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
|
1048 int val) |
|
1049 { |
|
1050 struct rtl8169_private *tp = netdev_priv(dev); |
|
1051 |
|
1052 rtl_writephy(tp, location, val); |
|
1053 } |
|
1054 |
|
1055 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) |
|
1056 { |
|
1057 struct rtl8169_private *tp = netdev_priv(dev); |
|
1058 |
|
1059 return rtl_readphy(tp, location); |
|
1060 } |
|
1061 |
|
1062 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
|
1063 { |
|
1064 unsigned int i; |
|
1065 |
|
1066 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
|
1067 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1068 |
|
1069 for (i = 0; i < 100; i++) { |
|
1070 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) |
|
1071 break; |
|
1072 udelay(10); |
|
1073 } |
|
1074 } |
|
1075 |
|
1076 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) |
|
1077 { |
|
1078 u16 value = 0xffff; |
|
1079 unsigned int i; |
|
1080 |
|
1081 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
|
1082 |
|
1083 for (i = 0; i < 100; i++) { |
|
1084 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { |
|
1085 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; |
|
1086 break; |
|
1087 } |
|
1088 udelay(10); |
|
1089 } |
|
1090 |
|
1091 return value; |
|
1092 } |
|
1093 |
|
1094 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) |
|
1095 { |
|
1096 unsigned int i; |
|
1097 |
|
1098 RTL_W32(CSIDR, value); |
|
1099 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | |
|
1100 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1101 |
|
1102 for (i = 0; i < 100; i++) { |
|
1103 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) |
|
1104 break; |
|
1105 udelay(10); |
|
1106 } |
|
1107 } |
|
1108 |
|
1109 static u32 rtl_csi_read(void __iomem *ioaddr, int addr) |
|
1110 { |
|
1111 u32 value = ~0x00; |
|
1112 unsigned int i; |
|
1113 |
|
1114 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | |
|
1115 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); |
|
1116 |
|
1117 for (i = 0; i < 100; i++) { |
|
1118 if (RTL_R32(CSIAR) & CSIAR_FLAG) { |
|
1119 value = RTL_R32(CSIDR); |
|
1120 break; |
|
1121 } |
|
1122 udelay(10); |
|
1123 } |
|
1124 |
|
1125 return value; |
|
1126 } |
|
1127 |
|
1128 static |
|
1129 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) |
|
1130 { |
|
1131 unsigned int i; |
|
1132 |
|
1133 BUG_ON((addr & 3) || (mask == 0)); |
|
1134 RTL_W32(ERIDR, val); |
|
1135 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); |
|
1136 |
|
1137 for (i = 0; i < 100; i++) { |
|
1138 if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
|
1139 break; |
|
1140 udelay(100); |
|
1141 } |
|
1142 } |
|
1143 |
|
1144 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) |
|
1145 { |
|
1146 u32 value = ~0x00; |
|
1147 unsigned int i; |
|
1148 |
|
1149 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); |
|
1150 |
|
1151 for (i = 0; i < 100; i++) { |
|
1152 if (RTL_R32(ERIAR) & ERIAR_FLAG) { |
|
1153 value = RTL_R32(ERIDR); |
|
1154 break; |
|
1155 } |
|
1156 udelay(100); |
|
1157 } |
|
1158 |
|
1159 return value; |
|
1160 } |
|
1161 |
|
1162 static void |
|
1163 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) |
|
1164 { |
|
1165 u32 val; |
|
1166 |
|
1167 val = rtl_eri_read(ioaddr, addr, type); |
|
1168 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); |
|
1169 } |
|
1170 |
|
1171 struct exgmac_reg { |
|
1172 u16 addr; |
|
1173 u16 mask; |
|
1174 u32 val; |
|
1175 }; |
|
1176 |
|
1177 static void rtl_write_exgmac_batch(void __iomem *ioaddr, |
|
1178 const struct exgmac_reg *r, int len) |
|
1179 { |
|
1180 while (len-- > 0) { |
|
1181 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
|
1182 r++; |
|
1183 } |
|
1184 } |
|
1185 |
|
1186 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
|
1187 { |
|
1188 u8 value = 0xff; |
|
1189 unsigned int i; |
|
1190 |
|
1191 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
|
1192 |
|
1193 for (i = 0; i < 300; i++) { |
|
1194 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { |
|
1195 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; |
|
1196 break; |
|
1197 } |
|
1198 udelay(100); |
|
1199 } |
|
1200 |
|
1201 return value; |
|
1202 } |
|
1203 |
|
1204 static u16 rtl_get_events(struct rtl8169_private *tp) |
|
1205 { |
|
1206 void __iomem *ioaddr = tp->mmio_addr; |
|
1207 |
|
1208 return RTL_R16(IntrStatus); |
|
1209 } |
|
1210 |
|
1211 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) |
|
1212 { |
|
1213 void __iomem *ioaddr = tp->mmio_addr; |
|
1214 |
|
1215 RTL_W16(IntrStatus, bits); |
|
1216 mmiowb(); |
|
1217 } |
|
1218 |
|
1219 static void rtl_irq_disable(struct rtl8169_private *tp) |
|
1220 { |
|
1221 void __iomem *ioaddr = tp->mmio_addr; |
|
1222 |
|
1223 RTL_W16(IntrMask, 0); |
|
1224 mmiowb(); |
|
1225 } |
|
1226 |
|
1227 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
|
1228 { |
|
1229 void __iomem *ioaddr = tp->mmio_addr; |
|
1230 |
|
1231 RTL_W16(IntrMask, bits); |
|
1232 } |
|
1233 |
|
1234 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
|
1235 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) |
|
1236 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) |
|
1237 |
|
1238 static void rtl_irq_enable_all(struct rtl8169_private *tp) |
|
1239 { |
|
1240 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1241 } |
|
1242 |
|
1243 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
|
1244 { |
|
1245 void __iomem *ioaddr = tp->mmio_addr; |
|
1246 |
|
1247 rtl_irq_disable(tp); |
|
1248 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
|
1249 RTL_R8(ChipCmd); |
|
1250 } |
|
1251 |
|
1252 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
|
1253 { |
|
1254 void __iomem *ioaddr = tp->mmio_addr; |
|
1255 |
|
1256 return RTL_R32(TBICSR) & TBIReset; |
|
1257 } |
|
1258 |
|
1259 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
|
1260 { |
|
1261 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
|
1262 } |
|
1263 |
|
1264 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) |
|
1265 { |
|
1266 return RTL_R32(TBICSR) & TBILinkOk; |
|
1267 } |
|
1268 |
|
1269 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) |
|
1270 { |
|
1271 return RTL_R8(PHYstatus) & LinkStatus; |
|
1272 } |
|
1273 |
|
1274 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
|
1275 { |
|
1276 void __iomem *ioaddr = tp->mmio_addr; |
|
1277 |
|
1278 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
|
1279 } |
|
1280 |
|
1281 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
|
1282 { |
|
1283 unsigned int val; |
|
1284 |
|
1285 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
|
1286 rtl_writephy(tp, MII_BMCR, val & 0xffff); |
|
1287 } |
|
1288 |
|
1289 static void rtl_link_chg_patch(struct rtl8169_private *tp) |
|
1290 { |
|
1291 void __iomem *ioaddr = tp->mmio_addr; |
|
1292 struct net_device *dev = tp->dev; |
|
1293 |
|
1294 if (!netif_running(dev)) |
|
1295 return; |
|
1296 |
|
1297 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
1298 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1299 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1300 0x00000011, ERIAR_EXGMAC); |
|
1301 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1302 0x00000005, ERIAR_EXGMAC); |
|
1303 } else if (RTL_R8(PHYstatus) & _100bps) { |
|
1304 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1305 0x0000001f, ERIAR_EXGMAC); |
|
1306 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1307 0x00000005, ERIAR_EXGMAC); |
|
1308 } else { |
|
1309 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1310 0x0000001f, ERIAR_EXGMAC); |
|
1311 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1312 0x0000003f, ERIAR_EXGMAC); |
|
1313 } |
|
1314 /* Reset packet filter */ |
|
1315 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
|
1316 ERIAR_EXGMAC); |
|
1317 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
|
1318 ERIAR_EXGMAC); |
|
1319 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
1320 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
1321 if (RTL_R8(PHYstatus) & _1000bpsF) { |
|
1322 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1323 0x00000011, ERIAR_EXGMAC); |
|
1324 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1325 0x00000005, ERIAR_EXGMAC); |
|
1326 } else { |
|
1327 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, |
|
1328 0x0000001f, ERIAR_EXGMAC); |
|
1329 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, |
|
1330 0x0000003f, ERIAR_EXGMAC); |
|
1331 } |
|
1332 } |
|
1333 } |
|
1334 |
|
1335 static void __rtl8169_check_link_status(struct net_device *dev, |
|
1336 struct rtl8169_private *tp, |
|
1337 void __iomem *ioaddr, bool pm) |
|
1338 { |
|
1339 if (tp->ecdev) { |
|
1340 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
1341 return; |
|
1342 } |
|
1343 |
|
1344 if (tp->link_ok(ioaddr)) { |
|
1345 rtl_link_chg_patch(tp); |
|
1346 /* This is to cancel a scheduled suspend if there's one. */ |
|
1347 if (pm) |
|
1348 pm_request_resume(&tp->pci_dev->dev); |
|
1349 netif_carrier_on(dev); |
|
1350 if (net_ratelimit()) |
|
1351 netif_info(tp, ifup, dev, "link up\n"); |
|
1352 } else { |
|
1353 netif_carrier_off(dev); |
|
1354 netif_info(tp, ifdown, dev, "link down\n"); |
|
1355 if (pm) |
|
1356 pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
|
1357 } |
|
1358 } |
|
1359 |
|
1360 static void rtl8169_check_link_status(struct net_device *dev, |
|
1361 struct rtl8169_private *tp, |
|
1362 void __iomem *ioaddr) |
|
1363 { |
|
1364 __rtl8169_check_link_status(dev, tp, ioaddr, false); |
|
1365 } |
|
1366 |
|
1367 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
|
1368 |
|
1369 static u32 __rtl8169_get_wol(struct rtl8169_private *tp) |
|
1370 { |
|
1371 void __iomem *ioaddr = tp->mmio_addr; |
|
1372 u8 options; |
|
1373 u32 wolopts = 0; |
|
1374 |
|
1375 options = RTL_R8(Config1); |
|
1376 if (!(options & PMEnable)) |
|
1377 return 0; |
|
1378 |
|
1379 options = RTL_R8(Config3); |
|
1380 if (options & LinkUp) |
|
1381 wolopts |= WAKE_PHY; |
|
1382 if (options & MagicPacket) |
|
1383 wolopts |= WAKE_MAGIC; |
|
1384 |
|
1385 options = RTL_R8(Config5); |
|
1386 if (options & UWF) |
|
1387 wolopts |= WAKE_UCAST; |
|
1388 if (options & BWF) |
|
1389 wolopts |= WAKE_BCAST; |
|
1390 if (options & MWF) |
|
1391 wolopts |= WAKE_MCAST; |
|
1392 |
|
1393 return wolopts; |
|
1394 } |
|
1395 |
|
1396 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1397 { |
|
1398 struct rtl8169_private *tp = netdev_priv(dev); |
|
1399 |
|
1400 rtl_lock_work(tp); |
|
1401 |
|
1402 wol->supported = WAKE_ANY; |
|
1403 wol->wolopts = __rtl8169_get_wol(tp); |
|
1404 |
|
1405 rtl_unlock_work(tp); |
|
1406 } |
|
1407 |
|
1408 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) |
|
1409 { |
|
1410 void __iomem *ioaddr = tp->mmio_addr; |
|
1411 unsigned int i; |
|
1412 static const struct { |
|
1413 u32 opt; |
|
1414 u16 reg; |
|
1415 u8 mask; |
|
1416 } cfg[] = { |
|
1417 { WAKE_PHY, Config3, LinkUp }, |
|
1418 { WAKE_MAGIC, Config3, MagicPacket }, |
|
1419 { WAKE_UCAST, Config5, UWF }, |
|
1420 { WAKE_BCAST, Config5, BWF }, |
|
1421 { WAKE_MCAST, Config5, MWF }, |
|
1422 { WAKE_ANY, Config5, LanWake } |
|
1423 }; |
|
1424 u8 options; |
|
1425 |
|
1426 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
1427 |
|
1428 for (i = 0; i < ARRAY_SIZE(cfg); i++) { |
|
1429 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
|
1430 if (wolopts & cfg[i].opt) |
|
1431 options |= cfg[i].mask; |
|
1432 RTL_W8(cfg[i].reg, options); |
|
1433 } |
|
1434 |
|
1435 switch (tp->mac_version) { |
|
1436 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: |
|
1437 options = RTL_R8(Config1) & ~PMEnable; |
|
1438 if (wolopts) |
|
1439 options |= PMEnable; |
|
1440 RTL_W8(Config1, options); |
|
1441 break; |
|
1442 default: |
|
1443 options = RTL_R8(Config2) & ~PME_SIGNAL; |
|
1444 if (wolopts) |
|
1445 options |= PME_SIGNAL; |
|
1446 RTL_W8(Config2, options); |
|
1447 break; |
|
1448 } |
|
1449 |
|
1450 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
1451 } |
|
1452 |
|
1453 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
|
1454 { |
|
1455 struct rtl8169_private *tp = netdev_priv(dev); |
|
1456 |
|
1457 rtl_lock_work(tp); |
|
1458 |
|
1459 if (wol->wolopts) |
|
1460 tp->features |= RTL_FEATURE_WOL; |
|
1461 else |
|
1462 tp->features &= ~RTL_FEATURE_WOL; |
|
1463 __rtl8169_set_wol(tp, wol->wolopts); |
|
1464 |
|
1465 rtl_unlock_work(tp); |
|
1466 |
|
1467 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
|
1468 |
|
1469 return 0; |
|
1470 } |
|
1471 |
|
1472 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
|
1473 { |
|
1474 return rtl_chip_infos[tp->mac_version].fw_name; |
|
1475 } |
|
1476 |
|
1477 static void rtl8169_get_drvinfo(struct net_device *dev, |
|
1478 struct ethtool_drvinfo *info) |
|
1479 { |
|
1480 struct rtl8169_private *tp = netdev_priv(dev); |
|
1481 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
1482 |
|
1483 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
|
1484 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); |
|
1485 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); |
|
1486 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
|
1487 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
1488 strlcpy(info->fw_version, rtl_fw->version, |
|
1489 sizeof(info->fw_version)); |
|
1490 } |
|
1491 |
|
1492 static int rtl8169_get_regs_len(struct net_device *dev) |
|
1493 { |
|
1494 return R8169_REGS_SIZE; |
|
1495 } |
|
1496 |
|
1497 static int rtl8169_set_speed_tbi(struct net_device *dev, |
|
1498 u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
|
1499 { |
|
1500 struct rtl8169_private *tp = netdev_priv(dev); |
|
1501 void __iomem *ioaddr = tp->mmio_addr; |
|
1502 int ret = 0; |
|
1503 u32 reg; |
|
1504 |
|
1505 reg = RTL_R32(TBICSR); |
|
1506 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
|
1507 (duplex == DUPLEX_FULL)) { |
|
1508 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
|
1509 } else if (autoneg == AUTONEG_ENABLE) |
|
1510 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); |
|
1511 else { |
|
1512 netif_warn(tp, link, dev, |
|
1513 "incorrect speed setting refused in TBI mode\n"); |
|
1514 ret = -EOPNOTSUPP; |
|
1515 } |
|
1516 |
|
1517 return ret; |
|
1518 } |
|
1519 |
|
1520 static int rtl8169_set_speed_xmii(struct net_device *dev, |
|
1521 u8 autoneg, u16 speed, u8 duplex, u32 adv) |
|
1522 { |
|
1523 struct rtl8169_private *tp = netdev_priv(dev); |
|
1524 int giga_ctrl, bmcr; |
|
1525 int rc = -EINVAL; |
|
1526 |
|
1527 rtl_writephy(tp, 0x1f, 0x0000); |
|
1528 |
|
1529 if (autoneg == AUTONEG_ENABLE) { |
|
1530 int auto_nego; |
|
1531 |
|
1532 auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
|
1533 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
|
1534 ADVERTISE_100HALF | ADVERTISE_100FULL); |
|
1535 |
|
1536 if (adv & ADVERTISED_10baseT_Half) |
|
1537 auto_nego |= ADVERTISE_10HALF; |
|
1538 if (adv & ADVERTISED_10baseT_Full) |
|
1539 auto_nego |= ADVERTISE_10FULL; |
|
1540 if (adv & ADVERTISED_100baseT_Half) |
|
1541 auto_nego |= ADVERTISE_100HALF; |
|
1542 if (adv & ADVERTISED_100baseT_Full) |
|
1543 auto_nego |= ADVERTISE_100FULL; |
|
1544 |
|
1545 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
|
1546 |
|
1547 giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
|
1548 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
|
1549 |
|
1550 /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
|
1551 if (tp->mii.supports_gmii) { |
|
1552 if (adv & ADVERTISED_1000baseT_Half) |
|
1553 giga_ctrl |= ADVERTISE_1000HALF; |
|
1554 if (adv & ADVERTISED_1000baseT_Full) |
|
1555 giga_ctrl |= ADVERTISE_1000FULL; |
|
1556 } else if (adv & (ADVERTISED_1000baseT_Half | |
|
1557 ADVERTISED_1000baseT_Full)) { |
|
1558 netif_info(tp, link, dev, |
|
1559 "PHY does not support 1000Mbps\n"); |
|
1560 goto out; |
|
1561 } |
|
1562 |
|
1563 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
|
1564 |
|
1565 rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
|
1566 rtl_writephy(tp, MII_CTRL1000, giga_ctrl); |
|
1567 } else { |
|
1568 giga_ctrl = 0; |
|
1569 |
|
1570 if (speed == SPEED_10) |
|
1571 bmcr = 0; |
|
1572 else if (speed == SPEED_100) |
|
1573 bmcr = BMCR_SPEED100; |
|
1574 else |
|
1575 goto out; |
|
1576 |
|
1577 if (duplex == DUPLEX_FULL) |
|
1578 bmcr |= BMCR_FULLDPLX; |
|
1579 } |
|
1580 |
|
1581 rtl_writephy(tp, MII_BMCR, bmcr); |
|
1582 |
|
1583 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
1584 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
1585 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
|
1586 rtl_writephy(tp, 0x17, 0x2138); |
|
1587 rtl_writephy(tp, 0x0e, 0x0260); |
|
1588 } else { |
|
1589 rtl_writephy(tp, 0x17, 0x2108); |
|
1590 rtl_writephy(tp, 0x0e, 0x0000); |
|
1591 } |
|
1592 } |
|
1593 |
|
1594 rc = 0; |
|
1595 out: |
|
1596 return rc; |
|
1597 } |
|
1598 |
|
1599 static int rtl8169_set_speed(struct net_device *dev, |
|
1600 u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
|
1601 { |
|
1602 struct rtl8169_private *tp = netdev_priv(dev); |
|
1603 int ret; |
|
1604 |
|
1605 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
|
1606 if (ret < 0) |
|
1607 goto out; |
|
1608 |
|
1609 if (!tp->ecdev && netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
|
1610 (advertising & ADVERTISED_1000baseT_Full)) { |
|
1611 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
|
1612 } |
|
1613 out: |
|
1614 return ret; |
|
1615 } |
|
1616 |
|
1617 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1618 { |
|
1619 struct rtl8169_private *tp = netdev_priv(dev); |
|
1620 int ret; |
|
1621 |
|
1622 if (!tp->ecdev) { |
|
1623 del_timer_sync(&tp->timer); |
|
1624 } |
|
1625 |
|
1626 rtl_lock_work(tp); |
|
1627 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
|
1628 cmd->duplex, cmd->advertising); |
|
1629 rtl_unlock_work(tp); |
|
1630 |
|
1631 return ret; |
|
1632 } |
|
1633 |
|
1634 static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
|
1635 netdev_features_t features) |
|
1636 { |
|
1637 struct rtl8169_private *tp = netdev_priv(dev); |
|
1638 |
|
1639 if (dev->mtu > TD_MSS_MAX) |
|
1640 features &= ~NETIF_F_ALL_TSO; |
|
1641 |
|
1642 if (dev->mtu > JUMBO_1K && |
|
1643 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) |
|
1644 features &= ~NETIF_F_IP_CSUM; |
|
1645 |
|
1646 return features; |
|
1647 } |
|
1648 |
|
1649 static void __rtl8169_set_features(struct net_device *dev, |
|
1650 netdev_features_t features) |
|
1651 { |
|
1652 struct rtl8169_private *tp = netdev_priv(dev); |
|
1653 netdev_features_t changed = features ^ dev->features; |
|
1654 void __iomem *ioaddr = tp->mmio_addr; |
|
1655 |
|
1656 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX))) |
|
1657 return; |
|
1658 |
|
1659 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) { |
|
1660 if (features & NETIF_F_RXCSUM) |
|
1661 tp->cp_cmd |= RxChkSum; |
|
1662 else |
|
1663 tp->cp_cmd &= ~RxChkSum; |
|
1664 |
|
1665 if (dev->features & NETIF_F_HW_VLAN_RX) |
|
1666 tp->cp_cmd |= RxVlan; |
|
1667 else |
|
1668 tp->cp_cmd &= ~RxVlan; |
|
1669 |
|
1670 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
1671 RTL_R16(CPlusCmd); |
|
1672 } |
|
1673 if (changed & NETIF_F_RXALL) { |
|
1674 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt)); |
|
1675 if (features & NETIF_F_RXALL) |
|
1676 tmp |= (AcceptErr | AcceptRunt); |
|
1677 RTL_W32(RxConfig, tmp); |
|
1678 } |
|
1679 } |
|
1680 |
|
1681 static int rtl8169_set_features(struct net_device *dev, |
|
1682 netdev_features_t features) |
|
1683 { |
|
1684 struct rtl8169_private *tp = netdev_priv(dev); |
|
1685 |
|
1686 rtl_lock_work(tp); |
|
1687 __rtl8169_set_features(dev, features); |
|
1688 rtl_unlock_work(tp); |
|
1689 |
|
1690 return 0; |
|
1691 } |
|
1692 |
|
1693 |
|
1694 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
|
1695 struct sk_buff *skb) |
|
1696 { |
|
1697 return (vlan_tx_tag_present(skb)) ? |
|
1698 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
|
1699 } |
|
1700 |
|
1701 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
|
1702 { |
|
1703 u32 opts2 = le32_to_cpu(desc->opts2); |
|
1704 |
|
1705 if (opts2 & RxVlanTag) |
|
1706 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); |
|
1707 |
|
1708 desc->opts2 = 0; |
|
1709 } |
|
1710 |
|
1711 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1712 { |
|
1713 struct rtl8169_private *tp = netdev_priv(dev); |
|
1714 void __iomem *ioaddr = tp->mmio_addr; |
|
1715 u32 status; |
|
1716 |
|
1717 cmd->supported = |
|
1718 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
|
1719 cmd->port = PORT_FIBRE; |
|
1720 cmd->transceiver = XCVR_INTERNAL; |
|
1721 |
|
1722 status = RTL_R32(TBICSR); |
|
1723 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
|
1724 cmd->autoneg = !!(status & TBINwEnable); |
|
1725 |
|
1726 ethtool_cmd_speed_set(cmd, SPEED_1000); |
|
1727 cmd->duplex = DUPLEX_FULL; /* Always set */ |
|
1728 |
|
1729 return 0; |
|
1730 } |
|
1731 |
|
1732 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1733 { |
|
1734 struct rtl8169_private *tp = netdev_priv(dev); |
|
1735 |
|
1736 return mii_ethtool_gset(&tp->mii, cmd); |
|
1737 } |
|
1738 |
|
1739 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
|
1740 { |
|
1741 struct rtl8169_private *tp = netdev_priv(dev); |
|
1742 int rc; |
|
1743 |
|
1744 rtl_lock_work(tp); |
|
1745 rc = tp->get_settings(dev, cmd); |
|
1746 rtl_unlock_work(tp); |
|
1747 |
|
1748 return rc; |
|
1749 } |
|
1750 |
|
1751 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
|
1752 void *p) |
|
1753 { |
|
1754 struct rtl8169_private *tp = netdev_priv(dev); |
|
1755 |
|
1756 if (regs->len > R8169_REGS_SIZE) |
|
1757 regs->len = R8169_REGS_SIZE; |
|
1758 |
|
1759 rtl_lock_work(tp); |
|
1760 memcpy_fromio(p, tp->mmio_addr, regs->len); |
|
1761 rtl_unlock_work(tp); |
|
1762 } |
|
1763 |
|
1764 static u32 rtl8169_get_msglevel(struct net_device *dev) |
|
1765 { |
|
1766 struct rtl8169_private *tp = netdev_priv(dev); |
|
1767 |
|
1768 return tp->msg_enable; |
|
1769 } |
|
1770 |
|
1771 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) |
|
1772 { |
|
1773 struct rtl8169_private *tp = netdev_priv(dev); |
|
1774 |
|
1775 tp->msg_enable = value; |
|
1776 } |
|
1777 |
|
1778 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
|
1779 "tx_packets", |
|
1780 "rx_packets", |
|
1781 "tx_errors", |
|
1782 "rx_errors", |
|
1783 "rx_missed", |
|
1784 "align_errors", |
|
1785 "tx_single_collisions", |
|
1786 "tx_multi_collisions", |
|
1787 "unicast", |
|
1788 "broadcast", |
|
1789 "multicast", |
|
1790 "tx_aborted", |
|
1791 "tx_underrun", |
|
1792 }; |
|
1793 |
|
1794 static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
|
1795 { |
|
1796 switch (sset) { |
|
1797 case ETH_SS_STATS: |
|
1798 return ARRAY_SIZE(rtl8169_gstrings); |
|
1799 default: |
|
1800 return -EOPNOTSUPP; |
|
1801 } |
|
1802 } |
|
1803 |
|
1804 static void rtl8169_update_counters(struct net_device *dev) |
|
1805 { |
|
1806 struct rtl8169_private *tp = netdev_priv(dev); |
|
1807 void __iomem *ioaddr = tp->mmio_addr; |
|
1808 struct device *d = &tp->pci_dev->dev; |
|
1809 struct rtl8169_counters *counters; |
|
1810 dma_addr_t paddr; |
|
1811 u32 cmd; |
|
1812 int wait = 1000; |
|
1813 |
|
1814 /* |
|
1815 * Some chips are unable to dump tally counters when the receiver |
|
1816 * is disabled. |
|
1817 */ |
|
1818 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) |
|
1819 return; |
|
1820 |
|
1821 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
|
1822 if (!counters) |
|
1823 return; |
|
1824 |
|
1825 RTL_W32(CounterAddrHigh, (u64)paddr >> 32); |
|
1826 cmd = (u64)paddr & DMA_BIT_MASK(32); |
|
1827 RTL_W32(CounterAddrLow, cmd); |
|
1828 RTL_W32(CounterAddrLow, cmd | CounterDump); |
|
1829 |
|
1830 while (wait--) { |
|
1831 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { |
|
1832 memcpy(&tp->counters, counters, sizeof(*counters)); |
|
1833 break; |
|
1834 } |
|
1835 udelay(10); |
|
1836 } |
|
1837 |
|
1838 RTL_W32(CounterAddrLow, 0); |
|
1839 RTL_W32(CounterAddrHigh, 0); |
|
1840 |
|
1841 dma_free_coherent(d, sizeof(*counters), counters, paddr); |
|
1842 } |
|
1843 |
|
1844 static void rtl8169_get_ethtool_stats(struct net_device *dev, |
|
1845 struct ethtool_stats *stats, u64 *data) |
|
1846 { |
|
1847 struct rtl8169_private *tp = netdev_priv(dev); |
|
1848 |
|
1849 ASSERT_RTNL(); |
|
1850 |
|
1851 rtl8169_update_counters(dev); |
|
1852 |
|
1853 data[0] = le64_to_cpu(tp->counters.tx_packets); |
|
1854 data[1] = le64_to_cpu(tp->counters.rx_packets); |
|
1855 data[2] = le64_to_cpu(tp->counters.tx_errors); |
|
1856 data[3] = le32_to_cpu(tp->counters.rx_errors); |
|
1857 data[4] = le16_to_cpu(tp->counters.rx_missed); |
|
1858 data[5] = le16_to_cpu(tp->counters.align_errors); |
|
1859 data[6] = le32_to_cpu(tp->counters.tx_one_collision); |
|
1860 data[7] = le32_to_cpu(tp->counters.tx_multi_collision); |
|
1861 data[8] = le64_to_cpu(tp->counters.rx_unicast); |
|
1862 data[9] = le64_to_cpu(tp->counters.rx_broadcast); |
|
1863 data[10] = le32_to_cpu(tp->counters.rx_multicast); |
|
1864 data[11] = le16_to_cpu(tp->counters.tx_aborted); |
|
1865 data[12] = le16_to_cpu(tp->counters.tx_underun); |
|
1866 } |
|
1867 |
|
1868 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
|
1869 { |
|
1870 switch(stringset) { |
|
1871 case ETH_SS_STATS: |
|
1872 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); |
|
1873 break; |
|
1874 } |
|
1875 } |
|
1876 |
|
1877 static const struct ethtool_ops rtl8169_ethtool_ops = { |
|
1878 .get_drvinfo = rtl8169_get_drvinfo, |
|
1879 .get_regs_len = rtl8169_get_regs_len, |
|
1880 .get_link = ethtool_op_get_link, |
|
1881 .get_settings = rtl8169_get_settings, |
|
1882 .set_settings = rtl8169_set_settings, |
|
1883 .get_msglevel = rtl8169_get_msglevel, |
|
1884 .set_msglevel = rtl8169_set_msglevel, |
|
1885 .get_regs = rtl8169_get_regs, |
|
1886 .get_wol = rtl8169_get_wol, |
|
1887 .set_wol = rtl8169_set_wol, |
|
1888 .get_strings = rtl8169_get_strings, |
|
1889 .get_sset_count = rtl8169_get_sset_count, |
|
1890 .get_ethtool_stats = rtl8169_get_ethtool_stats, |
|
1891 }; |
|
1892 |
|
1893 static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
|
1894 struct net_device *dev, u8 default_version) |
|
1895 { |
|
1896 void __iomem *ioaddr = tp->mmio_addr; |
|
1897 /* |
|
1898 * The driver currently handles the 8168Bf and the 8168Be identically |
|
1899 * but they can be identified more specifically through the test below |
|
1900 * if needed: |
|
1901 * |
|
1902 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
|
1903 * |
|
1904 * Same thing for the 8101Eb and the 8101Ec: |
|
1905 * |
|
1906 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
|
1907 */ |
|
1908 static const struct rtl_mac_info { |
|
1909 u32 mask; |
|
1910 u32 val; |
|
1911 int mac_version; |
|
1912 } mac_info[] = { |
|
1913 /* 8168F family. */ |
|
1914 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
|
1915 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, |
|
1916 |
|
1917 /* 8168E family. */ |
|
1918 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
|
1919 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
|
1920 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, |
|
1921 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, |
|
1922 |
|
1923 /* 8168D family. */ |
|
1924 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
|
1925 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
|
1926 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
|
1927 |
|
1928 /* 8168DP family. */ |
|
1929 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, |
|
1930 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, |
|
1931 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
|
1932 |
|
1933 /* 8168C family. */ |
|
1934 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
|
1935 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
|
1936 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
|
1937 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
|
1938 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
|
1939 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
|
1940 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
|
1941 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
|
1942 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
|
1943 |
|
1944 /* 8168B family. */ |
|
1945 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, |
|
1946 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, |
|
1947 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
|
1948 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, |
|
1949 |
|
1950 /* 8101 family. */ |
|
1951 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
|
1952 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
|
1953 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, |
|
1954 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, |
|
1955 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
|
1956 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, |
|
1957 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
|
1958 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, |
|
1959 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, |
|
1960 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, |
|
1961 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
|
1962 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
|
1963 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
|
1964 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
|
1965 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, |
|
1966 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
|
1967 /* FIXME: where did these entries come from ? -- FR */ |
|
1968 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, |
|
1969 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
1970 |
|
1971 /* 8110 family. */ |
|
1972 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, |
|
1973 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, |
|
1974 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, |
|
1975 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, |
|
1976 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, |
|
1977 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, |
|
1978 |
|
1979 /* Catch-all */ |
|
1980 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } |
|
1981 }; |
|
1982 const struct rtl_mac_info *p = mac_info; |
|
1983 u32 reg; |
|
1984 |
|
1985 reg = RTL_R32(TxConfig); |
|
1986 while ((reg & p->mask) != p->val) |
|
1987 p++; |
|
1988 tp->mac_version = p->mac_version; |
|
1989 |
|
1990 if (tp->mac_version == RTL_GIGA_MAC_NONE) { |
|
1991 netif_notice(tp, probe, dev, |
|
1992 "unknown MAC, using family default\n"); |
|
1993 tp->mac_version = default_version; |
|
1994 } |
|
1995 } |
|
1996 |
|
1997 static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
|
1998 { |
|
1999 dprintk("mac_version = 0x%02x\n", tp->mac_version); |
|
2000 } |
|
2001 |
|
2002 struct phy_reg { |
|
2003 u16 reg; |
|
2004 u16 val; |
|
2005 }; |
|
2006 |
|
2007 static void rtl_writephy_batch(struct rtl8169_private *tp, |
|
2008 const struct phy_reg *regs, int len) |
|
2009 { |
|
2010 while (len-- > 0) { |
|
2011 rtl_writephy(tp, regs->reg, regs->val); |
|
2012 regs++; |
|
2013 } |
|
2014 } |
|
2015 |
|
2016 #define PHY_READ 0x00000000 |
|
2017 #define PHY_DATA_OR 0x10000000 |
|
2018 #define PHY_DATA_AND 0x20000000 |
|
2019 #define PHY_BJMPN 0x30000000 |
|
2020 #define PHY_READ_EFUSE 0x40000000 |
|
2021 #define PHY_READ_MAC_BYTE 0x50000000 |
|
2022 #define PHY_WRITE_MAC_BYTE 0x60000000 |
|
2023 #define PHY_CLEAR_READCOUNT 0x70000000 |
|
2024 #define PHY_WRITE 0x80000000 |
|
2025 #define PHY_READCOUNT_EQ_SKIP 0x90000000 |
|
2026 #define PHY_COMP_EQ_SKIPN 0xa0000000 |
|
2027 #define PHY_COMP_NEQ_SKIPN 0xb0000000 |
|
2028 #define PHY_WRITE_PREVIOUS 0xc0000000 |
|
2029 #define PHY_SKIPN 0xd0000000 |
|
2030 #define PHY_DELAY_MS 0xe0000000 |
|
2031 #define PHY_WRITE_ERI_WORD 0xf0000000 |
|
2032 |
|
2033 struct fw_info { |
|
2034 u32 magic; |
|
2035 char version[RTL_VER_SIZE]; |
|
2036 __le32 fw_start; |
|
2037 __le32 fw_len; |
|
2038 u8 chksum; |
|
2039 } __packed; |
|
2040 |
|
2041 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
|
2042 |
|
2043 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2044 { |
|
2045 const struct firmware *fw = rtl_fw->fw; |
|
2046 struct fw_info *fw_info = (struct fw_info *)fw->data; |
|
2047 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2048 char *version = rtl_fw->version; |
|
2049 bool rc = false; |
|
2050 |
|
2051 if (fw->size < FW_OPCODE_SIZE) |
|
2052 goto out; |
|
2053 |
|
2054 if (!fw_info->magic) { |
|
2055 size_t i, size, start; |
|
2056 u8 checksum = 0; |
|
2057 |
|
2058 if (fw->size < sizeof(*fw_info)) |
|
2059 goto out; |
|
2060 |
|
2061 for (i = 0; i < fw->size; i++) |
|
2062 checksum += fw->data[i]; |
|
2063 if (checksum != 0) |
|
2064 goto out; |
|
2065 |
|
2066 start = le32_to_cpu(fw_info->fw_start); |
|
2067 if (start > fw->size) |
|
2068 goto out; |
|
2069 |
|
2070 size = le32_to_cpu(fw_info->fw_len); |
|
2071 if (size > (fw->size - start) / FW_OPCODE_SIZE) |
|
2072 goto out; |
|
2073 |
|
2074 memcpy(version, fw_info->version, RTL_VER_SIZE); |
|
2075 |
|
2076 pa->code = (__le32 *)(fw->data + start); |
|
2077 pa->size = size; |
|
2078 } else { |
|
2079 if (fw->size % FW_OPCODE_SIZE) |
|
2080 goto out; |
|
2081 |
|
2082 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); |
|
2083 |
|
2084 pa->code = (__le32 *)fw->data; |
|
2085 pa->size = fw->size / FW_OPCODE_SIZE; |
|
2086 } |
|
2087 version[RTL_VER_SIZE - 1] = 0; |
|
2088 |
|
2089 rc = true; |
|
2090 out: |
|
2091 return rc; |
|
2092 } |
|
2093 |
|
2094 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
|
2095 struct rtl_fw_phy_action *pa) |
|
2096 { |
|
2097 bool rc = false; |
|
2098 size_t index; |
|
2099 |
|
2100 for (index = 0; index < pa->size; index++) { |
|
2101 u32 action = le32_to_cpu(pa->code[index]); |
|
2102 u32 regno = (action & 0x0fff0000) >> 16; |
|
2103 |
|
2104 switch(action & 0xf0000000) { |
|
2105 case PHY_READ: |
|
2106 case PHY_DATA_OR: |
|
2107 case PHY_DATA_AND: |
|
2108 case PHY_READ_EFUSE: |
|
2109 case PHY_CLEAR_READCOUNT: |
|
2110 case PHY_WRITE: |
|
2111 case PHY_WRITE_PREVIOUS: |
|
2112 case PHY_DELAY_MS: |
|
2113 break; |
|
2114 |
|
2115 case PHY_BJMPN: |
|
2116 if (regno > index) { |
|
2117 netif_err(tp, ifup, tp->dev, |
|
2118 "Out of range of firmware\n"); |
|
2119 goto out; |
|
2120 } |
|
2121 break; |
|
2122 case PHY_READCOUNT_EQ_SKIP: |
|
2123 if (index + 2 >= pa->size) { |
|
2124 netif_err(tp, ifup, tp->dev, |
|
2125 "Out of range of firmware\n"); |
|
2126 goto out; |
|
2127 } |
|
2128 break; |
|
2129 case PHY_COMP_EQ_SKIPN: |
|
2130 case PHY_COMP_NEQ_SKIPN: |
|
2131 case PHY_SKIPN: |
|
2132 if (index + 1 + regno >= pa->size) { |
|
2133 netif_err(tp, ifup, tp->dev, |
|
2134 "Out of range of firmware\n"); |
|
2135 goto out; |
|
2136 } |
|
2137 break; |
|
2138 |
|
2139 case PHY_READ_MAC_BYTE: |
|
2140 case PHY_WRITE_MAC_BYTE: |
|
2141 case PHY_WRITE_ERI_WORD: |
|
2142 default: |
|
2143 netif_err(tp, ifup, tp->dev, |
|
2144 "Invalid action 0x%08x\n", action); |
|
2145 goto out; |
|
2146 } |
|
2147 } |
|
2148 rc = true; |
|
2149 out: |
|
2150 return rc; |
|
2151 } |
|
2152 |
|
2153 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2154 { |
|
2155 struct net_device *dev = tp->dev; |
|
2156 int rc = -EINVAL; |
|
2157 |
|
2158 if (!rtl_fw_format_ok(tp, rtl_fw)) { |
|
2159 netif_err(tp, ifup, dev, "invalid firwmare\n"); |
|
2160 goto out; |
|
2161 } |
|
2162 |
|
2163 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) |
|
2164 rc = 0; |
|
2165 out: |
|
2166 return rc; |
|
2167 } |
|
2168 |
|
2169 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
|
2170 { |
|
2171 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
|
2172 u32 predata, count; |
|
2173 size_t index; |
|
2174 |
|
2175 predata = count = 0; |
|
2176 |
|
2177 for (index = 0; index < pa->size; ) { |
|
2178 u32 action = le32_to_cpu(pa->code[index]); |
|
2179 u32 data = action & 0x0000ffff; |
|
2180 u32 regno = (action & 0x0fff0000) >> 16; |
|
2181 |
|
2182 if (!action) |
|
2183 break; |
|
2184 |
|
2185 switch(action & 0xf0000000) { |
|
2186 case PHY_READ: |
|
2187 predata = rtl_readphy(tp, regno); |
|
2188 count++; |
|
2189 index++; |
|
2190 break; |
|
2191 case PHY_DATA_OR: |
|
2192 predata |= data; |
|
2193 index++; |
|
2194 break; |
|
2195 case PHY_DATA_AND: |
|
2196 predata &= data; |
|
2197 index++; |
|
2198 break; |
|
2199 case PHY_BJMPN: |
|
2200 index -= regno; |
|
2201 break; |
|
2202 case PHY_READ_EFUSE: |
|
2203 predata = rtl8168d_efuse_read(tp->mmio_addr, regno); |
|
2204 index++; |
|
2205 break; |
|
2206 case PHY_CLEAR_READCOUNT: |
|
2207 count = 0; |
|
2208 index++; |
|
2209 break; |
|
2210 case PHY_WRITE: |
|
2211 rtl_writephy(tp, regno, data); |
|
2212 index++; |
|
2213 break; |
|
2214 case PHY_READCOUNT_EQ_SKIP: |
|
2215 index += (count == data) ? 2 : 1; |
|
2216 break; |
|
2217 case PHY_COMP_EQ_SKIPN: |
|
2218 if (predata == data) |
|
2219 index += regno; |
|
2220 index++; |
|
2221 break; |
|
2222 case PHY_COMP_NEQ_SKIPN: |
|
2223 if (predata != data) |
|
2224 index += regno; |
|
2225 index++; |
|
2226 break; |
|
2227 case PHY_WRITE_PREVIOUS: |
|
2228 rtl_writephy(tp, regno, predata); |
|
2229 index++; |
|
2230 break; |
|
2231 case PHY_SKIPN: |
|
2232 index += regno + 1; |
|
2233 break; |
|
2234 case PHY_DELAY_MS: |
|
2235 mdelay(data); |
|
2236 index++; |
|
2237 break; |
|
2238 |
|
2239 case PHY_READ_MAC_BYTE: |
|
2240 case PHY_WRITE_MAC_BYTE: |
|
2241 case PHY_WRITE_ERI_WORD: |
|
2242 default: |
|
2243 BUG(); |
|
2244 } |
|
2245 } |
|
2246 } |
|
2247 |
|
2248 static void rtl_release_firmware(struct rtl8169_private *tp) |
|
2249 { |
|
2250 if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
|
2251 release_firmware(tp->rtl_fw->fw); |
|
2252 kfree(tp->rtl_fw); |
|
2253 } |
|
2254 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
2255 } |
|
2256 |
|
2257 static void rtl_apply_firmware(struct rtl8169_private *tp) |
|
2258 { |
|
2259 struct rtl_fw *rtl_fw = tp->rtl_fw; |
|
2260 |
|
2261 /* TODO: release firmware once rtl_phy_write_fw signals failures. */ |
|
2262 if (!IS_ERR_OR_NULL(rtl_fw)) |
|
2263 rtl_phy_write_fw(tp, rtl_fw); |
|
2264 } |
|
2265 |
|
2266 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) |
|
2267 { |
|
2268 if (rtl_readphy(tp, reg) != val) |
|
2269 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); |
|
2270 else |
|
2271 rtl_apply_firmware(tp); |
|
2272 } |
|
2273 |
|
2274 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
|
2275 { |
|
2276 static const struct phy_reg phy_reg_init[] = { |
|
2277 { 0x1f, 0x0001 }, |
|
2278 { 0x06, 0x006e }, |
|
2279 { 0x08, 0x0708 }, |
|
2280 { 0x15, 0x4000 }, |
|
2281 { 0x18, 0x65c7 }, |
|
2282 |
|
2283 { 0x1f, 0x0001 }, |
|
2284 { 0x03, 0x00a1 }, |
|
2285 { 0x02, 0x0008 }, |
|
2286 { 0x01, 0x0120 }, |
|
2287 { 0x00, 0x1000 }, |
|
2288 { 0x04, 0x0800 }, |
|
2289 { 0x04, 0x0000 }, |
|
2290 |
|
2291 { 0x03, 0xff41 }, |
|
2292 { 0x02, 0xdf60 }, |
|
2293 { 0x01, 0x0140 }, |
|
2294 { 0x00, 0x0077 }, |
|
2295 { 0x04, 0x7800 }, |
|
2296 { 0x04, 0x7000 }, |
|
2297 |
|
2298 { 0x03, 0x802f }, |
|
2299 { 0x02, 0x4f02 }, |
|
2300 { 0x01, 0x0409 }, |
|
2301 { 0x00, 0xf0f9 }, |
|
2302 { 0x04, 0x9800 }, |
|
2303 { 0x04, 0x9000 }, |
|
2304 |
|
2305 { 0x03, 0xdf01 }, |
|
2306 { 0x02, 0xdf20 }, |
|
2307 { 0x01, 0xff95 }, |
|
2308 { 0x00, 0xba00 }, |
|
2309 { 0x04, 0xa800 }, |
|
2310 { 0x04, 0xa000 }, |
|
2311 |
|
2312 { 0x03, 0xff41 }, |
|
2313 { 0x02, 0xdf20 }, |
|
2314 { 0x01, 0x0140 }, |
|
2315 { 0x00, 0x00bb }, |
|
2316 { 0x04, 0xb800 }, |
|
2317 { 0x04, 0xb000 }, |
|
2318 |
|
2319 { 0x03, 0xdf41 }, |
|
2320 { 0x02, 0xdc60 }, |
|
2321 { 0x01, 0x6340 }, |
|
2322 { 0x00, 0x007d }, |
|
2323 { 0x04, 0xd800 }, |
|
2324 { 0x04, 0xd000 }, |
|
2325 |
|
2326 { 0x03, 0xdf01 }, |
|
2327 { 0x02, 0xdf20 }, |
|
2328 { 0x01, 0x100a }, |
|
2329 { 0x00, 0xa0ff }, |
|
2330 { 0x04, 0xf800 }, |
|
2331 { 0x04, 0xf000 }, |
|
2332 |
|
2333 { 0x1f, 0x0000 }, |
|
2334 { 0x0b, 0x0000 }, |
|
2335 { 0x00, 0x9200 } |
|
2336 }; |
|
2337 |
|
2338 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2339 } |
|
2340 |
|
2341 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
|
2342 { |
|
2343 static const struct phy_reg phy_reg_init[] = { |
|
2344 { 0x1f, 0x0002 }, |
|
2345 { 0x01, 0x90d0 }, |
|
2346 { 0x1f, 0x0000 } |
|
2347 }; |
|
2348 |
|
2349 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2350 } |
|
2351 |
|
2352 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
|
2353 { |
|
2354 struct pci_dev *pdev = tp->pci_dev; |
|
2355 |
|
2356 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
|
2357 (pdev->subsystem_device != 0xe000)) |
|
2358 return; |
|
2359 |
|
2360 rtl_writephy(tp, 0x1f, 0x0001); |
|
2361 rtl_writephy(tp, 0x10, 0xf01b); |
|
2362 rtl_writephy(tp, 0x1f, 0x0000); |
|
2363 } |
|
2364 |
|
2365 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
|
2366 { |
|
2367 static const struct phy_reg phy_reg_init[] = { |
|
2368 { 0x1f, 0x0001 }, |
|
2369 { 0x04, 0x0000 }, |
|
2370 { 0x03, 0x00a1 }, |
|
2371 { 0x02, 0x0008 }, |
|
2372 { 0x01, 0x0120 }, |
|
2373 { 0x00, 0x1000 }, |
|
2374 { 0x04, 0x0800 }, |
|
2375 { 0x04, 0x9000 }, |
|
2376 { 0x03, 0x802f }, |
|
2377 { 0x02, 0x4f02 }, |
|
2378 { 0x01, 0x0409 }, |
|
2379 { 0x00, 0xf099 }, |
|
2380 { 0x04, 0x9800 }, |
|
2381 { 0x04, 0xa000 }, |
|
2382 { 0x03, 0xdf01 }, |
|
2383 { 0x02, 0xdf20 }, |
|
2384 { 0x01, 0xff95 }, |
|
2385 { 0x00, 0xba00 }, |
|
2386 { 0x04, 0xa800 }, |
|
2387 { 0x04, 0xf000 }, |
|
2388 { 0x03, 0xdf01 }, |
|
2389 { 0x02, 0xdf20 }, |
|
2390 { 0x01, 0x101a }, |
|
2391 { 0x00, 0xa0ff }, |
|
2392 { 0x04, 0xf800 }, |
|
2393 { 0x04, 0x0000 }, |
|
2394 { 0x1f, 0x0000 }, |
|
2395 |
|
2396 { 0x1f, 0x0001 }, |
|
2397 { 0x10, 0xf41b }, |
|
2398 { 0x14, 0xfb54 }, |
|
2399 { 0x18, 0xf5c7 }, |
|
2400 { 0x1f, 0x0000 }, |
|
2401 |
|
2402 { 0x1f, 0x0001 }, |
|
2403 { 0x17, 0x0cc0 }, |
|
2404 { 0x1f, 0x0000 } |
|
2405 }; |
|
2406 |
|
2407 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2408 |
|
2409 rtl8169scd_hw_phy_config_quirk(tp); |
|
2410 } |
|
2411 |
|
2412 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
|
2413 { |
|
2414 static const struct phy_reg phy_reg_init[] = { |
|
2415 { 0x1f, 0x0001 }, |
|
2416 { 0x04, 0x0000 }, |
|
2417 { 0x03, 0x00a1 }, |
|
2418 { 0x02, 0x0008 }, |
|
2419 { 0x01, 0x0120 }, |
|
2420 { 0x00, 0x1000 }, |
|
2421 { 0x04, 0x0800 }, |
|
2422 { 0x04, 0x9000 }, |
|
2423 { 0x03, 0x802f }, |
|
2424 { 0x02, 0x4f02 }, |
|
2425 { 0x01, 0x0409 }, |
|
2426 { 0x00, 0xf099 }, |
|
2427 { 0x04, 0x9800 }, |
|
2428 { 0x04, 0xa000 }, |
|
2429 { 0x03, 0xdf01 }, |
|
2430 { 0x02, 0xdf20 }, |
|
2431 { 0x01, 0xff95 }, |
|
2432 { 0x00, 0xba00 }, |
|
2433 { 0x04, 0xa800 }, |
|
2434 { 0x04, 0xf000 }, |
|
2435 { 0x03, 0xdf01 }, |
|
2436 { 0x02, 0xdf20 }, |
|
2437 { 0x01, 0x101a }, |
|
2438 { 0x00, 0xa0ff }, |
|
2439 { 0x04, 0xf800 }, |
|
2440 { 0x04, 0x0000 }, |
|
2441 { 0x1f, 0x0000 }, |
|
2442 |
|
2443 { 0x1f, 0x0001 }, |
|
2444 { 0x0b, 0x8480 }, |
|
2445 { 0x1f, 0x0000 }, |
|
2446 |
|
2447 { 0x1f, 0x0001 }, |
|
2448 { 0x18, 0x67c7 }, |
|
2449 { 0x04, 0x2000 }, |
|
2450 { 0x03, 0x002f }, |
|
2451 { 0x02, 0x4360 }, |
|
2452 { 0x01, 0x0109 }, |
|
2453 { 0x00, 0x3022 }, |
|
2454 { 0x04, 0x2800 }, |
|
2455 { 0x1f, 0x0000 }, |
|
2456 |
|
2457 { 0x1f, 0x0001 }, |
|
2458 { 0x17, 0x0cc0 }, |
|
2459 { 0x1f, 0x0000 } |
|
2460 }; |
|
2461 |
|
2462 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2463 } |
|
2464 |
|
2465 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
|
2466 { |
|
2467 static const struct phy_reg phy_reg_init[] = { |
|
2468 { 0x10, 0xf41b }, |
|
2469 { 0x1f, 0x0000 } |
|
2470 }; |
|
2471 |
|
2472 rtl_writephy(tp, 0x1f, 0x0001); |
|
2473 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2474 |
|
2475 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2476 } |
|
2477 |
|
2478 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
|
2479 { |
|
2480 static const struct phy_reg phy_reg_init[] = { |
|
2481 { 0x1f, 0x0001 }, |
|
2482 { 0x10, 0xf41b }, |
|
2483 { 0x1f, 0x0000 } |
|
2484 }; |
|
2485 |
|
2486 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2487 } |
|
2488 |
|
2489 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
|
2490 { |
|
2491 static const struct phy_reg phy_reg_init[] = { |
|
2492 { 0x1f, 0x0000 }, |
|
2493 { 0x1d, 0x0f00 }, |
|
2494 { 0x1f, 0x0002 }, |
|
2495 { 0x0c, 0x1ec8 }, |
|
2496 { 0x1f, 0x0000 } |
|
2497 }; |
|
2498 |
|
2499 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2500 } |
|
2501 |
|
2502 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
|
2503 { |
|
2504 static const struct phy_reg phy_reg_init[] = { |
|
2505 { 0x1f, 0x0001 }, |
|
2506 { 0x1d, 0x3d98 }, |
|
2507 { 0x1f, 0x0000 } |
|
2508 }; |
|
2509 |
|
2510 rtl_writephy(tp, 0x1f, 0x0000); |
|
2511 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2512 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2513 |
|
2514 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2515 } |
|
2516 |
|
2517 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
|
2518 { |
|
2519 static const struct phy_reg phy_reg_init[] = { |
|
2520 { 0x1f, 0x0001 }, |
|
2521 { 0x12, 0x2300 }, |
|
2522 { 0x1f, 0x0002 }, |
|
2523 { 0x00, 0x88d4 }, |
|
2524 { 0x01, 0x82b1 }, |
|
2525 { 0x03, 0x7002 }, |
|
2526 { 0x08, 0x9e30 }, |
|
2527 { 0x09, 0x01f0 }, |
|
2528 { 0x0a, 0x5500 }, |
|
2529 { 0x0c, 0x00c8 }, |
|
2530 { 0x1f, 0x0003 }, |
|
2531 { 0x12, 0xc096 }, |
|
2532 { 0x16, 0x000a }, |
|
2533 { 0x1f, 0x0000 }, |
|
2534 { 0x1f, 0x0000 }, |
|
2535 { 0x09, 0x2000 }, |
|
2536 { 0x09, 0x0000 } |
|
2537 }; |
|
2538 |
|
2539 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2540 |
|
2541 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2542 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2543 rtl_writephy(tp, 0x1f, 0x0000); |
|
2544 } |
|
2545 |
|
2546 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
|
2547 { |
|
2548 static const struct phy_reg phy_reg_init[] = { |
|
2549 { 0x1f, 0x0001 }, |
|
2550 { 0x12, 0x2300 }, |
|
2551 { 0x03, 0x802f }, |
|
2552 { 0x02, 0x4f02 }, |
|
2553 { 0x01, 0x0409 }, |
|
2554 { 0x00, 0xf099 }, |
|
2555 { 0x04, 0x9800 }, |
|
2556 { 0x04, 0x9000 }, |
|
2557 { 0x1d, 0x3d98 }, |
|
2558 { 0x1f, 0x0002 }, |
|
2559 { 0x0c, 0x7eb8 }, |
|
2560 { 0x06, 0x0761 }, |
|
2561 { 0x1f, 0x0003 }, |
|
2562 { 0x16, 0x0f0a }, |
|
2563 { 0x1f, 0x0000 } |
|
2564 }; |
|
2565 |
|
2566 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2567 |
|
2568 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2569 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2570 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2571 rtl_writephy(tp, 0x1f, 0x0000); |
|
2572 } |
|
2573 |
|
2574 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
|
2575 { |
|
2576 static const struct phy_reg phy_reg_init[] = { |
|
2577 { 0x1f, 0x0001 }, |
|
2578 { 0x12, 0x2300 }, |
|
2579 { 0x1d, 0x3d98 }, |
|
2580 { 0x1f, 0x0002 }, |
|
2581 { 0x0c, 0x7eb8 }, |
|
2582 { 0x06, 0x5461 }, |
|
2583 { 0x1f, 0x0003 }, |
|
2584 { 0x16, 0x0f0a }, |
|
2585 { 0x1f, 0x0000 } |
|
2586 }; |
|
2587 |
|
2588 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2589 |
|
2590 rtl_patchphy(tp, 0x16, 1 << 0); |
|
2591 rtl_patchphy(tp, 0x14, 1 << 5); |
|
2592 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2593 rtl_writephy(tp, 0x1f, 0x0000); |
|
2594 } |
|
2595 |
|
2596 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
|
2597 { |
|
2598 rtl8168c_3_hw_phy_config(tp); |
|
2599 } |
|
2600 |
|
2601 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
|
2602 { |
|
2603 static const struct phy_reg phy_reg_init_0[] = { |
|
2604 /* Channel Estimation */ |
|
2605 { 0x1f, 0x0001 }, |
|
2606 { 0x06, 0x4064 }, |
|
2607 { 0x07, 0x2863 }, |
|
2608 { 0x08, 0x059c }, |
|
2609 { 0x09, 0x26b4 }, |
|
2610 { 0x0a, 0x6a19 }, |
|
2611 { 0x0b, 0xdcc8 }, |
|
2612 { 0x10, 0xf06d }, |
|
2613 { 0x14, 0x7f68 }, |
|
2614 { 0x18, 0x7fd9 }, |
|
2615 { 0x1c, 0xf0ff }, |
|
2616 { 0x1d, 0x3d9c }, |
|
2617 { 0x1f, 0x0003 }, |
|
2618 { 0x12, 0xf49f }, |
|
2619 { 0x13, 0x070b }, |
|
2620 { 0x1a, 0x05ad }, |
|
2621 { 0x14, 0x94c0 }, |
|
2622 |
|
2623 /* |
|
2624 * Tx Error Issue |
|
2625 * Enhance line driver power |
|
2626 */ |
|
2627 { 0x1f, 0x0002 }, |
|
2628 { 0x06, 0x5561 }, |
|
2629 { 0x1f, 0x0005 }, |
|
2630 { 0x05, 0x8332 }, |
|
2631 { 0x06, 0x5561 }, |
|
2632 |
|
2633 /* |
|
2634 * Can not link to 1Gbps with bad cable |
|
2635 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2636 */ |
|
2637 { 0x1f, 0x0001 }, |
|
2638 { 0x17, 0x0cc0 }, |
|
2639 |
|
2640 { 0x1f, 0x0000 }, |
|
2641 { 0x0d, 0xf880 } |
|
2642 }; |
|
2643 void __iomem *ioaddr = tp->mmio_addr; |
|
2644 |
|
2645 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2646 |
|
2647 /* |
|
2648 * Rx Error Issue |
|
2649 * Fine Tune Switching regulator parameter |
|
2650 */ |
|
2651 rtl_writephy(tp, 0x1f, 0x0002); |
|
2652 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); |
|
2653 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); |
|
2654 |
|
2655 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2656 static const struct phy_reg phy_reg_init[] = { |
|
2657 { 0x1f, 0x0002 }, |
|
2658 { 0x05, 0x669a }, |
|
2659 { 0x1f, 0x0005 }, |
|
2660 { 0x05, 0x8330 }, |
|
2661 { 0x06, 0x669a }, |
|
2662 { 0x1f, 0x0002 } |
|
2663 }; |
|
2664 int val; |
|
2665 |
|
2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2667 |
|
2668 val = rtl_readphy(tp, 0x0d); |
|
2669 |
|
2670 if ((val & 0x00ff) != 0x006c) { |
|
2671 static const u32 set[] = { |
|
2672 0x0065, 0x0066, 0x0067, 0x0068, |
|
2673 0x0069, 0x006a, 0x006b, 0x006c |
|
2674 }; |
|
2675 int i; |
|
2676 |
|
2677 rtl_writephy(tp, 0x1f, 0x0002); |
|
2678 |
|
2679 val &= 0xff00; |
|
2680 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2681 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2682 } |
|
2683 } else { |
|
2684 static const struct phy_reg phy_reg_init[] = { |
|
2685 { 0x1f, 0x0002 }, |
|
2686 { 0x05, 0x6662 }, |
|
2687 { 0x1f, 0x0005 }, |
|
2688 { 0x05, 0x8330 }, |
|
2689 { 0x06, 0x6662 } |
|
2690 }; |
|
2691 |
|
2692 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2693 } |
|
2694 |
|
2695 /* RSET couple improve */ |
|
2696 rtl_writephy(tp, 0x1f, 0x0002); |
|
2697 rtl_patchphy(tp, 0x0d, 0x0300); |
|
2698 rtl_patchphy(tp, 0x0f, 0x0010); |
|
2699 |
|
2700 /* Fine tune PLL performance */ |
|
2701 rtl_writephy(tp, 0x1f, 0x0002); |
|
2702 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2703 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2704 |
|
2705 rtl_writephy(tp, 0x1f, 0x0005); |
|
2706 rtl_writephy(tp, 0x05, 0x001b); |
|
2707 |
|
2708 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); |
|
2709 |
|
2710 rtl_writephy(tp, 0x1f, 0x0000); |
|
2711 } |
|
2712 |
|
2713 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
|
2714 { |
|
2715 static const struct phy_reg phy_reg_init_0[] = { |
|
2716 /* Channel Estimation */ |
|
2717 { 0x1f, 0x0001 }, |
|
2718 { 0x06, 0x4064 }, |
|
2719 { 0x07, 0x2863 }, |
|
2720 { 0x08, 0x059c }, |
|
2721 { 0x09, 0x26b4 }, |
|
2722 { 0x0a, 0x6a19 }, |
|
2723 { 0x0b, 0xdcc8 }, |
|
2724 { 0x10, 0xf06d }, |
|
2725 { 0x14, 0x7f68 }, |
|
2726 { 0x18, 0x7fd9 }, |
|
2727 { 0x1c, 0xf0ff }, |
|
2728 { 0x1d, 0x3d9c }, |
|
2729 { 0x1f, 0x0003 }, |
|
2730 { 0x12, 0xf49f }, |
|
2731 { 0x13, 0x070b }, |
|
2732 { 0x1a, 0x05ad }, |
|
2733 { 0x14, 0x94c0 }, |
|
2734 |
|
2735 /* |
|
2736 * Tx Error Issue |
|
2737 * Enhance line driver power |
|
2738 */ |
|
2739 { 0x1f, 0x0002 }, |
|
2740 { 0x06, 0x5561 }, |
|
2741 { 0x1f, 0x0005 }, |
|
2742 { 0x05, 0x8332 }, |
|
2743 { 0x06, 0x5561 }, |
|
2744 |
|
2745 /* |
|
2746 * Can not link to 1Gbps with bad cable |
|
2747 * Decrease SNR threshold form 21.07dB to 19.04dB |
|
2748 */ |
|
2749 { 0x1f, 0x0001 }, |
|
2750 { 0x17, 0x0cc0 }, |
|
2751 |
|
2752 { 0x1f, 0x0000 }, |
|
2753 { 0x0d, 0xf880 } |
|
2754 }; |
|
2755 void __iomem *ioaddr = tp->mmio_addr; |
|
2756 |
|
2757 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
|
2758 |
|
2759 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
|
2760 static const struct phy_reg phy_reg_init[] = { |
|
2761 { 0x1f, 0x0002 }, |
|
2762 { 0x05, 0x669a }, |
|
2763 { 0x1f, 0x0005 }, |
|
2764 { 0x05, 0x8330 }, |
|
2765 { 0x06, 0x669a }, |
|
2766 |
|
2767 { 0x1f, 0x0002 } |
|
2768 }; |
|
2769 int val; |
|
2770 |
|
2771 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2772 |
|
2773 val = rtl_readphy(tp, 0x0d); |
|
2774 if ((val & 0x00ff) != 0x006c) { |
|
2775 static const u32 set[] = { |
|
2776 0x0065, 0x0066, 0x0067, 0x0068, |
|
2777 0x0069, 0x006a, 0x006b, 0x006c |
|
2778 }; |
|
2779 int i; |
|
2780 |
|
2781 rtl_writephy(tp, 0x1f, 0x0002); |
|
2782 |
|
2783 val &= 0xff00; |
|
2784 for (i = 0; i < ARRAY_SIZE(set); i++) |
|
2785 rtl_writephy(tp, 0x0d, val | set[i]); |
|
2786 } |
|
2787 } else { |
|
2788 static const struct phy_reg phy_reg_init[] = { |
|
2789 { 0x1f, 0x0002 }, |
|
2790 { 0x05, 0x2642 }, |
|
2791 { 0x1f, 0x0005 }, |
|
2792 { 0x05, 0x8330 }, |
|
2793 { 0x06, 0x2642 } |
|
2794 }; |
|
2795 |
|
2796 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2797 } |
|
2798 |
|
2799 /* Fine tune PLL performance */ |
|
2800 rtl_writephy(tp, 0x1f, 0x0002); |
|
2801 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); |
|
2802 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); |
|
2803 |
|
2804 /* Switching regulator Slew rate */ |
|
2805 rtl_writephy(tp, 0x1f, 0x0002); |
|
2806 rtl_patchphy(tp, 0x0f, 0x0017); |
|
2807 |
|
2808 rtl_writephy(tp, 0x1f, 0x0005); |
|
2809 rtl_writephy(tp, 0x05, 0x001b); |
|
2810 |
|
2811 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); |
|
2812 |
|
2813 rtl_writephy(tp, 0x1f, 0x0000); |
|
2814 } |
|
2815 |
|
2816 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
|
2817 { |
|
2818 static const struct phy_reg phy_reg_init[] = { |
|
2819 { 0x1f, 0x0002 }, |
|
2820 { 0x10, 0x0008 }, |
|
2821 { 0x0d, 0x006c }, |
|
2822 |
|
2823 { 0x1f, 0x0000 }, |
|
2824 { 0x0d, 0xf880 }, |
|
2825 |
|
2826 { 0x1f, 0x0001 }, |
|
2827 { 0x17, 0x0cc0 }, |
|
2828 |
|
2829 { 0x1f, 0x0001 }, |
|
2830 { 0x0b, 0xa4d8 }, |
|
2831 { 0x09, 0x281c }, |
|
2832 { 0x07, 0x2883 }, |
|
2833 { 0x0a, 0x6b35 }, |
|
2834 { 0x1d, 0x3da4 }, |
|
2835 { 0x1c, 0xeffd }, |
|
2836 { 0x14, 0x7f52 }, |
|
2837 { 0x18, 0x7fc6 }, |
|
2838 { 0x08, 0x0601 }, |
|
2839 { 0x06, 0x4063 }, |
|
2840 { 0x10, 0xf074 }, |
|
2841 { 0x1f, 0x0003 }, |
|
2842 { 0x13, 0x0789 }, |
|
2843 { 0x12, 0xf4bd }, |
|
2844 { 0x1a, 0x04fd }, |
|
2845 { 0x14, 0x84b0 }, |
|
2846 { 0x1f, 0x0000 }, |
|
2847 { 0x00, 0x9200 }, |
|
2848 |
|
2849 { 0x1f, 0x0005 }, |
|
2850 { 0x01, 0x0340 }, |
|
2851 { 0x1f, 0x0001 }, |
|
2852 { 0x04, 0x4000 }, |
|
2853 { 0x03, 0x1d21 }, |
|
2854 { 0x02, 0x0c32 }, |
|
2855 { 0x01, 0x0200 }, |
|
2856 { 0x00, 0x5554 }, |
|
2857 { 0x04, 0x4800 }, |
|
2858 { 0x04, 0x4000 }, |
|
2859 { 0x04, 0xf000 }, |
|
2860 { 0x03, 0xdf01 }, |
|
2861 { 0x02, 0xdf20 }, |
|
2862 { 0x01, 0x101a }, |
|
2863 { 0x00, 0xa0ff }, |
|
2864 { 0x04, 0xf800 }, |
|
2865 { 0x04, 0xf000 }, |
|
2866 { 0x1f, 0x0000 }, |
|
2867 |
|
2868 { 0x1f, 0x0007 }, |
|
2869 { 0x1e, 0x0023 }, |
|
2870 { 0x16, 0x0000 }, |
|
2871 { 0x1f, 0x0000 } |
|
2872 }; |
|
2873 |
|
2874 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2875 } |
|
2876 |
|
2877 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
|
2878 { |
|
2879 static const struct phy_reg phy_reg_init[] = { |
|
2880 { 0x1f, 0x0001 }, |
|
2881 { 0x17, 0x0cc0 }, |
|
2882 |
|
2883 { 0x1f, 0x0007 }, |
|
2884 { 0x1e, 0x002d }, |
|
2885 { 0x18, 0x0040 }, |
|
2886 { 0x1f, 0x0000 } |
|
2887 }; |
|
2888 |
|
2889 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2890 rtl_patchphy(tp, 0x0d, 1 << 5); |
|
2891 } |
|
2892 |
|
2893 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
|
2894 { |
|
2895 static const struct phy_reg phy_reg_init[] = { |
|
2896 /* Enable Delay cap */ |
|
2897 { 0x1f, 0x0005 }, |
|
2898 { 0x05, 0x8b80 }, |
|
2899 { 0x06, 0xc896 }, |
|
2900 { 0x1f, 0x0000 }, |
|
2901 |
|
2902 /* Channel estimation fine tune */ |
|
2903 { 0x1f, 0x0001 }, |
|
2904 { 0x0b, 0x6c20 }, |
|
2905 { 0x07, 0x2872 }, |
|
2906 { 0x1c, 0xefff }, |
|
2907 { 0x1f, 0x0003 }, |
|
2908 { 0x14, 0x6420 }, |
|
2909 { 0x1f, 0x0000 }, |
|
2910 |
|
2911 /* Update PFM & 10M TX idle timer */ |
|
2912 { 0x1f, 0x0007 }, |
|
2913 { 0x1e, 0x002f }, |
|
2914 { 0x15, 0x1919 }, |
|
2915 { 0x1f, 0x0000 }, |
|
2916 |
|
2917 { 0x1f, 0x0007 }, |
|
2918 { 0x1e, 0x00ac }, |
|
2919 { 0x18, 0x0006 }, |
|
2920 { 0x1f, 0x0000 } |
|
2921 }; |
|
2922 |
|
2923 rtl_apply_firmware(tp); |
|
2924 |
|
2925 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2926 |
|
2927 /* DCO enable for 10M IDLE Power */ |
|
2928 rtl_writephy(tp, 0x1f, 0x0007); |
|
2929 rtl_writephy(tp, 0x1e, 0x0023); |
|
2930 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
2931 rtl_writephy(tp, 0x1f, 0x0000); |
|
2932 |
|
2933 /* For impedance matching */ |
|
2934 rtl_writephy(tp, 0x1f, 0x0002); |
|
2935 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); |
|
2936 rtl_writephy(tp, 0x1f, 0x0000); |
|
2937 |
|
2938 /* PHY auto speed down */ |
|
2939 rtl_writephy(tp, 0x1f, 0x0007); |
|
2940 rtl_writephy(tp, 0x1e, 0x002d); |
|
2941 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); |
|
2942 rtl_writephy(tp, 0x1f, 0x0000); |
|
2943 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
2944 |
|
2945 rtl_writephy(tp, 0x1f, 0x0005); |
|
2946 rtl_writephy(tp, 0x05, 0x8b86); |
|
2947 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
2948 rtl_writephy(tp, 0x1f, 0x0000); |
|
2949 |
|
2950 rtl_writephy(tp, 0x1f, 0x0005); |
|
2951 rtl_writephy(tp, 0x05, 0x8b85); |
|
2952 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
2953 rtl_writephy(tp, 0x1f, 0x0007); |
|
2954 rtl_writephy(tp, 0x1e, 0x0020); |
|
2955 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); |
|
2956 rtl_writephy(tp, 0x1f, 0x0006); |
|
2957 rtl_writephy(tp, 0x00, 0x5a00); |
|
2958 rtl_writephy(tp, 0x1f, 0x0000); |
|
2959 rtl_writephy(tp, 0x0d, 0x0007); |
|
2960 rtl_writephy(tp, 0x0e, 0x003c); |
|
2961 rtl_writephy(tp, 0x0d, 0x4007); |
|
2962 rtl_writephy(tp, 0x0e, 0x0000); |
|
2963 rtl_writephy(tp, 0x0d, 0x0000); |
|
2964 } |
|
2965 |
|
2966 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
|
2967 { |
|
2968 static const struct phy_reg phy_reg_init[] = { |
|
2969 /* Enable Delay cap */ |
|
2970 { 0x1f, 0x0004 }, |
|
2971 { 0x1f, 0x0007 }, |
|
2972 { 0x1e, 0x00ac }, |
|
2973 { 0x18, 0x0006 }, |
|
2974 { 0x1f, 0x0002 }, |
|
2975 { 0x1f, 0x0000 }, |
|
2976 { 0x1f, 0x0000 }, |
|
2977 |
|
2978 /* Channel estimation fine tune */ |
|
2979 { 0x1f, 0x0003 }, |
|
2980 { 0x09, 0xa20f }, |
|
2981 { 0x1f, 0x0000 }, |
|
2982 { 0x1f, 0x0000 }, |
|
2983 |
|
2984 /* Green Setting */ |
|
2985 { 0x1f, 0x0005 }, |
|
2986 { 0x05, 0x8b5b }, |
|
2987 { 0x06, 0x9222 }, |
|
2988 { 0x05, 0x8b6d }, |
|
2989 { 0x06, 0x8000 }, |
|
2990 { 0x05, 0x8b76 }, |
|
2991 { 0x06, 0x8000 }, |
|
2992 { 0x1f, 0x0000 } |
|
2993 }; |
|
2994 |
|
2995 rtl_apply_firmware(tp); |
|
2996 |
|
2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
2998 |
|
2999 /* For 4-corner performance improve */ |
|
3000 rtl_writephy(tp, 0x1f, 0x0005); |
|
3001 rtl_writephy(tp, 0x05, 0x8b80); |
|
3002 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); |
|
3003 rtl_writephy(tp, 0x1f, 0x0000); |
|
3004 |
|
3005 /* PHY auto speed down */ |
|
3006 rtl_writephy(tp, 0x1f, 0x0004); |
|
3007 rtl_writephy(tp, 0x1f, 0x0007); |
|
3008 rtl_writephy(tp, 0x1e, 0x002d); |
|
3009 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3010 rtl_writephy(tp, 0x1f, 0x0002); |
|
3011 rtl_writephy(tp, 0x1f, 0x0000); |
|
3012 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3013 |
|
3014 /* improve 10M EEE waveform */ |
|
3015 rtl_writephy(tp, 0x1f, 0x0005); |
|
3016 rtl_writephy(tp, 0x05, 0x8b86); |
|
3017 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3018 rtl_writephy(tp, 0x1f, 0x0000); |
|
3019 |
|
3020 /* Improve 2-pair detection performance */ |
|
3021 rtl_writephy(tp, 0x1f, 0x0005); |
|
3022 rtl_writephy(tp, 0x05, 0x8b85); |
|
3023 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3024 rtl_writephy(tp, 0x1f, 0x0000); |
|
3025 |
|
3026 /* EEE setting */ |
|
3027 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, |
|
3028 ERIAR_EXGMAC); |
|
3029 rtl_writephy(tp, 0x1f, 0x0005); |
|
3030 rtl_writephy(tp, 0x05, 0x8b85); |
|
3031 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); |
|
3032 rtl_writephy(tp, 0x1f, 0x0004); |
|
3033 rtl_writephy(tp, 0x1f, 0x0007); |
|
3034 rtl_writephy(tp, 0x1e, 0x0020); |
|
3035 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
|
3036 rtl_writephy(tp, 0x1f, 0x0002); |
|
3037 rtl_writephy(tp, 0x1f, 0x0000); |
|
3038 rtl_writephy(tp, 0x0d, 0x0007); |
|
3039 rtl_writephy(tp, 0x0e, 0x003c); |
|
3040 rtl_writephy(tp, 0x0d, 0x4007); |
|
3041 rtl_writephy(tp, 0x0e, 0x0000); |
|
3042 rtl_writephy(tp, 0x0d, 0x0000); |
|
3043 |
|
3044 /* Green feature */ |
|
3045 rtl_writephy(tp, 0x1f, 0x0003); |
|
3046 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); |
|
3047 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); |
|
3048 rtl_writephy(tp, 0x1f, 0x0000); |
|
3049 } |
|
3050 |
|
3051 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
|
3052 { |
|
3053 static const struct phy_reg phy_reg_init[] = { |
|
3054 /* Channel estimation fine tune */ |
|
3055 { 0x1f, 0x0003 }, |
|
3056 { 0x09, 0xa20f }, |
|
3057 { 0x1f, 0x0000 }, |
|
3058 |
|
3059 /* Modify green table for giga & fnet */ |
|
3060 { 0x1f, 0x0005 }, |
|
3061 { 0x05, 0x8b55 }, |
|
3062 { 0x06, 0x0000 }, |
|
3063 { 0x05, 0x8b5e }, |
|
3064 { 0x06, 0x0000 }, |
|
3065 { 0x05, 0x8b67 }, |
|
3066 { 0x06, 0x0000 }, |
|
3067 { 0x05, 0x8b70 }, |
|
3068 { 0x06, 0x0000 }, |
|
3069 { 0x1f, 0x0000 }, |
|
3070 { 0x1f, 0x0007 }, |
|
3071 { 0x1e, 0x0078 }, |
|
3072 { 0x17, 0x0000 }, |
|
3073 { 0x19, 0x00fb }, |
|
3074 { 0x1f, 0x0000 }, |
|
3075 |
|
3076 /* Modify green table for 10M */ |
|
3077 { 0x1f, 0x0005 }, |
|
3078 { 0x05, 0x8b79 }, |
|
3079 { 0x06, 0xaa00 }, |
|
3080 { 0x1f, 0x0000 }, |
|
3081 |
|
3082 /* Disable hiimpedance detection (RTCT) */ |
|
3083 { 0x1f, 0x0003 }, |
|
3084 { 0x01, 0x328a }, |
|
3085 { 0x1f, 0x0000 } |
|
3086 }; |
|
3087 |
|
3088 rtl_apply_firmware(tp); |
|
3089 |
|
3090 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3091 |
|
3092 /* For 4-corner performance improve */ |
|
3093 rtl_writephy(tp, 0x1f, 0x0005); |
|
3094 rtl_writephy(tp, 0x05, 0x8b80); |
|
3095 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3096 rtl_writephy(tp, 0x1f, 0x0000); |
|
3097 |
|
3098 /* PHY auto speed down */ |
|
3099 rtl_writephy(tp, 0x1f, 0x0007); |
|
3100 rtl_writephy(tp, 0x1e, 0x002d); |
|
3101 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3102 rtl_writephy(tp, 0x1f, 0x0000); |
|
3103 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3104 |
|
3105 /* Improve 10M EEE waveform */ |
|
3106 rtl_writephy(tp, 0x1f, 0x0005); |
|
3107 rtl_writephy(tp, 0x05, 0x8b86); |
|
3108 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3109 rtl_writephy(tp, 0x1f, 0x0000); |
|
3110 |
|
3111 /* Improve 2-pair detection performance */ |
|
3112 rtl_writephy(tp, 0x1f, 0x0005); |
|
3113 rtl_writephy(tp, 0x05, 0x8b85); |
|
3114 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); |
|
3115 rtl_writephy(tp, 0x1f, 0x0000); |
|
3116 } |
|
3117 |
|
3118 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) |
|
3119 { |
|
3120 rtl_apply_firmware(tp); |
|
3121 |
|
3122 /* For 4-corner performance improve */ |
|
3123 rtl_writephy(tp, 0x1f, 0x0005); |
|
3124 rtl_writephy(tp, 0x05, 0x8b80); |
|
3125 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); |
|
3126 rtl_writephy(tp, 0x1f, 0x0000); |
|
3127 |
|
3128 /* PHY auto speed down */ |
|
3129 rtl_writephy(tp, 0x1f, 0x0007); |
|
3130 rtl_writephy(tp, 0x1e, 0x002d); |
|
3131 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); |
|
3132 rtl_writephy(tp, 0x1f, 0x0000); |
|
3133 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); |
|
3134 |
|
3135 /* Improve 10M EEE waveform */ |
|
3136 rtl_writephy(tp, 0x1f, 0x0005); |
|
3137 rtl_writephy(tp, 0x05, 0x8b86); |
|
3138 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); |
|
3139 rtl_writephy(tp, 0x1f, 0x0000); |
|
3140 } |
|
3141 |
|
3142 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
|
3143 { |
|
3144 static const struct phy_reg phy_reg_init[] = { |
|
3145 { 0x1f, 0x0003 }, |
|
3146 { 0x08, 0x441d }, |
|
3147 { 0x01, 0x9100 }, |
|
3148 { 0x1f, 0x0000 } |
|
3149 }; |
|
3150 |
|
3151 rtl_writephy(tp, 0x1f, 0x0000); |
|
3152 rtl_patchphy(tp, 0x11, 1 << 12); |
|
3153 rtl_patchphy(tp, 0x19, 1 << 13); |
|
3154 rtl_patchphy(tp, 0x10, 1 << 15); |
|
3155 |
|
3156 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3157 } |
|
3158 |
|
3159 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
|
3160 { |
|
3161 static const struct phy_reg phy_reg_init[] = { |
|
3162 { 0x1f, 0x0005 }, |
|
3163 { 0x1a, 0x0000 }, |
|
3164 { 0x1f, 0x0000 }, |
|
3165 |
|
3166 { 0x1f, 0x0004 }, |
|
3167 { 0x1c, 0x0000 }, |
|
3168 { 0x1f, 0x0000 }, |
|
3169 |
|
3170 { 0x1f, 0x0001 }, |
|
3171 { 0x15, 0x7701 }, |
|
3172 { 0x1f, 0x0000 } |
|
3173 }; |
|
3174 |
|
3175 /* Disable ALDPS before ram code */ |
|
3176 rtl_writephy(tp, 0x1f, 0x0000); |
|
3177 rtl_writephy(tp, 0x18, 0x0310); |
|
3178 msleep(100); |
|
3179 |
|
3180 rtl_apply_firmware(tp); |
|
3181 |
|
3182 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
|
3183 } |
|
3184 |
|
3185 static void rtl_hw_phy_config(struct net_device *dev) |
|
3186 { |
|
3187 struct rtl8169_private *tp = netdev_priv(dev); |
|
3188 |
|
3189 rtl8169_print_mac_version(tp); |
|
3190 |
|
3191 switch (tp->mac_version) { |
|
3192 case RTL_GIGA_MAC_VER_01: |
|
3193 break; |
|
3194 case RTL_GIGA_MAC_VER_02: |
|
3195 case RTL_GIGA_MAC_VER_03: |
|
3196 rtl8169s_hw_phy_config(tp); |
|
3197 break; |
|
3198 case RTL_GIGA_MAC_VER_04: |
|
3199 rtl8169sb_hw_phy_config(tp); |
|
3200 break; |
|
3201 case RTL_GIGA_MAC_VER_05: |
|
3202 rtl8169scd_hw_phy_config(tp); |
|
3203 break; |
|
3204 case RTL_GIGA_MAC_VER_06: |
|
3205 rtl8169sce_hw_phy_config(tp); |
|
3206 break; |
|
3207 case RTL_GIGA_MAC_VER_07: |
|
3208 case RTL_GIGA_MAC_VER_08: |
|
3209 case RTL_GIGA_MAC_VER_09: |
|
3210 rtl8102e_hw_phy_config(tp); |
|
3211 break; |
|
3212 case RTL_GIGA_MAC_VER_11: |
|
3213 rtl8168bb_hw_phy_config(tp); |
|
3214 break; |
|
3215 case RTL_GIGA_MAC_VER_12: |
|
3216 rtl8168bef_hw_phy_config(tp); |
|
3217 break; |
|
3218 case RTL_GIGA_MAC_VER_17: |
|
3219 rtl8168bef_hw_phy_config(tp); |
|
3220 break; |
|
3221 case RTL_GIGA_MAC_VER_18: |
|
3222 rtl8168cp_1_hw_phy_config(tp); |
|
3223 break; |
|
3224 case RTL_GIGA_MAC_VER_19: |
|
3225 rtl8168c_1_hw_phy_config(tp); |
|
3226 break; |
|
3227 case RTL_GIGA_MAC_VER_20: |
|
3228 rtl8168c_2_hw_phy_config(tp); |
|
3229 break; |
|
3230 case RTL_GIGA_MAC_VER_21: |
|
3231 rtl8168c_3_hw_phy_config(tp); |
|
3232 break; |
|
3233 case RTL_GIGA_MAC_VER_22: |
|
3234 rtl8168c_4_hw_phy_config(tp); |
|
3235 break; |
|
3236 case RTL_GIGA_MAC_VER_23: |
|
3237 case RTL_GIGA_MAC_VER_24: |
|
3238 rtl8168cp_2_hw_phy_config(tp); |
|
3239 break; |
|
3240 case RTL_GIGA_MAC_VER_25: |
|
3241 rtl8168d_1_hw_phy_config(tp); |
|
3242 break; |
|
3243 case RTL_GIGA_MAC_VER_26: |
|
3244 rtl8168d_2_hw_phy_config(tp); |
|
3245 break; |
|
3246 case RTL_GIGA_MAC_VER_27: |
|
3247 rtl8168d_3_hw_phy_config(tp); |
|
3248 break; |
|
3249 case RTL_GIGA_MAC_VER_28: |
|
3250 rtl8168d_4_hw_phy_config(tp); |
|
3251 break; |
|
3252 case RTL_GIGA_MAC_VER_29: |
|
3253 case RTL_GIGA_MAC_VER_30: |
|
3254 rtl8105e_hw_phy_config(tp); |
|
3255 break; |
|
3256 case RTL_GIGA_MAC_VER_31: |
|
3257 /* None. */ |
|
3258 break; |
|
3259 case RTL_GIGA_MAC_VER_32: |
|
3260 case RTL_GIGA_MAC_VER_33: |
|
3261 rtl8168e_1_hw_phy_config(tp); |
|
3262 break; |
|
3263 case RTL_GIGA_MAC_VER_34: |
|
3264 rtl8168e_2_hw_phy_config(tp); |
|
3265 break; |
|
3266 case RTL_GIGA_MAC_VER_35: |
|
3267 rtl8168f_1_hw_phy_config(tp); |
|
3268 break; |
|
3269 case RTL_GIGA_MAC_VER_36: |
|
3270 rtl8168f_2_hw_phy_config(tp); |
|
3271 break; |
|
3272 |
|
3273 default: |
|
3274 break; |
|
3275 } |
|
3276 } |
|
3277 |
|
3278 static void rtl_phy_work(struct rtl8169_private *tp) |
|
3279 { |
|
3280 struct timer_list *timer = &tp->timer; |
|
3281 void __iomem *ioaddr = tp->mmio_addr; |
|
3282 unsigned long timeout = RTL8169_PHY_TIMEOUT; |
|
3283 |
|
3284 assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
|
3285 |
|
3286 if (tp->phy_reset_pending(tp)) { |
|
3287 /* |
|
3288 * A busy loop could burn quite a few cycles on nowadays CPU. |
|
3289 * Let's delay the execution of the timer for a few ticks. |
|
3290 */ |
|
3291 timeout = HZ/10; |
|
3292 goto out_mod_timer; |
|
3293 } |
|
3294 |
|
3295 if (tp->link_ok(ioaddr)) |
|
3296 return; |
|
3297 |
|
3298 netif_warn(tp, link, tp->dev, "PHY reset until link up\n"); |
|
3299 |
|
3300 tp->phy_reset_enable(tp); |
|
3301 |
|
3302 out_mod_timer: |
|
3303 mod_timer(timer, jiffies + timeout); |
|
3304 } |
|
3305 |
|
3306 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) |
|
3307 { |
|
3308 if (!test_and_set_bit(flag, tp->wk.flags)) |
|
3309 schedule_work(&tp->wk.work); |
|
3310 } |
|
3311 |
|
3312 static void rtl8169_phy_timer(unsigned long __opaque) |
|
3313 { |
|
3314 struct net_device *dev = (struct net_device *)__opaque; |
|
3315 struct rtl8169_private *tp = netdev_priv(dev); |
|
3316 |
|
3317 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
|
3318 } |
|
3319 |
|
3320 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
|
3321 void __iomem *ioaddr) |
|
3322 { |
|
3323 iounmap(ioaddr); |
|
3324 pci_release_regions(pdev); |
|
3325 pci_clear_mwi(pdev); |
|
3326 pci_disable_device(pdev); |
|
3327 free_netdev(dev); |
|
3328 } |
|
3329 |
|
3330 static void rtl8169_phy_reset(struct net_device *dev, |
|
3331 struct rtl8169_private *tp) |
|
3332 { |
|
3333 unsigned int i; |
|
3334 |
|
3335 tp->phy_reset_enable(tp); |
|
3336 for (i = 0; i < 100; i++) { |
|
3337 if (!tp->phy_reset_pending(tp)) |
|
3338 return; |
|
3339 msleep(1); |
|
3340 } |
|
3341 netif_err(tp, link, dev, "PHY reset failed\n"); |
|
3342 } |
|
3343 |
|
3344 static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
|
3345 { |
|
3346 void __iomem *ioaddr = tp->mmio_addr; |
|
3347 |
|
3348 return (tp->mac_version == RTL_GIGA_MAC_VER_01) && |
|
3349 (RTL_R8(PHYstatus) & TBI_Enable); |
|
3350 } |
|
3351 |
|
3352 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
|
3353 { |
|
3354 void __iomem *ioaddr = tp->mmio_addr; |
|
3355 |
|
3356 rtl_hw_phy_config(dev); |
|
3357 |
|
3358 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
|
3359 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3360 RTL_W8(0x82, 0x01); |
|
3361 } |
|
3362 |
|
3363 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
|
3364 |
|
3365 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
3366 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
|
3367 |
|
3368 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
|
3369 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
|
3370 RTL_W8(0x82, 0x01); |
|
3371 dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
3372 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
|
3373 } |
|
3374 |
|
3375 rtl8169_phy_reset(dev, tp); |
|
3376 |
|
3377 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
|
3378 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
|
3379 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | |
|
3380 (tp->mii.supports_gmii ? |
|
3381 ADVERTISED_1000baseT_Half | |
|
3382 ADVERTISED_1000baseT_Full : 0)); |
|
3383 |
|
3384 if (rtl_tbi_enabled(tp)) |
|
3385 netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
|
3386 } |
|
3387 |
|
3388 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
|
3389 { |
|
3390 void __iomem *ioaddr = tp->mmio_addr; |
|
3391 u32 high; |
|
3392 u32 low; |
|
3393 |
|
3394 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); |
|
3395 high = addr[4] | (addr[5] << 8); |
|
3396 |
|
3397 rtl_lock_work(tp); |
|
3398 |
|
3399 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3400 |
|
3401 RTL_W32(MAC4, high); |
|
3402 RTL_R32(MAC4); |
|
3403 |
|
3404 RTL_W32(MAC0, low); |
|
3405 RTL_R32(MAC0); |
|
3406 |
|
3407 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
|
3408 const struct exgmac_reg e[] = { |
|
3409 { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, |
|
3410 { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, |
|
3411 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, |
|
3412 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | |
|
3413 low >> 16 }, |
|
3414 }; |
|
3415 |
|
3416 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); |
|
3417 } |
|
3418 |
|
3419 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3420 |
|
3421 rtl_unlock_work(tp); |
|
3422 } |
|
3423 |
|
3424 static int rtl_set_mac_address(struct net_device *dev, void *p) |
|
3425 { |
|
3426 struct rtl8169_private *tp = netdev_priv(dev); |
|
3427 struct sockaddr *addr = p; |
|
3428 |
|
3429 if (!is_valid_ether_addr(addr->sa_data)) |
|
3430 return -EADDRNOTAVAIL; |
|
3431 |
|
3432 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
|
3433 |
|
3434 rtl_rar_set(tp, dev->dev_addr); |
|
3435 |
|
3436 return 0; |
|
3437 } |
|
3438 |
|
3439 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
|
3440 { |
|
3441 struct rtl8169_private *tp = netdev_priv(dev); |
|
3442 struct mii_ioctl_data *data = if_mii(ifr); |
|
3443 |
|
3444 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
|
3445 } |
|
3446 |
|
3447 static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
|
3448 struct mii_ioctl_data *data, int cmd) |
|
3449 { |
|
3450 switch (cmd) { |
|
3451 case SIOCGMIIPHY: |
|
3452 data->phy_id = 32; /* Internal PHY */ |
|
3453 return 0; |
|
3454 |
|
3455 case SIOCGMIIREG: |
|
3456 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
|
3457 return 0; |
|
3458 |
|
3459 case SIOCSMIIREG: |
|
3460 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
|
3461 return 0; |
|
3462 } |
|
3463 return -EOPNOTSUPP; |
|
3464 } |
|
3465 |
|
3466 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
|
3467 { |
|
3468 return -EOPNOTSUPP; |
|
3469 } |
|
3470 |
|
3471 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
|
3472 { |
|
3473 if (tp->features & RTL_FEATURE_MSI) { |
|
3474 pci_disable_msi(pdev); |
|
3475 tp->features &= ~RTL_FEATURE_MSI; |
|
3476 } |
|
3477 } |
|
3478 |
|
3479 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
|
3480 { |
|
3481 struct mdio_ops *ops = &tp->mdio_ops; |
|
3482 |
|
3483 switch (tp->mac_version) { |
|
3484 case RTL_GIGA_MAC_VER_27: |
|
3485 ops->write = r8168dp_1_mdio_write; |
|
3486 ops->read = r8168dp_1_mdio_read; |
|
3487 break; |
|
3488 case RTL_GIGA_MAC_VER_28: |
|
3489 case RTL_GIGA_MAC_VER_31: |
|
3490 ops->write = r8168dp_2_mdio_write; |
|
3491 ops->read = r8168dp_2_mdio_read; |
|
3492 break; |
|
3493 default: |
|
3494 ops->write = r8169_mdio_write; |
|
3495 ops->read = r8169_mdio_read; |
|
3496 break; |
|
3497 } |
|
3498 } |
|
3499 |
|
3500 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
|
3501 { |
|
3502 void __iomem *ioaddr = tp->mmio_addr; |
|
3503 |
|
3504 switch (tp->mac_version) { |
|
3505 case RTL_GIGA_MAC_VER_25: |
|
3506 case RTL_GIGA_MAC_VER_26: |
|
3507 case RTL_GIGA_MAC_VER_29: |
|
3508 case RTL_GIGA_MAC_VER_30: |
|
3509 case RTL_GIGA_MAC_VER_32: |
|
3510 case RTL_GIGA_MAC_VER_33: |
|
3511 case RTL_GIGA_MAC_VER_34: |
|
3512 RTL_W32(RxConfig, RTL_R32(RxConfig) | |
|
3513 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
|
3514 break; |
|
3515 default: |
|
3516 break; |
|
3517 } |
|
3518 } |
|
3519 |
|
3520 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) |
|
3521 { |
|
3522 if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) |
|
3523 return false; |
|
3524 |
|
3525 rtl_writephy(tp, 0x1f, 0x0000); |
|
3526 rtl_writephy(tp, MII_BMCR, 0x0000); |
|
3527 |
|
3528 rtl_wol_suspend_quirk(tp); |
|
3529 |
|
3530 return true; |
|
3531 } |
|
3532 |
|
3533 static void r810x_phy_power_down(struct rtl8169_private *tp) |
|
3534 { |
|
3535 rtl_writephy(tp, 0x1f, 0x0000); |
|
3536 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3537 } |
|
3538 |
|
3539 static void r810x_phy_power_up(struct rtl8169_private *tp) |
|
3540 { |
|
3541 rtl_writephy(tp, 0x1f, 0x0000); |
|
3542 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3543 } |
|
3544 |
|
3545 static void r810x_pll_power_down(struct rtl8169_private *tp) |
|
3546 { |
|
3547 if (rtl_wol_pll_power_down(tp)) |
|
3548 return; |
|
3549 |
|
3550 r810x_phy_power_down(tp); |
|
3551 } |
|
3552 |
|
3553 static void r810x_pll_power_up(struct rtl8169_private *tp) |
|
3554 { |
|
3555 r810x_phy_power_up(tp); |
|
3556 } |
|
3557 |
|
3558 static void r8168_phy_power_up(struct rtl8169_private *tp) |
|
3559 { |
|
3560 rtl_writephy(tp, 0x1f, 0x0000); |
|
3561 switch (tp->mac_version) { |
|
3562 case RTL_GIGA_MAC_VER_11: |
|
3563 case RTL_GIGA_MAC_VER_12: |
|
3564 case RTL_GIGA_MAC_VER_17: |
|
3565 case RTL_GIGA_MAC_VER_18: |
|
3566 case RTL_GIGA_MAC_VER_19: |
|
3567 case RTL_GIGA_MAC_VER_20: |
|
3568 case RTL_GIGA_MAC_VER_21: |
|
3569 case RTL_GIGA_MAC_VER_22: |
|
3570 case RTL_GIGA_MAC_VER_23: |
|
3571 case RTL_GIGA_MAC_VER_24: |
|
3572 case RTL_GIGA_MAC_VER_25: |
|
3573 case RTL_GIGA_MAC_VER_26: |
|
3574 case RTL_GIGA_MAC_VER_27: |
|
3575 case RTL_GIGA_MAC_VER_28: |
|
3576 case RTL_GIGA_MAC_VER_31: |
|
3577 rtl_writephy(tp, 0x0e, 0x0000); |
|
3578 break; |
|
3579 default: |
|
3580 break; |
|
3581 } |
|
3582 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
|
3583 } |
|
3584 |
|
3585 static void r8168_phy_power_down(struct rtl8169_private *tp) |
|
3586 { |
|
3587 rtl_writephy(tp, 0x1f, 0x0000); |
|
3588 switch (tp->mac_version) { |
|
3589 case RTL_GIGA_MAC_VER_32: |
|
3590 case RTL_GIGA_MAC_VER_33: |
|
3591 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
|
3592 break; |
|
3593 |
|
3594 case RTL_GIGA_MAC_VER_11: |
|
3595 case RTL_GIGA_MAC_VER_12: |
|
3596 case RTL_GIGA_MAC_VER_17: |
|
3597 case RTL_GIGA_MAC_VER_18: |
|
3598 case RTL_GIGA_MAC_VER_19: |
|
3599 case RTL_GIGA_MAC_VER_20: |
|
3600 case RTL_GIGA_MAC_VER_21: |
|
3601 case RTL_GIGA_MAC_VER_22: |
|
3602 case RTL_GIGA_MAC_VER_23: |
|
3603 case RTL_GIGA_MAC_VER_24: |
|
3604 case RTL_GIGA_MAC_VER_25: |
|
3605 case RTL_GIGA_MAC_VER_26: |
|
3606 case RTL_GIGA_MAC_VER_27: |
|
3607 case RTL_GIGA_MAC_VER_28: |
|
3608 case RTL_GIGA_MAC_VER_31: |
|
3609 rtl_writephy(tp, 0x0e, 0x0200); |
|
3610 default: |
|
3611 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); |
|
3612 break; |
|
3613 } |
|
3614 } |
|
3615 |
|
3616 static void r8168_pll_power_down(struct rtl8169_private *tp) |
|
3617 { |
|
3618 void __iomem *ioaddr = tp->mmio_addr; |
|
3619 |
|
3620 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3621 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3622 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3623 r8168dp_check_dash(tp)) { |
|
3624 return; |
|
3625 } |
|
3626 |
|
3627 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
|
3628 tp->mac_version == RTL_GIGA_MAC_VER_24) && |
|
3629 (RTL_R16(CPlusCmd) & ASF)) { |
|
3630 return; |
|
3631 } |
|
3632 |
|
3633 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
|
3634 tp->mac_version == RTL_GIGA_MAC_VER_33) |
|
3635 rtl_ephy_write(ioaddr, 0x19, 0xff64); |
|
3636 |
|
3637 if (rtl_wol_pll_power_down(tp)) |
|
3638 return; |
|
3639 |
|
3640 r8168_phy_power_down(tp); |
|
3641 |
|
3642 switch (tp->mac_version) { |
|
3643 case RTL_GIGA_MAC_VER_25: |
|
3644 case RTL_GIGA_MAC_VER_26: |
|
3645 case RTL_GIGA_MAC_VER_27: |
|
3646 case RTL_GIGA_MAC_VER_28: |
|
3647 case RTL_GIGA_MAC_VER_31: |
|
3648 case RTL_GIGA_MAC_VER_32: |
|
3649 case RTL_GIGA_MAC_VER_33: |
|
3650 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
|
3651 break; |
|
3652 } |
|
3653 } |
|
3654 |
|
3655 static void r8168_pll_power_up(struct rtl8169_private *tp) |
|
3656 { |
|
3657 void __iomem *ioaddr = tp->mmio_addr; |
|
3658 |
|
3659 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
3660 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
3661 tp->mac_version == RTL_GIGA_MAC_VER_31) && |
|
3662 r8168dp_check_dash(tp)) { |
|
3663 return; |
|
3664 } |
|
3665 |
|
3666 switch (tp->mac_version) { |
|
3667 case RTL_GIGA_MAC_VER_25: |
|
3668 case RTL_GIGA_MAC_VER_26: |
|
3669 case RTL_GIGA_MAC_VER_27: |
|
3670 case RTL_GIGA_MAC_VER_28: |
|
3671 case RTL_GIGA_MAC_VER_31: |
|
3672 case RTL_GIGA_MAC_VER_32: |
|
3673 case RTL_GIGA_MAC_VER_33: |
|
3674 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
|
3675 break; |
|
3676 } |
|
3677 |
|
3678 r8168_phy_power_up(tp); |
|
3679 } |
|
3680 |
|
3681 static void rtl_generic_op(struct rtl8169_private *tp, |
|
3682 void (*op)(struct rtl8169_private *)) |
|
3683 { |
|
3684 if (op) |
|
3685 op(tp); |
|
3686 } |
|
3687 |
|
3688 static void rtl_pll_power_down(struct rtl8169_private *tp) |
|
3689 { |
|
3690 rtl_generic_op(tp, tp->pll_power_ops.down); |
|
3691 } |
|
3692 |
|
3693 static void rtl_pll_power_up(struct rtl8169_private *tp) |
|
3694 { |
|
3695 rtl_generic_op(tp, tp->pll_power_ops.up); |
|
3696 } |
|
3697 |
|
3698 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) |
|
3699 { |
|
3700 struct pll_power_ops *ops = &tp->pll_power_ops; |
|
3701 |
|
3702 switch (tp->mac_version) { |
|
3703 case RTL_GIGA_MAC_VER_07: |
|
3704 case RTL_GIGA_MAC_VER_08: |
|
3705 case RTL_GIGA_MAC_VER_09: |
|
3706 case RTL_GIGA_MAC_VER_10: |
|
3707 case RTL_GIGA_MAC_VER_16: |
|
3708 case RTL_GIGA_MAC_VER_29: |
|
3709 case RTL_GIGA_MAC_VER_30: |
|
3710 ops->down = r810x_pll_power_down; |
|
3711 ops->up = r810x_pll_power_up; |
|
3712 break; |
|
3713 |
|
3714 case RTL_GIGA_MAC_VER_11: |
|
3715 case RTL_GIGA_MAC_VER_12: |
|
3716 case RTL_GIGA_MAC_VER_17: |
|
3717 case RTL_GIGA_MAC_VER_18: |
|
3718 case RTL_GIGA_MAC_VER_19: |
|
3719 case RTL_GIGA_MAC_VER_20: |
|
3720 case RTL_GIGA_MAC_VER_21: |
|
3721 case RTL_GIGA_MAC_VER_22: |
|
3722 case RTL_GIGA_MAC_VER_23: |
|
3723 case RTL_GIGA_MAC_VER_24: |
|
3724 case RTL_GIGA_MAC_VER_25: |
|
3725 case RTL_GIGA_MAC_VER_26: |
|
3726 case RTL_GIGA_MAC_VER_27: |
|
3727 case RTL_GIGA_MAC_VER_28: |
|
3728 case RTL_GIGA_MAC_VER_31: |
|
3729 case RTL_GIGA_MAC_VER_32: |
|
3730 case RTL_GIGA_MAC_VER_33: |
|
3731 case RTL_GIGA_MAC_VER_34: |
|
3732 case RTL_GIGA_MAC_VER_35: |
|
3733 case RTL_GIGA_MAC_VER_36: |
|
3734 ops->down = r8168_pll_power_down; |
|
3735 ops->up = r8168_pll_power_up; |
|
3736 break; |
|
3737 |
|
3738 default: |
|
3739 ops->down = NULL; |
|
3740 ops->up = NULL; |
|
3741 break; |
|
3742 } |
|
3743 } |
|
3744 |
|
3745 static void rtl_init_rxcfg(struct rtl8169_private *tp) |
|
3746 { |
|
3747 void __iomem *ioaddr = tp->mmio_addr; |
|
3748 |
|
3749 switch (tp->mac_version) { |
|
3750 case RTL_GIGA_MAC_VER_01: |
|
3751 case RTL_GIGA_MAC_VER_02: |
|
3752 case RTL_GIGA_MAC_VER_03: |
|
3753 case RTL_GIGA_MAC_VER_04: |
|
3754 case RTL_GIGA_MAC_VER_05: |
|
3755 case RTL_GIGA_MAC_VER_06: |
|
3756 case RTL_GIGA_MAC_VER_10: |
|
3757 case RTL_GIGA_MAC_VER_11: |
|
3758 case RTL_GIGA_MAC_VER_12: |
|
3759 case RTL_GIGA_MAC_VER_13: |
|
3760 case RTL_GIGA_MAC_VER_14: |
|
3761 case RTL_GIGA_MAC_VER_15: |
|
3762 case RTL_GIGA_MAC_VER_16: |
|
3763 case RTL_GIGA_MAC_VER_17: |
|
3764 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
|
3765 break; |
|
3766 case RTL_GIGA_MAC_VER_18: |
|
3767 case RTL_GIGA_MAC_VER_19: |
|
3768 case RTL_GIGA_MAC_VER_20: |
|
3769 case RTL_GIGA_MAC_VER_21: |
|
3770 case RTL_GIGA_MAC_VER_22: |
|
3771 case RTL_GIGA_MAC_VER_23: |
|
3772 case RTL_GIGA_MAC_VER_24: |
|
3773 case RTL_GIGA_MAC_VER_34: |
|
3774 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
|
3775 break; |
|
3776 default: |
|
3777 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); |
|
3778 break; |
|
3779 } |
|
3780 } |
|
3781 |
|
3782 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
|
3783 { |
|
3784 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; |
|
3785 } |
|
3786 |
|
3787 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3788 { |
|
3789 void __iomem *ioaddr = tp->mmio_addr; |
|
3790 |
|
3791 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3792 rtl_generic_op(tp, tp->jumbo_ops.enable); |
|
3793 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3794 } |
|
3795 |
|
3796 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3797 { |
|
3798 void __iomem *ioaddr = tp->mmio_addr; |
|
3799 |
|
3800 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
3801 rtl_generic_op(tp, tp->jumbo_ops.disable); |
|
3802 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
3803 } |
|
3804 |
|
3805 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3806 { |
|
3807 void __iomem *ioaddr = tp->mmio_addr; |
|
3808 |
|
3809 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3810 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); |
|
3811 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
3812 } |
|
3813 |
|
3814 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3815 { |
|
3816 void __iomem *ioaddr = tp->mmio_addr; |
|
3817 |
|
3818 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3819 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); |
|
3820 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3821 } |
|
3822 |
|
3823 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3824 { |
|
3825 void __iomem *ioaddr = tp->mmio_addr; |
|
3826 |
|
3827 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3828 } |
|
3829 |
|
3830 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3831 { |
|
3832 void __iomem *ioaddr = tp->mmio_addr; |
|
3833 |
|
3834 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3835 } |
|
3836 |
|
3837 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3838 { |
|
3839 void __iomem *ioaddr = tp->mmio_addr; |
|
3840 |
|
3841 RTL_W8(MaxTxPacketSize, 0x3f); |
|
3842 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); |
|
3843 RTL_W8(Config4, RTL_R8(Config4) | 0x01); |
|
3844 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
|
3845 } |
|
3846 |
|
3847 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3848 { |
|
3849 void __iomem *ioaddr = tp->mmio_addr; |
|
3850 |
|
3851 RTL_W8(MaxTxPacketSize, 0x0c); |
|
3852 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); |
|
3853 RTL_W8(Config4, RTL_R8(Config4) & ~0x01); |
|
3854 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
3855 } |
|
3856 |
|
3857 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3858 { |
|
3859 rtl_tx_performance_tweak(tp->pci_dev, |
|
3860 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3861 } |
|
3862 |
|
3863 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3864 { |
|
3865 rtl_tx_performance_tweak(tp->pci_dev, |
|
3866 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
3867 } |
|
3868 |
|
3869 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) |
|
3870 { |
|
3871 void __iomem *ioaddr = tp->mmio_addr; |
|
3872 |
|
3873 r8168b_0_hw_jumbo_enable(tp); |
|
3874 |
|
3875 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); |
|
3876 } |
|
3877 |
|
3878 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) |
|
3879 { |
|
3880 void __iomem *ioaddr = tp->mmio_addr; |
|
3881 |
|
3882 r8168b_0_hw_jumbo_disable(tp); |
|
3883 |
|
3884 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
3885 } |
|
3886 |
|
3887 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp) |
|
3888 { |
|
3889 struct jumbo_ops *ops = &tp->jumbo_ops; |
|
3890 |
|
3891 switch (tp->mac_version) { |
|
3892 case RTL_GIGA_MAC_VER_11: |
|
3893 ops->disable = r8168b_0_hw_jumbo_disable; |
|
3894 ops->enable = r8168b_0_hw_jumbo_enable; |
|
3895 break; |
|
3896 case RTL_GIGA_MAC_VER_12: |
|
3897 case RTL_GIGA_MAC_VER_17: |
|
3898 ops->disable = r8168b_1_hw_jumbo_disable; |
|
3899 ops->enable = r8168b_1_hw_jumbo_enable; |
|
3900 break; |
|
3901 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ |
|
3902 case RTL_GIGA_MAC_VER_19: |
|
3903 case RTL_GIGA_MAC_VER_20: |
|
3904 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ |
|
3905 case RTL_GIGA_MAC_VER_22: |
|
3906 case RTL_GIGA_MAC_VER_23: |
|
3907 case RTL_GIGA_MAC_VER_24: |
|
3908 case RTL_GIGA_MAC_VER_25: |
|
3909 case RTL_GIGA_MAC_VER_26: |
|
3910 ops->disable = r8168c_hw_jumbo_disable; |
|
3911 ops->enable = r8168c_hw_jumbo_enable; |
|
3912 break; |
|
3913 case RTL_GIGA_MAC_VER_27: |
|
3914 case RTL_GIGA_MAC_VER_28: |
|
3915 ops->disable = r8168dp_hw_jumbo_disable; |
|
3916 ops->enable = r8168dp_hw_jumbo_enable; |
|
3917 break; |
|
3918 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ |
|
3919 case RTL_GIGA_MAC_VER_32: |
|
3920 case RTL_GIGA_MAC_VER_33: |
|
3921 case RTL_GIGA_MAC_VER_34: |
|
3922 ops->disable = r8168e_hw_jumbo_disable; |
|
3923 ops->enable = r8168e_hw_jumbo_enable; |
|
3924 break; |
|
3925 |
|
3926 /* |
|
3927 * No action needed for jumbo frames with 8169. |
|
3928 * No jumbo for 810x at all. |
|
3929 */ |
|
3930 default: |
|
3931 ops->disable = NULL; |
|
3932 ops->enable = NULL; |
|
3933 break; |
|
3934 } |
|
3935 } |
|
3936 |
|
3937 static void rtl_hw_reset(struct rtl8169_private *tp) |
|
3938 { |
|
3939 void __iomem *ioaddr = tp->mmio_addr; |
|
3940 int i; |
|
3941 |
|
3942 /* Soft reset the chip. */ |
|
3943 RTL_W8(ChipCmd, CmdReset); |
|
3944 |
|
3945 /* Check that the chip has finished the reset. */ |
|
3946 for (i = 0; i < 100; i++) { |
|
3947 if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
|
3948 break; |
|
3949 udelay(100); |
|
3950 } |
|
3951 } |
|
3952 |
|
3953 static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
|
3954 { |
|
3955 struct rtl_fw *rtl_fw; |
|
3956 const char *name; |
|
3957 int rc = -ENOMEM; |
|
3958 |
|
3959 name = rtl_lookup_firmware_name(tp); |
|
3960 if (!name) |
|
3961 goto out_no_firmware; |
|
3962 |
|
3963 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
|
3964 if (!rtl_fw) |
|
3965 goto err_warn; |
|
3966 |
|
3967 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
|
3968 if (rc < 0) |
|
3969 goto err_free; |
|
3970 |
|
3971 rc = rtl_check_firmware(tp, rtl_fw); |
|
3972 if (rc < 0) |
|
3973 goto err_release_firmware; |
|
3974 |
|
3975 tp->rtl_fw = rtl_fw; |
|
3976 out: |
|
3977 return; |
|
3978 |
|
3979 err_release_firmware: |
|
3980 release_firmware(rtl_fw->fw); |
|
3981 err_free: |
|
3982 kfree(rtl_fw); |
|
3983 err_warn: |
|
3984 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", |
|
3985 name, rc); |
|
3986 out_no_firmware: |
|
3987 tp->rtl_fw = NULL; |
|
3988 goto out; |
|
3989 } |
|
3990 |
|
3991 static void rtl_request_firmware(struct rtl8169_private *tp) |
|
3992 { |
|
3993 if (IS_ERR(tp->rtl_fw)) |
|
3994 rtl_request_uncached_firmware(tp); |
|
3995 } |
|
3996 |
|
3997 static void rtl_rx_close(struct rtl8169_private *tp) |
|
3998 { |
|
3999 void __iomem *ioaddr = tp->mmio_addr; |
|
4000 |
|
4001 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
|
4002 } |
|
4003 |
|
4004 static void rtl8169_hw_reset(struct rtl8169_private *tp) |
|
4005 { |
|
4006 void __iomem *ioaddr = tp->mmio_addr; |
|
4007 |
|
4008 /* Disable interrupts */ |
|
4009 rtl8169_irq_mask_and_ack(tp); |
|
4010 |
|
4011 rtl_rx_close(tp); |
|
4012 |
|
4013 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
4014 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
4015 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
4016 while (RTL_R8(TxPoll) & NPQ) |
|
4017 udelay(20); |
|
4018 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
|
4019 tp->mac_version == RTL_GIGA_MAC_VER_35 || |
|
4020 tp->mac_version == RTL_GIGA_MAC_VER_36) { |
|
4021 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4022 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
|
4023 udelay(100); |
|
4024 } else { |
|
4025 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
|
4026 udelay(100); |
|
4027 } |
|
4028 |
|
4029 rtl_hw_reset(tp); |
|
4030 } |
|
4031 |
|
4032 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
|
4033 { |
|
4034 void __iomem *ioaddr = tp->mmio_addr; |
|
4035 |
|
4036 /* Set DMA burst size and Interframe Gap Time */ |
|
4037 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4038 (InterFrameGap << TxInterFrameGapShift)); |
|
4039 } |
|
4040 |
|
4041 static void rtl_hw_start(struct net_device *dev) |
|
4042 { |
|
4043 struct rtl8169_private *tp = netdev_priv(dev); |
|
4044 |
|
4045 tp->hw_start(dev); |
|
4046 |
|
4047 if (!tp->ecdev) { |
|
4048 rtl_irq_enable_all(tp); |
|
4049 } |
|
4050 } |
|
4051 |
|
4052 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
|
4053 void __iomem *ioaddr) |
|
4054 { |
|
4055 /* |
|
4056 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh |
|
4057 * register to be written before TxDescAddrLow to work. |
|
4058 * Switching from MMIO to I/O access fixes the issue as well. |
|
4059 */ |
|
4060 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
|
4061 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
|
4062 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
|
4063 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
|
4064 } |
|
4065 |
|
4066 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) |
|
4067 { |
|
4068 u16 cmd; |
|
4069 |
|
4070 cmd = RTL_R16(CPlusCmd); |
|
4071 RTL_W16(CPlusCmd, cmd); |
|
4072 return cmd; |
|
4073 } |
|
4074 |
|
4075 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
|
4076 { |
|
4077 /* Low hurts. Let's disable the filtering. */ |
|
4078 RTL_W16(RxMaxSize, rx_buf_sz + 1); |
|
4079 } |
|
4080 |
|
4081 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
|
4082 { |
|
4083 static const struct rtl_cfg2_info { |
|
4084 u32 mac_version; |
|
4085 u32 clk; |
|
4086 u32 val; |
|
4087 } cfg2_info [] = { |
|
4088 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd |
|
4089 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, |
|
4090 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe |
|
4091 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } |
|
4092 }; |
|
4093 const struct rtl_cfg2_info *p = cfg2_info; |
|
4094 unsigned int i; |
|
4095 u32 clk; |
|
4096 |
|
4097 clk = RTL_R8(Config2) & PCI_Clock_66MHz; |
|
4098 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
|
4099 if ((p->mac_version == mac_version) && (p->clk == clk)) { |
|
4100 RTL_W32(0x7c, p->val); |
|
4101 break; |
|
4102 } |
|
4103 } |
|
4104 } |
|
4105 |
|
4106 static void rtl_set_rx_mode(struct net_device *dev) |
|
4107 { |
|
4108 struct rtl8169_private *tp = netdev_priv(dev); |
|
4109 void __iomem *ioaddr = tp->mmio_addr; |
|
4110 u32 mc_filter[2]; /* Multicast hash filter */ |
|
4111 int rx_mode; |
|
4112 u32 tmp = 0; |
|
4113 |
|
4114 if (dev->flags & IFF_PROMISC) { |
|
4115 /* Unconditionally log net taps. */ |
|
4116 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
|
4117 rx_mode = |
|
4118 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | |
|
4119 AcceptAllPhys; |
|
4120 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4121 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
|
4122 (dev->flags & IFF_ALLMULTI)) { |
|
4123 /* Too many to filter perfectly -- accept all multicasts. */ |
|
4124 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; |
|
4125 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4126 } else { |
|
4127 struct netdev_hw_addr *ha; |
|
4128 |
|
4129 rx_mode = AcceptBroadcast | AcceptMyPhys; |
|
4130 mc_filter[1] = mc_filter[0] = 0; |
|
4131 netdev_for_each_mc_addr(ha, dev) { |
|
4132 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; |
|
4133 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
|
4134 rx_mode |= AcceptMulticast; |
|
4135 } |
|
4136 } |
|
4137 |
|
4138 if (dev->features & NETIF_F_RXALL) |
|
4139 rx_mode |= (AcceptErr | AcceptRunt); |
|
4140 |
|
4141 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
|
4142 |
|
4143 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
|
4144 u32 data = mc_filter[0]; |
|
4145 |
|
4146 mc_filter[0] = swab32(mc_filter[1]); |
|
4147 mc_filter[1] = swab32(data); |
|
4148 } |
|
4149 |
|
4150 if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
|
4151 mc_filter[1] = mc_filter[0] = 0xffffffff; |
|
4152 |
|
4153 RTL_W32(MAR0 + 4, mc_filter[1]); |
|
4154 RTL_W32(MAR0 + 0, mc_filter[0]); |
|
4155 |
|
4156 RTL_W32(RxConfig, tmp); |
|
4157 } |
|
4158 |
|
4159 static void rtl_hw_start_8169(struct net_device *dev) |
|
4160 { |
|
4161 struct rtl8169_private *tp = netdev_priv(dev); |
|
4162 void __iomem *ioaddr = tp->mmio_addr; |
|
4163 struct pci_dev *pdev = tp->pci_dev; |
|
4164 |
|
4165 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
|
4166 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); |
|
4167 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); |
|
4168 } |
|
4169 |
|
4170 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4171 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4172 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4173 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4174 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4175 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4176 |
|
4177 rtl_init_rxcfg(tp); |
|
4178 |
|
4179 RTL_W8(EarlyTxThres, NoEarlyTx); |
|
4180 |
|
4181 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4182 |
|
4183 if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
|
4184 tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4185 tp->mac_version == RTL_GIGA_MAC_VER_03 || |
|
4186 tp->mac_version == RTL_GIGA_MAC_VER_04) |
|
4187 rtl_set_rx_tx_config_registers(tp); |
|
4188 |
|
4189 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
|
4190 |
|
4191 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
|
4192 tp->mac_version == RTL_GIGA_MAC_VER_03) { |
|
4193 dprintk("Set MAC Reg C+CR Offset 0xE0. " |
|
4194 "Bit-3 and bit-14 MUST be 1\n"); |
|
4195 tp->cp_cmd |= (1 << 14); |
|
4196 } |
|
4197 |
|
4198 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4199 |
|
4200 rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
|
4201 |
|
4202 /* |
|
4203 * Undocumented corner. Supposedly: |
|
4204 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
4205 */ |
|
4206 RTL_W16(IntrMitigate, 0x0000); |
|
4207 |
|
4208 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4209 |
|
4210 if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
|
4211 tp->mac_version != RTL_GIGA_MAC_VER_02 && |
|
4212 tp->mac_version != RTL_GIGA_MAC_VER_03 && |
|
4213 tp->mac_version != RTL_GIGA_MAC_VER_04) { |
|
4214 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4215 rtl_set_rx_tx_config_registers(tp); |
|
4216 } |
|
4217 |
|
4218 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4219 |
|
4220 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ |
|
4221 RTL_R8(IntrMask); |
|
4222 |
|
4223 RTL_W32(RxMissed, 0); |
|
4224 |
|
4225 rtl_set_rx_mode(dev); |
|
4226 |
|
4227 /* no early-rx interrupts */ |
|
4228 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4229 } |
|
4230 |
|
4231 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
|
4232 { |
|
4233 u32 csi; |
|
4234 |
|
4235 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; |
|
4236 rtl_csi_write(ioaddr, 0x070c, csi | bits); |
|
4237 } |
|
4238 |
|
4239 static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
|
4240 { |
|
4241 rtl_csi_access_enable(ioaddr, 0x17000000); |
|
4242 } |
|
4243 |
|
4244 static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
|
4245 { |
|
4246 rtl_csi_access_enable(ioaddr, 0x27000000); |
|
4247 } |
|
4248 |
|
4249 struct ephy_info { |
|
4250 unsigned int offset; |
|
4251 u16 mask; |
|
4252 u16 bits; |
|
4253 }; |
|
4254 |
|
4255 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
|
4256 { |
|
4257 u16 w; |
|
4258 |
|
4259 while (len-- > 0) { |
|
4260 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; |
|
4261 rtl_ephy_write(ioaddr, e->offset, w); |
|
4262 e++; |
|
4263 } |
|
4264 } |
|
4265 |
|
4266 static void rtl_disable_clock_request(struct pci_dev *pdev) |
|
4267 { |
|
4268 int cap = pci_pcie_cap(pdev); |
|
4269 |
|
4270 if (cap) { |
|
4271 u16 ctl; |
|
4272 |
|
4273 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4274 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4275 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4276 } |
|
4277 } |
|
4278 |
|
4279 static void rtl_enable_clock_request(struct pci_dev *pdev) |
|
4280 { |
|
4281 int cap = pci_pcie_cap(pdev); |
|
4282 |
|
4283 if (cap) { |
|
4284 u16 ctl; |
|
4285 |
|
4286 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); |
|
4287 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; |
|
4288 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); |
|
4289 } |
|
4290 } |
|
4291 |
|
4292 #define R8168_CPCMD_QUIRK_MASK (\ |
|
4293 EnableBist | \ |
|
4294 Mac_dbgo_oe | \ |
|
4295 Force_half_dup | \ |
|
4296 Force_rxflow_en | \ |
|
4297 Force_txflow_en | \ |
|
4298 Cxpl_dbg_sel | \ |
|
4299 ASF | \ |
|
4300 PktCntrDisable | \ |
|
4301 Mac_dbgo_sel) |
|
4302 |
|
4303 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4304 { |
|
4305 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4306 |
|
4307 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4308 |
|
4309 rtl_tx_performance_tweak(pdev, |
|
4310 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4311 } |
|
4312 |
|
4313 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4314 { |
|
4315 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4316 |
|
4317 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4318 |
|
4319 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); |
|
4320 } |
|
4321 |
|
4322 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4323 { |
|
4324 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
|
4325 |
|
4326 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4327 |
|
4328 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4329 |
|
4330 rtl_disable_clock_request(pdev); |
|
4331 |
|
4332 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4333 } |
|
4334 |
|
4335 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4336 { |
|
4337 static const struct ephy_info e_info_8168cp[] = { |
|
4338 { 0x01, 0, 0x0001 }, |
|
4339 { 0x02, 0x0800, 0x1000 }, |
|
4340 { 0x03, 0, 0x0042 }, |
|
4341 { 0x06, 0x0080, 0x0000 }, |
|
4342 { 0x07, 0, 0x2000 } |
|
4343 }; |
|
4344 |
|
4345 rtl_csi_access_enable_2(ioaddr); |
|
4346 |
|
4347 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
|
4348 |
|
4349 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4350 } |
|
4351 |
|
4352 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4353 { |
|
4354 rtl_csi_access_enable_2(ioaddr); |
|
4355 |
|
4356 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4357 |
|
4358 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4359 |
|
4360 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4361 } |
|
4362 |
|
4363 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4364 { |
|
4365 rtl_csi_access_enable_2(ioaddr); |
|
4366 |
|
4367 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4368 |
|
4369 /* Magic. */ |
|
4370 RTL_W8(DBG_REG, 0x20); |
|
4371 |
|
4372 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4373 |
|
4374 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4375 |
|
4376 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4377 } |
|
4378 |
|
4379 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4380 { |
|
4381 static const struct ephy_info e_info_8168c_1[] = { |
|
4382 { 0x02, 0x0800, 0x1000 }, |
|
4383 { 0x03, 0, 0x0002 }, |
|
4384 { 0x06, 0x0080, 0x0000 } |
|
4385 }; |
|
4386 |
|
4387 rtl_csi_access_enable_2(ioaddr); |
|
4388 |
|
4389 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
|
4390 |
|
4391 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
|
4392 |
|
4393 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4394 } |
|
4395 |
|
4396 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4397 { |
|
4398 static const struct ephy_info e_info_8168c_2[] = { |
|
4399 { 0x01, 0, 0x0001 }, |
|
4400 { 0x03, 0x0400, 0x0220 } |
|
4401 }; |
|
4402 |
|
4403 rtl_csi_access_enable_2(ioaddr); |
|
4404 |
|
4405 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
|
4406 |
|
4407 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4408 } |
|
4409 |
|
4410 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4411 { |
|
4412 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4413 } |
|
4414 |
|
4415 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4416 { |
|
4417 rtl_csi_access_enable_2(ioaddr); |
|
4418 |
|
4419 __rtl_hw_start_8168cp(ioaddr, pdev); |
|
4420 } |
|
4421 |
|
4422 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4423 { |
|
4424 rtl_csi_access_enable_2(ioaddr); |
|
4425 |
|
4426 rtl_disable_clock_request(pdev); |
|
4427 |
|
4428 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4429 |
|
4430 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4431 |
|
4432 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
|
4433 } |
|
4434 |
|
4435 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4436 { |
|
4437 rtl_csi_access_enable_1(ioaddr); |
|
4438 |
|
4439 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4440 |
|
4441 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4442 |
|
4443 rtl_disable_clock_request(pdev); |
|
4444 } |
|
4445 |
|
4446 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4447 { |
|
4448 static const struct ephy_info e_info_8168d_4[] = { |
|
4449 { 0x0b, ~0, 0x48 }, |
|
4450 { 0x19, 0x20, 0x50 }, |
|
4451 { 0x0c, ~0, 0x20 } |
|
4452 }; |
|
4453 int i; |
|
4454 |
|
4455 rtl_csi_access_enable_1(ioaddr); |
|
4456 |
|
4457 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4458 |
|
4459 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4460 |
|
4461 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { |
|
4462 const struct ephy_info *e = e_info_8168d_4 + i; |
|
4463 u16 w; |
|
4464 |
|
4465 w = rtl_ephy_read(ioaddr, e->offset); |
|
4466 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); |
|
4467 } |
|
4468 |
|
4469 rtl_enable_clock_request(pdev); |
|
4470 } |
|
4471 |
|
4472 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4473 { |
|
4474 static const struct ephy_info e_info_8168e_1[] = { |
|
4475 { 0x00, 0x0200, 0x0100 }, |
|
4476 { 0x00, 0x0000, 0x0004 }, |
|
4477 { 0x06, 0x0002, 0x0001 }, |
|
4478 { 0x06, 0x0000, 0x0030 }, |
|
4479 { 0x07, 0x0000, 0x2000 }, |
|
4480 { 0x00, 0x0000, 0x0020 }, |
|
4481 { 0x03, 0x5800, 0x2000 }, |
|
4482 { 0x03, 0x0000, 0x0001 }, |
|
4483 { 0x01, 0x0800, 0x1000 }, |
|
4484 { 0x07, 0x0000, 0x4000 }, |
|
4485 { 0x1e, 0x0000, 0x2000 }, |
|
4486 { 0x19, 0xffff, 0xfe6c }, |
|
4487 { 0x0a, 0x0000, 0x0040 } |
|
4488 }; |
|
4489 |
|
4490 rtl_csi_access_enable_2(ioaddr); |
|
4491 |
|
4492 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
|
4493 |
|
4494 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4495 |
|
4496 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4497 |
|
4498 rtl_disable_clock_request(pdev); |
|
4499 |
|
4500 /* Reset tx FIFO pointer */ |
|
4501 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
|
4502 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); |
|
4503 |
|
4504 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4505 } |
|
4506 |
|
4507 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4508 { |
|
4509 static const struct ephy_info e_info_8168e_2[] = { |
|
4510 { 0x09, 0x0000, 0x0080 }, |
|
4511 { 0x19, 0x0000, 0x0224 } |
|
4512 }; |
|
4513 |
|
4514 rtl_csi_access_enable_1(ioaddr); |
|
4515 |
|
4516 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
|
4517 |
|
4518 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4519 |
|
4520 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4521 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4522 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4523 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4524 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4525 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); |
|
4526 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4527 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4528 ERIAR_EXGMAC); |
|
4529 |
|
4530 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4531 |
|
4532 rtl_disable_clock_request(pdev); |
|
4533 |
|
4534 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4535 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4536 |
|
4537 /* Adjust EEE LED frequency */ |
|
4538 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4539 |
|
4540 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4541 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4542 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4543 } |
|
4544 |
|
4545 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4546 { |
|
4547 static const struct ephy_info e_info_8168f_1[] = { |
|
4548 { 0x06, 0x00c0, 0x0020 }, |
|
4549 { 0x08, 0x0001, 0x0002 }, |
|
4550 { 0x09, 0x0000, 0x0080 }, |
|
4551 { 0x19, 0x0000, 0x0224 } |
|
4552 }; |
|
4553 |
|
4554 rtl_csi_access_enable_1(ioaddr); |
|
4555 |
|
4556 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
|
4557 |
|
4558 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4559 |
|
4560 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4561 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
|
4562 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); |
|
4563 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); |
|
4564 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
|
4565 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); |
|
4566 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4567 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
|
4568 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
|
4569 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); |
|
4570 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, |
|
4571 ERIAR_EXGMAC); |
|
4572 |
|
4573 RTL_W8(MaxTxPacketSize, EarlySize); |
|
4574 |
|
4575 rtl_disable_clock_request(pdev); |
|
4576 |
|
4577 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
|
4578 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); |
|
4579 |
|
4580 /* Adjust EEE LED frequency */ |
|
4581 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); |
|
4582 |
|
4583 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4584 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
|
4585 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
|
4586 } |
|
4587 |
|
4588 static void rtl_hw_start_8168(struct net_device *dev) |
|
4589 { |
|
4590 struct rtl8169_private *tp = netdev_priv(dev); |
|
4591 void __iomem *ioaddr = tp->mmio_addr; |
|
4592 struct pci_dev *pdev = tp->pci_dev; |
|
4593 |
|
4594 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4595 |
|
4596 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4597 |
|
4598 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4599 |
|
4600 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
|
4601 |
|
4602 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4603 |
|
4604 RTL_W16(IntrMitigate, 0x5151); |
|
4605 |
|
4606 /* Work around for RxFIFO overflow. */ |
|
4607 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
|
4608 tp->event_slow |= RxFIFOOver | PCSTimeout; |
|
4609 tp->event_slow &= ~RxOverflow; |
|
4610 } |
|
4611 |
|
4612 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4613 |
|
4614 rtl_set_rx_mode(dev); |
|
4615 |
|
4616 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | |
|
4617 (InterFrameGap << TxInterFrameGapShift)); |
|
4618 |
|
4619 RTL_R8(IntrMask); |
|
4620 |
|
4621 switch (tp->mac_version) { |
|
4622 case RTL_GIGA_MAC_VER_11: |
|
4623 rtl_hw_start_8168bb(ioaddr, pdev); |
|
4624 break; |
|
4625 |
|
4626 case RTL_GIGA_MAC_VER_12: |
|
4627 case RTL_GIGA_MAC_VER_17: |
|
4628 rtl_hw_start_8168bef(ioaddr, pdev); |
|
4629 break; |
|
4630 |
|
4631 case RTL_GIGA_MAC_VER_18: |
|
4632 rtl_hw_start_8168cp_1(ioaddr, pdev); |
|
4633 break; |
|
4634 |
|
4635 case RTL_GIGA_MAC_VER_19: |
|
4636 rtl_hw_start_8168c_1(ioaddr, pdev); |
|
4637 break; |
|
4638 |
|
4639 case RTL_GIGA_MAC_VER_20: |
|
4640 rtl_hw_start_8168c_2(ioaddr, pdev); |
|
4641 break; |
|
4642 |
|
4643 case RTL_GIGA_MAC_VER_21: |
|
4644 rtl_hw_start_8168c_3(ioaddr, pdev); |
|
4645 break; |
|
4646 |
|
4647 case RTL_GIGA_MAC_VER_22: |
|
4648 rtl_hw_start_8168c_4(ioaddr, pdev); |
|
4649 break; |
|
4650 |
|
4651 case RTL_GIGA_MAC_VER_23: |
|
4652 rtl_hw_start_8168cp_2(ioaddr, pdev); |
|
4653 break; |
|
4654 |
|
4655 case RTL_GIGA_MAC_VER_24: |
|
4656 rtl_hw_start_8168cp_3(ioaddr, pdev); |
|
4657 break; |
|
4658 |
|
4659 case RTL_GIGA_MAC_VER_25: |
|
4660 case RTL_GIGA_MAC_VER_26: |
|
4661 case RTL_GIGA_MAC_VER_27: |
|
4662 rtl_hw_start_8168d(ioaddr, pdev); |
|
4663 break; |
|
4664 |
|
4665 case RTL_GIGA_MAC_VER_28: |
|
4666 rtl_hw_start_8168d_4(ioaddr, pdev); |
|
4667 break; |
|
4668 |
|
4669 case RTL_GIGA_MAC_VER_31: |
|
4670 rtl_hw_start_8168dp(ioaddr, pdev); |
|
4671 break; |
|
4672 |
|
4673 case RTL_GIGA_MAC_VER_32: |
|
4674 case RTL_GIGA_MAC_VER_33: |
|
4675 rtl_hw_start_8168e_1(ioaddr, pdev); |
|
4676 break; |
|
4677 case RTL_GIGA_MAC_VER_34: |
|
4678 rtl_hw_start_8168e_2(ioaddr, pdev); |
|
4679 break; |
|
4680 |
|
4681 case RTL_GIGA_MAC_VER_35: |
|
4682 case RTL_GIGA_MAC_VER_36: |
|
4683 rtl_hw_start_8168f_1(ioaddr, pdev); |
|
4684 break; |
|
4685 |
|
4686 default: |
|
4687 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
|
4688 dev->name, tp->mac_version); |
|
4689 break; |
|
4690 } |
|
4691 |
|
4692 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4693 |
|
4694 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4695 |
|
4696 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
|
4697 } |
|
4698 |
|
4699 #define R810X_CPCMD_QUIRK_MASK (\ |
|
4700 EnableBist | \ |
|
4701 Mac_dbgo_oe | \ |
|
4702 Force_half_dup | \ |
|
4703 Force_rxflow_en | \ |
|
4704 Force_txflow_en | \ |
|
4705 Cxpl_dbg_sel | \ |
|
4706 ASF | \ |
|
4707 PktCntrDisable | \ |
|
4708 Mac_dbgo_sel) |
|
4709 |
|
4710 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4711 { |
|
4712 static const struct ephy_info e_info_8102e_1[] = { |
|
4713 { 0x01, 0, 0x6e65 }, |
|
4714 { 0x02, 0, 0x091f }, |
|
4715 { 0x03, 0, 0xc2f9 }, |
|
4716 { 0x06, 0, 0xafb5 }, |
|
4717 { 0x07, 0, 0x0e00 }, |
|
4718 { 0x19, 0, 0xec80 }, |
|
4719 { 0x01, 0, 0x2e65 }, |
|
4720 { 0x01, 0, 0x6e65 } |
|
4721 }; |
|
4722 u8 cfg1; |
|
4723 |
|
4724 rtl_csi_access_enable_2(ioaddr); |
|
4725 |
|
4726 RTL_W8(DBG_REG, FIX_NAK_1); |
|
4727 |
|
4728 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4729 |
|
4730 RTL_W8(Config1, |
|
4731 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
|
4732 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4733 |
|
4734 cfg1 = RTL_R8(Config1); |
|
4735 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
|
4736 RTL_W8(Config1, cfg1 & ~LEDS0); |
|
4737 |
|
4738 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
|
4739 } |
|
4740 |
|
4741 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4742 { |
|
4743 rtl_csi_access_enable_2(ioaddr); |
|
4744 |
|
4745 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
|
4746 |
|
4747 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); |
|
4748 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
|
4749 } |
|
4750 |
|
4751 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4752 { |
|
4753 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
4754 |
|
4755 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); |
|
4756 } |
|
4757 |
|
4758 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4759 { |
|
4760 static const struct ephy_info e_info_8105e_1[] = { |
|
4761 { 0x07, 0, 0x4000 }, |
|
4762 { 0x19, 0, 0x0200 }, |
|
4763 { 0x19, 0, 0x0020 }, |
|
4764 { 0x1e, 0, 0x2000 }, |
|
4765 { 0x03, 0, 0x0001 }, |
|
4766 { 0x19, 0, 0x0100 }, |
|
4767 { 0x19, 0, 0x0004 }, |
|
4768 { 0x0a, 0, 0x0020 } |
|
4769 }; |
|
4770 |
|
4771 /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
|
4772 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
|
4773 |
|
4774 /* Disable Early Tally Counter */ |
|
4775 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
|
4776 |
|
4777 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
|
4778 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
|
4779 |
|
4780 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
|
4781 } |
|
4782 |
|
4783 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
|
4784 { |
|
4785 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
4786 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); |
|
4787 } |
|
4788 |
|
4789 static void rtl_hw_start_8101(struct net_device *dev) |
|
4790 { |
|
4791 struct rtl8169_private *tp = netdev_priv(dev); |
|
4792 void __iomem *ioaddr = tp->mmio_addr; |
|
4793 struct pci_dev *pdev = tp->pci_dev; |
|
4794 |
|
4795 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
|
4796 tp->event_slow &= ~RxFIFOOver; |
|
4797 |
|
4798 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
|
4799 tp->mac_version == RTL_GIGA_MAC_VER_16) { |
|
4800 int cap = pci_pcie_cap(pdev); |
|
4801 |
|
4802 if (cap) { |
|
4803 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, |
|
4804 PCI_EXP_DEVCTL_NOSNOOP_EN); |
|
4805 } |
|
4806 } |
|
4807 |
|
4808 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
4809 |
|
4810 switch (tp->mac_version) { |
|
4811 case RTL_GIGA_MAC_VER_07: |
|
4812 rtl_hw_start_8102e_1(ioaddr, pdev); |
|
4813 break; |
|
4814 |
|
4815 case RTL_GIGA_MAC_VER_08: |
|
4816 rtl_hw_start_8102e_3(ioaddr, pdev); |
|
4817 break; |
|
4818 |
|
4819 case RTL_GIGA_MAC_VER_09: |
|
4820 rtl_hw_start_8102e_2(ioaddr, pdev); |
|
4821 break; |
|
4822 |
|
4823 case RTL_GIGA_MAC_VER_29: |
|
4824 rtl_hw_start_8105e_1(ioaddr, pdev); |
|
4825 break; |
|
4826 case RTL_GIGA_MAC_VER_30: |
|
4827 rtl_hw_start_8105e_2(ioaddr, pdev); |
|
4828 break; |
|
4829 } |
|
4830 |
|
4831 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
4832 |
|
4833 RTL_W8(MaxTxPacketSize, TxPacketMax); |
|
4834 |
|
4835 rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
|
4836 |
|
4837 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
|
4838 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
4839 |
|
4840 RTL_W16(IntrMitigate, 0x0000); |
|
4841 |
|
4842 rtl_set_rx_tx_desc_registers(tp, ioaddr); |
|
4843 |
|
4844 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
4845 rtl_set_rx_tx_config_registers(tp); |
|
4846 |
|
4847 RTL_R8(IntrMask); |
|
4848 |
|
4849 rtl_set_rx_mode(dev); |
|
4850 |
|
4851 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
|
4852 } |
|
4853 |
|
4854 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) |
|
4855 { |
|
4856 struct rtl8169_private *tp = netdev_priv(dev); |
|
4857 |
|
4858 if (new_mtu < ETH_ZLEN || |
|
4859 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) |
|
4860 return -EINVAL; |
|
4861 |
|
4862 if (new_mtu > ETH_DATA_LEN) |
|
4863 rtl_hw_jumbo_enable(tp); |
|
4864 else |
|
4865 rtl_hw_jumbo_disable(tp); |
|
4866 |
|
4867 dev->mtu = new_mtu; |
|
4868 netdev_update_features(dev); |
|
4869 |
|
4870 return 0; |
|
4871 } |
|
4872 |
|
4873 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) |
|
4874 { |
|
4875 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
|
4876 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
|
4877 } |
|
4878 |
|
4879 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
|
4880 void **data_buff, struct RxDesc *desc) |
|
4881 { |
|
4882 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
|
4883 DMA_FROM_DEVICE); |
|
4884 |
|
4885 kfree(*data_buff); |
|
4886 *data_buff = NULL; |
|
4887 rtl8169_make_unusable_by_asic(desc); |
|
4888 } |
|
4889 |
|
4890 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) |
|
4891 { |
|
4892 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; |
|
4893 |
|
4894 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); |
|
4895 } |
|
4896 |
|
4897 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, |
|
4898 u32 rx_buf_sz) |
|
4899 { |
|
4900 desc->addr = cpu_to_le64(mapping); |
|
4901 wmb(); |
|
4902 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
4903 } |
|
4904 |
|
4905 static inline void *rtl8169_align(void *data) |
|
4906 { |
|
4907 return (void *)ALIGN((long)data, 16); |
|
4908 } |
|
4909 |
|
4910 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
|
4911 struct RxDesc *desc) |
|
4912 { |
|
4913 void *data; |
|
4914 dma_addr_t mapping; |
|
4915 struct device *d = &tp->pci_dev->dev; |
|
4916 struct net_device *dev = tp->dev; |
|
4917 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
|
4918 |
|
4919 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
|
4920 if (!data) |
|
4921 return NULL; |
|
4922 |
|
4923 if (rtl8169_align(data) != data) { |
|
4924 kfree(data); |
|
4925 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); |
|
4926 if (!data) |
|
4927 return NULL; |
|
4928 } |
|
4929 |
|
4930 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
|
4931 DMA_FROM_DEVICE); |
|
4932 if (unlikely(dma_mapping_error(d, mapping))) { |
|
4933 if (net_ratelimit()) |
|
4934 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); |
|
4935 goto err_out; |
|
4936 } |
|
4937 |
|
4938 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); |
|
4939 return data; |
|
4940 |
|
4941 err_out: |
|
4942 kfree(data); |
|
4943 return NULL; |
|
4944 } |
|
4945 |
|
4946 static void rtl8169_rx_clear(struct rtl8169_private *tp) |
|
4947 { |
|
4948 unsigned int i; |
|
4949 |
|
4950 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4951 if (tp->Rx_databuff[i]) { |
|
4952 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, |
|
4953 tp->RxDescArray + i); |
|
4954 } |
|
4955 } |
|
4956 } |
|
4957 |
|
4958 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
|
4959 { |
|
4960 desc->opts1 |= cpu_to_le32(RingEnd); |
|
4961 } |
|
4962 |
|
4963 static int rtl8169_rx_fill(struct rtl8169_private *tp) |
|
4964 { |
|
4965 unsigned int i; |
|
4966 |
|
4967 for (i = 0; i < NUM_RX_DESC; i++) { |
|
4968 void *data; |
|
4969 |
|
4970 if (tp->Rx_databuff[i]) |
|
4971 continue; |
|
4972 |
|
4973 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
|
4974 if (!data) { |
|
4975 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); |
|
4976 goto err_out; |
|
4977 } |
|
4978 tp->Rx_databuff[i] = data; |
|
4979 } |
|
4980 |
|
4981 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
|
4982 return 0; |
|
4983 |
|
4984 err_out: |
|
4985 rtl8169_rx_clear(tp); |
|
4986 return -ENOMEM; |
|
4987 } |
|
4988 |
|
4989 static int rtl8169_init_ring(struct net_device *dev) |
|
4990 { |
|
4991 struct rtl8169_private *tp = netdev_priv(dev); |
|
4992 |
|
4993 rtl8169_init_ring_indexes(tp); |
|
4994 |
|
4995 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); |
|
4996 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
|
4997 |
|
4998 return rtl8169_rx_fill(tp); |
|
4999 } |
|
5000 |
|
5001 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
|
5002 struct TxDesc *desc) |
|
5003 { |
|
5004 unsigned int len = tx_skb->len; |
|
5005 |
|
5006 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
|
5007 |
|
5008 desc->opts1 = 0x00; |
|
5009 desc->opts2 = 0x00; |
|
5010 desc->addr = 0x00; |
|
5011 tx_skb->len = 0; |
|
5012 } |
|
5013 |
|
5014 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
|
5015 unsigned int n) |
|
5016 { |
|
5017 unsigned int i; |
|
5018 |
|
5019 for (i = 0; i < n; i++) { |
|
5020 unsigned int entry = (start + i) % NUM_TX_DESC; |
|
5021 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5022 unsigned int len = tx_skb->len; |
|
5023 |
|
5024 if (len) { |
|
5025 struct sk_buff *skb = tx_skb->skb; |
|
5026 |
|
5027 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5028 tp->TxDescArray + entry); |
|
5029 if (skb) { |
|
5030 tp->dev->stats.tx_dropped++; |
|
5031 if (!tp->ecdev) { |
|
5032 dev_kfree_skb(skb); |
|
5033 } |
|
5034 tx_skb->skb = NULL; |
|
5035 } |
|
5036 } |
|
5037 } |
|
5038 } |
|
5039 |
|
5040 static void rtl8169_tx_clear(struct rtl8169_private *tp) |
|
5041 { |
|
5042 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); |
|
5043 tp->cur_tx = tp->dirty_tx = 0; |
|
5044 } |
|
5045 |
|
5046 static void rtl_reset_work(struct rtl8169_private *tp) |
|
5047 { |
|
5048 struct net_device *dev = tp->dev; |
|
5049 int i; |
|
5050 |
|
5051 napi_disable(&tp->napi); |
|
5052 netif_stop_queue(dev); |
|
5053 synchronize_sched(); |
|
5054 |
|
5055 rtl8169_hw_reset(tp); |
|
5056 |
|
5057 for (i = 0; i < NUM_RX_DESC; i++) |
|
5058 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); |
|
5059 |
|
5060 rtl8169_tx_clear(tp); |
|
5061 rtl8169_init_ring_indexes(tp); |
|
5062 |
|
5063 napi_enable(&tp->napi); |
|
5064 rtl_hw_start(dev); |
|
5065 netif_wake_queue(dev); |
|
5066 rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
|
5067 } |
|
5068 |
|
5069 static void rtl8169_tx_timeout(struct net_device *dev) |
|
5070 { |
|
5071 struct rtl8169_private *tp = netdev_priv(dev); |
|
5072 |
|
5073 if (!tp->ecdev) { |
|
5074 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5075 } |
|
5076 } |
|
5077 |
|
5078 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, |
|
5079 u32 *opts) |
|
5080 { |
|
5081 struct skb_shared_info *info = skb_shinfo(skb); |
|
5082 unsigned int cur_frag, entry; |
|
5083 struct TxDesc * uninitialized_var(txd); |
|
5084 struct device *d = &tp->pci_dev->dev; |
|
5085 |
|
5086 entry = tp->cur_tx; |
|
5087 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { |
|
5088 const skb_frag_t *frag = info->frags + cur_frag; |
|
5089 dma_addr_t mapping; |
|
5090 u32 status, len; |
|
5091 void *addr; |
|
5092 |
|
5093 entry = (entry + 1) % NUM_TX_DESC; |
|
5094 |
|
5095 txd = tp->TxDescArray + entry; |
|
5096 len = skb_frag_size(frag); |
|
5097 addr = skb_frag_address(frag); |
|
5098 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
|
5099 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5100 if (net_ratelimit()) |
|
5101 netif_err(tp, drv, tp->dev, |
|
5102 "Failed to map TX fragments DMA!\n"); |
|
5103 goto err_out; |
|
5104 } |
|
5105 |
|
5106 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5107 status = opts[0] | len | |
|
5108 (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5109 |
|
5110 txd->opts1 = cpu_to_le32(status); |
|
5111 txd->opts2 = cpu_to_le32(opts[1]); |
|
5112 txd->addr = cpu_to_le64(mapping); |
|
5113 |
|
5114 tp->tx_skb[entry].len = len; |
|
5115 } |
|
5116 |
|
5117 if (cur_frag) { |
|
5118 tp->tx_skb[entry].skb = skb; |
|
5119 txd->opts1 |= cpu_to_le32(LastFrag); |
|
5120 } |
|
5121 |
|
5122 return cur_frag; |
|
5123 |
|
5124 err_out: |
|
5125 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); |
|
5126 return -EIO; |
|
5127 } |
|
5128 |
|
5129 static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
|
5130 struct sk_buff *skb, u32 *opts) |
|
5131 { |
|
5132 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
|
5133 u32 mss = skb_shinfo(skb)->gso_size; |
|
5134 int offset = info->opts_offset; |
|
5135 |
|
5136 if (mss) { |
|
5137 opts[0] |= TD_LSO; |
|
5138 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; |
|
5139 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
|
5140 const struct iphdr *ip = ip_hdr(skb); |
|
5141 |
|
5142 if (ip->protocol == IPPROTO_TCP) |
|
5143 opts[offset] |= info->checksum.tcp; |
|
5144 else if (ip->protocol == IPPROTO_UDP) |
|
5145 opts[offset] |= info->checksum.udp; |
|
5146 else |
|
5147 WARN_ON_ONCE(1); |
|
5148 } |
|
5149 } |
|
5150 |
|
5151 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
|
5152 struct net_device *dev) |
|
5153 { |
|
5154 struct rtl8169_private *tp = netdev_priv(dev); |
|
5155 unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
|
5156 struct TxDesc *txd = tp->TxDescArray + entry; |
|
5157 void __iomem *ioaddr = tp->mmio_addr; |
|
5158 struct device *d = &tp->pci_dev->dev; |
|
5159 dma_addr_t mapping; |
|
5160 u32 status, len; |
|
5161 u32 opts[2]; |
|
5162 int frags; |
|
5163 |
|
5164 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
|
5165 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
|
5166 goto err_stop_0; |
|
5167 } |
|
5168 |
|
5169 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) |
|
5170 goto err_stop_0; |
|
5171 |
|
5172 len = skb_headlen(skb); |
|
5173 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
|
5174 if (unlikely(dma_mapping_error(d, mapping))) { |
|
5175 if (net_ratelimit()) |
|
5176 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); |
|
5177 goto err_dma_0; |
|
5178 } |
|
5179 |
|
5180 tp->tx_skb[entry].len = len; |
|
5181 txd->addr = cpu_to_le64(mapping); |
|
5182 |
|
5183 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
|
5184 opts[0] = DescOwn; |
|
5185 |
|
5186 rtl8169_tso_csum(tp, skb, opts); |
|
5187 |
|
5188 frags = rtl8169_xmit_frags(tp, skb, opts); |
|
5189 if (frags < 0) |
|
5190 goto err_dma_1; |
|
5191 else if (frags) |
|
5192 opts[0] |= FirstFrag; |
|
5193 else { |
|
5194 opts[0] |= FirstFrag | LastFrag; |
|
5195 tp->tx_skb[entry].skb = skb; |
|
5196 } |
|
5197 |
|
5198 txd->opts2 = cpu_to_le32(opts[1]); |
|
5199 |
|
5200 skb_tx_timestamp(skb); |
|
5201 |
|
5202 wmb(); |
|
5203 |
|
5204 /* Anti gcc 2.95.3 bugware (sic) */ |
|
5205 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
|
5206 txd->opts1 = cpu_to_le32(status); |
|
5207 |
|
5208 tp->cur_tx += frags + 1; |
|
5209 |
|
5210 wmb(); |
|
5211 |
|
5212 RTL_W8(TxPoll, NPQ); |
|
5213 |
|
5214 mmiowb(); |
|
5215 |
|
5216 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5217 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
|
5218 * not miss a ring update when it notices a stopped queue. |
|
5219 */ |
|
5220 smp_wmb(); |
|
5221 if (!tp->ecdev) { |
|
5222 netif_stop_queue(dev); |
|
5223 } |
|
5224 /* Sync with rtl_tx: |
|
5225 * - publish queue status and cur_tx ring index (write barrier) |
|
5226 * - refresh dirty_tx ring index (read barrier). |
|
5227 * May the current thread have a pessimistic view of the ring |
|
5228 * status and forget to wake up queue, a racing rtl_tx thread |
|
5229 * can't. |
|
5230 */ |
|
5231 smp_mb(); |
|
5232 if (!tp->ecdev && TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
|
5233 netif_wake_queue(dev); |
|
5234 } |
|
5235 |
|
5236 return NETDEV_TX_OK; |
|
5237 |
|
5238 err_dma_1: |
|
5239 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
|
5240 err_dma_0: |
|
5241 if (!tp->ecdev) { |
|
5242 dev_kfree_skb(skb); |
|
5243 } |
|
5244 dev->stats.tx_dropped++; |
|
5245 return NETDEV_TX_OK; |
|
5246 |
|
5247 err_stop_0: |
|
5248 if (!tp->ecdev) { |
|
5249 netif_stop_queue(dev); |
|
5250 } |
|
5251 dev->stats.tx_dropped++; |
|
5252 return NETDEV_TX_BUSY; |
|
5253 } |
|
5254 |
|
5255 static void rtl8169_pcierr_interrupt(struct net_device *dev) |
|
5256 { |
|
5257 struct rtl8169_private *tp = netdev_priv(dev); |
|
5258 struct pci_dev *pdev = tp->pci_dev; |
|
5259 u16 pci_status, pci_cmd; |
|
5260 |
|
5261 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); |
|
5262 pci_read_config_word(pdev, PCI_STATUS, &pci_status); |
|
5263 |
|
5264 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
|
5265 pci_cmd, pci_status); |
|
5266 |
|
5267 /* |
|
5268 * The recovery sequence below admits a very elaborated explanation: |
|
5269 * - it seems to work; |
|
5270 * - I did not see what else could be done; |
|
5271 * - it makes iop3xx happy. |
|
5272 * |
|
5273 * Feel free to adjust to your needs. |
|
5274 */ |
|
5275 if (pdev->broken_parity_status) |
|
5276 pci_cmd &= ~PCI_COMMAND_PARITY; |
|
5277 else |
|
5278 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; |
|
5279 |
|
5280 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); |
|
5281 |
|
5282 pci_write_config_word(pdev, PCI_STATUS, |
|
5283 pci_status & (PCI_STATUS_DETECTED_PARITY | |
|
5284 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | |
|
5285 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); |
|
5286 |
|
5287 /* The infamous DAC f*ckup only happens at boot time */ |
|
5288 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { |
|
5289 void __iomem *ioaddr = tp->mmio_addr; |
|
5290 |
|
5291 netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
|
5292 tp->cp_cmd &= ~PCIDAC; |
|
5293 RTL_W16(CPlusCmd, tp->cp_cmd); |
|
5294 dev->features &= ~NETIF_F_HIGHDMA; |
|
5295 } |
|
5296 |
|
5297 rtl8169_hw_reset(tp); |
|
5298 |
|
5299 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5300 } |
|
5301 |
|
5302 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
|
5303 { |
|
5304 unsigned int dirty_tx, tx_left; |
|
5305 |
|
5306 dirty_tx = tp->dirty_tx; |
|
5307 smp_rmb(); |
|
5308 tx_left = tp->cur_tx - dirty_tx; |
|
5309 |
|
5310 while (tx_left > 0) { |
|
5311 unsigned int entry = dirty_tx % NUM_TX_DESC; |
|
5312 struct ring_info *tx_skb = tp->tx_skb + entry; |
|
5313 u32 status; |
|
5314 |
|
5315 rmb(); |
|
5316 status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
|
5317 if (status & DescOwn) |
|
5318 break; |
|
5319 |
|
5320 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
|
5321 tp->TxDescArray + entry); |
|
5322 if (status & LastFrag) { |
|
5323 u64_stats_update_begin(&tp->tx_stats.syncp); |
|
5324 tp->tx_stats.packets++; |
|
5325 tp->tx_stats.bytes += tx_skb->skb->len; |
|
5326 u64_stats_update_end(&tp->tx_stats.syncp); |
|
5327 if (!tp->ecdev) { |
|
5328 dev_kfree_skb(tx_skb->skb); |
|
5329 } |
|
5330 tx_skb->skb = NULL; |
|
5331 } |
|
5332 dirty_tx++; |
|
5333 tx_left--; |
|
5334 } |
|
5335 |
|
5336 if (tp->dirty_tx != dirty_tx) { |
|
5337 tp->dirty_tx = dirty_tx; |
|
5338 /* Sync with rtl8169_start_xmit: |
|
5339 * - publish dirty_tx ring index (write barrier) |
|
5340 * - refresh cur_tx ring index and queue status (read barrier) |
|
5341 * May the current thread miss the stopped queue condition, |
|
5342 * a racing xmit thread can only have a right view of the |
|
5343 * ring status. |
|
5344 */ |
|
5345 smp_mb(); |
|
5346 if (!tp->ecdev && netif_queue_stopped(dev) && |
|
5347 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
|
5348 netif_wake_queue(dev); |
|
5349 } |
|
5350 /* |
|
5351 * 8168 hack: TxPoll requests are lost when the Tx packets are |
|
5352 * too close. Let's kick an extra TxPoll request when a burst |
|
5353 * of start_xmit activity is detected (if it is not detected, |
|
5354 * it is slow enough). -- FR |
|
5355 */ |
|
5356 if (tp->cur_tx != dirty_tx) { |
|
5357 void __iomem *ioaddr = tp->mmio_addr; |
|
5358 |
|
5359 RTL_W8(TxPoll, NPQ); |
|
5360 } |
|
5361 } |
|
5362 } |
|
5363 |
|
5364 static inline int rtl8169_fragmented_frame(u32 status) |
|
5365 { |
|
5366 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); |
|
5367 } |
|
5368 |
|
5369 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
|
5370 { |
|
5371 u32 status = opts1 & RxProtoMask; |
|
5372 |
|
5373 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || |
|
5374 ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
|
5375 skb->ip_summed = CHECKSUM_UNNECESSARY; |
|
5376 else |
|
5377 skb_checksum_none_assert(skb); |
|
5378 } |
|
5379 |
|
5380 static struct sk_buff *rtl8169_try_rx_copy(void *data, |
|
5381 struct rtl8169_private *tp, |
|
5382 int pkt_size, |
|
5383 dma_addr_t addr) |
|
5384 { |
|
5385 struct sk_buff *skb; |
|
5386 struct device *d = &tp->pci_dev->dev; |
|
5387 |
|
5388 data = rtl8169_align(data); |
|
5389 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5390 prefetch(data); |
|
5391 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); |
|
5392 if (skb) |
|
5393 memcpy(skb->data, data, pkt_size); |
|
5394 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5395 |
|
5396 return skb; |
|
5397 } |
|
5398 |
|
5399 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
|
5400 { |
|
5401 unsigned int cur_rx, rx_left; |
|
5402 unsigned int count; |
|
5403 |
|
5404 cur_rx = tp->cur_rx; |
|
5405 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; |
|
5406 rx_left = min(rx_left, budget); |
|
5407 |
|
5408 for (; rx_left > 0; rx_left--, cur_rx++) { |
|
5409 unsigned int entry = cur_rx % NUM_RX_DESC; |
|
5410 struct RxDesc *desc = tp->RxDescArray + entry; |
|
5411 u32 status; |
|
5412 |
|
5413 rmb(); |
|
5414 status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
|
5415 |
|
5416 if (status & DescOwn) |
|
5417 break; |
|
5418 if (unlikely(status & RxRES)) { |
|
5419 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
|
5420 status); |
|
5421 dev->stats.rx_errors++; |
|
5422 if (status & (RxRWT | RxRUNT)) |
|
5423 dev->stats.rx_length_errors++; |
|
5424 if (status & RxCRC) |
|
5425 dev->stats.rx_crc_errors++; |
|
5426 if (status & RxFOVF) { |
|
5427 if (!tp->ecdev) { |
|
5428 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5429 } |
|
5430 dev->stats.rx_fifo_errors++; |
|
5431 } |
|
5432 if ((status & (RxRUNT | RxCRC)) && |
|
5433 !(status & (RxRWT | RxFOVF)) && |
|
5434 (dev->features & NETIF_F_RXALL)) |
|
5435 goto process_pkt; |
|
5436 |
|
5437 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5438 } else { |
|
5439 struct sk_buff *skb; |
|
5440 dma_addr_t addr; |
|
5441 int pkt_size; |
|
5442 |
|
5443 process_pkt: |
|
5444 addr = le64_to_cpu(desc->addr); |
|
5445 if (likely(!(dev->features & NETIF_F_RXFCS))) |
|
5446 pkt_size = (status & 0x00003fff) - 4; |
|
5447 else |
|
5448 pkt_size = status & 0x00003fff; |
|
5449 |
|
5450 /* |
|
5451 * The driver does not support incoming fragmented |
|
5452 * frames. They are seen as a symptom of over-mtu |
|
5453 * sized frames. |
|
5454 */ |
|
5455 if (unlikely(rtl8169_fragmented_frame(status))) { |
|
5456 dev->stats.rx_dropped++; |
|
5457 dev->stats.rx_length_errors++; |
|
5458 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5459 continue; |
|
5460 } |
|
5461 |
|
5462 if (tp->ecdev) { |
|
5463 struct device *d = &tp->pci_dev->dev; |
|
5464 |
|
5465 /* reusing parts of rtl8169_try_rx_copy() */ |
|
5466 tp->Rx_databuff[entry] = rtl8169_align(tp->Rx_databuff[entry]); |
|
5467 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5468 prefetch(tp->Rx_databuff[entry]); |
|
5469 |
|
5470 ecdev_receive(tp->ecdev, tp->Rx_databuff[entry], pkt_size); |
|
5471 |
|
5472 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
|
5473 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5474 |
|
5475 rtl8169_rx_csum(tp->Rx_databuff[entry], status); |
|
5476 |
|
5477 // No need to detect link status as |
|
5478 // long as frames are received: Reset watchdog. |
|
5479 tp->ec_watchdog_jiffies = jiffies; |
|
5480 } |
|
5481 else { |
|
5482 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
|
5483 tp, pkt_size, addr); |
|
5484 rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
5485 if (!skb) { |
|
5486 dev->stats.rx_dropped++; |
|
5487 continue; |
|
5488 } |
|
5489 |
|
5490 rtl8169_rx_csum(skb, status); |
|
5491 skb_put(skb, pkt_size); |
|
5492 skb->protocol = eth_type_trans(skb, dev); |
|
5493 |
|
5494 rtl8169_rx_vlan_tag(desc, skb); |
|
5495 |
|
5496 napi_gro_receive(&tp->napi, skb); |
|
5497 } |
|
5498 |
|
5499 u64_stats_update_begin(&tp->rx_stats.syncp); |
|
5500 tp->rx_stats.packets++; |
|
5501 tp->rx_stats.bytes += pkt_size; |
|
5502 u64_stats_update_end(&tp->rx_stats.syncp); |
|
5503 } |
|
5504 |
|
5505 /* Work around for AMD plateform. */ |
|
5506 if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
|
5507 (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
|
5508 desc->opts2 = 0; |
|
5509 cur_rx++; |
|
5510 } |
|
5511 } |
|
5512 |
|
5513 count = cur_rx - tp->cur_rx; |
|
5514 tp->cur_rx = cur_rx; |
|
5515 |
|
5516 tp->dirty_rx += count; |
|
5517 |
|
5518 return count; |
|
5519 } |
|
5520 |
|
5521 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
|
5522 { |
|
5523 struct net_device *dev = dev_instance; |
|
5524 struct rtl8169_private *tp = netdev_priv(dev); |
|
5525 int handled = 0; |
|
5526 u16 status; |
|
5527 |
|
5528 status = rtl_get_events(tp); |
|
5529 if (status && status != 0xffff) { |
|
5530 status &= RTL_EVENT_NAPI | tp->event_slow; |
|
5531 if (status) { |
|
5532 handled = 1; |
|
5533 |
|
5534 rtl_irq_disable(tp); |
|
5535 napi_schedule(&tp->napi); |
|
5536 } |
|
5537 } |
|
5538 return IRQ_RETVAL(handled); |
|
5539 } |
|
5540 |
|
5541 /* |
|
5542 * Workqueue context. |
|
5543 */ |
|
5544 static void rtl_slow_event_work(struct rtl8169_private *tp) |
|
5545 { |
|
5546 struct net_device *dev = tp->dev; |
|
5547 u16 status; |
|
5548 |
|
5549 status = rtl_get_events(tp) & tp->event_slow; |
|
5550 rtl_ack_events(tp, status); |
|
5551 |
|
5552 if (unlikely(!tp->ecdev && (status & RxFIFOOver))) { |
|
5553 switch (tp->mac_version) { |
|
5554 /* Work around for rx fifo overflow */ |
|
5555 case RTL_GIGA_MAC_VER_11: |
|
5556 netif_stop_queue(dev); |
|
5557 /* XXX - Hack alert. See rtl_task(). */ |
|
5558 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); |
|
5559 default: |
|
5560 break; |
|
5561 } |
|
5562 } |
|
5563 |
|
5564 if (unlikely(!tp->ecdev && (status & SYSErr))) |
|
5565 rtl8169_pcierr_interrupt(dev); |
|
5566 |
|
5567 if (status & LinkChg) |
|
5568 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); |
|
5569 |
|
5570 if (!tp->ecdev) { |
|
5571 napi_disable(&tp->napi); |
|
5572 rtl_irq_disable(tp); |
|
5573 |
|
5574 napi_enable(&tp->napi); |
|
5575 napi_schedule(&tp->napi); |
|
5576 } |
|
5577 } |
|
5578 |
|
5579 static void rtl_task(struct work_struct *work) |
|
5580 { |
|
5581 static const struct { |
|
5582 int bitnr; |
|
5583 void (*action)(struct rtl8169_private *); |
|
5584 } rtl_work[] = { |
|
5585 /* XXX - keep rtl_slow_event_work() as first element. */ |
|
5586 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
|
5587 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, |
|
5588 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } |
|
5589 }; |
|
5590 struct rtl8169_private *tp = |
|
5591 container_of(work, struct rtl8169_private, wk.work); |
|
5592 struct net_device *dev = tp->dev; |
|
5593 int i; |
|
5594 |
|
5595 rtl_lock_work(tp); |
|
5596 |
|
5597 if (!netif_running(dev) || |
|
5598 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) |
|
5599 goto out_unlock; |
|
5600 |
|
5601 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { |
|
5602 bool pending; |
|
5603 |
|
5604 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
|
5605 if (pending) |
|
5606 rtl_work[i].action(tp); |
|
5607 } |
|
5608 |
|
5609 out_unlock: |
|
5610 rtl_unlock_work(tp); |
|
5611 } |
|
5612 |
|
5613 static void ec_poll(struct net_device *dev) |
|
5614 { |
|
5615 struct rtl8169_private *tp = netdev_priv(dev); |
|
5616 u16 status; |
|
5617 |
|
5618 status = rtl_get_events(tp); |
|
5619 rtl_ack_events(tp, status & ~tp->event_slow); |
|
5620 |
|
5621 if (status & RTL_EVENT_NAPI_RX) { |
|
5622 rtl_rx(dev, tp, 100); // FIXME |
|
5623 } |
|
5624 |
|
5625 if (status & RTL_EVENT_NAPI_TX) { |
|
5626 rtl_tx(dev, tp); |
|
5627 } |
|
5628 |
|
5629 if (jiffies - tp->ec_watchdog_jiffies >= 2 * HZ) { |
|
5630 void __iomem *ioaddr = tp->mmio_addr; |
|
5631 ecdev_set_link(tp->ecdev, tp->link_ok(ioaddr) ? 1 : 0); |
|
5632 tp->ec_watchdog_jiffies = jiffies; |
|
5633 } |
|
5634 } |
|
5635 |
|
5636 static int rtl8169_poll(struct napi_struct *napi, int budget) |
|
5637 { |
|
5638 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
|
5639 struct net_device *dev = tp->dev; |
|
5640 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
|
5641 int work_done= 0; |
|
5642 u16 status; |
|
5643 |
|
5644 status = rtl_get_events(tp); |
|
5645 rtl_ack_events(tp, status & ~tp->event_slow); |
|
5646 |
|
5647 if (status & RTL_EVENT_NAPI_RX) |
|
5648 work_done = rtl_rx(dev, tp, (u32) budget); |
|
5649 |
|
5650 if (status & RTL_EVENT_NAPI_TX) |
|
5651 rtl_tx(dev, tp); |
|
5652 |
|
5653 if (status & tp->event_slow) { |
|
5654 enable_mask &= ~tp->event_slow; |
|
5655 |
|
5656 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); |
|
5657 } |
|
5658 |
|
5659 if (work_done < budget) { |
|
5660 napi_complete(napi); |
|
5661 |
|
5662 rtl_irq_enable(tp, enable_mask); |
|
5663 mmiowb(); |
|
5664 } |
|
5665 |
|
5666 return work_done; |
|
5667 } |
|
5668 |
|
5669 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
|
5670 { |
|
5671 struct rtl8169_private *tp = netdev_priv(dev); |
|
5672 |
|
5673 if (tp->mac_version > RTL_GIGA_MAC_VER_06) |
|
5674 return; |
|
5675 |
|
5676 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); |
|
5677 RTL_W32(RxMissed, 0); |
|
5678 } |
|
5679 |
|
5680 static void rtl8169_down(struct net_device *dev) |
|
5681 { |
|
5682 struct rtl8169_private *tp = netdev_priv(dev); |
|
5683 void __iomem *ioaddr = tp->mmio_addr; |
|
5684 |
|
5685 if (!tp->ecdev) { |
|
5686 del_timer_sync(&tp->timer); |
|
5687 |
|
5688 napi_disable(&tp->napi); |
|
5689 netif_stop_queue(dev); |
|
5690 } |
|
5691 |
|
5692 rtl8169_hw_reset(tp); |
|
5693 /* |
|
5694 * At this point device interrupts can not be enabled in any function, |
|
5695 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
|
5696 * and napi is disabled (rtl8169_poll). |
|
5697 */ |
|
5698 rtl8169_rx_missed(dev, ioaddr); |
|
5699 |
|
5700 /* Give a racing hard_start_xmit a few cycles to complete. */ |
|
5701 synchronize_sched(); |
|
5702 |
|
5703 rtl8169_tx_clear(tp); |
|
5704 |
|
5705 rtl8169_rx_clear(tp); |
|
5706 |
|
5707 rtl_pll_power_down(tp); |
|
5708 } |
|
5709 |
|
5710 static int rtl8169_close(struct net_device *dev) |
|
5711 { |
|
5712 struct rtl8169_private *tp = netdev_priv(dev); |
|
5713 struct pci_dev *pdev = tp->pci_dev; |
|
5714 |
|
5715 pm_runtime_get_sync(&pdev->dev); |
|
5716 |
|
5717 /* Update counters before going down */ |
|
5718 rtl8169_update_counters(dev); |
|
5719 |
|
5720 rtl_lock_work(tp); |
|
5721 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5722 |
|
5723 rtl8169_down(dev); |
|
5724 rtl_unlock_work(tp); |
|
5725 |
|
5726 if (!tp->ecdev) { |
|
5727 free_irq(pdev->irq, dev); |
|
5728 } |
|
5729 |
|
5730 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
5731 tp->RxPhyAddr); |
|
5732 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
5733 tp->TxPhyAddr); |
|
5734 tp->TxDescArray = NULL; |
|
5735 tp->RxDescArray = NULL; |
|
5736 |
|
5737 pm_runtime_put_sync(&pdev->dev); |
|
5738 |
|
5739 return 0; |
|
5740 } |
|
5741 |
|
5742 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
5743 static void rtl8169_netpoll(struct net_device *dev) |
|
5744 { |
|
5745 struct rtl8169_private *tp = netdev_priv(dev); |
|
5746 |
|
5747 rtl8169_interrupt(tp->pci_dev->irq, dev); |
|
5748 } |
|
5749 #endif |
|
5750 |
|
5751 static int rtl_open(struct net_device *dev) |
|
5752 { |
|
5753 struct rtl8169_private *tp = netdev_priv(dev); |
|
5754 void __iomem *ioaddr = tp->mmio_addr; |
|
5755 struct pci_dev *pdev = tp->pci_dev; |
|
5756 int retval = -ENOMEM; |
|
5757 |
|
5758 pm_runtime_get_sync(&pdev->dev); |
|
5759 |
|
5760 /* |
|
5761 * Rx and Tx desscriptors needs 256 bytes alignment. |
|
5762 * dma_alloc_coherent provides more. |
|
5763 */ |
|
5764 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
|
5765 &tp->TxPhyAddr, GFP_KERNEL); |
|
5766 if (!tp->TxDescArray) |
|
5767 goto err_pm_runtime_put; |
|
5768 |
|
5769 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
|
5770 &tp->RxPhyAddr, GFP_KERNEL); |
|
5771 if (!tp->RxDescArray) |
|
5772 goto err_free_tx_0; |
|
5773 |
|
5774 retval = rtl8169_init_ring(dev); |
|
5775 if (retval < 0) |
|
5776 goto err_free_rx_1; |
|
5777 |
|
5778 INIT_WORK(&tp->wk.work, rtl_task); |
|
5779 |
|
5780 smp_mb(); |
|
5781 |
|
5782 rtl_request_firmware(tp); |
|
5783 |
|
5784 if (!tp->ecdev) { |
|
5785 retval = request_irq(pdev->irq, rtl8169_interrupt, |
|
5786 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
|
5787 dev->name, dev); |
|
5788 if (retval < 0) |
|
5789 goto err_release_fw_2; |
|
5790 } |
|
5791 |
|
5792 rtl_lock_work(tp); |
|
5793 |
|
5794 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5795 |
|
5796 if (!tp->ecdev) { |
|
5797 napi_enable(&tp->napi); |
|
5798 } |
|
5799 |
|
5800 rtl8169_init_phy(dev, tp); |
|
5801 |
|
5802 __rtl8169_set_features(dev, dev->features); |
|
5803 |
|
5804 rtl_pll_power_up(tp); |
|
5805 |
|
5806 rtl_hw_start(dev); |
|
5807 |
|
5808 if (!tp->ecdev) { |
|
5809 netif_start_queue(dev); |
|
5810 } |
|
5811 |
|
5812 rtl_unlock_work(tp); |
|
5813 |
|
5814 tp->saved_wolopts = 0; |
|
5815 pm_runtime_put_noidle(&pdev->dev); |
|
5816 |
|
5817 rtl8169_check_link_status(dev, tp, ioaddr); |
|
5818 out: |
|
5819 return retval; |
|
5820 |
|
5821 err_release_fw_2: |
|
5822 rtl_release_firmware(tp); |
|
5823 rtl8169_rx_clear(tp); |
|
5824 err_free_rx_1: |
|
5825 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
|
5826 tp->RxPhyAddr); |
|
5827 tp->RxDescArray = NULL; |
|
5828 err_free_tx_0: |
|
5829 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
|
5830 tp->TxPhyAddr); |
|
5831 tp->TxDescArray = NULL; |
|
5832 err_pm_runtime_put: |
|
5833 pm_runtime_put_noidle(&pdev->dev); |
|
5834 goto out; |
|
5835 } |
|
5836 |
|
5837 static struct rtnl_link_stats64 * |
|
5838 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
|
5839 { |
|
5840 struct rtl8169_private *tp = netdev_priv(dev); |
|
5841 void __iomem *ioaddr = tp->mmio_addr; |
|
5842 unsigned int start; |
|
5843 |
|
5844 if (netif_running(dev)) |
|
5845 rtl8169_rx_missed(dev, ioaddr); |
|
5846 |
|
5847 do { |
|
5848 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp); |
|
5849 stats->rx_packets = tp->rx_stats.packets; |
|
5850 stats->rx_bytes = tp->rx_stats.bytes; |
|
5851 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start)); |
|
5852 |
|
5853 |
|
5854 do { |
|
5855 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp); |
|
5856 stats->tx_packets = tp->tx_stats.packets; |
|
5857 stats->tx_bytes = tp->tx_stats.bytes; |
|
5858 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start)); |
|
5859 |
|
5860 stats->rx_dropped = dev->stats.rx_dropped; |
|
5861 stats->tx_dropped = dev->stats.tx_dropped; |
|
5862 stats->rx_length_errors = dev->stats.rx_length_errors; |
|
5863 stats->rx_errors = dev->stats.rx_errors; |
|
5864 stats->rx_crc_errors = dev->stats.rx_crc_errors; |
|
5865 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; |
|
5866 stats->rx_missed_errors = dev->stats.rx_missed_errors; |
|
5867 |
|
5868 return stats; |
|
5869 } |
|
5870 |
|
5871 static void rtl8169_net_suspend(struct net_device *dev) |
|
5872 { |
|
5873 struct rtl8169_private *tp = netdev_priv(dev); |
|
5874 |
|
5875 if (!netif_running(dev)) |
|
5876 return; |
|
5877 |
|
5878 netif_device_detach(dev); |
|
5879 netif_stop_queue(dev); |
|
5880 |
|
5881 rtl_lock_work(tp); |
|
5882 napi_disable(&tp->napi); |
|
5883 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5884 rtl_unlock_work(tp); |
|
5885 |
|
5886 rtl_pll_power_down(tp); |
|
5887 } |
|
5888 |
|
5889 #ifdef CONFIG_PM |
|
5890 |
|
5891 static int rtl8169_suspend(struct device *device) |
|
5892 { |
|
5893 struct pci_dev *pdev = to_pci_dev(device); |
|
5894 struct net_device *dev = pci_get_drvdata(pdev); |
|
5895 struct rtl8169_private *tp = netdev_priv(dev); |
|
5896 |
|
5897 if (tp->ecdev) { |
|
5898 return -EBUSY; |
|
5899 } |
|
5900 |
|
5901 rtl8169_net_suspend(dev); |
|
5902 |
|
5903 return 0; |
|
5904 } |
|
5905 |
|
5906 static void __rtl8169_resume(struct net_device *dev) |
|
5907 { |
|
5908 struct rtl8169_private *tp = netdev_priv(dev); |
|
5909 |
|
5910 netif_device_attach(dev); |
|
5911 |
|
5912 rtl_pll_power_up(tp); |
|
5913 |
|
5914 rtl_lock_work(tp); |
|
5915 napi_enable(&tp->napi); |
|
5916 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
|
5917 rtl_unlock_work(tp); |
|
5918 |
|
5919 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
|
5920 } |
|
5921 |
|
5922 static int rtl8169_resume(struct device *device) |
|
5923 { |
|
5924 struct pci_dev *pdev = to_pci_dev(device); |
|
5925 struct net_device *dev = pci_get_drvdata(pdev); |
|
5926 struct rtl8169_private *tp = netdev_priv(dev); |
|
5927 |
|
5928 if (tp->ecdev) { |
|
5929 return -EBUSY; |
|
5930 } |
|
5931 |
|
5932 rtl8169_init_phy(dev, tp); |
|
5933 |
|
5934 if (netif_running(dev)) |
|
5935 __rtl8169_resume(dev); |
|
5936 |
|
5937 return 0; |
|
5938 } |
|
5939 |
|
5940 static int rtl8169_runtime_suspend(struct device *device) |
|
5941 { |
|
5942 struct pci_dev *pdev = to_pci_dev(device); |
|
5943 struct net_device *dev = pci_get_drvdata(pdev); |
|
5944 struct rtl8169_private *tp = netdev_priv(dev); |
|
5945 |
|
5946 if (tp->ecdev) { |
|
5947 return -EBUSY; |
|
5948 } |
|
5949 |
|
5950 if (!tp->TxDescArray) |
|
5951 return 0; |
|
5952 |
|
5953 rtl_lock_work(tp); |
|
5954 tp->saved_wolopts = __rtl8169_get_wol(tp); |
|
5955 __rtl8169_set_wol(tp, WAKE_ANY); |
|
5956 rtl_unlock_work(tp); |
|
5957 |
|
5958 rtl8169_net_suspend(dev); |
|
5959 |
|
5960 return 0; |
|
5961 } |
|
5962 |
|
5963 static int rtl8169_runtime_resume(struct device *device) |
|
5964 { |
|
5965 struct pci_dev *pdev = to_pci_dev(device); |
|
5966 struct net_device *dev = pci_get_drvdata(pdev); |
|
5967 struct rtl8169_private *tp = netdev_priv(dev); |
|
5968 |
|
5969 if (tp->ecdev) { |
|
5970 return -EBUSY; |
|
5971 } |
|
5972 |
|
5973 if (!tp->TxDescArray) |
|
5974 return 0; |
|
5975 |
|
5976 rtl_lock_work(tp); |
|
5977 __rtl8169_set_wol(tp, tp->saved_wolopts); |
|
5978 tp->saved_wolopts = 0; |
|
5979 rtl_unlock_work(tp); |
|
5980 |
|
5981 rtl8169_init_phy(dev, tp); |
|
5982 |
|
5983 __rtl8169_resume(dev); |
|
5984 |
|
5985 return 0; |
|
5986 } |
|
5987 |
|
5988 static int rtl8169_runtime_idle(struct device *device) |
|
5989 { |
|
5990 struct pci_dev *pdev = to_pci_dev(device); |
|
5991 struct net_device *dev = pci_get_drvdata(pdev); |
|
5992 struct rtl8169_private *tp = netdev_priv(dev); |
|
5993 |
|
5994 return tp->TxDescArray ? -EBUSY : 0; |
|
5995 } |
|
5996 |
|
5997 static const struct dev_pm_ops rtl8169_pm_ops = { |
|
5998 .suspend = rtl8169_suspend, |
|
5999 .resume = rtl8169_resume, |
|
6000 .freeze = rtl8169_suspend, |
|
6001 .thaw = rtl8169_resume, |
|
6002 .poweroff = rtl8169_suspend, |
|
6003 .restore = rtl8169_resume, |
|
6004 .runtime_suspend = rtl8169_runtime_suspend, |
|
6005 .runtime_resume = rtl8169_runtime_resume, |
|
6006 .runtime_idle = rtl8169_runtime_idle, |
|
6007 }; |
|
6008 |
|
6009 #define RTL8169_PM_OPS (&rtl8169_pm_ops) |
|
6010 |
|
6011 #else /* !CONFIG_PM */ |
|
6012 |
|
6013 #define RTL8169_PM_OPS NULL |
|
6014 |
|
6015 #endif /* !CONFIG_PM */ |
|
6016 |
|
6017 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
|
6018 { |
|
6019 void __iomem *ioaddr = tp->mmio_addr; |
|
6020 |
|
6021 /* WoL fails with 8168b when the receiver is disabled. */ |
|
6022 switch (tp->mac_version) { |
|
6023 case RTL_GIGA_MAC_VER_11: |
|
6024 case RTL_GIGA_MAC_VER_12: |
|
6025 case RTL_GIGA_MAC_VER_17: |
|
6026 pci_clear_master(tp->pci_dev); |
|
6027 |
|
6028 RTL_W8(ChipCmd, CmdRxEnb); |
|
6029 /* PCI commit */ |
|
6030 RTL_R8(ChipCmd); |
|
6031 break; |
|
6032 default: |
|
6033 break; |
|
6034 } |
|
6035 } |
|
6036 |
|
6037 static void rtl_shutdown(struct pci_dev *pdev) |
|
6038 { |
|
6039 struct net_device *dev = pci_get_drvdata(pdev); |
|
6040 struct rtl8169_private *tp = netdev_priv(dev); |
|
6041 struct device *d = &pdev->dev; |
|
6042 |
|
6043 pm_runtime_get_sync(d); |
|
6044 |
|
6045 rtl8169_net_suspend(dev); |
|
6046 |
|
6047 /* Restore original MAC address */ |
|
6048 rtl_rar_set(tp, dev->perm_addr); |
|
6049 |
|
6050 rtl8169_hw_reset(tp); |
|
6051 |
|
6052 if (system_state == SYSTEM_POWER_OFF) { |
|
6053 if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
|
6054 rtl_wol_suspend_quirk(tp); |
|
6055 rtl_wol_shutdown_quirk(tp); |
|
6056 } |
|
6057 |
|
6058 pci_wake_from_d3(pdev, true); |
|
6059 pci_set_power_state(pdev, PCI_D3hot); |
|
6060 } |
|
6061 |
|
6062 pm_runtime_put_noidle(d); |
|
6063 } |
|
6064 |
|
6065 static void __devexit rtl_remove_one(struct pci_dev *pdev) |
|
6066 { |
|
6067 struct net_device *dev = pci_get_drvdata(pdev); |
|
6068 struct rtl8169_private *tp = netdev_priv(dev); |
|
6069 |
|
6070 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6071 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6072 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6073 rtl8168_driver_stop(tp); |
|
6074 } |
|
6075 |
|
6076 cancel_work_sync(&tp->wk.work); |
|
6077 |
|
6078 if (tp->ecdev) { |
|
6079 ecdev_close(tp->ecdev); |
|
6080 ecdev_withdraw(tp->ecdev); |
|
6081 } else { |
|
6082 netif_napi_del(&tp->napi); |
|
6083 |
|
6084 unregister_netdev(dev); |
|
6085 } |
|
6086 |
|
6087 rtl_release_firmware(tp); |
|
6088 |
|
6089 if (pci_dev_run_wake(pdev)) |
|
6090 pm_runtime_get_noresume(&pdev->dev); |
|
6091 |
|
6092 /* restore original MAC address */ |
|
6093 rtl_rar_set(tp, dev->perm_addr); |
|
6094 |
|
6095 rtl_disable_msi(pdev, tp); |
|
6096 rtl8169_release_board(pdev, dev, tp->mmio_addr); |
|
6097 pci_set_drvdata(pdev, NULL); |
|
6098 } |
|
6099 |
|
6100 static const struct net_device_ops rtl_netdev_ops = { |
|
6101 .ndo_open = rtl_open, |
|
6102 .ndo_stop = rtl8169_close, |
|
6103 .ndo_get_stats64 = rtl8169_get_stats64, |
|
6104 .ndo_start_xmit = rtl8169_start_xmit, |
|
6105 .ndo_tx_timeout = rtl8169_tx_timeout, |
|
6106 .ndo_validate_addr = eth_validate_addr, |
|
6107 .ndo_change_mtu = rtl8169_change_mtu, |
|
6108 .ndo_fix_features = rtl8169_fix_features, |
|
6109 .ndo_set_features = rtl8169_set_features, |
|
6110 .ndo_set_mac_address = rtl_set_mac_address, |
|
6111 .ndo_do_ioctl = rtl8169_ioctl, |
|
6112 .ndo_set_rx_mode = rtl_set_rx_mode, |
|
6113 #ifdef CONFIG_NET_POLL_CONTROLLER |
|
6114 .ndo_poll_controller = rtl8169_netpoll, |
|
6115 #endif |
|
6116 |
|
6117 }; |
|
6118 |
|
6119 static const struct rtl_cfg_info { |
|
6120 void (*hw_start)(struct net_device *); |
|
6121 unsigned int region; |
|
6122 unsigned int align; |
|
6123 u16 event_slow; |
|
6124 unsigned features; |
|
6125 u8 default_ver; |
|
6126 } rtl_cfg_infos [] = { |
|
6127 [RTL_CFG_0] = { |
|
6128 .hw_start = rtl_hw_start_8169, |
|
6129 .region = 1, |
|
6130 .align = 0, |
|
6131 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, |
|
6132 .features = RTL_FEATURE_GMII, |
|
6133 .default_ver = RTL_GIGA_MAC_VER_01, |
|
6134 }, |
|
6135 [RTL_CFG_1] = { |
|
6136 .hw_start = rtl_hw_start_8168, |
|
6137 .region = 2, |
|
6138 .align = 8, |
|
6139 .event_slow = SYSErr | LinkChg | RxOverflow, |
|
6140 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
|
6141 .default_ver = RTL_GIGA_MAC_VER_11, |
|
6142 }, |
|
6143 [RTL_CFG_2] = { |
|
6144 .hw_start = rtl_hw_start_8101, |
|
6145 .region = 2, |
|
6146 .align = 8, |
|
6147 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | |
|
6148 PCSTimeout, |
|
6149 .features = RTL_FEATURE_MSI, |
|
6150 .default_ver = RTL_GIGA_MAC_VER_13, |
|
6151 } |
|
6152 }; |
|
6153 |
|
6154 /* Cfg9346_Unlock assumed. */ |
|
6155 static unsigned rtl_try_msi(struct rtl8169_private *tp, |
|
6156 const struct rtl_cfg_info *cfg) |
|
6157 { |
|
6158 void __iomem *ioaddr = tp->mmio_addr; |
|
6159 unsigned msi = 0; |
|
6160 u8 cfg2; |
|
6161 |
|
6162 cfg2 = RTL_R8(Config2) & ~MSIEnable; |
|
6163 if (cfg->features & RTL_FEATURE_MSI) { |
|
6164 if (pci_enable_msi(tp->pci_dev)) { |
|
6165 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); |
|
6166 } else { |
|
6167 cfg2 |= MSIEnable; |
|
6168 msi = RTL_FEATURE_MSI; |
|
6169 } |
|
6170 } |
|
6171 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) |
|
6172 RTL_W8(Config2, cfg2); |
|
6173 return msi; |
|
6174 } |
|
6175 |
|
6176 static int __devinit |
|
6177 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
6178 { |
|
6179 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
|
6180 const unsigned int region = cfg->region; |
|
6181 struct rtl8169_private *tp; |
|
6182 struct mii_if_info *mii; |
|
6183 struct net_device *dev; |
|
6184 void __iomem *ioaddr; |
|
6185 int chipset, i; |
|
6186 int rc; |
|
6187 |
|
6188 if (netif_msg_drv(&debug)) { |
|
6189 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", |
|
6190 MODULENAME, RTL8169_VERSION); |
|
6191 } |
|
6192 |
|
6193 dev = alloc_etherdev(sizeof (*tp)); |
|
6194 if (!dev) { |
|
6195 rc = -ENOMEM; |
|
6196 goto out; |
|
6197 } |
|
6198 |
|
6199 SET_NETDEV_DEV(dev, &pdev->dev); |
|
6200 dev->netdev_ops = &rtl_netdev_ops; |
|
6201 tp = netdev_priv(dev); |
|
6202 tp->dev = dev; |
|
6203 tp->pci_dev = pdev; |
|
6204 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
|
6205 |
|
6206 mii = &tp->mii; |
|
6207 mii->dev = dev; |
|
6208 mii->mdio_read = rtl_mdio_read; |
|
6209 mii->mdio_write = rtl_mdio_write; |
|
6210 mii->phy_id_mask = 0x1f; |
|
6211 mii->reg_num_mask = 0x1f; |
|
6212 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); |
|
6213 |
|
6214 /* disable ASPM completely as that cause random device stop working |
|
6215 * problems as well as full system hangs for some PCIe devices users */ |
|
6216 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
|
6217 PCIE_LINK_STATE_CLKPM); |
|
6218 |
|
6219 /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
|
6220 rc = pci_enable_device(pdev); |
|
6221 if (rc < 0) { |
|
6222 netif_err(tp, probe, dev, "enable failure\n"); |
|
6223 goto err_out_free_dev_1; |
|
6224 } |
|
6225 |
|
6226 if (pci_set_mwi(pdev) < 0) |
|
6227 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); |
|
6228 |
|
6229 /* make sure PCI base addr 1 is MMIO */ |
|
6230 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
|
6231 netif_err(tp, probe, dev, |
|
6232 "region #%d not an MMIO resource, aborting\n", |
|
6233 region); |
|
6234 rc = -ENODEV; |
|
6235 goto err_out_mwi_2; |
|
6236 } |
|
6237 |
|
6238 /* check for weird/broken PCI region reporting */ |
|
6239 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
|
6240 netif_err(tp, probe, dev, |
|
6241 "Invalid PCI region size(s), aborting\n"); |
|
6242 rc = -ENODEV; |
|
6243 goto err_out_mwi_2; |
|
6244 } |
|
6245 |
|
6246 rc = pci_request_regions(pdev, MODULENAME); |
|
6247 if (rc < 0) { |
|
6248 netif_err(tp, probe, dev, "could not request regions\n"); |
|
6249 goto err_out_mwi_2; |
|
6250 } |
|
6251 |
|
6252 tp->cp_cmd = RxChkSum; |
|
6253 |
|
6254 if ((sizeof(dma_addr_t) > 4) && |
|
6255 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
|
6256 tp->cp_cmd |= PCIDAC; |
|
6257 dev->features |= NETIF_F_HIGHDMA; |
|
6258 } else { |
|
6259 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
6260 if (rc < 0) { |
|
6261 netif_err(tp, probe, dev, "DMA configuration failed\n"); |
|
6262 goto err_out_free_res_3; |
|
6263 } |
|
6264 } |
|
6265 |
|
6266 /* ioremap MMIO region */ |
|
6267 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
|
6268 if (!ioaddr) { |
|
6269 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
|
6270 rc = -EIO; |
|
6271 goto err_out_free_res_3; |
|
6272 } |
|
6273 tp->mmio_addr = ioaddr; |
|
6274 |
|
6275 if (!pci_is_pcie(pdev)) |
|
6276 netif_info(tp, probe, dev, "not PCI Express\n"); |
|
6277 |
|
6278 /* Identify chip attached to board */ |
|
6279 rtl8169_get_mac_version(tp, dev, cfg->default_ver); |
|
6280 |
|
6281 rtl_init_rxcfg(tp); |
|
6282 |
|
6283 rtl_irq_disable(tp); |
|
6284 |
|
6285 rtl_hw_reset(tp); |
|
6286 |
|
6287 rtl_ack_events(tp, 0xffff); |
|
6288 |
|
6289 pci_set_master(pdev); |
|
6290 |
|
6291 /* |
|
6292 * Pretend we are using VLANs; This bypasses a nasty bug where |
|
6293 * Interrupts stop flowing on high load on 8110SCd controllers. |
|
6294 */ |
|
6295 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6296 tp->cp_cmd |= RxVlan; |
|
6297 |
|
6298 rtl_init_mdio_ops(tp); |
|
6299 rtl_init_pll_power_ops(tp); |
|
6300 rtl_init_jumbo_ops(tp); |
|
6301 |
|
6302 rtl8169_print_mac_version(tp); |
|
6303 |
|
6304 chipset = tp->mac_version; |
|
6305 tp->txd_version = rtl_chip_infos[chipset].txd_version; |
|
6306 |
|
6307 RTL_W8(Cfg9346, Cfg9346_Unlock); |
|
6308 RTL_W8(Config1, RTL_R8(Config1) | PMEnable); |
|
6309 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); |
|
6310 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
|
6311 tp->features |= RTL_FEATURE_WOL; |
|
6312 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
|
6313 tp->features |= RTL_FEATURE_WOL; |
|
6314 tp->features |= rtl_try_msi(tp, cfg); |
|
6315 RTL_W8(Cfg9346, Cfg9346_Lock); |
|
6316 |
|
6317 if (rtl_tbi_enabled(tp)) { |
|
6318 tp->set_speed = rtl8169_set_speed_tbi; |
|
6319 tp->get_settings = rtl8169_gset_tbi; |
|
6320 tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
|
6321 tp->phy_reset_pending = rtl8169_tbi_reset_pending; |
|
6322 tp->link_ok = rtl8169_tbi_link_ok; |
|
6323 tp->do_ioctl = rtl_tbi_ioctl; |
|
6324 } else { |
|
6325 tp->set_speed = rtl8169_set_speed_xmii; |
|
6326 tp->get_settings = rtl8169_gset_xmii; |
|
6327 tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
|
6328 tp->phy_reset_pending = rtl8169_xmii_reset_pending; |
|
6329 tp->link_ok = rtl8169_xmii_link_ok; |
|
6330 tp->do_ioctl = rtl_xmii_ioctl; |
|
6331 } |
|
6332 |
|
6333 mutex_init(&tp->wk.mutex); |
|
6334 |
|
6335 /* Get MAC address */ |
|
6336 for (i = 0; i < ETH_ALEN; i++) |
|
6337 dev->dev_addr[i] = RTL_R8(MAC0 + i); |
|
6338 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
|
6339 |
|
6340 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
|
6341 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
|
6342 |
|
6343 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
|
6344 |
|
6345 /* don't enable SG, IP_CSUM and TSO by default - it might not work |
|
6346 * properly for all devices */ |
|
6347 dev->features |= NETIF_F_RXCSUM | |
|
6348 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6349 |
|
6350 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6351 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
|
6352 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
|
6353 NETIF_F_HIGHDMA; |
|
6354 |
|
6355 if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
|
6356 /* 8110SCd requires hardware Rx VLAN - disallow toggling */ |
|
6357 dev->hw_features &= ~NETIF_F_HW_VLAN_RX; |
|
6358 |
|
6359 dev->hw_features |= NETIF_F_RXALL; |
|
6360 dev->hw_features |= NETIF_F_RXFCS; |
|
6361 |
|
6362 tp->hw_start = cfg->hw_start; |
|
6363 tp->event_slow = cfg->event_slow; |
|
6364 |
|
6365 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
|
6366 ~(RxBOVF | RxFOVF) : ~0; |
|
6367 |
|
6368 init_timer(&tp->timer); |
|
6369 tp->timer.data = (unsigned long) dev; |
|
6370 tp->timer.function = rtl8169_phy_timer; |
|
6371 |
|
6372 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
|
6373 |
|
6374 // offer device to EtherCAT master module |
|
6375 tp->ecdev = ecdev_offer(dev, ec_poll, THIS_MODULE); |
|
6376 tp->ec_watchdog_jiffies = jiffies; |
|
6377 |
|
6378 if (!tp->ecdev) { |
|
6379 rc = register_netdev(dev); |
|
6380 if (rc < 0) |
|
6381 goto err_out_msi_4; |
|
6382 } |
|
6383 |
|
6384 pci_set_drvdata(pdev, dev); |
|
6385 |
|
6386 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
|
6387 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, |
|
6388 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); |
|
6389 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
|
6390 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " |
|
6391 "tx checksumming: %s]\n", |
|
6392 rtl_chip_infos[chipset].jumbo_max, |
|
6393 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); |
|
6394 } |
|
6395 |
|
6396 if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
|
6397 tp->mac_version == RTL_GIGA_MAC_VER_28 || |
|
6398 tp->mac_version == RTL_GIGA_MAC_VER_31) { |
|
6399 rtl8168_driver_start(tp); |
|
6400 } |
|
6401 |
|
6402 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
|
6403 |
|
6404 if (pci_dev_run_wake(pdev)) |
|
6405 pm_runtime_put_noidle(&pdev->dev); |
|
6406 |
|
6407 if (tp->ecdev) { |
|
6408 rc = ecdev_open(tp->ecdev); |
|
6409 if (rc) { |
|
6410 ecdev_withdraw(tp->ecdev); |
|
6411 goto err_out_msi_4; |
|
6412 } |
|
6413 } |
|
6414 else { |
|
6415 netif_carrier_off(dev); |
|
6416 } |
|
6417 |
|
6418 out: |
|
6419 return rc; |
|
6420 |
|
6421 err_out_msi_4: |
|
6422 netif_napi_del(&tp->napi); |
|
6423 rtl_disable_msi(pdev, tp); |
|
6424 iounmap(ioaddr); |
|
6425 err_out_free_res_3: |
|
6426 pci_release_regions(pdev); |
|
6427 err_out_mwi_2: |
|
6428 pci_clear_mwi(pdev); |
|
6429 pci_disable_device(pdev); |
|
6430 err_out_free_dev_1: |
|
6431 free_netdev(dev); |
|
6432 goto out; |
|
6433 } |
|
6434 |
|
6435 static struct pci_driver rtl8169_pci_driver = { |
|
6436 .name = MODULENAME, |
|
6437 .id_table = rtl8169_pci_tbl, |
|
6438 .probe = rtl_init_one, |
|
6439 .remove = __devexit_p(rtl_remove_one), |
|
6440 .shutdown = rtl_shutdown, |
|
6441 .driver.pm = RTL8169_PM_OPS, |
|
6442 }; |
|
6443 |
|
6444 static int __init rtl8169_init_module(void) |
|
6445 { |
|
6446 return pci_register_driver(&rtl8169_pci_driver); |
|
6447 } |
|
6448 |
|
6449 static void __exit rtl8169_cleanup_module(void) |
|
6450 { |
|
6451 pci_unregister_driver(&rtl8169_pci_driver); |
|
6452 } |
|
6453 |
|
6454 module_init(rtl8169_init_module); |
|
6455 module_exit(rtl8169_cleanup_module); |