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1 /******************************************************************************* |
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2 |
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3 Intel PRO/1000 Linux driver |
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4 Copyright(c) 1999 - 2012 Intel Corporation. |
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5 |
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6 This program is free software; you can redistribute it and/or modify it |
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7 under the terms and conditions of the GNU General Public License, |
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8 version 2, as published by the Free Software Foundation. |
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9 |
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10 This program is distributed in the hope it will be useful, but WITHOUT |
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11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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13 more details. |
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14 |
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15 You should have received a copy of the GNU General Public License along with |
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16 this program; if not, write to the Free Software Foundation, Inc., |
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17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
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18 |
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19 The full GNU General Public License is included in this distribution in |
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20 the file called "COPYING". |
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21 |
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22 Contact Information: |
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23 Linux NICS <linux.nics@intel.com> |
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24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
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25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
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26 |
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27 *******************************************************************************/ |
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28 |
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29 #include "e1000-3.8-ethercat.h" |
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30 |
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31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); |
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32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
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33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); |
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34 static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
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35 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
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36 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
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37 u16 *data, bool read, bool page_set); |
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38 static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
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39 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
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40 u16 *data, bool read); |
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41 |
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42 /* Cable length tables */ |
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43 static const u16 e1000_m88_cable_length_table[] = { |
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44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; |
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45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
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46 ARRAY_SIZE(e1000_m88_cable_length_table) |
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47 |
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48 static const u16 e1000_igp_2_cable_length_table[] = { |
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49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, |
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50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, |
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51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, |
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52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, |
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53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, |
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54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, |
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55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, |
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56 124}; |
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57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
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58 ARRAY_SIZE(e1000_igp_2_cable_length_table) |
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59 |
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60 #define BM_PHY_REG_PAGE(offset) \ |
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61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
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62 #define BM_PHY_REG_NUM(offset) \ |
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63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ |
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64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ |
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65 ~MAX_PHY_REG_ADDRESS))) |
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66 |
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67 #define HV_INTC_FC_PAGE_START 768 |
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68 #define I82578_ADDR_REG 29 |
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69 #define I82577_ADDR_REG 16 |
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70 #define I82577_CFG_REG 22 |
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71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
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72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ |
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73 #define I82577_CTRL_REG 23 |
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74 |
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75 /* 82577 specific PHY registers */ |
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76 #define I82577_PHY_CTRL_2 18 |
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77 #define I82577_PHY_STATUS_2 26 |
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78 #define I82577_PHY_DIAG_STATUS 31 |
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79 |
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80 /* I82577 PHY Status 2 */ |
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81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
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82 #define I82577_PHY_STATUS2_MDIX 0x0800 |
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83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
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84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
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85 |
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86 /* I82577 PHY Control 2 */ |
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87 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 |
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88 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 |
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89 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
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90 |
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91 /* I82577 PHY Diagnostics Status */ |
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92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
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93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
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94 |
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95 /* BM PHY Copper Specific Control 1 */ |
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96 #define BM_CS_CTRL1 16 |
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97 |
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98 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
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99 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 |
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100 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 |
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101 |
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102 /** |
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103 * e1000e_check_reset_block_generic - Check if PHY reset is blocked |
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104 * @hw: pointer to the HW structure |
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105 * |
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106 * Read the PHY management control register and check whether a PHY reset |
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107 * is blocked. If a reset is not blocked return 0, otherwise |
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108 * return E1000_BLK_PHY_RESET (12). |
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109 **/ |
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110 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) |
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111 { |
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112 u32 manc; |
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113 |
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114 manc = er32(MANC); |
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115 |
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116 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
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117 E1000_BLK_PHY_RESET : 0; |
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118 } |
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119 |
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120 /** |
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121 * e1000e_get_phy_id - Retrieve the PHY ID and revision |
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122 * @hw: pointer to the HW structure |
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123 * |
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124 * Reads the PHY registers and stores the PHY ID and possibly the PHY |
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125 * revision in the hardware structure. |
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126 **/ |
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127 s32 e1000e_get_phy_id(struct e1000_hw *hw) |
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128 { |
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129 struct e1000_phy_info *phy = &hw->phy; |
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130 s32 ret_val = 0; |
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131 u16 phy_id; |
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132 u16 retry_count = 0; |
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133 |
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134 if (!phy->ops.read_reg) |
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135 return 0; |
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136 |
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137 while (retry_count < 2) { |
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138 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
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139 if (ret_val) |
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140 return ret_val; |
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141 |
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142 phy->id = (u32)(phy_id << 16); |
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143 udelay(20); |
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144 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); |
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145 if (ret_val) |
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146 return ret_val; |
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147 |
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148 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
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149 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
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150 |
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151 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
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152 return 0; |
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153 |
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154 retry_count++; |
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155 } |
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156 |
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157 return 0; |
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158 } |
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159 |
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160 /** |
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161 * e1000e_phy_reset_dsp - Reset PHY DSP |
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162 * @hw: pointer to the HW structure |
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163 * |
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164 * Reset the digital signal processor. |
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165 **/ |
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166 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) |
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167 { |
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168 s32 ret_val; |
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169 |
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170 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
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171 if (ret_val) |
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172 return ret_val; |
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173 |
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174 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); |
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175 } |
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176 |
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177 /** |
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178 * e1000e_read_phy_reg_mdic - Read MDI control register |
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179 * @hw: pointer to the HW structure |
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180 * @offset: register offset to be read |
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181 * @data: pointer to the read data |
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182 * |
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183 * Reads the MDI control register in the PHY at offset and stores the |
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184 * information read to data. |
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185 **/ |
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186 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
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187 { |
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188 struct e1000_phy_info *phy = &hw->phy; |
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189 u32 i, mdic = 0; |
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190 |
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191 if (offset > MAX_PHY_REG_ADDRESS) { |
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192 e_dbg("PHY Address %d is out of range\n", offset); |
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193 return -E1000_ERR_PARAM; |
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194 } |
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195 |
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196 /* Set up Op-code, Phy Address, and register offset in the MDI |
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197 * Control register. The MAC will take care of interfacing with the |
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198 * PHY to retrieve the desired data. |
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199 */ |
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200 mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
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201 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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202 (E1000_MDIC_OP_READ)); |
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203 |
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204 ew32(MDIC, mdic); |
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205 |
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206 /* Poll the ready bit to see if the MDI read completed |
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207 * Increasing the time out as testing showed failures with |
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208 * the lower time out |
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209 */ |
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210 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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211 udelay(50); |
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212 mdic = er32(MDIC); |
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213 if (mdic & E1000_MDIC_READY) |
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214 break; |
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215 } |
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216 if (!(mdic & E1000_MDIC_READY)) { |
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217 e_dbg("MDI Read did not complete\n"); |
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218 return -E1000_ERR_PHY; |
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219 } |
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220 if (mdic & E1000_MDIC_ERROR) { |
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221 e_dbg("MDI Error\n"); |
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222 return -E1000_ERR_PHY; |
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223 } |
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224 *data = (u16) mdic; |
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225 |
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226 /* Allow some time after each MDIC transaction to avoid |
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227 * reading duplicate data in the next MDIC transaction. |
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228 */ |
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229 if (hw->mac.type == e1000_pch2lan) |
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230 udelay(100); |
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231 |
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232 return 0; |
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233 } |
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234 |
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235 /** |
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236 * e1000e_write_phy_reg_mdic - Write MDI control register |
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237 * @hw: pointer to the HW structure |
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238 * @offset: register offset to write to |
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239 * @data: data to write to register at offset |
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240 * |
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241 * Writes data to MDI control register in the PHY at offset. |
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242 **/ |
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243 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
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244 { |
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245 struct e1000_phy_info *phy = &hw->phy; |
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246 u32 i, mdic = 0; |
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247 |
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248 if (offset > MAX_PHY_REG_ADDRESS) { |
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249 e_dbg("PHY Address %d is out of range\n", offset); |
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250 return -E1000_ERR_PARAM; |
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251 } |
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252 |
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253 /* Set up Op-code, Phy Address, and register offset in the MDI |
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254 * Control register. The MAC will take care of interfacing with the |
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255 * PHY to retrieve the desired data. |
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256 */ |
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257 mdic = (((u32)data) | |
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258 (offset << E1000_MDIC_REG_SHIFT) | |
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259 (phy->addr << E1000_MDIC_PHY_SHIFT) | |
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260 (E1000_MDIC_OP_WRITE)); |
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261 |
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262 ew32(MDIC, mdic); |
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263 |
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264 /* Poll the ready bit to see if the MDI read completed |
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265 * Increasing the time out as testing showed failures with |
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266 * the lower time out |
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267 */ |
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268 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
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269 udelay(50); |
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270 mdic = er32(MDIC); |
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271 if (mdic & E1000_MDIC_READY) |
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272 break; |
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273 } |
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274 if (!(mdic & E1000_MDIC_READY)) { |
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275 e_dbg("MDI Write did not complete\n"); |
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276 return -E1000_ERR_PHY; |
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277 } |
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278 if (mdic & E1000_MDIC_ERROR) { |
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279 e_dbg("MDI Error\n"); |
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280 return -E1000_ERR_PHY; |
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281 } |
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282 |
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283 /* Allow some time after each MDIC transaction to avoid |
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284 * reading duplicate data in the next MDIC transaction. |
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285 */ |
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286 if (hw->mac.type == e1000_pch2lan) |
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287 udelay(100); |
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288 |
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289 return 0; |
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290 } |
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291 |
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292 /** |
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293 * e1000e_read_phy_reg_m88 - Read m88 PHY register |
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294 * @hw: pointer to the HW structure |
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295 * @offset: register offset to be read |
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296 * @data: pointer to the read data |
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297 * |
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298 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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299 * and storing the retrieved information in data. Release any acquired |
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300 * semaphores before exiting. |
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301 **/ |
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302 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) |
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303 { |
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304 s32 ret_val; |
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305 |
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306 ret_val = hw->phy.ops.acquire(hw); |
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307 if (ret_val) |
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308 return ret_val; |
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309 |
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310 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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311 data); |
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312 |
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313 hw->phy.ops.release(hw); |
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314 |
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315 return ret_val; |
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316 } |
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317 |
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318 /** |
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319 * e1000e_write_phy_reg_m88 - Write m88 PHY register |
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320 * @hw: pointer to the HW structure |
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321 * @offset: register offset to write to |
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322 * @data: data to write at register offset |
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323 * |
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324 * Acquires semaphore, if necessary, then writes the data to PHY register |
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325 * at the offset. Release any acquired semaphores before exiting. |
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326 **/ |
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327 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) |
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328 { |
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329 s32 ret_val; |
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330 |
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331 ret_val = hw->phy.ops.acquire(hw); |
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332 if (ret_val) |
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333 return ret_val; |
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334 |
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335 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
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336 data); |
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337 |
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338 hw->phy.ops.release(hw); |
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339 |
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340 return ret_val; |
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341 } |
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342 |
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343 /** |
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344 * e1000_set_page_igp - Set page as on IGP-like PHY(s) |
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345 * @hw: pointer to the HW structure |
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346 * @page: page to set (shifted left when necessary) |
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347 * |
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348 * Sets PHY page required for PHY register access. Assumes semaphore is |
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349 * already acquired. Note, this function sets phy.addr to 1 so the caller |
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350 * must set it appropriately (if necessary) after this function returns. |
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351 **/ |
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352 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) |
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353 { |
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354 e_dbg("Setting page 0x%x\n", page); |
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355 |
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356 hw->phy.addr = 1; |
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357 |
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358 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); |
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359 } |
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360 |
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361 /** |
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362 * __e1000e_read_phy_reg_igp - Read igp PHY register |
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363 * @hw: pointer to the HW structure |
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364 * @offset: register offset to be read |
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365 * @data: pointer to the read data |
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366 * @locked: semaphore has already been acquired or not |
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367 * |
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368 * Acquires semaphore, if necessary, then reads the PHY register at offset |
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369 * and stores the retrieved information in data. Release any acquired |
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370 * semaphores before exiting. |
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371 **/ |
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372 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
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373 bool locked) |
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374 { |
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375 s32 ret_val = 0; |
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376 |
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377 if (!locked) { |
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378 if (!hw->phy.ops.acquire) |
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379 return 0; |
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380 |
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381 ret_val = hw->phy.ops.acquire(hw); |
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382 if (ret_val) |
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383 return ret_val; |
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384 } |
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385 |
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386 if (offset > MAX_PHY_MULTI_PAGE_REG) |
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387 ret_val = e1000e_write_phy_reg_mdic(hw, |
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388 IGP01E1000_PHY_PAGE_SELECT, |
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389 (u16)offset); |
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390 if (!ret_val) |
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391 ret_val = e1000e_read_phy_reg_mdic(hw, |
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392 MAX_PHY_REG_ADDRESS & offset, |
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393 data); |
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394 if (!locked) |
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395 hw->phy.ops.release(hw); |
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396 |
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397 return ret_val; |
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398 } |
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399 |
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400 /** |
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401 * e1000e_read_phy_reg_igp - Read igp PHY register |
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402 * @hw: pointer to the HW structure |
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403 * @offset: register offset to be read |
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404 * @data: pointer to the read data |
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405 * |
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406 * Acquires semaphore then reads the PHY register at offset and stores the |
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407 * retrieved information in data. |
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408 * Release the acquired semaphore before exiting. |
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409 **/ |
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410 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
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411 { |
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412 return __e1000e_read_phy_reg_igp(hw, offset, data, false); |
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413 } |
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414 |
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415 /** |
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416 * e1000e_read_phy_reg_igp_locked - Read igp PHY register |
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417 * @hw: pointer to the HW structure |
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418 * @offset: register offset to be read |
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419 * @data: pointer to the read data |
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420 * |
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421 * Reads the PHY register at offset and stores the retrieved information |
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422 * in data. Assumes semaphore already acquired. |
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423 **/ |
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424 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
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425 { |
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426 return __e1000e_read_phy_reg_igp(hw, offset, data, true); |
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427 } |
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428 |
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429 /** |
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430 * e1000e_write_phy_reg_igp - Write igp PHY register |
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431 * @hw: pointer to the HW structure |
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432 * @offset: register offset to write to |
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433 * @data: data to write at register offset |
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434 * @locked: semaphore has already been acquired or not |
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435 * |
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436 * Acquires semaphore, if necessary, then writes the data to PHY register |
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437 * at the offset. Release any acquired semaphores before exiting. |
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438 **/ |
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439 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
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440 bool locked) |
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441 { |
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442 s32 ret_val = 0; |
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443 |
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444 if (!locked) { |
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445 if (!hw->phy.ops.acquire) |
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446 return 0; |
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447 |
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448 ret_val = hw->phy.ops.acquire(hw); |
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449 if (ret_val) |
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450 return ret_val; |
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451 } |
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452 |
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453 if (offset > MAX_PHY_MULTI_PAGE_REG) |
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454 ret_val = e1000e_write_phy_reg_mdic(hw, |
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455 IGP01E1000_PHY_PAGE_SELECT, |
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456 (u16)offset); |
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457 if (!ret_val) |
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458 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & |
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459 offset, |
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460 data); |
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461 if (!locked) |
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462 hw->phy.ops.release(hw); |
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463 |
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464 return ret_val; |
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465 } |
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466 |
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467 /** |
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468 * e1000e_write_phy_reg_igp - Write igp PHY register |
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469 * @hw: pointer to the HW structure |
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470 * @offset: register offset to write to |
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471 * @data: data to write at register offset |
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472 * |
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473 * Acquires semaphore then writes the data to PHY register |
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474 * at the offset. Release any acquired semaphores before exiting. |
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475 **/ |
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476 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
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477 { |
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478 return __e1000e_write_phy_reg_igp(hw, offset, data, false); |
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479 } |
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480 |
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481 /** |
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482 * e1000e_write_phy_reg_igp_locked - Write igp PHY register |
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483 * @hw: pointer to the HW structure |
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484 * @offset: register offset to write to |
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485 * @data: data to write at register offset |
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486 * |
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487 * Writes the data to PHY register at the offset. |
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488 * Assumes semaphore already acquired. |
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489 **/ |
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490 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) |
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491 { |
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492 return __e1000e_write_phy_reg_igp(hw, offset, data, true); |
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493 } |
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494 |
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495 /** |
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496 * __e1000_read_kmrn_reg - Read kumeran register |
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497 * @hw: pointer to the HW structure |
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498 * @offset: register offset to be read |
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499 * @data: pointer to the read data |
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500 * @locked: semaphore has already been acquired or not |
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501 * |
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502 * Acquires semaphore, if necessary. Then reads the PHY register at offset |
|
503 * using the kumeran interface. The information retrieved is stored in data. |
|
504 * Release any acquired semaphores before exiting. |
|
505 **/ |
|
506 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
|
507 bool locked) |
|
508 { |
|
509 u32 kmrnctrlsta; |
|
510 |
|
511 if (!locked) { |
|
512 s32 ret_val = 0; |
|
513 |
|
514 if (!hw->phy.ops.acquire) |
|
515 return 0; |
|
516 |
|
517 ret_val = hw->phy.ops.acquire(hw); |
|
518 if (ret_val) |
|
519 return ret_val; |
|
520 } |
|
521 |
|
522 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
523 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
|
524 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
525 e1e_flush(); |
|
526 |
|
527 udelay(2); |
|
528 |
|
529 kmrnctrlsta = er32(KMRNCTRLSTA); |
|
530 *data = (u16)kmrnctrlsta; |
|
531 |
|
532 if (!locked) |
|
533 hw->phy.ops.release(hw); |
|
534 |
|
535 return 0; |
|
536 } |
|
537 |
|
538 /** |
|
539 * e1000e_read_kmrn_reg - Read kumeran register |
|
540 * @hw: pointer to the HW structure |
|
541 * @offset: register offset to be read |
|
542 * @data: pointer to the read data |
|
543 * |
|
544 * Acquires semaphore then reads the PHY register at offset using the |
|
545 * kumeran interface. The information retrieved is stored in data. |
|
546 * Release the acquired semaphore before exiting. |
|
547 **/ |
|
548 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
|
549 { |
|
550 return __e1000_read_kmrn_reg(hw, offset, data, false); |
|
551 } |
|
552 |
|
553 /** |
|
554 * e1000e_read_kmrn_reg_locked - Read kumeran register |
|
555 * @hw: pointer to the HW structure |
|
556 * @offset: register offset to be read |
|
557 * @data: pointer to the read data |
|
558 * |
|
559 * Reads the PHY register at offset using the kumeran interface. The |
|
560 * information retrieved is stored in data. |
|
561 * Assumes semaphore already acquired. |
|
562 **/ |
|
563 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
564 { |
|
565 return __e1000_read_kmrn_reg(hw, offset, data, true); |
|
566 } |
|
567 |
|
568 /** |
|
569 * __e1000_write_kmrn_reg - Write kumeran register |
|
570 * @hw: pointer to the HW structure |
|
571 * @offset: register offset to write to |
|
572 * @data: data to write at register offset |
|
573 * @locked: semaphore has already been acquired or not |
|
574 * |
|
575 * Acquires semaphore, if necessary. Then write the data to PHY register |
|
576 * at the offset using the kumeran interface. Release any acquired semaphores |
|
577 * before exiting. |
|
578 **/ |
|
579 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
|
580 bool locked) |
|
581 { |
|
582 u32 kmrnctrlsta; |
|
583 |
|
584 if (!locked) { |
|
585 s32 ret_val = 0; |
|
586 |
|
587 if (!hw->phy.ops.acquire) |
|
588 return 0; |
|
589 |
|
590 ret_val = hw->phy.ops.acquire(hw); |
|
591 if (ret_val) |
|
592 return ret_val; |
|
593 } |
|
594 |
|
595 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
|
596 E1000_KMRNCTRLSTA_OFFSET) | data; |
|
597 ew32(KMRNCTRLSTA, kmrnctrlsta); |
|
598 e1e_flush(); |
|
599 |
|
600 udelay(2); |
|
601 |
|
602 if (!locked) |
|
603 hw->phy.ops.release(hw); |
|
604 |
|
605 return 0; |
|
606 } |
|
607 |
|
608 /** |
|
609 * e1000e_write_kmrn_reg - Write kumeran register |
|
610 * @hw: pointer to the HW structure |
|
611 * @offset: register offset to write to |
|
612 * @data: data to write at register offset |
|
613 * |
|
614 * Acquires semaphore then writes the data to the PHY register at the offset |
|
615 * using the kumeran interface. Release the acquired semaphore before exiting. |
|
616 **/ |
|
617 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) |
|
618 { |
|
619 return __e1000_write_kmrn_reg(hw, offset, data, false); |
|
620 } |
|
621 |
|
622 /** |
|
623 * e1000e_write_kmrn_reg_locked - Write kumeran register |
|
624 * @hw: pointer to the HW structure |
|
625 * @offset: register offset to write to |
|
626 * @data: data to write at register offset |
|
627 * |
|
628 * Write the data to PHY register at the offset using the kumeran interface. |
|
629 * Assumes semaphore already acquired. |
|
630 **/ |
|
631 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
632 { |
|
633 return __e1000_write_kmrn_reg(hw, offset, data, true); |
|
634 } |
|
635 |
|
636 /** |
|
637 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode |
|
638 * @hw: pointer to the HW structure |
|
639 * |
|
640 * Sets up Master/slave mode |
|
641 **/ |
|
642 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) |
|
643 { |
|
644 s32 ret_val; |
|
645 u16 phy_data; |
|
646 |
|
647 /* Resolve Master/Slave mode */ |
|
648 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data); |
|
649 if (ret_val) |
|
650 return ret_val; |
|
651 |
|
652 /* load defaults for future use */ |
|
653 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? |
|
654 ((phy_data & CR_1000T_MS_VALUE) ? |
|
655 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; |
|
656 |
|
657 switch (hw->phy.ms_type) { |
|
658 case e1000_ms_force_master: |
|
659 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
|
660 break; |
|
661 case e1000_ms_force_slave: |
|
662 phy_data |= CR_1000T_MS_ENABLE; |
|
663 phy_data &= ~(CR_1000T_MS_VALUE); |
|
664 break; |
|
665 case e1000_ms_auto: |
|
666 phy_data &= ~CR_1000T_MS_ENABLE; |
|
667 /* fall-through */ |
|
668 default: |
|
669 break; |
|
670 } |
|
671 |
|
672 return e1e_wphy(hw, PHY_1000T_CTRL, phy_data); |
|
673 } |
|
674 |
|
675 /** |
|
676 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link |
|
677 * @hw: pointer to the HW structure |
|
678 * |
|
679 * Sets up Carrier-sense on Transmit and downshift values. |
|
680 **/ |
|
681 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) |
|
682 { |
|
683 s32 ret_val; |
|
684 u16 phy_data; |
|
685 |
|
686 /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
|
687 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
|
688 if (ret_val) |
|
689 return ret_val; |
|
690 |
|
691 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
|
692 |
|
693 /* Enable downshift */ |
|
694 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
|
695 |
|
696 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); |
|
697 if (ret_val) |
|
698 return ret_val; |
|
699 |
|
700 /* Set MDI/MDIX mode */ |
|
701 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); |
|
702 if (ret_val) |
|
703 return ret_val; |
|
704 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; |
|
705 /* Options: |
|
706 * 0 - Auto (default) |
|
707 * 1 - MDI mode |
|
708 * 2 - MDI-X mode |
|
709 */ |
|
710 switch (hw->phy.mdix) { |
|
711 case 1: |
|
712 break; |
|
713 case 2: |
|
714 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; |
|
715 break; |
|
716 case 0: |
|
717 default: |
|
718 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; |
|
719 break; |
|
720 } |
|
721 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); |
|
722 if (ret_val) |
|
723 return ret_val; |
|
724 |
|
725 return e1000_set_master_slave_mode(hw); |
|
726 } |
|
727 |
|
728 /** |
|
729 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link |
|
730 * @hw: pointer to the HW structure |
|
731 * |
|
732 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
|
733 * and downshift values are set also. |
|
734 **/ |
|
735 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) |
|
736 { |
|
737 struct e1000_phy_info *phy = &hw->phy; |
|
738 s32 ret_val; |
|
739 u16 phy_data; |
|
740 |
|
741 /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
|
742 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
743 if (ret_val) |
|
744 return ret_val; |
|
745 |
|
746 /* For BM PHY this bit is downshift enable */ |
|
747 if (phy->type != e1000_phy_bm) |
|
748 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
749 |
|
750 /* Options: |
|
751 * MDI/MDI-X = 0 (default) |
|
752 * 0 - Auto for all speeds |
|
753 * 1 - MDI mode |
|
754 * 2 - MDI-X mode |
|
755 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
|
756 */ |
|
757 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
758 |
|
759 switch (phy->mdix) { |
|
760 case 1: |
|
761 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
|
762 break; |
|
763 case 2: |
|
764 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
|
765 break; |
|
766 case 3: |
|
767 phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
|
768 break; |
|
769 case 0: |
|
770 default: |
|
771 phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
|
772 break; |
|
773 } |
|
774 |
|
775 /* Options: |
|
776 * disable_polarity_correction = 0 (default) |
|
777 * Automatic Correction for Reversed Cable Polarity |
|
778 * 0 - Disabled |
|
779 * 1 - Enabled |
|
780 */ |
|
781 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
|
782 if (phy->disable_polarity_correction) |
|
783 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
|
784 |
|
785 /* Enable downshift on BM (disabled by default) */ |
|
786 if (phy->type == e1000_phy_bm) { |
|
787 /* For 82574/82583, first disable then enable downshift */ |
|
788 if (phy->id == BME1000_E_PHY_ID_R2) { |
|
789 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; |
|
790 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, |
|
791 phy_data); |
|
792 if (ret_val) |
|
793 return ret_val; |
|
794 /* Commit the changes. */ |
|
795 ret_val = e1000e_commit_phy(hw); |
|
796 if (ret_val) { |
|
797 e_dbg("Error committing the PHY changes\n"); |
|
798 return ret_val; |
|
799 } |
|
800 } |
|
801 |
|
802 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
|
803 } |
|
804 |
|
805 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
806 if (ret_val) |
|
807 return ret_val; |
|
808 |
|
809 if ((phy->type == e1000_phy_m88) && |
|
810 (phy->revision < E1000_REVISION_4) && |
|
811 (phy->id != BME1000_E_PHY_ID_R2)) { |
|
812 /* Force TX_CLK in the Extended PHY Specific Control Register |
|
813 * to 25MHz clock. |
|
814 */ |
|
815 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
816 if (ret_val) |
|
817 return ret_val; |
|
818 |
|
819 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
820 |
|
821 if ((phy->revision == 2) && |
|
822 (phy->id == M88E1111_I_PHY_ID)) { |
|
823 /* 82573L PHY - set the downshift counter to 5x. */ |
|
824 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
825 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
|
826 } else { |
|
827 /* Configure Master and Slave downshift values */ |
|
828 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
|
829 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
|
830 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
|
831 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
|
832 } |
|
833 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
834 if (ret_val) |
|
835 return ret_val; |
|
836 } |
|
837 |
|
838 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
|
839 /* Set PHY page 0, register 29 to 0x0003 */ |
|
840 ret_val = e1e_wphy(hw, 29, 0x0003); |
|
841 if (ret_val) |
|
842 return ret_val; |
|
843 |
|
844 /* Set PHY page 0, register 30 to 0x0000 */ |
|
845 ret_val = e1e_wphy(hw, 30, 0x0000); |
|
846 if (ret_val) |
|
847 return ret_val; |
|
848 } |
|
849 |
|
850 /* Commit the changes. */ |
|
851 ret_val = e1000e_commit_phy(hw); |
|
852 if (ret_val) { |
|
853 e_dbg("Error committing the PHY changes\n"); |
|
854 return ret_val; |
|
855 } |
|
856 |
|
857 if (phy->type == e1000_phy_82578) { |
|
858 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
859 if (ret_val) |
|
860 return ret_val; |
|
861 |
|
862 /* 82578 PHY - set the downshift count to 1x. */ |
|
863 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; |
|
864 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; |
|
865 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
866 if (ret_val) |
|
867 return ret_val; |
|
868 } |
|
869 |
|
870 return 0; |
|
871 } |
|
872 |
|
873 /** |
|
874 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link |
|
875 * @hw: pointer to the HW structure |
|
876 * |
|
877 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
|
878 * igp PHY's. |
|
879 **/ |
|
880 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) |
|
881 { |
|
882 struct e1000_phy_info *phy = &hw->phy; |
|
883 s32 ret_val; |
|
884 u16 data; |
|
885 |
|
886 ret_val = e1000_phy_hw_reset(hw); |
|
887 if (ret_val) { |
|
888 e_dbg("Error resetting the PHY.\n"); |
|
889 return ret_val; |
|
890 } |
|
891 |
|
892 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
|
893 * timeout issues when LFS is enabled. |
|
894 */ |
|
895 msleep(100); |
|
896 |
|
897 /* disable lplu d0 during driver init */ |
|
898 ret_val = e1000_set_d0_lplu_state(hw, false); |
|
899 if (ret_val) { |
|
900 e_dbg("Error Disabling LPLU D0\n"); |
|
901 return ret_val; |
|
902 } |
|
903 /* Configure mdi-mdix settings */ |
|
904 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
|
905 if (ret_val) |
|
906 return ret_val; |
|
907 |
|
908 data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
909 |
|
910 switch (phy->mdix) { |
|
911 case 1: |
|
912 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
913 break; |
|
914 case 2: |
|
915 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
916 break; |
|
917 case 0: |
|
918 default: |
|
919 data |= IGP01E1000_PSCR_AUTO_MDIX; |
|
920 break; |
|
921 } |
|
922 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); |
|
923 if (ret_val) |
|
924 return ret_val; |
|
925 |
|
926 /* set auto-master slave resolution settings */ |
|
927 if (hw->mac.autoneg) { |
|
928 /* when autonegotiation advertisement is only 1000Mbps then we |
|
929 * should disable SmartSpeed and enable Auto MasterSlave |
|
930 * resolution as hardware default. |
|
931 */ |
|
932 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
|
933 /* Disable SmartSpeed */ |
|
934 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
935 &data); |
|
936 if (ret_val) |
|
937 return ret_val; |
|
938 |
|
939 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
940 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
941 data); |
|
942 if (ret_val) |
|
943 return ret_val; |
|
944 |
|
945 /* Set auto Master/Slave resolution process */ |
|
946 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); |
|
947 if (ret_val) |
|
948 return ret_val; |
|
949 |
|
950 data &= ~CR_1000T_MS_ENABLE; |
|
951 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); |
|
952 if (ret_val) |
|
953 return ret_val; |
|
954 } |
|
955 |
|
956 ret_val = e1000_set_master_slave_mode(hw); |
|
957 } |
|
958 |
|
959 return ret_val; |
|
960 } |
|
961 |
|
962 /** |
|
963 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation |
|
964 * @hw: pointer to the HW structure |
|
965 * |
|
966 * Reads the MII auto-neg advertisement register and/or the 1000T control |
|
967 * register and if the PHY is already setup for auto-negotiation, then |
|
968 * return successful. Otherwise, setup advertisement and flow control to |
|
969 * the appropriate values for the wanted auto-negotiation. |
|
970 **/ |
|
971 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) |
|
972 { |
|
973 struct e1000_phy_info *phy = &hw->phy; |
|
974 s32 ret_val; |
|
975 u16 mii_autoneg_adv_reg; |
|
976 u16 mii_1000t_ctrl_reg = 0; |
|
977 |
|
978 phy->autoneg_advertised &= phy->autoneg_mask; |
|
979 |
|
980 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
|
981 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
|
982 if (ret_val) |
|
983 return ret_val; |
|
984 |
|
985 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
|
986 /* Read the MII 1000Base-T Control Register (Address 9). */ |
|
987 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
|
988 if (ret_val) |
|
989 return ret_val; |
|
990 } |
|
991 |
|
992 /* Need to parse both autoneg_advertised and fc and set up |
|
993 * the appropriate PHY registers. First we will parse for |
|
994 * autoneg_advertised software override. Since we can advertise |
|
995 * a plethora of combinations, we need to check each bit |
|
996 * individually. |
|
997 */ |
|
998 |
|
999 /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
|
1000 * Advertisement Register (Address 4) and the 1000 mb speed bits in |
|
1001 * the 1000Base-T Control Register (Address 9). |
|
1002 */ |
|
1003 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | |
|
1004 NWAY_AR_100TX_HD_CAPS | |
|
1005 NWAY_AR_10T_FD_CAPS | |
|
1006 NWAY_AR_10T_HD_CAPS); |
|
1007 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); |
|
1008 |
|
1009 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
|
1010 |
|
1011 /* Do we want to advertise 10 Mb Half Duplex? */ |
|
1012 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
|
1013 e_dbg("Advertise 10mb Half duplex\n"); |
|
1014 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
|
1015 } |
|
1016 |
|
1017 /* Do we want to advertise 10 Mb Full Duplex? */ |
|
1018 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
|
1019 e_dbg("Advertise 10mb Full duplex\n"); |
|
1020 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
|
1021 } |
|
1022 |
|
1023 /* Do we want to advertise 100 Mb Half Duplex? */ |
|
1024 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
|
1025 e_dbg("Advertise 100mb Half duplex\n"); |
|
1026 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
|
1027 } |
|
1028 |
|
1029 /* Do we want to advertise 100 Mb Full Duplex? */ |
|
1030 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
|
1031 e_dbg("Advertise 100mb Full duplex\n"); |
|
1032 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
|
1033 } |
|
1034 |
|
1035 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
|
1036 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
|
1037 e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
|
1038 |
|
1039 /* Do we want to advertise 1000 Mb Full Duplex? */ |
|
1040 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
|
1041 e_dbg("Advertise 1000mb Full duplex\n"); |
|
1042 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
|
1043 } |
|
1044 |
|
1045 /* Check for a software override of the flow control settings, and |
|
1046 * setup the PHY advertisement registers accordingly. If |
|
1047 * auto-negotiation is enabled, then software will have to set the |
|
1048 * "PAUSE" bits to the correct value in the Auto-Negotiation |
|
1049 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- |
|
1050 * negotiation. |
|
1051 * |
|
1052 * The possible values of the "fc" parameter are: |
|
1053 * 0: Flow control is completely disabled |
|
1054 * 1: Rx flow control is enabled (we can receive pause frames |
|
1055 * but not send pause frames). |
|
1056 * 2: Tx flow control is enabled (we can send pause frames |
|
1057 * but we do not support receiving pause frames). |
|
1058 * 3: Both Rx and Tx flow control (symmetric) are enabled. |
|
1059 * other: No software override. The flow control configuration |
|
1060 * in the EEPROM is used. |
|
1061 */ |
|
1062 switch (hw->fc.current_mode) { |
|
1063 case e1000_fc_none: |
|
1064 /* Flow control (Rx & Tx) is completely disabled by a |
|
1065 * software over-ride. |
|
1066 */ |
|
1067 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1068 break; |
|
1069 case e1000_fc_rx_pause: |
|
1070 /* Rx Flow control is enabled, and Tx Flow control is |
|
1071 * disabled, by a software over-ride. |
|
1072 * |
|
1073 * Since there really isn't a way to advertise that we are |
|
1074 * capable of Rx Pause ONLY, we will advertise that we |
|
1075 * support both symmetric and asymmetric Rx PAUSE. Later |
|
1076 * (in e1000e_config_fc_after_link_up) we will disable the |
|
1077 * hw's ability to send PAUSE frames. |
|
1078 */ |
|
1079 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1080 break; |
|
1081 case e1000_fc_tx_pause: |
|
1082 /* Tx Flow control is enabled, and Rx Flow control is |
|
1083 * disabled, by a software over-ride. |
|
1084 */ |
|
1085 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
|
1086 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
|
1087 break; |
|
1088 case e1000_fc_full: |
|
1089 /* Flow control (both Rx and Tx) is enabled by a software |
|
1090 * over-ride. |
|
1091 */ |
|
1092 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
|
1093 break; |
|
1094 default: |
|
1095 e_dbg("Flow control param set incorrectly\n"); |
|
1096 return -E1000_ERR_CONFIG; |
|
1097 } |
|
1098 |
|
1099 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
|
1100 if (ret_val) |
|
1101 return ret_val; |
|
1102 |
|
1103 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
|
1104 |
|
1105 if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
|
1106 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
|
1107 |
|
1108 return ret_val; |
|
1109 } |
|
1110 |
|
1111 /** |
|
1112 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link |
|
1113 * @hw: pointer to the HW structure |
|
1114 * |
|
1115 * Performs initial bounds checking on autoneg advertisement parameter, then |
|
1116 * configure to advertise the full capability. Setup the PHY to autoneg |
|
1117 * and restart the negotiation process between the link partner. If |
|
1118 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
|
1119 **/ |
|
1120 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) |
|
1121 { |
|
1122 struct e1000_phy_info *phy = &hw->phy; |
|
1123 s32 ret_val; |
|
1124 u16 phy_ctrl; |
|
1125 |
|
1126 /* Perform some bounds checking on the autoneg advertisement |
|
1127 * parameter. |
|
1128 */ |
|
1129 phy->autoneg_advertised &= phy->autoneg_mask; |
|
1130 |
|
1131 /* If autoneg_advertised is zero, we assume it was not defaulted |
|
1132 * by the calling code so we set to advertise full capability. |
|
1133 */ |
|
1134 if (!phy->autoneg_advertised) |
|
1135 phy->autoneg_advertised = phy->autoneg_mask; |
|
1136 |
|
1137 e_dbg("Reconfiguring auto-neg advertisement params\n"); |
|
1138 ret_val = e1000_phy_setup_autoneg(hw); |
|
1139 if (ret_val) { |
|
1140 e_dbg("Error Setting up Auto-Negotiation\n"); |
|
1141 return ret_val; |
|
1142 } |
|
1143 e_dbg("Restarting Auto-Neg\n"); |
|
1144 |
|
1145 /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
|
1146 * the Auto Neg Restart bit in the PHY control register. |
|
1147 */ |
|
1148 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); |
|
1149 if (ret_val) |
|
1150 return ret_val; |
|
1151 |
|
1152 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
|
1153 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); |
|
1154 if (ret_val) |
|
1155 return ret_val; |
|
1156 |
|
1157 /* Does the user want to wait for Auto-Neg to complete here, or |
|
1158 * check at a later time (for example, callback routine). |
|
1159 */ |
|
1160 if (phy->autoneg_wait_to_complete) { |
|
1161 ret_val = e1000_wait_autoneg(hw); |
|
1162 if (ret_val) { |
|
1163 e_dbg("Error while waiting for autoneg to complete\n"); |
|
1164 return ret_val; |
|
1165 } |
|
1166 } |
|
1167 |
|
1168 hw->mac.get_link_status = true; |
|
1169 |
|
1170 return ret_val; |
|
1171 } |
|
1172 |
|
1173 /** |
|
1174 * e1000e_setup_copper_link - Configure copper link settings |
|
1175 * @hw: pointer to the HW structure |
|
1176 * |
|
1177 * Calls the appropriate function to configure the link for auto-neg or forced |
|
1178 * speed and duplex. Then we check for link, once link is established calls |
|
1179 * to configure collision distance and flow control are called. If link is |
|
1180 * not established, we return -E1000_ERR_PHY (-2). |
|
1181 **/ |
|
1182 s32 e1000e_setup_copper_link(struct e1000_hw *hw) |
|
1183 { |
|
1184 s32 ret_val; |
|
1185 bool link; |
|
1186 |
|
1187 if (hw->mac.autoneg) { |
|
1188 /* Setup autoneg and flow control advertisement and perform |
|
1189 * autonegotiation. |
|
1190 */ |
|
1191 ret_val = e1000_copper_link_autoneg(hw); |
|
1192 if (ret_val) |
|
1193 return ret_val; |
|
1194 } else { |
|
1195 /* PHY will be set to 10H, 10F, 100H or 100F |
|
1196 * depending on user settings. |
|
1197 */ |
|
1198 e_dbg("Forcing Speed and Duplex\n"); |
|
1199 ret_val = e1000_phy_force_speed_duplex(hw); |
|
1200 if (ret_val) { |
|
1201 e_dbg("Error Forcing Speed and Duplex\n"); |
|
1202 return ret_val; |
|
1203 } |
|
1204 } |
|
1205 |
|
1206 /* Check link status. Wait up to 100 microseconds for link to become |
|
1207 * valid. |
|
1208 */ |
|
1209 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
|
1210 &link); |
|
1211 if (ret_val) |
|
1212 return ret_val; |
|
1213 |
|
1214 if (link) { |
|
1215 e_dbg("Valid link established!!!\n"); |
|
1216 hw->mac.ops.config_collision_dist(hw); |
|
1217 ret_val = e1000e_config_fc_after_link_up(hw); |
|
1218 } else { |
|
1219 e_dbg("Unable to establish link!!!\n"); |
|
1220 } |
|
1221 |
|
1222 return ret_val; |
|
1223 } |
|
1224 |
|
1225 /** |
|
1226 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
|
1227 * @hw: pointer to the HW structure |
|
1228 * |
|
1229 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1230 * auto-crossover to force MDI manually. Waits for link and returns |
|
1231 * successful if link up is successful, else -E1000_ERR_PHY (-2). |
|
1232 **/ |
|
1233 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
|
1234 { |
|
1235 struct e1000_phy_info *phy = &hw->phy; |
|
1236 s32 ret_val; |
|
1237 u16 phy_data; |
|
1238 bool link; |
|
1239 |
|
1240 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
|
1241 if (ret_val) |
|
1242 return ret_val; |
|
1243 |
|
1244 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1245 |
|
1246 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
|
1247 if (ret_val) |
|
1248 return ret_val; |
|
1249 |
|
1250 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
|
1251 * forced whenever speed and duplex are forced. |
|
1252 */ |
|
1253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
|
1254 if (ret_val) |
|
1255 return ret_val; |
|
1256 |
|
1257 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
|
1258 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
|
1259 |
|
1260 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
|
1261 if (ret_val) |
|
1262 return ret_val; |
|
1263 |
|
1264 e_dbg("IGP PSCR: %X\n", phy_data); |
|
1265 |
|
1266 udelay(1); |
|
1267 |
|
1268 if (phy->autoneg_wait_to_complete) { |
|
1269 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
|
1270 |
|
1271 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1272 100000, &link); |
|
1273 if (ret_val) |
|
1274 return ret_val; |
|
1275 |
|
1276 if (!link) |
|
1277 e_dbg("Link taking longer than expected.\n"); |
|
1278 |
|
1279 /* Try once more */ |
|
1280 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1281 100000, &link); |
|
1282 } |
|
1283 |
|
1284 return ret_val; |
|
1285 } |
|
1286 |
|
1287 /** |
|
1288 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
|
1289 * @hw: pointer to the HW structure |
|
1290 * |
|
1291 * Calls the PHY setup function to force speed and duplex. Clears the |
|
1292 * auto-crossover to force MDI manually. Resets the PHY to commit the |
|
1293 * changes. If time expires while waiting for link up, we reset the DSP. |
|
1294 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
|
1295 * successful completion, else return corresponding error code. |
|
1296 **/ |
|
1297 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
|
1298 { |
|
1299 struct e1000_phy_info *phy = &hw->phy; |
|
1300 s32 ret_val; |
|
1301 u16 phy_data; |
|
1302 bool link; |
|
1303 |
|
1304 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
|
1305 * forced whenever speed and duplex are forced. |
|
1306 */ |
|
1307 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1308 if (ret_val) |
|
1309 return ret_val; |
|
1310 |
|
1311 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
|
1312 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1313 if (ret_val) |
|
1314 return ret_val; |
|
1315 |
|
1316 e_dbg("M88E1000 PSCR: %X\n", phy_data); |
|
1317 |
|
1318 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
|
1319 if (ret_val) |
|
1320 return ret_val; |
|
1321 |
|
1322 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
1323 |
|
1324 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
|
1325 if (ret_val) |
|
1326 return ret_val; |
|
1327 |
|
1328 /* Reset the phy to commit changes. */ |
|
1329 ret_val = e1000e_commit_phy(hw); |
|
1330 if (ret_val) |
|
1331 return ret_val; |
|
1332 |
|
1333 if (phy->autoneg_wait_to_complete) { |
|
1334 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
|
1335 |
|
1336 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1337 100000, &link); |
|
1338 if (ret_val) |
|
1339 return ret_val; |
|
1340 |
|
1341 if (!link) { |
|
1342 if (hw->phy.type != e1000_phy_m88) { |
|
1343 e_dbg("Link taking longer than expected.\n"); |
|
1344 } else { |
|
1345 /* We didn't get link. |
|
1346 * Reset the DSP and cross our fingers. |
|
1347 */ |
|
1348 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
|
1349 0x001d); |
|
1350 if (ret_val) |
|
1351 return ret_val; |
|
1352 ret_val = e1000e_phy_reset_dsp(hw); |
|
1353 if (ret_val) |
|
1354 return ret_val; |
|
1355 } |
|
1356 } |
|
1357 |
|
1358 /* Try once more */ |
|
1359 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1360 100000, &link); |
|
1361 if (ret_val) |
|
1362 return ret_val; |
|
1363 } |
|
1364 |
|
1365 if (hw->phy.type != e1000_phy_m88) |
|
1366 return 0; |
|
1367 |
|
1368 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
|
1369 if (ret_val) |
|
1370 return ret_val; |
|
1371 |
|
1372 /* Resetting the phy means we need to re-force TX_CLK in the |
|
1373 * Extended PHY Specific Control Register to 25MHz clock from |
|
1374 * the reset value of 2.5MHz. |
|
1375 */ |
|
1376 phy_data |= M88E1000_EPSCR_TX_CLK_25; |
|
1377 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
|
1378 if (ret_val) |
|
1379 return ret_val; |
|
1380 |
|
1381 /* In addition, we must re-enable CRS on Tx for both half and full |
|
1382 * duplex. |
|
1383 */ |
|
1384 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1385 if (ret_val) |
|
1386 return ret_val; |
|
1387 |
|
1388 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
|
1389 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
|
1390 |
|
1391 return ret_val; |
|
1392 } |
|
1393 |
|
1394 /** |
|
1395 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex |
|
1396 * @hw: pointer to the HW structure |
|
1397 * |
|
1398 * Forces the speed and duplex settings of the PHY. |
|
1399 * This is a function pointer entry point only called by |
|
1400 * PHY setup routines. |
|
1401 **/ |
|
1402 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) |
|
1403 { |
|
1404 struct e1000_phy_info *phy = &hw->phy; |
|
1405 s32 ret_val; |
|
1406 u16 data; |
|
1407 bool link; |
|
1408 |
|
1409 ret_val = e1e_rphy(hw, PHY_CONTROL, &data); |
|
1410 if (ret_val) |
|
1411 return ret_val; |
|
1412 |
|
1413 e1000e_phy_force_speed_duplex_setup(hw, &data); |
|
1414 |
|
1415 ret_val = e1e_wphy(hw, PHY_CONTROL, data); |
|
1416 if (ret_val) |
|
1417 return ret_val; |
|
1418 |
|
1419 /* Disable MDI-X support for 10/100 */ |
|
1420 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
1421 if (ret_val) |
|
1422 return ret_val; |
|
1423 |
|
1424 data &= ~IFE_PMC_AUTO_MDIX; |
|
1425 data &= ~IFE_PMC_FORCE_MDIX; |
|
1426 |
|
1427 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
|
1428 if (ret_val) |
|
1429 return ret_val; |
|
1430 |
|
1431 e_dbg("IFE PMC: %X\n", data); |
|
1432 |
|
1433 udelay(1); |
|
1434 |
|
1435 if (phy->autoneg_wait_to_complete) { |
|
1436 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); |
|
1437 |
|
1438 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1439 100000, &link); |
|
1440 if (ret_val) |
|
1441 return ret_val; |
|
1442 |
|
1443 if (!link) |
|
1444 e_dbg("Link taking longer than expected.\n"); |
|
1445 |
|
1446 /* Try once more */ |
|
1447 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
1448 100000, &link); |
|
1449 if (ret_val) |
|
1450 return ret_val; |
|
1451 } |
|
1452 |
|
1453 return 0; |
|
1454 } |
|
1455 |
|
1456 /** |
|
1457 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
|
1458 * @hw: pointer to the HW structure |
|
1459 * @phy_ctrl: pointer to current value of PHY_CONTROL |
|
1460 * |
|
1461 * Forces speed and duplex on the PHY by doing the following: disable flow |
|
1462 * control, force speed/duplex on the MAC, disable auto speed detection, |
|
1463 * disable auto-negotiation, configure duplex, configure speed, configure |
|
1464 * the collision distance, write configuration to CTRL register. The |
|
1465 * caller must write to the PHY_CONTROL register for these settings to |
|
1466 * take affect. |
|
1467 **/ |
|
1468 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) |
|
1469 { |
|
1470 struct e1000_mac_info *mac = &hw->mac; |
|
1471 u32 ctrl; |
|
1472 |
|
1473 /* Turn off flow control when forcing speed/duplex */ |
|
1474 hw->fc.current_mode = e1000_fc_none; |
|
1475 |
|
1476 /* Force speed/duplex on the mac */ |
|
1477 ctrl = er32(CTRL); |
|
1478 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
1479 ctrl &= ~E1000_CTRL_SPD_SEL; |
|
1480 |
|
1481 /* Disable Auto Speed Detection */ |
|
1482 ctrl &= ~E1000_CTRL_ASDE; |
|
1483 |
|
1484 /* Disable autoneg on the phy */ |
|
1485 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; |
|
1486 |
|
1487 /* Forcing Full or Half Duplex? */ |
|
1488 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
|
1489 ctrl &= ~E1000_CTRL_FD; |
|
1490 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; |
|
1491 e_dbg("Half Duplex\n"); |
|
1492 } else { |
|
1493 ctrl |= E1000_CTRL_FD; |
|
1494 *phy_ctrl |= MII_CR_FULL_DUPLEX; |
|
1495 e_dbg("Full Duplex\n"); |
|
1496 } |
|
1497 |
|
1498 /* Forcing 10mb or 100mb? */ |
|
1499 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
|
1500 ctrl |= E1000_CTRL_SPD_100; |
|
1501 *phy_ctrl |= MII_CR_SPEED_100; |
|
1502 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
|
1503 e_dbg("Forcing 100mb\n"); |
|
1504 } else { |
|
1505 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
|
1506 *phy_ctrl |= MII_CR_SPEED_10; |
|
1507 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
|
1508 e_dbg("Forcing 10mb\n"); |
|
1509 } |
|
1510 |
|
1511 hw->mac.ops.config_collision_dist(hw); |
|
1512 |
|
1513 ew32(CTRL, ctrl); |
|
1514 } |
|
1515 |
|
1516 /** |
|
1517 * e1000e_set_d3_lplu_state - Sets low power link up state for D3 |
|
1518 * @hw: pointer to the HW structure |
|
1519 * @active: boolean used to enable/disable lplu |
|
1520 * |
|
1521 * Success returns 0, Failure returns 1 |
|
1522 * |
|
1523 * The low power link up (lplu) state is set to the power management level D3 |
|
1524 * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
|
1525 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
|
1526 * is used during Dx states where the power conservation is most important. |
|
1527 * During driver activity, SmartSpeed should be enabled so performance is |
|
1528 * maintained. |
|
1529 **/ |
|
1530 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
|
1531 { |
|
1532 struct e1000_phy_info *phy = &hw->phy; |
|
1533 s32 ret_val; |
|
1534 u16 data; |
|
1535 |
|
1536 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
|
1537 if (ret_val) |
|
1538 return ret_val; |
|
1539 |
|
1540 if (!active) { |
|
1541 data &= ~IGP02E1000_PM_D3_LPLU; |
|
1542 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1543 if (ret_val) |
|
1544 return ret_val; |
|
1545 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
|
1546 * during Dx states where the power conservation is most |
|
1547 * important. During driver activity we should enable |
|
1548 * SmartSpeed, so performance is maintained. |
|
1549 */ |
|
1550 if (phy->smart_speed == e1000_smart_speed_on) { |
|
1551 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1552 &data); |
|
1553 if (ret_val) |
|
1554 return ret_val; |
|
1555 |
|
1556 data |= IGP01E1000_PSCFR_SMART_SPEED; |
|
1557 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1558 data); |
|
1559 if (ret_val) |
|
1560 return ret_val; |
|
1561 } else if (phy->smart_speed == e1000_smart_speed_off) { |
|
1562 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1563 &data); |
|
1564 if (ret_val) |
|
1565 return ret_val; |
|
1566 |
|
1567 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1568 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
|
1569 data); |
|
1570 if (ret_val) |
|
1571 return ret_val; |
|
1572 } |
|
1573 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
|
1574 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
|
1575 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
|
1576 data |= IGP02E1000_PM_D3_LPLU; |
|
1577 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
|
1578 if (ret_val) |
|
1579 return ret_val; |
|
1580 |
|
1581 /* When LPLU is enabled, we should disable SmartSpeed */ |
|
1582 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
|
1583 if (ret_val) |
|
1584 return ret_val; |
|
1585 |
|
1586 data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
|
1587 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
|
1588 } |
|
1589 |
|
1590 return ret_val; |
|
1591 } |
|
1592 |
|
1593 /** |
|
1594 * e1000e_check_downshift - Checks whether a downshift in speed occurred |
|
1595 * @hw: pointer to the HW structure |
|
1596 * |
|
1597 * Success returns 0, Failure returns 1 |
|
1598 * |
|
1599 * A downshift is detected by querying the PHY link health. |
|
1600 **/ |
|
1601 s32 e1000e_check_downshift(struct e1000_hw *hw) |
|
1602 { |
|
1603 struct e1000_phy_info *phy = &hw->phy; |
|
1604 s32 ret_val; |
|
1605 u16 phy_data, offset, mask; |
|
1606 |
|
1607 switch (phy->type) { |
|
1608 case e1000_phy_m88: |
|
1609 case e1000_phy_gg82563: |
|
1610 case e1000_phy_bm: |
|
1611 case e1000_phy_82578: |
|
1612 offset = M88E1000_PHY_SPEC_STATUS; |
|
1613 mask = M88E1000_PSSR_DOWNSHIFT; |
|
1614 break; |
|
1615 case e1000_phy_igp_2: |
|
1616 case e1000_phy_igp_3: |
|
1617 offset = IGP01E1000_PHY_LINK_HEALTH; |
|
1618 mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
|
1619 break; |
|
1620 default: |
|
1621 /* speed downshift not supported */ |
|
1622 phy->speed_downgraded = false; |
|
1623 return 0; |
|
1624 } |
|
1625 |
|
1626 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1627 |
|
1628 if (!ret_val) |
|
1629 phy->speed_downgraded = !!(phy_data & mask); |
|
1630 |
|
1631 return ret_val; |
|
1632 } |
|
1633 |
|
1634 /** |
|
1635 * e1000_check_polarity_m88 - Checks the polarity. |
|
1636 * @hw: pointer to the HW structure |
|
1637 * |
|
1638 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1639 * |
|
1640 * Polarity is determined based on the PHY specific status register. |
|
1641 **/ |
|
1642 s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
|
1643 { |
|
1644 struct e1000_phy_info *phy = &hw->phy; |
|
1645 s32 ret_val; |
|
1646 u16 data; |
|
1647 |
|
1648 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); |
|
1649 |
|
1650 if (!ret_val) |
|
1651 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) |
|
1652 ? e1000_rev_polarity_reversed |
|
1653 : e1000_rev_polarity_normal; |
|
1654 |
|
1655 return ret_val; |
|
1656 } |
|
1657 |
|
1658 /** |
|
1659 * e1000_check_polarity_igp - Checks the polarity. |
|
1660 * @hw: pointer to the HW structure |
|
1661 * |
|
1662 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
1663 * |
|
1664 * Polarity is determined based on the PHY port status register, and the |
|
1665 * current speed (since there is no polarity at 100Mbps). |
|
1666 **/ |
|
1667 s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
|
1668 { |
|
1669 struct e1000_phy_info *phy = &hw->phy; |
|
1670 s32 ret_val; |
|
1671 u16 data, offset, mask; |
|
1672 |
|
1673 /* Polarity is determined based on the speed of |
|
1674 * our connection. |
|
1675 */ |
|
1676 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
1677 if (ret_val) |
|
1678 return ret_val; |
|
1679 |
|
1680 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
1681 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
1682 offset = IGP01E1000_PHY_PCS_INIT_REG; |
|
1683 mask = IGP01E1000_PHY_POLARITY_MASK; |
|
1684 } else { |
|
1685 /* This really only applies to 10Mbps since |
|
1686 * there is no polarity for 100Mbps (always 0). |
|
1687 */ |
|
1688 offset = IGP01E1000_PHY_PORT_STATUS; |
|
1689 mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
|
1690 } |
|
1691 |
|
1692 ret_val = e1e_rphy(hw, offset, &data); |
|
1693 |
|
1694 if (!ret_val) |
|
1695 phy->cable_polarity = (data & mask) |
|
1696 ? e1000_rev_polarity_reversed |
|
1697 : e1000_rev_polarity_normal; |
|
1698 |
|
1699 return ret_val; |
|
1700 } |
|
1701 |
|
1702 /** |
|
1703 * e1000_check_polarity_ife - Check cable polarity for IFE PHY |
|
1704 * @hw: pointer to the HW structure |
|
1705 * |
|
1706 * Polarity is determined on the polarity reversal feature being enabled. |
|
1707 **/ |
|
1708 s32 e1000_check_polarity_ife(struct e1000_hw *hw) |
|
1709 { |
|
1710 struct e1000_phy_info *phy = &hw->phy; |
|
1711 s32 ret_val; |
|
1712 u16 phy_data, offset, mask; |
|
1713 |
|
1714 /* Polarity is determined based on the reversal feature being enabled. |
|
1715 */ |
|
1716 if (phy->polarity_correction) { |
|
1717 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; |
|
1718 mask = IFE_PESC_POLARITY_REVERSED; |
|
1719 } else { |
|
1720 offset = IFE_PHY_SPECIAL_CONTROL; |
|
1721 mask = IFE_PSC_FORCE_POLARITY; |
|
1722 } |
|
1723 |
|
1724 ret_val = e1e_rphy(hw, offset, &phy_data); |
|
1725 |
|
1726 if (!ret_val) |
|
1727 phy->cable_polarity = (phy_data & mask) |
|
1728 ? e1000_rev_polarity_reversed |
|
1729 : e1000_rev_polarity_normal; |
|
1730 |
|
1731 return ret_val; |
|
1732 } |
|
1733 |
|
1734 /** |
|
1735 * e1000_wait_autoneg - Wait for auto-neg completion |
|
1736 * @hw: pointer to the HW structure |
|
1737 * |
|
1738 * Waits for auto-negotiation to complete or for the auto-negotiation time |
|
1739 * limit to expire, which ever happens first. |
|
1740 **/ |
|
1741 static s32 e1000_wait_autoneg(struct e1000_hw *hw) |
|
1742 { |
|
1743 s32 ret_val = 0; |
|
1744 u16 i, phy_status; |
|
1745 |
|
1746 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
|
1747 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
|
1748 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1749 if (ret_val) |
|
1750 break; |
|
1751 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1752 if (ret_val) |
|
1753 break; |
|
1754 if (phy_status & MII_SR_AUTONEG_COMPLETE) |
|
1755 break; |
|
1756 msleep(100); |
|
1757 } |
|
1758 |
|
1759 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
|
1760 * has completed. |
|
1761 */ |
|
1762 return ret_val; |
|
1763 } |
|
1764 |
|
1765 /** |
|
1766 * e1000e_phy_has_link_generic - Polls PHY for link |
|
1767 * @hw: pointer to the HW structure |
|
1768 * @iterations: number of times to poll for link |
|
1769 * @usec_interval: delay between polling attempts |
|
1770 * @success: pointer to whether polling was successful or not |
|
1771 * |
|
1772 * Polls the PHY status register for link, 'iterations' number of times. |
|
1773 **/ |
|
1774 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
|
1775 u32 usec_interval, bool *success) |
|
1776 { |
|
1777 s32 ret_val = 0; |
|
1778 u16 i, phy_status; |
|
1779 |
|
1780 for (i = 0; i < iterations; i++) { |
|
1781 /* Some PHYs require the PHY_STATUS register to be read |
|
1782 * twice due to the link bit being sticky. No harm doing |
|
1783 * it across the board. |
|
1784 */ |
|
1785 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1786 if (ret_val) |
|
1787 /* If the first read fails, another entity may have |
|
1788 * ownership of the resources, wait and try again to |
|
1789 * see if they have relinquished the resources yet. |
|
1790 */ |
|
1791 udelay(usec_interval); |
|
1792 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
|
1793 if (ret_val) |
|
1794 break; |
|
1795 if (phy_status & MII_SR_LINK_STATUS) |
|
1796 break; |
|
1797 if (usec_interval >= 1000) |
|
1798 mdelay(usec_interval/1000); |
|
1799 else |
|
1800 udelay(usec_interval); |
|
1801 } |
|
1802 |
|
1803 *success = (i < iterations); |
|
1804 |
|
1805 return ret_val; |
|
1806 } |
|
1807 |
|
1808 /** |
|
1809 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY |
|
1810 * @hw: pointer to the HW structure |
|
1811 * |
|
1812 * Reads the PHY specific status register to retrieve the cable length |
|
1813 * information. The cable length is determined by averaging the minimum and |
|
1814 * maximum values to get the "average" cable length. The m88 PHY has four |
|
1815 * possible cable length values, which are: |
|
1816 * Register Value Cable Length |
|
1817 * 0 < 50 meters |
|
1818 * 1 50 - 80 meters |
|
1819 * 2 80 - 110 meters |
|
1820 * 3 110 - 140 meters |
|
1821 * 4 > 140 meters |
|
1822 **/ |
|
1823 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) |
|
1824 { |
|
1825 struct e1000_phy_info *phy = &hw->phy; |
|
1826 s32 ret_val; |
|
1827 u16 phy_data, index; |
|
1828 |
|
1829 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1830 if (ret_val) |
|
1831 return ret_val; |
|
1832 |
|
1833 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
|
1834 M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
|
1835 |
|
1836 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) |
|
1837 return -E1000_ERR_PHY; |
|
1838 |
|
1839 phy->min_cable_length = e1000_m88_cable_length_table[index]; |
|
1840 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
|
1841 |
|
1842 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1843 |
|
1844 return 0; |
|
1845 } |
|
1846 |
|
1847 /** |
|
1848 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
|
1849 * @hw: pointer to the HW structure |
|
1850 * |
|
1851 * The automatic gain control (agc) normalizes the amplitude of the |
|
1852 * received signal, adjusting for the attenuation produced by the |
|
1853 * cable. By reading the AGC registers, which represent the |
|
1854 * combination of coarse and fine gain value, the value can be put |
|
1855 * into a lookup table to obtain the approximate cable length |
|
1856 * for each channel. |
|
1857 **/ |
|
1858 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) |
|
1859 { |
|
1860 struct e1000_phy_info *phy = &hw->phy; |
|
1861 s32 ret_val; |
|
1862 u16 phy_data, i, agc_value = 0; |
|
1863 u16 cur_agc_index, max_agc_index = 0; |
|
1864 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
|
1865 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
|
1866 IGP02E1000_PHY_AGC_A, |
|
1867 IGP02E1000_PHY_AGC_B, |
|
1868 IGP02E1000_PHY_AGC_C, |
|
1869 IGP02E1000_PHY_AGC_D |
|
1870 }; |
|
1871 |
|
1872 /* Read the AGC registers for all channels */ |
|
1873 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
|
1874 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); |
|
1875 if (ret_val) |
|
1876 return ret_val; |
|
1877 |
|
1878 /* Getting bits 15:9, which represent the combination of |
|
1879 * coarse and fine gain values. The result is a number |
|
1880 * that can be put into the lookup table to obtain the |
|
1881 * approximate cable length. |
|
1882 */ |
|
1883 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
|
1884 IGP02E1000_AGC_LENGTH_MASK; |
|
1885 |
|
1886 /* Array index bound check. */ |
|
1887 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
|
1888 (cur_agc_index == 0)) |
|
1889 return -E1000_ERR_PHY; |
|
1890 |
|
1891 /* Remove min & max AGC values from calculation. */ |
|
1892 if (e1000_igp_2_cable_length_table[min_agc_index] > |
|
1893 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1894 min_agc_index = cur_agc_index; |
|
1895 if (e1000_igp_2_cable_length_table[max_agc_index] < |
|
1896 e1000_igp_2_cable_length_table[cur_agc_index]) |
|
1897 max_agc_index = cur_agc_index; |
|
1898 |
|
1899 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
|
1900 } |
|
1901 |
|
1902 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
|
1903 e1000_igp_2_cable_length_table[max_agc_index]); |
|
1904 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
|
1905 |
|
1906 /* Calculate cable length with the error range of +/- 10 meters. */ |
|
1907 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
|
1908 (agc_value - IGP02E1000_AGC_RANGE) : 0; |
|
1909 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
|
1910 |
|
1911 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
|
1912 |
|
1913 return 0; |
|
1914 } |
|
1915 |
|
1916 /** |
|
1917 * e1000e_get_phy_info_m88 - Retrieve PHY information |
|
1918 * @hw: pointer to the HW structure |
|
1919 * |
|
1920 * Valid for only copper links. Read the PHY status register (sticky read) |
|
1921 * to verify that link is up. Read the PHY special control register to |
|
1922 * determine the polarity and 10base-T extended distance. Read the PHY |
|
1923 * special status register to determine MDI/MDIx and current speed. If |
|
1924 * speed is 1000, then determine cable length, local and remote receiver. |
|
1925 **/ |
|
1926 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) |
|
1927 { |
|
1928 struct e1000_phy_info *phy = &hw->phy; |
|
1929 s32 ret_val; |
|
1930 u16 phy_data; |
|
1931 bool link; |
|
1932 |
|
1933 if (phy->media_type != e1000_media_type_copper) { |
|
1934 e_dbg("Phy info is only valid for copper media\n"); |
|
1935 return -E1000_ERR_CONFIG; |
|
1936 } |
|
1937 |
|
1938 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
1939 if (ret_val) |
|
1940 return ret_val; |
|
1941 |
|
1942 if (!link) { |
|
1943 e_dbg("Phy info is only valid if link is up\n"); |
|
1944 return -E1000_ERR_CONFIG; |
|
1945 } |
|
1946 |
|
1947 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
|
1948 if (ret_val) |
|
1949 return ret_val; |
|
1950 |
|
1951 phy->polarity_correction = !!(phy_data & |
|
1952 M88E1000_PSCR_POLARITY_REVERSAL); |
|
1953 |
|
1954 ret_val = e1000_check_polarity_m88(hw); |
|
1955 if (ret_val) |
|
1956 return ret_val; |
|
1957 |
|
1958 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
|
1959 if (ret_val) |
|
1960 return ret_val; |
|
1961 |
|
1962 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
|
1963 |
|
1964 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
|
1965 ret_val = e1000_get_cable_length(hw); |
|
1966 if (ret_val) |
|
1967 return ret_val; |
|
1968 |
|
1969 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); |
|
1970 if (ret_val) |
|
1971 return ret_val; |
|
1972 |
|
1973 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) |
|
1974 ? e1000_1000t_rx_status_ok |
|
1975 : e1000_1000t_rx_status_not_ok; |
|
1976 |
|
1977 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) |
|
1978 ? e1000_1000t_rx_status_ok |
|
1979 : e1000_1000t_rx_status_not_ok; |
|
1980 } else { |
|
1981 /* Set values to "undefined" */ |
|
1982 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
1983 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
1984 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
1985 } |
|
1986 |
|
1987 return ret_val; |
|
1988 } |
|
1989 |
|
1990 /** |
|
1991 * e1000e_get_phy_info_igp - Retrieve igp PHY information |
|
1992 * @hw: pointer to the HW structure |
|
1993 * |
|
1994 * Read PHY status to determine if link is up. If link is up, then |
|
1995 * set/determine 10base-T extended distance and polarity correction. Read |
|
1996 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
1997 * determine on the cable length, local and remote receiver. |
|
1998 **/ |
|
1999 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) |
|
2000 { |
|
2001 struct e1000_phy_info *phy = &hw->phy; |
|
2002 s32 ret_val; |
|
2003 u16 data; |
|
2004 bool link; |
|
2005 |
|
2006 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
2007 if (ret_val) |
|
2008 return ret_val; |
|
2009 |
|
2010 if (!link) { |
|
2011 e_dbg("Phy info is only valid if link is up\n"); |
|
2012 return -E1000_ERR_CONFIG; |
|
2013 } |
|
2014 |
|
2015 phy->polarity_correction = true; |
|
2016 |
|
2017 ret_val = e1000_check_polarity_igp(hw); |
|
2018 if (ret_val) |
|
2019 return ret_val; |
|
2020 |
|
2021 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
|
2022 if (ret_val) |
|
2023 return ret_val; |
|
2024 |
|
2025 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
|
2026 |
|
2027 if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
|
2028 IGP01E1000_PSSR_SPEED_1000MBPS) { |
|
2029 ret_val = e1000_get_cable_length(hw); |
|
2030 if (ret_val) |
|
2031 return ret_val; |
|
2032 |
|
2033 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); |
|
2034 if (ret_val) |
|
2035 return ret_val; |
|
2036 |
|
2037 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
|
2038 ? e1000_1000t_rx_status_ok |
|
2039 : e1000_1000t_rx_status_not_ok; |
|
2040 |
|
2041 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
|
2042 ? e1000_1000t_rx_status_ok |
|
2043 : e1000_1000t_rx_status_not_ok; |
|
2044 } else { |
|
2045 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2046 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2047 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2048 } |
|
2049 |
|
2050 return ret_val; |
|
2051 } |
|
2052 |
|
2053 /** |
|
2054 * e1000_get_phy_info_ife - Retrieves various IFE PHY states |
|
2055 * @hw: pointer to the HW structure |
|
2056 * |
|
2057 * Populates "phy" structure with various feature states. |
|
2058 **/ |
|
2059 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) |
|
2060 { |
|
2061 struct e1000_phy_info *phy = &hw->phy; |
|
2062 s32 ret_val; |
|
2063 u16 data; |
|
2064 bool link; |
|
2065 |
|
2066 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
2067 if (ret_val) |
|
2068 return ret_val; |
|
2069 |
|
2070 if (!link) { |
|
2071 e_dbg("Phy info is only valid if link is up\n"); |
|
2072 return -E1000_ERR_CONFIG; |
|
2073 } |
|
2074 |
|
2075 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
|
2076 if (ret_val) |
|
2077 return ret_val; |
|
2078 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
|
2079 |
|
2080 if (phy->polarity_correction) { |
|
2081 ret_val = e1000_check_polarity_ife(hw); |
|
2082 if (ret_val) |
|
2083 return ret_val; |
|
2084 } else { |
|
2085 /* Polarity is forced */ |
|
2086 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) |
|
2087 ? e1000_rev_polarity_reversed |
|
2088 : e1000_rev_polarity_normal; |
|
2089 } |
|
2090 |
|
2091 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
|
2092 if (ret_val) |
|
2093 return ret_val; |
|
2094 |
|
2095 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
|
2096 |
|
2097 /* The following parameters are undefined for 10/100 operation. */ |
|
2098 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
2099 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
2100 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
2101 |
|
2102 return 0; |
|
2103 } |
|
2104 |
|
2105 /** |
|
2106 * e1000e_phy_sw_reset - PHY software reset |
|
2107 * @hw: pointer to the HW structure |
|
2108 * |
|
2109 * Does a software reset of the PHY by reading the PHY control register and |
|
2110 * setting/write the control register reset bit to the PHY. |
|
2111 **/ |
|
2112 s32 e1000e_phy_sw_reset(struct e1000_hw *hw) |
|
2113 { |
|
2114 s32 ret_val; |
|
2115 u16 phy_ctrl; |
|
2116 |
|
2117 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); |
|
2118 if (ret_val) |
|
2119 return ret_val; |
|
2120 |
|
2121 phy_ctrl |= MII_CR_RESET; |
|
2122 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); |
|
2123 if (ret_val) |
|
2124 return ret_val; |
|
2125 |
|
2126 udelay(1); |
|
2127 |
|
2128 return ret_val; |
|
2129 } |
|
2130 |
|
2131 /** |
|
2132 * e1000e_phy_hw_reset_generic - PHY hardware reset |
|
2133 * @hw: pointer to the HW structure |
|
2134 * |
|
2135 * Verify the reset block is not blocking us from resetting. Acquire |
|
2136 * semaphore (if necessary) and read/set/write the device control reset |
|
2137 * bit in the PHY. Wait the appropriate delay time for the device to |
|
2138 * reset and release the semaphore (if necessary). |
|
2139 **/ |
|
2140 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
|
2141 { |
|
2142 struct e1000_phy_info *phy = &hw->phy; |
|
2143 s32 ret_val; |
|
2144 u32 ctrl; |
|
2145 |
|
2146 if (phy->ops.check_reset_block) { |
|
2147 ret_val = phy->ops.check_reset_block(hw); |
|
2148 if (ret_val) |
|
2149 return 0; |
|
2150 } |
|
2151 |
|
2152 ret_val = phy->ops.acquire(hw); |
|
2153 if (ret_val) |
|
2154 return ret_val; |
|
2155 |
|
2156 ctrl = er32(CTRL); |
|
2157 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); |
|
2158 e1e_flush(); |
|
2159 |
|
2160 udelay(phy->reset_delay_us); |
|
2161 |
|
2162 ew32(CTRL, ctrl); |
|
2163 e1e_flush(); |
|
2164 |
|
2165 udelay(150); |
|
2166 |
|
2167 phy->ops.release(hw); |
|
2168 |
|
2169 return e1000_get_phy_cfg_done(hw); |
|
2170 } |
|
2171 |
|
2172 /** |
|
2173 * e1000e_get_cfg_done - Generic configuration done |
|
2174 * @hw: pointer to the HW structure |
|
2175 * |
|
2176 * Generic function to wait 10 milli-seconds for configuration to complete |
|
2177 * and return success. |
|
2178 **/ |
|
2179 s32 e1000e_get_cfg_done(struct e1000_hw *hw) |
|
2180 { |
|
2181 mdelay(10); |
|
2182 |
|
2183 return 0; |
|
2184 } |
|
2185 |
|
2186 /** |
|
2187 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY |
|
2188 * @hw: pointer to the HW structure |
|
2189 * |
|
2190 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
|
2191 **/ |
|
2192 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) |
|
2193 { |
|
2194 e_dbg("Running IGP 3 PHY init script\n"); |
|
2195 |
|
2196 /* PHY init IGP 3 */ |
|
2197 /* Enable rise/fall, 10-mode work in class-A */ |
|
2198 e1e_wphy(hw, 0x2F5B, 0x9018); |
|
2199 /* Remove all caps from Replica path filter */ |
|
2200 e1e_wphy(hw, 0x2F52, 0x0000); |
|
2201 /* Bias trimming for ADC, AFE and Driver (Default) */ |
|
2202 e1e_wphy(hw, 0x2FB1, 0x8B24); |
|
2203 /* Increase Hybrid poly bias */ |
|
2204 e1e_wphy(hw, 0x2FB2, 0xF8F0); |
|
2205 /* Add 4% to Tx amplitude in Gig mode */ |
|
2206 e1e_wphy(hw, 0x2010, 0x10B0); |
|
2207 /* Disable trimming (TTT) */ |
|
2208 e1e_wphy(hw, 0x2011, 0x0000); |
|
2209 /* Poly DC correction to 94.6% + 2% for all channels */ |
|
2210 e1e_wphy(hw, 0x20DD, 0x249A); |
|
2211 /* ABS DC correction to 95.9% */ |
|
2212 e1e_wphy(hw, 0x20DE, 0x00D3); |
|
2213 /* BG temp curve trim */ |
|
2214 e1e_wphy(hw, 0x28B4, 0x04CE); |
|
2215 /* Increasing ADC OPAMP stage 1 currents to max */ |
|
2216 e1e_wphy(hw, 0x2F70, 0x29E4); |
|
2217 /* Force 1000 ( required for enabling PHY regs configuration) */ |
|
2218 e1e_wphy(hw, 0x0000, 0x0140); |
|
2219 /* Set upd_freq to 6 */ |
|
2220 e1e_wphy(hw, 0x1F30, 0x1606); |
|
2221 /* Disable NPDFE */ |
|
2222 e1e_wphy(hw, 0x1F31, 0xB814); |
|
2223 /* Disable adaptive fixed FFE (Default) */ |
|
2224 e1e_wphy(hw, 0x1F35, 0x002A); |
|
2225 /* Enable FFE hysteresis */ |
|
2226 e1e_wphy(hw, 0x1F3E, 0x0067); |
|
2227 /* Fixed FFE for short cable lengths */ |
|
2228 e1e_wphy(hw, 0x1F54, 0x0065); |
|
2229 /* Fixed FFE for medium cable lengths */ |
|
2230 e1e_wphy(hw, 0x1F55, 0x002A); |
|
2231 /* Fixed FFE for long cable lengths */ |
|
2232 e1e_wphy(hw, 0x1F56, 0x002A); |
|
2233 /* Enable Adaptive Clip Threshold */ |
|
2234 e1e_wphy(hw, 0x1F72, 0x3FB0); |
|
2235 /* AHT reset limit to 1 */ |
|
2236 e1e_wphy(hw, 0x1F76, 0xC0FF); |
|
2237 /* Set AHT master delay to 127 msec */ |
|
2238 e1e_wphy(hw, 0x1F77, 0x1DEC); |
|
2239 /* Set scan bits for AHT */ |
|
2240 e1e_wphy(hw, 0x1F78, 0xF9EF); |
|
2241 /* Set AHT Preset bits */ |
|
2242 e1e_wphy(hw, 0x1F79, 0x0210); |
|
2243 /* Change integ_factor of channel A to 3 */ |
|
2244 e1e_wphy(hw, 0x1895, 0x0003); |
|
2245 /* Change prop_factor of channels BCD to 8 */ |
|
2246 e1e_wphy(hw, 0x1796, 0x0008); |
|
2247 /* Change cg_icount + enable integbp for channels BCD */ |
|
2248 e1e_wphy(hw, 0x1798, 0xD008); |
|
2249 /* Change cg_icount + enable integbp + change prop_factor_master |
|
2250 * to 8 for channel A |
|
2251 */ |
|
2252 e1e_wphy(hw, 0x1898, 0xD918); |
|
2253 /* Disable AHT in Slave mode on channel A */ |
|
2254 e1e_wphy(hw, 0x187A, 0x0800); |
|
2255 /* Enable LPLU and disable AN to 1000 in non-D0a states, |
|
2256 * Enable SPD+B2B |
|
2257 */ |
|
2258 e1e_wphy(hw, 0x0019, 0x008D); |
|
2259 /* Enable restart AN on an1000_dis change */ |
|
2260 e1e_wphy(hw, 0x001B, 0x2080); |
|
2261 /* Enable wh_fifo read clock in 10/100 modes */ |
|
2262 e1e_wphy(hw, 0x0014, 0x0045); |
|
2263 /* Restart AN, Speed selection is 1000 */ |
|
2264 e1e_wphy(hw, 0x0000, 0x1340); |
|
2265 |
|
2266 return 0; |
|
2267 } |
|
2268 |
|
2269 /* Internal function pointers */ |
|
2270 |
|
2271 /** |
|
2272 * e1000_get_phy_cfg_done - Generic PHY configuration done |
|
2273 * @hw: pointer to the HW structure |
|
2274 * |
|
2275 * Return success if silicon family did not implement a family specific |
|
2276 * get_cfg_done function. |
|
2277 **/ |
|
2278 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
2279 { |
|
2280 if (hw->phy.ops.get_cfg_done) |
|
2281 return hw->phy.ops.get_cfg_done(hw); |
|
2282 |
|
2283 return 0; |
|
2284 } |
|
2285 |
|
2286 /** |
|
2287 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex |
|
2288 * @hw: pointer to the HW structure |
|
2289 * |
|
2290 * When the silicon family has not implemented a forced speed/duplex |
|
2291 * function for the PHY, simply return 0. |
|
2292 **/ |
|
2293 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
|
2294 { |
|
2295 if (hw->phy.ops.force_speed_duplex) |
|
2296 return hw->phy.ops.force_speed_duplex(hw); |
|
2297 |
|
2298 return 0; |
|
2299 } |
|
2300 |
|
2301 /** |
|
2302 * e1000e_get_phy_type_from_id - Get PHY type from id |
|
2303 * @phy_id: phy_id read from the phy |
|
2304 * |
|
2305 * Returns the phy type from the id. |
|
2306 **/ |
|
2307 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) |
|
2308 { |
|
2309 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2310 |
|
2311 switch (phy_id) { |
|
2312 case M88E1000_I_PHY_ID: |
|
2313 case M88E1000_E_PHY_ID: |
|
2314 case M88E1111_I_PHY_ID: |
|
2315 case M88E1011_I_PHY_ID: |
|
2316 phy_type = e1000_phy_m88; |
|
2317 break; |
|
2318 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ |
|
2319 phy_type = e1000_phy_igp_2; |
|
2320 break; |
|
2321 case GG82563_E_PHY_ID: |
|
2322 phy_type = e1000_phy_gg82563; |
|
2323 break; |
|
2324 case IGP03E1000_E_PHY_ID: |
|
2325 phy_type = e1000_phy_igp_3; |
|
2326 break; |
|
2327 case IFE_E_PHY_ID: |
|
2328 case IFE_PLUS_E_PHY_ID: |
|
2329 case IFE_C_E_PHY_ID: |
|
2330 phy_type = e1000_phy_ife; |
|
2331 break; |
|
2332 case BME1000_E_PHY_ID: |
|
2333 case BME1000_E_PHY_ID_R2: |
|
2334 phy_type = e1000_phy_bm; |
|
2335 break; |
|
2336 case I82578_E_PHY_ID: |
|
2337 phy_type = e1000_phy_82578; |
|
2338 break; |
|
2339 case I82577_E_PHY_ID: |
|
2340 phy_type = e1000_phy_82577; |
|
2341 break; |
|
2342 case I82579_E_PHY_ID: |
|
2343 phy_type = e1000_phy_82579; |
|
2344 break; |
|
2345 case I217_E_PHY_ID: |
|
2346 phy_type = e1000_phy_i217; |
|
2347 break; |
|
2348 default: |
|
2349 phy_type = e1000_phy_unknown; |
|
2350 break; |
|
2351 } |
|
2352 return phy_type; |
|
2353 } |
|
2354 |
|
2355 /** |
|
2356 * e1000e_determine_phy_address - Determines PHY address. |
|
2357 * @hw: pointer to the HW structure |
|
2358 * |
|
2359 * This uses a trial and error method to loop through possible PHY |
|
2360 * addresses. It tests each by reading the PHY ID registers and |
|
2361 * checking for a match. |
|
2362 **/ |
|
2363 s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
|
2364 { |
|
2365 u32 phy_addr = 0; |
|
2366 u32 i; |
|
2367 enum e1000_phy_type phy_type = e1000_phy_unknown; |
|
2368 |
|
2369 hw->phy.id = phy_type; |
|
2370 |
|
2371 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { |
|
2372 hw->phy.addr = phy_addr; |
|
2373 i = 0; |
|
2374 |
|
2375 do { |
|
2376 e1000e_get_phy_id(hw); |
|
2377 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); |
|
2378 |
|
2379 /* If phy_type is valid, break - we found our |
|
2380 * PHY address |
|
2381 */ |
|
2382 if (phy_type != e1000_phy_unknown) |
|
2383 return 0; |
|
2384 |
|
2385 usleep_range(1000, 2000); |
|
2386 i++; |
|
2387 } while (i < 10); |
|
2388 } |
|
2389 |
|
2390 return -E1000_ERR_PHY_TYPE; |
|
2391 } |
|
2392 |
|
2393 /** |
|
2394 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address |
|
2395 * @page: page to access |
|
2396 * |
|
2397 * Returns the phy address for the page requested. |
|
2398 **/ |
|
2399 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) |
|
2400 { |
|
2401 u32 phy_addr = 2; |
|
2402 |
|
2403 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) |
|
2404 phy_addr = 1; |
|
2405 |
|
2406 return phy_addr; |
|
2407 } |
|
2408 |
|
2409 /** |
|
2410 * e1000e_write_phy_reg_bm - Write BM PHY register |
|
2411 * @hw: pointer to the HW structure |
|
2412 * @offset: register offset to write to |
|
2413 * @data: data to write at register offset |
|
2414 * |
|
2415 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2416 * at the offset. Release any acquired semaphores before exiting. |
|
2417 **/ |
|
2418 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) |
|
2419 { |
|
2420 s32 ret_val; |
|
2421 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2422 |
|
2423 ret_val = hw->phy.ops.acquire(hw); |
|
2424 if (ret_val) |
|
2425 return ret_val; |
|
2426 |
|
2427 /* Page 800 works differently than the rest so it has its own func */ |
|
2428 if (page == BM_WUC_PAGE) { |
|
2429 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2430 false, false); |
|
2431 goto release; |
|
2432 } |
|
2433 |
|
2434 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2435 |
|
2436 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2437 u32 page_shift, page_select; |
|
2438 |
|
2439 /* Page select is register 31 for phy address 1 and 22 for |
|
2440 * phy address 2 and 3. Page select is shifted only for |
|
2441 * phy address 1. |
|
2442 */ |
|
2443 if (hw->phy.addr == 1) { |
|
2444 page_shift = IGP_PAGE_SHIFT; |
|
2445 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2446 } else { |
|
2447 page_shift = 0; |
|
2448 page_select = BM_PHY_PAGE_SELECT; |
|
2449 } |
|
2450 |
|
2451 /* Page is shifted left, PHY expects (page x 32) */ |
|
2452 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2453 (page << page_shift)); |
|
2454 if (ret_val) |
|
2455 goto release; |
|
2456 } |
|
2457 |
|
2458 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2459 data); |
|
2460 |
|
2461 release: |
|
2462 hw->phy.ops.release(hw); |
|
2463 return ret_val; |
|
2464 } |
|
2465 |
|
2466 /** |
|
2467 * e1000e_read_phy_reg_bm - Read BM PHY register |
|
2468 * @hw: pointer to the HW structure |
|
2469 * @offset: register offset to be read |
|
2470 * @data: pointer to the read data |
|
2471 * |
|
2472 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2473 * and storing the retrieved information in data. Release any acquired |
|
2474 * semaphores before exiting. |
|
2475 **/ |
|
2476 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2477 { |
|
2478 s32 ret_val; |
|
2479 u32 page = offset >> IGP_PAGE_SHIFT; |
|
2480 |
|
2481 ret_val = hw->phy.ops.acquire(hw); |
|
2482 if (ret_val) |
|
2483 return ret_val; |
|
2484 |
|
2485 /* Page 800 works differently than the rest so it has its own func */ |
|
2486 if (page == BM_WUC_PAGE) { |
|
2487 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2488 true, false); |
|
2489 goto release; |
|
2490 } |
|
2491 |
|
2492 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
|
2493 |
|
2494 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2495 u32 page_shift, page_select; |
|
2496 |
|
2497 /* Page select is register 31 for phy address 1 and 22 for |
|
2498 * phy address 2 and 3. Page select is shifted only for |
|
2499 * phy address 1. |
|
2500 */ |
|
2501 if (hw->phy.addr == 1) { |
|
2502 page_shift = IGP_PAGE_SHIFT; |
|
2503 page_select = IGP01E1000_PHY_PAGE_SELECT; |
|
2504 } else { |
|
2505 page_shift = 0; |
|
2506 page_select = BM_PHY_PAGE_SELECT; |
|
2507 } |
|
2508 |
|
2509 /* Page is shifted left, PHY expects (page x 32) */ |
|
2510 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, |
|
2511 (page << page_shift)); |
|
2512 if (ret_val) |
|
2513 goto release; |
|
2514 } |
|
2515 |
|
2516 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2517 data); |
|
2518 release: |
|
2519 hw->phy.ops.release(hw); |
|
2520 return ret_val; |
|
2521 } |
|
2522 |
|
2523 /** |
|
2524 * e1000e_read_phy_reg_bm2 - Read BM PHY register |
|
2525 * @hw: pointer to the HW structure |
|
2526 * @offset: register offset to be read |
|
2527 * @data: pointer to the read data |
|
2528 * |
|
2529 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2530 * and storing the retrieved information in data. Release any acquired |
|
2531 * semaphores before exiting. |
|
2532 **/ |
|
2533 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2534 { |
|
2535 s32 ret_val; |
|
2536 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2537 |
|
2538 ret_val = hw->phy.ops.acquire(hw); |
|
2539 if (ret_val) |
|
2540 return ret_val; |
|
2541 |
|
2542 /* Page 800 works differently than the rest so it has its own func */ |
|
2543 if (page == BM_WUC_PAGE) { |
|
2544 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2545 true, false); |
|
2546 goto release; |
|
2547 } |
|
2548 |
|
2549 hw->phy.addr = 1; |
|
2550 |
|
2551 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2552 |
|
2553 /* Page is shifted left, PHY expects (page x 32) */ |
|
2554 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2555 page); |
|
2556 |
|
2557 if (ret_val) |
|
2558 goto release; |
|
2559 } |
|
2560 |
|
2561 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2562 data); |
|
2563 release: |
|
2564 hw->phy.ops.release(hw); |
|
2565 return ret_val; |
|
2566 } |
|
2567 |
|
2568 /** |
|
2569 * e1000e_write_phy_reg_bm2 - Write BM PHY register |
|
2570 * @hw: pointer to the HW structure |
|
2571 * @offset: register offset to write to |
|
2572 * @data: data to write at register offset |
|
2573 * |
|
2574 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2575 * at the offset. Release any acquired semaphores before exiting. |
|
2576 **/ |
|
2577 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) |
|
2578 { |
|
2579 s32 ret_val; |
|
2580 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); |
|
2581 |
|
2582 ret_val = hw->phy.ops.acquire(hw); |
|
2583 if (ret_val) |
|
2584 return ret_val; |
|
2585 |
|
2586 /* Page 800 works differently than the rest so it has its own func */ |
|
2587 if (page == BM_WUC_PAGE) { |
|
2588 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2589 false, false); |
|
2590 goto release; |
|
2591 } |
|
2592 |
|
2593 hw->phy.addr = 1; |
|
2594 |
|
2595 if (offset > MAX_PHY_MULTI_PAGE_REG) { |
|
2596 /* Page is shifted left, PHY expects (page x 32) */ |
|
2597 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, |
|
2598 page); |
|
2599 |
|
2600 if (ret_val) |
|
2601 goto release; |
|
2602 } |
|
2603 |
|
2604 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
|
2605 data); |
|
2606 |
|
2607 release: |
|
2608 hw->phy.ops.release(hw); |
|
2609 return ret_val; |
|
2610 } |
|
2611 |
|
2612 /** |
|
2613 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
|
2614 * @hw: pointer to the HW structure |
|
2615 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
|
2616 * |
|
2617 * Assumes semaphore already acquired and phy_reg points to a valid memory |
|
2618 * address to store contents of the BM_WUC_ENABLE_REG register. |
|
2619 **/ |
|
2620 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
|
2621 { |
|
2622 s32 ret_val; |
|
2623 u16 temp; |
|
2624 |
|
2625 /* All page select, port ctrl and wakeup registers use phy address 1 */ |
|
2626 hw->phy.addr = 1; |
|
2627 |
|
2628 /* Select Port Control Registers page */ |
|
2629 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
|
2630 if (ret_val) { |
|
2631 e_dbg("Could not set Port Control page\n"); |
|
2632 return ret_val; |
|
2633 } |
|
2634 |
|
2635 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
|
2636 if (ret_val) { |
|
2637 e_dbg("Could not read PHY register %d.%d\n", |
|
2638 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2639 return ret_val; |
|
2640 } |
|
2641 |
|
2642 /* Enable both PHY wakeup mode and Wakeup register page writes. |
|
2643 * Prevent a power state change by disabling ME and Host PHY wakeup. |
|
2644 */ |
|
2645 temp = *phy_reg; |
|
2646 temp |= BM_WUC_ENABLE_BIT; |
|
2647 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); |
|
2648 |
|
2649 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); |
|
2650 if (ret_val) { |
|
2651 e_dbg("Could not write PHY register %d.%d\n", |
|
2652 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2653 return ret_val; |
|
2654 } |
|
2655 |
|
2656 /* Select Host Wakeup Registers page - caller now able to write |
|
2657 * registers on the Wakeup registers page |
|
2658 */ |
|
2659 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
|
2660 } |
|
2661 |
|
2662 /** |
|
2663 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs |
|
2664 * @hw: pointer to the HW structure |
|
2665 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG |
|
2666 * |
|
2667 * Restore BM_WUC_ENABLE_REG to its original value. |
|
2668 * |
|
2669 * Assumes semaphore already acquired and *phy_reg is the contents of the |
|
2670 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by |
|
2671 * caller. |
|
2672 **/ |
|
2673 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
|
2674 { |
|
2675 s32 ret_val = 0; |
|
2676 |
|
2677 /* Select Port Control Registers page */ |
|
2678 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
|
2679 if (ret_val) { |
|
2680 e_dbg("Could not set Port Control page\n"); |
|
2681 return ret_val; |
|
2682 } |
|
2683 |
|
2684 /* Restore 769.17 to its original value */ |
|
2685 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); |
|
2686 if (ret_val) |
|
2687 e_dbg("Could not restore PHY register %d.%d\n", |
|
2688 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
|
2689 |
|
2690 return ret_val; |
|
2691 } |
|
2692 |
|
2693 /** |
|
2694 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register |
|
2695 * @hw: pointer to the HW structure |
|
2696 * @offset: register offset to be read or written |
|
2697 * @data: pointer to the data to read or write |
|
2698 * @read: determines if operation is read or write |
|
2699 * @page_set: BM_WUC_PAGE already set and access enabled |
|
2700 * |
|
2701 * Read the PHY register at offset and store the retrieved information in |
|
2702 * data, or write data to PHY register at offset. Note the procedure to |
|
2703 * access the PHY wakeup registers is different than reading the other PHY |
|
2704 * registers. It works as such: |
|
2705 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 |
|
2706 * 2) Set page to 800 for host (801 if we were manageability) |
|
2707 * 3) Write the address using the address opcode (0x11) |
|
2708 * 4) Read or write the data using the data opcode (0x12) |
|
2709 * 5) Restore 769.17.2 to its original value |
|
2710 * |
|
2711 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and |
|
2712 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). |
|
2713 * |
|
2714 * Assumes semaphore is already acquired. When page_set==true, assumes |
|
2715 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack |
|
2716 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). |
|
2717 **/ |
|
2718 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
|
2719 u16 *data, bool read, bool page_set) |
|
2720 { |
|
2721 s32 ret_val; |
|
2722 u16 reg = BM_PHY_REG_NUM(offset); |
|
2723 u16 page = BM_PHY_REG_PAGE(offset); |
|
2724 u16 phy_reg = 0; |
|
2725 |
|
2726 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ |
|
2727 if ((hw->mac.type == e1000_pchlan) && |
|
2728 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) |
|
2729 e_dbg("Attempting to access page %d while gig enabled.\n", |
|
2730 page); |
|
2731 |
|
2732 if (!page_set) { |
|
2733 /* Enable access to PHY wakeup registers */ |
|
2734 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
2735 if (ret_val) { |
|
2736 e_dbg("Could not enable PHY wakeup reg access\n"); |
|
2737 return ret_val; |
|
2738 } |
|
2739 } |
|
2740 |
|
2741 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); |
|
2742 |
|
2743 /* Write the Wakeup register page offset value using opcode 0x11 */ |
|
2744 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
|
2745 if (ret_val) { |
|
2746 e_dbg("Could not write address opcode to page %d\n", page); |
|
2747 return ret_val; |
|
2748 } |
|
2749 |
|
2750 if (read) { |
|
2751 /* Read the Wakeup register page value using opcode 0x12 */ |
|
2752 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2753 data); |
|
2754 } else { |
|
2755 /* Write the Wakeup register page value using opcode 0x12 */ |
|
2756 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
|
2757 *data); |
|
2758 } |
|
2759 |
|
2760 if (ret_val) { |
|
2761 e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
|
2762 return ret_val; |
|
2763 } |
|
2764 |
|
2765 if (!page_set) |
|
2766 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
|
2767 |
|
2768 return ret_val; |
|
2769 } |
|
2770 |
|
2771 /** |
|
2772 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down |
|
2773 * @hw: pointer to the HW structure |
|
2774 * |
|
2775 * In the case of a PHY power down to save power, or to turn off link during a |
|
2776 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2777 * settings. |
|
2778 **/ |
|
2779 void e1000_power_up_phy_copper(struct e1000_hw *hw) |
|
2780 { |
|
2781 u16 mii_reg = 0; |
|
2782 |
|
2783 /* The PHY will retain its settings across a power down/up cycle */ |
|
2784 e1e_rphy(hw, PHY_CONTROL, &mii_reg); |
|
2785 mii_reg &= ~MII_CR_POWER_DOWN; |
|
2786 e1e_wphy(hw, PHY_CONTROL, mii_reg); |
|
2787 } |
|
2788 |
|
2789 /** |
|
2790 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down |
|
2791 * @hw: pointer to the HW structure |
|
2792 * |
|
2793 * In the case of a PHY power down to save power, or to turn off link during a |
|
2794 * driver unload, or wake on lan is not enabled, restore the link to previous |
|
2795 * settings. |
|
2796 **/ |
|
2797 void e1000_power_down_phy_copper(struct e1000_hw *hw) |
|
2798 { |
|
2799 u16 mii_reg = 0; |
|
2800 |
|
2801 /* The PHY will retain its settings across a power down/up cycle */ |
|
2802 e1e_rphy(hw, PHY_CONTROL, &mii_reg); |
|
2803 mii_reg |= MII_CR_POWER_DOWN; |
|
2804 e1e_wphy(hw, PHY_CONTROL, mii_reg); |
|
2805 usleep_range(1000, 2000); |
|
2806 } |
|
2807 |
|
2808 /** |
|
2809 * e1000e_commit_phy - Soft PHY reset |
|
2810 * @hw: pointer to the HW structure |
|
2811 * |
|
2812 * Performs a soft PHY reset on those that apply. This is a function pointer |
|
2813 * entry point called by drivers. |
|
2814 **/ |
|
2815 s32 e1000e_commit_phy(struct e1000_hw *hw) |
|
2816 { |
|
2817 if (hw->phy.ops.commit) |
|
2818 return hw->phy.ops.commit(hw); |
|
2819 |
|
2820 return 0; |
|
2821 } |
|
2822 |
|
2823 /** |
|
2824 * e1000_set_d0_lplu_state - Sets low power link up state for D0 |
|
2825 * @hw: pointer to the HW structure |
|
2826 * @active: boolean used to enable/disable lplu |
|
2827 * |
|
2828 * Success returns 0, Failure returns 1 |
|
2829 * |
|
2830 * The low power link up (lplu) state is set to the power management level D0 |
|
2831 * and SmartSpeed is disabled when active is true, else clear lplu for D0 |
|
2832 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
|
2833 * is used during Dx states where the power conservation is most important. |
|
2834 * During driver activity, SmartSpeed should be enabled so performance is |
|
2835 * maintained. This is a function pointer entry point called by drivers. |
|
2836 **/ |
|
2837 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
|
2838 { |
|
2839 if (hw->phy.ops.set_d0_lplu_state) |
|
2840 return hw->phy.ops.set_d0_lplu_state(hw, active); |
|
2841 |
|
2842 return 0; |
|
2843 } |
|
2844 |
|
2845 /** |
|
2846 * __e1000_read_phy_reg_hv - Read HV PHY register |
|
2847 * @hw: pointer to the HW structure |
|
2848 * @offset: register offset to be read |
|
2849 * @data: pointer to the read data |
|
2850 * @locked: semaphore has already been acquired or not |
|
2851 * |
|
2852 * Acquires semaphore, if necessary, then reads the PHY register at offset |
|
2853 * and stores the retrieved information in data. Release any acquired |
|
2854 * semaphore before exiting. |
|
2855 **/ |
|
2856 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
|
2857 bool locked, bool page_set) |
|
2858 { |
|
2859 s32 ret_val; |
|
2860 u16 page = BM_PHY_REG_PAGE(offset); |
|
2861 u16 reg = BM_PHY_REG_NUM(offset); |
|
2862 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2863 |
|
2864 if (!locked) { |
|
2865 ret_val = hw->phy.ops.acquire(hw); |
|
2866 if (ret_val) |
|
2867 return ret_val; |
|
2868 } |
|
2869 |
|
2870 /* Page 800 works differently than the rest so it has its own func */ |
|
2871 if (page == BM_WUC_PAGE) { |
|
2872 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
|
2873 true, page_set); |
|
2874 goto out; |
|
2875 } |
|
2876 |
|
2877 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2878 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2879 data, true); |
|
2880 goto out; |
|
2881 } |
|
2882 |
|
2883 if (!page_set) { |
|
2884 if (page == HV_INTC_FC_PAGE_START) |
|
2885 page = 0; |
|
2886 |
|
2887 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
2888 /* Page is shifted left, PHY expects (page x 32) */ |
|
2889 ret_val = e1000_set_page_igp(hw, |
|
2890 (page << IGP_PAGE_SHIFT)); |
|
2891 |
|
2892 hw->phy.addr = phy_addr; |
|
2893 |
|
2894 if (ret_val) |
|
2895 goto out; |
|
2896 } |
|
2897 } |
|
2898 |
|
2899 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
|
2900 page << IGP_PAGE_SHIFT, reg); |
|
2901 |
|
2902 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
|
2903 data); |
|
2904 out: |
|
2905 if (!locked) |
|
2906 hw->phy.ops.release(hw); |
|
2907 |
|
2908 return ret_val; |
|
2909 } |
|
2910 |
|
2911 /** |
|
2912 * e1000_read_phy_reg_hv - Read HV PHY register |
|
2913 * @hw: pointer to the HW structure |
|
2914 * @offset: register offset to be read |
|
2915 * @data: pointer to the read data |
|
2916 * |
|
2917 * Acquires semaphore then reads the PHY register at offset and stores |
|
2918 * the retrieved information in data. Release the acquired semaphore |
|
2919 * before exiting. |
|
2920 **/ |
|
2921 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2922 { |
|
2923 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
|
2924 } |
|
2925 |
|
2926 /** |
|
2927 * e1000_read_phy_reg_hv_locked - Read HV PHY register |
|
2928 * @hw: pointer to the HW structure |
|
2929 * @offset: register offset to be read |
|
2930 * @data: pointer to the read data |
|
2931 * |
|
2932 * Reads the PHY register at offset and stores the retrieved information |
|
2933 * in data. Assumes semaphore already acquired. |
|
2934 **/ |
|
2935 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2936 { |
|
2937 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
|
2938 } |
|
2939 |
|
2940 /** |
|
2941 * e1000_read_phy_reg_page_hv - Read HV PHY register |
|
2942 * @hw: pointer to the HW structure |
|
2943 * @offset: register offset to write to |
|
2944 * @data: data to write at register offset |
|
2945 * |
|
2946 * Reads the PHY register at offset and stores the retrieved information |
|
2947 * in data. Assumes semaphore already acquired and page already set. |
|
2948 **/ |
|
2949 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) |
|
2950 { |
|
2951 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); |
|
2952 } |
|
2953 |
|
2954 /** |
|
2955 * __e1000_write_phy_reg_hv - Write HV PHY register |
|
2956 * @hw: pointer to the HW structure |
|
2957 * @offset: register offset to write to |
|
2958 * @data: data to write at register offset |
|
2959 * @locked: semaphore has already been acquired or not |
|
2960 * |
|
2961 * Acquires semaphore, if necessary, then writes the data to PHY register |
|
2962 * at the offset. Release any acquired semaphores before exiting. |
|
2963 **/ |
|
2964 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
|
2965 bool locked, bool page_set) |
|
2966 { |
|
2967 s32 ret_val; |
|
2968 u16 page = BM_PHY_REG_PAGE(offset); |
|
2969 u16 reg = BM_PHY_REG_NUM(offset); |
|
2970 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
|
2971 |
|
2972 if (!locked) { |
|
2973 ret_val = hw->phy.ops.acquire(hw); |
|
2974 if (ret_val) |
|
2975 return ret_val; |
|
2976 } |
|
2977 |
|
2978 /* Page 800 works differently than the rest so it has its own func */ |
|
2979 if (page == BM_WUC_PAGE) { |
|
2980 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
|
2981 false, page_set); |
|
2982 goto out; |
|
2983 } |
|
2984 |
|
2985 if (page > 0 && page < HV_INTC_FC_PAGE_START) { |
|
2986 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, |
|
2987 &data, false); |
|
2988 goto out; |
|
2989 } |
|
2990 |
|
2991 if (!page_set) { |
|
2992 if (page == HV_INTC_FC_PAGE_START) |
|
2993 page = 0; |
|
2994 |
|
2995 /* Workaround MDIO accesses being disabled after entering IEEE |
|
2996 * Power Down (when bit 11 of the PHY Control register is set) |
|
2997 */ |
|
2998 if ((hw->phy.type == e1000_phy_82578) && |
|
2999 (hw->phy.revision >= 1) && |
|
3000 (hw->phy.addr == 2) && |
|
3001 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
|
3002 u16 data2 = 0x7EFF; |
|
3003 ret_val = e1000_access_phy_debug_regs_hv(hw, |
|
3004 (1 << 6) | 0x3, |
|
3005 &data2, false); |
|
3006 if (ret_val) |
|
3007 goto out; |
|
3008 } |
|
3009 |
|
3010 if (reg > MAX_PHY_MULTI_PAGE_REG) { |
|
3011 /* Page is shifted left, PHY expects (page x 32) */ |
|
3012 ret_val = e1000_set_page_igp(hw, |
|
3013 (page << IGP_PAGE_SHIFT)); |
|
3014 |
|
3015 hw->phy.addr = phy_addr; |
|
3016 |
|
3017 if (ret_val) |
|
3018 goto out; |
|
3019 } |
|
3020 } |
|
3021 |
|
3022 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
|
3023 page << IGP_PAGE_SHIFT, reg); |
|
3024 |
|
3025 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
|
3026 data); |
|
3027 |
|
3028 out: |
|
3029 if (!locked) |
|
3030 hw->phy.ops.release(hw); |
|
3031 |
|
3032 return ret_val; |
|
3033 } |
|
3034 |
|
3035 /** |
|
3036 * e1000_write_phy_reg_hv - Write HV PHY register |
|
3037 * @hw: pointer to the HW structure |
|
3038 * @offset: register offset to write to |
|
3039 * @data: data to write at register offset |
|
3040 * |
|
3041 * Acquires semaphore then writes the data to PHY register at the offset. |
|
3042 * Release the acquired semaphores before exiting. |
|
3043 **/ |
|
3044 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) |
|
3045 { |
|
3046 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
|
3047 } |
|
3048 |
|
3049 /** |
|
3050 * e1000_write_phy_reg_hv_locked - Write HV PHY register |
|
3051 * @hw: pointer to the HW structure |
|
3052 * @offset: register offset to write to |
|
3053 * @data: data to write at register offset |
|
3054 * |
|
3055 * Writes the data to PHY register at the offset. Assumes semaphore |
|
3056 * already acquired. |
|
3057 **/ |
|
3058 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) |
|
3059 { |
|
3060 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
|
3061 } |
|
3062 |
|
3063 /** |
|
3064 * e1000_write_phy_reg_page_hv - Write HV PHY register |
|
3065 * @hw: pointer to the HW structure |
|
3066 * @offset: register offset to write to |
|
3067 * @data: data to write at register offset |
|
3068 * |
|
3069 * Writes the data to PHY register at the offset. Assumes semaphore |
|
3070 * already acquired and page already set. |
|
3071 **/ |
|
3072 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) |
|
3073 { |
|
3074 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); |
|
3075 } |
|
3076 |
|
3077 /** |
|
3078 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
|
3079 * @page: page to be accessed |
|
3080 **/ |
|
3081 static u32 e1000_get_phy_addr_for_hv_page(u32 page) |
|
3082 { |
|
3083 u32 phy_addr = 2; |
|
3084 |
|
3085 if (page >= HV_INTC_FC_PAGE_START) |
|
3086 phy_addr = 1; |
|
3087 |
|
3088 return phy_addr; |
|
3089 } |
|
3090 |
|
3091 /** |
|
3092 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers |
|
3093 * @hw: pointer to the HW structure |
|
3094 * @offset: register offset to be read or written |
|
3095 * @data: pointer to the data to be read or written |
|
3096 * @read: determines if operation is read or write |
|
3097 * |
|
3098 * Reads the PHY register at offset and stores the retreived information |
|
3099 * in data. Assumes semaphore already acquired. Note that the procedure |
|
3100 * to access these regs uses the address port and data port to read/write. |
|
3101 * These accesses done with PHY address 2 and without using pages. |
|
3102 **/ |
|
3103 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, |
|
3104 u16 *data, bool read) |
|
3105 { |
|
3106 s32 ret_val; |
|
3107 u32 addr_reg = 0; |
|
3108 u32 data_reg = 0; |
|
3109 |
|
3110 /* This takes care of the difference with desktop vs mobile phy */ |
|
3111 addr_reg = (hw->phy.type == e1000_phy_82578) ? |
|
3112 I82578_ADDR_REG : I82577_ADDR_REG; |
|
3113 data_reg = addr_reg + 1; |
|
3114 |
|
3115 /* All operations in this function are phy address 2 */ |
|
3116 hw->phy.addr = 2; |
|
3117 |
|
3118 /* masking with 0x3F to remove the page from offset */ |
|
3119 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
|
3120 if (ret_val) { |
|
3121 e_dbg("Could not write the Address Offset port register\n"); |
|
3122 return ret_val; |
|
3123 } |
|
3124 |
|
3125 /* Read or write the data value next */ |
|
3126 if (read) |
|
3127 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); |
|
3128 else |
|
3129 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
|
3130 |
|
3131 if (ret_val) |
|
3132 e_dbg("Could not access the Data port register\n"); |
|
3133 |
|
3134 return ret_val; |
|
3135 } |
|
3136 |
|
3137 /** |
|
3138 * e1000_link_stall_workaround_hv - Si workaround |
|
3139 * @hw: pointer to the HW structure |
|
3140 * |
|
3141 * This function works around a Si bug where the link partner can get |
|
3142 * a link up indication before the PHY does. If small packets are sent |
|
3143 * by the link partner they can be placed in the packet buffer without |
|
3144 * being properly accounted for by the PHY and will stall preventing |
|
3145 * further packets from being received. The workaround is to clear the |
|
3146 * packet buffer after the PHY detects link up. |
|
3147 **/ |
|
3148 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) |
|
3149 { |
|
3150 s32 ret_val = 0; |
|
3151 u16 data; |
|
3152 |
|
3153 if (hw->phy.type != e1000_phy_82578) |
|
3154 return 0; |
|
3155 |
|
3156 /* Do not apply workaround if in PHY loopback bit 14 set */ |
|
3157 e1e_rphy(hw, PHY_CONTROL, &data); |
|
3158 if (data & PHY_CONTROL_LB) |
|
3159 return 0; |
|
3160 |
|
3161 /* check if link is up and at 1Gbps */ |
|
3162 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
|
3163 if (ret_val) |
|
3164 return ret_val; |
|
3165 |
|
3166 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
|
3167 BM_CS_STATUS_SPEED_MASK; |
|
3168 |
|
3169 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
|
3170 BM_CS_STATUS_SPEED_1000)) |
|
3171 return 0; |
|
3172 |
|
3173 msleep(200); |
|
3174 |
|
3175 /* flush the packets in the fifo buffer */ |
|
3176 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | |
|
3177 HV_MUX_DATA_CTRL_FORCE_SPEED); |
|
3178 if (ret_val) |
|
3179 return ret_val; |
|
3180 |
|
3181 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
|
3182 } |
|
3183 |
|
3184 /** |
|
3185 * e1000_check_polarity_82577 - Checks the polarity. |
|
3186 * @hw: pointer to the HW structure |
|
3187 * |
|
3188 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
|
3189 * |
|
3190 * Polarity is determined based on the PHY specific status register. |
|
3191 **/ |
|
3192 s32 e1000_check_polarity_82577(struct e1000_hw *hw) |
|
3193 { |
|
3194 struct e1000_phy_info *phy = &hw->phy; |
|
3195 s32 ret_val; |
|
3196 u16 data; |
|
3197 |
|
3198 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
|
3199 |
|
3200 if (!ret_val) |
|
3201 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) |
|
3202 ? e1000_rev_polarity_reversed |
|
3203 : e1000_rev_polarity_normal; |
|
3204 |
|
3205 return ret_val; |
|
3206 } |
|
3207 |
|
3208 /** |
|
3209 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY |
|
3210 * @hw: pointer to the HW structure |
|
3211 * |
|
3212 * Calls the PHY setup function to force speed and duplex. |
|
3213 **/ |
|
3214 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) |
|
3215 { |
|
3216 struct e1000_phy_info *phy = &hw->phy; |
|
3217 s32 ret_val; |
|
3218 u16 phy_data; |
|
3219 bool link; |
|
3220 |
|
3221 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
|
3222 if (ret_val) |
|
3223 return ret_val; |
|
3224 |
|
3225 e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
|
3226 |
|
3227 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
|
3228 if (ret_val) |
|
3229 return ret_val; |
|
3230 |
|
3231 udelay(1); |
|
3232 |
|
3233 if (phy->autoneg_wait_to_complete) { |
|
3234 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
|
3235 |
|
3236 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
3237 100000, &link); |
|
3238 if (ret_val) |
|
3239 return ret_val; |
|
3240 |
|
3241 if (!link) |
|
3242 e_dbg("Link taking longer than expected.\n"); |
|
3243 |
|
3244 /* Try once more */ |
|
3245 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
|
3246 100000, &link); |
|
3247 } |
|
3248 |
|
3249 return ret_val; |
|
3250 } |
|
3251 |
|
3252 /** |
|
3253 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information |
|
3254 * @hw: pointer to the HW structure |
|
3255 * |
|
3256 * Read PHY status to determine if link is up. If link is up, then |
|
3257 * set/determine 10base-T extended distance and polarity correction. Read |
|
3258 * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
|
3259 * determine on the cable length, local and remote receiver. |
|
3260 **/ |
|
3261 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) |
|
3262 { |
|
3263 struct e1000_phy_info *phy = &hw->phy; |
|
3264 s32 ret_val; |
|
3265 u16 data; |
|
3266 bool link; |
|
3267 |
|
3268 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
|
3269 if (ret_val) |
|
3270 return ret_val; |
|
3271 |
|
3272 if (!link) { |
|
3273 e_dbg("Phy info is only valid if link is up\n"); |
|
3274 return -E1000_ERR_CONFIG; |
|
3275 } |
|
3276 |
|
3277 phy->polarity_correction = true; |
|
3278 |
|
3279 ret_val = e1000_check_polarity_82577(hw); |
|
3280 if (ret_val) |
|
3281 return ret_val; |
|
3282 |
|
3283 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
|
3284 if (ret_val) |
|
3285 return ret_val; |
|
3286 |
|
3287 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
|
3288 |
|
3289 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == |
|
3290 I82577_PHY_STATUS2_SPEED_1000MBPS) { |
|
3291 ret_val = hw->phy.ops.get_cable_length(hw); |
|
3292 if (ret_val) |
|
3293 return ret_val; |
|
3294 |
|
3295 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); |
|
3296 if (ret_val) |
|
3297 return ret_val; |
|
3298 |
|
3299 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
|
3300 ? e1000_1000t_rx_status_ok |
|
3301 : e1000_1000t_rx_status_not_ok; |
|
3302 |
|
3303 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
|
3304 ? e1000_1000t_rx_status_ok |
|
3305 : e1000_1000t_rx_status_not_ok; |
|
3306 } else { |
|
3307 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
|
3308 phy->local_rx = e1000_1000t_rx_status_undefined; |
|
3309 phy->remote_rx = e1000_1000t_rx_status_undefined; |
|
3310 } |
|
3311 |
|
3312 return 0; |
|
3313 } |
|
3314 |
|
3315 /** |
|
3316 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY |
|
3317 * @hw: pointer to the HW structure |
|
3318 * |
|
3319 * Reads the diagnostic status register and verifies result is valid before |
|
3320 * placing it in the phy_cable_length field. |
|
3321 **/ |
|
3322 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) |
|
3323 { |
|
3324 struct e1000_phy_info *phy = &hw->phy; |
|
3325 s32 ret_val; |
|
3326 u16 phy_data, length; |
|
3327 |
|
3328 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
|
3329 if (ret_val) |
|
3330 return ret_val; |
|
3331 |
|
3332 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
|
3333 I82577_DSTATUS_CABLE_LENGTH_SHIFT; |
|
3334 |
|
3335 if (length == E1000_CABLE_LENGTH_UNDEFINED) |
|
3336 ret_val = -E1000_ERR_PHY; |
|
3337 |
|
3338 phy->cable_length = length; |
|
3339 |
|
3340 return 0; |
|
3341 } |